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-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi44
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 8a59465..3e4d383 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -97,4 +97,48 @@
0 189 0x4
0 190 0x4>;
};
+
+ mmcif: mmcif@0x10010000 {
+ compatible = "renesas,sh-mmcif";
+ reg = <0xe6bd0000 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 140 0x4
+ 0 141 0x4>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ sdhi0: sdhi@0xee100000 {
+ compatible = "renesas,r8a7740-sdhi";
+ reg = <0xee100000 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 83 4
+ 0 84 4
+ 0 85 4>;
+ cap-sd-highspeed;
+ status = "disabled";
+ };
+
+ /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
+ sdhi1: sdhi@0xee120000 {
+ compatible = "renesas,r8a7740-sdhi";
+ reg = <0xee120000 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 88 4
+ 0 89 4>;
+ toshiba,mmc-wrprotect-disable;
+ cap-sd-highspeed;
+ status = "disabled";
+ };
+
+ sdhi2: sdhi@0xee140000 {
+ compatible = "renesas,r8a7740-sdhi";
+ reg = <0xee140000 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 104 4
+ 0 105 4>;
+ toshiba,mmc-wrprotect-disable;
+ cap-sd-highspeed;
+ status = "disabled";
+ };
};