OMAP4470 LPDDR interface configuration update for 466MHz

Some instability with OMAP4470 when running the DDR at 466MHz is
discovered. This instability is resolved with updated LPDDR settings:

- DLL delay should be set to 461ps:
  DDR_PHY_CTRL_1_SHDW[11:4] = 0x37

- Read latency should be set to 0xB:
  DDR_PHY_CTRL_1_SHDW[3:0] = 0xB

- Slew Rate should be set to “FASTEST” and Impedance Control to “Drv12”:
  CONTROL_LPDDR2IOx_2[LPDDR2IO1_GR10_SR] = 0
  CONTROL_LPDDR2IOx_2[LPDDR2IO1_GR10_I] = 7
  where x=[1-2]

Change-Id: Ifa47a7ccae437225db5838039e528c04250a911d
Signed-off-by: Volodymyr Mieshkov <volodymyr.mieshkov@ti.com>

1 files changed, 38 insertions, 2 deletions

diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 065a94f..74c7255 100755
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -1126,6 +1126,37 @@ static u32 __init _usec_to_val_scrm(unsigned long rate, u32 usec,
 
 }
 
+/*
+ * According to the OMAP4470 LPDDR interface configuration
+ * update for 466MHz Slew Rate should be set to “FASTEST”
+ * and Impedance Control to “Drv12”:
+ * - CONTROL_LPDDR2IOx_2[LPDDR2IO1_GR10_SR] = 0
+ * - CONTROL_LPDDR2IOx_2[LPDDR2IO1_GR10_I] = 7
+ * where x=[1-2]
+ */
+static void __init syscontrol_lpddr2io_config_update_466_mhz(void)
+{
+	u32 v;
+
+	pr_info("OMAP4470 LPDDR interface configuration update for 466 MHz\n");
+
+	/* Setup LPDDR2IO1_2 */
+	v = omap4_ctrl_pad_readl(
+		OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2);
+	v &= ~OMAP4_LPDDR2IO1_GR10_SR_MASK;
+	v |= OMAP4_LPDDR2IO1_GR10_I_MASK;
+	omap4_ctrl_pad_writel(v,
+		OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2);
+
+	/* Setup LPDDR2IO2_2 */
+	v = omap4_ctrl_pad_readl(
+		OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2);
+	v &= ~OMAP4_LPDDR2IO2_GR10_SR_MASK;
+	v |= OMAP4_LPDDR2IO2_GR10_I_MASK;
+	omap4_ctrl_pad_writel(v,
+		OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2);
+}
+
 static void __init syscontrol_setup_regs(void)
 {
 	u32 v;
@@ -1134,14 +1165,19 @@ static void __init syscontrol_setup_regs(void)
 	v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3);
 	v &= ~(OMAP4_LPDDR21_VREF_EN_CA_MASK | OMAP4_LPDDR21_VREF_EN_DQ_MASK);
 	v |= OMAP4_LPDDR21_VREF_AUTO_EN_CA_MASK | OMAP4_LPDDR21_VREF_AUTO_EN_DQ_MASK;
-        omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3);
+	omap4_ctrl_pad_writel(v,
+		OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3);
 
 	v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3);
 	v &= ~(OMAP4_LPDDR21_VREF_EN_CA_MASK | OMAP4_LPDDR21_VREF_EN_DQ_MASK);
 	v |= OMAP4_LPDDR21_VREF_AUTO_EN_CA_MASK | OMAP4_LPDDR21_VREF_AUTO_EN_DQ_MASK;
-        omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3);
+	omap4_ctrl_pad_writel(v,
+		OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3);
 
 	syscontrol_lpddr_clk_io_errata(true);
+
+	if (cpu_is_omap447x())
+		syscontrol_lpddr2io_config_update_466_mhz();
 }
 
 static void __init prcm_setup_regs(void)