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| author | Nicole Chalhoub <n-chalhoub@ti.com> | 2012-05-25 14:51:48 +0300 |
|---|---|---|
| committer | Ziyann <jaraidaniel@gmail.com> | 2014-10-01 12:59:50 +0200 |
| commit | c075d46dd8d087746fcdd96a77c121396440000f (patch) | |
| tree | 785ba12205a9e2e27713aab74127ddc327724f88 /drivers/cpufreq/cpufreq_interactive.c | |
| parent | d00fbdf4dac93b7c5201c6d048a3adcd74149fec (diff) | |
| download | kernel_samsung_tuna-c075d46dd8d087746fcdd96a77c121396440000f.zip kernel_samsung_tuna-c075d46dd8d087746fcdd96a77c121396440000f.tar.gz kernel_samsung_tuna-c075d46dd8d087746fcdd96a77c121396440000f.tar.bz2 | |
OMAP4: DPLL cascading: Tune cpufreq interactive governor
During DPLL cascading timer_rate of interactive timer should be
increased, otherwise interactive governor will try to put system
out of DPLL cascading very frequently
[Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>:
Ported and adapted to p-android-omap-3.0]
Change-Id: I99bd86a8277b75f3f985124372f1c1b02f7d5ff2
Signed-off-by: Nicole Chalhoub <n-chalhoub@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
Conflicts:
drivers/cpufreq/cpufreq_interactive.c
Diffstat (limited to 'drivers/cpufreq/cpufreq_interactive.c')
| -rwxr-xr-x[-rw-r--r--] | drivers/cpufreq/cpufreq_interactive.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/cpufreq/cpufreq_interactive.c b/drivers/cpufreq/cpufreq_interactive.c index 7d1952c..15f6724 100644..100755 --- a/drivers/cpufreq/cpufreq_interactive.c +++ b/drivers/cpufreq/cpufreq_interactive.c @@ -87,6 +87,9 @@ static unsigned long min_sample_time = DEFAULT_MIN_SAMPLE_TIME; */ #define DEFAULT_TIMER_RATE (20 * USEC_PER_MSEC) static unsigned long timer_rate = DEFAULT_TIMER_RATE; +#ifdef CONFIG_OMAP4_DPLL_CASCADING +static unsigned long default_timer_rate; +#endif /* * Wait this long before raising speed above hispeed, by default a single @@ -122,6 +125,19 @@ struct cpufreq_governor cpufreq_gov_interactive = { .owner = THIS_MODULE, }; +#ifdef CONFIG_OMAP4_DPLL_CASCADING +void cpufreq_interactive_set_timer_rate(unsigned long val, unsigned int reset) +{ + if (!reset) { + default_timer_rate = timer_rate; + timer_rate = val; + } else { + if (timer_rate == val) + timer_rate = default_timer_rate; + } +} +#endif + static void cpufreq_interactive_timer_resched( struct cpufreq_interactive_cpuinfo *pcpu) { @@ -1014,6 +1030,10 @@ static int __init cpufreq_interactive_init(void) unsigned int i; struct cpufreq_interactive_cpuinfo *pcpu; struct sched_param param = { .sched_priority = MAX_RT_PRIO-1 }; + +#ifdef CONFIG_OMAP4_DPLL_CASCADING + default_timer_rate = DEFAULT_TIMER_RATE; +#endif /* Initalize per-cpu timers */ for_each_possible_cpu(i) { |