kernel_samsung_tuna.git - kernel/samsung/tuna

	Commit message (Collapse)	Author	Age	Files	Lines
*	tuna: very slightly relax ram timings	Boy Petersen	2015-08-21	1	-6/+6
\| \| \| \| \|	...to avoid errors. Got a report via PM that the sharper values may cause instabilities. I guess these settings are final now.
*	tuna: sharper ram timings according to specs	Boy Petersen	2015-08-21	1	-8/+8
\| \| \| \| \| \| \| \| \| \| \|	Samsung K3PE7E700M RAM chips are CL5. Set it accordingly. Also, set tRCD and tRP to what's still stable. Adjust tWR, tCAS and tRAS to reflect sane values. Lower does not necessarily mean better in these cases. Information sources: http://en.wikipedia.org/wiki/SDRAM_latency http://forums.legitreviews.com/about20065.html
*	optimized LPDDR RAM timings (~10% throughput increase)	Boy Petersen	2014-12-16	1	-9/+9
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Tweaked the device's RAM timings. Benchmarks suggest a 10 percent thorughput improvement (RgBandwidth RAM misc benchmark; threads: 1. 20 benchmark instances each, best result wins): Stock Tweaked Copy 1249.9 MB/s -> 1373.0 MB/s --> 9.86 % improvement Scale 1084.8 MB/s -> 1188.1 MB/s --> 9.52 % improvement Add 938.4 MB/s -> 1050.2 MB/s --> 11.91 % improvement Triad 923.0 MB/s -> 1043.5 MB/s --> 13.06 % improvement Change-Id: I082e7515d2995910b115c3fe0283fe25808d1cfb
*	ARM: omap4: tuna: emif: use device level self refresh timing	Nishanth Menon	2011-11-14	1	-3/+2
\| \| \| \| \| \| \| \| \| \| \| \|	Use a single self refresh time param for the entire device. Increase selfrefresh time to 262144 cycles from 2048. Change-Id: Iaac85c50a4fdacc228f955e650e096919c33fb27 Reported-by: Vinay Amancha <vinaykumar@ti.com> Reported-by: Vinay Chaurasia <vinaych@ti.com> Signed-off-by: Girish S G <girishsg@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
*	ARM: omap4: tuna: emif: increase memory self refresh idle time	Colin Cross	2011-10-15	1	-1/+1
\| \| \| \| \| \| \| \| \| \|	Increase the emif idle time before putting the memory into self refresh from 80 ns to 5.12 us (2048 ddr cycles @ 400 MHz) when the memory is at full speed. The lower idle time causes significant performance issues. Change-Id: Idb49b93c4b33d260b8a20e866b2eb33e75342232 Signed-off-by: Colin Cross <ccross@android.com>
*	ARM: omap4: tuna: emif: provide self-refresh timing	Gilles-Arnaud Bleu-Laine	2011-10-14	1	-2/+4
\| \| \| \| \| \| \| \|	Define timing for Tuna DDR to be in a safe value which is recommended to be 16 DDR clk cycles. Change-Id: Id840d67d497cc60c5984db18638dde1ad96b2543 Signed-off-by: Gilles-Arnaud Bleu-Laine <gilles@ti.com>
*	board-tuna: Add Samsung DDR organisation and timings.	Santosh Shilimkar	2011-06-30	1	-0/+107
	Tuna board memory configuartion is as below The memory organisation is as below : EMIF1 - CS0 - 4 Gb EMIF2 - CS0 - 4 Gb -------------------- TOTAL - 8 Gb Change-Id: I3517ab2f52ce0452bbb9fdd011ef6bb2bca56bbd Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>