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path: root/drivers/gpio/gpio-omap.c
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* GPIO: OMAP: Fix the sequence to clear the IRQ statusGirish S G2014-10-011-6/+8
| | | | | | | | | | | | | | | | The recommended way to clear the GPIO IRQ status is to: - Enable the IRQ - clear the status If this above sequence is not followed, i.e., if the status is cleared after disabling the IRQ then sWAKEUP will not be cleared and gates the module transition. Change-Id: I8bd1b820ac8be70530cd6430f26ce541bfd3f9d9 Signed-off-by: Huzefa Kankroliwala <huzefank@ti.com> Signed-off-by: Girish S G <girishsg@ti.com> Signed-off-by: Andrii Anisov <andrii.anisov@ti.com>
* gpio/omap: fix _set_gpio_irqenable implementationTarun Kanti DebBarma2014-10-011-1/+4
| | | | | | | | | | | | | | | This function should be capable of both enabling and disabling interrupts based upon the *enable* parameter. Right now the function only enables the interrupt and *enable* is not used at all. So add the interrupt disable capability also using the parameter. Change-Id: I9b902184cabe8990205c9d488d261d79a84b94d4 Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
* GPIO: OMAP2+: On suspend don't wakeup on non-wakeupable interrupts.Ambresh K2014-10-011-4/+6
| | | | | | | | | | | | | | | | | | | | | While in suspend, device should only be woken-up from those gpio pins, who has explicitly marked itself has wakeup capable through enable_irq_wake() functions from respective drivers. In current implementation, it address the issue where interrupts were lost when system had entered deeper c-state. So in CpuIdle path all the pins with interrupts enabled where marked has wakeup capable to get the system out of deeper c-states. With this approach, it is observed that lots of spurious interrupts are waking system from suspend, even though they not suppose wake the device. So based on, whether prepare idle is called from CpuIdle or suspend mark gpio wakeup capable. Change-Id: Ib3f9be6e56c0656f4b8736861740ed0b4394384f Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Hema Kalliguddi <hemahk@ti.com>
* ARM: OMAP4: Add put/get sync clocks in setwakeenableDan Murphy2014-10-011-0/+12
| | | | | | | | | Need to add the clock calls to the setwakeupenable GPIO functions as on 4430 when going to idle the IRQ enable register is trying to be accessed with clocks off causing a kernel panic. Change-Id: Ia01ea21ff8674a4f48263addfc3bcc7b8475f17c Signed-off-by: Dan Murphy <dmurphy@ti.com>
* ARM: omap4: gpio: Use pad wakeupevent to detect pulses for edge triggered gpiosArve Hjønnevåg2011-12-141-0/+7
| | | | | | | | | | | | | | | | | | | | | When the gpio controller is off we use the pad wakeup to wake up. The current code only detects edges if the state of the gpio when we wake up is different from the state we read before we turned the gpio controller off. This will miss short pulses. We now use the pad wakeupevent status to try to detect these pulses. If the interrupt is configured for dual edge triggering this will generate an interrupt for any pulse detected. If the interrupt is configured for single edge detect we only generate an interrupt if the old state matches the starting state for the enabled edge detect. This will still miss a pulse when the interrupt is configured for only the second edge in that pulse. We may also falsely generate an interrupt if an edge of the wrong polarity occured before reading the initial state (since the pad wakeup is enabled before then). Change-Id: Id9a68cd97b0281a7debb2f37d845979894b63bcc Signed-off-by: Arve Hjønnevåg <arve@android.com>
* ARM: omap4: gpio: Fix omap2_gpio_set_wakeupenables to have an effectArve Hjønnevåg2011-12-141-0/+22
| | | | | | | | | | | The wakeupenable bits set by this function do not take effect unless omap4_trigger_ioctrl is called. This function cannot be safely called after any gpio bank is disabled however, so enable the pad wakeup for all the gpio banks, call omap4_trigger_ioctrl, then disable the gpio banks. Change-Id: I4dd5aac70ebfebe9187fc4058d6470e03f89035b Signed-off-by: Arve Hjønnevåg <arve@android.com>
* ARM: omap4: gpio: Fix wakeup for masked level triggered interruptsArve Hjønnevåg2011-12-061-2/+2
| | | | | | | | When converting level triggered interrupts to edge triggered for low power modes, only unmasked interrupts were set up. Change-Id: Ib8acfa47e9dfe992422a40bab423f0de64293476 Signed-off-by: Arve Hjønnevåg <arve@android.com>
* ARM: omap4: gpio: Fix lost gpio edge interrutps in low power idle modes.Arve Hjønnevåg2011-12-051-2/+2
| | | | | | | | | | Use the same omap2_gpio_prepare_for_idle sequence for idle as for suspend. The existing suspend sequence will check if the gpio state has changed while in the low power mode and force an interrupt to be generated if needed. Change-Id: I274f38ebcaa811d6d43550912b7de82ffdb120e9 Signed-off-by: Arve Hjønnevåg <arve@android.com>
* ARM: omap: gpio: fix external abort when trying to read unclocked registerMike J. Chen2011-11-301-2/+8
| | | | | | | | omap2_gpio_prepare_for_idle() was calling omap2_gpio_set_wakeupenables() on banks that weren't in use and cause external aborts. Change-Id: Ifbb01f9d7d635a81cdd6798a582d22690d3a97cb Signed-off-by: Mike J. Chen <mjchen@google.com>
* ARM: omap4: gpio: abort suspend if a level wake interrupt is pendingColin Cross2011-11-141-5/+39
| | | | | | | | | | | If a level wake interrupt arrives after disable_irq has been called but before suspend, the interrupt will be masked. The omap gpio driver erases all triggering information when masking an interrupt. Track the triggering state of gpio interrupts, and abort suspend if a masked wakeup interrupt is active when suspending. Change-Id: I117b592d21c455074796deaea8148edf0947eb35 Signed-off-by: Colin Cross <ccross@android.com>
* gpio: omap: fix gpio transitions to off modeColin Cross2011-11-141-26/+27
| | | | | | | | | | | | | | When transitioning to off mode, it is possible that the powerdomain that contains the gpio block does not transition due to another clock domain being on. In this case, we must do the same configuration on the gpios as in the non-off mode case. Modify omap2_gpio_set_edge_wakeup to use different variables to save context vs. omap_save_context, and both set the edge wakeups and call pm_runtime_put_sync when going to off mode. Change-Id: I2890f7f3dd2c3dfe493cf748a523004a76e560c2 Signed-off-by: Colin Cross <ccross@android.com>
* ARM: omap: gpio: set wakeupenable bits when entering idle modesColin Cross2011-11-031-0/+47
| | | | | | | | | | | | | | | THe pad wakeupenable bits are required to wake through a gpio when in OFF or OSWR. If the wakeupenable bits are set when the controller is not in idle, a PRCM and a GPIO interrupt will occur for every interrupt. Set the wakeupenable bits for every active gpio interrupt when entering any gpio idle mode. Also sets the irq chip flag IRQCHIP_MASK_ON_SUSPEND to cause the irq pm code to mask all non-wake gpios in suspend, which will ensure the wakeupenable bit is not set on non-wake gpios. Change-Id: I03b8d954a65f8cc47388319e983decf03308448f Signed-off-by: Colin Cross <ccross@android.com>
* gpio: omap: clear level bits when switching to edge detect in idleColin Cross2011-11-031-13/+42
| | | | | | | | | | | | | | | | | | The gpio controller in omap4 can only wake from idle on edge triggered lines. The level triggered interrupts are converted to edge triggered in idle. It appears that the edge triggered enable bits are ignored if the level triggered bit is also set, so clear the level trigger bit in idle and restore it later. If a level triggered interrupt is pending when the level detect register is cleared the edge detect setting will not detect it, and the interrupt will be lost. After clearing the level detect bits, manually check the datain register against the saved level detect values, and abort the transition if the interrupt is pending. Change-Id: I43fbee728cb6ebc407b8c4430a1cd37165354dc6 Signed-off-by: Colin Cross <ccross@android.com>
* ARM: omap2+: gpio: simplify updating gpios in off vs. retentionColin Cross2011-11-031-61/+53
| | | | | | | | | | | | | | Call the same function to set up the gpio controllers for off mode and retention, and get rid of the external apis to set edge wakeups. Calling both omap2_gpio_prepare_for_idle and omap2_gpio_set_edge_wakeup, as was done when entering off mode, was never safe because both functions save their context in the same location. Change-Id: I159bdc1863aec9827d7fb1ec0525afd632be6fa6 Signed-off-by: Colin Cross <ccross@android.com>
* omap: gpio: put_sync_suspend instead of put_sync in freeMiguel Vadillo2011-10-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | put_sync might sleep and omap_gpio_free is calling it between spinlocks thus changing it to put_sync_suspend to avoid the following warning: [ 104.568847] BUG: sleeping function called from invalid context at drivers/base/power/runtime.c:735 [ 104.578460] in_atomic(): 1, irqs_disabled(): 128, pid: 297, name: kworker/0:3 [ 104.586090] Backtrace: [ 104.588775] [<c00531c4>] (dump_backtrace+0x0/0x110) from [<c0574ae8>] (dump_stack+0x18/0x1c) [ 104.597747] r6:60000013 r5:ffff9e48 r4:00000000 r3:60000093 [ 104.603759] [<c0574ad0>] (dump_stack+0x0/0x1c) from [<c008337c>] (__might_sleep+0x130/0x134) [ 104.612701] [<c008324c>] (__might_sleep+0x0/0x134) from [<c02cf1b0>] (__pm_runtime_idle+0x94/0x98) [ 104.622192] r5:00000004 r4:c787ac08 [ 104.626007] [<c02cf11c>] (__pm_runtime_idle+0x0/0x98) from [<c0236cc8>] (omap_gpio_free+0xa0/0xb0) [ 104.635467] r7:00000013 r6:60000013 r5:c7877268 r4:c7877200 [ 104.641510] [<c0236c28>] (omap_gpio_free+0x0/0xb0) from [<c0235438>] (gpio_free+0xa4/0x108) [ 104.650329] r7:000000f9 r6:c787727c r5:c07acfe0 r4:00000053 [ 104.656372] [<c0235394>] (gpio_free+0x0/0x108) from [<c0277e3c>] (_resource_free+0x170/0x274) [ 104.665405] [<c0277ccc>] (_resource_free+0x0/0x274) from [<c0278ddc>] (rprm_cb+0x56c/0x604) [ 104.674255] r7:00000066 r6:c7a1ac08 r5:c7a14cd0 r4:00200200 [ 104.680267] [<c0278870>] (rprm_cb+0x0/0x604) from [<c0275910>] (rpmsg_recv_done+0xbc/0x17c) [ 104.689117] [<c0275854>] (rpmsg_recv_done+0x0/0x17c) from [<c0274b54>] (vring_interrupt+0x44/0x54) [ 104.698608] r8:00000004 r7:00000000 r6:00000002 r5:00000002 r4:c074f918 [ 104.705718] [<c0274b10>] (vring_interrupt+0x0/0x54) from [<c007b1cc>] (omap_rpmsg_mbox_callback+0x6c/0) [ 104.715972] [<c007b160>] (omap_rpmsg_mbox_callback+0x0/0xb8) from [<c00b8088>] (notifier_call_chain+0x) [ 104.726562] r5:00000000 r4:fffffffe [ 104.730346] [<c00b803c>] (notifier_call_chain+0x0/0x8c) from [<c00b8480>] (__blocking_notifier_call_ch) [ 104.741485] r8:c0749a88 r7:00000004 r6:00000002 r5:00000000 r4:c0749a68 [ 104.748413] r3:ffffffff [ 104.751220] [<c00b842c>] (__blocking_notifier_call_chain+0x0/0x6c) from [<c00b84b8>] (blocking_notifie) [ 104.763183] r8:00000004 r7:00000000 r6:c63ab434 r5:c6fcbefc r4:c63ab420 [ 104.770294] [<c00b8498>] (blocking_notifier_call_chain+0x0/0x28) from [<c007fe54>] (mbox_rx_work+0x84/) [ 104.780639] [<c007fdd0>] (mbox_rx_work+0x0/0xe8) from [<c00aaf40>] (process_one_work+0x114/0x410) [ 104.790008] r8:c007fdd0 r7:00000000 r6:c1837500 r5:c18335c0 r4:c6f3b580 [ 104.797149] [<c00aae2c>] (process_one_work+0x0/0x410) from [<c00ab5e4>] (worker_thread+0x1a8/0x490) [ 104.806732] [<c00ab43c>] (worker_thread+0x0/0x490) from [<c00b2208>] (kthread+0x94/0x98) [ 104.815307] [<c00b2174>] (kthread+0x0/0x98) from [<c009860c>] (do_exit+0x0/0x720) [ 104.823211] r7:00000013 r6:c009860c r5:c00b2174 r4:c7909e94 Change-Id: I051f13d82d6b776641ebd65ff16f9ce0f02fdf57 Signed-off-by: Miguel Vadillo <vadillo@ti.com>
* GPIO: OMAP: Remove IS_ERR_VALUE callsTodd Poynor2011-10-141-10/+10
| | | | | Change-Id: If12733e5bb468e6ba67bd2618f3c0ca8afd7d766 Signed-off-by: Todd Poynor <toddpoynor@google.com>
* OMAP4: Enable/Disable GPIO clocks before/after Regiter access.Rajeev Kulkarni2011-10-141-4/+27
| | | | | | | | | | On 4430 system was crashing in idle path while accessing GPIO regiters w/o its clocks enabled. In Many platforms some banks may not be used at all. Before acessing any GPIO bank register ensure that the clocks are active. Once accessing is done disable the clocks. Signed-off-by: Axel Haslem <axelhaslam@ti.com> Signed-off-by: Rajeev Kulkarni <rajeevk@ti.com>
* gpio: omap: leave edge detect bits alone in idleColin Cross2011-10-111-2/+2
| | | | | | | | | The edge detect bits should be left set if they were set entering idle, even if wkup_status was cleared for any reason. Apply wkup_status to the level detect bits only. Change-Id: I11b0ae629004a42a7fd8d7d5b2a32208586d7697 Signed-off-by: Colin Cross <ccross@android.com>
* GPIO: OMAP: set edge trigger for wakeup gpioAxel Haslam2011-10-061-0/+47
| | | | | | | | | | Only edge trigger is supported for wakeup. if a gpio is set as wakeup, and level trigger, make sure we set the edge trigger so that we can wake up. Change-Id: Ibb61042be6ce053729ff20f3cb8d53899afe42b1 Signed-off-by: Axel Haslam <axelhaslam@ti.com>
* GPIO: OMAP: Fix GPIO_IRQWAKEN_0 accessAxel Haslam2011-10-061-9/+26
| | | | | | | | | | | The use of the new GPIO_IRQWAKEN_0 register cannot use the same logic as the GPIO_CLEARWKUPENA and GPIO_SETWKUENA. To set GPIO_IRQWAKEN_0 we need to read the register and OR the corresponding bit. to clear the wakeup we need clear the bit NOT set it. Change-Id: Iabbe553e3db283804f5b89dfba3f5fa35b88d9dc Signed-off-by: Axel Haslam <axelhaslam@ti.com>
* OMAP: PM: replace omap_pm_get_dev_context_loss_count with ↵Axel Haslam2011-09-061-13/+3
| | | | | | | | | | | | | | | | | | | | | | omap_pm_was_context_lost Drivers just need to know if thier context was lost or not. There is not much point in maintaining a count This removes omap_pm_get_dev_context_loss_count and replaces it with omap_pm_was_context_lost Adapt drivers to use the omap_pm_was_context_lost API, which returns a bool value instead of relying on the incrementing context lost counter. This makes drivers a little more snappier as they do not need to restore contexts when not needed. WARNING: this changes the api set available to drivers to use from OMAP PM layer. Change-Id: I7fd9183d3e12982bb40651df9378637073121399 Signed-off-by: Axel Haslam <axelhaslam@ti.com>
* GPIO: OMAP: use put_sync_suspend instead of put_syncNishanth Menon2011-08-291-1/+1
| | | | | | | | | save is usually called by arch's suspend path where interrupts are disabled. we should use put_sync_suspend instead of put_sync to prevent sleepable calls to callbacks. Change-Id: I1194b23753d1ad94ffaa23bc9f36ead418d13974 Signed-off-by: Nishanth Menon <nm@ti.com>
* GPIO: OMAP: setup irq enable only after configuring interrupt in restoreNishanth Menon2011-08-291-4/+4
| | | | | | | | | Setup the interrupt enable registers only after we have configured the required edge and required configurations, not before, to prevent spurious events as part of restore routine. Change-Id: I3936d3b8f9b5c12052e2e388d79558b2e134fb35 Signed-off-by: Nishanth Menon <nm@ti.com>
* GPIO: OMAP: restore OE only after setting the output levelNishanth Menon2011-08-291-1/+1
| | | | | | | | Setup the dataout register before setting the GPIO to output mode in restore path. Change-Id: I0d3ecd9eda97a466e73e1cd2e16b7b54be3c2139 Signed-off-by: Nishanth Menon <nm@ti.com>
* GPIO: OMAP: handle set_dataout reg capable IP on restoreNishanth Menon2011-08-291-1/+6
| | | | | | | | | | GPIO IP revisions such as those used in OMAP4 have a set_dataout while the previous revisions used a single dataout register. Depending on what is available restore the dataout settings to the right register. Change-Id: I07c8c0d90f4fe115533711bd587ae0d92f9e0232 Signed-off-by: Nishanth Menon <nm@ti.com>
* GPIO: OMAP: save and restore wakeup_set register not statusNishanth Menon2011-08-291-2/+2
| | | | | | | | Status register has no meaning for save and restore. We need to save and restore the wakeup_set register instead. Change-Id: I50fa813aa77391622845dcc012cf1ee74377dd67 Signed-off-by: Nishanth Menon <nm@ti.com>
* GPIO: OMAP: save and restore debounce as wellNishanth Menon2011-08-291-3/+17
| | | | | | | | | | GPIO debounce needs to be saved and restored as well for proper restoration for driver expectation. To save the registers, we cannot cut the clock before the save, hence move the clk disable after the save. Change-Id: I902ca8a4ab9750c49413f20a5782eb31f9241f1c Signed-off-by: Nishanth Menon <nm@ti.com>
* GPIO: OMAP: mark complete once restoredNishanth Menon2011-08-291-0/+1
| | | | | | | Mark the GPIO bank as restored once restoration is complete. Change-Id: Id4dd1380fade04870beac1b5115f9d15325fbd49 Signed-off-by: Nishanth Menon <nm@ti.com>
* GPIO: OMAP: use put_sync_suspend instead of put_sync in irq handler.Colin Cross2011-07-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | GPIO uses put_sync in irq handler at the moment, this causes the following warning with a check patch such as https://patchwork.kernel.org/patch/1001572/: [ 4.036560] BUG: sleeping function called from invalid context at drivers/base/power/runtime.c:735 [ 4.046508] in_atomic(): 1, irqs_disabled(): 128, pid: 1, name: swapper [ 4.053863] Backtrace: [ 4.056762] [<c00508d0>] (dump_backtrace+0x0/0x10c) from [<c0533870>] (dump_stack+0x18/0x1c) [ 4.066131] r7:00000000 r6:ffff6c05 r5:c06ce080 r4:de43a000 [ 4.072784] [<c0533858>] (dump_stack+0x0/0x1c) from [<c0079744>] (__might_sleep+0x108/0x128) [ 4.082183] [<c007963c>] (__might_sleep+0x0/0x128) from [<c027b824>] (__pm_runtime_idle+0x90/0x98) [ 4.092132] r6:c06d0720 r5:00000004 r4:de486808 [ 4.097534] [<c027b794>] (__pm_runtime_idle+0x0/0x98) from [<c0204ce0>] (gpio_irq_handler+0x1e8/0x270) [ 4.107849] r7:00000000 r6:c06d0720 r5:c06e7220 r4:de474000 [ 4.114501] [<c0204af8>] (gpio_irq_handler+0x0/0x270) from [<c00cc570>] (generic_handle_irq+0x3c/0x48) [ 4.124847] [<c00cc534>] (generic_handle_irq+0x0/0x48) from [<c0046054>] (asm_do_IRQ+0x54/0xb4) [ 4.134521] [<c0046000>] (asm_do_IRQ+0x0/0xb4) from [<c004c448>] (__irq_svc+0x48/0xe0) Instead, use put_sync_suspend and since the gpio devices are already marked as used in irq enabled case, the change removes a potential invalid condition. Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Colin Cross <ccross@google.com>
* GPIO: OMAP2+: allow level/edge triggeringGirish S Ghongdemath2011-07-141-1/+2
| | | | | | | | The code does a wrong check and does not allow OMAP2+ to set level type. Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Girish S G <girishsg@ti.com>
* GPIO: OMAP: restore context only if previously savedAxel Haslam2011-07-141-2/+5
| | | | | | | | | | On probe a call to runtime get sync will eventualy result in a context restore. We do not want to restore any context, if it was never saved on the first place. Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Axel Haslam <axelhaslam@ti.com>
* GPIO: OMAP2+: Clean prepare_for_idle and resume_after_idleTarun Kanti DebBarma2011-07-141-147/+160
| | | | | | | | | | Simplify omap2_gpio_prepare_for_idle() and omap2_gpio_resume_after_idle() by moving most of the stuff to *_pm_runtime_suspend() and *_pm_runtime_resume(). Also, omap_gpio_suspend() and omap_gpio_resume() optimized to operate per GPIO bank instead of operating on entire list every time. Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com> Signed-off-by: Charulatha V <charu@ti.com>
* GPIO: OMAP: Use PM runtime frameworkCharulatha V2011-07-141-20/+80
| | | | | | | | | | | Call runtime pm APIs pm_runtime_get_sync() and pm_runtime_put_sync() for enabling/disabling clocks appropriately. Remove syscore_ops and instead use dev_pm_ops now. [girishsg@ti.com: Fixed review comments] Signed-off-by: Girish S G <girishsg@ti.com> Signed-off-by: Charulatha V <charu@ti.com> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
* GPIO: OMAP: Remove bank->method & METHOD_* macrosCharulatha V2011-07-141-12/+6
| | | | | | | | The only bank->type (method) used in the OMAP GPIO driver is MPUIO type as they need to be handled separately. Identify the same using a flag and remove all METHOD_* macros. Signed-off-by: Charulatha V <charu@ti.com>
* GPIO: OMAP: Fix use of readl/readw to access isr_regCharulatha V2011-07-141-3/+5
| | | | | | | | In gpio_irq_handler, isr register is always accessed as 32 bit register and only for OMAP15xx the first 16 MSBs are masked. Correct this by using the appropriate readl/readw registers as per the bank width. Signed-off-by: Charulatha V <charu@ti.com>
* GPIO: OMAP15xx: Use pinctrl offset instead of macroCharulatha V2011-07-141-5/+3
| | | | | | Use regs->pinctrl field instead of using the macro OMAP1510_GPIO_PIN_CONTROL Signed-off-by: Charulatha V <charu@ti.com>
* GPIO: OMAP: Clean omap_gpio_mod_init functionCharulatha V2011-07-141-40/+81
| | | | | | | | | With register offsets now defined for respective OMAP versions we can get rid of cpu_class_* checks. In addition, organized common initialization for the different OMAP silicon versions. Signed-off-by: Charulatha V <charu@ti.com> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
* GPIO: OMAP: Clean set_gpio_triggering functionTarun Kanti DebBarma2011-07-141-91/+33
| | | | | | | | Getting rid of ifdefs within the function by adding register offset intctrl and associating OMAPXXXX_GPIO_INT_CONTROL in respective SoC specific files. Signed-off-by: Charulatha V <charu@ti.com> Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
* GPIO: OMAP: Remove hardcoded offsets in ctxt save/restoreTarun Kanti DebBarma2011-07-141-22/+20
| | | | | | | | | It is not required to use hard-coded offsets any more in context save and restore functions and instead use the generic offsets which have been correctly initialized during device registration. Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com> Signed-off-by: Charulatha V <charu@ti.com>
* GPIO: OMAP: Use level/edge detect reg offsetsTarun Kanti DebBarma2011-07-141-82/+36
| | | | | | | | | By adding level and edge detection register offsets and then initializing them correctly according to OMAP versions during device registrations we can now remove lot of revision checks in these functions. Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com> Signed-off-by: Charulatha V <charu@ti.com>
* GPIO: OMAP: Use wkup regs off/suspend support flagTarun Kanti DebBarma2011-07-141-102/+22
| | | | | | | | | | | | | | | | | Wakeup register offsets are initialized according to OMAP versions during device registration. These explicit checks are no longer needed. mpuio_init() function is defined under #ifdefs. It is required only in case of MPUIO bank type and only when PM operations are supported by it. This is applicable only in case of OMAP16xx SoC's MPUIO GPIO bank type. For all the other cases it is a dummy function. Hence clean up the same and remove all the OMAP SoC specific #ifdefs. bank_is_mpuio() is defined as a check to identify if the bank type is MPUIO. It is not required to define it separately as zero for OMAP2plus. Remove this. Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com> Signed-off-by: Charulatha V <charu@ti.com>
* GPIO: OMAP: Avoid cpu checks during module ena/disableCharulatha V2011-07-141-30/+23
| | | | | | | Remove cpu-is checks while enabling/disabling OMAP GPIO module during a gpio request/free. Signed-off-by: Charulatha V <charu@ti.com>
* GPIO: OMAP2+: Make non-wakeup GPIO part of pdataCharulatha V2011-07-141-7/+1
| | | | | | | Non-wakeup GPIOs are available only in OMAP2. Avoid cpu_is checks by making non_wakeup_gpios as part of pdata. Signed-off-by: Charulatha V <charu@ti.com>
* GPIO: OMAP: Handle save/restore ctx in GPIO driverCharulatha V2011-07-141-73/+56
| | | | | | | | | | | Modify omap_gpio_prepare_for_idle() & omap_gpio_resume_after_idle() functions to handle save context & restore context respectively in the OMAP GPIO driver itself instead of calling these functions from pm specific files. For this, in gpio_prepare_for_idle(), call *_get_context_loss_count() and in gpio_resume_after_idle() call it again. If the count is different, do restore context. The workaround_enabled flag is no more required and is removed. Signed-off-by: Charulatha V <charu@ti.com>
* GPIO: OMAP: Make gpio_context part of gpio_bank structureCharulatha V2011-07-141-42/+34
| | | | | | | | Currently gpio_context array used to save gpio bank's context, is used only for OMAP3 architecture. Move gpio_context as part of gpio_bank structure so that it can be specific to each gpio bank and can be used for any OMAP architecture Signed-off-by: Charulatha V <charu@ti.com>
* GPIO: OMAP2+: Use flag to identify wakeup domainCharulatha V2011-07-141-7/+6
| | | | | | | | | | | | | | In omap3, save/restore context is implemented for GPIO banks 2-6 as GPIO bank1 is in wakeup domain. Instead of identifying bank's power domain by bank id, use 'loses_context' flag which is filled by pwrdm_can_ever_lose_context() during dev_init. For getting the powerdomain pointer, omap_hwmod_get_pwrdm() is used. omap_device_get_pwrdm() could not be used as the pwrdm information needs to be filled in pdata, whereas omap_device_get_pwrdm() could be used only after omap_device_build() call. Signed-off-by: Charulatha V <charu@ti.com>
* GPIO: OMAP: Remove dependency on gpio_bank_countTarun Kanti DebBarma2011-07-141-93/+80
| | | | | | | | The gpio_bank_count is the count of number of GPIO devices in a SoC. Remove this dependency from the driver by using list. Also remove the dependency on array of pointers to gpio_bank struct of all GPIO devices. Signed-off-by: Charulatha V <charu@ti.com>
* GPIO: OMAP: cleanup show revision, remove cpu_is checks, display only onceKevin Hilman2011-07-141-8/+6
| | | | | | | | | | | | | | | | Remove cpu_is_* checks from gpio_show_revision() by passing in the revision address offset from platform data. SoCs with no revision register (15xx, 7xx, and all MPUIOs) use -1 (actually, USHRT_MAX) to signify no register. While here, all GPIO banks are assumed to be the same revision, so fix show_revision() to only show the revision for the first bank it finds. This removes duplicate GPIO revision prints during boot. Thanks to Charulatha V <charu@ti.com> for finding/fixing a few -1s that were missed in the original patch. Signed-off-by: Kevin Hilman <khilman@ti.com>
* GPIO: OMAP: debounce remove SoC specific registers, use pdataKevin Hilman2011-07-141-12/+3
| | | | | | Use register offsets passed in from pdata for accessing debounce registers. Signed-off-by: Kevin Hilman <khilman@ti.com>
* GPIO: OMAP: cleanup _set_gpio_wakeup(), remove ifdefsTarun Kanti DebBarma2011-07-141-34/+16
| | | | | | | | | | | | Make _set_gpio_wakeup() generic by removing ifdefs. Code for the various SoCs/bank-methods was already the same, except for the non-wakeup GPIO checking. But that flag is set on a per-SoC basis, so can be used for all SoCs. While here, use dev_err() and remove GPIO bank calculation assumption based on subtracting bank pointers. Signed-off-by: Kevin Hilman <khilman@ti.com>
generated by cgit v1.1 at 2025-01-08 01:56:51 +0000