| Commit message (Collapse) | Author | Age | Files | Lines |
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Conflicts:
arch/arm/include/asm/hardware/cache-l2x0.h
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commit c39e8e4354ce4daf23336de5daa28a3b01f00aa6 upstream.
The TX_FIFO register is 10 bits wide. The lower 8 bits are the data to be
written, while the upper two bits are flags to indicate stop/start.
The driver apparently attempted to optimize write access, by only writing a
byte in those cases where the stop/start bits are zero. However, we have
seen cases where the lower byte is duplicated onto the upper byte by the
hardware, which causes inadvertent stop/starts.
This patch changes the write access to the transmit FIFO to always be 16 bits
wide.
Signed off by: Steven A. Falco <sfalco@harris.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Once i2c driver shutdown has been called, ignore any more
transfer requests. This patch adds the missing callback.
Leave the PMIC i2c (i2c-1) alive, since power_off case needs it
well after shutdown handlers have been called for power_off case.
Change-Id: I4f4553327e5c024f78acb8501864dd9beb1883c3
Signed-off-by: Semen Protsenko <semen.protsenko@ti.com>
Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
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The I2C clocks change from 96MHz to 48MHz in dpll cascading
mode.The I2C driver is registerd with DPLL cascading and
the change in clocks is handled.The device speed of > 1Mbps
is not supported in DPLL cascading mode.
[Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>:
Ported and adapted to p-android-omap-3.0]
Change-Id: Ib37648012476a8246cc9e437f707b6e3969e13a3
Signed-off-by: Madhusudhan Chikkature <madhu.cr@ti.com>
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
Conflicts:
drivers/i2c/busses/i2c-omap.c
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becomes valid
Bus busy status bit is not effective when functional part of the I2C controller
is not valid, and bus busy detection in omap_i2c_wait_for_bb() will be skipped
sometimes. So we should wait till functional part of the I2C controller
completely becomes valid, after setting the I2Ci.I2C_CON[15] I2C_EN bit to 1.
For doing that we have to wait till RDONE bit of SYSS register reach "1".
For details see TRM, 23.1.4.3 HS I2C Software Reset.
Change-Id: I989855d6cb2b1aa0098e11245dacb77583fe6647
Signed-off-by: Semen Protsenko <semen.protsenko@ti.com>
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Interrupts that occur during omap_i2c_bus_clear() can cause to
erroneous behaviour in interrupt handler, i.e. multiple printing of
"RRDY IRQ while no data requested" message. So disable interrupts
in omap_i2c_bus_clear() function since they can't be handled correctly.
Change-Id: If4525c93284766d0a2705d7ca4d1f962e3cc4b15
Signed-off-by: Semen Protsenko <semen.protsenko@ti.com>
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Enable the interrupts only when I2C hw spinlock is acquired
Change-Id: I610236a1c1150f5746546c7bd3a0fad6eff2e706
Signed-off-by: Huzefa Kankroliwala <huzefank@ti.com>
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In case a peripheral is driving SDA bus low (ie. a start condition), provide
a constant clock output using the test mode of the OMAP I2C controller to
try and clear the bus. Soft reset I2C controller after attempting the bus clear
to ensure that controller is in a good state.
Based upon Vikram Pandita's patch from TI Android 3.0 kernel and modified for
mainline by Jon Hunter. A couple differences from the original patch ...
1. Add a new function for bus clear
2. Ensure that the CON.I2C_EN bit is set when using the SYSTEST feature to
output a permanent clock. This bit needs to be set and tpyically it would
be set by the unidle function but this is not the case for all OMAP
generations.
3. Program the SYSTEST setting only the bits we care about. However, restore
SYSTEST registers to there original state as some OMAP generations do not
implement perform a soft-reset.
4. Clear the CON register after performing the bus clear, so when we call the
init function the controller is disabled and the init function will
re-enable later.
Original patch can be found here:
http://git.omapzoom.org/?p=kernel/omap.git;a=commit;h=a2ab04192ba25e60f95ba1ff3af5601a2d7b5bd1
Change-Id: I299357568aeafa4bff4caa5dedb294adbd80df36
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
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By definition, wait_for_completion_timeout() returns an unsigned value and
therefore, it is not necessary to check if the return value is less than zero
as this is not possible.
Move the call to wait_for_completion_timeout() onto a single line as it is less
than 80 characters.
Change-Id: I906a112c1ef339aa0b7ad26896669fa413448fa8
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
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- The reset in the driver at init is not needed anymore as the
hwmod framework takes care of reseting it.
- Reset is removed from omap_i2c_init, which was called
not only during probe, but also after time out and error handling.
device_reset were added in those places to effect the reset.
- Earlier the hwmod SYSC settings were over-written in the driver.
Removing the same and letting the hwmod take care of the settings.
- Clean up the SYSS_RESETDONE_MASK macro as it is no longer needed.
- Clean up the SYSCONFIG SYSC bit defination macros.
- Fix the typos in wakeup.
Change-Id: I8f4ccdf783de6fe3d883e4aa5290473ea0117945
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Conflicts:
drivers/i2c/busses/i2c-omap.c
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Adding support for hwspinlock in I2C driver
in Blaze and Blaze_Tablet2.
Also adding an api omap_i2c_get_hwspinlockid to be
used by remote proc to populate the resource table.
Change-Id: I5f554ead10806c90442359365dcb8ebff51bf2bf
Signed-off-by: Christina Warren <cawarren@ti.com>
Conflicts:
arch/arm/mach-omap2/board-4430sdp.c
arch/arm/mach-omap2/board-44xx-tablet.c
arch/arm/plat-omap/include/plat/i2c.h
drivers/i2c/busses/i2c-omap.c
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The SYSC register should not accessed in the driver removing the
define from the driver.
Also clean up the syscstate from the omap_i2c_dev struct.
Change-Id: I95a7668de47a26523b51a9d13aea83b7aa7def03
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
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Fix an issue in the omap i2c host controller driver where it was not properly
clearing out an error condition in the unit after a NAK'ed transaction causing
the subsequent transaction to time out.
Change-Id: I5cdc8e740acdbc8116dca4d13f1a2cee37f75582
Signed-off-by: Mike J. Chen <mjchen@google.com>
Signed-off-by: Ruslan Bilovol <ruslan.bilovol@ti.com>
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On OMAP4 OMAP_I2C_STAT_NACK is causing a timeout on the next access.
The isr cleans all flags in OMAP_I2C_CON_REG by setting OMAP_I2C_CON_STP
OMAP_I2C_CON_STP is also set in omap_i2c_xfer_msg on the last message.
According to the TI TSR the sequence for OMAP_I2C_STAT_NACK and
OMAP_I2C_STAT_AL are nearly the same.
Removing the OMAP_I2C_CON_STP part in the isr fix the problem.
Tested on OMAP4430 and OMAP3530 (here NACK was not a problem)
Fixes also booting on 2430sdp.
[Picked from http://patches.linaro.org/1899/]
Change-Id: I9bdeba8853ced27659770ad9390bd1b4be573155
Signed-off-by: Jan Weitzel <j.weitzel@phytec.de>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
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Fixup incompatible code in opp.c: omap_init_opp_table()
Change-Id: Iac7d60b814a539285d00e0a3dbb6e3f0060cb683
Signed-off-by: Todd Poynor <toddpoynor@google.com>
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commit 9868a060ccf769c08ec378a9829137e272e9a92c upstream.
The freed IRQ is not necessary the one requested in probe.
Even if it was, with two or more i2c-controllers it will fails anyway.
Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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commit 6c557cfee08751d22aed34840f389b846f0f4508 upstream.
In the driver's suspend function, clk_enable() was used instead of
clk_disable(). This is corrected with this patch.
Signed-off-by: Roland Stigge <stigge@antcom.de>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
[wsa: reworded commit header slightly]
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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This reverts commit 6c8e76e158a9bc849ec946ab030595e06ad89210.
This currently hangs at early boot, although per the TRM the change
is correct.
Change-Id: I24a25a7da0d8525e6e9775c01b23ce1cf9e452a4
Signed-off-by: Todd Poynor <toddpoynor@google.com>
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Change-Id: I336ba4d61beba035ecc237ccc68b012e48702a87
Signed-off-by: Todd Poynor <toddpoynor@google.com>
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Change-Id: I76904a60370e2cb9cc29ccde5d526d9183ff4f8e
Signed-off-by: Todd Poynor <toddpoynor@google.com>
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commit 844990daa2e69a4258049ba9c2bae1180657dac3 upstream.
The hardware generates an interrupt for every completed command in the
queue while the code assumed that it will only generate one interrupt
when the queue is empty. So, explicitly check if the queue is really
empty. This patch fixed problems which occurred due to high traffic on
the bus. While we are here, move the completion-initialization after the
parameter error checking.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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commit ff35e8b18984ad2a82cbd259fc07f0be4b34b1aa upstream.
This patch modified the setting value of
I2C Bus Transfer Rate Setting Counter regisrer.
Signed-off-by: Toshiharu Okada <toshiharu-linux@dsn.okisemi.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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commit 2727b1753934e154931d6b3bdf20c9b2398457a2 upstream.
Correct OMAP_I2C_SYSC_REG offset in omap4 register map.
Offset 0x20 is reserved and OMAP_I2C_SYSC_REG has 0x10 as offset.
Signed-off-by: Alexander Aring <a.aring@phytec.de>
[khilman@ti.com: minor changelog edits]
Signed-off-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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commit 7c1f59c9d5caf3a84f35549b5d58f3c055a68da5 upstream.
When adding checks for ACPI resource conflicts to many bus drivers,
not enough attention was paid to the error paths, and for several
drivers this causes 0 to be returned on error in some cases. Fix this
by properly returning a non-zero value on every error.
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Conflicts:
arch/arm/mach-omap2/dpll3xxx.c
Change-Id: Ie53daed5cabbadef73d18969263ff2f7b77b3dc7
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When cpu_is_omap44xx, dev->regs is set to point to
omap4_reg_map[], which contains entries for
OMAP_I2C_IRQENABLE_SET and OMAP_I2C_IRQENABLE_CLR. These entries
are not present in the other reg_map. However, the code that
uses these registers does not ensure that cpu_is_omap44xx before
using them. This can cause register 0x00 (the revision register)
to be accessed instead and the proper register to not be
accessed. This problem was observed on the OMAP3630 and caused
long hangs.
The fix is to ensure that cpu_is_omap44xx before accessing the
registers.
Thanks to vikram pandita for pointing me in the right direction.
Change-Id: Ic3accee9ce251724f13056bdb01f4db3308cd099
Signed-off-by: Scott Anderson <saa@google.com>
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In case a peripheral is holding the DATA bus low, provide a 400Khz
constant clock output using the TEST register.
Also soft reset the I2C controller so that there is no stale state
left in the HW state machine.
A WARN_ON() will be generated when a BB timeout happens.
Change-Id: I23b824f6ae3435ea2e4abf0cbc047584b1e9b449
Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
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The decision to call i2c_detect_ext_master() must be made dynamically. This
way we are locking out A9 I2C clients without any external requests.
Signed-off-by: Iliyan Malchev <malchev@google.com>
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Causes sensor and audio delays.
This reverts commit f0526a82e8f65e8a9acdd6ad5eaea738b569a3a5.
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Do not report XUDF or ROVR as an error to the driver making i2c transfer.
Its an indication by OMAP hw that these conditions are hitting,
but the real transfer should still go through
Change-Id: Id721d0037a850d34e15dd070ec4e53dacc90a8c4
Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
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For indicating ready-for-next-transfer, there is ARDY interrupt.
There is no need to have this interrupt enabled for indication of current
transfer as complete.
So resort to a combination of Interrupt and Polling mechanism.
Interrupt mechanism for: RRDY/RDR and XRDY/XDR
Polling mechanism for: ARDY
Before a message is to be sent, check for ARDY status ready with a timeout protection.
For one message the flow is:
Fifo operation; one interrupt; Done
Thus avoiding ARDY wait/interrupt altogether.
For two/more message transfer the flow is:
Fifo operation;one interrupt; wait_ardy(); fifo operation;Done
Thus avoiding 2 ARDY interrupts, instead only one ardy wait
Change-Id: Icf26731db373073bc300da2804979b5d509ac448
Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
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dev->iestate variable has the correct info on the interrupts enabled
at any time. So avoid un-necessary I2C_IE_REG read.
Change-Id: I75e315ef51b3f30bb41680cda7f4921218458fc1
Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
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For omap4xxx do not use the legacy register I2C_IE,
instead use the IRQENABLE_SET/CLR variant for future compatibility
Also at probe, there is no need to enable interrupts.
Change-Id: I103ce3c28a8a6d47a1a166cde440e73e772b2af2
Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
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IRQENABLE_CLR register should be written all 1's to clear interrupt enable
Change-Id: I04298218d381726892646112c9130ffed982ad7f
Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
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No new functionality, just add the missing register
Change-Id: I535e8a52f4bd12c9cea04db8f860ad82d85eedc9
Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
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Change-Id: I668431f6c62ace328e4a0207900c58232a96190d
Signed-off-by: Todd Poynor <toddpoynor@google.com>
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Note: Perform some special handling for externally controlled I2C devices.
For now we only disable spurious IRQs.
Change-Id: I50731ca50d675b7a997b1c0f87797eb8a90bbc8c
Signed-off-by: Gilles-Arnaud Bleu-Laine <gilles@ti.com>
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Dump I2C registers and associated PRCM module and FCLK info on
transfer completion timeouts and timeouts waiting for bus ready,
in hopes of tracking down intermittent errors.
Change-Id: I91d9630dd43468e1d4e69ec79f178d54cbccd317
Signed-off-by: Todd Poynor <toddpoynor@google.com>
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