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authorJean-Baptiste Queru <jbq@google.com>2012-08-27 14:22:22 -0700
committerandroid code review <noreply-gerritcodereview@google.com>2012-08-27 14:22:22 -0700
commitc3c5358b94f48799fd595c829ce223b43588bac1 (patch)
tree8c8146386d2de520fa14ea38781ea1ef0fe8d6a1 /libpixelflinger/codeflinger/CodeCache.cpp
parentbaba99840400f5b835d44b6d91e2190136277988 (diff)
parent2bc2b792782b304b15d8c48b54916a9b3fa3a7ac (diff)
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Merge "Add MIPS support to pixelflinger."
Diffstat (limited to 'libpixelflinger/codeflinger/CodeCache.cpp')
-rw-r--r--libpixelflinger/codeflinger/CodeCache.cpp12
1 files changed, 9 insertions, 3 deletions
diff --git a/libpixelflinger/codeflinger/CodeCache.cpp b/libpixelflinger/codeflinger/CodeCache.cpp
index 60fc771..7688290 100644
--- a/libpixelflinger/codeflinger/CodeCache.cpp
+++ b/libpixelflinger/codeflinger/CodeCache.cpp
@@ -39,6 +39,12 @@ namespace android {
#include <errno.h>
#endif
+#if defined(__mips__)
+#include <asm/cachectl.h>
+#include <errno.h>
+#endif
+
+// ----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// A dlmalloc mspace is used to manage the code cache over a mmaped region.
@@ -200,12 +206,12 @@ int CodeCache::cache( const AssemblyKeyBase& keyBase,
mCacheInUse += assemblySize;
mWhen++;
// synchronize caches...
-#if defined(__arm__)
+#if defined(__arm__) || defined(__mips__)
const long base = long(assembly->base());
const long curr = base + long(assembly->size());
err = cacheflush(base, curr, 0);
- ALOGE_IF(err, "__ARM_NR_cacheflush error %s\n",
- strerror(errno));
+ ALOGE_IF(err, "cacheflush error %s\n",
+ strerror(errno));
#endif
}