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| author | Steve Ellcey <Steve.Ellcey@imgtec.com> | 2014-07-03 13:25:21 -0700 |
|---|---|---|
| committer | Steve Ellcey <Steve.Ellcey@imgtec.com> | 2014-07-03 16:13:56 -0700 |
| commit | 8390634fd5fb311f01b82ba35a8db4b40b983cc8 (patch) | |
| tree | 0a83785a2d0c687553eb05872c30582fe6b5d9b1 | |
| parent | bcfb04363768d7eb2910bbefb263effae28ace10 (diff) | |
| download | toolchain_binutils-8390634fd5fb311f01b82ba35a8db4b40b983cc8.zip toolchain_binutils-8390634fd5fb311f01b82ba35a8db4b40b983cc8.tar.gz toolchain_binutils-8390634fd5fb311f01b82ba35a8db4b40b983cc8.tar.bz2 | |
Update Binutils 2.24 to include mips32r6, mips64r6 and MSA changes.
Change-Id: I24f28bc29dff188ba059388d8d5478f51da56a12
461 files changed, 26107 insertions, 2777 deletions
diff --git a/binutils-2.24/ChangeLog b/binutils-2.24/ChangeLog index e41638b..3dc2583 100644 --- a/binutils-2.24/ChangeLog +++ b/binutils-2.24/ChangeLog @@ -1,7 +1,33 @@ +2014-05-01 Richard Sandiford <rdsandiford@googlemail.com> + + * config.sub, config.guess: Import from upstream. + 2013-11-23 Alan Modra <amodra@gmail.com> * config.sub, config.guess: Import from upstream. +2013-11-11 Catherine Moore <clm@codesourcery.com> + + gas/ + * config/mips/tc-mips.c (convert_reg_type): Use + INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY. + (reg_needs_delay): Likewise. + (insns_between): Likewise. + + include/ + * opcode/mips.h (INSN_LOAD_MEMORY_DELAY): Rename to... + (INSN_LOAD_MEMORY): ...this. + + opcodes/ + * mips-dis.c (print_insn_mips): Use + INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY. + (print_insn_micromips): Likewise. + * mips-opc.c (LDD): Remove. + (CLD): Include INSN_LOAD_MEMORY. + (LM): New. + (mips_builtin_opcodes): Use LM instead of LDD. + Add LM to load instructions. + 2013-09-20 Alan Modra <amodra@gmail.com> * libtool.m4 (_LT_ENABLE_LOCK <ld -m flags>): Remove non-canonical diff --git a/binutils-2.24/bfd/ChangeLog b/binutils-2.24/bfd/ChangeLog index 2c4719c..b225e10 100644 --- a/binutils-2.24/bfd/ChangeLog +++ b/binutils-2.24/bfd/ChangeLog @@ -1,3 +1,55 @@ +2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com> + + * aoutx.h (NAME (aout, machine_type)): Add mips32r3, mips64r3, + mips32r5 and mips64r5. + * archures.c (bfd_architecture): Likewise. + * bfd-in2.h (bfd_architecture): Likewise. + * cpu-mips.c (arch_info_struct): Likewise. + * elfxx-mips.c (mips_set_isa_flags): Likewise. + +2014-05-06 Richard Sandiford <rdsandiford@googlemail.com> + + * elfxx-mips.h (elfxx-mips.h): Declare. + * elfxx-mips.c (mips_elf_merge_obj_attributes): Use it to report + Tag_GNU_MIPS_ABI_FP mismatches. + (_bfd_mips_fp_abi_string): New function. + +2014-04-17 Kwok Cheung Yeung <kcy@codesourcery.com> + + * elfxx-mips.c (struct mips_got_info): Delete assigned_gotno + field. Add assigned_low_gotno and assigned_high_gotno fields. + (mips_elf_create_local_got_entry): Update out-of-space condition. + Set index of new GOT entry to assigned_low_gotno if required by + the current relocation, else set it to assigned_high_gotno. + (mips_elf_set_global_gotidx): Replace uses of assigned_gotno + with assigned_low_gotno. + (mips_elf_multi_got): Initialize assigned_low_gotno and + assigned_high_gotno in secondary GOTs. Use assigned_low_gotno + in place of assigned_gotno when handling global GOT entries. + (mips_elf_lay_out_got): Initialize assigned_low_gotno and + assigned_high_gotno. + (_bfd_mips_elf_finish_dynamic_sections): Account for a possible + gap in the middle of local GOT space. + +2014-03-04 Heiher <r@hev.cc> + + * elfxx-mips.c (mips_set_isa_flags): Use E_MIPS_ARCH_64R2 for + Loongson-3A. + (mips_mach_extensions): Make bfd_mach_mips_loongson_3a an + extension of bfd_mach_mipsisa64r2. + +2014-02-18 Jack Carter <jack.carter@imgtec.com> + + * elfxx-mips.c(_bfd_mips_elf_modify_segment_map): Deleted hard coding of + PT_DYNAMIC segment flags. + +2014-01-16 Alan Modra <amodra@gmail.com> + + * elfxx-mips.c (mips_elf_record_got_page_entry): Pass in a + mips_elf_traverse_got_arg* rather than mips_got_info*. + Adjust caller. Alloc on output_bfd rather than symbol section + owner. + 2013-12-02 Tristan Gingold <gingold@adacore.com> * configure.in: Bump version to 2.24 @@ -219,6 +271,20 @@ * elf.c (copy_elf_program_header): Only consider SEC_ALLOC sections when finding lowest_section. +2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> + + * elfxx-mips.c (mips_elf_obj_tdata): Add abi_msa_bfd. + (mips_elf_merge_obj_attributes): Set abi_msa_bfd to the first object + file that has a Tag_GNU_MIPS_ABI_MSA attribute. + Merge Tag_GNU_MIPS_ABI_MSA attributes. + +2013-10-13 Richard Sandiford <rdsandiford@googlemail.com> + + * elfxx-mips.c (mips_use_local_got_p): New function. + (mips_elf_count_got_symbols, mips_elf_calculate_relocation): Use it. + (_bfd_mips_elf_check_relocs): Set pointer_equality_needed for + GOT and absolute references. + 2013-10-09 Roland McGrath <mcgrathr@google.com> * elf64-alpha.c (elf64_alpha_relax_tls_get_addr): Cast switch diff --git a/binutils-2.24/bfd/aoutx.h b/binutils-2.24/bfd/aoutx.h index 1e0ad38..e54366c 100644 --- a/binutils-2.24/bfd/aoutx.h +++ b/binutils-2.24/bfd/aoutx.h @@ -793,9 +793,15 @@ NAME (aout, machine_type) (enum bfd_architecture arch, case bfd_mach_mips16: case bfd_mach_mipsisa32: case bfd_mach_mipsisa32r2: + case bfd_mach_mipsisa32r3: + case bfd_mach_mipsisa32r5: + case bfd_mach_mipsisa32r6: case bfd_mach_mips5: case bfd_mach_mipsisa64: case bfd_mach_mipsisa64r2: + case bfd_mach_mipsisa64r3: + case bfd_mach_mipsisa64r5: + case bfd_mach_mipsisa64r6: case bfd_mach_mips_sb1: case bfd_mach_mips_xlr: /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc. */ diff --git a/binutils-2.24/bfd/archures.c b/binutils-2.24/bfd/archures.c index 97c540a..be78a22 100644 --- a/binutils-2.24/bfd/archures.c +++ b/binutils-2.24/bfd/archures.c @@ -180,8 +180,14 @@ DESCRIPTION .#define bfd_mach_mips_xlr 887682 {* decimal 'XLR' *} .#define bfd_mach_mipsisa32 32 .#define bfd_mach_mipsisa32r2 33 +.#define bfd_mach_mipsisa32r3 34 +.#define bfd_mach_mipsisa32r5 36 +.#define bfd_mach_mipsisa32r6 37 .#define bfd_mach_mipsisa64 64 .#define bfd_mach_mipsisa64r2 65 +.#define bfd_mach_mipsisa64r3 66 +.#define bfd_mach_mipsisa64r5 68 +.#define bfd_mach_mipsisa64r6 69 .#define bfd_mach_mips_micromips 96 . bfd_arch_i386, {* Intel 386 *} .#define bfd_mach_i386_intel_syntax (1 << 0) diff --git a/binutils-2.24/bfd/bfd-in2.h b/binutils-2.24/bfd/bfd-in2.h index 756af87..3097f04 100644 --- a/binutils-2.24/bfd/bfd-in2.h +++ b/binutils-2.24/bfd/bfd-in2.h @@ -1935,8 +1935,14 @@ enum bfd_architecture #define bfd_mach_mips_xlr 887682 /* decimal 'XLR' */ #define bfd_mach_mipsisa32 32 #define bfd_mach_mipsisa32r2 33 +#define bfd_mach_mipsisa32r3 34 +#define bfd_mach_mipsisa32r5 36 +#define bfd_mach_mipsisa32r6 37 #define bfd_mach_mipsisa64 64 #define bfd_mach_mipsisa64r2 65 +#define bfd_mach_mipsisa64r3 66 +#define bfd_mach_mipsisa64r5 68 +#define bfd_mach_mipsisa64r6 69 #define bfd_mach_mips_micromips 96 bfd_arch_i386, /* Intel 386 */ #define bfd_mach_i386_intel_syntax (1 << 0) @@ -2896,6 +2902,12 @@ to compensate for the borrow when the low bits are added. */ BFD_RELOC_MICROMIPS_10_PCREL_S1, BFD_RELOC_MICROMIPS_16_PCREL_S1, +/* MIPS PC-relative relocations. */ + BFD_RELOC_MIPS_21_PCREL_S2, + BFD_RELOC_MIPS_26_PCREL_S2, + BFD_RELOC_MIPS_18_PCREL_S3, + BFD_RELOC_MIPS_19_PCREL_S2, + /* microMIPS versions of generic BFD relocs. */ BFD_RELOC_MICROMIPS_GPREL16, BFD_RELOC_MICROMIPS_HI16, diff --git a/binutils-2.24/bfd/config.bfd b/binutils-2.24/bfd/config.bfd index 5324d39..d1643cc 100644 --- a/binutils-2.24/bfd/config.bfd +++ b/binutils-2.24/bfd/config.bfd @@ -1024,7 +1024,7 @@ case "${targ}" in targ_defvec=bfd_elf32_tradlittlemips_vec targ_selvecs="bfd_elf32_tradbigmips_vec bfd_elf32_ntradbigmips_vec bfd_elf32_ntradlittlemips_vec bfd_elf64_tradbigmips_vec bfd_elf64_tradlittlemips_vec" ;; - mips*-sde-elf* | mips*-mti-elf*) + mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) targ_defvec=bfd_elf32_tradbigmips_vec targ_selvecs="bfd_elf32_tradlittlemips_vec bfd_elf32_ntradbigmips_vec bfd_elf32_ntradlittlemips_vec bfd_elf64_tradbigmips_vec bfd_elf64_tradlittlemips_vec" ;; diff --git a/binutils-2.24/bfd/cpu-mips.c b/binutils-2.24/bfd/cpu-mips.c index 59a7c16..fc37cbe 100644 --- a/binutils-2.24/bfd/cpu-mips.c +++ b/binutils-2.24/bfd/cpu-mips.c @@ -89,8 +89,14 @@ enum I_mips5, I_mipsisa32, I_mipsisa32r2, + I_mipsisa32r3, + I_mipsisa32r5, + I_mipsisa32r6, I_mipsisa64, I_mipsisa64r2, + I_mipsisa64r3, + I_mipsisa64r5, + I_mipsisa64r6, I_sb1, I_loongson_2e, I_loongson_2f, @@ -133,8 +139,14 @@ static const bfd_arch_info_type arch_info_struct[] = N (64, 64, bfd_mach_mips5, "mips:mips5", FALSE, NN(I_mips5)), N (32, 32, bfd_mach_mipsisa32, "mips:isa32", FALSE, NN(I_mipsisa32)), N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)), + N (32, 32, bfd_mach_mipsisa32r3,"mips:isa32r3", FALSE, NN(I_mipsisa32r3)), + N (32, 32, bfd_mach_mipsisa32r5,"mips:isa32r5", FALSE, NN(I_mipsisa32r5)), + N (32, 32, bfd_mach_mipsisa32r6,"mips:isa32r6", FALSE, NN(I_mipsisa32r6)), N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)), N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)), + N (64, 64, bfd_mach_mipsisa64r3,"mips:isa64r3", FALSE, NN(I_mipsisa64r3)), + N (64, 64, bfd_mach_mipsisa64r5,"mips:isa64r5", FALSE, NN(I_mipsisa64r5)), + N (64, 64, bfd_mach_mipsisa64r6,"mips:isa64r6", FALSE, NN(I_mipsisa64r6)), N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)), N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", FALSE, NN(I_loongson_2e)), N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)), diff --git a/binutils-2.24/bfd/elf32-mips.c b/binutils-2.24/bfd/elf32-mips.c index eec2ef7..c9c4cc3 100644 --- a/binutils-2.24/bfd/elf32-mips.c +++ b/binutils-2.24/bfd/elf32-mips.c @@ -717,6 +717,100 @@ static reloc_howto_type elf_mips_howto_table_rel[] = 0x0, /* src_mask */ 0xffffffff, /* dst_mask */ FALSE), /* pcrel_offset */ + + EMPTY_HOWTO (52), + EMPTY_HOWTO (53), + EMPTY_HOWTO (54), + EMPTY_HOWTO (55), + EMPTY_HOWTO (56), + EMPTY_HOWTO (57), + EMPTY_HOWTO (58), + EMPTY_HOWTO (59), + + HOWTO (R_MIPS_PC21_S2, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 21, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC21_S2", /* name */ + TRUE, /* partial_inplace */ + 0x001fffff, /* src_mask */ + 0x001fffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PC26_S2, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 26, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC26_S2", /* name */ + TRUE, /* partial_inplace */ + 0x03ffffff, /* src_mask */ + 0x03ffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PC18_S3, /* type */ + 3, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 18, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC18_S3", /* name */ + TRUE, /* partial_inplace */ + 0x0003ffff, /* src_mask */ + 0x0003ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PC19_S2, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 19, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC19_S2", /* name */ + TRUE, /* partial_inplace */ + 0x0007ffff, /* src_mask */ + 0x0007ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PCHI16, /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PCHI16", /* name */ + TRUE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PCLO16, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PCLO16", /* name */ + TRUE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + }; /* The reloc used for BFD_RELOC_CTOR when doing a 64 bit link. This @@ -1906,7 +2000,13 @@ static const struct elf_reloc_map mips_reloc_map[] = { BFD_RELOC_MIPS_TLS_TPREL32, R_MIPS_TLS_TPREL32 }, { BFD_RELOC_MIPS_TLS_TPREL64, R_MIPS_TLS_TPREL64 }, { BFD_RELOC_MIPS_TLS_TPREL_HI16, R_MIPS_TLS_TPREL_HI16 }, - { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 } + { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 }, + { BFD_RELOC_MIPS_21_PCREL_S2, R_MIPS_PC21_S2 }, + { BFD_RELOC_MIPS_26_PCREL_S2, R_MIPS_PC26_S2 }, + { BFD_RELOC_MIPS_18_PCREL_S3, R_MIPS_PC18_S3 }, + { BFD_RELOC_MIPS_19_PCREL_S2, R_MIPS_PC19_S2 }, + { BFD_RELOC_HI16_S_PCREL, R_MIPS_PCHI16 }, + { BFD_RELOC_LO16_PCREL, R_MIPS_PCLO16 } }; static const struct elf_reloc_map mips16_reloc_map[] = @@ -2316,6 +2416,8 @@ static const struct ecoff_debug_swap mips_elf32_ecoff_debug_swap = { #define elf_backend_collect TRUE #define elf_backend_type_change_ok TRUE #define elf_backend_can_gc_sections TRUE +#define elf_backend_gc_mark_extra_sections \ + _bfd_mips_elf_gc_mark_extra_sections #define elf_info_to_howto mips_info_to_howto_rela #define elf_info_to_howto_rel mips_info_to_howto_rel #define elf_backend_sym_is_global mips_elf_sym_is_global diff --git a/binutils-2.24/bfd/elf64-mips.c b/binutils-2.24/bfd/elf64-mips.c index a0c5cc5..c090fb7 100644 --- a/binutils-2.24/bfd/elf64-mips.c +++ b/binutils-2.24/bfd/elf64-mips.c @@ -807,6 +807,100 @@ static reloc_howto_type mips_elf64_howto_table_rel[] = 0x0, /* src_mask */ 0xffffffff, /* dst_mask */ FALSE), /* pcrel_offset */ + + EMPTY_HOWTO (52), + EMPTY_HOWTO (53), + EMPTY_HOWTO (54), + EMPTY_HOWTO (55), + EMPTY_HOWTO (56), + EMPTY_HOWTO (57), + EMPTY_HOWTO (58), + EMPTY_HOWTO (59), + + HOWTO (R_MIPS_PC21_S2, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 21, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC21_S2", /* name */ + TRUE, /* partial_inplace */ + 0x001fffff, /* src_mask */ + 0x001fffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PC26_S2, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 26, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC26_S2", /* name */ + TRUE, /* partial_inplace */ + 0x03ffffff, /* src_mask */ + 0x03ffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PC18_S3, /* type */ + 3, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 18, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC18_S3", /* name */ + TRUE, /* partial_inplace */ + 0x0003ffff, /* src_mask */ + 0x0003ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PC19_S2, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 19, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC19_S2", /* name */ + TRUE, /* partial_inplace */ + 0x0007ffff, /* src_mask */ + 0x0007ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PCHI16, /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PCHI16", /* name */ + TRUE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PCLO16, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PCLO16", /* name */ + TRUE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + }; /* The relocation table used for SHT_RELA sections. */ @@ -1494,6 +1588,100 @@ static reloc_howto_type mips_elf64_howto_table_rela[] = 0x0, /* src_mask */ 0xffffffff, /* dst_mask */ FALSE), /* pcrel_offset */ + + EMPTY_HOWTO (52), + EMPTY_HOWTO (53), + EMPTY_HOWTO (54), + EMPTY_HOWTO (55), + EMPTY_HOWTO (56), + EMPTY_HOWTO (57), + EMPTY_HOWTO (58), + EMPTY_HOWTO (59), + + HOWTO (R_MIPS_PC21_S2, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 21, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC21_S2", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0x001fffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PC26_S2, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 26, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC26_S2", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0x03ffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PC18_S3, /* type */ + 3, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 18, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC18_S3", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0x0003ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PC19_S2, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 19, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC19_S2", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0x0007ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PCHI16, /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PCHI16", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0x0000ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PCLO16, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PCLO16", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0x0000ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + }; static reloc_howto_type mips16_elf64_howto_table_rel[] = @@ -3204,7 +3392,13 @@ static const struct elf_reloc_map mips_reloc_map[] = { BFD_RELOC_MIPS_TLS_TPREL32, R_MIPS_TLS_TPREL32 }, { BFD_RELOC_MIPS_TLS_TPREL64, R_MIPS_TLS_TPREL64 }, { BFD_RELOC_MIPS_TLS_TPREL_HI16, R_MIPS_TLS_TPREL_HI16 }, - { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 } + { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 }, + { BFD_RELOC_MIPS_21_PCREL_S2, R_MIPS_PC21_S2 }, + { BFD_RELOC_MIPS_26_PCREL_S2, R_MIPS_PC26_S2 }, + { BFD_RELOC_MIPS_18_PCREL_S3, R_MIPS_PC18_S3 }, + { BFD_RELOC_MIPS_19_PCREL_S2, R_MIPS_PC19_S2 }, + { BFD_RELOC_HI16_S_PCREL, R_MIPS_PCHI16 }, + { BFD_RELOC_LO16_PCREL, R_MIPS_PCLO16 } }; static const struct elf_reloc_map mips16_reloc_map[] = @@ -4187,6 +4381,8 @@ const struct elf_size_info mips_elf64_size_info = #define elf_backend_collect TRUE #define elf_backend_type_change_ok TRUE #define elf_backend_can_gc_sections TRUE +#define elf_backend_gc_mark_extra_sections \ + _bfd_mips_elf_gc_mark_extra_sections #define elf_info_to_howto mips_elf64_info_to_howto_rela #define elf_info_to_howto_rel mips_elf64_info_to_howto_rel #define elf_backend_object_p mips_elf64_object_p diff --git a/binutils-2.24/bfd/elfn32-mips.c b/binutils-2.24/bfd/elfn32-mips.c index 2daf79e..2fb019f 100644 --- a/binutils-2.24/bfd/elfn32-mips.c +++ b/binutils-2.24/bfd/elfn32-mips.c @@ -771,6 +771,100 @@ static reloc_howto_type elf_mips_howto_table_rel[] = 0x0, /* src_mask */ 0xffffffff, /* dst_mask */ FALSE), /* pcrel_offset */ + + EMPTY_HOWTO (52), + EMPTY_HOWTO (53), + EMPTY_HOWTO (54), + EMPTY_HOWTO (55), + EMPTY_HOWTO (56), + EMPTY_HOWTO (57), + EMPTY_HOWTO (58), + EMPTY_HOWTO (59), + + HOWTO (R_MIPS_PC21_S2, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 21, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC21_S2", /* name */ + TRUE, /* partial_inplace */ + 0x001fffff, /* src_mask */ + 0x001fffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PC26_S2, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 26, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC26_S2", /* name */ + TRUE, /* partial_inplace */ + 0x03ffffff, /* src_mask */ + 0x03ffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PC18_S3, /* type */ + 3, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 18, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC18_S3", /* name */ + TRUE, /* partial_inplace */ + 0x0003ffff, /* src_mask */ + 0x0003ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PC19_S2, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 19, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC19_S2", /* name */ + TRUE, /* partial_inplace */ + 0x0007ffff, /* src_mask */ + 0x0007ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PCHI16, /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PCHI16", /* name */ + TRUE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PCLO16, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PCLO16", /* name */ + TRUE, /* partial_inplace */ + 0x0000ffff, /* src_mask */ + 0x0000ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + }; /* The relocation table used for SHT_RELA sections. */ @@ -1459,6 +1553,100 @@ static reloc_howto_type elf_mips_howto_table_rela[] = 0x0, /* src_mask */ 0xffffffff, /* dst_mask */ FALSE), /* pcrel_offset */ + + EMPTY_HOWTO (52), + EMPTY_HOWTO (53), + EMPTY_HOWTO (54), + EMPTY_HOWTO (55), + EMPTY_HOWTO (56), + EMPTY_HOWTO (57), + EMPTY_HOWTO (58), + EMPTY_HOWTO (59), + + HOWTO (R_MIPS_PC21_S2, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 21, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC21_S2", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0x001fffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PC26_S2, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 26, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC26_S2", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0x03ffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PC18_S3, /* type */ + 3, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 18, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC18_S3", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0x0003ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PC19_S2, /* type */ + 2, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 19, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PC19_S2", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0x0007ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PCHI16, /* type */ + 16, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PCHI16", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0x0000ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + HOWTO (R_MIPS_PCLO16, /* type */ + 0, /* rightshift */ + 2, /* size (0 = byte, 1 = short, 2 = long) */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_mips_elf_generic_reloc, /* special_function */ + "R_MIPS_PCLO16", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0x0000ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + }; static reloc_howto_type elf_mips16_howto_table_rel[] = @@ -3019,7 +3207,13 @@ static const struct elf_reloc_map mips_reloc_map[] = { BFD_RELOC_MIPS_TLS_TPREL32, R_MIPS_TLS_TPREL32 }, { BFD_RELOC_MIPS_TLS_TPREL64, R_MIPS_TLS_TPREL64 }, { BFD_RELOC_MIPS_TLS_TPREL_HI16, R_MIPS_TLS_TPREL_HI16 }, - { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 } + { BFD_RELOC_MIPS_TLS_TPREL_LO16, R_MIPS_TLS_TPREL_LO16 }, + { BFD_RELOC_MIPS_21_PCREL_S2, R_MIPS_PC21_S2 }, + { BFD_RELOC_MIPS_26_PCREL_S2, R_MIPS_PC26_S2 }, + { BFD_RELOC_MIPS_18_PCREL_S3, R_MIPS_PC18_S3 }, + { BFD_RELOC_MIPS_19_PCREL_S2, R_MIPS_PC19_S2 }, + { BFD_RELOC_HI16_S_PCREL, R_MIPS_PCHI16 }, + { BFD_RELOC_LO16_PCREL, R_MIPS_PCLO16 } }; static const struct elf_reloc_map mips16_reloc_map[] = @@ -3411,6 +3605,8 @@ static const struct ecoff_debug_swap mips_elf32_ecoff_debug_swap = { #define elf_backend_collect TRUE #define elf_backend_type_change_ok TRUE #define elf_backend_can_gc_sections TRUE +#define elf_backend_gc_mark_extra_sections \ + _bfd_mips_elf_gc_mark_extra_sections #define elf_info_to_howto mips_info_to_howto_rela #define elf_info_to_howto_rel mips_info_to_howto_rel #define elf_backend_sym_is_global mips_elf_sym_is_global diff --git a/binutils-2.24/bfd/elfxx-mips.c b/binutils-2.24/bfd/elfxx-mips.c index d7498e1..4b8bca7 100644 --- a/binutils-2.24/bfd/elfxx-mips.c +++ b/binutils-2.24/bfd/elfxx-mips.c @@ -168,8 +168,10 @@ struct mips_got_info unsigned int page_gotno; /* The number of relocations needed for the GOT entries. */ unsigned int relocs; - /* The number of local .got entries we have used. */ - unsigned int assigned_gotno; + /* The first unused local .got entry. */ + unsigned int assigned_low_gotno; + /* The last unused local .got entry. */ + unsigned int assigned_high_gotno; /* A hash table holding members of the got. */ struct htab *got_entries; /* A hash table holding mips_got_page_ref structures. */ @@ -542,6 +544,13 @@ struct mips_elf_obj_tdata /* Input BFD providing Tag_GNU_MIPS_ABI_FP attribute for output. */ bfd *abi_fp_bfd; + /* Input BFD providing Tag_GNU_MIPS_ABI_MSA attribute for output. */ + bfd *abi_msa_bfd; + + /* The abiflags for this object. */ + Elf_Internal_ABIFlags_v0 abiflags; + bfd_boolean abiflags_valid; + /* The GOT requirements of input bfds. */ struct mips_got_info *got; @@ -771,6 +780,10 @@ static bfd *reldyn_sorting_bfd; #define PIC_OBJECT_P(abfd) \ ((elf_elfheader (abfd)->e_flags & EF_MIPS_PIC) != 0) +/* Nonzero if ABFD is using the O32 ABI. */ +#define ABI_O32_P(abfd) \ + ((elf_elfheader (abfd)->e_flags & EF_MIPS_ABI) == E_MIPS_ABI_O32) + /* Nonzero if ABFD is using the N32 ABI. */ #define ABI_N32_P(abfd) \ ((elf_elfheader (abfd)->e_flags & EF_MIPS_ABI2) != 0) @@ -786,6 +799,11 @@ static bfd *reldyn_sorting_bfd; #define MICROMIPS_P(abfd) \ ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0) +/* Nonzero if ABFD is MIPS R6. */ +#define MIPSR6_P(abfd) \ + ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R6 \ + || (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64R6) + /* The IRIX compatibility level we are striving for. */ #define IRIX_COMPAT(abfd) \ (get_elf_backend_data (abfd)->elf_backend_mips_irix_compat (abfd)) @@ -803,6 +821,10 @@ static bfd *reldyn_sorting_bfd; #define MIPS_ELF_OPTIONS_SECTION_NAME_P(NAME) \ (strcmp (NAME, ".MIPS.options") == 0 || strcmp (NAME, ".options") == 0) +/* True if NAME is the recognized name of any SHT_MIPS_ABIFLAGS section. */ +#define MIPS_ELF_ABIFLAGS_SECTION_NAME_P(NAME) \ + (strcmp (NAME, ".MIPS.abiflags") == 0) + /* Whether the section is readonly. */ #define MIPS_ELF_READONLY_SECTION(sec) \ ((sec->flags & (SEC_ALLOC | SEC_LOAD | SEC_READONLY)) \ @@ -1083,6 +1105,14 @@ static const bfd_vma mips_exec_plt_entry[] = 0x03200008 /* jr $25 */ }; +static const bfd_vma mipsr6_exec_plt_entry[] = +{ + 0x3c0f0000, /* lui $15, %hi(.got.plt entry) */ + 0x01f90000, /* l[wd] $25, %lo(.got.plt entry)($15) */ + 0x25f80000, /* addiu $24, $15, %lo(.got.plt entry) */ + 0x03200009 /* jr $25 */ +}; + /* The format of subsequent MIPS16 o32 PLT entries. We use v0 ($2) and v1 ($3) as temporaries because t8 ($24) and t9 ($25) are not directly addressable. */ @@ -2163,7 +2193,8 @@ hi16_reloc_p (int r_type) { return (r_type == R_MIPS_HI16 || r_type == R_MIPS16_HI16 - || r_type == R_MICROMIPS_HI16); + || r_type == R_MICROMIPS_HI16 + || r_type == R_MIPS_PCHI16); } static inline bfd_boolean @@ -2171,7 +2202,8 @@ lo16_reloc_p (int r_type) { return (r_type == R_MIPS_LO16 || r_type == R_MIPS16_LO16 - || r_type == R_MICROMIPS_LO16); + || r_type == R_MICROMIPS_LO16 + || r_type == R_MIPS_PCLO16); } static inline bfd_boolean @@ -2189,6 +2221,13 @@ jal_reloc_p (int r_type) } static inline bfd_boolean +aligned_pcrel_reloc_p (int r_type) +{ + return (r_type == R_MIPS_PC18_S3 + || r_type == R_MIPS_PC19_S2); +} + +static inline bfd_boolean micromips_branch_reloc_p (int r_type) { return (r_type == R_MICROMIPS_26_S1 @@ -2659,6 +2698,46 @@ bfd_mips_elf_swap_options_out (bfd *abfd, const Elf_Internal_Options *in, H_PUT_16 (abfd, in->section, ex->section); H_PUT_32 (abfd, in->info, ex->info); } + +/* Swap in an abiflags structure. */ + +void +bfd_mips_elf_swap_abiflags_v0_in (bfd *abfd, + const Elf_External_ABIFlags_v0 *ex, + Elf_Internal_ABIFlags_v0 *in) +{ + in->version = H_GET_16 (abfd, ex->version); + in->isa_level = H_GET_8 (abfd, ex->isa_level); + in->isa_rev = H_GET_8 (abfd, ex->isa_rev); + in->gpr_size = H_GET_8 (abfd, ex->gpr_size); + in->cpr1_size = H_GET_8 (abfd, ex->cpr1_size); + in->cpr2_size = H_GET_8 (abfd, ex->cpr2_size); + in->fp_abi = H_GET_8 (abfd, ex->fp_abi); + in->isa_ext = H_GET_32 (abfd, ex->isa_ext); + in->ases = H_GET_32 (abfd, ex->ases); + in->flags1 = H_GET_32 (abfd, ex->flags1); + in->flags2 = H_GET_32 (abfd, ex->flags2); +} + +/* Swap out an abiflags structure. */ + +void +bfd_mips_elf_swap_abiflags_v0_out (bfd *abfd, + const Elf_Internal_ABIFlags_v0 *in, + Elf_External_ABIFlags_v0 *ex) +{ + H_PUT_16 (abfd, in->version, ex->version); + H_PUT_8 (abfd, in->isa_level, ex->isa_level); + H_PUT_8 (abfd, in->isa_rev, ex->isa_rev); + H_PUT_8 (abfd, in->gpr_size, ex->gpr_size); + H_PUT_8 (abfd, in->cpr1_size, ex->cpr1_size); + H_PUT_8 (abfd, in->cpr2_size, ex->cpr2_size); + H_PUT_8 (abfd, in->fp_abi, ex->fp_abi); + H_PUT_32 (abfd, in->isa_ext, ex->isa_ext); + H_PUT_32 (abfd, in->ases, ex->ases); + H_PUT_32 (abfd, in->flags1, ex->flags1); + H_PUT_32 (abfd, in->flags2, ex->flags2); +} /* This function is called via qsort() to sort the dynamic relocation entries by increasing r_symndx value. */ @@ -3632,7 +3711,7 @@ mips_elf_create_local_got_entry (bfd *abfd, struct bfd_link_info *info, if (entry) return entry; - if (g->assigned_gotno >= g->local_gotno) + if (g->assigned_low_gotno > g->assigned_high_gotno) { /* We didn't allocate enough space in the GOT. */ (*_bfd_error_handler) @@ -3645,7 +3724,14 @@ mips_elf_create_local_got_entry (bfd *abfd, struct bfd_link_info *info, if (!entry) return NULL; - lookup.gotidx = MIPS_ELF_GOT_SIZE (abfd) * g->assigned_gotno++; + if (got16_reloc_p (r_type) + || call16_reloc_p (r_type) + || got_page_reloc_p (r_type) + || got_disp_reloc_p (r_type)) + lookup.gotidx = MIPS_ELF_GOT_SIZE (abfd) * g->assigned_low_gotno++; + else + lookup.gotidx = MIPS_ELF_GOT_SIZE (abfd) * g->assigned_high_gotno--; + *entry = lookup; *loc = entry; @@ -4086,9 +4172,10 @@ mips_elf_pages_for_range (const struct mips_got_page_range *range) /* Record that G requires a page entry that can reach SEC + ADDEND. */ static bfd_boolean -mips_elf_record_got_page_entry (struct mips_got_info *g, +mips_elf_record_got_page_entry (struct mips_elf_traverse_got_arg *arg, asection *sec, bfd_signed_vma addend) { + struct mips_got_info *g = arg->g; struct mips_got_page_entry lookup, *entry; struct mips_got_page_range **range_ptr, *range; bfd_vma old_pages, new_pages; @@ -4105,7 +4192,7 @@ mips_elf_record_got_page_entry (struct mips_got_info *g, entry = (struct mips_got_page_entry *) *loc; if (!entry) { - entry = bfd_zalloc (sec->owner, sizeof (*entry)); + entry = bfd_zalloc (arg->info->output_bfd, sizeof (*entry)); if (!entry) return FALSE; @@ -4125,7 +4212,7 @@ mips_elf_record_got_page_entry (struct mips_got_info *g, range = *range_ptr; if (!range || addend < range->min_addend - 0xffff) { - range = bfd_zalloc (sec->owner, sizeof (*range)); + range = bfd_zalloc (arg->info->output_bfd, sizeof (*range)); if (!range) return FALSE; @@ -4245,7 +4332,7 @@ mips_elf_resolve_got_page_ref (void **refp, void *data) else addend = isym->st_value + ref->addend; } - if (!mips_elf_record_got_page_entry (arg->g, sec, addend)) + if (!mips_elf_record_got_page_entry (arg, sec, addend)) { arg->g = NULL; return 0; @@ -4299,6 +4386,36 @@ mips_elf_resolve_final_got_entries (struct bfd_link_info *info, return TRUE; } +/* Return true if a GOT entry for H should live in the local rather than + global GOT area. */ + +static bfd_boolean +mips_use_local_got_p (struct bfd_link_info *info, + struct mips_elf_link_hash_entry *h) +{ + /* Symbols that aren't in the dynamic symbol table must live in the + local GOT. This includes symbols that are completely undefined + and which therefore don't bind locally. We'll report undefined + symbols later if appropriate. */ + if (h->root.dynindx == -1) + return TRUE; + + /* Symbols that bind locally can (and in the case of forced-local + symbols, must) live in the local GOT. */ + if (h->got_only_for_calls + ? SYMBOL_CALLS_LOCAL (info, &h->root) + : SYMBOL_REFERENCES_LOCAL (info, &h->root)) + return TRUE; + + /* If this is an executable that must provide a definition of the symbol, + either though PLTs or copy relocations, then that address should go in + the local rather than global GOT. */ + if (info->executable && h->has_static_relocs) + return TRUE; + + return FALSE; +} + /* A mips_elf_link_hash_traverse callback for which DATA points to the link_info structure. Decide whether the hash entry needs an entry in the global part of the primary GOT, setting global_got_area accordingly. @@ -4318,18 +4435,8 @@ mips_elf_count_got_symbols (struct mips_elf_link_hash_entry *h, void *data) if (h->global_got_area != GGA_NONE) { /* Make a final decision about whether the symbol belongs in the - local or global GOT. Symbols that bind locally can (and in the - case of forced-local symbols, must) live in the local GOT. - Those that are aren't in the dynamic symbol table must also - live in the local GOT. - - Note that the former condition does not always imply the - latter: symbols do not bind locally if they are completely - undefined. We'll report undefined symbols later if appropriate. */ - if (h->root.dynindx == -1 - || (h->got_only_for_calls - ? SYMBOL_CALLS_LOCAL (info, &h->root) - : SYMBOL_REFERENCES_LOCAL (info, &h->root))) + local or global GOT. */ + if (mips_use_local_got_p (info, h)) /* The symbol belongs in the local GOT. We no longer need this entry if it was only used for relocations; those relocations will be against the null or section symbol instead of H. */ @@ -4604,12 +4711,12 @@ mips_elf_set_global_gotidx (void **entryp, void *data) && entry->symndx == -1 && entry->d.h->global_got_area != GGA_NONE) { - if (!mips_elf_set_gotidx (entryp, arg->value * arg->g->assigned_gotno)) + if (!mips_elf_set_gotidx (entryp, arg->value * arg->g->assigned_low_gotno)) { arg->g = NULL; return 0; } - arg->g->assigned_gotno += 1; + arg->g->assigned_low_gotno += 1; if (arg->info->shared || (elf_hash_table (arg->info)->dynamic_sections_created @@ -4742,7 +4849,7 @@ mips_elf_multi_got (bfd *abfd, struct bfd_link_info *info, htab_traverse (g->got_entries, mips_elf_set_global_got_area, &tga); /* Now go through the GOTs assigning them offset ranges. - [assigned_gotno, local_gotno[ will be set to the range of local + [assigned_low_gotno, local_gotno[ will be set to the range of local entries in each GOT. We can then compute the end of a GOT by adding local_gotno to global_gotno. We reverse the list and make it circular since then we'll be able to quickly compute the @@ -4765,9 +4872,10 @@ mips_elf_multi_got (bfd *abfd, struct bfd_link_info *info, struct mips_got_info *gn; assign += htab->reserved_gotno; - g->assigned_gotno = assign; + g->assigned_low_gotno = assign; g->local_gotno += assign; g->local_gotno += (pages < g->page_gotno ? pages : g->page_gotno); + g->assigned_high_gotno = g->local_gotno - 1; assign = g->local_gotno + g->global_gotno + g->tls_gotno; /* Take g out of the direct list, and push it onto the reversed @@ -4806,21 +4914,21 @@ mips_elf_multi_got (bfd *abfd, struct bfd_link_info *info, /* Assign offsets to global GOT entries and count how many relocations they need. */ - save_assign = g->assigned_gotno; - g->assigned_gotno = g->local_gotno; + save_assign = g->assigned_low_gotno; + g->assigned_low_gotno = g->local_gotno; tga.info = info; tga.value = MIPS_ELF_GOT_SIZE (abfd); tga.g = g; htab_traverse (g->got_entries, mips_elf_set_global_gotidx, &tga); if (!tga.g) return FALSE; - BFD_ASSERT (g->assigned_gotno == g->local_gotno + g->global_gotno); - g->assigned_gotno = save_assign; + BFD_ASSERT (g->assigned_low_gotno == g->local_gotno + g->global_gotno); + g->assigned_low_gotno = save_assign; if (info->shared) { - g->relocs += g->local_gotno - g->assigned_gotno; - BFD_ASSERT (g->assigned_gotno == g->next->local_gotno + g->relocs += g->local_gotno - g->assigned_low_gotno; + BFD_ASSERT (g->assigned_low_gotno == g->next->local_gotno + g->next->global_gotno + g->next->tls_gotno + htab->reserved_gotno); @@ -5075,6 +5183,8 @@ mips_elf_relocation_needs_la25_stub (bfd *input_bfd, int r_type, { case R_MIPS_26: case R_MIPS_PC16: + case R_MIPS_PC21_S2: + case R_MIPS_PC26_S2: case R_MICROMIPS_26_S1: case R_MICROMIPS_PC7_S1: case R_MICROMIPS_PC10_S1: @@ -5468,10 +5578,7 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd, && (target_is_16_bit_code_p || target_is_micromips_code_p)))); - local_p = (h == NULL - || (h->got_only_for_calls - ? SYMBOL_CALLS_LOCAL (info, &h->root) - : SYMBOL_REFERENCES_LOCAL (info, &h->root))); + local_p = (h == NULL || mips_use_local_got_p (info, h)); gp0 = _bfd_get_gp_value (input_bfd); gp = _bfd_get_gp_value (abfd); @@ -5862,12 +5969,74 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd, case R_MIPS_PC16: case R_MIPS_GNU_REL16_S2: - value = symbol + _bfd_mips_elf_sign_extend (addend, 18) - p; + if (howto->partial_inplace) + addend = _bfd_mips_elf_sign_extend (addend, 18); + value = symbol + addend - p; overflowed_p = mips_elf_overflow_p (value, 18); value >>= howto->rightshift; value &= howto->dst_mask; break; + case R_MIPS_PC21_S2: + if (howto->partial_inplace) + addend = _bfd_mips_elf_sign_extend (addend, 23); + value = symbol + addend - p; + overflowed_p = mips_elf_overflow_p (value, 23); + value >>= howto->rightshift; + value &= howto->dst_mask; + break; + + case R_MIPS_PC26_S2: + if (howto->partial_inplace) + addend = _bfd_mips_elf_sign_extend (addend, 28); + value = symbol + addend - p; + overflowed_p = mips_elf_overflow_p (value, 28); + value >>= howto->rightshift; + value &= howto->dst_mask; + break; + + case R_MIPS_PC18_S3: + if (howto->partial_inplace) + addend = _bfd_mips_elf_sign_extend (addend, 21); + + if ((symbol + addend) & 7) + return bfd_reloc_outofrange; + + value = symbol + addend - ((p | 7) ^ 7); + overflowed_p = mips_elf_overflow_p (value, 21); + value >>= howto->rightshift; + value &= howto->dst_mask; + break; + + case R_MIPS_PC19_S2: + if (howto->partial_inplace) + addend = _bfd_mips_elf_sign_extend (addend, 21); + + if ((symbol + addend) & 3) + return bfd_reloc_outofrange; + + value = symbol + addend - p; + overflowed_p = mips_elf_overflow_p (value, 21); + value >>= howto->rightshift; + value &= howto->dst_mask; + break; + + case R_MIPS_PCHI16: + if (howto->partial_inplace) + addend = _bfd_mips_elf_sign_extend (addend, 16); + value = mips_elf_high (symbol + addend - p); + BFD_ASSERT (howto->rightshift == 16); + overflowed_p = mips_elf_overflow_p (value, 16); + value &= howto->dst_mask; + break; + + case R_MIPS_PCLO16: + if (howto->partial_inplace) + addend = _bfd_mips_elf_sign_extend (addend, 16); + value = symbol + _bfd_mips_elf_sign_extend (addend, 16) - p; + value &= howto->dst_mask; + break; + case R_MICROMIPS_PC7_S1: value = symbol + _bfd_mips_elf_sign_extend (addend, 8) - p; overflowed_p = mips_elf_overflow_p (value, 8); @@ -6434,6 +6603,12 @@ _bfd_elf_mips_mach (flagword flags) case E_MIPS_ARCH_64R2: return bfd_mach_mipsisa64r2; + + case E_MIPS_ARCH_32R6: + return bfd_mach_mipsisa32r6; + + case E_MIPS_ARCH_64R6: + return bfd_mach_mipsisa64r6; } } @@ -6879,6 +7054,11 @@ _bfd_mips_elf_section_from_shdr (bfd *abfd, if (!MIPS_ELF_OPTIONS_SECTION_NAME_P (name)) return FALSE; break; + case SHT_MIPS_ABIFLAGS: + if (!MIPS_ELF_ABIFLAGS_SECTION_NAME_P (name)) + return FALSE; + flags = (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_SAME_SIZE); + break; case SHT_MIPS_DWARF: if (! CONST_STRNEQ (name, ".debug_") && ! CONST_STRNEQ (name, ".zdebug_")) @@ -6909,6 +7089,20 @@ _bfd_mips_elf_section_from_shdr (bfd *abfd, return FALSE; } + if (hdr->sh_type == SHT_MIPS_ABIFLAGS) + { + Elf_External_ABIFlags_v0 ext; + + if (! bfd_get_section_contents (abfd, hdr->bfd_section, + &ext, 0, sizeof ext)) + return FALSE; + bfd_mips_elf_swap_abiflags_v0_in (abfd, &ext, + &mips_elf_tdata (abfd)->abiflags); + if (mips_elf_tdata (abfd)->abiflags.version != 0) + return FALSE; + mips_elf_tdata (abfd)->abiflags_valid = TRUE; + } + /* FIXME: We should record sh_info for a .gptab section. */ /* For a .reginfo section, set the gp value in the tdata information @@ -7075,6 +7269,11 @@ _bfd_mips_elf_fake_sections (bfd *abfd, Elf_Internal_Shdr *hdr, asection *sec) hdr->sh_entsize = 1; hdr->sh_flags |= SHF_MIPS_NOSTRIP; } + else if (CONST_STRNEQ (name, ".MIPS.abiflags")) + { + hdr->sh_type = SHT_MIPS_ABIFLAGS; + hdr->sh_entsize = sizeof (Elf_External_ABIFlags_v0); + } else if (CONST_STRNEQ (name, ".debug_") || CONST_STRNEQ (name, ".zdebug_")) { @@ -7586,6 +7785,8 @@ mips_elf_add_lo16_rel_addend (bfd *abfd, lo16_type = R_MIPS16_LO16; else if (micromips_reloc_p (r_type)) lo16_type = R_MICROMIPS_LO16; + else if (r_type == R_MIPS_PCHI16) + lo16_type = R_MIPS_PCLO16; else lo16_type = R_MIPS_LO16; @@ -7955,6 +8156,8 @@ _bfd_mips_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, unsigned int r_type; struct elf_link_hash_entry *h; bfd_boolean can_make_dynamic_p; + bfd_boolean call_reloc_p; + bfd_boolean constrain_symbol_p; r_symndx = ELF_R_SYM (abfd, rel->r_info); r_type = ELF_R_TYPE (abfd, rel->r_info); @@ -7987,12 +8190,30 @@ _bfd_mips_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, /* Set CAN_MAKE_DYNAMIC_P to true if we can convert this relocation into a dynamic one. */ can_make_dynamic_p = FALSE; + + /* Set CALL_RELOC_P to true if the relocation is for a call, + and if pointer equality therefore doesn't matter. */ + call_reloc_p = FALSE; + + /* Set CONSTRAIN_SYMBOL_P if we need to take the relocation + into account when deciding how to define the symbol. + Relocations in nonallocatable sections such as .pdr and + .debug* should have no effect. */ + constrain_symbol_p = ((sec->flags & SEC_ALLOC) != 0); + switch (r_type) { - case R_MIPS_GOT16: case R_MIPS_CALL16: case R_MIPS_CALL_HI16: case R_MIPS_CALL_LO16: + case R_MIPS16_CALL16: + case R_MICROMIPS_CALL16: + case R_MICROMIPS_CALL_HI16: + case R_MICROMIPS_CALL_LO16: + call_reloc_p = TRUE; + /* Fall through. */ + + case R_MIPS_GOT16: case R_MIPS_GOT_HI16: case R_MIPS_GOT_LO16: case R_MIPS_GOT_PAGE: @@ -8002,14 +8223,10 @@ _bfd_mips_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, case R_MIPS_TLS_GD: case R_MIPS_TLS_LDM: case R_MIPS16_GOT16: - case R_MIPS16_CALL16: case R_MIPS16_TLS_GOTTPREL: case R_MIPS16_TLS_GD: case R_MIPS16_TLS_LDM: case R_MICROMIPS_GOT16: - case R_MICROMIPS_CALL16: - case R_MICROMIPS_CALL_HI16: - case R_MICROMIPS_CALL_LO16: case R_MICROMIPS_GOT_HI16: case R_MICROMIPS_GOT_LO16: case R_MICROMIPS_GOT_PAGE: @@ -8030,12 +8247,27 @@ _bfd_mips_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, bfd_set_error (bfd_error_bad_value); return FALSE; } + can_make_dynamic_p = TRUE; break; - /* This is just a hint; it can safely be ignored. Don't set - has_static_relocs for the corresponding symbol. */ + case R_MIPS_NONE: case R_MIPS_JALR: case R_MICROMIPS_JALR: + /* These relocations have empty fields and are purely there to + provide link information. The symbol value doesn't matter. */ + constrain_symbol_p = FALSE; + break; + + case R_MIPS_GPREL16: + case R_MIPS_GPREL32: + case R_MIPS16_GPREL: + case R_MICROMIPS_GPREL16: + /* GP-relative relocations always resolve to a definition in a + regular input file, ignoring the one-definition rule. This is + important for the GP setup sequence in NewABI code, which + always resolves to a local function even if other relocations + against the symbol wouldn't. */ + constrain_symbol_p = FALSE; break; case R_MIPS_32: @@ -8062,51 +8294,41 @@ _bfd_mips_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, can_make_dynamic_p = TRUE; if (dynobj == NULL) elf_hash_table (info)->dynobj = dynobj = abfd; - break; } - /* For sections that are not SEC_ALLOC a copy reloc would be - output if possible (implying questionable semantics for - read-only data objects) or otherwise the final link would - fail as ld.so will not process them and could not therefore - handle any outstanding dynamic relocations. - - For such sections that are also SEC_DEBUGGING, we can avoid - these problems by simply ignoring any relocs as these - sections have a predefined use and we know it is safe to do - so. - - This is needed in cases such as a global symbol definition - in a shared library causing a common symbol from an object - file to be converted to an undefined reference. If that - happens, then all the relocations against this symbol from - SEC_DEBUGGING sections in the object file will resolve to - nil. */ - if ((sec->flags & SEC_DEBUGGING) != 0) - break; - /* Fall through. */ - - default: - /* Most static relocations require pointer equality, except - for branches. */ - if (h) - h->pointer_equality_needed = TRUE; - /* Fall through. */ + break; case R_MIPS_26: case R_MIPS_PC16: + case R_MIPS_PC21_S2: + case R_MIPS_PC26_S2: case R_MIPS16_26: case R_MICROMIPS_26_S1: case R_MICROMIPS_PC7_S1: case R_MICROMIPS_PC10_S1: case R_MICROMIPS_PC16_S1: case R_MICROMIPS_PC23_S2: - if (h) - ((struct mips_elf_link_hash_entry *) h)->has_static_relocs = TRUE; + call_reloc_p = TRUE; break; } if (h) { + if (constrain_symbol_p) + { + if (!can_make_dynamic_p) + ((struct mips_elf_link_hash_entry *) h)->has_static_relocs = 1; + + if (!call_reloc_p) + h->pointer_equality_needed = 1; + + /* We must not create a stub for a symbol that has + relocations related to taking the function's address. + This doesn't apply to VxWorks, where CALL relocs refer + to a .got.plt entry instead of a normal .got entry. */ + if (!htab->is_vxworks && (!can_make_dynamic_p || !call_reloc_p)) + ((struct mips_elf_link_hash_entry *) h)->no_fn_stub = TRUE; + } + /* Relocations against the special VxWorks __GOTT_BASE__ and __GOTT_INDEX__ symbols must be left to the loader. Allocate room for them in .rela.dyn. */ @@ -8387,28 +8609,6 @@ _bfd_mips_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, h->plt.plist->need_comp = TRUE; } - /* We must not create a stub for a symbol that has relocations - related to taking the function's address. This doesn't apply to - VxWorks, where CALL relocs refer to a .got.plt entry instead of - a normal .got entry. */ - if (!htab->is_vxworks && h != NULL) - switch (r_type) - { - default: - ((struct mips_elf_link_hash_entry *) h)->no_fn_stub = TRUE; - break; - case R_MIPS16_CALL16: - case R_MIPS_CALL16: - case R_MIPS_CALL_HI16: - case R_MIPS_CALL_LO16: - case R_MIPS_JALR: - case R_MICROMIPS_CALL16: - case R_MICROMIPS_CALL_HI16: - case R_MICROMIPS_CALL_LO16: - case R_MICROMIPS_JALR: - break; - } - /* See if this reloc would need to refer to a MIPS16 hard-float stub, if there is one. We only need to handle global symbols here; we decide whether to keep or delete stubs for local symbols @@ -8997,7 +9197,7 @@ bfd_boolean _bfd_mips_elf_always_size_sections (bfd *output_bfd, struct bfd_link_info *info) { - asection *ri; + asection *sect; struct mips_elf_link_hash_table *htab; struct mips_htab_traverse_info hti; @@ -9005,9 +9205,14 @@ _bfd_mips_elf_always_size_sections (bfd *output_bfd, BFD_ASSERT (htab != NULL); /* The .reginfo section has a fixed size. */ - ri = bfd_get_section_by_name (output_bfd, ".reginfo"); - if (ri != NULL) - bfd_set_section_size (output_bfd, ri, sizeof (Elf32_External_RegInfo)); + sect = bfd_get_section_by_name (output_bfd, ".reginfo"); + if (sect != NULL) + bfd_set_section_size (output_bfd, sect, sizeof (Elf32_External_RegInfo)); + + /* The .MIPS.abiflags section has a fixed size. */ + sect = bfd_get_section_by_name (output_bfd, ".MIPS.abiflags"); + if (sect != NULL) + bfd_set_section_size (output_bfd, sect, sizeof (Elf_External_ABIFlags_v0)); hti.info = info; hti.output_bfd = output_bfd; @@ -9046,13 +9251,13 @@ mips_elf_lay_out_got (bfd *output_bfd, struct bfd_link_info *info) /* Allocate room for the reserved entries. VxWorks always reserves 3 entries; other objects only reserve 2 entries. */ - BFD_ASSERT (g->assigned_gotno == 0); + BFD_ASSERT (g->assigned_low_gotno == 0); if (htab->is_vxworks) htab->reserved_gotno = 3; else htab->reserved_gotno = 2; g->local_gotno += htab->reserved_gotno; - g->assigned_gotno = htab->reserved_gotno; + g->assigned_low_gotno = htab->reserved_gotno; /* Decide which symbols need to go in the global part of the GOT and count the number of reloc-only GOT symbols. */ @@ -9095,6 +9300,7 @@ mips_elf_lay_out_got (bfd *output_bfd, struct bfd_link_info *info) page_gotno = g->page_gotno; g->local_gotno += page_gotno; + g->assigned_high_gotno = g->local_gotno - 1; s->size += g->local_gotno * MIPS_ELF_GOT_SIZE (output_bfd); s->size += g->global_gotno * MIPS_ELF_GOT_SIZE (output_bfd); @@ -10019,6 +10225,13 @@ _bfd_mips_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, (info, msg, name, input_bfd, input_section, rel->r_offset); return FALSE; } + if (aligned_pcrel_reloc_p (howto->type)) + { + msg = _("PC-relative load from unaligned address"); + info->callbacks->warning + (info, msg, name, input_bfd, input_section, rel->r_offset); + return FALSE; + } /* Fall through. */ default: @@ -10308,7 +10521,11 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd, load = MIPS_ELF_LOAD_WORD (output_bfd); /* Fill in the PLT entry itself. */ - plt_entry = mips_exec_plt_entry; + + if (MIPSR6_P (output_bfd)) + plt_entry = mipsr6_exec_plt_entry; + else + plt_entry = mips_exec_plt_entry; bfd_put_32 (output_bfd, plt_entry[0] | got_address_high, loc); bfd_put_32 (output_bfd, plt_entry[1] | got_address_low | load, loc + 4); @@ -11369,10 +11586,14 @@ _bfd_mips_elf_finish_dynamic_sections (bfd *output_bfd, if (! info->shared) continue; - while (got_index < g->assigned_gotno) + for (; got_index < g->local_gotno; got_index++) { + if (got_index >= g->assigned_low_gotno + && got_index <= g->assigned_high_gotno) + continue; + rel[0].r_offset = rel[1].r_offset = rel[2].r_offset - = got_index++ * MIPS_ELF_GOT_SIZE (output_bfd); + = got_index * MIPS_ELF_GOT_SIZE (output_bfd); if (!(mips_elf_create_dynamic_relocation (output_bfd, info, rel, NULL, bfd_abs_section_ptr, @@ -11606,7 +11827,7 @@ mips_set_isa_flags (bfd *abfd) break; case bfd_mach_mips_loongson_3a: - val = E_MIPS_ARCH_64 | E_MIPS_MACH_LS3A; + val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_LS3A; break; case bfd_mach_mips_octeon: @@ -11631,12 +11852,24 @@ mips_set_isa_flags (bfd *abfd) break; case bfd_mach_mipsisa32r2: + case bfd_mach_mipsisa32r3: + case bfd_mach_mipsisa32r5: val = E_MIPS_ARCH_32R2; break; case bfd_mach_mipsisa64r2: + case bfd_mach_mipsisa64r3: + case bfd_mach_mipsisa64r5: val = E_MIPS_ARCH_64R2; break; + + case bfd_mach_mipsisa32r6: + val = E_MIPS_ARCH_32R6; + break; + + case bfd_mach_mipsisa64r6: + val = E_MIPS_ARCH_64R6; + break; } elf_elfheader (abfd)->e_flags &= ~(EF_MIPS_ARCH | EF_MIPS_MACH); elf_elfheader (abfd)->e_flags |= val; @@ -11745,6 +11978,10 @@ _bfd_mips_elf_additional_program_headers (bfd *abfd, if (s && (s->flags & SEC_LOAD)) ++ret; + /* See if we need a PT_MIPS_ABIFLAGS segment. */ + if (bfd_get_section_by_name (abfd, ".MIPS.abiflags")) + ++ret; + /* See if we need a PT_MIPS_OPTIONS segment. */ if (IRIX_COMPAT (abfd) == ict_irix6 && bfd_get_section_by_name (abfd, @@ -11807,6 +12044,37 @@ _bfd_mips_elf_modify_segment_map (bfd *abfd, } } + /* If there is a .MIPS.abiflags section, we need a PT_MIPS_ABIFLAGS + segment. */ + s = bfd_get_section_by_name (abfd, ".MIPS.abiflags"); + if (s != NULL && (s->flags & SEC_LOAD) != 0) + { + for (m = elf_seg_map (abfd); m != NULL; m = m->next) + if (m->p_type == PT_MIPS_ABIFLAGS) + break; + if (m == NULL) + { + amt = sizeof *m; + m = bfd_zalloc (abfd, amt); + if (m == NULL) + return FALSE; + + m->p_type = PT_MIPS_ABIFLAGS; + m->count = 1; + m->sections[0] = s; + + /* We want to put it after the PHDR and INTERP segments. */ + pm = &elf_seg_map (abfd); + while (*pm != NULL + && ((*pm)->p_type == PT_PHDR + || (*pm)->p_type == PT_INTERP)) + pm = &(*pm)->next; + + m->next = *pm; + *pm = m; + } + } + /* For IRIX 6, we don't have .mdebug sections, nor does anything but .dynamic end up in PT_DYNAMIC. However, we do have to insert a PT_MIPS_OPTIONS segment immediately following the program header @@ -11901,18 +12169,6 @@ _bfd_mips_elf_modify_segment_map (bfd *abfd, if ((*pm)->p_type == PT_DYNAMIC) break; m = *pm; - if (m != NULL && IRIX_COMPAT (abfd) == ict_none) - { - /* For a normal mips executable the permissions for the PT_DYNAMIC - segment are read, write and execute. We do that here since - the code in elf.c sets only the read permission. This matters - sometimes for the dynamic linker. */ - if (bfd_get_section_by_name (abfd, ".dynamic") != NULL) - { - m->p_flags = PF_R | PF_W | PF_X; - m->p_flags_valid = 1; - } - } /* GNU/Linux binaries do not need the extended PT_DYNAMIC section. glibc's dynamic linker has traditionally derived the number of tags from the p_filesz field, and sometimes allocates stack @@ -12102,6 +12358,36 @@ _bfd_mips_elf_gc_sweep_hook (bfd *abfd ATTRIBUTE_UNUSED, return TRUE; } + +/* Prevent .MIPS.abiflags from being discarded with --gc-sections. */ + +bfd_boolean +_bfd_mips_elf_gc_mark_extra_sections (struct bfd_link_info *info, + elf_gc_mark_hook_fn gc_mark_hook) +{ + bfd *sub; + + _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook); + + for (sub = info->input_bfds; sub != NULL; sub = sub->link_next) + { + asection *o; + + if (! is_mips_elf (sub)) + continue; + + for (o = sub->sections; o != NULL; o = o->next) + if (!o->gc_mark + && MIPS_ELF_ABIFLAGS_SECTION_NAME_P + (bfd_get_section_name (sub, o))) + { + if (!_bfd_elf_gc_mark (info, o, gc_mark_hook)) + return FALSE; + } + } + + return TRUE; +} /* Copy data from a MIPS ELF indirect symbol to its direct symbol, hiding the old indirect symbol. Process additional relocation @@ -13552,6 +13838,177 @@ _bfd_mips_elf_insn32 (struct bfd_link_info *info, bfd_boolean on) mips_elf_hash_table (info)->insn32 = on; } +/* Return the .MIPS.abiflags value representing each ISA Extension. */ + +unsigned int +bfd_mips_isa_ext (bfd *abfd) +{ + switch (bfd_get_mach (abfd)) + { + case bfd_mach_mips3900: + return AFL_EXT_3900; + case bfd_mach_mips4010: + return AFL_EXT_4010; + case bfd_mach_mips4100: + return AFL_EXT_4100; + case bfd_mach_mips4111: + return AFL_EXT_4111; + case bfd_mach_mips4120: + return AFL_EXT_4120; + case bfd_mach_mips4650: + return AFL_EXT_4650; + case bfd_mach_mips5400: + return AFL_EXT_5400; + case bfd_mach_mips5500: + return AFL_EXT_5500; + case bfd_mach_mips5900: + return AFL_EXT_5900; + case bfd_mach_mips10000: + return AFL_EXT_10000; + case bfd_mach_mips_loongson_2e: + return AFL_EXT_LOONGSON_2E; + case bfd_mach_mips_loongson_2f: + return AFL_EXT_LOONGSON_2F; + case bfd_mach_mips_loongson_3a: + return AFL_EXT_LOONGSON_3A; + case bfd_mach_mips_sb1: + return AFL_EXT_SB1; + case bfd_mach_mips_octeon: + return AFL_EXT_OCTEON; + case bfd_mach_mips_octeonp: + return AFL_EXT_OCTEONP; + case bfd_mach_mips_octeon2: + return AFL_EXT_OCTEON2; + case bfd_mach_mips_xlr: + return AFL_EXT_XLR; + } + return 0; +} + +/* Update the isa_level, isa_rev, isa_ext fields of abiflags. */ + +static void +update_mips_abiflags_isa (bfd *abfd, Elf_Internal_ABIFlags_v0 *abiflags) +{ + switch (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) + { + case E_MIPS_ARCH_1: + abiflags->isa_level = 1; + abiflags->isa_rev = 0; + break; + case E_MIPS_ARCH_2: + abiflags->isa_level = 2; + abiflags->isa_rev = 0; + break; + case E_MIPS_ARCH_3: + abiflags->isa_level = 3; + abiflags->isa_rev = 0; + break; + case E_MIPS_ARCH_4: + abiflags->isa_level = 4; + abiflags->isa_rev = 0; + break; + case E_MIPS_ARCH_5: + abiflags->isa_level = 5; + abiflags->isa_rev = 0; + break; + case E_MIPS_ARCH_32: + abiflags->isa_level = 32; + abiflags->isa_rev = 1; + break; + case E_MIPS_ARCH_32R2: + abiflags->isa_level = 32; + /* Handle MIPS32r3 and MIPS32r5 which do not have a header flag. */ + if (abiflags->isa_rev < 2) + abiflags->isa_rev = 2; + break; + case E_MIPS_ARCH_32R6: + abiflags->isa_level = 32; + abiflags->isa_rev = 6; + break; + case E_MIPS_ARCH_64: + abiflags->isa_level = 64; + abiflags->isa_rev = 1; + break; + case E_MIPS_ARCH_64R2: + /* Handle MIPS64r3 and MIPS64r5 which do not have a header flag. */ + abiflags->isa_level = 64; + if (abiflags->isa_rev < 2) + abiflags->isa_rev = 2; + break; + case E_MIPS_ARCH_64R6: + abiflags->isa_level = 64; + abiflags->isa_rev = 6; + break; + default: + (*_bfd_error_handler) + (_("%B: Unknown architecture %s"), + abfd, bfd_printable_name (abfd)); + } + + abiflags->isa_ext = bfd_mips_isa_ext (abfd); +} + +/* Return true if the given ELF header flags describe a 32-bit binary. */ + +static bfd_boolean +mips_32bit_flags_p (flagword flags) +{ + return ((flags & EF_MIPS_32BITMODE) != 0 + || (flags & EF_MIPS_ABI) == E_MIPS_ABI_O32 + || (flags & EF_MIPS_ABI) == E_MIPS_ABI_EABI32 + || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_1 + || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_2 + || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32 + || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R2 + || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R6); +} + +/* Infer the content of the ABI flags based on the elf header. */ + +static void +infer_mips_abiflags (bfd *abfd, Elf_Internal_ABIFlags_v0* abiflags) +{ + obj_attribute *in_attr; + + memset (abiflags, 0, sizeof (Elf_Internal_ABIFlags_v0)); + update_mips_abiflags_isa (abfd, abiflags); + + if (mips_32bit_flags_p (elf_elfheader (abfd)->e_flags)) + abiflags->gpr_size = AFL_REG_32; + else + abiflags->gpr_size = AFL_REG_64; + + abiflags->cpr1_size = AFL_REG_NONE; + + in_attr = elf_known_obj_attributes (abfd)[OBJ_ATTR_GNU]; + abiflags->fp_abi = in_attr[Tag_GNU_MIPS_ABI_FP].i; + + if (abiflags->fp_abi == Val_GNU_MIPS_ABI_FP_SINGLE + || abiflags->fp_abi == Val_GNU_MIPS_ABI_FP_XX + || (abiflags->fp_abi == Val_GNU_MIPS_ABI_FP_DOUBLE + && abiflags->gpr_size == AFL_REG_32)) + abiflags->cpr1_size = AFL_REG_32; + else if (abiflags->fp_abi == Val_GNU_MIPS_ABI_FP_DOUBLE + || abiflags->fp_abi == Val_GNU_MIPS_ABI_FP_64 + || abiflags->fp_abi == Val_GNU_MIPS_ABI_FP_64A) + abiflags->cpr1_size = AFL_REG_64; + + abiflags->cpr2_size = AFL_REG_NONE; + + if (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH_ASE_MDMX) + abiflags->ases |= AFL_ASE_MDMX; + if (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH_ASE_M16) + abiflags->ases |= AFL_ASE_MIPS16; + if (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) + abiflags->ases |= AFL_ASE_MICROMIPS; + + if (abiflags->fp_abi != Val_GNU_MIPS_ABI_FP_ANY + && abiflags->fp_abi != Val_GNU_MIPS_ABI_FP_SOFT + && abiflags->fp_abi != Val_GNU_MIPS_ABI_FP_64A) + abiflags->flags1 |= AFL_FLAGS1_ODDSPREG; +} + /* We need to use a special link routine to handle the .reginfo and the .mdebug sections. We need to merge all instances of these sections together, not write them all out sequentially. */ @@ -13562,7 +14019,7 @@ _bfd_mips_elf_final_link (bfd *abfd, struct bfd_link_info *info) asection *o; struct bfd_link_order *p; asection *reginfo_sec, *mdebug_sec, *gptab_data_sec, *gptab_bss_sec; - asection *rtproc_sec; + asection *rtproc_sec, *abiflags_sec; Elf32_RegInfo reginfo; struct ecoff_debug_info debug; struct mips_htab_traverse_info hti; @@ -13644,12 +14101,46 @@ _bfd_mips_elf_final_link (bfd *abfd, struct bfd_link_info *info) /* Go through the sections and collect the .reginfo and .mdebug information. */ + abiflags_sec = NULL; reginfo_sec = NULL; mdebug_sec = NULL; gptab_data_sec = NULL; gptab_bss_sec = NULL; for (o = abfd->sections; o != NULL; o = o->next) { + if (strcmp (o->name, ".MIPS.abiflags") == 0) + { + /* We have found the .MIPS.abiflags section in the output file. + Look through all the link_orders comprising it and remove them. + The data is merged in _bfd_mips_elf_merge_private_bfd_data. */ + for (p = o->map_head.link_order; p != NULL; p = p->next) + { + asection *input_section; + + if (p->type != bfd_indirect_link_order) + { + if (p->type == bfd_data_link_order) + continue; + abort (); + } + + input_section = p->u.indirect.section; + + /* Hack: reset the SEC_HAS_CONTENTS flag so that + elf_link_input_bfd ignores this section. */ + input_section->flags &= ~SEC_HAS_CONTENTS; + } + + /* Size has been set in _bfd_mips_elf_always_size_sections. */ + BFD_ASSERT(o->size == sizeof (Elf_External_ABIFlags_v0)); + + /* Skip this section later on (I don't think this currently + matters, but someday it might). */ + o->map_head.link_order = NULL; + + abiflags_sec = o; + } + if (strcmp (o->name, ".reginfo") == 0) { memset (®info, 0, sizeof reginfo); @@ -14134,6 +14625,24 @@ _bfd_mips_elf_final_link (bfd *abfd, struct bfd_link_info *info) /* Now write out the computed sections. */ + if (abiflags_sec != NULL) + { + Elf_External_ABIFlags_v0 ext; + Elf_Internal_ABIFlags_v0 *abiflags; + + abiflags = &mips_elf_tdata (abfd)->abiflags; + + /* Set up the abiflags if no valid input sections were found. */ + if (!mips_elf_tdata (abfd)->abiflags_valid) + { + infer_mips_abiflags (abfd, abiflags); + mips_elf_tdata (abfd)->abiflags_valid = TRUE; + } + bfd_mips_elf_swap_abiflags_v0_out (abfd, abiflags, &ext); + if (! bfd_set_section_contents (abfd, abiflags_sec, &ext, 0, sizeof ext)) + return FALSE; + } + if (reginfo_sec != NULL) { Elf32_External_RegInfo ext; @@ -14202,12 +14711,12 @@ static const struct mips_mach_extension mips_mach_extensions[] = { bfd_mach_mips_octeon2, bfd_mach_mips_octeonp }, { bfd_mach_mips_octeonp, bfd_mach_mips_octeon }, { bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 }, + { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64r2 }, /* MIPS64 extensions. */ { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 }, { bfd_mach_mips_sb1, bfd_mach_mipsisa64 }, { bfd_mach_mips_xlr, bfd_mach_mipsisa64 }, - { bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64 }, /* MIPS V extensions. */ { bfd_mach_mipsisa64, bfd_mach_mips5 }, @@ -14291,21 +14800,6 @@ mips_mach_extends_p (unsigned long base, unsigned long extension) } -/* Return true if the given ELF header flags describe a 32-bit binary. */ - -static bfd_boolean -mips_32bit_flags_p (flagword flags) -{ - return ((flags & EF_MIPS_32BITMODE) != 0 - || (flags & EF_MIPS_ABI) == E_MIPS_ABI_O32 - || (flags & EF_MIPS_ABI) == E_MIPS_ABI_EABI32 - || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_1 - || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_2 - || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32 - || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R2); -} - - /* Merge object attributes from IBFD into OBFD. Raise an error if there are conflicting attributes. */ static bfd_boolean @@ -14314,12 +14808,18 @@ mips_elf_merge_obj_attributes (bfd *ibfd, bfd *obfd) obj_attribute *in_attr; obj_attribute *out_attr; bfd *abi_fp_bfd; + bfd *abi_msa_bfd; abi_fp_bfd = mips_elf_tdata (obfd)->abi_fp_bfd; in_attr = elf_known_obj_attributes (ibfd)[OBJ_ATTR_GNU]; if (!abi_fp_bfd && in_attr[Tag_GNU_MIPS_ABI_FP].i != Val_GNU_MIPS_ABI_FP_ANY) mips_elf_tdata (obfd)->abi_fp_bfd = ibfd; + abi_msa_bfd = mips_elf_tdata (obfd)->abi_msa_bfd; + if (!abi_msa_bfd + && in_attr[Tag_GNU_MIPS_ABI_MSA].i != Val_GNU_MIPS_ABI_MSA_ANY) + mips_elf_tdata (obfd)->abi_msa_bfd = ibfd; + if (!elf_known_obj_attributes_proc (obfd)[0].i) { /* This is the first object. Copy the attributes. */ @@ -14337,175 +14837,111 @@ mips_elf_merge_obj_attributes (bfd *ibfd, bfd *obfd) out_attr = elf_known_obj_attributes (obfd)[OBJ_ATTR_GNU]; if (in_attr[Tag_GNU_MIPS_ABI_FP].i != out_attr[Tag_GNU_MIPS_ABI_FP].i) { - out_attr[Tag_GNU_MIPS_ABI_FP].type = 1; - if (out_attr[Tag_GNU_MIPS_ABI_FP].i == Val_GNU_MIPS_ABI_FP_ANY) - out_attr[Tag_GNU_MIPS_ABI_FP].i = in_attr[Tag_GNU_MIPS_ABI_FP].i; - else if (in_attr[Tag_GNU_MIPS_ABI_FP].i != Val_GNU_MIPS_ABI_FP_ANY) - switch (out_attr[Tag_GNU_MIPS_ABI_FP].i) - { - case Val_GNU_MIPS_ABI_FP_DOUBLE: - switch (in_attr[Tag_GNU_MIPS_ABI_FP].i) - { - case Val_GNU_MIPS_ABI_FP_SINGLE: - _bfd_error_handler - (_("Warning: %B uses %s (set by %B), %B uses %s"), - obfd, abi_fp_bfd, ibfd, "-mdouble-float", "-msingle-float"); - break; + int out_fp, in_fp; - case Val_GNU_MIPS_ABI_FP_SOFT: - _bfd_error_handler - (_("Warning: %B uses %s (set by %B), %B uses %s"), - obfd, abi_fp_bfd, ibfd, "-mhard-float", "-msoft-float"); - break; - - case Val_GNU_MIPS_ABI_FP_64: - _bfd_error_handler - (_("Warning: %B uses %s (set by %B), %B uses %s"), - obfd, abi_fp_bfd, ibfd, - "-mdouble-float", "-mips32r2 -mfp64"); - break; - - default: - _bfd_error_handler - (_("Warning: %B uses %s (set by %B), " - "%B uses unknown floating point ABI %d"), - obfd, abi_fp_bfd, ibfd, - "-mdouble-float", in_attr[Tag_GNU_MIPS_ABI_FP].i); - break; - } - break; - - case Val_GNU_MIPS_ABI_FP_SINGLE: - switch (in_attr[Tag_GNU_MIPS_ABI_FP].i) - { - case Val_GNU_MIPS_ABI_FP_DOUBLE: - _bfd_error_handler - (_("Warning: %B uses %s (set by %B), %B uses %s"), - obfd, abi_fp_bfd, ibfd, "-msingle-float", "-mdouble-float"); - break; - - case Val_GNU_MIPS_ABI_FP_SOFT: - _bfd_error_handler - (_("Warning: %B uses %s (set by %B), %B uses %s"), - obfd, abi_fp_bfd, ibfd, "-mhard-float", "-msoft-float"); - break; - - case Val_GNU_MIPS_ABI_FP_64: - _bfd_error_handler - (_("Warning: %B uses %s (set by %B), %B uses %s"), - obfd, abi_fp_bfd, ibfd, - "-msingle-float", "-mips32r2 -mfp64"); - break; - - default: - _bfd_error_handler - (_("Warning: %B uses %s (set by %B), " - "%B uses unknown floating point ABI %d"), - obfd, abi_fp_bfd, ibfd, - "-msingle-float", in_attr[Tag_GNU_MIPS_ABI_FP].i); - break; - } - break; - - case Val_GNU_MIPS_ABI_FP_SOFT: - switch (in_attr[Tag_GNU_MIPS_ABI_FP].i) - { - case Val_GNU_MIPS_ABI_FP_DOUBLE: - case Val_GNU_MIPS_ABI_FP_SINGLE: - case Val_GNU_MIPS_ABI_FP_64: - _bfd_error_handler - (_("Warning: %B uses %s (set by %B), %B uses %s"), - obfd, abi_fp_bfd, ibfd, "-msoft-float", "-mhard-float"); - break; - - default: - _bfd_error_handler - (_("Warning: %B uses %s (set by %B), " - "%B uses unknown floating point ABI %d"), - obfd, abi_fp_bfd, ibfd, - "-msoft-float", in_attr[Tag_GNU_MIPS_ABI_FP].i); - break; - } - break; - - case Val_GNU_MIPS_ABI_FP_64: - switch (in_attr[Tag_GNU_MIPS_ABI_FP].i) - { - case Val_GNU_MIPS_ABI_FP_DOUBLE: - _bfd_error_handler - (_("Warning: %B uses %s (set by %B), %B uses %s"), - obfd, abi_fp_bfd, ibfd, - "-mips32r2 -mfp64", "-mdouble-float"); - break; - - case Val_GNU_MIPS_ABI_FP_SINGLE: - _bfd_error_handler - (_("Warning: %B uses %s (set by %B), %B uses %s"), - obfd, abi_fp_bfd, ibfd, - "-mips32r2 -mfp64", "-msingle-float"); - break; - - case Val_GNU_MIPS_ABI_FP_SOFT: - _bfd_error_handler - (_("Warning: %B uses %s (set by %B), %B uses %s"), - obfd, abi_fp_bfd, ibfd, "-mhard-float", "-msoft-float"); - break; + out_fp = out_attr[Tag_GNU_MIPS_ABI_FP].i; + in_fp = in_attr[Tag_GNU_MIPS_ABI_FP].i; + out_attr[Tag_GNU_MIPS_ABI_FP].type = 1; + if (out_fp == Val_GNU_MIPS_ABI_FP_ANY) + out_attr[Tag_GNU_MIPS_ABI_FP].i = in_fp; + else if (out_fp == Val_GNU_MIPS_ABI_FP_XX + && (in_fp == Val_GNU_MIPS_ABI_FP_DOUBLE + || in_fp == Val_GNU_MIPS_ABI_FP_64 + || in_fp == Val_GNU_MIPS_ABI_FP_64A)) + { + mips_elf_tdata (obfd)->abi_fp_bfd = ibfd; + out_attr[Tag_GNU_MIPS_ABI_FP].i = in_attr[Tag_GNU_MIPS_ABI_FP].i; + } + else if (in_fp == Val_GNU_MIPS_ABI_FP_XX + && (out_fp == Val_GNU_MIPS_ABI_FP_DOUBLE + || out_fp == Val_GNU_MIPS_ABI_FP_64 + || out_fp == Val_GNU_MIPS_ABI_FP_64A)) + /* Keep the current setting. */; + else if (out_fp == Val_GNU_MIPS_ABI_FP_64A + && in_fp == Val_GNU_MIPS_ABI_FP_64) + { + mips_elf_tdata (obfd)->abi_fp_bfd = ibfd; + out_attr[Tag_GNU_MIPS_ABI_FP].i = in_attr[Tag_GNU_MIPS_ABI_FP].i; + } + else if (in_fp == Val_GNU_MIPS_ABI_FP_64A + && out_fp == Val_GNU_MIPS_ABI_FP_64) + /* Keep the current setting. */; + else if (in_fp != Val_GNU_MIPS_ABI_FP_ANY) + { + const char *out_string, *in_string; + + out_string = _bfd_mips_fp_abi_string (out_fp); + in_string = _bfd_mips_fp_abi_string (in_fp); + /* First warn about cases involving unrecognised ABIs. */ + if (!out_string && !in_string) + _bfd_error_handler + (_("Warning: %B uses unknown floating point ABI %d " + "(set by %B), %B uses unknown floating point ABI %d"), + obfd, abi_fp_bfd, ibfd, out_fp, in_fp); + else if (!out_string) + _bfd_error_handler + (_("Warning: %B uses unknown floating point ABI %d " + "(set by %B), %B uses %s"), + obfd, abi_fp_bfd, ibfd, out_fp, in_string); + else if (!in_string) + _bfd_error_handler + (_("Warning: %B uses %s (set by %B), " + "%B uses unknown floating point ABI %d"), + obfd, abi_fp_bfd, ibfd, out_string, in_fp); + else + { + /* If one of the bfds is soft-float, the other must be + hard-float. The exact choice of hard-float ABI isn't + really relevant to the error message. */ + if (in_fp == Val_GNU_MIPS_ABI_FP_SOFT) + out_string = "-mhard-float"; + else if (out_fp == Val_GNU_MIPS_ABI_FP_SOFT) + in_string = "-mhard-float"; + _bfd_error_handler + (_("Warning: %B uses %s (set by %B), %B uses %s"), + obfd, abi_fp_bfd, ibfd, out_string, in_string); + } + } + } - default: - _bfd_error_handler - (_("Warning: %B uses %s (set by %B), " - "%B uses unknown floating point ABI %d"), - obfd, abi_fp_bfd, ibfd, - "-mips32r2 -mfp64", in_attr[Tag_GNU_MIPS_ABI_FP].i); - break; - } + /* Check for conflicting Tag_GNU_MIPS_ABI_MSA attributes and merge + non-conflicting ones. */ + if (in_attr[Tag_GNU_MIPS_ABI_MSA].i != out_attr[Tag_GNU_MIPS_ABI_MSA].i) + { + out_attr[Tag_GNU_MIPS_ABI_MSA].type = 1; + if (out_attr[Tag_GNU_MIPS_ABI_MSA].i == Val_GNU_MIPS_ABI_MSA_ANY) + out_attr[Tag_GNU_MIPS_ABI_MSA].i = in_attr[Tag_GNU_MIPS_ABI_MSA].i; + else if (in_attr[Tag_GNU_MIPS_ABI_MSA].i != Val_GNU_MIPS_ABI_MSA_ANY) + switch (out_attr[Tag_GNU_MIPS_ABI_MSA].i) + { + case Val_GNU_MIPS_ABI_MSA_128: + _bfd_error_handler + (_("Warning: %B uses %s (set by %B), " + "%B uses unknown MSA ABI %d"), + obfd, abi_msa_bfd, ibfd, + "-mmsa", in_attr[Tag_GNU_MIPS_ABI_MSA].i); break; default: - switch (in_attr[Tag_GNU_MIPS_ABI_FP].i) + switch (in_attr[Tag_GNU_MIPS_ABI_MSA].i) { - case Val_GNU_MIPS_ABI_FP_DOUBLE: - _bfd_error_handler - (_("Warning: %B uses unknown floating point ABI %d " - "(set by %B), %B uses %s"), - obfd, abi_fp_bfd, ibfd, - out_attr[Tag_GNU_MIPS_ABI_FP].i, "-mdouble-float"); - break; - - case Val_GNU_MIPS_ABI_FP_SINGLE: + case Val_GNU_MIPS_ABI_MSA_128: _bfd_error_handler - (_("Warning: %B uses unknown floating point ABI %d " + (_("Warning: %B uses unknown MSA ABI %d " "(set by %B), %B uses %s"), - obfd, abi_fp_bfd, ibfd, - out_attr[Tag_GNU_MIPS_ABI_FP].i, "-msingle-float"); - break; - - case Val_GNU_MIPS_ABI_FP_SOFT: - _bfd_error_handler - (_("Warning: %B uses unknown floating point ABI %d " - "(set by %B), %B uses %s"), - obfd, abi_fp_bfd, ibfd, - out_attr[Tag_GNU_MIPS_ABI_FP].i, "-msoft-float"); - break; - - case Val_GNU_MIPS_ABI_FP_64: - _bfd_error_handler - (_("Warning: %B uses unknown floating point ABI %d " - "(set by %B), %B uses %s"), - obfd, abi_fp_bfd, ibfd, - out_attr[Tag_GNU_MIPS_ABI_FP].i, "-mips32r2 -mfp64"); - break; + obfd, abi_msa_bfd, ibfd, + out_attr[Tag_GNU_MIPS_ABI_MSA].i, "-mmsa"); + break; default: _bfd_error_handler - (_("Warning: %B uses unknown floating point ABI %d " - "(set by %B), %B uses unknown floating point ABI %d"), - obfd, abi_fp_bfd, ibfd, - out_attr[Tag_GNU_MIPS_ABI_FP].i, - in_attr[Tag_GNU_MIPS_ABI_FP].i); + (_("Warning: %B uses unknown MSA ABI %d " + "(set by %B), %B uses unknown MSA ABI %d"), + obfd, abi_msa_bfd, ibfd, + out_attr[Tag_GNU_MIPS_ABI_MSA].i, + in_attr[Tag_GNU_MIPS_ABI_MSA].i); break; } - break; } } @@ -14526,6 +14962,7 @@ _bfd_mips_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) bfd_boolean ok; bfd_boolean null_input_bfd = TRUE; asection *sec; + obj_attribute *out_attr; /* Check if we have the same endianness. */ if (! _bfd_generic_verify_endian_match (ibfd, obfd)) @@ -14547,17 +14984,98 @@ _bfd_mips_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) return FALSE; } + /* Set up the FP ABI attribute from the abiflags if it is not already + set. */ + if (mips_elf_tdata (ibfd)->abiflags_valid) + { + obj_attribute *in_attr = elf_known_obj_attributes (ibfd)[OBJ_ATTR_GNU]; + if (in_attr[Tag_GNU_MIPS_ABI_FP].i == Val_GNU_MIPS_ABI_FP_ANY) + in_attr[Tag_GNU_MIPS_ABI_FP].i = + mips_elf_tdata (ibfd)->abiflags.fp_abi; + } + if (!mips_elf_merge_obj_attributes (ibfd, obfd)) return FALSE; - new_flags = elf_elfheader (ibfd)->e_flags; - elf_elfheader (obfd)->e_flags |= new_flags & EF_MIPS_NOREORDER; - old_flags = elf_elfheader (obfd)->e_flags; + /* Check to see if the input BFD actually contains any sections. + If not, its flags may not have been initialised either, but it cannot + actually cause any incompatibility. */ + for (sec = ibfd->sections; sec != NULL; sec = sec->next) + { + /* Ignore synthetic sections and empty .text, .data and .bss sections + which are automatically generated by gas. Also ignore fake + (s)common sections, since merely defining a common symbol does + not affect compatibility. */ + if ((sec->flags & SEC_IS_COMMON) == 0 + && strcmp (sec->name, ".reginfo") + && strcmp (sec->name, ".mdebug") + && (sec->size != 0 + || (strcmp (sec->name, ".text") + && strcmp (sec->name, ".data") + && strcmp (sec->name, ".bss")))) + { + null_input_bfd = FALSE; + break; + } + } + if (null_input_bfd) + return TRUE; + + /* Populate abiflags using existing information. */ + if (!mips_elf_tdata (ibfd)->abiflags_valid) + { + infer_mips_abiflags (ibfd, &mips_elf_tdata (ibfd)->abiflags); + mips_elf_tdata (ibfd)->abiflags_valid = TRUE; + } + else + { + Elf_Internal_ABIFlags_v0 abiflags; + Elf_Internal_ABIFlags_v0 in_abiflags; + infer_mips_abiflags (ibfd, &abiflags); + in_abiflags = mips_elf_tdata (ibfd)->abiflags; + + /* It is not possible to infer the correct ISA revision + for R3 or R5 so drop down to R2 for the checks. */ + if (in_abiflags.isa_rev == 3 || in_abiflags.isa_rev == 5) + in_abiflags.isa_rev = 2; + + if (in_abiflags.isa_level != abiflags.isa_level + || in_abiflags.isa_rev != abiflags.isa_rev + || in_abiflags.isa_ext != abiflags.isa_ext) + (*_bfd_error_handler) + (_("%B: warning: Inconsistent ISA between e_flags and " + ".MIPS.abiflags"), ibfd); + if (abiflags.fp_abi != Val_GNU_MIPS_ABI_FP_ANY + && in_abiflags.fp_abi != abiflags.fp_abi) + (*_bfd_error_handler) + (_("%B: warning: Inconsistent FP ABI between e_flags and " + ".MIPS.abiflags"), ibfd); + if ((in_abiflags.ases & abiflags.ases) != abiflags.ases) + (*_bfd_error_handler) + (_("%B: warning: Inconsistent ASEs between e_flags and " + ".MIPS.abiflags"), ibfd); + if (in_abiflags.isa_ext != abiflags.isa_ext) + (*_bfd_error_handler) + (_("%B: warning: Inconsistent ISA extensions between e_flags and " + ".MIPS.abiflags"), ibfd); + if (in_abiflags.flags2 != 0) + (*_bfd_error_handler) + (_("%B: warning: Unexpected flag in the flags2 field of " + ".MIPS.abiflags (0x%lx)"), ibfd, + (unsigned long) in_abiflags.flags2); + } + + if (!mips_elf_tdata (obfd)->abiflags_valid) + { + /* Copy input abiflags if output abiflags are not already valid. */ + mips_elf_tdata (obfd)->abiflags = mips_elf_tdata (ibfd)->abiflags; + mips_elf_tdata (obfd)->abiflags_valid = TRUE; + } if (! elf_flags_init (obfd)) { elf_flags_init (obfd) = TRUE; - elf_elfheader (obfd)->e_flags = new_flags; + elf_elfheader (obfd)->e_flags = elf_elfheader (ibfd)->e_flags; elf_elfheader (obfd)->e_ident[EI_CLASS] = elf_elfheader (ibfd)->e_ident[EI_CLASS]; @@ -14569,11 +15087,42 @@ _bfd_mips_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) if (! bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd))) return FALSE; + + /* Update the ABI flags isa_level, isa_rev and isa_ext fields. */ + update_mips_abiflags_isa (obfd, &mips_elf_tdata (obfd)->abiflags); } return TRUE; } + /* Update the output abiflags fp_abi using the computed fp_abi. */ + out_attr = elf_known_obj_attributes (obfd)[OBJ_ATTR_GNU]; + mips_elf_tdata (obfd)->abiflags.fp_abi = out_attr[Tag_GNU_MIPS_ABI_FP].i; + +#define max(a,b) ((a) > (b) ? (a) : (b)) + /* Merge abiflags. */ + mips_elf_tdata (obfd)->abiflags.isa_rev + = max (mips_elf_tdata (obfd)->abiflags.isa_rev, + mips_elf_tdata (ibfd)->abiflags.isa_rev); + mips_elf_tdata (obfd)->abiflags.gpr_size + = max (mips_elf_tdata (obfd)->abiflags.gpr_size, + mips_elf_tdata (ibfd)->abiflags.gpr_size); + mips_elf_tdata (obfd)->abiflags.cpr1_size + = max (mips_elf_tdata (obfd)->abiflags.cpr1_size, + mips_elf_tdata (ibfd)->abiflags.cpr1_size); + mips_elf_tdata (obfd)->abiflags.cpr2_size + = max (mips_elf_tdata (obfd)->abiflags.cpr2_size, + mips_elf_tdata (ibfd)->abiflags.cpr2_size); +#undef max + mips_elf_tdata (obfd)->abiflags.ases + |= mips_elf_tdata (ibfd)->abiflags.ases; + mips_elf_tdata (obfd)->abiflags.flags1 + |= mips_elf_tdata (ibfd)->abiflags.flags1; + + new_flags = elf_elfheader (ibfd)->e_flags; + elf_elfheader (obfd)->e_flags |= new_flags & EF_MIPS_NOREORDER; + old_flags = elf_elfheader (obfd)->e_flags; + /* Check flag compatibility. */ new_flags &= ~EF_MIPS_NOREORDER; @@ -14596,30 +15145,6 @@ _bfd_mips_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) if (new_flags == old_flags) return TRUE; - /* Check to see if the input BFD actually contains any sections. - If not, its flags may not have been initialised either, but it cannot - actually cause any incompatibility. */ - for (sec = ibfd->sections; sec != NULL; sec = sec->next) - { - /* Ignore synthetic sections and empty .text, .data and .bss sections - which are automatically generated by gas. Also ignore fake - (s)common sections, since merely defining a common symbol does - not affect compatibility. */ - if ((sec->flags & SEC_IS_COMMON) == 0 - && strcmp (sec->name, ".reginfo") - && strcmp (sec->name, ".mdebug") - && (sec->size != 0 - || (strcmp (sec->name, ".text") - && strcmp (sec->name, ".data") - && strcmp (sec->name, ".bss")))) - { - null_input_bfd = FALSE; - break; - } - } - if (null_input_bfd) - return TRUE; - ok = TRUE; if (((new_flags & (EF_MIPS_PIC | EF_MIPS_CPIC)) != 0) @@ -14660,6 +15185,9 @@ _bfd_mips_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) elf_elfheader (obfd)->e_flags |= new_flags & (EF_MIPS_ARCH | EF_MIPS_MACH | EF_MIPS_32BITMODE); + /* Update the ABI flags isa_level, isa_rev, isa_ext fields. */ + update_mips_abiflags_isa (obfd, &mips_elf_tdata (obfd)->abiflags); + /* Copy across the ABI flags if OBFD doesn't use them and if that was what caused us to treat IBFD as 32-bit. */ if ((old_flags & EF_MIPS_ABI) == 0 @@ -14745,6 +15273,20 @@ _bfd_mips_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) old_flags &= ~EF_MIPS_NAN2008; } + /* Compare FP64 state. */ + if ((new_flags & EF_MIPS_FP64) != (old_flags & EF_MIPS_FP64)) + { + _bfd_error_handler (_("%B: linking %s module with previous %s modules"), + ibfd, + (new_flags & EF_MIPS_FP64 + ? "-mfp64" : "-mfp32"), + (old_flags & EF_MIPS_FP64 + ? "-mfp64" : "-mfp32")); + ok = FALSE; + new_flags &= ~EF_MIPS_FP64; + old_flags &= ~EF_MIPS_FP64; + } + /* Warn about any other mismatches */ if (new_flags != old_flags) { @@ -14876,6 +15418,188 @@ _bfd_mips_elf_get_target_dtag (bfd_vma dtag) } } +/* Return the meaning of Tag_GNU_MIPS_ABI_FP value FP, or null if + not known. */ + +const char * +_bfd_mips_fp_abi_string (int fp) +{ + switch (fp) + { + /* These strings aren't translated because they're simply + option lists. */ + case Val_GNU_MIPS_ABI_FP_DOUBLE: + return "-mdouble-float"; + + case Val_GNU_MIPS_ABI_FP_SINGLE: + return "-msingle-float"; + + case Val_GNU_MIPS_ABI_FP_SOFT: + return "-msoft-float"; + + case Val_GNU_MIPS_ABI_FP_OLD_64: + return _("-mips32r2 -mfp64 (12 callee-saved)"); + + case Val_GNU_MIPS_ABI_FP_XX: + return "-mfpxx"; + + case Val_GNU_MIPS_ABI_FP_64: + return "-mgp32 -mfp64"; + + case Val_GNU_MIPS_ABI_FP_64A: + return "-mgp32 -mfp64 -mno-odd-spreg"; + + default: + return 0; + } +} + +static void +print_mips_ases (FILE *file, unsigned int mask) +{ + if (mask & AFL_ASE_DSP) + fputs ("\n\tDSP ASE", file); + if (mask & AFL_ASE_DSPR2) + fputs ("\n\tDSP R2 ASE", file); + if (mask & AFL_ASE_EVA) + fputs ("\n\tEnhanced VA Scheme", file); + if (mask & AFL_ASE_MCU) + fputs ("\n\tMCU (MicroController) ASE", file); + if (mask & AFL_ASE_MDMX) + fputs ("\n\tMDMX ASE", file); + if (mask & AFL_ASE_MIPS3D) + fputs ("\n\tMIPS-3D ASE", file); + if (mask & AFL_ASE_MT) + fputs ("\n\tMT ASE", file); + if (mask & AFL_ASE_SMARTMIPS) + fputs ("\n\tSmartMIPS ASE", file); + if (mask & AFL_ASE_VIRT) + fputs ("\n\tVZ ASE", file); + if (mask & AFL_ASE_MSA) + fputs ("\n\tMSA ASE", file); + if (mask & AFL_ASE_MIPS16) + fputs ("\n\tMIPS16 ASE", file); + if (mask & AFL_ASE_MICROMIPS) + fputs ("\n\tMICROMIPS ASE", file); + if (mask & AFL_ASE_XPA) + fputs ("\n\tXPA ASE", file); + if (mask == 0) + fprintf (file, "\n\t%s", _("None")); +} + +static void +print_mips_isa_ext (FILE *file, unsigned int isa_ext) +{ + switch (isa_ext) + { + case 0: + fputs (_("None"), file); + break; + case AFL_EXT_XLR: + fputs ("RMI XLR", file); + break; + case AFL_EXT_OCTEON2: + fputs ("Cavium Networks Octeon2", file); + break; + case AFL_EXT_OCTEONP: + fputs ("Cavium Networks OcteonP", file); + break; + case AFL_EXT_LOONGSON_3A: + fputs ("Loongson 3A", file); + break; + case AFL_EXT_OCTEON: + fputs ("Cavium Networks Octeon", file); + break; + case AFL_EXT_5900: + fputs ("Toshiba R5900", file); + break; + case AFL_EXT_4650: + fputs ("MIPS R4650", file); + break; + case AFL_EXT_4010: + fputs ("LSI R4010", file); + break; + case AFL_EXT_4100: + fputs ("NEC VR4100", file); + break; + case AFL_EXT_3900: + fputs ("Toshiba R3900", file); + break; + case AFL_EXT_10000: + fputs ("MIPS R10000", file); + break; + case AFL_EXT_SB1: + fputs ("Broadcom SB-1", file); + break; + case AFL_EXT_4111: + fputs ("NEC VR4111/VR4181", file); + break; + case AFL_EXT_4120: + fputs ("NEC VR4120", file); + break; + case AFL_EXT_5400: + fputs ("NEC VR5400", file); + break; + case AFL_EXT_5500: + fputs ("NEC VR5500", file); + break; + case AFL_EXT_LOONGSON_2E: + fputs ("ST Microelectronics Loongson 2E", file); + break; + case AFL_EXT_LOONGSON_2F: + fputs ("ST Microelectronics Loongson 2F", file); + break; + default: + fputs (_("Unknown"), file); + break; + } +} + +static void +print_mips_fp_abi_value (FILE *file, int val) +{ + switch (val) + { + case Val_GNU_MIPS_ABI_FP_ANY: + fprintf (file, _("Hard or soft float\n")); + break; + case Val_GNU_MIPS_ABI_FP_DOUBLE: + fprintf (file, _("Hard float (double precision)\n")); + break; + case Val_GNU_MIPS_ABI_FP_SINGLE: + fprintf (file, _("Hard float (single precision)\n")); + break; + case Val_GNU_MIPS_ABI_FP_SOFT: + fprintf (file, _("Soft float\n")); + break; + case Val_GNU_MIPS_ABI_FP_OLD_64: + fprintf (file, _("Hard float (MIPS32r2 64-bit FPU 12 callee-saved)\n")); + break; + case Val_GNU_MIPS_ABI_FP_XX: + fprintf (file, _("Hard float (32-bit CPU, Any FPU)\n")); + break; + case Val_GNU_MIPS_ABI_FP_64: + fprintf (file, _("Hard float (32-bit CPU, 64-bit FPU)\n")); + break; + case Val_GNU_MIPS_ABI_FP_64A: + fprintf (file, _("Hard float compat (32-bit CPU, 64-bit FPU)\n")); + break; + default: + fprintf (file, "??? (%d)\n", val); + break; + } +} + +static int +get_mips_reg_size (int reg_size) +{ + return (reg_size == AFL_REG_NONE) ? 0 + : (reg_size == AFL_REG_32) ? 32 + : (reg_size == AFL_REG_64) ? 64 + : (reg_size == AFL_REG_128) ? 128 + : -1; +} + bfd_boolean _bfd_mips_elf_print_private_bfd_data (bfd *abfd, void *ptr) { @@ -14924,6 +15648,10 @@ _bfd_mips_elf_print_private_bfd_data (bfd *abfd, void *ptr) fprintf (file, " [mips32r2]"); else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64R2) fprintf (file, " [mips64r2]"); + else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R6) + fprintf (file, " [mips32r6]"); + else if ((elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) == E_MIPS_ARCH_64R6) + fprintf (file, " [mips64r6]"); else fprintf (file, _(" [unknown ISA]")); @@ -14940,7 +15668,7 @@ _bfd_mips_elf_print_private_bfd_data (bfd *abfd, void *ptr) fprintf (file, " [nan2008]"); if (elf_elfheader (abfd)->e_flags & EF_MIPS_FP64) - fprintf (file, " [fp64]"); + fprintf (file, " [old fp64]"); if (elf_elfheader (abfd)->e_flags & EF_MIPS_32BITMODE) fprintf (file, " [32bitmode]"); @@ -14964,6 +15692,30 @@ _bfd_mips_elf_print_private_bfd_data (bfd *abfd, void *ptr) fputc ('\n', file); + if (mips_elf_tdata (abfd)->abiflags_valid) + { + Elf_Internal_ABIFlags_v0 *abiflags = &mips_elf_tdata (abfd)->abiflags; + fprintf (file, "\nMIPS ABI Flags Version: %d\n", abiflags->version); + fprintf (file, "\nISA: MIPS%d", abiflags->isa_level); + if (abiflags->isa_rev > 1) + fprintf (file, "r%d", abiflags->isa_rev); + fprintf (file, "\nGPR size: %d", + get_mips_reg_size (abiflags->gpr_size)); + fprintf (file, "\nCPR1 size: %d", + get_mips_reg_size (abiflags->cpr1_size)); + fprintf (file, "\nCPR2 size: %d", + get_mips_reg_size (abiflags->cpr2_size)); + fputs ("\nFP ABI: ", file); + print_mips_fp_abi_value (file, abiflags->fp_abi); + fputs ("ISA Extension: ", file); + print_mips_isa_ext (file, abiflags->isa_ext); + fputs ("\nASEs:", file); + print_mips_ases (file, abiflags->ases); + fprintf (file, "\nFLAGS 1: %8.8lx", abiflags->flags1); + fprintf (file, "\nFLAGS 2: %8.8lx", abiflags->flags2); + fputc ('\n', file); + } + return TRUE; } @@ -15284,4 +16036,8 @@ _bfd_mips_post_process_headers (bfd *abfd, struct bfd_link_info *link_info) if (htab->use_plts_and_copy_relocs && !htab->is_vxworks) i_ehdrp->e_ident[EI_ABIVERSION] = 1; } + + if (mips_elf_tdata (abfd)->abiflags.fp_abi == Val_GNU_MIPS_ABI_FP_64 + || mips_elf_tdata (abfd)->abiflags.fp_abi == Val_GNU_MIPS_ABI_FP_64A) + i_ehdrp->e_ident[EI_ABIVERSION] = 3; } diff --git a/binutils-2.24/bfd/elfxx-mips.h b/binutils-2.24/bfd/elfxx-mips.h index f27dc15..9814e7a 100644 --- a/binutils-2.24/bfd/elfxx-mips.h +++ b/binutils-2.24/bfd/elfxx-mips.h @@ -109,6 +109,8 @@ extern bfd_boolean _bfd_mips_elf_merge_private_bfd_data (bfd *, bfd *); extern bfd_boolean _bfd_mips_elf_set_private_flags (bfd *, flagword); +extern const char * _bfd_mips_fp_abi_string + (int); extern bfd_boolean _bfd_mips_elf_print_private_bfd_data (bfd *, void *); extern bfd_boolean _bfd_mips_elf_discard_info @@ -156,6 +158,8 @@ extern bfd_vma _bfd_mips_elf_plt_sym_val (bfd_vma, const asection *, const arelent *rel); extern long _bfd_mips_elf_get_synthetic_symtab (bfd *, long, asymbol **, long, asymbol **, asymbol **); +extern bfd_boolean _bfd_mips_elf_gc_mark_extra_sections + (struct bfd_link_info *, elf_gc_mark_hook_fn); extern void _bfd_mips_post_process_headers (bfd *abfd, struct bfd_link_info *link_info); diff --git a/binutils-2.24/bfd/libbfd.h b/binutils-2.24/bfd/libbfd.h index 4aaecbf..e29839b 100644 --- a/binutils-2.24/bfd/libbfd.h +++ b/binutils-2.24/bfd/libbfd.h @@ -1128,6 +1128,10 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_MICROMIPS_7_PCREL_S1", "BFD_RELOC_MICROMIPS_10_PCREL_S1", "BFD_RELOC_MICROMIPS_16_PCREL_S1", + "BFD_RELOC_MIPS_21_PCREL_S2", + "BFD_RELOC_MIPS_26_PCREL_S2", + "BFD_RELOC_MIPS_18_PCREL_S3", + "BFD_RELOC_MIPS_19_PCREL_S2", "BFD_RELOC_MICROMIPS_GPREL16", "BFD_RELOC_MICROMIPS_HI16", "BFD_RELOC_MICROMIPS_HI16_S", diff --git a/binutils-2.24/bfd/reloc.c b/binutils-2.24/bfd/reloc.c index 77a04f8..8151d9b 100644 --- a/binutils-2.24/bfd/reloc.c +++ b/binutils-2.24/bfd/reloc.c @@ -2293,6 +2293,17 @@ ENUMDOC microMIPS PC-relative relocations. ENUM + BFD_RELOC_MIPS_21_PCREL_S2 +ENUMX + BFD_RELOC_MIPS_26_PCREL_S2 +ENUMX + BFD_RELOC_MIPS_18_PCREL_S3 +ENUMX + BFD_RELOC_MIPS_19_PCREL_S2 +ENUMDOC + MIPS PC-relative relocations. + +ENUM BFD_RELOC_MICROMIPS_GPREL16 ENUMX BFD_RELOC_MICROMIPS_HI16 diff --git a/binutils-2.24/binutils/ChangeLog b/binutils-2.24/binutils/ChangeLog index f9014b5..e4ee252 100644 --- a/binutils-2.24/binutils/ChangeLog +++ b/binutils-2.24/binutils/ChangeLog @@ -1,3 +1,12 @@ +2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com> + + * doc/binutils.texi: Document the disassemble MIPS XPA instructions + command line option. + +2014-02-06 Andrew Pinski <apinski@cavium.com> + + * readelf.c (get_machine_flags): Handle E_MIPS_MACH_OCTEON3 case. + 2013-11-22 Cory Fields <cory@coryfields.com> * windres.c (define_resource): Use zero for timestamp, making @@ -28,6 +37,11 @@ * nm.c (display_rel_file): Treat bfd_error_no_symbols as non-fatal. +2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> + + * readelf.c (display_mips_gnu_attribute): Support Tag_GNU_MIPS_ABI_MSA. + * doc/binutils.texi: Document -Mmsa disassembler option. + 2013-10-12 H.J. Lu <hongjiu.lu@intel.com> * dwarf.c (display_debug_frames): Pass offset_size to diff --git a/binutils-2.24/binutils/doc/binutils.texi b/binutils-2.24/binutils/doc/binutils.texi index 9176d9b..59a33b1 100644 --- a/binutils-2.24/binutils/doc/binutils.texi +++ b/binutils-2.24/binutils/doc/binutils.texi @@ -2114,9 +2114,15 @@ Print the 'raw' instruction mnemonic instead of some pseudo instruction mnemonic. I.e., print 'daddu' or 'or' instead of 'move', 'sll' instead of 'nop', etc. +@item msa +Disassemble MSA instructions. + @item virt Disassemble the virtualization ASE instructions. +@item xpa +Disassemble the eXtended Physical Address (XPA) ASE instructions. + @item gpr-names=@var{ABI} Print GPR (general-purpose register) names as appropriate for the specified ABI. By default, GPR names are selected according to diff --git a/binutils-2.24/binutils/readelf.c b/binutils-2.24/binutils/readelf.c index 61ea0ad..8e0c819 100644 --- a/binutils-2.24/binutils/readelf.c +++ b/binutils-2.24/binutils/readelf.c @@ -2601,6 +2601,7 @@ get_machine_flags (unsigned e_flags, unsigned e_machine) case E_MIPS_MACH_LS3A: strcat (buf, ", loongson-3a"); break; case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break; case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break; + case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break; case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break; case 0: /* We simply ignore the field in this case to avoid confusion: @@ -2643,8 +2644,10 @@ get_machine_flags (unsigned e_flags, unsigned e_machine) case E_MIPS_ARCH_5: strcat (buf, ", mips5"); break; case E_MIPS_ARCH_32: strcat (buf, ", mips32"); break; case E_MIPS_ARCH_32R2: strcat (buf, ", mips32r2"); break; + case E_MIPS_ARCH_32R6: strcat (buf, ", mips32r6"); break; case E_MIPS_ARCH_64: strcat (buf, ", mips64"); break; case E_MIPS_ARCH_64R2: strcat (buf, ", mips64r2"); break; + case E_MIPS_ARCH_64R6: strcat (buf, ", mips64r6"); break; default: strcat (buf, _(", unknown ISA")); break; } break; @@ -2951,6 +2954,8 @@ get_mips_segment_type (unsigned long type) return "RTPROC"; case PT_MIPS_OPTIONS: return "OPTIONS"; + case PT_MIPS_ABIFLAGS: + return "ABIFLAGS"; default: break; } @@ -3150,6 +3155,7 @@ get_mips_section_type_name (unsigned int sh_type) case SHT_MIPS_EH_REGION: return "MIPS_EH_REGION"; case SHT_MIPS_XLATE_OLD: return "MIPS_XLATE_OLD"; case SHT_MIPS_PDR_EXCEPTION: return "MIPS_PDR_EXCEPTION"; + case SHT_MIPS_ABIFLAGS: return "MIPS_ABIFLAGS"; default: break; } @@ -11755,6 +11761,41 @@ display_sparc_gnu_attribute (unsigned char * p, return display_tag_value (tag, p, end); } +static void +print_mips_fp_abi_value (int val) +{ + switch (val) + { + case Val_GNU_MIPS_ABI_FP_ANY: + printf (_("Hard or soft float\n")); + break; + case Val_GNU_MIPS_ABI_FP_DOUBLE: + printf (_("Hard float (double precision)\n")); + break; + case Val_GNU_MIPS_ABI_FP_SINGLE: + printf (_("Hard float (single precision)\n")); + break; + case Val_GNU_MIPS_ABI_FP_SOFT: + printf (_("Soft float\n")); + break; + case Val_GNU_MIPS_ABI_FP_OLD_64: + printf (_("Hard float (MIPS32r2 64-bit FPU 12 callee-saved)\n")); + break; + case Val_GNU_MIPS_ABI_FP_XX: + printf (_("Hard float (32-bit CPU, Any FPU)\n")); + break; + case Val_GNU_MIPS_ABI_FP_64: + printf (_("Hard float (32-bit CPU, 64-bit FPU)\n")); + break; + case Val_GNU_MIPS_ABI_FP_64A: + printf (_("Hard float compat (32-bit CPU, 64-bit FPU)\n")); + break; + default: + printf ("??? (%d)\n", val); + break; + } +} + static unsigned char * display_mips_gnu_attribute (unsigned char * p, int tag, @@ -11769,29 +11810,34 @@ display_mips_gnu_attribute (unsigned char * p, p += len; printf (" Tag_GNU_MIPS_ABI_FP: "); + print_mips_fp_abi_value (val); + + return p; + } + + if (tag == Tag_GNU_MIPS_ABI_MSA) + { + unsigned int len; + int val; + + val = read_uleb128 (p, &len, end); + p += len; + printf (" Tag_GNU_MIPS_ABI_MSA: "); + switch (val) { - case Val_GNU_MIPS_ABI_FP_ANY: - printf (_("Hard or soft float\n")); + case Val_GNU_MIPS_ABI_MSA_ANY: + printf (_("Any MSA or not\n")); break; - case Val_GNU_MIPS_ABI_FP_DOUBLE: - printf (_("Hard float (double precision)\n")); - break; - case Val_GNU_MIPS_ABI_FP_SINGLE: - printf (_("Hard float (single precision)\n")); - break; - case Val_GNU_MIPS_ABI_FP_SOFT: - printf (_("Soft float\n")); - break; - case Val_GNU_MIPS_ABI_FP_64: - printf (_("Hard float (MIPS32r2 64-bit FPU)\n")); + case Val_GNU_MIPS_ABI_MSA_128: + printf (_("128-bit MSA\n")); break; default: printf ("??? (%d)\n", val); break; } return p; - } + } return display_tag_value (tag & 1, p, end); } @@ -12361,10 +12407,121 @@ print_mips_pltgot_entry (unsigned char * data, bfd_vma pltgot, bfd_vma addr) return addr + (is_32bit_elf ? 4 : 8); } +static void +print_mips_ases (unsigned int mask) +{ + if (mask & AFL_ASE_DSP) + fputs ("\n\tDSP ASE", stdout); + if (mask & AFL_ASE_DSPR2) + fputs ("\n\tDSP R2 ASE", stdout); + if (mask & AFL_ASE_EVA) + fputs ("\n\tEnhanced VA Scheme", stdout); + if (mask & AFL_ASE_MCU) + fputs ("\n\tMCU (MicroController) ASE", stdout); + if (mask & AFL_ASE_MDMX) + fputs ("\n\tMDMX ASE", stdout); + if (mask & AFL_ASE_MIPS3D) + fputs ("\n\tMIPS-3D ASE", stdout); + if (mask & AFL_ASE_MT) + fputs ("\n\tMT ASE", stdout); + if (mask & AFL_ASE_SMARTMIPS) + fputs ("\n\tSmartMIPS ASE", stdout); + if (mask & AFL_ASE_VIRT) + fputs ("\n\tVZ ASE", stdout); + if (mask & AFL_ASE_MSA) + fputs ("\n\tMSA ASE", stdout); + if (mask & AFL_ASE_MIPS16) + fputs ("\n\tMIPS16 ASE", stdout); + if (mask & AFL_ASE_MICROMIPS) + fputs ("\n\tMICROMIPS ASE", stdout); + if (mask & AFL_ASE_XPA) + fputs ("\n\tXPA ASE", stdout); + if (mask == 0) + fprintf (stdout, "\n\t%s", _("None")); +} + +static void +print_mips_isa_ext (unsigned int isa_ext) +{ + switch (isa_ext) + { + case 0: + fputs (_("None"), stdout); + break; + case AFL_EXT_XLR: + fputs ("RMI XLR", stdout); + break; + case AFL_EXT_OCTEON2: + fputs ("Cavium Networks Octeon2", stdout); + break; + case AFL_EXT_OCTEONP: + fputs ("Cavium Networks OcteonP", stdout); + break; + case AFL_EXT_LOONGSON_3A: + fputs ("Loongson 3A", stdout); + break; + case AFL_EXT_OCTEON: + fputs ("Cavium Networks Octeon", stdout); + break; + case AFL_EXT_5900: + fputs ("Toshiba R5900", stdout); + break; + case AFL_EXT_4650: + fputs ("MIPS R4650", stdout); + break; + case AFL_EXT_4010: + fputs ("LSI R4010", stdout); + break; + case AFL_EXT_4100: + fputs ("NEC VR4100", stdout); + break; + case AFL_EXT_3900: + fputs ("Toshiba R3900", stdout); + break; + case AFL_EXT_10000: + fputs ("MIPS R10000", stdout); + break; + case AFL_EXT_SB1: + fputs ("Broadcom SB-1", stdout); + break; + case AFL_EXT_4111: + fputs ("NEC VR4111/VR4181", stdout); + break; + case AFL_EXT_4120: + fputs ("NEC VR4120", stdout); + break; + case AFL_EXT_5400: + fputs ("NEC VR5400", stdout); + break; + case AFL_EXT_5500: + fputs ("NEC VR5500", stdout); + break; + case AFL_EXT_LOONGSON_2E: + fputs ("ST Microelectronics Loongson 2E", stdout); + break; + case AFL_EXT_LOONGSON_2F: + fputs ("ST Microelectronics Loongson 2F", stdout); + break; + default: + fputs (_("Unknown"), stdout); + } +} + +static int +get_mips_reg_size (int reg_size) +{ + return (reg_size == AFL_REG_NONE) ? 0 + : (reg_size == AFL_REG_32) ? 32 + : (reg_size == AFL_REG_64) ? 64 + : (reg_size == AFL_REG_128) ? 128 + : -1; +} + static int process_mips_specific (FILE * file) { Elf_Internal_Dyn * entry; + Elf_Internal_Shdr *sect = NULL; size_t liblist_offset = 0; size_t liblistno = 0; size_t conflictsno = 0; @@ -12382,6 +12539,57 @@ process_mips_specific (FILE * file) process_attributes (file, NULL, SHT_GNU_ATTRIBUTES, NULL, display_mips_gnu_attribute); + sect = find_section (".MIPS.abiflags"); + + if (sect != NULL) + { + Elf_External_ABIFlags_v0 *abiflags_ext; + Elf_Internal_ABIFlags_v0 abiflags_in; + + if (sizeof (Elf_External_ABIFlags_v0) != sect->sh_size) + fputs ("\nCorrupt ABI Flags section.\n", stdout); + else + { + abiflags_ext = get_data (NULL, file, sect->sh_offset, 1, + sect->sh_size, _("MIPS ABI Flags section")); + if (abiflags_ext) + { + abiflags_in.version = BYTE_GET (abiflags_ext->version); + abiflags_in.isa_level = BYTE_GET (abiflags_ext->isa_level); + abiflags_in.isa_rev = BYTE_GET (abiflags_ext->isa_rev); + abiflags_in.gpr_size = BYTE_GET (abiflags_ext->gpr_size); + abiflags_in.cpr1_size = BYTE_GET (abiflags_ext->cpr1_size); + abiflags_in.cpr2_size = BYTE_GET (abiflags_ext->cpr2_size); + abiflags_in.fp_abi = BYTE_GET (abiflags_ext->fp_abi); + abiflags_in.isa_ext = BYTE_GET (abiflags_ext->isa_ext); + abiflags_in.ases = BYTE_GET (abiflags_ext->ases); + abiflags_in.flags1 = BYTE_GET (abiflags_ext->flags1); + abiflags_in.flags2 = BYTE_GET (abiflags_ext->flags2); + + printf ("\nMIPS ABI Flags Version: %d\n", abiflags_in.version); + printf ("\nISA: MIPS%d", abiflags_in.isa_level); + if (abiflags_in.isa_rev > 1) + printf ("r%d", abiflags_in.isa_rev); + printf ("\nGPR size: %d", + get_mips_reg_size (abiflags_in.gpr_size)); + printf ("\nCPR1 size: %d", + get_mips_reg_size (abiflags_in.cpr1_size)); + printf ("\nCPR2 size: %d", + get_mips_reg_size (abiflags_in.cpr2_size)); + fputs ("\nFP ABI: ", stdout); + print_mips_fp_abi_value (abiflags_in.fp_abi); + fputs ("ISA Extension: ", stdout); + print_mips_isa_ext (abiflags_in.isa_ext); + fputs ("\nASEs:", stdout); + print_mips_ases (abiflags_in.ases); + printf ("\nFLAGS 1: %8.8lx", abiflags_in.flags1); + printf ("\nFLAGS 2: %8.8lx", abiflags_in.flags2); + fputc ('\n', stdout); + free (abiflags_ext); + } + } + } + /* We have a lot of special sections. Thanks SGI! */ if (dynamic_section == NULL) /* No information available. */ @@ -12521,11 +12729,11 @@ process_mips_specific (FILE * file) if (options_offset != 0) { Elf_External_Options * eopt; - Elf_Internal_Shdr * sect = section_headers; Elf_Internal_Options * iopt; Elf_Internal_Options * option; size_t offset; int cnt; + sect = section_headers; /* Find the section header so that we get the size. */ while (sect->sh_type != SHT_MIPS_OPTIONS) diff --git a/binutils-2.24/binutils/testsuite/ChangeLog b/binutils-2.24/binutils/testsuite/ChangeLog index 1ab6e86..90ccd39 100644 --- a/binutils-2.24/binutils/testsuite/ChangeLog +++ b/binutils-2.24/binutils/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2013-11-27 Matthew Fortune <matthew.fortune@imgtec.com> + + * binutils-all/objcopy.exp: Consider mips-mti-elf the same as + mips-sde-elf + * binutils-all/readelf.exp: Likewise + 2013-10-12 H.J. Lu <hongjiu.lu@intel.com> * binutils-all/x86-64/compressed-1a.d: Updated for 64-bit addresses. diff --git a/binutils-2.24/binutils/testsuite/binutils-all/objcopy.exp b/binutils-2.24/binutils/testsuite/binutils-all/objcopy.exp index 4dfb73c..66d3d51 100644 --- a/binutils-2.24/binutils/testsuite/binutils-all/objcopy.exp +++ b/binutils-2.24/binutils/testsuite/binutils-all/objcopy.exp @@ -988,7 +988,9 @@ if [is_elf_format] { # targ_defvec=bfd_elf32_nbigmips_vec or # targ_defvec=bfd_elf32_nlittlemips_vec in config.bfd. When syncing, # don't forget that earlier case-matches trump later ones. - if { ![istarget "mips*-sde-elf*"] && ![istarget "mips64*-*-openbsd*"] } { + if { ![istarget "mips*-sde-elf*"] && ![istarget "mips*-mti-elf*"] + && ![istarget "mips*-img-elf*"] + && ![istarget "mips64*-*-openbsd*"] } { setup_xfail "mips*-*-irix5*" "mips*-*-irix6*" "mips*-*-elf*" \ "mips*-*-rtems*" "mips*-*-windiss" "mips*-*-none" \ "mips*-*-openbsd*" "mips*-*-chorus*" diff --git a/binutils-2.24/binutils/testsuite/binutils-all/readelf.exp b/binutils-2.24/binutils/testsuite/binutils-all/readelf.exp index db56a86..a0f54d9 100644 --- a/binutils-2.24/binutils/testsuite/binutils-all/readelf.exp +++ b/binutils-2.24/binutils/testsuite/binutils-all/readelf.exp @@ -102,6 +102,8 @@ proc readelf_test { options binary_file regexp_file xfails } { if [istarget "mips*-*-*"] then { if { [istarget "mips*-*-*linux*"] || [istarget "mips*-sde-elf*"] + || [istarget "mips*-mti-elf*"] + || [istarget "mips*-img-elf*"] || [istarget "mips*-*freebsd*"] } then { set target_machine tmips } else { diff --git a/binutils-2.24/binutils/testsuite/binutils-all/readelf.s b/binutils-2.24/binutils/testsuite/binutils-all/readelf.s index 8361a7e..3b044b1 100644 --- a/binutils-2.24/binutils/testsuite/binutils-all/readelf.s +++ b/binutils-2.24/binutils/testsuite/binutils-all/readelf.s @@ -6,16 +6,16 @@ Section Headers: # On the normal MIPS systems, sections must be aligned to 16 byte # boundaries. On IA64, text sections are aligned to 16 byte boundaries. +\[ 1\] .text +PROGBITS +00000000 0000(34|40) 0000(08|10) 00 +AX +0 +0 +(.|..) - +\[ 2\] .rel.+text +REL. +0+ 0+.* 00000. 0. +. +1 +4 + +\[ 2\] .rel.+text +REL. +0+ 0+.* 0000.. 0. +I +.+ +1 +4 # MIPS targets put .rela.text here. #... +\[ .\] .data +PROGBITS +00000000 0000(3c|48|50) 0000(04|10) 00 +WA +0 +0 +(.|..) +\[ .\] .bss +NOBITS +00000000 0000(40|4c|60) 000000 00 +WA +0 +0 +(.|..) -# MIPS targets put .reginfo and .mdebug here. +# MIPS targets put .reginfo, .mdebug, .MIPS.abiflags and .gnu.attributes here. # v850 targets put .call_table_data and .call_table_text here. #... +\[ .\] .shstrtab +STRTAB +00000000 0+.* 0+.* 00 +0 +0 +. - +\[ .\] .symtab +SYMTAB +00000000 0+.* 0+.* 10 +.. +. +4 + +\[..\] .symtab +SYMTAB +00000000 0+.* 0+.* 10 +.. +.+ +4 +\[..\] .strtab +STRTAB +00000000 0+.* 0+.* 00 +0 +0 +1 Key to Flags: #... diff --git a/binutils-2.24/binutils/testsuite/binutils-all/readelf.ss-tmips b/binutils-2.24/binutils/testsuite/binutils-all/readelf.ss-tmips index 1f87248..c59f753 100644 --- a/binutils-2.24/binutils/testsuite/binutils-all/readelf.ss-tmips +++ b/binutils-2.24/binutils/testsuite/binutils-all/readelf.ss-tmips @@ -1,5 +1,5 @@ -Symbol table '.symtab' contains 12 entries: +Symbol table '.symtab' contains 14 entries: +Num: +Value +Size +Type +Bind +Vis +Ndx +Name +0: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +UND +1: 00000000 +0 +SECTION +LOCAL +DEFAULT +1 @@ -9,7 +9,9 @@ Symbol table '.symtab' contains 12 entries: +5: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +3 static_data_symbol +6: 00000000 +0 +SECTION +LOCAL +DEFAULT +5 +7: 00000000 +0 +SECTION +LOCAL +DEFAULT +6 - +8: 00000000 +0 +OBJECT +GLOBAL +DEFAULT +1 text_symbol - +9: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND external_symbol - +10: 00000000 +0 +OBJECT +GLOBAL +DEFAULT +3 data_symbol - +11: 00000004 +4 +(COMMON|OBJECT) +GLOBAL +DEFAULT +(PRC|COM) common_symbol + +8: 00000000 +0 +SECTION +LOCAL +DEFAULT +7 + +9: 00000000 +0 +SECTION +LOCAL +DEFAULT +8 + +10: 00000000 +0 +OBJECT +GLOBAL +DEFAULT +1 text_symbol + +11: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND external_symbol + +12: 00000000 +0 +OBJECT +GLOBAL +DEFAULT +3 data_symbol + +13: 00000004 +4 +(COMMON|OBJECT) +GLOBAL +DEFAULT +(PRC|COM) common_symbol diff --git a/binutils-2.24/binutils/testsuite/binutils-all/strip-3.d b/binutils-2.24/binutils/testsuite/binutils-all/strip-3.d index acfec85..ee2708e 100644 --- a/binutils-2.24/binutils/testsuite/binutils-all/strip-3.d +++ b/binutils-2.24/binutils/testsuite/binutils-all/strip-3.d @@ -1,6 +1,6 @@ #PROG: strip #source: empty.s -#strip: -R .text -R .data -R .bss -R .ARM.attributes -R .reginfo -R .pdr -R .xtensa.info +#strip: -R .text -R .data -R .bss -R .ARM.attributes -R .reginfo -R .gnu.attributes -R .MIPS.abiflags -R .pdr -R .xtensa.info #readelf: -S --wide #name: strip empty file #target: *-*-linux* *-*-gnu* diff --git a/binutils-2.24/config.guess b/binutils-2.24/config.guess index b79252d..1f5c50c 100755 --- a/binutils-2.24/config.guess +++ b/binutils-2.24/config.guess @@ -1,8 +1,8 @@ #! /bin/sh # Attempt to guess a canonical system name. -# Copyright 1992-2013 Free Software Foundation, Inc. +# Copyright 1992-2014 Free Software Foundation, Inc. -timestamp='2013-06-10' +timestamp='2014-03-23' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by @@ -50,7 +50,7 @@ version="\ GNU config.guess ($timestamp) Originally written by Per Bothner. -Copyright 1992-2013 Free Software Foundation, Inc. +Copyright 1992-2014 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." @@ -149,7 +149,7 @@ Linux|GNU|GNU/*) LIBC=gnu #endif EOF - eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC'` + eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^LIBC' | sed 's, ,,g'` ;; esac @@ -826,7 +826,7 @@ EOF *:MINGW*:*) echo ${UNAME_MACHINE}-pc-mingw32 exit ;; - i*:MSYS*:*) + *:MSYS*:*) echo ${UNAME_MACHINE}-pc-msys exit ;; i*:windows32*:*) @@ -969,10 +969,10 @@ EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep '^CPU'` test x"${CPU}" != x && { echo "${CPU}-unknown-linux-${LIBC}"; exit; } ;; - or1k:Linux:*:*) - echo ${UNAME_MACHINE}-unknown-linux-${LIBC} + openrisc*:Linux:*:*) + echo or1k-unknown-linux-${LIBC} exit ;; - or32:Linux:*:*) + or32:Linux:*:* | or1k*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-${LIBC} exit ;; padre:Linux:*:*) @@ -1260,16 +1260,26 @@ EOF if test "$UNAME_PROCESSOR" = unknown ; then UNAME_PROCESSOR=powerpc fi - if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then - if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ - (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ - grep IS_64BIT_ARCH >/dev/null - then - case $UNAME_PROCESSOR in - i386) UNAME_PROCESSOR=x86_64 ;; - powerpc) UNAME_PROCESSOR=powerpc64 ;; - esac + if test `echo "$UNAME_RELEASE" | sed -e 's/\..*//'` -le 10 ; then + if [ "$CC_FOR_BUILD" != 'no_compiler_found' ]; then + if (echo '#ifdef __LP64__'; echo IS_64BIT_ARCH; echo '#endif') | \ + (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | \ + grep IS_64BIT_ARCH >/dev/null + then + case $UNAME_PROCESSOR in + i386) UNAME_PROCESSOR=x86_64 ;; + powerpc) UNAME_PROCESSOR=powerpc64 ;; + esac + fi fi + elif test "$UNAME_PROCESSOR" = i386 ; then + # Avoid executing cc on OS X 10.9, as it ships with a stub + # that puts up a graphical alert prompting to install + # developer tools. Any system running Mac OS X 10.7 or + # later (Darwin 11 and later) is required to have a 64-bit + # processor. This is not true of the ARM version of Darwin + # that Apple uses in portable devices. + UNAME_PROCESSOR=x86_64 fi echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} exit ;; @@ -1361,154 +1371,6 @@ EOF exit ;; esac -eval $set_cc_for_build -cat >$dummy.c <<EOF -#ifdef _SEQUENT_ -# include <sys/types.h> -# include <sys/utsname.h> -#endif -main () -{ -#if defined (sony) -#if defined (MIPSEB) - /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, - I don't know.... */ - printf ("mips-sony-bsd\n"); exit (0); -#else -#include <sys/param.h> - printf ("m68k-sony-newsos%s\n", -#ifdef NEWSOS4 - "4" -#else - "" -#endif - ); exit (0); -#endif -#endif - -#if defined (__arm) && defined (__acorn) && defined (__unix) - printf ("arm-acorn-riscix\n"); exit (0); -#endif - -#if defined (hp300) && !defined (hpux) - printf ("m68k-hp-bsd\n"); exit (0); -#endif - -#if defined (NeXT) -#if !defined (__ARCHITECTURE__) -#define __ARCHITECTURE__ "m68k" -#endif - int version; - version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`; - if (version < 4) - printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version); - else - printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version); - exit (0); -#endif - -#if defined (MULTIMAX) || defined (n16) -#if defined (UMAXV) - printf ("ns32k-encore-sysv\n"); exit (0); -#else -#if defined (CMU) - printf ("ns32k-encore-mach\n"); exit (0); -#else - printf ("ns32k-encore-bsd\n"); exit (0); -#endif -#endif -#endif - -#if defined (__386BSD__) - printf ("i386-pc-bsd\n"); exit (0); -#endif - -#if defined (sequent) -#if defined (i386) - printf ("i386-sequent-dynix\n"); exit (0); -#endif -#if defined (ns32000) - printf ("ns32k-sequent-dynix\n"); exit (0); -#endif -#endif - -#if defined (_SEQUENT_) - struct utsname un; - - uname(&un); - - if (strncmp(un.version, "V2", 2) == 0) { - printf ("i386-sequent-ptx2\n"); exit (0); - } - if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ - printf ("i386-sequent-ptx1\n"); exit (0); - } - printf ("i386-sequent-ptx\n"); exit (0); - -#endif - -#if defined (vax) -# if !defined (ultrix) -# include <sys/param.h> -# if defined (BSD) -# if BSD == 43 - printf ("vax-dec-bsd4.3\n"); exit (0); -# else -# if BSD == 199006 - printf ("vax-dec-bsd4.3reno\n"); exit (0); -# else - printf ("vax-dec-bsd\n"); exit (0); -# endif -# endif -# else - printf ("vax-dec-bsd\n"); exit (0); -# endif -# else - printf ("vax-dec-ultrix\n"); exit (0); -# endif -#endif - -#if defined (alliant) && defined (i860) - printf ("i860-alliant-bsd\n"); exit (0); -#endif - - exit (1); -} -EOF - -$CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && SYSTEM_NAME=`$dummy` && - { echo "$SYSTEM_NAME"; exit; } - -# Apollos put the system type in the environment. - -test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit; } - -# Convex versions that predate uname can use getsysinfo(1) - -if [ -x /usr/convex/getsysinfo ] -then - case `getsysinfo -f cpu_type` in - c1*) - echo c1-convex-bsd - exit ;; - c2*) - if getsysinfo -f scalar_acc - then echo c32-convex-bsd - else echo c2-convex-bsd - fi - exit ;; - c34*) - echo c34-convex-bsd - exit ;; - c38*) - echo c38-convex-bsd - exit ;; - c4*) - echo c4-convex-bsd - exit ;; - esac -fi - cat >&2 <<EOF $0: unable to guess system type diff --git a/binutils-2.24/config.sub b/binutils-2.24/config.sub index 61cb4bc..d654d03 100755 --- a/binutils-2.24/config.sub +++ b/binutils-2.24/config.sub @@ -1,8 +1,8 @@ #! /bin/sh # Configuration validation subroutine script. -# Copyright 1992-2013 Free Software Foundation, Inc. +# Copyright 1992-2014 Free Software Foundation, Inc. -timestamp='2013-10-01' +timestamp='2014-05-01' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by @@ -68,7 +68,7 @@ Report bugs and patches to <config-patches@gnu.org>." version="\ GNU config.sub ($timestamp) -Copyright 1992-2013 Free Software Foundation, Inc. +Copyright 1992-2014 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." @@ -283,8 +283,10 @@ case $basic_machine in | mips64vr5900 | mips64vr5900el \ | mipsisa32 | mipsisa32el \ | mipsisa32r2 | mipsisa32r2el \ + | mipsisa32r6 | mipsisa32r6el \ | mipsisa64 | mipsisa64el \ | mipsisa64r2 | mipsisa64r2el \ + | mipsisa64r6 | mipsisa64r6el \ | mipsisa64sb1 | mipsisa64sb1el \ | mipsisa64sr71k | mipsisa64sr71kel \ | mipsr5900 | mipsr5900el \ @@ -296,8 +298,7 @@ case $basic_machine in | nds32 | nds32le | nds32be \ | nios | nios2 | nios2eb | nios2el \ | ns16k | ns32k \ - | open8 \ - | or1k | or32 \ + | open8 | or1k | or1knd | or32 \ | pdp10 | pdp11 | pj | pjl \ | powerpc | powerpc64 | powerpc64le | powerpcle \ | pyramid \ @@ -402,8 +403,10 @@ case $basic_machine in | mips64vr5900-* | mips64vr5900el-* \ | mipsisa32-* | mipsisa32el-* \ | mipsisa32r2-* | mipsisa32r2el-* \ + | mipsisa32r6-* | mipsisa32r6el-* \ | mipsisa64-* | mipsisa64el-* \ | mipsisa64r2-* | mipsisa64r2el-* \ + | mipsisa64r6-* | mipsisa64r6el-* \ | mipsisa64sb1-* | mipsisa64sb1el-* \ | mipsisa64sr71k-* | mipsisa64sr71kel-* \ | mipsr5900-* | mipsr5900el-* \ @@ -415,6 +418,7 @@ case $basic_machine in | nios-* | nios2-* | nios2eb-* | nios2el-* \ | none-* | np1-* | ns16k-* | ns32k-* \ | open8-* \ + | or1k*-* \ | orion-* \ | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* \ @@ -1376,7 +1380,7 @@ case $os in | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \ | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \ | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \ - | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es*) + | -skyos* | -haiku* | -rdos* | -toppers* | -drops* | -es* | -tirtos*) # Remember, each alternative MUST END IN *, to match a version number. ;; -qnx*) @@ -1594,9 +1598,6 @@ case $basic_machine in mips*-*) os=-elf ;; - or1k-*) - os=-elf - ;; or32-*) os=-coff ;; diff --git a/binutils-2.24/configure b/binutils-2.24/configure index ee45e1b..bae77b4 100755 --- a/binutils-2.24/configure +++ b/binutils-2.24/configure @@ -3770,7 +3770,7 @@ case "${target}" in microblaze*) noconfigdirs="$noconfigdirs gprof" ;; - mips*-sde-elf* | mips*-mti-elf*) + mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) if test x$with_newlib = xyes; then noconfigdirs="$noconfigdirs gprof" fi @@ -6926,7 +6926,7 @@ case "${target}" in spu-*-*) target_makefile_frag="config/mt-spu" ;; - mips*-sde-elf* | mips*-mti-elf*) + mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) target_makefile_frag="config/mt-sde" ;; mipsisa*-*-elfoabi*) diff --git a/binutils-2.24/configure.ac b/binutils-2.24/configure.ac index aaf68cd..353e3c2 100644 --- a/binutils-2.24/configure.ac +++ b/binutils-2.24/configure.ac @@ -1106,7 +1106,7 @@ case "${target}" in microblaze*) noconfigdirs="$noconfigdirs gprof" ;; - mips*-sde-elf* | mips*-mti-elf*) + mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) if test x$with_newlib = xyes; then noconfigdirs="$noconfigdirs gprof" fi @@ -2358,7 +2358,7 @@ case "${target}" in spu-*-*) target_makefile_frag="config/mt-spu" ;; - mips*-sde-elf* | mips*-mti-elf*) + mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) target_makefile_frag="config/mt-sde" ;; mipsisa*-*-elfoabi*) diff --git a/binutils-2.24/elfcpp/ChangeLog b/binutils-2.24/elfcpp/ChangeLog index 3ae46c1..e21afa6 100644 --- a/binutils-2.24/elfcpp/ChangeLog +++ b/binutils-2.24/elfcpp/ChangeLog @@ -1,3 +1,36 @@ +2014-04-15 Sasa Stankovic <Sasa.Stankovic@imgtec.com> + + * mips.h (R _MIPS16_TLS_GD, R_MIPS16_TLS_LDM, R_MIPS16_TLS_DTPREL_HI16, + R_MIPS16_TLS_DTPREL_LO16, R_MIPS16_TLS_GOTTPREL, + R_MIPS16_TLS_TPREL_HI16, R_MIPS16_TLS_TPREL_LO16, R_MICROMIPS_26_S1, + R_MICROMIPS_HI16, R_MICROMIPS_LO16, R_MICROMIPS_GPREL16, + R_MICROMIPS_LITERAL, R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1, + R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1, R_MICROMIPS_CALL16, + R_MICROMIPS_GOT_DISP, R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST, + R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16, R_MICROMIPS_SUB, + R_MICROMIPS_HIGHER, R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16, + R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP, R_MICROMIPS_JALR, + R_MICROMIPS_HI0_LO16, R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM, + R_MICROMIPS_TLS_DTPREL_HI16, R_MICROMIPS_TLS_DTPREL_LO16, + R_MICROMIPS_TLS_GOTTPREL, R_MICROMIPS_TLS_TPREL_HI16, + R_MICROMIPS_TLS_TPREL_LO16, R_MICROMIPS_GPREL7_S2, + R_MICROMIPS_PC23_S20, R_MIPS_EH): New enums for relocations (mips16 and + micromips). + (STO_MIPS_FLAGS): New enum constant. + (elf_st_is_mips16): New function. + (elf_st_is_micromips): New function. + (is_micromips): New function. + (abi_n32): New function. + (abi_n64): New function. + (ODK_NULL, ODK_REGINFO, ODK_EXCEPTIONS, ODK_PAD, ODK_HWPATCH, ODK_FILL, + ODK_TAGS, ODK_HWAND, ODK_HWOR, ODK_GP_GROUP, ODK_IDENT): New enum + constants. + * elfcpp.h (SHT_MIPS_OPTIONS): New enum constant. + +2014-02-06 Andrew Pinski <apinski@cavium.com> + + * mips.h (E_MIPS_MACH_OCTEON3): New enum constant. + 2013-11-17 H.J. Lu <hongjiu.lu@intel.com> * x86_64.h (R_X86_64_PC32_BND): New. diff --git a/binutils-2.24/elfcpp/elfcpp.h b/binutils-2.24/elfcpp/elfcpp.h index 067c775..e41a7c6 100644 --- a/binutils-2.24/elfcpp/elfcpp.h +++ b/binutils-2.24/elfcpp/elfcpp.h @@ -401,9 +401,11 @@ enum SHT // x86_64 unwind information. SHT_X86_64_UNWIND = 0x70000001, - //MIPS-specific section types. - // Register info section + // MIPS-specific section types. + // Section contains register usage information. SHT_MIPS_REGINFO = 0x70000006, + // Section contains miscellaneous options. + SHT_MIPS_OPTIONS = 0x7000000d, // Link editor is to sort the entries in this section based on the // address specified in the associated symbol table entry. @@ -489,7 +491,9 @@ enum PT // Runtime procedure table. PT_MIPS_RTPROC = 0x70000001, // .MIPS.options section. - PT_MIPS_OPTIONS = 0x70000002 + PT_MIPS_OPTIONS = 0x70000002, + // .MIPS.abiflags section. + PT_MIPS_ABIFLAGS = 0x70000003 }; // The valid bit flags found in the Phdr p_flags field. diff --git a/binutils-2.24/elfcpp/mips.h b/binutils-2.24/elfcpp/mips.h index 8c2d8f4..d45197d 100644 --- a/binutils-2.24/elfcpp/mips.h +++ b/binutils-2.24/elfcpp/mips.h @@ -1,7 +1,8 @@ // mips.h -- ELF definitions specific to EM_MIPS -*- C++ -*- // Copyright 2012 Free Software Foundation, Inc. -// Written by Aleksandar Simeonov <aleksandar.simeonov@rt-rk.com>. +// Written by Sasa Stankovic <sasa.stankovic@rt-rk.com> +// and Aleksandar Simeonov <aleksandar.simeonov@rt-rk.com>. // This file is part of elfcpp. @@ -46,16 +47,16 @@ enum { R_MIPS_NONE = 0, R_MIPS_16 = 1, - R_MIPS_32 = 2, - R_MIPS_REL32 = 3, + R_MIPS_32 = 2, // In Elf 64: alias R_MIPS_ADD + R_MIPS_REL32 = 3, // In Elf 64: alias R_MIPS_REL R_MIPS_26 = 4, R_MIPS_HI16 = 5, R_MIPS_LO16 = 6, - R_MIPS_GPREL16 = 7, + R_MIPS_GPREL16 = 7, // In Elf 64: alias R_MIPS_GPREL R_MIPS_LITERAL = 8, - R_MIPS_GOT16 = 9, + R_MIPS_GOT16 = 9, // In Elf 64: alias R_MIPS_GOT R_MIPS_PC16 = 10, - R_MIPS_CALL16 = 11, + R_MIPS_CALL16 = 11, // In Elf 64: alias R_MIPS_CALL R_MIPS_GPREL32 = 12, R_MIPS_UNUSED1 = 13, R_MIPS_UNUSED2 = 14, @@ -69,48 +70,101 @@ enum R_MIPS_GOT_HI16 = 22, R_MIPS_GOT_LO16 = 23, R_MIPS_SUB = 24, - R_MIPS_INSERT_A = 25, // Empty relocation - R_MIPS_INSERT_B = 26, // Empty relocation - R_MIPS_DELETE = 27, // Empty relocation + R_MIPS_INSERT_A = 25, + R_MIPS_INSERT_B = 26, + R_MIPS_DELETE = 27, R_MIPS_HIGHER = 28, R_MIPS_HIGHEST = 29, R_MIPS_CALL_HI16 = 30, R_MIPS_CALL_LO16 = 31, R_MIPS_SCN_DISP = 32, - R_MIPS_REL16 = 33, // Empty relocation - R_MIPS_ADD_IMMEDIATE = 34, // Empty relocation - R_MIPS_PJUMP = 35, // Empty relocation - R_MIPS_RELGOT = 36, // Empty relocation + R_MIPS_REL16 = 33, + R_MIPS_ADD_IMMEDIATE = 34, + R_MIPS_PJUMP = 35, + R_MIPS_RELGOT = 36, R_MIPS_JALR = 37, + // TLS relocations. R_MIPS_TLS_DTPMOD32 = 38, R_MIPS_TLS_DTPREL32 = 39, - R_MIPS_TLS_DTPMOD64 = 40, // Empty relocation - R_MIPS_TLS_DTPREL64 = 41, // Empty relocation + R_MIPS_TLS_DTPMOD64 = 40, + R_MIPS_TLS_DTPREL64 = 41, R_MIPS_TLS_GD = 42, R_MIPS_TLS_LDM = 43, R_MIPS_TLS_DTPREL_HI16 = 44, R_MIPS_TLS_DTPREL_LO16 = 45, R_MIPS_TLS_GOTTPREL = 46, R_MIPS_TLS_TPREL32 = 47, - R_MIPS_TLS_TPREL64 = 48, // Empty relocation + R_MIPS_TLS_TPREL64 = 48, R_MIPS_TLS_TPREL_HI16 = 49, R_MIPS_TLS_TPREL_LO16 = 50, R_MIPS_GLOB_DAT = 51, + // These relocs are used for the mips16. R_MIPS16_26 = 100, R_MIPS16_GPREL = 101, R_MIPS16_GOT16 = 102, R_MIPS16_CALL16 = 103, R_MIPS16_HI16 = 104, R_MIPS16_LO16 = 105, + R_MIPS16_TLS_GD = 106, + R_MIPS16_TLS_LDM = 107, + R_MIPS16_TLS_DTPREL_HI16 = 108, + R_MIPS16_TLS_DTPREL_LO16 = 109, + R_MIPS16_TLS_GOTTPREL = 110, + R_MIPS16_TLS_TPREL_HI16 = 111, + R_MIPS16_TLS_TPREL_LO16 = 112, + R_MIPS_COPY = 126, R_MIPS_JUMP_SLOT = 127, + + // These relocations are specific to microMIPS. + R_MICROMIPS_26_S1 = 133, + R_MICROMIPS_HI16 = 134, + R_MICROMIPS_LO16 = 135, + R_MICROMIPS_GPREL16 = 136, // In Elf 64: alias R_MICROMIPS_GPREL + R_MICROMIPS_LITERAL = 137, + R_MICROMIPS_GOT16 = 138, // In Elf 64: alias R_MICROMIPS_GOT + R_MICROMIPS_PC7_S1 = 139, + R_MICROMIPS_PC10_S1 = 140, + R_MICROMIPS_PC16_S1 = 141, + R_MICROMIPS_CALL16 = 142, // In Elf 64: alias R_MICROMIPS_CALL + R_MICROMIPS_GOT_DISP = 145, + R_MICROMIPS_GOT_PAGE = 146, + R_MICROMIPS_GOT_OFST = 147, + R_MICROMIPS_GOT_HI16 = 148, + R_MICROMIPS_GOT_LO16 = 149, + R_MICROMIPS_SUB = 150, + R_MICROMIPS_HIGHER = 151, + R_MICROMIPS_HIGHEST = 152, + R_MICROMIPS_CALL_HI16 = 153, + R_MICROMIPS_CALL_LO16 = 154, + R_MICROMIPS_SCN_DISP = 155, + R_MICROMIPS_JALR = 156, + R_MICROMIPS_HI0_LO16 = 157, + // TLS relocations. + R_MICROMIPS_TLS_GD = 162, + R_MICROMIPS_TLS_LDM = 163, + R_MICROMIPS_TLS_DTPREL_HI16 = 164, + R_MICROMIPS_TLS_DTPREL_LO16 = 165, + R_MICROMIPS_TLS_GOTTPREL = 166, + R_MICROMIPS_TLS_TPREL_HI16 = 169, + R_MICROMIPS_TLS_TPREL_LO16 = 170, + // microMIPS GP- and PC-relative relocations. + R_MICROMIPS_GPREL7_S2 = 172, + R_MICROMIPS_PC23_S2 = 173, + + // This was a GNU extension used by embedded-PIC. It was co-opted by + // mips-linux for exception-handling data. GCC stopped using it in + // May, 2004, then started using it again for compact unwind tables. R_MIPS_PC32 = 248, + R_MIPS_EH = 249, + // This relocation is used internally by gas. R_MIPS_GNU_REL16_S2 = 250, + // These are GNU extensions to enable C++ vtable garbage collection. R_MIPS_GNU_VTINHERIT = 253, R_MIPS_GNU_VTENTRY = 254 }; -// Processor specific flags for the ELF header e_flags field. */ +// Processor specific flags for the ELF header e_flags field. enum { // At least one .noreorder directive appears in the source. @@ -164,6 +218,7 @@ enum E_MIPS_MACH_OCTEON = 0x008b0000, E_MIPS_MACH_XLR = 0x008c0000, E_MIPS_MACH_OCTEON2 = 0x008d0000, + E_MIPS_MACH_OCTEON3 = 0x008e0000, E_MIPS_MACH_5400 = 0x00910000, E_MIPS_MACH_5500 = 0x00980000, E_MIPS_MACH_9000 = 0x00990000, @@ -195,6 +250,10 @@ enum E_MIPS_ARCH_32R2 = 0x70000000, // -mips64r2 code. E_MIPS_ARCH_64R2 = 0x80000000, + // -mips32r6 code. + E_MIPS_ARCH_32R6 = 0x90000000, + // -mips64r6 code. + E_MIPS_ARCH_64R6 = 0xa0000000, }; enum @@ -235,6 +294,10 @@ enum // Note that one of the MIPS16 bits overlaps with STO_MIPS_PIC. STO_MIPS_ISA = 0xc0, + // The mask spanning the rest of MIPS psABI flags. At most one is expected + // to be set except for STO_MIPS16. + STO_MIPS_FLAGS = ~(STO_MIPS_ISA | 0x3), + // The MIPS psABI was updated in 2008 with support for PLTs and copy // relocs. There are therefore two types of nonzero SHN_UNDEF functions: // PLT entries and traditional MIPS lazy binding stubs. We mark the former @@ -262,6 +325,57 @@ enum DTP_OFFSET = 0x8000 }; + +bool +elf_st_is_mips16(unsigned char st_other) +{ return (st_other & elfcpp::STO_MIPS16) == elfcpp::STO_MIPS16; } + +bool +elf_st_is_micromips(unsigned char st_other) +{ return (st_other & elfcpp::STO_MIPS_ISA) == elfcpp::STO_MICROMIPS; } + +// Whether the ABI is N32. +bool +abi_n32(elfcpp::Elf_Word e_flags) +{ return (e_flags & elfcpp::EF_MIPS_ABI2) != 0; } + +// Whether the ABI is N64. +bool +abi_64(unsigned char ei_class) +{ return ei_class == elfcpp::ELFCLASS64; } + +// Whether the file has microMIPS code. +bool +is_micromips(elfcpp::Elf_Word e_flags) +{ return (e_flags & elfcpp::EF_MIPS_ARCH_ASE_MICROMIPS) != 0; } + +// Values which may appear in the kind field of an Elf_Options structure. +enum +{ + // Undefined. + ODK_NULL = 0, + // Register usage and GP value. + ODK_REGINFO = 1, + // Exception processing information. + ODK_EXCEPTIONS = 2, + // Section padding information. + ODK_PAD = 3, + // Hardware workarounds performed. + ODK_HWPATCH = 4, + // Fill value used by the linker. + ODK_FILL = 5, + // Reserved space for desktop tools. + ODK_TAGS = 6, + // Hardware workarounds, AND bits when merging. + ODK_HWAND = 7, + // Hardware workarounds, OR bits when merging. + ODK_HWOR = 8, + // GP group to use for text/data sections. + ODK_GP_GROUP = 9, + // ID information. + ODK_IDENT = 10 +}; + } // End namespace elfcpp. #endif // !defined(ELFCPP_MIPS_H) diff --git a/binutils-2.24/gas/ChangeLog b/binutils-2.24/gas/ChangeLog index 7fafa26..1bcaa36 100644 --- a/binutils-2.24/gas/ChangeLog +++ b/binutils-2.24/gas/ChangeLog @@ -1,3 +1,157 @@ +2014-05-20 Richard Sandiford <rdsandiford@googlemail.com> + + * config/obj-elf.h (obj_elf_seen_attribute): Declare. + * config/obj-elf.c (recorded_attribute_info): New structure. + (recorded_attributes): New variable. + (record_attribute, obj_elf_seen_attribute): New functions. + (obj_elf_vendor_attribute): Record which attributes have been seen. + +2014-05-20 Matthew Fortune <matthew.fortune@imgtec.com> + + * config/tc-mips.c (file_mips_opts_checked): New static global. + (s_module): New static function. + (file_ase): Remove. + (mips_pseudo_table): Add .module handler. + (mips_set_ase): Add opts argument and use instead of mips_opts. + (md_assemble): Use file_mips_check_options. + (md_parse_option): Update to use file_mips_opts instead of mips_opts. + (mips_set_architecture): Delete function. Moved to... + (mips_after_parse_args): Here. All logic now applies to + file_mips_opts first and then copies the final state to mips_opts. + Move error checking and defaults inference to mips_check_options and + file_mips_check_options. + (mips_check_options): New static function. Common option checking for + command line, .module and .set. Use .module values in error messages + instead of refering to command line options. + (file_mips_check_options): New static function. A wrapper for + mips_check_options with file_mips_opts. Updates BFD arch based on + final options. + (s_mipsset): Split into s_mipsset and parse_code_option. Settings + supported by both .set and .module are moved to parse_code_option. + Warnings and errors are kept in s_mipsset because when + parse_code_option is used with s_module the warnings are deferred + until code is generated. Any setting supporting 'default' value is + kept in s_mipsset as it is not applicable to s_module. Inferred + settings are also kept in s_mipsset as s_module does not infer any + settings. Use mips_check_options. + (parse_code_option): New static function derived from s_mipsset. + (s_module): New static function that implements .module. Allows file + level settings to be changed until code is generated. + (s_cpload, s_cpsetup, s_cplocal): Use file_mips_check_options. + (s_cprestore, s_cpreturn, s_cpadd, mips_address_bytes): Likewise. + (mips_elf_final_processing): Update file_ase to file_mips_opts.ase. + (md_mips_end): Use file_mips_check_options. + * doc/c-mips.texi: Document .module. + +2014-05-20 Matthew Fortune <matthew.fortune@imgtec.com> + + * config/tc-mips.c (FP64_ASES): Add ASE_MSA. + (mips_after_parse_args): Do not select ASE_MSA without -mfp64. + +2014-05-18 Richard Sandiford <rdsandiford@googlemail.com> + + * config/tc-mips.c (md_obj_begin): Delete. + (md_obj_end): Fold into... + (md_mips_end): ...here. Move to end of file. + +2014-05-13 Matthew Fortune <matthew.fortune@imgtec.com> + + * config/tc-mips.c (mips_set_options): Rename gp32 to gp throughout. + (HAVE_32BIT_GPRS, HAVE_64BIT_GPRS): Remove. Re-implement via GPR_SIZE. + (HAVE_32BIT_FPRS, HAVE_64BIT_FPRS): Remove. Re-implement via FPR_SIZE. + (GPR_SIZE, FPR_SIZE): New macros. Use throughout. + +2014-05-08 Matthew Fortune <matthew.fortune@imgtec.com> + + * config/tc-mips.c (md_parse_option): Update missed file_mips_isa + references. + +2014-05-08 Matthew Fortune <matthew.fortune@imgtec.com> + + * config/tc-mips.c (mips_set_options): Rename fp32 field to fp. + Update fp32 == 0 to fp == 64 and fp32 == 1 to fp != 64 throughout. + (file_mips_gp32, file_mips_fp32, file_mips_soft_float, + file_mips_single_float, file_mips_isa, file_mips_arch): Merge into + one struct... + (file_mips_opts): Here. New static global. Update throughout. + (mips_opts): Update defaults for gp32 and fp. + +2014-05-08 Matthew Fortune <matthew.fortune@imgtec.com> + + * config/tc-mips.c (streq): Define. + (mips_convert_symbolic_attribute): New function. + * config/tc-mips.h (CONVERT_SYMBOLIC_ATTRIBUTE): Define. + (mips_convert_symbolic_attribute): New prototype. + +2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com> + + * tc-mips.c (ISA_SUPPORTS_MIPS16E): Add mips32r3, mips32r5, mips64r3 + and mips64r5. + (ISA_HAS_64BIT_FPRS): Likewise. + (ISA_HAS_ROR): Likewise. + (ISA_HAS_ODD_SINGLE_FPR): Likewise. + (ISA_HAS_MXHC1): Likewise. + (hilo_interlocks): Likewise. + (md_longopts): Likewise. + (ISA_HAS_64BIT_REGS): Add mips64r3 and mips64r5. + (ISA_HAS_DROR): Likewise. + (options): Add OPTION_MIPS32R3, OPTION_MIPS32R5, OPTION_MIPS64R3, and + OPTION_MIPS64R5. + (mips_isa_rev): Add support for mips32r3, mips32r5, mips64r3 and + mips64r5. + (md_parse_option): Likewise. + (s_mipsset): Likewise. + (mips_cpu_info_table): Add entries for mips32r3, mips32r5, mips64r3 + and mips64r5. Also change p5600 entry to be mips32r5. + * configure.in: Add support for mips32r3, mips32r5, mips64r3 and + mips64r5. + * configure: Regenerate. + * doc/c-mips.texi: Document the -mips32r3, -mips32r5, -mips64r3 and + -mips64r5 command line options. + * doc/as.texinfo: Likewise. + +2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com> + + * config/tc-mips.c (options): Add OPTION_XPA and OPTION_NO_XPA. + (md_longopts): Add xpa and no-xpa command line options. + (mips_ases): Add MIPS XPA ASE. + (mips_cpu_info_table): Update p5600 entry to allow the XPA ASE. + * doc/as.texinfo: Document the MIPS XPA command line options. + * doc/c-mips.texi: Document the MIPS XPA command line options, + and assembler directives. + +2014-04-10 Andrew Bennett <andrew.bennett@imgtec.com> + + * config/tc-mips.c (mips_cpu_info_table): Add P5600 + configuation. + * doc/c-mips.texi: Document p5600. + +2014-03-20 Richard Sandiford <rdsandiford@googlemail.com> + + * config/tc-mips.h (DIFF_EXPR_OK, CFI_DIFF_EXPR_OK): Define. + * config/tc-mips.c (md_pcrel_from): Remove error message. + (md_apply_fix): Convert PC-relative BFD_RELOC_32s to + BFD_RELOC_32_PCREL. Report a specific error message for unhandled + PC-relative expressions. Handle BFD_RELOC_8. + +2014-03-04 Heiher <r@hev.cc> + + * config/tc-mips.c (mips_cpu_info_table): Use ISA_MIPS64R2 for + Loongson-3A. + +2013-11-19 Catherine Moore <clm@codesourcery.com> + + * config/tc-mips.c (mips_fix_pmc_rm7000): Declare. + (options): Add OPTION_FIX_PMC_RM7000 and OPTION_NO_FIX_PMC_RM7000. + (md_longopts): Add mfix-pmc-rm7000 and mno-fix-pmc-rm7000. + (INSN_DMULT): Define. + (INSN_DMULTU): Define. + (insns_between): Detect PMC RM7000 errata. + (md_parse_option): Supprt OPTION_FIX_PMC_RM7000 and + OPTION_NO_FIX_PMC_RM7000. + * doc/as.texinfo: Document new options. + * doc/c-mips.texi: Likewise. + 2013-11-18 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (lex_got): Add a dummy "int bnd_prefix" @@ -113,6 +267,38 @@ * config/tc-aarch64.c (parse_operands): Avoid trying to parse a vector register as an immediate. +2013-10-18 Chao-ying Fu <Chao-ying.Fu@imgtec.com> + + * config/tc-mips.c (fpr_read_mask): Test MSA registers. + (fpr_write_mask): Test MSA registers. + (can_swap_branch_p): Check fpr write followed by fpr read. + +2013-10-14 Richard Sandiford <rdsandiford@googlemail.com> + Chao-ying Fu <Chao-ying.Fu@imgtec.com> + + * config/tc-mips.c (options): Add OPTION_MSA and OPTION_NO_MSA. + (md_longopts): Add mmsa and mno-msa. + (mips_ases): Add msa. + (RTYPE_MASK): Update. + (RTYPE_MSA): New define. + (OT_REG_ELEMENT): Replace with... + (OT_INTEGER_INDEX, OT_REG_INDEX): ...these new operand types. + (mips_operand_token): Replace reg_element with index. + (mips_parse_argument_token): Treat vector indices as separate tokens. + Handle register indices. + (md_begin): Add MSA register names. + (operand_reg_mask): Handle cases for OP_IMM_INDEX and OP_REG_INDEX. + (convert_reg_type): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL. + (match_mdmx_imm_reg_operand): Update accordingly. + (match_imm_index_operand): New function. + (match_reg_index_operand): New function. + (match_operand): Handle cases for OP_IMM_INDEX and OP_REG_INDEX. + (md_convert_frag): Convert bz.b/h/w/d, bnz.b/h/w/d, bz.v bnz.v. + (md_show_usage): Print -mmsa and -mno-msa. + * doc/as.texinfo: Document -mmsa and -mno-msa. + * doc/c-mips.texi: Document -mmsa and -mno-msa. + Document .set msa and .set nomsa. + 2013-09-20 Alan Modra <amodra@gmail.com> * configure: Regenerate. diff --git a/binutils-2.24/gas/config/obj-elf.c b/binutils-2.24/gas/config/obj-elf.c index 3377261..1991655 100644 --- a/binutils-2.24/gas/config/obj-elf.c +++ b/binutils-2.24/gas/config/obj-elf.c @@ -1460,6 +1460,62 @@ skip_past_char (char ** str, char c) } #define skip_past_comma(str) skip_past_char (str, ',') +/* A list of attributes that have been explicitly set by the assembly code. + VENDOR is the vendor id, BASE is the tag shifted right by the number + of bits in MASK, and bit N of MASK is set if tag BASE+N has been set. */ +struct recorded_attribute_info { + struct recorded_attribute_info *next; + int vendor; + unsigned int base; + unsigned long mask; +}; +static struct recorded_attribute_info *recorded_attributes; + +/* Record that we have seen an explicit specification of attribute TAG + for vendor VENDOR. */ + +static void +record_attribute (int vendor, unsigned int tag) +{ + unsigned int base; + unsigned long mask; + struct recorded_attribute_info *rai; + + base = tag / (8 * sizeof (rai->mask)); + mask = 1UL << (tag % (8 * sizeof (rai->mask))); + for (rai = recorded_attributes; rai; rai = rai->next) + if (rai->vendor == vendor && rai->base == base) + { + rai->mask |= mask; + return; + } + + rai = XNEW (struct recorded_attribute_info); + rai->next = recorded_attributes; + rai->vendor = vendor; + rai->base = base; + rai->mask = mask; + recorded_attributes = rai; +} + +/* Return true if we have seen an explicit specification of attribute TAG + for vendor VENDOR. */ + +bfd_boolean +obj_elf_seen_attribute (int vendor, unsigned int tag) +{ + unsigned int base; + unsigned long mask; + struct recorded_attribute_info *rai; + + base = tag / (8 * sizeof (rai->mask)); + mask = 1UL << (tag % (8 * sizeof (rai->mask))); + for (rai = recorded_attributes; rai; rai = rai->next) + if (rai->vendor == vendor && rai->base == base) + return (rai->mask & mask) != 0; + return FALSE; +} + /* Parse an attribute directive for VENDOR. Returns the attribute number read, or zero on error. */ @@ -1542,6 +1598,7 @@ obj_elf_vendor_attribute (int vendor) s = demand_copy_C_string (&len); } + record_attribute (vendor, tag); switch (type & 3) { case 3: diff --git a/binutils-2.24/gas/config/obj-elf.h b/binutils-2.24/gas/config/obj-elf.h index d4fd4d5..5db80d3 100644 --- a/binutils-2.24/gas/config/obj-elf.h +++ b/binutils-2.24/gas/config/obj-elf.h @@ -167,6 +167,8 @@ extern void obj_elf_change_section (const char *, int, bfd_vma, int, const char *, int, int); extern struct fix *obj_elf_vtable_inherit (int); extern struct fix *obj_elf_vtable_entry (int); +extern bfd_boolean obj_elf_seen_attribute + (int, unsigned int); extern int obj_elf_vendor_attribute (int); /* BFD wants to write the udata field, which is a no-no for the diff --git a/binutils-2.24/gas/config/tc-mips.c b/binutils-2.24/gas/config/tc-mips.c index dd61d72..05faec7 100644 --- a/binutils-2.24/gas/config/tc-mips.c +++ b/binutils-2.24/gas/config/tc-mips.c @@ -44,6 +44,8 @@ typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; #define DBG(x) #endif +#define streq(a, b) (strcmp (a, b) == 0) + #define SKIP_SPACE_TABS(S) \ do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) @@ -89,6 +91,7 @@ int mips_flag_pdr = TRUE; #include "ecoff.h" static char *mips_regmask_frag; +static char *mips_flags_frag; #define ZERO 0 #define ATREG 1 @@ -241,8 +244,8 @@ struct mips_set_options /* Restrict general purpose registers and floating point registers to 32 bit. This is initially determined when -mgp32 or -mfp32 is passed but can changed if the assembler code uses .set mipsN. */ - int gp32; - int fp32; + int gp; + int fp; /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march command line option, and the default CPU. */ int arch; @@ -257,40 +260,45 @@ struct mips_set_options Changed by .set singlefloat or .set doublefloat, command-line options -msingle-float or -mdouble-float. The default is false. */ bfd_boolean single_float; -}; -/* This is the struct we use to hold the current set of options. Note - that we must set the isa field to ISA_UNKNOWN and the ASE fields to - -1 to indicate that they have not been initialized. */ + /* 1 if single-precision operations on odd-numbered registers are + not allowed (even if supported by ISA_HAS_ODD_SINGLE_FPR). */ + int nooddspreg; +}; -/* True if -mgp32 was passed. */ -static int file_mips_gp32 = -1; +/* Specifies whether module level options have been checked yet. */ +static bfd_boolean file_mips_opts_checked = FALSE; -/* True if -mfp32 was passed. */ -static int file_mips_fp32 = -1; +/* Do we support nan2008? 0 if we don't, 1 if we do, and -1 if the + value has not been initialized. Changed by `.nan legacy' and + `.nan 2008', and the -mnan=legacy and -mnan=2008 command line + options, and the default CPU. */ +static int mips_nan2008 = -1; -/* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ -static int file_mips_soft_float = 0; +/* This is the struct we use to hold the module level set of options. + Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and + fp fields to -1 to indicate that they have not been initialized. */ -/* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ -static int file_mips_single_float = 0; +static struct mips_set_options file_mips_opts = +{ + /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, + /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, + /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, + /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, + /* soft_float */ FALSE, /* single_float */ FALSE, /* nooddspreg */ -1 +}; -/* True if -mnan=2008, false if -mnan=legacy. */ -static bfd_boolean mips_flag_nan2008 = FALSE; +/* This is similar to file_mips_opts, but for the current set of options. */ static struct mips_set_options mips_opts = { /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, - /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, - /* soft_float */ FALSE, /* single_float */ FALSE + /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, + /* soft_float */ FALSE, /* single_float */ FALSE, /* nooddspreg */ -1 }; -/* The set of ASEs that were selected on the command line, either - explicitly via ASE options or implicitly through things like -march. */ -static unsigned int file_ase; - /* Which bits of file_ase were explicitly set or cleared by ASE options. */ static unsigned int file_ase_explicit; @@ -300,16 +308,17 @@ static unsigned int file_ase_explicit; unsigned long mips_gprmask; unsigned long mips_cprmask[4]; -/* MIPS ISA we are using for this output file. */ -static int file_mips_isa = ISA_UNKNOWN; - /* True if any MIPS16 code was produced. */ static int file_ase_mips16; #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ || mips_opts.isa == ISA_MIPS32R2 \ + || mips_opts.isa == ISA_MIPS32R3 \ + || mips_opts.isa == ISA_MIPS32R5 \ || mips_opts.isa == ISA_MIPS64 \ - || mips_opts.isa == ISA_MIPS64R2) + || mips_opts.isa == ISA_MIPS64R2 \ + || mips_opts.isa == ISA_MIPS64R3 \ + || mips_opts.isa == ISA_MIPS64R5) /* True if any microMIPS code was produced. */ static int file_ase_micromips; @@ -327,7 +336,6 @@ static int file_ase_micromips; #endif /* The argument of the -march= flag. The architecture we are assembling. */ -static int file_mips_arch = CPU_UNKNOWN; static const char *mips_arch_string; /* The argument of the -mtune= flag. The architecture for which we @@ -347,13 +355,20 @@ static int mips_32bitmode = 0; || (ABI) == N64_ABI \ || (ABI) == O64_ABI) +#define ISA_IS_R6(ISA) \ + ((ISA) == ISA_MIPS32R6 \ + || (ISA) == ISA_MIPS64R6) + /* Return true if ISA supports 64 bit wide gp registers. */ #define ISA_HAS_64BIT_REGS(ISA) \ ((ISA) == ISA_MIPS3 \ || (ISA) == ISA_MIPS4 \ || (ISA) == ISA_MIPS5 \ || (ISA) == ISA_MIPS64 \ - || (ISA) == ISA_MIPS64R2) + || (ISA) == ISA_MIPS64R2 \ + || (ISA) == ISA_MIPS64R3 \ + || (ISA) == ISA_MIPS64R5 \ + || (ISA) == ISA_MIPS64R6) /* Return true if ISA supports 64 bit wide float registers. */ #define ISA_HAS_64BIT_FPRS(ISA) \ @@ -361,13 +376,22 @@ static int mips_32bitmode = 0; || (ISA) == ISA_MIPS4 \ || (ISA) == ISA_MIPS5 \ || (ISA) == ISA_MIPS32R2 \ + || (ISA) == ISA_MIPS32R3 \ + || (ISA) == ISA_MIPS32R5 \ + || (ISA) == ISA_MIPS32R6 \ || (ISA) == ISA_MIPS64 \ - || (ISA) == ISA_MIPS64R2) + || (ISA) == ISA_MIPS64R2 \ + || (ISA) == ISA_MIPS64R3 \ + || (ISA) == ISA_MIPS64R5 \ + || (ISA) == ISA_MIPS64R6) /* Return true if ISA supports 64-bit right rotate (dror et al.) instructions. */ #define ISA_HAS_DROR(ISA) \ ((ISA) == ISA_MIPS64R2 \ + || (ISA) == ISA_MIPS64R3 \ + || (ISA) == ISA_MIPS64R5 \ + || (ISA) == ISA_MIPS64R6 \ || (mips_opts.micromips \ && ISA_HAS_64BIT_REGS (ISA)) \ ) @@ -376,32 +400,69 @@ static int mips_32bitmode = 0; instructions. */ #define ISA_HAS_ROR(ISA) \ ((ISA) == ISA_MIPS32R2 \ + || (ISA) == ISA_MIPS32R3 \ + || (ISA) == ISA_MIPS32R5 \ + || (ISA) == ISA_MIPS32R6 \ || (ISA) == ISA_MIPS64R2 \ + || (ISA) == ISA_MIPS64R3 \ + || (ISA) == ISA_MIPS64R5 \ + || (ISA) == ISA_MIPS64R6 \ || (mips_opts.ase & ASE_SMARTMIPS) \ || mips_opts.micromips \ ) /* Return true if ISA supports single-precision floats in odd registers. */ -#define ISA_HAS_ODD_SINGLE_FPR(ISA) \ - ((ISA) == ISA_MIPS32 \ - || (ISA) == ISA_MIPS32R2 \ - || (ISA) == ISA_MIPS64 \ - || (ISA) == ISA_MIPS64R2) +#define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ + (((ISA) == ISA_MIPS32 \ + || (ISA) == ISA_MIPS32R2 \ + || (ISA) == ISA_MIPS32R3 \ + || (ISA) == ISA_MIPS32R5 \ + || (ISA) == ISA_MIPS32R6 \ + || (ISA) == ISA_MIPS64 \ + || (ISA) == ISA_MIPS64R2 \ + || (ISA) == ISA_MIPS64R3 \ + || (ISA) == ISA_MIPS64R5 \ + || (ISA) == ISA_MIPS64R6 \ + || (CPU) == CPU_R5900) \ + && (CPU) != CPU_LOONGSON_3A) /* Return true if ISA supports move to/from high part of a 64-bit floating-point register. */ #define ISA_HAS_MXHC1(ISA) \ ((ISA) == ISA_MIPS32R2 \ - || (ISA) == ISA_MIPS64R2) - -#define HAVE_32BIT_GPRS \ - (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) + || (ISA) == ISA_MIPS32R3 \ + || (ISA) == ISA_MIPS32R5 \ + || (ISA) == ISA_MIPS32R6 \ + || (ISA) == ISA_MIPS64R2 \ + || (ISA) == ISA_MIPS64R3 \ + || (ISA) == ISA_MIPS64R5 \ + || (ISA) == ISA_MIPS64R6) + +/* Return true if ISA supports legacy NAN. */ +#define ISA_HAS_LEGACY_NAN(ISA) \ + ((ISA) == ISA_MIPS1 \ + || (ISA) == ISA_MIPS2 \ + || (ISA) == ISA_MIPS3 \ + || (ISA) == ISA_MIPS4 \ + || (ISA) == ISA_MIPS5 \ + || (ISA) == ISA_MIPS32 \ + || (ISA) == ISA_MIPS32R2 \ + || (ISA) == ISA_MIPS32R3 \ + || (ISA) == ISA_MIPS32R5 \ + || (ISA) == ISA_MIPS64 \ + || (ISA) == ISA_MIPS64R2 \ + || (ISA) == ISA_MIPS64R3 \ + || (ISA) == ISA_MIPS64R5) -#define HAVE_32BIT_FPRS \ - (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) +#define GPR_SIZE \ + (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ + ? 32 \ + : mips_opts.gp) -#define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) -#define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) +#define FPR_SIZE \ + (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ + ? 32 \ + : mips_opts.fp) #define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) @@ -412,7 +473,7 @@ static int mips_32bitmode = 0; /* The ABI-derived address size. */ #define HAVE_64BIT_ADDRESSES \ - (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) + (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) #define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) /* The size of symbolic constants (i.e., expressions of the form @@ -475,8 +536,14 @@ static int mips_32bitmode = 0; #define hilo_interlocks \ (mips_opts.isa == ISA_MIPS32 \ || mips_opts.isa == ISA_MIPS32R2 \ + || mips_opts.isa == ISA_MIPS32R3 \ + || mips_opts.isa == ISA_MIPS32R5 \ + || mips_opts.isa == ISA_MIPS32R6 \ || mips_opts.isa == ISA_MIPS64 \ || mips_opts.isa == ISA_MIPS64R2 \ + || mips_opts.isa == ISA_MIPS64R3 \ + || mips_opts.isa == ISA_MIPS64R5 \ + || mips_opts.isa == ISA_MIPS64R6 \ || mips_opts.arch == CPU_R4010 \ || mips_opts.arch == CPU_R5900 \ || mips_opts.arch == CPU_R10000 \ @@ -491,7 +558,7 @@ static int mips_32bitmode = 0; /* Whether the processor uses hardware interlocks to protect reads from the GPRs after they are loaded from memory, and thus does not require nops to be inserted. This applies to instructions marked - INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA + INSN_LOAD_MEMORY. These nops are only required at MIPS ISA level I and microMIPS mode instructions are always interlocked. */ #define gpr_interlocks \ (mips_opts.isa != ISA_MIPS1 \ @@ -539,7 +606,7 @@ static int mips_32bitmode = 0; ((mips_opts.mips16 | mips_opts.micromips) != 0) /* The minimum and maximum signed values that can be stored in a GPR. */ -#define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1)) +#define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) #define GPR_SMIN (-GPR_SMAX - 1) /* MIPS PIC level. */ @@ -865,6 +932,9 @@ static int mips_fix_vr4130; /* ...likewise -mfix-24k. */ static int mips_fix_24k; +/* ...likewise -mfix-rm7000 */ +static int mips_fix_rm7000; + /* ...likewise -mfix-cn63xxp1 */ static bfd_boolean mips_fix_cn63xxp1; @@ -1268,8 +1338,7 @@ static void s_ehword (int); static void s_cpadd (int); static void s_insn (int); static void s_nan (int); -static void md_obj_begin (void); -static void md_obj_end (void); +static void s_module (int); static void s_mips_ent (int); static void s_mips_end (int); static void s_mips_frame (int); @@ -1282,6 +1351,7 @@ static bfd_boolean pic_need_relax (symbolS *, asection *); static int relaxed_branch_length (fragS *, asection *, int); static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); +static void file_mips_check_options (void); /* Table and functions used to map between CPU/ISA names, and ISA levels, and CPU numbers. */ @@ -1316,7 +1386,13 @@ enum options OPTION_MIPS32, OPTION_MIPS64, OPTION_MIPS32R2, + OPTION_MIPS32R3, + OPTION_MIPS32R5, + OPTION_MIPS32R6, OPTION_MIPS64R2, + OPTION_MIPS64R3, + OPTION_MIPS64R5, + OPTION_MIPS64R6, OPTION_MIPS16, OPTION_NO_MIPS16, OPTION_MIPS3D, @@ -1329,12 +1405,16 @@ enum options OPTION_NO_MT, OPTION_VIRT, OPTION_NO_VIRT, + OPTION_MSA, + OPTION_NO_MSA, OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_EVA, OPTION_NO_EVA, + OPTION_XPA, + OPTION_NO_XPA, OPTION_MICROMIPS, OPTION_NO_MICROMIPS, OPTION_MCU, @@ -1352,6 +1432,8 @@ enum options OPTION_MNO_7000_HILO_FIX, OPTION_FIX_24K, OPTION_NO_FIX_24K, + OPTION_FIX_RM7000, + OPTION_NO_FIX_RM7000, OPTION_FIX_LOONGSON2F_JUMP, OPTION_NO_FIX_LOONGSON2F_JUMP, OPTION_FIX_LOONGSON2F_NOP, @@ -1371,6 +1453,7 @@ enum options OPTION_CONSTRUCT_FLOATS, OPTION_NO_CONSTRUCT_FLOATS, OPTION_FP64, + OPTION_FPXX, OPTION_GP64, OPTION_RELAX_BRANCH, OPTION_NO_RELAX_BRANCH, @@ -1398,6 +1481,8 @@ enum options OPTION_NO_PDR, OPTION_MVXWORKS_PIC, OPTION_NAN, + OPTION_ODD_SPREG, + OPTION_NO_ODD_SPREG, OPTION_END_OF_ENUM }; @@ -1415,7 +1500,13 @@ struct option md_longopts[] = {"mips32", no_argument, NULL, OPTION_MIPS32}, {"mips64", no_argument, NULL, OPTION_MIPS64}, {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, + {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, + {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, + {"mips32r6", no_argument, NULL, OPTION_MIPS32R6}, {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, + {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, + {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, + {"mips64r6", no_argument, NULL, OPTION_MIPS64R6}, /* Options which specify Application Specific Extensions (ASEs). */ {"mips16", no_argument, NULL, OPTION_MIPS16}, @@ -1440,6 +1531,10 @@ struct option md_longopts[] = {"mno-mcu", no_argument, NULL, OPTION_NO_MCU}, {"mvirt", no_argument, NULL, OPTION_VIRT}, {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, + {"mmsa", no_argument, NULL, OPTION_MSA}, + {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, + {"mxpa", no_argument, NULL, OPTION_XPA}, + {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, /* Old-style architecture options. Don't add more of these. */ {"m4650", no_argument, NULL, OPTION_M4650}, @@ -1465,6 +1560,8 @@ struct option md_longopts[] = {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130}, {"mfix-24k", no_argument, NULL, OPTION_FIX_24K}, {"mno-fix-24k", no_argument, NULL, OPTION_NO_FIX_24K}, + {"mfix-rm7000", no_argument, NULL, OPTION_FIX_RM7000}, + {"mno-fix-rm7000", no_argument, NULL, OPTION_NO_FIX_RM7000}, {"mfix-cn63xxp1", no_argument, NULL, OPTION_FIX_CN63XXP1}, {"mno-fix-cn63xxp1", no_argument, NULL, OPTION_NO_FIX_CN63XXP1}, @@ -1480,6 +1577,7 @@ struct option md_longopts[] = {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, {"mfp64", no_argument, NULL, OPTION_FP64}, + {"mfpxx", no_argument, NULL, OPTION_FPXX}, {"mgp64", no_argument, NULL, OPTION_GP64}, {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, @@ -1493,6 +1591,8 @@ struct option md_longopts[] = {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, + {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, + {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, /* Strictly speaking this next option is ELF specific, but we allow it for other ports as well in order to @@ -1546,51 +1646,77 @@ struct mips_ase int mips64_rev; int micromips32_rev; int micromips64_rev; + + /* The architecture revisions for MIPS32, MIPS64, microMIPS32 and microMIPS64 + where the ASE was removed or -1 if the extension has not been removed. */ + int mips32_rem_rev; + int mips64_rem_rev; + int micromips32_rem_rev; + int micromips64_rem_rev; }; /* A table of all supported ASEs. */ static const struct mips_ase mips_ases[] = { { "dsp", ASE_DSP, ASE_DSP64, OPTION_DSP, OPTION_NO_DSP, - 2, 2, 2, 2 }, + 2, 2, 2, 2, + 6, 6, 6, 6 }, { "dspr2", ASE_DSP | ASE_DSPR2, 0, OPTION_DSPR2, OPTION_NO_DSPR2, - 2, 2, 2, 2 }, + 2, 2, 2, 2, + 6, 6, 6, 6 }, { "eva", ASE_EVA, 0, OPTION_EVA, OPTION_NO_EVA, - 2, 2, 2, 2 }, + 2, 2, 2, 2, + -1, -1, -1, -1 }, { "mcu", ASE_MCU, 0, OPTION_MCU, OPTION_NO_MCU, - 2, 2, 2, 2 }, + 2, 2, 2, 2, + -1, -1, -1, -1 }, /* Deprecated in MIPS64r5, but we don't implement that yet. */ { "mdmx", ASE_MDMX, 0, OPTION_MDMX, OPTION_NO_MDMX, - -1, 1, -1, -1 }, + -1, 1, -1, -1, + -1, 6, -1, -1 }, /* Requires 64-bit FPRs, so the minimum MIPS32 revision is 2. */ { "mips3d", ASE_MIPS3D, 0, OPTION_MIPS3D, OPTION_NO_MIPS3D, - 2, 1, -1, -1 }, + 2, 1, -1, -1, + 6, 6, -1, -1 }, { "mt", ASE_MT, 0, OPTION_MT, OPTION_NO_MT, - 2, 2, -1, -1 }, + 2, 2, -1, -1, + -1, -1, -1, -1 }, { "smartmips", ASE_SMARTMIPS, 0, OPTION_SMARTMIPS, OPTION_NO_SMARTMIPS, - 1, -1, -1, -1 }, + 1, -1, -1, -1, + 6, -1, -1, -1 }, { "virt", ASE_VIRT, ASE_VIRT64, OPTION_VIRT, OPTION_NO_VIRT, - 2, 2, 2, 2 } + 2, 2, 2, 2, + -1, -1, -1, -1 }, + + { "msa", ASE_MSA, ASE_MSA64, + OPTION_MSA, OPTION_NO_MSA, + 2, 2, 2, 2, + -1, -1, -1, -1 }, + + { "xpa", ASE_XPA, 0, + OPTION_XPA, OPTION_NO_XPA, + 2, 2, -1, -1, + -1, -1, -1, -1 }, }; /* The set of ASEs that require -mfp64. */ -#define FP64_ASES (ASE_MIPS3D | ASE_MDMX) +#define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) /* Groups of ASE_* flags that represent different revisions of an ASE. */ static const unsigned int mips_ase_groups[] = { @@ -1639,6 +1765,7 @@ static const pseudo_typeS mips_pseudo_table[] = {"cpadd", s_cpadd, 0}, {"insn", s_insn, 0}, {"nan", s_nan, 0}, + {"module", s_module, 0}, /* Relatively generic pseudo-ops that happen to be used on MIPS chips. */ @@ -1706,6 +1833,7 @@ static const pseudo_typeS mips_nonecoff_pseudo_table[] = int mips_address_bytes (void) { + file_mips_check_options (); return HAVE_64BIT_ADDRESSES ? 8 : 4; } @@ -1840,6 +1968,15 @@ mips_isa_rev (void) if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) return 2; + if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) + return 3; + + if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) + return 5; + + if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6) + return 6; + /* microMIPS implies revision 2 or above. */ if (mips_opts.micromips) return 2; @@ -1870,14 +2007,22 @@ static void mips_check_isa_supports_ase (const struct mips_ase *ase) { const char *base; - int min_rev, size; + int size, min_rev, rem_rev; static unsigned int warned_isa; static unsigned int warned_fp32; if (ISA_HAS_64BIT_REGS (mips_opts.isa)) - min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; + { + min_rev = mips_opts.micromips ? ase->micromips64_rev : ase->mips64_rev; + rem_rev = mips_opts.micromips ? ase->micromips64_rem_rev + : ase->mips64_rem_rev; + } else - min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; + { + min_rev = mips_opts.micromips ? ase->micromips32_rev : ase->mips32_rev; + rem_rev = mips_opts.micromips ? ase->micromips32_rem_rev + : ase->mips32_rem_rev; + } if ((min_rev < 0 || mips_isa_rev () < min_rev) && (warned_isa & ase->flags) != ase->flags) { @@ -1891,8 +2036,18 @@ mips_check_isa_supports_ase (const struct mips_ase *ase) as_warn (_("the `%s' extension requires %s%d revision %d or greater"), ase->name, base, size, min_rev); } + if ((rem_rev > 0 && mips_isa_rev () >= rem_rev) + && (warned_isa & ase->flags) != ase->flags) + { + warned_isa |= ase->flags; + base = mips_opts.micromips ? "microMIPS" : "MIPS"; + size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32; + as_warn (_("the `%s' extension was removed in %s%d revision %d"), + ase->name, base, size, rem_rev); + } + if ((ase->flags & FP64_ASES) - && mips_opts.fp32 + && mips_opts.fp != 64 && (warned_fp32 & ase->flags) != ase->flags) { warned_fp32 |= ase->flags; @@ -1920,14 +2075,15 @@ mips_check_isa_supports_ases (void) that were affected. */ static unsigned int -mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p) +mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, + bfd_boolean enabled_p) { unsigned int mask; mask = mips_ase_mask (ase->flags); - mips_opts.ase &= ~mask; + opts->ase &= ~mask; if (enabled_p) - mips_opts.ase |= ase->flags; + opts->ase |= ase->flags; return mask; } @@ -2347,7 +2503,7 @@ struct regname { }; #define RNUM_MASK 0x00000ff -#define RTYPE_MASK 0x0efff00 +#define RTYPE_MASK 0x0ffff00 #define RTYPE_NUM 0x0000100 #define RTYPE_FPU 0x0000200 #define RTYPE_FCC 0x0000400 @@ -2363,6 +2519,7 @@ struct regname { #define RTYPE_R5900_Q 0x0100000 #define RTYPE_R5900_R 0x0200000 #define RTYPE_R5900_ACC 0x0400000 +#define RTYPE_MSA 0x0800000 #define RWARN 0x8000000 #define GENERIC_REGISTER_NUMBERS \ @@ -2747,8 +2904,11 @@ enum mips_operand_token_type { /* A 4-bit XYZW channel mask. */ OT_CHANNELS, - /* An element of a vector, e.g. $v0[1]. */ - OT_REG_ELEMENT, + /* A constant vector index, e.g. [1]. */ + OT_INTEGER_INDEX, + + /* A register vector index, e.g. [$2]. */ + OT_REG_INDEX, /* A continuous range of registers, e.g. $s0-$s4. */ OT_REG_RANGE, @@ -2777,17 +2937,14 @@ struct mips_operand_token enum mips_operand_token_type type; union { - /* The register symbol value for an OT_REG. */ + /* The register symbol value for an OT_REG or OT_REG_INDEX. */ unsigned int regno; /* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */ unsigned int channels; - /* The register symbol value and index for an OT_REG_ELEMENT. */ - struct { - unsigned int regno; - addressT index; - } reg_element; + /* The integer value of an OT_INTEGER_INDEX. */ + addressT index; /* The two register symbol values involved in an OT_REG_RANGE. */ struct { @@ -2948,20 +3105,32 @@ mips_parse_argument_token (char *s, char float_format) mips_add_token (&token, OT_REG_RANGE); return s; } - else if (*s == '[') - { - /* A vector element. */ - expressionS element; + /* Add the register itself. */ + token.u.regno = regno1; + mips_add_token (&token, OT_REG); + + /* Check for a vector index. */ + if (*s == '[') + { ++s; SKIP_SPACE_TABS (s); - my_getExpression (&element, s); - if (element.X_op != O_constant) + if (mips_parse_register (&s, &token.u.regno, NULL)) + mips_add_token (&token, OT_REG_INDEX); + else { - set_insn_error (0, _("vector element must be constant")); - return 0; + expressionS element; + + my_getExpression (&element, s); + if (element.X_op != O_constant) + { + set_insn_error (0, _("vector element must be constant")); + return 0; + } + s = expr_end; + token.u.index = element.X_add_number; + mips_add_token (&token, OT_INTEGER_INDEX); } - s = expr_end; SKIP_SPACE_TABS (s); if (*s != ']') { @@ -2969,16 +3138,7 @@ mips_parse_argument_token (char *s, char float_format) return 0; } ++s; - - token.u.reg_element.regno = regno1; - token.u.reg_element.index = element.X_add_number; - mips_add_token (&token, OT_REG_ELEMENT); - return s; } - - /* Looks like just a plain register. */ - token.u.regno = regno1; - mips_add_token (&token, OT_REG); return s; } @@ -3214,7 +3374,7 @@ validate_mips_insn (const struct mips_opcode *opcode, used_bits &= ~(mask & 0x700); } /* Skip prefix characters. */ - if (decode_operand && (*s == '+' || *s == 'm')) + if (decode_operand && (*s == '+' || *s == 'm' || *s == '-')) ++s; opno += 1; break; @@ -3319,7 +3479,7 @@ md_begin (void) g_switch_value = 0; } - if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) + if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) as_warn (_("could not set architecture and machine")); op_hash = hash_new (); @@ -3460,6 +3620,10 @@ md_begin (void) symbol_table_insert (symbol_new (regname, reg_section, RTYPE_VI | i, &zero_address_frag)); + /* MSA register. */ + snprintf (regname, sizeof (regname) - 1, "$w%d", i); + symbol_table_insert (symbol_new (regname, reg_section, + RTYPE_MSA | i, &zero_address_frag)); } obstack_init (&mips_operand_tokens); @@ -3541,6 +3705,12 @@ md_begin (void) } } + sec = subseg_new (".MIPS.abiflags", (subsegT) 0); + bfd_set_section_flags (stdoutput, sec, + SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); + bfd_set_section_alignment (stdoutput, sec, 3); + mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); + if (ECOFF_DEBUGGING) { sec = subseg_new (".mdebug", (subsegT) 0); @@ -3560,19 +3730,260 @@ md_begin (void) subseg_set (seg, subseg); } - if (! ECOFF_DEBUGGING) - md_obj_begin (); - if (mips_fix_vr4120) init_vr4120_conflicts (); } -void -md_mips_end (void) +static inline void +fpabi_incompatible_with (int fpabi, const char *what) { - mips_emit_delays (); - if (! ECOFF_DEBUGGING) - md_obj_end (); + as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), + Tag_GNU_MIPS_ABI_FP, fpabi, what); +} + +static inline void +fpabi_requires (int fpabi, const char *what) +{ + as_warn (_(".gnu_attribute %d,%d requires `%s'"), + Tag_GNU_MIPS_ABI_FP, fpabi, what); +} + +/* Check -mabi and register sizes against the specified FP ABI. */ +static void +check_fpabi (int fpabi) +{ + bfd_boolean needs_check = FALSE; + switch (fpabi) + { + case Val_GNU_MIPS_ABI_FP_DOUBLE: + if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) + fpabi_incompatible_with (fpabi, "gp=64 fp=32"); + else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) + fpabi_incompatible_with (fpabi, "gp=32 fp=64"); + else + needs_check = TRUE; + break; + + case Val_GNU_MIPS_ABI_FP_XX: + if (mips_abi != O32_ABI) + fpabi_requires (fpabi, "-mabi=32"); + else if (file_mips_opts.fp != 0) + fpabi_requires (fpabi, "fp=xx"); + else + needs_check = TRUE; + break; + + case Val_GNU_MIPS_ABI_FP_64A: + case Val_GNU_MIPS_ABI_FP_64: + if (mips_abi != O32_ABI) + fpabi_requires (fpabi, "-mabi=32"); + else if (file_mips_opts.fp == 32) + fpabi_incompatible_with (fpabi, "fp=32"); + else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && !file_mips_opts.nooddspreg) + fpabi_requires (fpabi, "-mno-odd-spreg"); + else + needs_check = TRUE; + break; + + case Val_GNU_MIPS_ABI_FP_SINGLE: + if (file_mips_opts.soft_float) + fpabi_incompatible_with (fpabi, "softfloat"); + else if (!file_mips_opts.single_float) + fpabi_requires (fpabi, "singlefloat"); + break; + + case Val_GNU_MIPS_ABI_FP_SOFT: + if (!file_mips_opts.soft_float) + fpabi_requires (fpabi, "softfloat"); + break; + + case Val_GNU_MIPS_ABI_FP_OLD_64: + as_warn (_(".gnu_attribute %d,%d is no longer supported"), + Tag_GNU_MIPS_ABI_FP, fpabi); + break; + + default: + as_warn (_(".gnu_attribute %d,%d is not a recognized" + " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); + break; + } + + if (needs_check && file_mips_opts.soft_float) + fpabi_incompatible_with (fpabi, "softfloat"); + else if (needs_check && file_mips_opts.single_float) + fpabi_incompatible_with (fpabi, "singlefloat"); +} + +/* Perform consistency checks on the current options. */ + +static void +mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) +{ + /* Check the size of integer registers agrees with the ABI and ISA. */ + if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) + as_bad (_("`gp=64' used with a 32-bit processor")); + else if (abi_checks + && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) + as_bad (_("`gp=32' used with a 64-bit ABI")); + else if (abi_checks + && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) + as_bad (_("`gp=64' used with a 32-bit ABI")); + + /* Check the size of the float registers agrees with the ABI and ISA. */ + switch (opts->fp) + { + case 0: + if (!CPU_HAS_LDC1_SDC1 (opts->arch)) + as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); + else if (opts->single_float == 1) + as_bad (_("`fp=xx' cannot be used with `singlefloat'")); + break; + case 64: + if (!ISA_HAS_64BIT_FPRS (opts->isa)) + as_bad (_("`fp=64' used with a 32-bit fpu")); + else if (abi_checks + && ABI_NEEDS_32BIT_REGS (mips_abi) + && !ISA_HAS_MXHC1 (opts->isa)) + as_warn (_("`fp=64' used with a 32-bit ABI")); + break; + case 32: + if (abi_checks + && ABI_NEEDS_64BIT_REGS (mips_abi)) + as_warn (_("`fp=32' used with a 64-bit ABI")); + if (ISA_IS_R6 (mips_opts.isa)) + as_bad (_("`fp=32' used with a MIPS R6 cpu")); + break; + default: + as_bad (_("Unknown size of floating point registers")); + break; + } + + if (opts->micromips == 1 && opts->mips16 == 1) + as_bad (_("`mips16' cannot be used with `micromips'")); + else if (ISA_IS_R6 (mips_opts.isa) + && (opts->micromips == 1 + || opts->mips16 == 1)) + as_fatal (_("neither `micromips' nor `mips16' can be used with " + "`mips32r6' or `mips64r6'")); + + if (ISA_IS_R6 (opts->isa) && mips_relax_branch) + as_fatal (_("branch relaxation is not supported in `mips32r6' " + "or `mips64r6'")); +} + +/* Perform consistency checks on the module level options exactly once. + This is a deferred check that happens: + at the first .set directive + or, at the first pseudo op that generates code (inc .dc.a) + or, at the first instruction + or, at the end. */ + +static void +file_mips_check_options (void) +{ + const struct mips_cpu_info *arch_info = 0; + + if (file_mips_opts_checked) + return; + + /* The following code determines the register size. + Similar code was added to GCC 3.3 (see override_options() in + config/mips/mips.c). The GAS and GCC code should be kept in sync + as much as possible. */ + + if (file_mips_opts.gp < 0) + { + /* Infer the integer register size from the ABI and processor. + Restrict ourselves to 32-bit registers if that's all the + processor has, or if the ABI cannot handle 64-bit registers. */ + file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) + || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) + ? 32 : 64; + } + + if (file_mips_opts.fp < 0) + { + /* No user specified float register size. + ??? GAS treats single-float processors as though they had 64-bit + float registers (although it complains when double-precision + instructions are used). As things stand, saying they have 32-bit + registers would lead to spurious "register must be even" messages. + So here we assume float registers are never smaller than the + integer ones. */ + if (file_mips_opts.gp == 64) + /* 64-bit integer registers implies 64-bit float registers. */ + file_mips_opts.fp = 64; + else if ((file_mips_opts.ase & FP64_ASES) + && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) + /* Handle ASEs that require 64-bit float registers, if possible. */ + file_mips_opts.fp = 64; + else if (ISA_IS_R6 (mips_opts.isa)) + /* R6 implies 64-bit float registers. */ + file_mips_opts.fp = 64; + else + /* 32-bit float registers. */ + file_mips_opts.fp = 32; + } + + arch_info = mips_cpu_info_from_arch (file_mips_opts.arch); + + /* Disable operations on odd-numbered floating-point registers by default + for generic MIPS cores when using the FPXX ABI. This only applies when + targetting 32-bit floating-point registers. */ + if (file_mips_opts.nooddspreg < 0) + { + /* This check is valid as long as all MIPS_CPU_IS_ISA entries for + MIPS 32 and above are associated with dummy CPU entries rather + than specific implementations. */ + if ((arch_info->flags & MIPS_CPU_IS_ISA) && file_mips_opts.fp == 0) + file_mips_opts.nooddspreg = 1; + else + file_mips_opts.nooddspreg = 0; + } + + /* End of GCC-shared inference code. */ + + /* This flag is set when we have a 64-bit capable CPU but use only + 32-bit wide registers. Note that EABI does not use it. */ + if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) + && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) + || mips_abi == O32_ABI)) + mips_32bitmode = 1; + + if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) + as_bad (_("trap exception not supported at ISA 1")); + + /* If the selected architecture includes support for ASEs, enable + generation of code for them. */ + if (file_mips_opts.mips16 == -1) + file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; + if (file_mips_opts.micromips == -1) + file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) + ? 1 : 0; + + if (mips_nan2008 == -1) + mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1; + else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0) + as_fatal (_("current isa does not support legacy NaN")); + + /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from + being selected implicitly. */ + if (file_mips_opts.fp != 64) + file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; + + /* If the user didn't explicitly select or deselect a particular ASE, + use the default setting for the CPU. */ + file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); + + /* Set up the current options. These may change throughout assembly. */ + mips_opts = file_mips_opts; + + mips_check_isa_supports_ases (); + mips_check_options (&file_mips_opts, TRUE); + file_mips_opts_checked = TRUE; + + if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) + as_warn (_("could not set architecture and machine")); } void @@ -3582,6 +3993,8 @@ md_assemble (char *str) bfd_reloc_code_real_type unused_reloc[3] = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; + file_mips_check_options (); + imm_expr.X_op = O_absent; offset_expr.X_op = O_absent; offset_reloc[0] = BFD_RELOC_UNUSED; @@ -3732,9 +4145,15 @@ limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) case BFD_RELOC_MICROMIPS_7_PCREL_S1: case BFD_RELOC_MICROMIPS_10_PCREL_S1: case BFD_RELOC_MICROMIPS_16_PCREL_S1: + case BFD_RELOC_MIPS_21_PCREL_S2: + case BFD_RELOC_MIPS_26_PCREL_S2: + case BFD_RELOC_MIPS_18_PCREL_S3: + case BFD_RELOC_MIPS_19_PCREL_S2: return TRUE; case BFD_RELOC_32_PCREL: + case BFD_RELOC_HI16_S_PCREL: + case BFD_RELOC_LO16_PCREL: return HAVE_64BIT_ADDRESSES; default: @@ -4005,6 +4424,7 @@ operand_reg_mask (const struct mips_cl_insn *insn, case OP_PC: case OP_VU0_SUFFIX: case OP_VU0_MATCH_SUFFIX: + case OP_IMM_INDEX: abort (); case OP_REG: @@ -4036,6 +4456,19 @@ operand_reg_mask (const struct mips_cl_insn *insn, uval = insn_extract_operand (insn, operand); return (1 << (uval & 31)) | (1 << (uval >> 5)); + case OP_SAME_RS_RT: + if (!(type_mask & (1 << OP_REG_GP))) + return 0; + uval = insn_extract_operand (insn, operand); + gas_assert ((uval & 31) == (uval >> 5)); + return 1 << (uval & 31); + + case OP_CHECK_PREV: + if (!(type_mask & (1 << OP_REG_GP))) + return 0; + uval = insn_extract_operand (insn, operand); + return 1 << (uval & 31); + case OP_LWM_SWM_LIST: abort (); @@ -4050,6 +4483,11 @@ operand_reg_mask (const struct mips_cl_insn *insn, if ((vsel & 0x18) == 0x18) return 0; return 1 << (uval & 31); + + case OP_REG_INDEX: + if (!(type_mask & (1 << OP_REG_GP))) + return 0; + return 1 << insn_extract_operand (insn, operand); } abort (); } @@ -4139,12 +4577,13 @@ fpr_read_mask (const struct mips_cl_insn *ip) unsigned long pinfo; unsigned int mask; - mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC), + mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) + | (1 << OP_REG_MSA)), insn_read_mask (ip->insn_mo)); pinfo = ip->insn_mo->pinfo; /* Conservatively treat all operands to an FP_D instruction are doubles. (This is overly pessimistic for things like cvt.d.s.) */ - if (HAVE_32BIT_FPRS && (pinfo & FP_D)) + if (FPR_SIZE != 64 && (pinfo & FP_D)) mask |= mask << 1; return mask; } @@ -4157,12 +4596,13 @@ fpr_write_mask (const struct mips_cl_insn *ip) unsigned long pinfo; unsigned int mask; - mask = insn_reg_mask (ip, (1 << OP_REG_FP) | (1 << OP_REG_VEC), + mask = insn_reg_mask (ip, ((1 << OP_REG_FP) | (1 << OP_REG_VEC) + | (1 << OP_REG_MSA)), insn_write_mask (ip->insn_mo)); pinfo = ip->insn_mo->pinfo; /* Conservatively treat all operands to an FP_D instruction are doubles. (This is overly pessimistic for things like cvt.s.d.) */ - if (HAVE_32BIT_FPRS && (pinfo & FP_D)) + if (FPR_SIZE != 64 && (pinfo & FP_D)) mask |= mask << 1; return mask; } @@ -4174,39 +4614,41 @@ static bfd_boolean mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) { const char *s = insn->name; + bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) + || FPR_SIZE == 64) + && !mips_opts.nooddspreg; if (insn->pinfo == INSN_MACRO) /* Let a macro pass, we'll catch it later when it is expanded. */ return TRUE; - if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || mips_opts.arch == CPU_R5900) - { - /* Allow odd registers for single-precision ops. */ - switch (insn->pinfo & (FP_S | FP_D)) - { - case FP_S: - case 0: - return TRUE; - case FP_D: - return FALSE; - default: - break; - } + /* Single-precision coprocessor loads and moves are OK for 32-bit registers, + otherwise it depends on oddspreg. */ + if ((insn->pinfo & FP_S) + && (insn->pinfo & INSN_FP_32_MOVE)) + return FPR_SIZE == 32 || oddspreg; - /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ - s = strchr (insn->name, '.'); - if (s != NULL && opnum == 2) - s = strchr (s + 1, '.'); - return (s != NULL && (s[1] == 'w' || s[1] == 's')); + /* Allow odd registers for single-precision ops and double-precision if the + floating-point registers are 64-bit wide. */ + switch (insn->pinfo & (FP_S | FP_D)) + { + case FP_S: + case 0: + return oddspreg; + case FP_D: + return FPR_SIZE == 64; + default: + break; } - /* Single-precision coprocessor loads and moves are OK too. */ - if ((insn->pinfo & FP_S) - && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY - | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) - return TRUE; + /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ + s = strchr (insn->name, '.'); + if (s != NULL && opnum == 2) + s = strchr (s + 1, '.'); + if (s != NULL && (s[1] == 'w' || s[1] == 's')) + return oddspreg; - return FALSE; + return FPR_SIZE == 64; } /* Information about an instruction argument that we're trying to match. */ @@ -4365,7 +4807,7 @@ convert_reg_type (const struct mips_opcode *opcode, && (opcode->pinfo & (INSN_COPROC_MOVE_DELAY | INSN_COPROC_MEMORY_DELAY | INSN_LOAD_COPROC_DELAY - | INSN_LOAD_MEMORY_DELAY + | INSN_LOAD_MEMORY | INSN_STORE_MEMORY))) return RTYPE_FPU | RTYPE_VEC; return RTYPE_FPU; @@ -4408,6 +4850,12 @@ convert_reg_type (const struct mips_opcode *opcode, case OP_REG_R5900_ACC: return RTYPE_R5900_ACC; + + case OP_REG_MSA: + return RTYPE_MSA; + + case OP_REG_MSA_CTRL: + return RTYPE_NUM; } abort (); } @@ -4423,9 +4871,14 @@ check_regno (struct mips_arg_info *arg, if (type == OP_REG_FP && (regno & 1) != 0 - && HAVE_32BIT_FPRS + && (FPR_SIZE == 32 || mips_abi == O32_ABI) && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) - as_warn (_("float register should be even, was %d"), regno); + { + if (FPR_SIZE == 32) + as_warn (_("float register should be even, was %d"), regno); + else + as_bad (_("float register should be even, was %d"), regno); + } if (type == OP_REG_CCC) { @@ -4805,6 +5258,72 @@ match_clo_clz_dest_operand (struct mips_arg_info *arg, return TRUE; } +/* OP_CHECK_PREV matcher. */ + +static bfd_boolean +match_check_prev_operand (struct mips_arg_info *arg, + const struct mips_operand *operand_base) +{ + const struct mips_check_prev_operand *operand; + unsigned int regno; + + operand = (const struct mips_check_prev_operand *) operand_base; + + if (!match_reg (arg, OP_REG_GP, ®no)) + return FALSE; + + if (operand->check_not_zero && regno == 0) + { + set_insn_error (arg->argnum, _("the source register must not be $0")); + return FALSE; + } + + if (operand->check_not_zero && operand->check_not_equal + && regno == 0 && regno == arg->last_regno) + { + set_insn_error (arg->argnum, + _("the source registers must not be $0 and different")); + return FALSE; + } + + if (operand->check_greater_than && regno <= arg->last_regno) + return FALSE; + else if (operand->check_less_than && regno >= arg->last_regno) + return FALSE; + else if (operand->check_greater_than_or_equal && regno < arg->last_regno) + return FALSE; + else if (operand->check_less_than_or_equal && regno > arg->last_regno) + return FALSE; + + arg->last_regno = regno; + + insn_insert_operand (arg->insn, operand_base, regno); + return TRUE; +} + +/* OP_SAME_RS_RT matcher. */ + +static bfd_boolean +match_same_rs_rt_operand (struct mips_arg_info *arg, + const struct mips_operand *operand) +{ + unsigned int regno; + + if (!match_reg (arg, OP_REG_GP, ®no)) + return FALSE; + + if (regno == 0) + { + set_insn_error (arg->argnum, _("the source register must not be $0")); + return FALSE; + } + + arg->last_regno = regno; + + insn_insert_operand (arg->insn, operand, regno | (regno << 5)); + return TRUE; +} + /* OP_LWM_SWM_LIST matcher. */ static bfd_boolean @@ -5078,7 +5597,7 @@ match_mdmx_imm_reg_operand (struct mips_arg_info *arg, uval = mips_extract_operand (operand, opcode->match); is_qh = (uval != 0); - if (arg->token->type == OT_REG || arg->token->type == OT_REG_ELEMENT) + if (arg->token->type == OT_REG) { if ((opcode->membership & INSN_5400) && strcmp (opcode->name, "rzu.ob") == 0) @@ -5088,20 +5607,21 @@ match_mdmx_imm_reg_operand (struct mips_arg_info *arg, return FALSE; } + if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) + return FALSE; + ++arg->token; + /* Check whether this is a vector register or a broadcast of a single element. */ - if (arg->token->type == OT_REG_ELEMENT) + if (arg->token->type == OT_INTEGER_INDEX) { - if (!match_regno (arg, OP_REG_VEC, arg->token->u.reg_element.regno, - ®no)) - return FALSE; - if (arg->token->u.reg_element.index > (is_qh ? 3 : 7)) + if (arg->token->u.index > (is_qh ? 3 : 7)) { set_insn_error (arg->argnum, _("invalid element selector")); return FALSE; } - else - uval |= arg->token->u.reg_element.index << (is_qh ? 2 : 1) << 5; + uval |= arg->token->u.index << (is_qh ? 2 : 1) << 5; + ++arg->token; } else { @@ -5115,15 +5635,12 @@ match_mdmx_imm_reg_operand (struct mips_arg_info *arg, return FALSE; } - if (!match_regno (arg, OP_REG_VEC, arg->token->u.regno, ®no)) - return FALSE; if (is_qh) uval |= MDMX_FMTSEL_VEC_QH << 5; else uval |= MDMX_FMTSEL_VEC_OB << 5; } uval |= regno; - ++arg->token; } else { @@ -5146,6 +5663,47 @@ match_mdmx_imm_reg_operand (struct mips_arg_info *arg, return TRUE; } +/* OP_IMM_INDEX matcher. */ + +static bfd_boolean +match_imm_index_operand (struct mips_arg_info *arg, + const struct mips_operand *operand) +{ + unsigned int max_val; + + if (arg->token->type != OT_INTEGER_INDEX) + return FALSE; + + max_val = (1 << operand->size) - 1; + if (arg->token->u.index > max_val) + { + match_out_of_range (arg); + return FALSE; + } + insn_insert_operand (arg->insn, operand, arg->token->u.index); + ++arg->token; + return TRUE; +} + +/* OP_REG_INDEX matcher. */ + +static bfd_boolean +match_reg_index_operand (struct mips_arg_info *arg, + const struct mips_operand *operand) +{ + unsigned int regno; + + if (arg->token->type != OT_REG_INDEX) + return FALSE; + + if (!match_regno (arg, OP_REG_GP, arg->token->u.regno, ®no)) + return FALSE; + + insn_insert_operand (arg->insn, operand, regno); + ++arg->token; + return TRUE; +} + /* OP_PC matcher. */ static bfd_boolean @@ -5240,13 +5798,16 @@ match_float_constant (struct mips_arg_info *arg, expressionS *imm, /* Handle 64-bit constants for which an immediate value is best. */ if (length == 8 && !mips_disable_float_construction - /* Constants can only be constructed in GPRs and copied - to FPRs if the GPRs are at least as wide as the FPRs. - Force the constant into memory if we are using 64-bit FPRs - but the GPRs are only 32 bits wide. */ - /* ??? No longer true with the addition of MTHC1, but this - is legacy code... */ - && (using_gprs || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) + /* Constants can only be constructed in GPRs and copied to FPRs if the + GPRs are at least as wide as the FPRs or MTHC1 is available. + Unlike most tests for 32-bit floating-point registers this check + specifically looks for GPR_SIZE == 32 as the FPXX ABI does not + permit 64-bit moves without MXHC1. + Force the constant into memory otherwise. */ + && (using_gprs + || GPR_SIZE == 64 + || ISA_HAS_MXHC1 (mips_opts.isa) + || FPR_SIZE == 32) && ((data[0] == 0 && data[1] == 0) || (data[2] == 0 && data[3] == 0)) && ((data[4] == 0 && data[5] == 0) @@ -5256,7 +5817,7 @@ match_float_constant (struct mips_arg_info *arg, expressionS *imm, If using 32-bit registers, set IMM to the high order 32 bits and OFFSET to the low order 32 bits. Otherwise, set IMM to the entire 64 bit constant. */ - if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) + if (GPR_SIZE == 32 || FPR_SIZE != 64) { imm->X_op = O_constant; offset->X_op = O_constant; @@ -5426,6 +5987,19 @@ match_operand (struct mips_arg_info *arg, case OP_VU0_MATCH_SUFFIX: return match_vu0_suffix_operand (arg, operand, TRUE); + + case OP_IMM_INDEX: + return match_imm_index_operand (arg, operand); + + case OP_REG_INDEX: + return match_reg_index_operand (arg, operand); + + case OP_SAME_RS_RT: + return match_same_rs_rt_operand (arg, operand); + + case OP_CHECK_PREV: + return match_check_prev_operand (arg, operand); + } abort (); } @@ -5454,7 +6028,7 @@ reg_needs_delay (unsigned int reg) prev_pinfo = history[0].insn_mo->pinfo; if (!mips_opts.noreorder - && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) && !gpr_interlocks) + && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks) || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) && !cop_interlocks)) && (gpr_write_mask (&history[0]) & (1 << reg))) return TRUE; @@ -5484,8 +6058,10 @@ classify_vr4120_insn (const char *name) return NUM_FIX_VR4120_CLASSES; } -#define INSN_ERET 0x42000018 -#define INSN_DERET 0x4200001f +#define INSN_ERET 0x42000018 +#define INSN_DERET 0x4200001f +#define INSN_DMULT 0x1c +#define INSN_DMULTU 0x1d /* Return the number of instructions that must separate INSN1 and INSN2, where INSN1 is the earlier instruction. Return the worst-case value @@ -5536,6 +6112,18 @@ insns_between (const struct mips_cl_insn *insn1, } } + /* If we're working around PMC RM7000 errata, there must be three + nops between a dmult and a load instruction. */ + if (mips_fix_rm7000 && !mips_opts.micromips) + { + if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT + || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU) + { + if (pinfo2 & INSN_LOAD_MEMORY) + return 3; + } + } + /* If working around VR4120 errata, check for combinations that need a single intervening instruction. */ if (mips_fix_vr4120 && !mips_opts.micromips) @@ -5558,7 +6146,7 @@ insns_between (const struct mips_cl_insn *insn1, /* Check for GPR or coprocessor load delays. All such delays are on the RT register. */ /* Itbl support may require additional care here. */ - if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY)) + if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY)) || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY))) { if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))) @@ -5612,6 +6200,14 @@ insns_between (const struct mips_cl_insn *insn1, return 1; } + /* Forbidden slots can not contain Control Transfer Instructions (CTIs) + CTIs include all branches and jumps, nal, eret, eretnc, deret, wait, + and pause. */ + if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT) + && ((pinfo2 & INSN_NO_DELAY_SLOT) + || (insn2 && delayed_branch_p (insn2)))) + return 1; + return 0; } @@ -5997,6 +6593,7 @@ can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, { unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2; unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write; + unsigned int fpr_read, prev_fpr_write; /* -O2 and above is required for this optimization. */ if (mips_optimize < 2) @@ -6071,6 +6668,11 @@ can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr, if (gpr_read & prev_gpr_write) return FALSE; + fpr_read = fpr_read_mask (ip); + prev_fpr_write = fpr_write_mask (&history[0]); + if (fpr_read & prev_fpr_write) + return FALSE; + /* If the branch writes a register that the previous instruction sets, we can not swap. */ gpr_write = gpr_write_mask (ip); @@ -6463,6 +7065,40 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr, } break; + case BFD_RELOC_MIPS_21_PCREL_S2: + { + int shift; + + shift = 2; + if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) + as_bad (_("branch to misaligned address (0x%lx)"), + (unsigned long) address_expr->X_add_number); + if ((address_expr->X_add_number + (1 << (shift + 20))) + & ~((1 << (shift + 21)) - 1)) + as_bad (_("branch address range overflow (0x%lx)"), + (unsigned long) address_expr->X_add_number); + ip->insn_opcode |= ((address_expr->X_add_number >> shift) + & 0x1fffff); + } + break; + + case BFD_RELOC_MIPS_26_PCREL_S2: + { + int shift; + + shift = 2; + if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0) + as_bad (_("branch to misaligned address (0x%lx)"), + (unsigned long) address_expr->X_add_number); + if ((address_expr->X_add_number + (1 << (shift + 25))) + & ~((1 << (shift + 26)) - 1)) + as_bad (_("branch address range overflow (0x%lx)"), + (unsigned long) address_expr->X_add_number); + ip->insn_opcode |= ((address_expr->X_add_number >> shift) + & 0x3ffffff); + } + break; + default: { offsetT value; @@ -6726,7 +7362,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr, /* These relocations can have an addend that won't fit in 4 octets for 64bit assembly. */ - if (HAVE_64BIT_GPRS + if (GPR_SIZE == 64 && ! howto->partial_inplace && (reloc_type[0] == BFD_RELOC_16 || reloc_type[0] == BFD_RELOC_32 @@ -7127,12 +7763,33 @@ match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, arg.opnum += 1; switch (*args) { + case '-': + switch (args[1]) + { + case 'A': + *offset_reloc = BFD_RELOC_MIPS_19_PCREL_S2; + break; + + case 'B': + *offset_reloc = BFD_RELOC_MIPS_18_PCREL_S3; + break; + } + break; + case '+': switch (args[1]) { case 'i': *offset_reloc = BFD_RELOC_MIPS_JMP; break; + + case '\'': + *offset_reloc = BFD_RELOC_MIPS_26_PCREL_S2; + break; + + case '\"': + *offset_reloc = BFD_RELOC_MIPS_21_PCREL_S2; + break; } break; @@ -7140,7 +7797,7 @@ match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, if (!match_const_int (&arg, &imm_expr.X_add_number)) return FALSE; imm_expr.X_op = O_constant; - if (HAVE_32BIT_GPRS) + if (GPR_SIZE == 32) normalize_constant_expr (&imm_expr); continue; @@ -7218,7 +7875,7 @@ match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, abort (); /* Skip prefixes. */ - if (*args == '+' || *args == 'm') + if (*args == '+' || *args == 'm' || *args == '-') args++; if (mips_optional_operand_p (operand) @@ -7350,7 +8007,7 @@ match_mips16_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode, if (!match_const_int (&arg, &imm_expr.X_add_number)) return FALSE; imm_expr.X_op = O_constant; - if (HAVE_32BIT_GPRS) + if (GPR_SIZE == 32) normalize_constant_expr (&imm_expr); continue; @@ -7869,7 +8526,7 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...) uval |= (uval << 5); insn_insert_operand (&insn, operand, uval); - if (*fmt == '+' || *fmt == 'm') + if (*fmt == '+' || *fmt == 'm' || *fmt == '-') ++fmt; break; } @@ -8077,7 +8734,7 @@ set_at (int reg, int unsignedp) AT, reg, BFD_RELOC_LO16); else { - load_register (AT, &imm_expr, HAVE_64BIT_GPRS); + load_register (AT, &imm_expr, GPR_SIZE == 64); macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); } } @@ -8203,7 +8860,7 @@ load_register (int reg, expressionS *ep, int dbl) /* The value is larger than 32 bits. */ - if (!dbl || HAVE_32BIT_GPRS) + if (!dbl || GPR_SIZE == 32) { char value[32]; @@ -8659,7 +9316,7 @@ move_register (int dest, int source) && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) macro_build (NULL, "move", "mp,mj", dest, source); else - macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", + macro_build (NULL, GPR_SIZE == 32 ? "addu" : "daddu", "d,v,t", dest, source, 0); } @@ -9142,7 +9799,7 @@ macro (struct mips_cl_insn *ip, char *str) } used_at = 1; - load_register (AT, &imm_expr, HAVE_64BIT_GPRS); + load_register (AT, &imm_expr, GPR_SIZE == 64); macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); break; @@ -9186,7 +9843,7 @@ macro (struct mips_cl_insn *ip, char *str) { op[1] = AT; used_at = 1; - load_register (op[1], &imm_expr, HAVE_64BIT_GPRS); + load_register (op[1], &imm_expr, GPR_SIZE == 64); } /* Fall through. */ case M_BEQL: @@ -9286,7 +9943,7 @@ macro (struct mips_cl_insn *ip, char *str) likely = 1; case M_BGTU_I: if (op[0] == 0 - || (HAVE_32BIT_GPRS + || (GPR_SIZE == 32 && imm_expr.X_add_number == -1)) goto do_false; ++imm_expr.X_add_number; @@ -9403,7 +10060,7 @@ macro (struct mips_cl_insn *ip, char *str) likely = 1; case M_BLEU_I: if (op[0] == 0 - || (HAVE_32BIT_GPRS + || (GPR_SIZE == 32 && imm_expr.X_add_number == -1)) goto do_true; ++imm_expr.X_add_number; @@ -9668,7 +10325,7 @@ macro (struct mips_cl_insn *ip, char *str) zero, we then add a base register to it. */ breg = op[2]; - if (dbl && HAVE_32BIT_GPRS) + if (dbl && GPR_SIZE == 32) as_warn (_("dla used to load 32-bit register")); if (!dbl && HAVE_64BIT_OBJECTS) @@ -11331,7 +11988,7 @@ macro (struct mips_cl_insn *ip, char *str) zero or in OFFSET_EXPR. */ if (imm_expr.X_op == O_constant) { - if (HAVE_64BIT_GPRS) + if (GPR_SIZE == 64) load_register (op[0], &imm_expr, 1); else { @@ -11380,7 +12037,7 @@ macro (struct mips_cl_insn *ip, char *str) } /* Now we load the register(s). */ - if (HAVE_64BIT_GPRS) + if (GPR_SIZE == 64) { used_at = 1; macro_build (&offset_expr, "ld", "t,o(b)", op[0], @@ -11411,15 +12068,19 @@ macro (struct mips_cl_insn *ip, char *str) if (imm_expr.X_op == O_constant) { used_at = 1; - load_register (AT, &imm_expr, HAVE_64BIT_FPRS); - if (HAVE_64BIT_FPRS) - { - gas_assert (HAVE_64BIT_GPRS); - macro_build (NULL, "dmtc1", "t,S", AT, op[0]); - } + load_register (AT, &imm_expr, FPR_SIZE == 64); + if (FPR_SIZE == 64 && GPR_SIZE == 64) + macro_build (NULL, "dmtc1", "t,S", AT, op[0]); else { - macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1); + if (ISA_HAS_MXHC1 (mips_opts.isa)) + macro_build (NULL, "mthc1", "t,G", AT, op[0]); + else if (FPR_SIZE != 32) + as_bad (_("Unable to generate `%s' compliant code " + "without mthc1"), + (FPR_SIZE == 64) ? "fp64" : "fpxx"); + else + macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1); if (offset_expr.X_op == O_absent) macro_build (NULL, "mtc1", "t,G", 0, op[0]); else @@ -11512,7 +12173,7 @@ macro (struct mips_cl_insn *ip, char *str) case M_LD_AB: fmt = "t,o(b)"; - if (HAVE_64BIT_GPRS) + if (GPR_SIZE == 64) { s = "ld"; goto ld; @@ -11522,7 +12183,7 @@ macro (struct mips_cl_insn *ip, char *str) case M_SD_AB: fmt = "t,o(b)"; - if (HAVE_64BIT_GPRS) + if (GPR_SIZE == 64) { s = "sd"; goto ld_st; @@ -12163,19 +12824,19 @@ macro (struct mips_cl_insn *ip, char *str) && imm_expr.X_add_number < 0) { imm_expr.X_add_number = -imm_expr.X_add_number; - macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", + macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); } else if (CPU_HAS_SEQ (mips_opts.arch)) { used_at = 1; - load_register (AT, &imm_expr, HAVE_64BIT_GPRS); + load_register (AT, &imm_expr, GPR_SIZE == 64); macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); break; } else { - load_register (AT, &imm_expr, HAVE_64BIT_GPRS); + load_register (AT, &imm_expr, GPR_SIZE == 64); macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); used_at = 1; } @@ -12200,7 +12861,7 @@ macro (struct mips_cl_insn *ip, char *str) op[0], op[1], BFD_RELOC_LO16); else { - load_register (AT, &imm_expr, HAVE_64BIT_GPRS); + load_register (AT, &imm_expr, GPR_SIZE == 64); macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", op[0], op[1], AT); used_at = 1; @@ -12224,7 +12885,7 @@ macro (struct mips_cl_insn *ip, char *str) s = "sltu"; sgti: used_at = 1; - load_register (AT, &imm_expr, HAVE_64BIT_GPRS); + load_register (AT, &imm_expr, GPR_SIZE == 64); macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); break; @@ -12245,7 +12906,7 @@ macro (struct mips_cl_insn *ip, char *str) s = "sltu"; slei: used_at = 1; - load_register (AT, &imm_expr, HAVE_64BIT_GPRS); + load_register (AT, &imm_expr, GPR_SIZE == 64); macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); break; @@ -12259,7 +12920,7 @@ macro (struct mips_cl_insn *ip, char *str) break; } used_at = 1; - load_register (AT, &imm_expr, HAVE_64BIT_GPRS); + load_register (AT, &imm_expr, GPR_SIZE == 64); macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); break; @@ -12272,7 +12933,7 @@ macro (struct mips_cl_insn *ip, char *str) break; } used_at = 1; - load_register (AT, &imm_expr, HAVE_64BIT_GPRS); + load_register (AT, &imm_expr, GPR_SIZE == 64); macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); break; @@ -12298,7 +12959,7 @@ macro (struct mips_cl_insn *ip, char *str) { as_warn (_("instruction %s: result is always true"), ip->insn_mo->name); - macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", + macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", op[0], 0, BFD_RELOC_LO16); break; } @@ -12320,19 +12981,19 @@ macro (struct mips_cl_insn *ip, char *str) && imm_expr.X_add_number < 0) { imm_expr.X_add_number = -imm_expr.X_add_number; - macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", + macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", op[0], op[1], BFD_RELOC_LO16); } else if (CPU_HAS_SEQ (mips_opts.arch)) { used_at = 1; - load_register (AT, &imm_expr, HAVE_64BIT_GPRS); + load_register (AT, &imm_expr, GPR_SIZE == 64); macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); break; } else { - load_register (AT, &imm_expr, HAVE_64BIT_GPRS); + load_register (AT, &imm_expr, GPR_SIZE == 64); macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); used_at = 1; } @@ -12398,7 +13059,7 @@ macro (struct mips_cl_insn *ip, char *str) s = "tne"; trap: used_at = 1; - load_register (AT, &imm_expr, HAVE_64BIT_GPRS); + load_register (AT, &imm_expr, GPR_SIZE == 64); macro_build (NULL, s, "s,t", op[0], AT); break; @@ -13155,7 +13816,9 @@ static const struct percent_op_match mips_percent_op[] = {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16}, {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16}, {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL}, - {"%hi", BFD_RELOC_HI16_S} + {"%hi", BFD_RELOC_HI16_S}, + {"%pcrel_hi", BFD_RELOC_HI16_S_PCREL}, + {"%pcrel_lo", BFD_RELOC_LO16_PCREL} }; static const struct percent_op_match mips16_percent_op[] = @@ -13348,7 +14011,7 @@ md_parse_option (int c, char *arg) for (i = 0; i < ARRAY_SIZE (mips_ases); i++) if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) { - file_ase_explicit |= mips_set_ase (&mips_ases[i], + file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, c == mips_ases[i].option_on); return 1; } @@ -13398,39 +14061,63 @@ md_parse_option (int c, char *arg) break; case OPTION_MIPS1: - file_mips_isa = ISA_MIPS1; + file_mips_opts.isa = ISA_MIPS1; break; case OPTION_MIPS2: - file_mips_isa = ISA_MIPS2; + file_mips_opts.isa = ISA_MIPS2; break; case OPTION_MIPS3: - file_mips_isa = ISA_MIPS3; + file_mips_opts.isa = ISA_MIPS3; break; case OPTION_MIPS4: - file_mips_isa = ISA_MIPS4; + file_mips_opts.isa = ISA_MIPS4; break; case OPTION_MIPS5: - file_mips_isa = ISA_MIPS5; + file_mips_opts.isa = ISA_MIPS5; break; case OPTION_MIPS32: - file_mips_isa = ISA_MIPS32; + file_mips_opts.isa = ISA_MIPS32; break; case OPTION_MIPS32R2: - file_mips_isa = ISA_MIPS32R2; + file_mips_opts.isa = ISA_MIPS32R2; + break; + + case OPTION_MIPS32R3: + file_mips_opts.isa = ISA_MIPS32R3; + break; + + case OPTION_MIPS32R5: + file_mips_opts.isa = ISA_MIPS32R5; + break; + + case OPTION_MIPS32R6: + file_mips_opts.isa = ISA_MIPS32R6; break; case OPTION_MIPS64R2: - file_mips_isa = ISA_MIPS64R2; + file_mips_opts.isa = ISA_MIPS64R2; + break; + + case OPTION_MIPS64R3: + file_mips_opts.isa = ISA_MIPS64R3; + break; + + case OPTION_MIPS64R5: + file_mips_opts.isa = ISA_MIPS64R5; + break; + + case OPTION_MIPS64R6: + file_mips_opts.isa = ISA_MIPS64R6; break; case OPTION_MIPS64: - file_mips_isa = ISA_MIPS64; + file_mips_opts.isa = ISA_MIPS64; break; case OPTION_MTUNE: @@ -13474,32 +14161,32 @@ md_parse_option (int c, char *arg) break; case OPTION_MICROMIPS: - if (mips_opts.mips16 == 1) + if (file_mips_opts.mips16 == 1) { as_bad (_("-mmicromips cannot be used with -mips16")); return 0; } - mips_opts.micromips = 1; + file_mips_opts.micromips = 1; mips_no_prev_insn (); break; case OPTION_NO_MICROMIPS: - mips_opts.micromips = 0; + file_mips_opts.micromips = 0; mips_no_prev_insn (); break; case OPTION_MIPS16: - if (mips_opts.micromips == 1) + if (file_mips_opts.micromips == 1) { as_bad (_("-mips16 cannot be used with -micromips")); return 0; } - mips_opts.mips16 = 1; + file_mips_opts.mips16 = 1; mips_no_prev_insn (); break; case OPTION_NO_MIPS16: - mips_opts.mips16 = 0; + file_mips_opts.mips16 = 0; mips_no_prev_insn (); break; @@ -13511,6 +14198,14 @@ md_parse_option (int c, char *arg) mips_fix_24k = 0; break; + case OPTION_FIX_RM7000: + mips_fix_rm7000 = 1; + break; + + case OPTION_NO_FIX_RM7000: + mips_fix_rm7000 = 0; + break; + case OPTION_FIX_LOONGSON2F_JUMP: mips_fix_loongson2f_jump = TRUE; break; @@ -13560,11 +14255,11 @@ md_parse_option (int c, char *arg) break; case OPTION_INSN32: - mips_opts.insn32 = TRUE; + file_mips_opts.insn32 = TRUE; break; case OPTION_NO_INSN32: - mips_opts.insn32 = FALSE; + file_mips_opts.insn32 = FALSE; break; case OPTION_MSHARED: @@ -13576,11 +14271,11 @@ md_parse_option (int c, char *arg) break; case OPTION_MSYM32: - mips_opts.sym32 = TRUE; + file_mips_opts.sym32 = TRUE; break; case OPTION_MNO_SYM32: - mips_opts.sym32 = FALSE; + file_mips_opts.sym32 = FALSE; break; /* When generating ELF code, we permit -KPIC and -call_shared to @@ -13630,35 +14325,47 @@ md_parse_option (int c, char *arg) break; case OPTION_GP32: - file_mips_gp32 = 1; + file_mips_opts.gp = 32; break; case OPTION_GP64: - file_mips_gp32 = 0; + file_mips_opts.gp = 64; break; case OPTION_FP32: - file_mips_fp32 = 1; + file_mips_opts.fp = 32; + break; + + case OPTION_FPXX: + file_mips_opts.fp = 0; break; case OPTION_FP64: - file_mips_fp32 = 0; + file_mips_opts.fp = 64; + break; + + case OPTION_ODD_SPREG: + file_mips_opts.nooddspreg = 0; + break; + + case OPTION_NO_ODD_SPREG: + file_mips_opts.nooddspreg = 1; break; case OPTION_SINGLE_FLOAT: - file_mips_single_float = 1; + file_mips_opts.single_float = 1; break; case OPTION_DOUBLE_FLOAT: - file_mips_single_float = 0; + file_mips_opts.single_float = 0; break; case OPTION_SOFT_FLOAT: - file_mips_soft_float = 1; + file_mips_opts.soft_float = 1; break; case OPTION_HARD_FLOAT: - file_mips_soft_float = 0; + file_mips_opts.soft_float = 0; break; case OPTION_MABI: @@ -13714,9 +14421,9 @@ md_parse_option (int c, char *arg) case OPTION_NAN: if (strcmp (arg, "2008") == 0) - mips_flag_nan2008 = TRUE; + mips_nan2008 = 1; else if (strcmp (arg, "legacy") == 0) - mips_flag_nan2008 = FALSE; + mips_nan2008 = 0; else { as_fatal (_("invalid NaN setting -mnan=%s"), arg); @@ -13733,22 +14440,7 @@ md_parse_option (int c, char *arg) return 1; } -/* Set up globals to generate code for the ISA or processor - described by INFO. */ - -static void -mips_set_architecture (const struct mips_cpu_info *info) -{ - if (info != 0) - { - file_mips_arch = info->cpu; - mips_opts.arch = info->cpu; - mips_opts.isa = info->isa; - } -} - - -/* Likewise for tuning. */ +/* Set up globals to tune for the ISA or processor described by INFO. */ static void mips_set_tune (const struct mips_cpu_info *info) @@ -13775,7 +14467,7 @@ mips_after_parse_args (void) if (mips_abi == NO_ABI) mips_abi = MIPS_DEFAULT_ABI; - /* The following code determines the architecture and register size. + /* The following code determines the architecture. Similar code was added to GCC 3.3 (see override_options() in config/mips/mips.c). The GAS and GCC code should be kept in sync as much as possible. */ @@ -13783,9 +14475,9 @@ mips_after_parse_args (void) if (mips_arch_string != 0) arch_info = mips_parse_cpu ("-march", mips_arch_string); - if (file_mips_isa != ISA_UNKNOWN) + if (file_mips_opts.isa != ISA_UNKNOWN) { - /* Handle -mipsN. At this point, file_mips_isa contains the + /* Handle -mipsN. At this point, file_mips_opts.isa contains the ISA level specified by -mipsN, while arch_info->isa contains the -march selection (if any). */ if (arch_info != 0) @@ -13793,14 +14485,14 @@ mips_after_parse_args (void) /* -march takes precedence over -mipsN, since it is more descriptive. There's no harm in specifying both as long as the ISA levels are the same. */ - if (file_mips_isa != arch_info->isa) + if (file_mips_opts.isa != arch_info->isa) as_bad (_("-%s conflicts with the other architecture options," " which imply -%s"), - mips_cpu_info_from_isa (file_mips_isa)->name, + mips_cpu_info_from_isa (file_mips_opts.isa)->name, mips_cpu_info_from_isa (arch_info->isa)->name); } else - arch_info = mips_cpu_info_from_isa (file_mips_isa); + arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); } if (arch_info == 0) @@ -13813,9 +14505,17 @@ mips_after_parse_args (void) as_bad (_("-march=%s is not compatible with the selected ABI"), arch_info->name); - mips_set_architecture (arch_info); + file_mips_opts.arch = arch_info->cpu; + file_mips_opts.isa = arch_info->isa; - /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ + /* Set up initial mips_opts state. */ + mips_opts = file_mips_opts; + + /* The register size inference code is now placed in + file_mips_check_options. */ + + /* Optimize for file_mips_opts.arch, unless -mtune selects a different + processor. */ if (mips_tune_string != 0) tune_info = mips_parse_cpu ("-mtune", mips_tune_string); @@ -13824,101 +14524,6 @@ mips_after_parse_args (void) else mips_set_tune (tune_info); - if (file_mips_gp32 >= 0) - { - /* The user specified the size of the integer registers. Make sure - it agrees with the ABI and ISA. */ - if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) - as_bad (_("-mgp64 used with a 32-bit processor")); - else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) - as_bad (_("-mgp32 used with a 64-bit ABI")); - else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) - as_bad (_("-mgp64 used with a 32-bit ABI")); - } - else - { - /* Infer the integer register size from the ABI and processor. - Restrict ourselves to 32-bit registers if that's all the - processor has, or if the ABI cannot handle 64-bit registers. */ - file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) - || !ISA_HAS_64BIT_REGS (mips_opts.isa)); - } - - switch (file_mips_fp32) - { - default: - case -1: - /* No user specified float register size. - ??? GAS treats single-float processors as though they had 64-bit - float registers (although it complains when double-precision - instructions are used). As things stand, saying they have 32-bit - registers would lead to spurious "register must be even" messages. - So here we assume float registers are never smaller than the - integer ones. */ - if (file_mips_gp32 == 0) - /* 64-bit integer registers implies 64-bit float registers. */ - file_mips_fp32 = 0; - else if ((mips_opts.ase & FP64_ASES) - && ISA_HAS_64BIT_FPRS (mips_opts.isa)) - /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ - file_mips_fp32 = 0; - else - /* 32-bit float registers. */ - file_mips_fp32 = 1; - break; - - /* The user specified the size of the float registers. Check if it - agrees with the ABI and ISA. */ - case 0: - if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) - as_bad (_("-mfp64 used with a 32-bit fpu")); - else if (ABI_NEEDS_32BIT_REGS (mips_abi) - && !ISA_HAS_MXHC1 (mips_opts.isa)) - as_warn (_("-mfp64 used with a 32-bit ABI")); - break; - case 1: - if (ABI_NEEDS_64BIT_REGS (mips_abi)) - as_warn (_("-mfp32 used with a 64-bit ABI")); - break; - } - - /* End of GCC-shared inference code. */ - - /* This flag is set when we have a 64-bit capable CPU but use only - 32-bit wide registers. Note that EABI does not use it. */ - if (ISA_HAS_64BIT_REGS (mips_opts.isa) - && ((mips_abi == NO_ABI && file_mips_gp32 == 1) - || mips_abi == O32_ABI)) - mips_32bitmode = 1; - - if (mips_opts.isa == ISA_MIPS1 && mips_trap) - as_bad (_("trap exception not supported at ISA 1")); - - /* If the selected architecture includes support for ASEs, enable - generation of code for them. */ - if (mips_opts.mips16 == -1) - mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; - if (mips_opts.micromips == -1) - mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; - - /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those - ASEs from being selected implicitly. */ - if (file_mips_fp32 == 1) - file_ase_explicit |= ASE_MIPS3D | ASE_MDMX; - - /* If the user didn't explicitly select or deselect a particular ASE, - use the default setting for the CPU. */ - mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); - - file_mips_isa = mips_opts.isa; - file_ase = mips_opts.ase; - mips_opts.gp32 = file_mips_gp32; - mips_opts.fp32 = file_mips_fp32; - mips_opts.soft_float = file_mips_soft_float; - mips_opts.single_float = file_mips_single_float; - - mips_check_isa_supports_ases (); - if (mips_flag_mdebug < 0) mips_flag_mdebug = 0; } @@ -13945,19 +14550,13 @@ md_pcrel_from (fixS *fixP) case BFD_RELOC_MICROMIPS_16_PCREL_S1: case BFD_RELOC_MICROMIPS_JMP: case BFD_RELOC_16_PCREL_S2: + case BFD_RELOC_MIPS_21_PCREL_S2: + case BFD_RELOC_MIPS_26_PCREL_S2: case BFD_RELOC_MIPS_JMP: /* Return the address of the delay slot. */ return addr + 4; - case BFD_RELOC_32_PCREL: - return addr; - default: - /* We have no relocation type for PC relative MIPS16 instructions. */ - if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) - as_bad_where (fixP->fx_file, fixP->fx_line, - _("PC relative MIPS16 instruction references" - " a different section")); return addr; } } @@ -14118,6 +14717,17 @@ mips_force_relocation (fixS *fixp) || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1) return 1; + /* We want all PC-relative relocations to be kept for R6 relaxation. */ + if (ISA_IS_R6 (mips_opts.isa) + && (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2 + || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 + || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 + || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 + || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 + || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL + || fixp->fx_r_type == BFD_RELOC_LO16_PCREL)) + return 1; + return 0; } @@ -14154,13 +14764,44 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) unsigned long insn; reloc_howto_type *howto; - /* We ignore generic BFD relocations we don't know about. */ - howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); - if (! howto) - return; + if (fixP->fx_pcrel) + switch (fixP->fx_r_type) + { + case BFD_RELOC_16_PCREL_S2: + case BFD_RELOC_MICROMIPS_7_PCREL_S1: + case BFD_RELOC_MICROMIPS_10_PCREL_S1: + case BFD_RELOC_MICROMIPS_16_PCREL_S1: + case BFD_RELOC_32_PCREL: + case BFD_RELOC_MIPS_21_PCREL_S2: + case BFD_RELOC_MIPS_26_PCREL_S2: + case BFD_RELOC_MIPS_19_PCREL_S2: + case BFD_RELOC_HI16_S_PCREL: + case BFD_RELOC_LO16_PCREL: + case BFD_RELOC_MIPS_18_PCREL_S3: + break; + + case BFD_RELOC_32: + fixP->fx_r_type = BFD_RELOC_32_PCREL; + break; + + default: + as_bad_where (fixP->fx_file, fixP->fx_line, + _("PC-relative reference to a different section")); + break; + } + + /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations + that have no MIPS ELF equivalent. */ + if (fixP->fx_r_type != BFD_RELOC_8) + { + howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); + if (!howto) + return; + } gas_assert (fixP->fx_size == 2 || fixP->fx_size == 4 + || fixP->fx_r_type == BFD_RELOC_8 || fixP->fx_r_type == BFD_RELOC_16 || fixP->fx_r_type == BFD_RELOC_64 || fixP->fx_r_type == BFD_RELOC_CTOR @@ -14172,12 +14813,6 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) buf = fixP->fx_frag->fr_literal + fixP->fx_where; - gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 - || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 - || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 - || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 - || fixP->fx_r_type == BFD_RELOC_32_PCREL); - /* Don't treat parts of a composite relocation as done. There are two reasons for this: @@ -14327,6 +14962,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) case BFD_RELOC_32: case BFD_RELOC_32_PCREL: case BFD_RELOC_16: + case BFD_RELOC_8: /* If we are deleting this reloc entry, we must fill in the value now. This can happen if we have a .word which is not resolved when it appears but is later defined. */ @@ -14334,6 +14970,45 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) md_number_to_chars (buf, *valP, fixP->fx_size); break; + case BFD_RELOC_MIPS_21_PCREL_S2: + if ((*valP & 0x3) != 0) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("branch to misaligned address (%lx)"), (long) *valP); + + gas_assert(!fixP->fx_done); + break; + + case BFD_RELOC_MIPS_26_PCREL_S2: + if ((*valP & 0x3) != 0) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("branch to misaligned address (%lx)"), (long) *valP); + + gas_assert(!fixP->fx_done); + break; + + case BFD_RELOC_MIPS_18_PCREL_S3: + if ((*valP & 0x7) != 0) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("pc rel from misaligned address (%lx)"), + (long) *valP); + + gas_assert(!fixP->fx_done); + break; + + case BFD_RELOC_MIPS_19_PCREL_S2: + if ((*valP & 0x3) != 0) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("pc rel from misaligned address (%lx)"), + (long) *valP); + + gas_assert(!fixP->fx_done); + break; + + case BFD_RELOC_HI16_S_PCREL: + case BFD_RELOC_LO16_PCREL: + gas_assert(!fixP->fx_done); + break; + case BFD_RELOC_16_PCREL_S2: if ((*valP & 0x3) != 0) as_bad_where (fixP->fx_file, fixP->fx_line, @@ -14794,30 +15469,11 @@ struct mips_option_stack static struct mips_option_stack *mips_opts_stack; -/* Handle the .set pseudo-op. */ - -static void -s_mipsset (int x ATTRIBUTE_UNUSED) +static bfd_boolean +parse_code_option (char * name) { - char *name = input_line_pointer, ch; const struct mips_ase *ase; - - while (!is_end_of_line[(unsigned char) *input_line_pointer]) - ++input_line_pointer; - ch = *input_line_pointer; - *input_line_pointer = '\0'; - - if (strcmp (name, "reorder") == 0) - { - if (mips_opts.noreorder) - end_noreorder (); - } - else if (strcmp (name, "noreorder") == 0) - { - if (!mips_opts.noreorder) - start_noreorder (); - } - else if (strncmp (name, "at=", 3) == 0) + if (strncmp (name, "at=", 3) == 0) { char *s = name + 3; @@ -14825,61 +15481,27 @@ s_mipsset (int x ATTRIBUTE_UNUSED) as_bad (_("unrecognized register name `%s'"), s); } else if (strcmp (name, "at") == 0) - { - mips_opts.at = ATREG; - } + mips_opts.at = ATREG; else if (strcmp (name, "noat") == 0) - { - mips_opts.at = ZERO; - } - else if (strcmp (name, "macro") == 0) - { - mips_opts.warn_about_macros = 0; - } - else if (strcmp (name, "nomacro") == 0) - { - if (mips_opts.noreorder == 0) - as_bad (_("`noreorder' must be set before `nomacro'")); - mips_opts.warn_about_macros = 1; - } + mips_opts.at = ZERO; else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) - { - mips_opts.nomove = 0; - } + mips_opts.nomove = 0; else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) - { - mips_opts.nomove = 1; - } + mips_opts.nomove = 1; else if (strcmp (name, "bopt") == 0) - { - mips_opts.nobopt = 0; - } + mips_opts.nobopt = 0; else if (strcmp (name, "nobopt") == 0) - { - mips_opts.nobopt = 1; - } - else if (strcmp (name, "gp=default") == 0) - mips_opts.gp32 = file_mips_gp32; + mips_opts.nobopt = 1; else if (strcmp (name, "gp=32") == 0) - mips_opts.gp32 = 1; + mips_opts.gp = 32; else if (strcmp (name, "gp=64") == 0) - { - if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) - as_warn (_("%s isa does not support 64-bit registers"), - mips_cpu_info_from_isa (mips_opts.isa)->name); - mips_opts.gp32 = 0; - } - else if (strcmp (name, "fp=default") == 0) - mips_opts.fp32 = file_mips_fp32; + mips_opts.gp = 64; else if (strcmp (name, "fp=32") == 0) - mips_opts.fp32 = 1; + mips_opts.fp = 32; + else if (strcmp (name, "fp=xx") == 0) + mips_opts.fp = 0; else if (strcmp (name, "fp=64") == 0) - { - if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) - as_warn (_("%s isa does not support 64-bit floating point registers"), - mips_cpu_info_from_isa (mips_opts.isa)->name); - mips_opts.fp32 = 0; - } + mips_opts.fp = 64; else if (strcmp (name, "softfloat") == 0) mips_opts.soft_float = 1; else if (strcmp (name, "hardfloat") == 0) @@ -14888,47 +15510,35 @@ s_mipsset (int x ATTRIBUTE_UNUSED) mips_opts.single_float = 1; else if (strcmp (name, "doublefloat") == 0) mips_opts.single_float = 0; + else if (strcmp (name, "nooddspreg") == 0) + mips_opts.nooddspreg = 1; + else if (strcmp (name, "oddspreg") == 0) + mips_opts.nooddspreg = 0; else if (strcmp (name, "mips16") == 0 || strcmp (name, "MIPS-16") == 0) - { - if (mips_opts.micromips == 1) - as_fatal (_("`mips16' cannot be used with `micromips'")); - mips_opts.mips16 = 1; - } + mips_opts.mips16 = 1; else if (strcmp (name, "nomips16") == 0 || strcmp (name, "noMIPS-16") == 0) mips_opts.mips16 = 0; else if (strcmp (name, "micromips") == 0) - { - if (mips_opts.mips16 == 1) - as_fatal (_("`micromips' cannot be used with `mips16'")); - mips_opts.micromips = 1; - } + mips_opts.micromips = 1; else if (strcmp (name, "nomicromips") == 0) mips_opts.micromips = 0; else if (name[0] == 'n' && name[1] == 'o' && (ase = mips_lookup_ase (name + 2))) - mips_set_ase (ase, FALSE); + mips_set_ase (ase, &mips_opts, FALSE); else if ((ase = mips_lookup_ase (name))) - mips_set_ase (ase, TRUE); + mips_set_ase (ase, &mips_opts, TRUE); else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) { - int reset = 0; - /* Permit the user to change the ISA and architecture on the fly. Needless to say, misuse can cause serious problems. */ - if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) - { - reset = 1; - mips_opts.isa = file_mips_isa; - mips_opts.arch = file_mips_arch; - } - else if (strncmp (name, "arch=", 5) == 0) + if (strncmp (name, "arch=", 5) == 0) { const struct mips_cpu_info *p; - p = mips_parse_cpu("internal use", name + 5); + p = mips_parse_cpu ("internal use", name + 5); if (!p) as_bad (_("unknown architecture %s"), name + 5); else @@ -14941,7 +15551,7 @@ s_mipsset (int x ATTRIBUTE_UNUSED) { const struct mips_cpu_info *p; - p = mips_parse_cpu("internal use", name); + p = mips_parse_cpu ("internal use", name); if (!p) as_bad (_("unknown ISA level %s"), name + 4); else @@ -14952,42 +15562,6 @@ s_mipsset (int x ATTRIBUTE_UNUSED) } else as_bad (_("unknown ISA or architecture %s"), name); - - switch (mips_opts.isa) - { - case 0: - break; - case ISA_MIPS1: - case ISA_MIPS2: - case ISA_MIPS32: - case ISA_MIPS32R2: - mips_opts.gp32 = 1; - mips_opts.fp32 = 1; - break; - case ISA_MIPS3: - case ISA_MIPS4: - case ISA_MIPS5: - case ISA_MIPS64: - case ISA_MIPS64R2: - mips_opts.gp32 = 0; - if (mips_opts.arch == CPU_R5900) - { - mips_opts.fp32 = 1; - } - else - { - mips_opts.fp32 = 0; - } - break; - default: - as_bad (_("unknown ISA level %s"), name + 4); - break; - } - if (reset) - { - mips_opts.gp32 = file_mips_gp32; - mips_opts.fp32 = file_mips_fp32; - } } else if (strcmp (name, "autoextend") == 0) mips_opts.noautoextend = 0; @@ -14997,6 +15571,68 @@ s_mipsset (int x ATTRIBUTE_UNUSED) mips_opts.insn32 = TRUE; else if (strcmp (name, "noinsn32") == 0) mips_opts.insn32 = FALSE; + else if (strcmp (name, "sym32") == 0) + mips_opts.sym32 = TRUE; + else if (strcmp (name, "nosym32") == 0) + mips_opts.sym32 = FALSE; + else + return FALSE; + return TRUE; +} + +/* Handle the .set pseudo-op. */ + +static void +s_mipsset (int x ATTRIBUTE_UNUSED) +{ + char *name = input_line_pointer, ch; + int prev_isa = mips_opts.isa; + + file_mips_check_options (); + + while (!is_end_of_line[(unsigned char) *input_line_pointer]) + ++input_line_pointer; + ch = *input_line_pointer; + *input_line_pointer = '\0'; + + if (strchr (name, ',')) + { + /* Generic ".set" directive; use the generic handler. */ + *input_line_pointer = ch; + input_line_pointer = name; + s_set (0); + return; + } + + if (strcmp (name, "reorder") == 0) + { + if (mips_opts.noreorder) + end_noreorder (); + } + else if (strcmp (name, "noreorder") == 0) + { + if (!mips_opts.noreorder) + start_noreorder (); + } + else if (strcmp (name, "macro") == 0) + mips_opts.warn_about_macros = 0; + else if (strcmp (name, "nomacro") == 0) + { + if (mips_opts.noreorder == 0) + as_bad (_("`noreorder' must be set before `nomacro'")); + mips_opts.warn_about_macros = 1; + } + else if (strcmp (name, "gp=default") == 0) + mips_opts.gp = file_mips_opts.gp; + else if (strcmp (name, "fp=default") == 0) + mips_opts.fp = file_mips_opts.fp; + else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) + { + mips_opts.isa = file_mips_opts.isa; + mips_opts.arch = file_mips_opts.arch; + mips_opts.gp = file_mips_opts.gp; + mips_opts.fp = file_mips_opts.fp; + } else if (strcmp (name, "push") == 0) { struct mips_option_stack *s; @@ -15027,23 +15663,87 @@ s_mipsset (int x ATTRIBUTE_UNUSED) free (s); } } - else if (strcmp (name, "sym32") == 0) - mips_opts.sym32 = TRUE; - else if (strcmp (name, "nosym32") == 0) - mips_opts.sym32 = FALSE; - else if (strchr (name, ',')) + else if (!parse_code_option (name)) + as_warn (_("tried to set unrecognized symbol: %s\n"), name); + + /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp + registers based on what is supported by the arch/cpu. */ + if (mips_opts.isa != prev_isa) { - /* Generic ".set" directive; use the generic handler. */ - *input_line_pointer = ch; - input_line_pointer = name; - s_set (0); - return; + switch (mips_opts.isa) + { + case 0: + break; + case ISA_MIPS1: + /* MIPS I cannot support FPXX. */ + mips_opts.fp = 32; + /* fall-through. */ + case ISA_MIPS2: + case ISA_MIPS32: + case ISA_MIPS32R2: + case ISA_MIPS32R3: + case ISA_MIPS32R5: + mips_opts.gp = 32; + if (mips_opts.fp != 0) + mips_opts.fp = 32; + break; + case ISA_MIPS32R6: + mips_opts.gp = 32; + mips_opts.fp = 64; + break; + case ISA_MIPS3: + case ISA_MIPS4: + case ISA_MIPS5: + case ISA_MIPS64: + case ISA_MIPS64R2: + case ISA_MIPS64R3: + case ISA_MIPS64R5: + case ISA_MIPS64R6: + mips_opts.gp = 64; + if (mips_opts.fp != 0) + { + if (mips_opts.arch == CPU_R5900) + mips_opts.fp = 32; + else + mips_opts.fp = 64; + } + break; + default: + as_bad (_("unknown ISA level %s"), name + 4); + break; + } } - else + + mips_check_options (&mips_opts, FALSE); + + mips_check_isa_supports_ases (); + *input_line_pointer = ch; + demand_empty_rest_of_line (); +} + +/* Handle the .module pseudo-op. */ + +static void +s_module (int ignore ATTRIBUTE_UNUSED) +{ + char *name = input_line_pointer, ch; + + while (!is_end_of_line[(unsigned char) *input_line_pointer]) + ++input_line_pointer; + ch = *input_line_pointer; + *input_line_pointer = '\0'; + + if (!file_mips_opts_checked) { - as_warn (_("tried to set unrecognized symbol: %s\n"), name); + if (!parse_code_option (name)) + as_bad (_(".module used with unrecognized symbol: %s\n"), name); + + /* Update module level settings from mips_opts. */ + file_mips_opts = mips_opts; } - mips_check_isa_supports_ases (); + else + as_bad (_(".module is not permitted after generating code")); + *input_line_pointer = ch; demand_empty_rest_of_line (); } @@ -15090,6 +15790,8 @@ s_cpload (int ignore ATTRIBUTE_UNUSED) int reg; int in_shared; + file_mips_check_options (); + /* If we are not generating SVR4 PIC code, or if this is NewABI code, .cpload is ignored. */ if (mips_pic != SVR4_PIC || HAVE_NEWABI) @@ -15167,6 +15869,8 @@ s_cpsetup (int ignore ATTRIBUTE_UNUSED) expressionS ex_sym; int reg1; + file_mips_check_options (); + /* If we are not generating SVR4 PIC code, .cpsetup is ignored. We also need NewABI support. */ if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) @@ -15270,6 +15974,8 @@ s_cpsetup (int ignore ATTRIBUTE_UNUSED) static void s_cplocal (int ignore ATTRIBUTE_UNUSED) { + file_mips_check_options (); + /* If we are not generating SVR4 PIC code, or if this is not NewABI code, .cplocal is ignored. */ if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) @@ -15298,6 +16004,8 @@ s_cprestore (int ignore ATTRIBUTE_UNUSED) { expressionS ex; + file_mips_check_options (); + /* If we are not generating SVR4 PIC code, or if this is NewABI code, .cprestore is ignored. */ if (mips_pic != SVR4_PIC || HAVE_NEWABI) @@ -15345,6 +16053,8 @@ s_cpreturn (int ignore ATTRIBUTE_UNUSED) { expressionS ex; + file_mips_check_options (); + /* If we are not generating SVR4 PIC code, .cpreturn is ignored. We also need NewABI support. */ if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) @@ -15579,6 +16289,8 @@ s_cpadd (int ignore ATTRIBUTE_UNUSED) { int reg; + file_mips_check_options (); + /* This is ignored when not generating SVR4 PIC code. */ if (mips_pic != SVR4_PIC) { @@ -15629,10 +16341,15 @@ s_nan (int ignore ATTRIBUTE_UNUSED) if (i == sizeof (str_2008) - 1 && memcmp (input_line_pointer, str_2008, i) == 0) - mips_flag_nan2008 = TRUE; + mips_nan2008 = 1; else if (i == sizeof (str_legacy) - 1 && memcmp (input_line_pointer, str_legacy, i) == 0) - mips_flag_nan2008 = FALSE; + { + if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) + mips_nan2008 = 0; + else + as_fatal (_("current isa does not support legacy NaN")); + } else as_bad (_("bad .nan directive")); @@ -16410,7 +17127,13 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) || fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 || fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 - || fixp->fx_r_type == BFD_RELOC_32_PCREL); + || fixp->fx_r_type == BFD_RELOC_32_PCREL + || fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2 + || fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2 + || fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3 + || fixp->fx_r_type == BFD_RELOC_MIPS_19_PCREL_S2 + || fixp->fx_r_type == BFD_RELOC_HI16_S_PCREL + || fixp->fx_r_type == BFD_RELOC_LO16_PCREL); /* At this point, fx_addnumber is "symbol offset - pcrel address". Relocations want only the symbol offset. */ @@ -16539,11 +17262,21 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) switch ((insn >> 28) & 0xf) { case 4: - /* bc[0-3][tf]l? instructions can have the condition - reversed by tweaking a single TF bit, and their - opcodes all have 0x4???????. */ - gas_assert ((insn & 0xf3e00000) == 0x41000000); - insn ^= 0x00010000; + if ((insn & 0xff000000) == 0x47000000 + || (insn & 0xff600000) == 0x45600000) + { + /* BZ.df/BNZ.df, BZ.V/BNZ.V can have the condition + reversed by tweaking bit 23. */ + insn ^= 0x00800000; + } + else + { + /* bc[0-3][tf]l? instructions can have the condition + reversed by tweaking a single TF bit, and their + opcodes all have 0x4???????. */ + gas_assert ((insn & 0xf3e00000) == 0x41000000); + insn ^= 0x00010000; + } break; case 0: @@ -16810,6 +17543,11 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) || (insn & 0xffe30000) == 0x42800000 /* bc2f */ || (insn & 0xffe30000) == 0x42a00000) /* bc2t */ insn ^= 0x00200000; + else if ((insn & 0xff000000) == 0x83000000 /* BZ.df + BNZ.df */ + || (insn & 0xff600000) == 0x81600000) /* BZ.V + BNZ.V */ + insn ^= 0x00800000; else abort (); @@ -17129,11 +17867,131 @@ mips_add_dot_label (symbolS *sym) mips_compressed_mark_label (sym); } +/* Converting ASE flags from internal to .MIPS.abiflags values. */ +static unsigned int +mips_convert_ase_flags (int ase) +{ + unsigned int ext_ases = 0; + + if (ase & ASE_DSP) + ext_ases |= AFL_ASE_DSP; + if (ase & ASE_DSPR2) + ext_ases |= AFL_ASE_DSPR2; + if (ase & ASE_EVA) + ext_ases |= AFL_ASE_EVA; + if (ase & ASE_MCU) + ext_ases |= AFL_ASE_MCU; + if (ase & ASE_MDMX) + ext_ases |= AFL_ASE_MDMX; + if (ase & ASE_MIPS3D) + ext_ases |= AFL_ASE_MIPS3D; + if (ase & ASE_MT) + ext_ases |= AFL_ASE_MT; + if (ase & ASE_SMARTMIPS) + ext_ases |= AFL_ASE_SMARTMIPS; + if (ase & ASE_VIRT) + ext_ases |= AFL_ASE_VIRT; + if (ase & ASE_MSA) + ext_ases |= AFL_ASE_MSA; + if (ase & ASE_XPA) + ext_ases |= AFL_ASE_XPA; + + return ext_ases; +} /* Some special processing for a MIPS ELF file. */ void mips_elf_final_processing (void) { + int fpabi; + Elf_Internal_ABIFlags_v0 flags; + + flags.version = 0; + flags.isa_rev = 0; + switch (file_mips_opts.isa) + { + case INSN_ISA1: + flags.isa_level = 1; + break; + case INSN_ISA2: + flags.isa_level = 2; + break; + case INSN_ISA3: + flags.isa_level = 3; + break; + case INSN_ISA4: + flags.isa_level = 4; + break; + case INSN_ISA5: + flags.isa_level = 5; + break; + case INSN_ISA32: + flags.isa_level = 32; + flags.isa_rev = 1; + break; + case INSN_ISA32R2: + flags.isa_level = 32; + flags.isa_rev = 2; + break; + case INSN_ISA32R3: + flags.isa_level = 32; + flags.isa_rev = 3; + break; + case INSN_ISA32R5: + flags.isa_level = 32; + flags.isa_rev = 5; + break; + case INSN_ISA32R6: + flags.isa_level = 32; + flags.isa_rev = 6; + break; + case INSN_ISA64: + flags.isa_level = 64; + flags.isa_rev = 1; + break; + case INSN_ISA64R2: + flags.isa_level = 64; + flags.isa_rev = 2; + break; + case INSN_ISA64R3: + flags.isa_level = 64; + flags.isa_rev = 3; + break; + case INSN_ISA64R5: + flags.isa_level = 64; + flags.isa_rev = 5; + break; + case INSN_ISA64R6: + flags.isa_level = 64; + flags.isa_rev = 6; + break; + } + + flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; + flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE + : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 + : (file_mips_opts.fp == 64) ? AFL_REG_64 + : AFL_REG_32; + flags.cpr2_size = AFL_REG_NONE; + flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, + Tag_GNU_MIPS_ABI_FP); + flags.isa_ext = bfd_mips_isa_ext (stdoutput); + flags.ases = mips_convert_ase_flags (file_mips_opts.ase); + if (file_ase_mips16) + flags.ases |= AFL_ASE_MIPS16; + if (file_ase_micromips) + flags.ases |= AFL_ASE_MICROMIPS; + flags.flags1 = 0; + if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) + || file_mips_opts.fp == 64) + && !file_mips_opts.nooddspreg) + flags.flags1 |= AFL_FLAGS1_ODDSPREG; + flags.flags2 = 0; + + bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, + ((Elf_External_ABIFlags_v0 *) + mips_flags_frag)); + /* Write out the register information. */ if (mips_abi != N64_ABI) { @@ -17185,7 +18043,7 @@ mips_elf_final_processing (void) elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; if (file_ase_micromips) elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; - if (file_ase & ASE_MDMX) + if (file_mips_opts.ase & ASE_MDMX) elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; /* Set the MIPS ELF ABI flags. */ @@ -17195,7 +18053,7 @@ mips_elf_final_processing (void) elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; else if (mips_abi == EABI_ABI) { - if (!file_mips_gp32) + if (file_mips_opts.gp == 64) elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; else elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; @@ -17208,11 +18066,13 @@ mips_elf_final_processing (void) if (mips_32bitmode) elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE; - if (mips_flag_nan2008) + if (mips_nan2008 == 1) elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; /* 32 bit code with 64 bit FP registers. */ - if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) + fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, + Tag_GNU_MIPS_ABI_FP); + if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; } @@ -17316,19 +18176,6 @@ mips_handle_align (fragS *fragp) fragp->fr_var = size; } -static void -md_obj_begin (void) -{ -} - -static void -md_obj_end (void) -{ - /* Check for premature end, nesting errors, etc. */ - if (cur_proc_ptr) - as_warn (_("missing .end at end of assembly")); -} - static long get_number (void) { @@ -17663,8 +18510,14 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, + { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, + { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, + { "mips32r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R6, CPU_MIPS32R6 }, { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, + { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, + { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, + { "mips64r6", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R6, CPU_MIPS64R6 }, /* MIPS I */ { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, @@ -17767,6 +18620,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, + /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ + { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, /* MIPS 64 */ { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, @@ -17779,7 +18634,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = /* Broadcom SB-1A CPU core */ { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, - { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A }, + { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A }, /* MIPS 64 Release 2 */ @@ -17880,8 +18735,9 @@ mips_parse_cpu (const char *option, const char *cpu_string) if (ABI_NEEDS_64BIT_REGS (mips_abi)) return mips_cpu_info_from_isa (ISA_MIPS3); - if (file_mips_gp32 >= 0) - return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); + if (file_mips_opts.gp >= 0) + return mips_cpu_info_from_isa (file_mips_opts.gp == 32 + ? ISA_MIPS1 : ISA_MIPS3); return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT ? ISA_MIPS3 @@ -17975,8 +18831,14 @@ MIPS options:\n\ -mips5 generate MIPS ISA V instructions\n\ -mips32 generate MIPS32 ISA instructions\n\ -mips32r2 generate MIPS32 release 2 ISA instructions\n\ +-mips32r3 generate MIPS32 release 3 ISA instructions\n\ +-mips32r5 generate MIPS32 release 5 ISA instructions\n\ +-mips32r6 generate MIPS32 release 6 ISA instructions\n\ -mips64 generate MIPS64 ISA instructions\n\ -mips64r2 generate MIPS64 release 2 ISA instructions\n\ +-mips64r3 generate MIPS64 release 3 ISA instructions\n\ +-mips64r5 generate MIPS64 release 5 ISA instructions\n\ +-mips64r6 generate MIPS64 release 6 ISA instructions\n\ -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); first = 1; @@ -18021,6 +18883,12 @@ MIPS options:\n\ -mmcu generate MCU instructions\n\ -mno-mcu do not generate MCU instructions\n")); fprintf (stream, _("\ +-mmsa generate MSA instructions\n\ +-mno-msa do not generate MSA instructions\n")); + fprintf (stream, _("\ +-mxpa generate eXtended Physical Address (XPA) instructions\n\ +-mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); + fprintf (stream, _("\ -mvirt generate Virtualization instructions\n\ -mno-virt do not generate Virtualization instructions\n")); fprintf (stream, _("\ @@ -18121,3 +18989,92 @@ tc_mips_regname_to_dw2regnum (char *regname) return regnum; } + +/* Implement CONVERT_SYMBOLIC_ATTRIBUTE. + Given a symbolic attribute NAME, return the proper integer value. + Returns -1 if the attribute is not known. */ + +int +mips_convert_symbolic_attribute (const char *name) +{ + static const struct + { + const char * name; + const int tag; + } + attribute_table[] = + { +#define T(tag) {#tag, tag} + T (Tag_GNU_MIPS_ABI_FP), + T (Tag_GNU_MIPS_ABI_MSA), +#undef T + }; + unsigned int i; + + if (name == NULL) + return -1; + + for (i = 0; i < ARRAY_SIZE (attribute_table); i++) + if (streq (name, attribute_table[i].name)) + return attribute_table[i].tag; + + return -1; +} + +void +md_mips_end (void) +{ + int fpabi = Val_GNU_MIPS_ABI_FP_ANY; + + mips_emit_delays (); + if (cur_proc_ptr) + as_warn (_("missing .end at end of assembly")); + + /* Just in case no code was emitted, do the consistency check. */ + file_mips_check_options (); + + /* Set a floating-point ABI if the user did not. */ + if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) + { + + /* Perform consistency checks on the floating-point ABI. */ + fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, + Tag_GNU_MIPS_ABI_FP); + if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) + check_fpabi (fpabi); + } + else + { + /* Soft-float gets precedence over single-float, the two options should + not be used together so this should not matter. */ + if (file_mips_opts.soft_float == 1) + fpabi = Val_GNU_MIPS_ABI_FP_SOFT; + /* Single-float gets precedence over all double_float cases. */ + else if (file_mips_opts.single_float == 1) + fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; + else + { + switch (file_mips_opts.fp) + { + case 32: + if (file_mips_opts.gp == 32) + fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; + break; + case 0: + fpabi = Val_GNU_MIPS_ABI_FP_XX; + break; + case 64: + if (file_mips_opts.gp == 32 && file_mips_opts.nooddspreg) + fpabi = Val_GNU_MIPS_ABI_FP_64A; + else if (file_mips_opts.gp == 32) + fpabi = Val_GNU_MIPS_ABI_FP_64; + else + fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; + break; + } + } + + bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, + Tag_GNU_MIPS_ABI_FP, fpabi); + } +} diff --git a/binutils-2.24/gas/config/tc-mips.h b/binutils-2.24/gas/config/tc-mips.h index c7eaa04..35205ae 100644 --- a/binutils-2.24/gas/config/tc-mips.h +++ b/binutils-2.24/gas/config/tc-mips.h @@ -190,4 +190,12 @@ extern int tc_mips_regname_to_dw2regnum (char *regname); #define DWARF2_DEFAULT_RETURN_COLUMN 31 #define DWARF2_CIE_DATA_ALIGNMENT (-4) +#define DIFF_EXPR_OK +/* We define DIFF_EXPR_OK because of R_MIPS_PC32, but we have no + 64-bit form for n64 CFIs. */ +#define CFI_DIFF_EXPR_OK 0 + +#define CONVERT_SYMBOLIC_ATTRIBUTE(name) mips_convert_symbolic_attribute (name) +extern int mips_convert_symbolic_attribute (const char *); + #endif /* TC_MIPS */ diff --git a/binutils-2.24/gas/configure b/binutils-2.24/gas/configure index 590528c..44db1ee 100755 --- a/binutils-2.24/gas/configure +++ b/binutils-2.24/gas/configure @@ -12036,21 +12036,45 @@ _ACEOF mipsisa32r2 | mipsisa32r2el) mips_cpu=mips32r2 ;; + mipsisa32r3 | mipsisa32r3el) + mips_cpu=mips32r3 + ;; + mipsisa32r5 | mipsisa32r5el) + mips_cpu=mips32r5 + ;; + mipsisa32r6 | mipsisa32r6el) + mips_cpu=mips32r6 + ;; mipsisa64 | mipsisa64el) mips_cpu=mips64 ;; mipsisa64r2 | mipsisa64r2el) mips_cpu=mips64r2 ;; + mipsisa64r3 | mipsisa64r3el) + mips_cpu=mips64r3 + ;; + mipsisa64r5 | mipsisa64r5el) + mips_cpu=mips64r5 + ;; + mipsisa64r6 | mipsisa64r6el) + mips_cpu=mips64r6 + ;; mipstx39 | mipstx39el) mips_cpu=r3900 ;; mips64vr | mips64vrel) mips_cpu=vr4100 ;; + mips64*-*android*) + mips_cpu=mips64r6 + ;; mipsisa32r2* | mipsisa64r2*) mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r2//' -e 's/el$//'` ;; + mipsisa32r6* | mipsisa64r6*) + mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r6//' -e 's/el$//'` + ;; mips64* | mipsisa64* | mipsisa32*) mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..//' -e 's/el$//'` ;; @@ -12089,7 +12113,7 @@ _ACEOF mips*-linux* | mips*-freebsd* | mips*-kfreebsd*-gnu) mips_default_abi=O32_ABI ;; - mips64*-openbsd*) + mips64*-openbsd* | mips64*-*android*) mips_default_abi=N64_ABI ;; *) diff --git a/binutils-2.24/gas/configure.in b/binutils-2.24/gas/configure.in index 121fcfc..06ca650 100644 --- a/binutils-2.24/gas/configure.in +++ b/binutils-2.24/gas/configure.in @@ -213,23 +213,49 @@ changequote([,])dnl mipsisa32r2 | mipsisa32r2el) mips_cpu=mips32r2 ;; + mipsisa32r3 | mipsisa32r3el) + mips_cpu=mips32r3 + ;; + mipsisa32r5 | mipsisa32r5el) + mips_cpu=mips32r5 + ;; + mipsisa32r6 | mipsisa32r6el) + mips_cpu=mips32r6 + ;; mipsisa64 | mipsisa64el) mips_cpu=mips64 ;; mipsisa64r2 | mipsisa64r2el) mips_cpu=mips64r2 ;; + mipsisa64r3 | mipsisa64r3el) + mips_cpu=mips64r3 + ;; + mipsisa64r5 | mipsisa64r5el) + mips_cpu=mips64r5 + ;; + mipsisa64r6 | mipsisa64r6el) + mips_cpu=mips64r6 + ;; mipstx39 | mipstx39el) mips_cpu=r3900 ;; mips64vr | mips64vrel) mips_cpu=vr4100 ;; + mips64*-*android*) + mips_cpu=mips64r6 + ;; mipsisa32r2* | mipsisa64r2*) changequote(,)dnl mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r2//' -e 's/el$//'` changequote([,])dnl ;; + mipsisa32r6* | mipsisa64r6*) +changequote(,)dnl + mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..r6//' -e 's/el$//'` +changequote([,])dnl + ;; mips64* | mipsisa64* | mipsisa32*) changequote(,)dnl mips_cpu=`echo $target_cpu | sed -e 's/[a-z]*..//' -e 's/el$//'` @@ -272,7 +298,7 @@ changequote([,])dnl mips*-linux* | mips*-freebsd* | mips*-kfreebsd*-gnu) mips_default_abi=O32_ABI ;; - mips64*-openbsd*) + mips64*-openbsd* | mips64*-*android*) mips_default_abi=N64_ABI ;; *) diff --git a/binutils-2.24/gas/configure.tgt b/binutils-2.24/gas/configure.tgt index 77c1d9b..130cfa4 100644 --- a/binutils-2.24/gas/configure.tgt +++ b/binutils-2.24/gas/configure.tgt @@ -324,7 +324,8 @@ case ${generic_target} in mips*-*-freebsd* | mips*-*-kfreebsd*-gnu) fmt=elf em=freebsd ;; mips-*-sysv4*MP* | mips-*-gnu*) fmt=elf em=tmips ;; - mips*-sde-elf* | mips*-mti-elf*) fmt=elf em=tmips ;; + mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) + fmt=elf em=tmips ;; mips-*-elf* | mips-*-rtems*) fmt=elf ;; mips-*-netbsd*) fmt=elf em=tmips ;; mips-*-openbsd*) fmt=elf em=tmips ;; diff --git a/binutils-2.24/gas/doc/as.texinfo b/binutils-2.24/gas/doc/as.texinfo index de6b5b0..e22e16e 100644 --- a/binutils-2.24/gas/doc/as.texinfo +++ b/binutils-2.24/gas/doc/as.texinfo @@ -399,9 +399,12 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. [@b{-g}[@var{debug level}]] [@b{-G} @var{num}] [@b{-KPIC}] [@b{-call_shared}] [@b{-non_shared}] [@b{-xgot} [@b{-mvxworks-pic}] [@b{-mabi}=@var{ABI}] [@b{-32}] [@b{-n32}] [@b{-64}] [@b{-mfp32}] [@b{-mgp32}] + [@b{-mfp64}] [@b{-mgp64}] [@b{-mfpxx}] + [@b{-modd-spreg}] [@b{-mno-odd-spreg}] [@b{-march}=@var{CPU}] [@b{-mtune}=@var{CPU}] [@b{-mips1}] [@b{-mips2}] [@b{-mips3}] [@b{-mips4}] [@b{-mips5}] [@b{-mips32}] [@b{-mips32r2}] - [@b{-mips64}] [@b{-mips64r2}] + [@b{-mips32r3}] [@b{-mips32r5}] [@b{-mips32r6}] [@b{-mips64}] [@b{-mips64r2}] + [@b{-mips64r3}] [@b{-mips64r5}] [@b{-mips64r6}] [@b{-construct-floats}] [@b{-no-construct-floats}] [@b{-mnan=@var{encoding}}] [@b{-trap}] [@b{-no-break}] [@b{-break}] [@b{-no-trap}] @@ -412,10 +415,13 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. [@b{-mdmx}] [@b{-no-mdmx}] [@b{-mdsp}] [@b{-mno-dsp}] [@b{-mdspr2}] [@b{-mno-dspr2}] + [@b{-mmsa}] [@b{-mno-msa}] + [@b{-mxpa}] [@b{-mno-xpa}] [@b{-mmt}] [@b{-mno-mt}] [@b{-mmcu}] [@b{-mno-mcu}] [@b{-minsn32}] [@b{-mno-insn32}] [@b{-mfix7000}] [@b{-mno-fix7000}] + [@b{-mfix-rm7000}] [@b{-mno-fix-rm7000}] [@b{-mfix-vr4120}] [@b{-mno-fix-vr4120}] [@b{-mfix-vr4130}] [@b{-mno-fix-vr4130}] [@b{-mdebug}] [@b{-no-mdebug}] @@ -1248,15 +1254,24 @@ Generate ``little endian'' format output. @itemx -mips5 @itemx -mips32 @itemx -mips32r2 +@itemx -mips32r3 +@itemx -mips32r5 +@itemx -mips32r6 @itemx -mips64 @itemx -mips64r2 +@itemx -mips64r3 +@itemx -mips64r5 +@itemx -mips64r6 Generate code for a particular MIPS Instruction Set Architecture level. @samp{-mips1} is an alias for @samp{-march=r3000}, @samp{-mips2} is an alias for @samp{-march=r6000}, @samp{-mips3} is an alias for @samp{-march=r4000} and @samp{-mips4} is an alias for @samp{-march=r8000}. -@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and -@samp{-mips64r2} correspond to generic MIPS V, MIPS32, MIPS32 Release 2, -MIPS64, and MIPS64 Release 2 ISA processors, respectively. +@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3}, +@samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2}, +@samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to generic +MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 +Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and +MIPS64 Release 6 ISA processors, respectively. @item -march=@var{cpu} Generate code for a particular MIPS CPU. @@ -1269,6 +1284,11 @@ Schedule and tune for a particular MIPS CPU. Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions. +@item -mfix-rm7000 +@itemx -mno-fix-rm7000 +Cause nops to be inserted if a dmult or dmultu instruction is +followed by a load instruction. + @item -mdebug @itemx -no-mdebug Cause stabs-style debugging output to go into an ECOFF-style .mdebug @@ -1285,6 +1305,26 @@ flags force a certain group of registers to be treated as 32 bits wide at all times. @samp{-mgp32} controls the size of general-purpose registers and @samp{-mfp32} controls the size of floating-point registers. +@item -mgp64 +@itemx -mfp64 +The register sizes are normally inferred from the ISA and ABI, but these +flags force a certain group of registers to be treated as 64 bits wide at +all times. @samp{-mgp64} controls the size of general-purpose registers +and @samp{-mfp64} controls the size of floating-point registers. + +@item -mfpxx +The register sizes are normally inferred from the ISA and ABI, but using +this flag in combination with @samp{-mabi=32} enables an ABI variant +which will operate correctly with floating-point registers which are +32 or 64 bits wide. + +@item -modd-spreg +@itemx -mno-odd-spreg +Enable use of floating-point operations on odd-numbered single-precision +registers when supported by the ISA. By default @samp{-modd-spreg} is +selected except when targetting a generic MIPS architecture in combination +with @samp{-mfpxx} then @samp{-mno-odd-spreg} is selected. + @item -mips16 @itemx -no-mips16 Generate code for the MIPS 16 processor. This is equivalent to putting @@ -1329,6 +1369,18 @@ This option implies -mdsp. This tells the assembler to accept DSP Release 2 instructions. @samp{-mno-dspr2} turns off this option. +@item -mmsa +@itemx -mno-msa +Generate code for the MIPS SIMD Architecture Extension. +This tells the assembler to accept MSA instructions. +@samp{-mno-msa} turns off this option. + +@item -mxpa +@itemx -mno-xpa +Generate code for the MIPS eXtended Physical Address (XPA) Extension. +This tells the assembler to accept XPA instructions. +@samp{-mno-xpa} turns off this option. + @item -mmt @itemx -mno-mt Generate code for the MT Application Specific Extension. diff --git a/binutils-2.24/gas/doc/c-mips.texi b/binutils-2.24/gas/doc/c-mips.texi index 8a25a76..19dde2a 100644 --- a/binutils-2.24/gas/doc/c-mips.texi +++ b/binutils-2.24/gas/doc/c-mips.texi @@ -30,6 +30,7 @@ Assembly Language Programming'' in the same work. * MIPS assembly options:: Directives to control code generation * MIPS autoextend:: Directives for extending MIPS 16 bit instructions * MIPS insn:: Directive to mark data as an instruction +* MIPS FP ABIs:: Marking which FP ABI is in use * MIPS NaN Encodings:: Directives to record which NaN encoding is being used * MIPS Option Stack:: Directives to save and restore options * MIPS ASE Instruction Generation Overrides:: Directives to control @@ -83,17 +84,26 @@ VxWorks-style position-independent macro expansions. @itemx -mips5 @itemx -mips32 @itemx -mips32r2 +@itemx -mips32r3 +@itemx -mips32r5 +@itemx -mips32r6 @itemx -mips64 @itemx -mips64r2 +@itemx -mips64r3 +@itemx -mips64r5 +@itemx -mips64r6 Generate code for a particular MIPS Instruction Set Architecture level. @samp{-mips1} corresponds to the R2000 and R3000 processors, @samp{-mips2} to the R6000 processor, @samp{-mips3} to the R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors. -@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and -@samp{-mips64r2} correspond to generic MIPS V, MIPS32, MIPS32 Release 2, -MIPS64, and MIPS64 Release 2 ISA processors, respectively. You can also -switch instruction sets during the assembly; see @ref{MIPS ISA, -Directives to override the ISA level}. +@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3}, +@samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2}, +@samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to +generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 +Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64 +Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, +respectively. You can also switch instruction sets during the assembly; +see @ref{MIPS ISA, Directives to override the ISA level}. @item -mgp32 @itemx -mfp32 @@ -121,6 +131,23 @@ The @code{.set gp=64} and @code{.set fp=64} directives allow the size of registers to be changed for parts of an object. The default value is restored by @code{.set gp=default} and @code{.set fp=default}. +@item -mfpxx +Make no assumptions about whether 32-bit or 64-bit floating-point +registers are available. This is provided to support having modules +compatible with either @samp{-mfp32} or @samp{-mfp64}. This option can +only be used with MIPS II and above. + +The @code{.set fp=xx} directive allows a part of an object to be marked +as not making assumptions about 32-bit or 64-bita FP registers. The +default value is restored by @code{.set fp=default}. + +@item -modd-spreg +@itemx -mno-odd-spreg +Enable use of floating-point operations on odd-numbered single-precision +registers when supported by the ISA. By default @samp{-modd-spreg} is +selected except when targetting a generic MIPS architecture in combination +with @samp{-mfpxx} then @samp{-mno-odd-spreg} is selected. + @item -mips16 @itemx -no-mips16 Generate code for the MIPS 16 processor. This is equivalent to putting @@ -179,6 +206,18 @@ Generate code for the MCU Application Specific Extension. This tells the assembler to accept MCU instructions. @samp{-mno-mcu} turns off this option. +@item -mmsa +@itemx -mno-msa +Generate code for the MIPS SIMD Architecture Extension. +This tells the assembler to accept MSA instructions. +@samp{-mno-msa} turns off this option. + +@item -mxpa +@itemx -mno-xpa +Generate code for the MIPS eXtended Physical Address (XPA) Extension. +This tells the assembler to accept XPA instructions. +@samp{-mno-xpa} turns off this option. + @item -mvirt @itemx -mno-virt Generate code for the Virtualization Application Specific Extension. @@ -200,6 +239,11 @@ selected, allowing all instructions to be used. Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions. +@item -mfix-rm7000 +@itemx -mno-fix-rm7000 +Cause nops to be inserted if a dmult or dmultu instruction is +followed by a load instruction. + @item -mfix-loongson2f-jump @itemx -mno-fix-loongson2f-jump Eliminate instruction fetch from outside 256M region to work around the @@ -328,6 +372,7 @@ m14kec, 1004kf2_1, 1004kf, 1004kf1_1, +p5600, 5kc, 5kf, 20kc, @@ -636,8 +681,8 @@ Small data is not supported for SVR4-style PIC. @kindex @code{.set mips@var{n}} @sc{gnu} @code{@value{AS}} supports an additional directive to change the MIPS Instruction Set Architecture level on the fly: @code{.set -mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 -or 64r2. +mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3, +32r5, 32r6, 64, 64r2, 64r3, 64r5 or 64r6. The values other than 0 make the assembler accept instructions for the corresponding ISA level, from that point on in the assembly. @code{.set mips@var{n}} affects not only which instructions @@ -671,6 +716,20 @@ Traditional MIPS assemblers do not support this directive. @node MIPS assembly options @section Directives to control code generation +@cindex MIPS directives to override command line options +@kindex @code{.module} +The @code{.module} directive allows command line options to be set directly +from assembly. The format of the directive matches the @code{.set} +directive but only those options which are relevant to a whole module are +supported. The effect of a @code{.module} directive is the same as the +corresponding command line option. Where @code{.set} directives support +returning to a default then the @code{.module} directives do not as they +define the defaults. + +These module-level directives must appear first in assembly. + +Traditional MIPS assemblers do not support this directive. + @cindex MIPS 32-bit microMIPS instruction generation override @kindex @code{.set insn32} @kindex @code{.set noinsn32} @@ -733,6 +792,115 @@ baz: @end example +@node MIPS FP ABIs +@section Directives to control the FP ABI +@menu +* MIPS FP ABI History:: History of FP ABIs +* MIPS FP ABI Variants:: Supported FP ABIs +* MIPS FP ABI Selection:: Automatic selection of FP ABI +* MIPS FP ABI Compatibility:: Linking different FP ABI variants +@end menu + +@node MIPS FP ABI History +@subsection History of FP ABIs +@cindex @code{.gnu_attribute 4, @var{n}} directive, MIPS +@cindex @code{.gnu_attribute Tag_GNU_MIPS_ABI_FP, @var{n}} directive, MIPS +The MIPS ABIs support a variety of different floating-point extensions +where calling-convention and register sizes vary for floating-point data. +The extensions exist to support a wide variety of optional architecture +features. The resulting ABI variants are generally incompatible with each +other and must be tracked carefully. + +Traditionally the use of an explicit @code{.gnu_attribute 4, @var{n}} +directive is used to indicate which ABI is in use by a specific module. +It was then left to the user to ensure that command line options and the +selected ABI were compatible with some potential for inconsistencies. + +@node MIPS FP ABI Variants +@subsection Supported FP ABIs +The supported floating-point ABI variants are: + +@table @code +@item 0 - No floating-point +This variant is used to indicate that floating-point is not used within +the module at all and therefore has no impact on the ABI. This is the +default. + +@item 1 - Double-precision +This variant indicates that double-precision support is used. For 64-bit +ABIs this means that 64-bit wide floating-point registers are required. +For 32-bit ABIs this means that 32-bit wide floating-point registers are +required and double-precision operations use pairs of registers. + +@item 2 - Single-precision +This variant indicates that single-precision support is used. Double +precision operations will be supported via soft-float routines. + +@item 3 - Soft-float +This variant indicates that although floating-point support is used all +operations are emulated in software. This means the ABI is modified to +pass all floating-point data in general-purpose registers. + +@item 4 - Deprecated +This variant existed as an initial attempt at supporting 64-bit wide +floating-point registers for O32 ABI on a MIPS32r2 cpu. This has been +superceded by @value{5} and @value{6}. + +@item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU +This variant is used by 32-bit ABIs to indicate that the floating-point +code in the module has been designed to operate correctly with either +32-bit wide or 64-bit wide floating-point registers. Double-precision +support is used. Only O32 currently supports this variant and requires +a minimum architecture of MIPS II. + +@item 6 - Double-precision 32-bit FPU, 64-bit FPU +This variant is used by 32-bit ABIs to indicate that the floating-point +code in the module requires 64-bit wide floating-point registers. +Double-precision support is used. Only O32 currently supports this +variant and requires a minimum architecture of MIPS32r2. + +@item 7 - Double-precision compat 32-bit FPU, 64-bit FPU +This variant is used by 32-bit ABIs to indicate that the floating-point +code in the module requires 64-bit wide floating-point registers. +Double-precision support is used. This differs from the previous ABI +as it restricts use of odd-numbered single-precision registers. Only +O32 currently supports this variant and requires a minimum architecture +of MIPS32r2. +@end table + +@node MIPS FP ABI Selection +@subsection Automatic selection of FP ABI +@cindex @code{.module fp=@var{nn}} directive, MIPS +In order to simplify and add safety to the process of selecting the +correct floating-point ABI, the assembler will automatically infer the +correct @code{.gnu_attribute 4, @var{n}} directive based on command line +options and @code{.module} overrides. Where an explicit +@code{.gnu_attribute 4, @var{n}} directive has been seen then a warning +will be raised if it does not match an inferred setting. + +The floating-point ABI is inferred as follows. If @samp{-msoft-float} +has been used the module will be marked as soft-float. If +@samp{-msingle-float} has been used then the module will be marked as +single-precision. The remaining ABIs are then selected based +on the FP register width. Double-precision is selected if the width +of GP and FP registers match and the special double-precision variants +for 32-bit ABIs are then selected depending on @samp{-mfpxx}, +@samp{-mfp64} and @samp{-mno-odd-spreg}. + +@node MIPS FP ABI Compatibility +@subsection Linking different FP ABI variants +Modules using the default FP ABI (no floating-point) can be linked with +any other (singular) FP ABI variant. + +Special compatibility support exists for O32 with the four +double-precision FP ABI variants. The @samp{-mfpxx} FP ABI is specifically +designed to be compatible with the standard double-precision ABI and the +@samp{-mfp64} FP ABIs. This makes it desirable for O32 modules to be +built as @samp{-mfpxx} to ensure the maximum compatibility with other +modules produced for more specific needs. The only FP ABIs which cannot +be linked together are the standard double-precision ABI and the full +@samp{-mfp64} ABI with @samp{-modd-spreg}. + @node MIPS NaN Encodings @section Directives to record which NaN encoding is being used @@ -853,6 +1021,14 @@ from the MCU Application Specific Extension from that point on in the assembly. The @code{.set nomcu} directive prevents MCU instructions from being accepted. +@cindex MIPS SIMD Architecture instruction generation override +@kindex @code{.set msa} +@kindex @code{.set nomsa} +The directive @code{.set msa} makes the assembler accept instructions +from the MIPS SIMD Architecture Extension from that point on +in the assembly. The @code{.set nomsa} directive prevents MSA +instructions from being accepted. + @cindex Virtualization instruction generation override @kindex @code{.set virt} @kindex @code{.set novirt} @@ -861,6 +1037,13 @@ from the Virtualization Application Specific Extension from that point on in the assembly. The @code{.set novirt} directive prevents Virtualization instructions from being accepted. +@cindex MIPS eXtended Physical Address (XPA) instruction generation override +@kindex @code{.set xpa} +@kindex @code{.set noxpa} +The directive @code{.set xpa} makes the assembler accept instructions +from the XPA Extension from that point on in the assembly. The +@code{.set noxpa} directive prevents XPA instructions from being accepted. + Traditional MIPS assemblers do not support these directives. @node MIPS Floating-Point diff --git a/binutils-2.24/gas/testsuite/ChangeLog b/binutils-2.24/gas/testsuite/ChangeLog index be67b6e..74a9b0b 100644 --- a/binutils-2.24/gas/testsuite/ChangeLog +++ b/binutils-2.24/gas/testsuite/ChangeLog @@ -1,8 +1,100 @@ +2014-05-20 Matthew Fortune <matthew.fortune@imgtec.com> + + * gas/mips/mips.exp: Add new tests. Use 64-bit ABI for relax-bc1any. + Fix micromips arch definition to use mips64r2 consistently. + * gas/mips/module-defer-warn1.s: New. + * gas/mips/module-defer-warn1.d: New. + * gas/mips/module-defer-warn2.s: New. + * gas/mips/module-defer-warn2.l: New. + * gas/mips/module-override.d: New. + * gas/mips/module-override.s: New. + * gas/mips/mips-gp32-fp64.l: Update expected output. + * gas/mips/mips-gp64-fp32-pic.l: Update expected output. + * gas/mips/mips-gp64-fp32.l: Update expected output. + +2014-05-20 Matthew Fortune <matthew.fortune@imgtec.com> + + * gas/mips/micromips@msa-branch.d: Rework expected output for fp64. + * gas/mips/msa-branch.d: Likewise. + +2014-05-08 Matthew Fortune <matthew.fortune@imgtec.com> + + * gas/mips/attr-gnu-abi-fp-1.s: New. + * gas/mips/attr-gnu-abi-fp-1.d: New. + * gas/mips/attr-gnu-abi-msa-1.s: New. + * gas/mips/attr-gnu-abi-msa-1.d: New. + * gas/mips/mips.exp: Add new tests. + +2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com> + + * gas/mips/mips.exp: Add MIPS32r5 tests. Also add the mips32r3, + mips32r5, mips64r3 and mips64r5 isas to the testsuite. + * gas/mips/r5.s: New test. + * gas/mips/r5.d: Likewise. + +2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com> + + * gas/mips/mips.exp: Add xpa tests. + * gas/mips/xpa.s: New test. + * gas/mips/xpa.d: Likewise. + +2014-03-20 Richard Sandiford <rdsandiford@googlemail.com> + + * gas/all/gas.exp: Remove XFAIL of forward.d for MIPS. + * gas/mips/pcrel-1.s, gas/mips/pcrel-1.d, gas/mips/pcrel-2.s, + gas/mips/pcrel-2.d, gas/mips/pcrel-3.s, gas/mips/pcrel-3.l, + gas/mips/pcrel-4.s, gas/mips/pcrel-4-32.d, gas/mips/pcrel-4-n32.d, + gas/mips/pcrel-4-64.d: New tests. + * gas/mips/mips.exp: Run them. + * gas/mips/lui-2.l: Tweak error message for line 7. + +2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com> + + * gas/mips/mips.exp: Add CP1 register name tests. + * gas/mips/cp1-names-mips32.d: New test. + * gas/mips/cp1-names-mips32r2.d: New test. + * gas/mips/cp1-names-mips64.d: New test. + * gas/mips/cp1-names-mips64r2.d: New test. + * gas/mips/cp1-names-numeric.d: New test. + * gas/mips/cp1-names-r3000.d: New test. + * gas/mips/cp1-names-r4000.d: New test. + * gas/mips/cp1-names-sb1.d: New test. + * gas/mips/cp1-names.s: New test. + * gas/mips/micromips-insn32.d: Add the correct symbolic names for the CP1 + registers. + * gas/mips/micromips-noinsn32.d: Likewise. + * gas/mips/micromips-trap.d: Likewise. + * gas/mips/micromips.d: Likewise. + +2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com> + + * gas/mips/msa.s: Reduced maximum element index range + for sldi, splati, copy_s, copy_u, insert and insve instructions. + * gas/mips/msa64.s: Likewise. + * gas/mips/micromips@msa.d: Likewise. + * gas/mips/micromips@msa64.d: Likewise. + * gas/mips/msa.d: Likewise. + * gas/mips/msa64.d: Likewise. + +2013-11-27 Matthew Fortune <matthew.fortune@imgtec.com> + + * gas/mips/mips.exp: Consider mips-mti-elf the same as mips-sde-elf + 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com> * gas/aarch64/msr.s: Add tests. * gas/aarch64/msr.d: Update. +2013-11-19 Catherine Moore <clm@codesourcery.com> + + * gas/mips/fix-pmc-rm7000-1.d: New. + * gas/mips/fix-pmc-rm7000-1.s: New. + * gas/mips/fix-pmc-rm7000-2.d: New. + * gas/mips/fix-pmc-rm7000-2.s: New. + * gas/mips/micromips@fix-pmc-rm7000-1.d: New. + * gas/mips/micromips@fix-pmc-rm7000-2.d: New. + * gas/mips/mips.exp: Run new tests. + 2013-11-18 Renlin Li <Renlin.Li@arm.com> * gas/arm/attr-march-armv7ve.d: New test case for armv7ve. @@ -83,6 +175,21 @@ * gas/aarch64/advsimd-mov-bad.d: New file. * gas/aarch64/advsimd-mov-bad.s: Likewise. +2013-10-18 Chao-ying Fu <Chao-ying.Fu@imgtec.com> + + * gas/mips/micromips@msa-branch.d, gas/mips/msa-branch.d, + gas/mips/msa-branch.s: New. + * gas/mips/mips.exp: Run new tests. + +2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> + + * gas/mips/micromips@msa-relax.d, gas/mips/micromips@msa.d, + gas/mips/micromips@msa64.d, gas/mips/msa-relax.d, + gas/mips/msa-relax.l, gas/mips/msa-relax.s, + gas/mips/msa.d, gas/mips/msa.s, gas/mips/msa64.d, + gas/mips/msa64.s: New. + * gas/mips/mips.exp: Run new tests. + 2013-10-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/mpx.s: Remove bndcl/bndcu/bndcn tests with AX. @@ -91,6 +198,10 @@ * gas/i386/mpx.d: Updated. * gas/i386/x86-64-mpx.d: Likewise. +2013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com> + + * gas/mips/micromips@virt64.d: Fix dmfgc0 and dmtgc0. + 2013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com> * gas/s390/zarch-z196.s, gas/s390/zarch-z196.d: Test CLIH with diff --git a/binutils-2.24/gas/testsuite/gas/all/gas.exp b/binutils-2.24/gas/testsuite/gas/all/gas.exp index 35bcd95..5a19662 100644 --- a/binutils-2.24/gas/testsuite/gas/all/gas.exp +++ b/binutils-2.24/gas/testsuite/gas/all/gas.exp @@ -100,7 +100,7 @@ case $target_triplet in { default { # Some targets don't manage to resolve BFD_RELOC_8 for constants. setup_xfail "alpha*-*-*" "*c30*-*-*" "*c4x*-*-*" \ - "d\[13\]0v*-*-*" "i860-*-*" "mips*-*-*" \ + "d\[13\]0v*-*-*" "i860-*-*" \ "pdp11-*-*" "xtensa*-*-*" run_dump_test forward } diff --git a/binutils-2.24/gas/testsuite/gas/elf/section2.e-mips b/binutils-2.24/gas/testsuite/gas/elf/section2.e-mips index 9e70f5c..e7588cf 100644 --- a/binutils-2.24/gas/testsuite/gas/elf/section2.e-mips +++ b/binutils-2.24/gas/testsuite/gas/elf/section2.e-mips @@ -1,10 +1,12 @@ -Symbol table '.symtab' contains 7 entries: +Symbol table '.symtab' contains 9 entries: +Num: +Value +Size +Type +Bind +Vis +Ndx +Name +0: 0+0 +0 +NOTYPE +LOCAL +DEFAULT +UND +1: 0+0 +0 +SECTION +LOCAL +DEFAULT +1 (|\.text) +2: 0+0 +0 +SECTION +LOCAL +DEFAULT +2 (|\.data) +3: 0+0 +0 +SECTION +LOCAL +DEFAULT +3 (|\.bss) - +4: 0+0 +0 +SECTION +LOCAL +DEFAULT +6 (|A) + +4: 0+0 +0 +SECTION +LOCAL +DEFAULT +7 (|A) +5: 0+0 +0 +SECTION +LOCAL +DEFAULT +4 (|\.reginfo) - +6: 0+0 +0 +SECTION +LOCAL +DEFAULT +5 (|\.pdr) + +6: 0+0 +0 +SECTION +LOCAL +DEFAULT +5 (|\.MIPS\.abiflags) + +7: 0+0 +0 +SECTION +LOCAL +DEFAULT +6 (|\.pdr) + +8: 0+0 +0 +SECTION +LOCAL +DEFAULT +8 (|\.gnu\.attributes) diff --git a/binutils-2.24/gas/testsuite/gas/mips/24k-triple-stores-1.s b/binutils-2.24/gas/testsuite/gas/mips/24k-triple-stores-1.s index 87c67a9..20e9f85 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/24k-triple-stores-1.s +++ b/binutils-2.24/gas/testsuite/gas/mips/24k-triple-stores-1.s @@ -19,6 +19,7 @@ foo: sw $5,24($sp) sw $6,32($sp) +.ifndef r6 swr $2,0($sp) swr $3,8($sp) swr $4,16($sp) @@ -30,6 +31,7 @@ foo: swl $4,16($sp) swl $5,24($sp) swl $6,32($sp) +.endif sc $2,0($sp) sc $3,8($sp) @@ -63,6 +65,7 @@ foo: sdc2 $5,24($sp) sdc2 $6,32($sp) +.ifndef r6 swxc1 $f0,$9($8) swxc1 $f1,$10($8) swxc1 $f2,$11($8) @@ -80,6 +83,7 @@ foo: suxc1 $f4,$11($8) suxc1 $f6,$12($8) suxc1 $f8,$13($8) +.endif # Force at least 8 (non-delay-slot) zero bytes,to make 'objdump' print ... .align 2 diff --git a/binutils-2.24/gas/testsuite/gas/mips/24k-triple-stores-2.s b/binutils-2.24/gas/testsuite/gas/mips/24k-triple-stores-2.s index 13b9cd4..9ef6b00 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/24k-triple-stores-2.s +++ b/binutils-2.24/gas/testsuite/gas/mips/24k-triple-stores-2.s @@ -16,6 +16,7 @@ foo: sw $4,8($sp) break +.ifndef r6 swr $2,0($sp) swr $3,-16($sp) swr $4,16($sp) @@ -26,6 +27,7 @@ foo: swl $4,16($sp) swl $5,24($sp) swl $6,0($sp) +.endif # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... .align 2 diff --git a/binutils-2.24/gas/testsuite/gas/mips/24k-triple-stores-3.s b/binutils-2.24/gas/testsuite/gas/mips/24k-triple-stores-3.s index 1a54c64..4a13dba 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/24k-triple-stores-3.s +++ b/binutils-2.24/gas/testsuite/gas/mips/24k-triple-stores-3.s @@ -60,6 +60,7 @@ foo: sw $4,15($8) break +.ifndef r6 swl $2,4($sp) swl $3,10($sp) swl $4,17($sp) @@ -94,6 +95,7 @@ foo: swl $3,17($8) swr $4,28($8) break +.endif # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... .align 2 diff --git a/binutils-2.24/gas/testsuite/gas/mips/24k-triple-stores-6.s b/binutils-2.24/gas/testsuite/gas/mips/24k-triple-stores-6.s index eb087e1..7d5c97d 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/24k-triple-stores-6.s +++ b/binutils-2.24/gas/testsuite/gas/mips/24k-triple-stores-6.s @@ -1,6 +1,7 @@ # Store macros foo: +.ifndef r6 usw $ra,80($sp) usw $s3,88($sp) usw $s8,96($sp) @@ -10,6 +11,7 @@ foo: ush $s3,88($sp) ush $s8,96($sp) break +.endif # swc1 macro s.s $f0,80($sp) diff --git a/binutils-2.24/gas/testsuite/gas/mips/add.s b/binutils-2.24/gas/testsuite/gas/mips/add.s index 44e964b..57606c2 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/add.s +++ b/binutils-2.24/gas/testsuite/gas/mips/add.s @@ -1,13 +1,15 @@ # Source file used to test the add macro. foo: +.ifndef r6 add $4,$4,0 add $4,$4,1 add $4,$4,0x8000 add $4,$4,-0x8000 add $4,$4,0x10000 add $4,$4,0x1a5a5 - +.endif + # addu is handled the same way add is; just confirm that it isn't # totally broken. addu $4,$4,1 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-0.d b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-0.d new file mode 100644 index 0000000..0189334 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-0.d @@ -0,0 +1,17 @@ +#PROG: readelf +#readelf: -A +#name: MIPS gnu_attribute 4,0 + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard or soft float +ISA Extension: .* +ASEs: +#... +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-0.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-0.s new file mode 100644 index 0000000..a143746 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-0.s @@ -0,0 +1 @@ +.gnu_attribute 4,0 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-mfp32.l b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-mfp32.l new file mode 100644 index 0000000..96db3ce --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-mfp32.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Warning: `fp=32' used with a 64-bit ABI +.*: Warning: .gnu_attribute 4,1 is incompatible with `gp=64 fp=32' diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-mfp32.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-mfp32.s new file mode 100644 index 0000000..e985a56 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-mfp32.s @@ -0,0 +1 @@ +.gnu_attribute 4,1 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-mfp64.l b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-mfp64.l new file mode 100644 index 0000000..78b5fc4 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-mfp64.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,1 is incompatible with `gp=32 fp=64' diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-mfp64.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-mfp64.s new file mode 100644 index 0000000..e985a56 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-mfp64.s @@ -0,0 +1 @@ +.gnu_attribute 4,1 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-mfpxx.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-mfpxx.s new file mode 100644 index 0000000..e985a56 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-mfpxx.s @@ -0,0 +1 @@ +.gnu_attribute 4,1 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-msingle-float.l b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-msingle-float.l new file mode 100644 index 0000000..c37c520 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-msingle-float.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,1 is incompatible with `singlefloat' diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-msingle-float.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-msingle-float.s new file mode 100644 index 0000000..e985a56 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-msingle-float.s @@ -0,0 +1 @@ +.gnu_attribute 4,1 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-msoft-float.l b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-msoft-float.l new file mode 100644 index 0000000..819abfa --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-msoft-float.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,1 is incompatible with `softfloat' diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-msoft-float.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-msoft-float.s new file mode 100644 index 0000000..e985a56 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1-msoft-float.s @@ -0,0 +1 @@ +.gnu_attribute 4,1 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1.d b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1.d new file mode 100644 index 0000000..137d4aa --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-1.s +#PROG: readelf +#readelf: -A +#name: MIPS gnu_attribute 4,1 (double precision) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: .* +ASEs: +#... +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1.s new file mode 100644 index 0000000..e985a56 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-1.s @@ -0,0 +1 @@ +.gnu_attribute 4,1 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2-mdouble-float.l b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2-mdouble-float.l new file mode 100644 index 0000000..b138323 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2-mdouble-float.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,2 requires `singlefloat' diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2-mdouble-float.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2-mdouble-float.s new file mode 100644 index 0000000..54ebf4e --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2-mdouble-float.s @@ -0,0 +1 @@ +.gnu_attribute 4,2 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2-msoft-float.l b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2-msoft-float.l new file mode 100644 index 0000000..9d421bd --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2-msoft-float.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,2 is incompatible with `softfloat' diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2-msoft-float.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2-msoft-float.s new file mode 100644 index 0000000..54ebf4e --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2-msoft-float.s @@ -0,0 +1 @@ +.gnu_attribute 4,2 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2.d b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2.d new file mode 100644 index 0000000..17b0c2a --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2.d @@ -0,0 +1,23 @@ +#source: attr-gnu-4-2.s +#as: -msingle-float +#PROG: readelf +#readelf: -A +#name: MIPS gnu_attribute 4,2 (single precision) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: .* +ASEs: +#... +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2.s new file mode 100644 index 0000000..54ebf4e --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-2.s @@ -0,0 +1 @@ +.gnu_attribute 4,2 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-3-mhard-float.l b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-3-mhard-float.l new file mode 100644 index 0000000..21b1039 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-3-mhard-float.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,3 requires `softfloat' diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-3-mhard-float.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-3-mhard-float.s new file mode 100644 index 0000000..32e5f5d --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-3-mhard-float.s @@ -0,0 +1 @@ +.gnu_attribute 4,3 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-3.d b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-3.d new file mode 100644 index 0000000..49a10a4 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-3.d @@ -0,0 +1,23 @@ +#as: -msoft-float +#source: attr-gnu-4-3.s +#PROG: readelf +#readelf: -A +#name: MIPS gnu_attribute 4,3 (-msoft-float) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: .* +ASEs: +#... +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-3.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-3.s new file mode 100644 index 0000000..32e5f5d --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-3.s @@ -0,0 +1 @@ +.gnu_attribute 4,3 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-4.l b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-4.l new file mode 100644 index 0000000..c7d611d --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-4.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,4 is no longer supported diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-4.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-4.s new file mode 100644 index 0000000..3ff129a --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-4.s @@ -0,0 +1 @@ +.gnu_attribute 4,4 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-5-64.l b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-5-64.l new file mode 100644 index 0000000..26c187b --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-5-64.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,5 requires `-mabi=32' diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-5-64.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-5-64.s new file mode 100644 index 0000000..b21ec3b --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-5-64.s @@ -0,0 +1 @@ +.gnu_attribute 4,5 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-5.d b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-5.d new file mode 100644 index 0000000..cd12097 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-5.d @@ -0,0 +1,23 @@ +#as: -32 -mfpxx +#source: attr-gnu-4-5.s +#PROG: readelf +#readelf: -A +#name: MIPS gnu_attribute 4,5 (-mfpxx) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: .* +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-5.l b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-5.l new file mode 100644 index 0000000..018d692 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-5.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,5 requires `fp=xx' diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-5.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-5.s new file mode 100644 index 0000000..b21ec3b --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-5.s @@ -0,0 +1 @@ +.gnu_attribute 4,5 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-6-64.l b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-6-64.l new file mode 100644 index 0000000..fa1764e --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-6-64.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,6 requires `-mabi=32' diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-6-64.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-6-64.s new file mode 100644 index 0000000..96ace49 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-6-64.s @@ -0,0 +1 @@ +.gnu_attribute 4,6 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-6.d b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-6.d new file mode 100644 index 0000000..83c4e21 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-6.d @@ -0,0 +1,23 @@ +#as: -32 +#source: attr-gnu-4-6.s +#PROG: readelf +#readelf: -A +#name: MIPS gnu_attribute 4,6 (-mfp64) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: .* +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-6.l b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-6.l new file mode 100644 index 0000000..999b5e2 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-6.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,6 is incompatible with `fp=32' diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-6.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-6.s new file mode 100644 index 0000000..96ace49 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-4-6.s @@ -0,0 +1 @@ +.gnu_attribute 4,6 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-abi-fp-1.d b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-abi-fp-1.d new file mode 100644 index 0000000..ce5bbc2 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-abi-fp-1.d @@ -0,0 +1,22 @@ +#as: -32 +#source: attr-gnu-abi-fp-1.s +#readelf: -A +#name: MIPS gnu_attribute Tag_GNU_MIPS_ABI_FP,1 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS1 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-abi-fp-1.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-abi-fp-1.s new file mode 100644 index 0000000..a96caaf --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-abi-fp-1.s @@ -0,0 +1 @@ +.gnu_attribute Tag_GNU_MIPS_ABI_FP,1 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-abi-msa-1.d b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-abi-msa-1.d new file mode 100644 index 0000000..7508feb --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-abi-msa-1.d @@ -0,0 +1,22 @@ +#source: attr-gnu-abi-msa-1.s +#readelf: -A +#name: MIPS gnu_attribute Tag_GNU_MIPS_ABI_MSA,1 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Tag_GNU_MIPS_ABI_MSA: 128-bit MSA + +MIPS ABI Flags Version: 0 + +ISA: MIPS1 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-abi-msa-1.s b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-abi-msa-1.s new file mode 100644 index 0000000..f22883e --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-gnu-abi-msa-1.s @@ -0,0 +1 @@ +.gnu_attribute Tag_GNU_MIPS_ABI_MSA,1 diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-none-double.d b/binutils-2.24/gas/testsuite/gas/mips/attr-none-double.d new file mode 100644 index 0000000..8d9c69b --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-none-double.d @@ -0,0 +1,22 @@ +#PROG: readelf +#source: empty.s +#readelf: -A +#name: MIPS infer fpabi (double-precision) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: .* +ASEs: +#... +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-none-o32-fp64.d b/binutils-2.24/gas/testsuite/gas/mips/attr-none-o32-fp64.d new file mode 100644 index 0000000..f34c648 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-none-o32-fp64.d @@ -0,0 +1,23 @@ +#as: -mfp64 -32 +#source: empty.s +#PROG: readelf +#readelf: -A +#name: MIPS infer fpabi (O32 fp64) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: .* +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-none-o32-fpxx.d b/binutils-2.24/gas/testsuite/gas/mips/attr-none-o32-fpxx.d new file mode 100644 index 0000000..0d600fb --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-none-o32-fpxx.d @@ -0,0 +1,23 @@ +#as: -mfpxx -32 +#source: empty.s +#PROG: readelf +#readelf: -A +#name: MIPS infer fpabi (O32 fpxx) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: .* +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-none-single-float.d b/binutils-2.24/gas/testsuite/gas/mips/attr-none-single-float.d new file mode 100644 index 0000000..f1cd2ff --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-none-single-float.d @@ -0,0 +1,23 @@ +#as: -msingle-float +#PROG: readelf +#source: empty.s +#readelf: -A +#name: MIPS infer fpabi (single-precision) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: .* +ASEs: +#... +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/attr-none-soft-float.d b/binutils-2.24/gas/testsuite/gas/mips/attr-none-soft-float.d new file mode 100644 index 0000000..6db888d --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/attr-none-soft-float.d @@ -0,0 +1,23 @@ +#as: -msoft-float +#PROG: readelf +#source: empty.s +#readelf: -A +#name: MIPS infer fpabi (soft-precision) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: 0 +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: .* +ASEs: +#... +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/beq.s b/binutils-2.24/gas/testsuite/gas/mips/beq.s index d9e4c60..785f9ed 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/beq.s +++ b/binutils-2.24/gas/testsuite/gas/mips/beq.s @@ -12,10 +12,12 @@ text_label: # bne is handled by the same code as beq. Just sanity check. bne $4,0,text_label +.ifndef r6 # Test that branches which overflow are converted to jumps. .space 0x20000 b text_label bal text_label +.endif # Branch to an external label. # b external_label diff --git a/binutils-2.24/gas/testsuite/gas/mips/cache.s b/binutils-2.24/gas/testsuite/gas/mips/cache.s index 5f66c4d..6b8cc22 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/cache.s +++ b/binutils-2.24/gas/testsuite/gas/mips/cache.s @@ -15,6 +15,10 @@ .text text_label: + .ifdef r6 + cache 5, 255($2) + cache 5, -256($3) + .else cache 5, 2047($2) cache 5, -2048($3) @@ -35,6 +39,7 @@ text_label: cache 5, -32769($9) cache 5, 36864($10) cache 5, -36865($11) + .endif # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... .align 2 diff --git a/binutils-2.24/gas/testsuite/gas/mips/call-nonpic-1.d b/binutils-2.24/gas/testsuite/gas/mips/call-nonpic-1.d index 61d2b09..cd1b442 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/call-nonpic-1.d +++ b/binutils-2.24/gas/testsuite/gas/mips/call-nonpic-1.d @@ -4,6 +4,19 @@ .* private flags = 10001004: .* +MIPS ABI Flags Version: 0 + +ISA: MIPS2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + Disassembly of section \.text: diff --git a/binutils-2.24/gas/testsuite/gas/mips/cp1-names-mips32.d b/binutils-2.24/gas/testsuite/gas/mips/cp1-names-mips32.d new file mode 100644 index 0000000..93d3253 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/cp1-names-mips32.d @@ -0,0 +1,74 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=mips32 +#name: MIPS CP1 register disassembly (mips32) +#source: cp1-names.s + +# Check objdump's handling of -M cp1-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 44c00000 ctc1 \$0,c1_fir +0+0004 <[^>]*> 44c00800 ctc1 \$0,c1_ufr +0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2 +0+000c <[^>]*> 44c01800 ctc1 \$0,\$3 +0+0010 <[^>]*> 44c02000 ctc1 \$0,c1_unfr +0+0014 <[^>]*> 44c02800 ctc1 \$0,\$5 +0+0018 <[^>]*> 44c03000 ctc1 \$0,\$6 +0+001c <[^>]*> 44c03800 ctc1 \$0,\$7 +0+0020 <[^>]*> 44c04000 ctc1 \$0,\$8 +0+0024 <[^>]*> 44c04800 ctc1 \$0,\$9 +0+0028 <[^>]*> 44c05000 ctc1 \$0,\$10 +0+002c <[^>]*> 44c05800 ctc1 \$0,\$11 +0+0030 <[^>]*> 44c06000 ctc1 \$0,\$12 +0+0034 <[^>]*> 44c06800 ctc1 \$0,\$13 +0+0038 <[^>]*> 44c07000 ctc1 \$0,\$14 +0+003c <[^>]*> 44c07800 ctc1 \$0,\$15 +0+0040 <[^>]*> 44c08000 ctc1 \$0,\$16 +0+0044 <[^>]*> 44c08800 ctc1 \$0,\$17 +0+0048 <[^>]*> 44c09000 ctc1 \$0,\$18 +0+004c <[^>]*> 44c09800 ctc1 \$0,\$19 +0+0050 <[^>]*> 44c0a000 ctc1 \$0,\$20 +0+0054 <[^>]*> 44c0a800 ctc1 \$0,\$21 +0+0058 <[^>]*> 44c0b000 ctc1 \$0,\$22 +0+005c <[^>]*> 44c0b800 ctc1 \$0,\$23 +0+0060 <[^>]*> 44c0c000 ctc1 \$0,\$24 +0+0064 <[^>]*> 44c0c800 ctc1 \$0,c1_fccr +0+0068 <[^>]*> 44c0d000 ctc1 \$0,c1_fexr +0+006c <[^>]*> 44c0d800 ctc1 \$0,\$27 +0+0070 <[^>]*> 44c0e000 ctc1 \$0,c1_fenr +0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29 +0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30 +0+007c <[^>]*> 44c0f800 ctc1 \$0,c1_fcsr +0+0080 <[^>]*> 44400000 cfc1 \$0,c1_fir +0+0084 <[^>]*> 44400800 cfc1 \$0,c1_ufr +0+0088 <[^>]*> 44401000 cfc1 \$0,\$2 +0+008c <[^>]*> 44401800 cfc1 \$0,\$3 +0+0090 <[^>]*> 44402000 cfc1 \$0,c1_unfr +0+0094 <[^>]*> 44402800 cfc1 \$0,\$5 +0+0098 <[^>]*> 44403000 cfc1 \$0,\$6 +0+009c <[^>]*> 44403800 cfc1 \$0,\$7 +0+00a0 <[^>]*> 44404000 cfc1 \$0,\$8 +0+00a4 <[^>]*> 44404800 cfc1 \$0,\$9 +0+00a8 <[^>]*> 44405000 cfc1 \$0,\$10 +0+00ac <[^>]*> 44405800 cfc1 \$0,\$11 +0+00b0 <[^>]*> 44406000 cfc1 \$0,\$12 +0+00b4 <[^>]*> 44406800 cfc1 \$0,\$13 +0+00b8 <[^>]*> 44407000 cfc1 \$0,\$14 +0+00bc <[^>]*> 44407800 cfc1 \$0,\$15 +0+00c0 <[^>]*> 44408000 cfc1 \$0,\$16 +0+00c4 <[^>]*> 44408800 cfc1 \$0,\$17 +0+00c8 <[^>]*> 44409000 cfc1 \$0,\$18 +0+00cc <[^>]*> 44409800 cfc1 \$0,\$19 +0+00d0 <[^>]*> 4440a000 cfc1 \$0,\$20 +0+00d4 <[^>]*> 4440a800 cfc1 \$0,\$21 +0+00d8 <[^>]*> 4440b000 cfc1 \$0,\$22 +0+00dc <[^>]*> 4440b800 cfc1 \$0,\$23 +0+00e0 <[^>]*> 4440c000 cfc1 \$0,\$24 +0+00e4 <[^>]*> 4440c800 cfc1 \$0,c1_fccr +0+00e8 <[^>]*> 4440d000 cfc1 \$0,c1_fexr +0+00ec <[^>]*> 4440d800 cfc1 \$0,\$27 +0+00f0 <[^>]*> 4440e000 cfc1 \$0,c1_fenr +0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29 +0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30 +0+00fc <[^>]*> 4440f800 cfc1 \$0,c1_fcsr + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/cp1-names-mips32r2.d b/binutils-2.24/gas/testsuite/gas/mips/cp1-names-mips32r2.d new file mode 100644 index 0000000..03d6a19 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/cp1-names-mips32r2.d @@ -0,0 +1,74 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=mips32r2 +#name: MIPS CP1 register disassembly (mips32r2) +#source: cp1-names.s + +# Check objdump's handling of -M cp1-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 44c00000 ctc1 \$0,c1_fir +0+0004 <[^>]*> 44c00800 ctc1 \$0,c1_ufr +0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2 +0+000c <[^>]*> 44c01800 ctc1 \$0,\$3 +0+0010 <[^>]*> 44c02000 ctc1 \$0,c1_unfr +0+0014 <[^>]*> 44c02800 ctc1 \$0,\$5 +0+0018 <[^>]*> 44c03000 ctc1 \$0,\$6 +0+001c <[^>]*> 44c03800 ctc1 \$0,\$7 +0+0020 <[^>]*> 44c04000 ctc1 \$0,\$8 +0+0024 <[^>]*> 44c04800 ctc1 \$0,\$9 +0+0028 <[^>]*> 44c05000 ctc1 \$0,\$10 +0+002c <[^>]*> 44c05800 ctc1 \$0,\$11 +0+0030 <[^>]*> 44c06000 ctc1 \$0,\$12 +0+0034 <[^>]*> 44c06800 ctc1 \$0,\$13 +0+0038 <[^>]*> 44c07000 ctc1 \$0,\$14 +0+003c <[^>]*> 44c07800 ctc1 \$0,\$15 +0+0040 <[^>]*> 44c08000 ctc1 \$0,\$16 +0+0044 <[^>]*> 44c08800 ctc1 \$0,\$17 +0+0048 <[^>]*> 44c09000 ctc1 \$0,\$18 +0+004c <[^>]*> 44c09800 ctc1 \$0,\$19 +0+0050 <[^>]*> 44c0a000 ctc1 \$0,\$20 +0+0054 <[^>]*> 44c0a800 ctc1 \$0,\$21 +0+0058 <[^>]*> 44c0b000 ctc1 \$0,\$22 +0+005c <[^>]*> 44c0b800 ctc1 \$0,\$23 +0+0060 <[^>]*> 44c0c000 ctc1 \$0,\$24 +0+0064 <[^>]*> 44c0c800 ctc1 \$0,c1_fccr +0+0068 <[^>]*> 44c0d000 ctc1 \$0,c1_fexr +0+006c <[^>]*> 44c0d800 ctc1 \$0,\$27 +0+0070 <[^>]*> 44c0e000 ctc1 \$0,c1_fenr +0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29 +0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30 +0+007c <[^>]*> 44c0f800 ctc1 \$0,c1_fcsr +0+0080 <[^>]*> 44400000 cfc1 \$0,c1_fir +0+0084 <[^>]*> 44400800 cfc1 \$0,c1_ufr +0+0088 <[^>]*> 44401000 cfc1 \$0,\$2 +0+008c <[^>]*> 44401800 cfc1 \$0,\$3 +0+0090 <[^>]*> 44402000 cfc1 \$0,c1_unfr +0+0094 <[^>]*> 44402800 cfc1 \$0,\$5 +0+0098 <[^>]*> 44403000 cfc1 \$0,\$6 +0+009c <[^>]*> 44403800 cfc1 \$0,\$7 +0+00a0 <[^>]*> 44404000 cfc1 \$0,\$8 +0+00a4 <[^>]*> 44404800 cfc1 \$0,\$9 +0+00a8 <[^>]*> 44405000 cfc1 \$0,\$10 +0+00ac <[^>]*> 44405800 cfc1 \$0,\$11 +0+00b0 <[^>]*> 44406000 cfc1 \$0,\$12 +0+00b4 <[^>]*> 44406800 cfc1 \$0,\$13 +0+00b8 <[^>]*> 44407000 cfc1 \$0,\$14 +0+00bc <[^>]*> 44407800 cfc1 \$0,\$15 +0+00c0 <[^>]*> 44408000 cfc1 \$0,\$16 +0+00c4 <[^>]*> 44408800 cfc1 \$0,\$17 +0+00c8 <[^>]*> 44409000 cfc1 \$0,\$18 +0+00cc <[^>]*> 44409800 cfc1 \$0,\$19 +0+00d0 <[^>]*> 4440a000 cfc1 \$0,\$20 +0+00d4 <[^>]*> 4440a800 cfc1 \$0,\$21 +0+00d8 <[^>]*> 4440b000 cfc1 \$0,\$22 +0+00dc <[^>]*> 4440b800 cfc1 \$0,\$23 +0+00e0 <[^>]*> 4440c000 cfc1 \$0,\$24 +0+00e4 <[^>]*> 4440c800 cfc1 \$0,c1_fccr +0+00e8 <[^>]*> 4440d000 cfc1 \$0,c1_fexr +0+00ec <[^>]*> 4440d800 cfc1 \$0,\$27 +0+00f0 <[^>]*> 4440e000 cfc1 \$0,c1_fenr +0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29 +0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30 +0+00fc <[^>]*> 4440f800 cfc1 \$0,c1_fcsr + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/cp1-names-mips64.d b/binutils-2.24/gas/testsuite/gas/mips/cp1-names-mips64.d new file mode 100644 index 0000000..a7afaf1 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/cp1-names-mips64.d @@ -0,0 +1,74 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=mips64 +#name: MIPS CP1 register disassembly (mips64) +#source: cp1-names.s + +# Check objdump's handling of -M cp1-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 44c00000 ctc1 \$0,c1_fir +0+0004 <[^>]*> 44c00800 ctc1 \$0,c1_ufr +0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2 +0+000c <[^>]*> 44c01800 ctc1 \$0,\$3 +0+0010 <[^>]*> 44c02000 ctc1 \$0,c1_unfr +0+0014 <[^>]*> 44c02800 ctc1 \$0,\$5 +0+0018 <[^>]*> 44c03000 ctc1 \$0,\$6 +0+001c <[^>]*> 44c03800 ctc1 \$0,\$7 +0+0020 <[^>]*> 44c04000 ctc1 \$0,\$8 +0+0024 <[^>]*> 44c04800 ctc1 \$0,\$9 +0+0028 <[^>]*> 44c05000 ctc1 \$0,\$10 +0+002c <[^>]*> 44c05800 ctc1 \$0,\$11 +0+0030 <[^>]*> 44c06000 ctc1 \$0,\$12 +0+0034 <[^>]*> 44c06800 ctc1 \$0,\$13 +0+0038 <[^>]*> 44c07000 ctc1 \$0,\$14 +0+003c <[^>]*> 44c07800 ctc1 \$0,\$15 +0+0040 <[^>]*> 44c08000 ctc1 \$0,\$16 +0+0044 <[^>]*> 44c08800 ctc1 \$0,\$17 +0+0048 <[^>]*> 44c09000 ctc1 \$0,\$18 +0+004c <[^>]*> 44c09800 ctc1 \$0,\$19 +0+0050 <[^>]*> 44c0a000 ctc1 \$0,\$20 +0+0054 <[^>]*> 44c0a800 ctc1 \$0,\$21 +0+0058 <[^>]*> 44c0b000 ctc1 \$0,\$22 +0+005c <[^>]*> 44c0b800 ctc1 \$0,\$23 +0+0060 <[^>]*> 44c0c000 ctc1 \$0,\$24 +0+0064 <[^>]*> 44c0c800 ctc1 \$0,c1_fccr +0+0068 <[^>]*> 44c0d000 ctc1 \$0,c1_fexr +0+006c <[^>]*> 44c0d800 ctc1 \$0,\$27 +0+0070 <[^>]*> 44c0e000 ctc1 \$0,c1_fenr +0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29 +0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30 +0+007c <[^>]*> 44c0f800 ctc1 \$0,c1_fcsr +0+0080 <[^>]*> 44400000 cfc1 \$0,c1_fir +0+0084 <[^>]*> 44400800 cfc1 \$0,c1_ufr +0+0088 <[^>]*> 44401000 cfc1 \$0,\$2 +0+008c <[^>]*> 44401800 cfc1 \$0,\$3 +0+0090 <[^>]*> 44402000 cfc1 \$0,c1_unfr +0+0094 <[^>]*> 44402800 cfc1 \$0,\$5 +0+0098 <[^>]*> 44403000 cfc1 \$0,\$6 +0+009c <[^>]*> 44403800 cfc1 \$0,\$7 +0+00a0 <[^>]*> 44404000 cfc1 \$0,\$8 +0+00a4 <[^>]*> 44404800 cfc1 \$0,\$9 +0+00a8 <[^>]*> 44405000 cfc1 \$0,\$10 +0+00ac <[^>]*> 44405800 cfc1 \$0,\$11 +0+00b0 <[^>]*> 44406000 cfc1 \$0,\$12 +0+00b4 <[^>]*> 44406800 cfc1 \$0,\$13 +0+00b8 <[^>]*> 44407000 cfc1 \$0,\$14 +0+00bc <[^>]*> 44407800 cfc1 \$0,\$15 +0+00c0 <[^>]*> 44408000 cfc1 \$0,\$16 +0+00c4 <[^>]*> 44408800 cfc1 \$0,\$17 +0+00c8 <[^>]*> 44409000 cfc1 \$0,\$18 +0+00cc <[^>]*> 44409800 cfc1 \$0,\$19 +0+00d0 <[^>]*> 4440a000 cfc1 \$0,\$20 +0+00d4 <[^>]*> 4440a800 cfc1 \$0,\$21 +0+00d8 <[^>]*> 4440b000 cfc1 \$0,\$22 +0+00dc <[^>]*> 4440b800 cfc1 \$0,\$23 +0+00e0 <[^>]*> 4440c000 cfc1 \$0,\$24 +0+00e4 <[^>]*> 4440c800 cfc1 \$0,c1_fccr +0+00e8 <[^>]*> 4440d000 cfc1 \$0,c1_fexr +0+00ec <[^>]*> 4440d800 cfc1 \$0,\$27 +0+00f0 <[^>]*> 4440e000 cfc1 \$0,c1_fenr +0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29 +0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30 +0+00fc <[^>]*> 4440f800 cfc1 \$0,c1_fcsr + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/cp1-names-mips64r2.d b/binutils-2.24/gas/testsuite/gas/mips/cp1-names-mips64r2.d new file mode 100644 index 0000000..45bc9d1 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/cp1-names-mips64r2.d @@ -0,0 +1,74 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=mips64r2 +#name: MIPS CP1 register disassembly (mips64r2) +#source: cp1-names.s + +# Check objdump's handling of -M cp1-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 44c00000 ctc1 \$0,c1_fir +0+0004 <[^>]*> 44c00800 ctc1 \$0,c1_ufr +0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2 +0+000c <[^>]*> 44c01800 ctc1 \$0,\$3 +0+0010 <[^>]*> 44c02000 ctc1 \$0,c1_unfr +0+0014 <[^>]*> 44c02800 ctc1 \$0,\$5 +0+0018 <[^>]*> 44c03000 ctc1 \$0,\$6 +0+001c <[^>]*> 44c03800 ctc1 \$0,\$7 +0+0020 <[^>]*> 44c04000 ctc1 \$0,\$8 +0+0024 <[^>]*> 44c04800 ctc1 \$0,\$9 +0+0028 <[^>]*> 44c05000 ctc1 \$0,\$10 +0+002c <[^>]*> 44c05800 ctc1 \$0,\$11 +0+0030 <[^>]*> 44c06000 ctc1 \$0,\$12 +0+0034 <[^>]*> 44c06800 ctc1 \$0,\$13 +0+0038 <[^>]*> 44c07000 ctc1 \$0,\$14 +0+003c <[^>]*> 44c07800 ctc1 \$0,\$15 +0+0040 <[^>]*> 44c08000 ctc1 \$0,\$16 +0+0044 <[^>]*> 44c08800 ctc1 \$0,\$17 +0+0048 <[^>]*> 44c09000 ctc1 \$0,\$18 +0+004c <[^>]*> 44c09800 ctc1 \$0,\$19 +0+0050 <[^>]*> 44c0a000 ctc1 \$0,\$20 +0+0054 <[^>]*> 44c0a800 ctc1 \$0,\$21 +0+0058 <[^>]*> 44c0b000 ctc1 \$0,\$22 +0+005c <[^>]*> 44c0b800 ctc1 \$0,\$23 +0+0060 <[^>]*> 44c0c000 ctc1 \$0,\$24 +0+0064 <[^>]*> 44c0c800 ctc1 \$0,c1_fccr +0+0068 <[^>]*> 44c0d000 ctc1 \$0,c1_fexr +0+006c <[^>]*> 44c0d800 ctc1 \$0,\$27 +0+0070 <[^>]*> 44c0e000 ctc1 \$0,c1_fenr +0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29 +0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30 +0+007c <[^>]*> 44c0f800 ctc1 \$0,c1_fcsr +0+0080 <[^>]*> 44400000 cfc1 \$0,c1_fir +0+0084 <[^>]*> 44400800 cfc1 \$0,c1_ufr +0+0088 <[^>]*> 44401000 cfc1 \$0,\$2 +0+008c <[^>]*> 44401800 cfc1 \$0,\$3 +0+0090 <[^>]*> 44402000 cfc1 \$0,c1_unfr +0+0094 <[^>]*> 44402800 cfc1 \$0,\$5 +0+0098 <[^>]*> 44403000 cfc1 \$0,\$6 +0+009c <[^>]*> 44403800 cfc1 \$0,\$7 +0+00a0 <[^>]*> 44404000 cfc1 \$0,\$8 +0+00a4 <[^>]*> 44404800 cfc1 \$0,\$9 +0+00a8 <[^>]*> 44405000 cfc1 \$0,\$10 +0+00ac <[^>]*> 44405800 cfc1 \$0,\$11 +0+00b0 <[^>]*> 44406000 cfc1 \$0,\$12 +0+00b4 <[^>]*> 44406800 cfc1 \$0,\$13 +0+00b8 <[^>]*> 44407000 cfc1 \$0,\$14 +0+00bc <[^>]*> 44407800 cfc1 \$0,\$15 +0+00c0 <[^>]*> 44408000 cfc1 \$0,\$16 +0+00c4 <[^>]*> 44408800 cfc1 \$0,\$17 +0+00c8 <[^>]*> 44409000 cfc1 \$0,\$18 +0+00cc <[^>]*> 44409800 cfc1 \$0,\$19 +0+00d0 <[^>]*> 4440a000 cfc1 \$0,\$20 +0+00d4 <[^>]*> 4440a800 cfc1 \$0,\$21 +0+00d8 <[^>]*> 4440b000 cfc1 \$0,\$22 +0+00dc <[^>]*> 4440b800 cfc1 \$0,\$23 +0+00e0 <[^>]*> 4440c000 cfc1 \$0,\$24 +0+00e4 <[^>]*> 4440c800 cfc1 \$0,c1_fccr +0+00e8 <[^>]*> 4440d000 cfc1 \$0,c1_fexr +0+00ec <[^>]*> 4440d800 cfc1 \$0,\$27 +0+00f0 <[^>]*> 4440e000 cfc1 \$0,c1_fenr +0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29 +0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30 +0+00fc <[^>]*> 4440f800 cfc1 \$0,c1_fcsr + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/cp1-names-numeric.d b/binutils-2.24/gas/testsuite/gas/mips/cp1-names-numeric.d new file mode 100644 index 0000000..e0ab337 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/cp1-names-numeric.d @@ -0,0 +1,74 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=numeric +#name: MIPS CP1 register disassembly (numeric) +#source: cp1-names.s + +# Check objdump's handling of -M cp1-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 44c00000 ctc1 \$0,\$0 +0+0004 <[^>]*> 44c00800 ctc1 \$0,\$1 +0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2 +0+000c <[^>]*> 44c01800 ctc1 \$0,\$3 +0+0010 <[^>]*> 44c02000 ctc1 \$0,\$4 +0+0014 <[^>]*> 44c02800 ctc1 \$0,\$5 +0+0018 <[^>]*> 44c03000 ctc1 \$0,\$6 +0+001c <[^>]*> 44c03800 ctc1 \$0,\$7 +0+0020 <[^>]*> 44c04000 ctc1 \$0,\$8 +0+0024 <[^>]*> 44c04800 ctc1 \$0,\$9 +0+0028 <[^>]*> 44c05000 ctc1 \$0,\$10 +0+002c <[^>]*> 44c05800 ctc1 \$0,\$11 +0+0030 <[^>]*> 44c06000 ctc1 \$0,\$12 +0+0034 <[^>]*> 44c06800 ctc1 \$0,\$13 +0+0038 <[^>]*> 44c07000 ctc1 \$0,\$14 +0+003c <[^>]*> 44c07800 ctc1 \$0,\$15 +0+0040 <[^>]*> 44c08000 ctc1 \$0,\$16 +0+0044 <[^>]*> 44c08800 ctc1 \$0,\$17 +0+0048 <[^>]*> 44c09000 ctc1 \$0,\$18 +0+004c <[^>]*> 44c09800 ctc1 \$0,\$19 +0+0050 <[^>]*> 44c0a000 ctc1 \$0,\$20 +0+0054 <[^>]*> 44c0a800 ctc1 \$0,\$21 +0+0058 <[^>]*> 44c0b000 ctc1 \$0,\$22 +0+005c <[^>]*> 44c0b800 ctc1 \$0,\$23 +0+0060 <[^>]*> 44c0c000 ctc1 \$0,\$24 +0+0064 <[^>]*> 44c0c800 ctc1 \$0,\$25 +0+0068 <[^>]*> 44c0d000 ctc1 \$0,\$26 +0+006c <[^>]*> 44c0d800 ctc1 \$0,\$27 +0+0070 <[^>]*> 44c0e000 ctc1 \$0,\$28 +0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29 +0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30 +0+007c <[^>]*> 44c0f800 ctc1 \$0,\$31 +0+0080 <[^>]*> 44400000 cfc1 \$0,\$0 +0+0084 <[^>]*> 44400800 cfc1 \$0,\$1 +0+0088 <[^>]*> 44401000 cfc1 \$0,\$2 +0+008c <[^>]*> 44401800 cfc1 \$0,\$3 +0+0090 <[^>]*> 44402000 cfc1 \$0,\$4 +0+0094 <[^>]*> 44402800 cfc1 \$0,\$5 +0+0098 <[^>]*> 44403000 cfc1 \$0,\$6 +0+009c <[^>]*> 44403800 cfc1 \$0,\$7 +0+00a0 <[^>]*> 44404000 cfc1 \$0,\$8 +0+00a4 <[^>]*> 44404800 cfc1 \$0,\$9 +0+00a8 <[^>]*> 44405000 cfc1 \$0,\$10 +0+00ac <[^>]*> 44405800 cfc1 \$0,\$11 +0+00b0 <[^>]*> 44406000 cfc1 \$0,\$12 +0+00b4 <[^>]*> 44406800 cfc1 \$0,\$13 +0+00b8 <[^>]*> 44407000 cfc1 \$0,\$14 +0+00bc <[^>]*> 44407800 cfc1 \$0,\$15 +0+00c0 <[^>]*> 44408000 cfc1 \$0,\$16 +0+00c4 <[^>]*> 44408800 cfc1 \$0,\$17 +0+00c8 <[^>]*> 44409000 cfc1 \$0,\$18 +0+00cc <[^>]*> 44409800 cfc1 \$0,\$19 +0+00d0 <[^>]*> 4440a000 cfc1 \$0,\$20 +0+00d4 <[^>]*> 4440a800 cfc1 \$0,\$21 +0+00d8 <[^>]*> 4440b000 cfc1 \$0,\$22 +0+00dc <[^>]*> 4440b800 cfc1 \$0,\$23 +0+00e0 <[^>]*> 4440c000 cfc1 \$0,\$24 +0+00e4 <[^>]*> 4440c800 cfc1 \$0,\$25 +0+00e8 <[^>]*> 4440d000 cfc1 \$0,\$26 +0+00ec <[^>]*> 4440d800 cfc1 \$0,\$27 +0+00f0 <[^>]*> 4440e000 cfc1 \$0,\$28 +0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29 +0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30 +0+00fc <[^>]*> 4440f800 cfc1 \$0,\$31 + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/cp1-names-r3000.d b/binutils-2.24/gas/testsuite/gas/mips/cp1-names-r3000.d new file mode 100644 index 0000000..25b5bfb --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/cp1-names-r3000.d @@ -0,0 +1,75 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=r3000 +#name: MIPS CP1 register disassembly (r3000) +#as: -32 -march=r3000 +#source: cp1-names.s + +# Check objdump's handling of -M cp1-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section \.text: +0+0000 <[^>]*> 44c00000 ctc1 \$0,\$0 +0+0004 <[^>]*> 44c00800 ctc1 \$0,\$1 +0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2 +0+000c <[^>]*> 44c01800 ctc1 \$0,\$3 +0+0010 <[^>]*> 44c02000 ctc1 \$0,\$4 +0+0014 <[^>]*> 44c02800 ctc1 \$0,\$5 +0+0018 <[^>]*> 44c03000 ctc1 \$0,\$6 +0+001c <[^>]*> 44c03800 ctc1 \$0,\$7 +0+0020 <[^>]*> 44c04000 ctc1 \$0,\$8 +0+0024 <[^>]*> 44c04800 ctc1 \$0,\$9 +0+0028 <[^>]*> 44c05000 ctc1 \$0,\$10 +0+002c <[^>]*> 44c05800 ctc1 \$0,\$11 +0+0030 <[^>]*> 44c06000 ctc1 \$0,\$12 +0+0034 <[^>]*> 44c06800 ctc1 \$0,\$13 +0+0038 <[^>]*> 44c07000 ctc1 \$0,\$14 +0+003c <[^>]*> 44c07800 ctc1 \$0,\$15 +0+0040 <[^>]*> 44c08000 ctc1 \$0,\$16 +0+0044 <[^>]*> 44c08800 ctc1 \$0,\$17 +0+0048 <[^>]*> 44c09000 ctc1 \$0,\$18 +0+004c <[^>]*> 44c09800 ctc1 \$0,\$19 +0+0050 <[^>]*> 44c0a000 ctc1 \$0,\$20 +0+0054 <[^>]*> 44c0a800 ctc1 \$0,\$21 +0+0058 <[^>]*> 44c0b000 ctc1 \$0,\$22 +0+005c <[^>]*> 44c0b800 ctc1 \$0,\$23 +0+0060 <[^>]*> 44c0c000 ctc1 \$0,\$24 +0+0064 <[^>]*> 44c0c800 ctc1 \$0,\$25 +0+0068 <[^>]*> 44c0d000 ctc1 \$0,\$26 +0+006c <[^>]*> 44c0d800 ctc1 \$0,\$27 +0+0070 <[^>]*> 44c0e000 ctc1 \$0,\$28 +0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29 +0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30 +0+007c <[^>]*> 44c0f800 ctc1 \$0,\$31 +0+0080 <[^>]*> 44400000 cfc1 \$0,\$0 +0+0084 <[^>]*> 44400800 cfc1 \$0,\$1 +0+0088 <[^>]*> 44401000 cfc1 \$0,\$2 +0+008c <[^>]*> 44401800 cfc1 \$0,\$3 +0+0090 <[^>]*> 44402000 cfc1 \$0,\$4 +0+0094 <[^>]*> 44402800 cfc1 \$0,\$5 +0+0098 <[^>]*> 44403000 cfc1 \$0,\$6 +0+009c <[^>]*> 44403800 cfc1 \$0,\$7 +0+00a0 <[^>]*> 44404000 cfc1 \$0,\$8 +0+00a4 <[^>]*> 44404800 cfc1 \$0,\$9 +0+00a8 <[^>]*> 44405000 cfc1 \$0,\$10 +0+00ac <[^>]*> 44405800 cfc1 \$0,\$11 +0+00b0 <[^>]*> 44406000 cfc1 \$0,\$12 +0+00b4 <[^>]*> 44406800 cfc1 \$0,\$13 +0+00b8 <[^>]*> 44407000 cfc1 \$0,\$14 +0+00bc <[^>]*> 44407800 cfc1 \$0,\$15 +0+00c0 <[^>]*> 44408000 cfc1 \$0,\$16 +0+00c4 <[^>]*> 44408800 cfc1 \$0,\$17 +0+00c8 <[^>]*> 44409000 cfc1 \$0,\$18 +0+00cc <[^>]*> 44409800 cfc1 \$0,\$19 +0+00d0 <[^>]*> 4440a000 cfc1 \$0,\$20 +0+00d4 <[^>]*> 4440a800 cfc1 \$0,\$21 +0+00d8 <[^>]*> 4440b000 cfc1 \$0,\$22 +0+00dc <[^>]*> 4440b800 cfc1 \$0,\$23 +0+00e0 <[^>]*> 4440c000 cfc1 \$0,\$24 +0+00e4 <[^>]*> 4440c800 cfc1 \$0,\$25 +0+00e8 <[^>]*> 4440d000 cfc1 \$0,\$26 +0+00ec <[^>]*> 4440d800 cfc1 \$0,\$27 +0+00f0 <[^>]*> 4440e000 cfc1 \$0,\$28 +0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29 +0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30 +0+00fc <[^>]*> 4440f800 cfc1 \$0,\$31 + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/cp1-names-r4000.d b/binutils-2.24/gas/testsuite/gas/mips/cp1-names-r4000.d new file mode 100644 index 0000000..a1030a2 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/cp1-names-r4000.d @@ -0,0 +1,75 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric +#name: MIPS CP1 register disassembly +#as: -32 -march=r4000 +#source: cp1-names.s + +# Check objdump's handling of -M cp1-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section \.text: +0+0000 <[^>]*> 44c00000 ctc1 \$0,\$0 +0+0004 <[^>]*> 44c00800 ctc1 \$0,\$1 +0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2 +0+000c <[^>]*> 44c01800 ctc1 \$0,\$3 +0+0010 <[^>]*> 44c02000 ctc1 \$0,\$4 +0+0014 <[^>]*> 44c02800 ctc1 \$0,\$5 +0+0018 <[^>]*> 44c03000 ctc1 \$0,\$6 +0+001c <[^>]*> 44c03800 ctc1 \$0,\$7 +0+0020 <[^>]*> 44c04000 ctc1 \$0,\$8 +0+0024 <[^>]*> 44c04800 ctc1 \$0,\$9 +0+0028 <[^>]*> 44c05000 ctc1 \$0,\$10 +0+002c <[^>]*> 44c05800 ctc1 \$0,\$11 +0+0030 <[^>]*> 44c06000 ctc1 \$0,\$12 +0+0034 <[^>]*> 44c06800 ctc1 \$0,\$13 +0+0038 <[^>]*> 44c07000 ctc1 \$0,\$14 +0+003c <[^>]*> 44c07800 ctc1 \$0,\$15 +0+0040 <[^>]*> 44c08000 ctc1 \$0,\$16 +0+0044 <[^>]*> 44c08800 ctc1 \$0,\$17 +0+0048 <[^>]*> 44c09000 ctc1 \$0,\$18 +0+004c <[^>]*> 44c09800 ctc1 \$0,\$19 +0+0050 <[^>]*> 44c0a000 ctc1 \$0,\$20 +0+0054 <[^>]*> 44c0a800 ctc1 \$0,\$21 +0+0058 <[^>]*> 44c0b000 ctc1 \$0,\$22 +0+005c <[^>]*> 44c0b800 ctc1 \$0,\$23 +0+0060 <[^>]*> 44c0c000 ctc1 \$0,\$24 +0+0064 <[^>]*> 44c0c800 ctc1 \$0,\$25 +0+0068 <[^>]*> 44c0d000 ctc1 \$0,\$26 +0+006c <[^>]*> 44c0d800 ctc1 \$0,\$27 +0+0070 <[^>]*> 44c0e000 ctc1 \$0,\$28 +0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29 +0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30 +0+007c <[^>]*> 44c0f800 ctc1 \$0,\$31 +0+0080 <[^>]*> 44400000 cfc1 \$0,\$0 +0+0084 <[^>]*> 44400800 cfc1 \$0,\$1 +0+0088 <[^>]*> 44401000 cfc1 \$0,\$2 +0+008c <[^>]*> 44401800 cfc1 \$0,\$3 +0+0090 <[^>]*> 44402000 cfc1 \$0,\$4 +0+0094 <[^>]*> 44402800 cfc1 \$0,\$5 +0+0098 <[^>]*> 44403000 cfc1 \$0,\$6 +0+009c <[^>]*> 44403800 cfc1 \$0,\$7 +0+00a0 <[^>]*> 44404000 cfc1 \$0,\$8 +0+00a4 <[^>]*> 44404800 cfc1 \$0,\$9 +0+00a8 <[^>]*> 44405000 cfc1 \$0,\$10 +0+00ac <[^>]*> 44405800 cfc1 \$0,\$11 +0+00b0 <[^>]*> 44406000 cfc1 \$0,\$12 +0+00b4 <[^>]*> 44406800 cfc1 \$0,\$13 +0+00b8 <[^>]*> 44407000 cfc1 \$0,\$14 +0+00bc <[^>]*> 44407800 cfc1 \$0,\$15 +0+00c0 <[^>]*> 44408000 cfc1 \$0,\$16 +0+00c4 <[^>]*> 44408800 cfc1 \$0,\$17 +0+00c8 <[^>]*> 44409000 cfc1 \$0,\$18 +0+00cc <[^>]*> 44409800 cfc1 \$0,\$19 +0+00d0 <[^>]*> 4440a000 cfc1 \$0,\$20 +0+00d4 <[^>]*> 4440a800 cfc1 \$0,\$21 +0+00d8 <[^>]*> 4440b000 cfc1 \$0,\$22 +0+00dc <[^>]*> 4440b800 cfc1 \$0,\$23 +0+00e0 <[^>]*> 4440c000 cfc1 \$0,\$24 +0+00e4 <[^>]*> 4440c800 cfc1 \$0,\$25 +0+00e8 <[^>]*> 4440d000 cfc1 \$0,\$26 +0+00ec <[^>]*> 4440d800 cfc1 \$0,\$27 +0+00f0 <[^>]*> 4440e000 cfc1 \$0,\$28 +0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29 +0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30 +0+00fc <[^>]*> 4440f800 cfc1 \$0,\$31 + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/cp1-names-sb1.d b/binutils-2.24/gas/testsuite/gas/mips/cp1-names-sb1.d new file mode 100644 index 0000000..dc4407d --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/cp1-names-sb1.d @@ -0,0 +1,74 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp1-names=sb1 +#name: MIPS CP1 register disassembly (sb1) +#source: cp1-names.s + +# Check objdump's handling of -M cp1-names=foo options. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 44c00000 ctc1 \$0,c1_fir +0+0004 <[^>]*> 44c00800 ctc1 \$0,c1_ufr +0+0008 <[^>]*> 44c01000 ctc1 \$0,\$2 +0+000c <[^>]*> 44c01800 ctc1 \$0,\$3 +0+0010 <[^>]*> 44c02000 ctc1 \$0,c1_unfr +0+0014 <[^>]*> 44c02800 ctc1 \$0,\$5 +0+0018 <[^>]*> 44c03000 ctc1 \$0,\$6 +0+001c <[^>]*> 44c03800 ctc1 \$0,\$7 +0+0020 <[^>]*> 44c04000 ctc1 \$0,\$8 +0+0024 <[^>]*> 44c04800 ctc1 \$0,\$9 +0+0028 <[^>]*> 44c05000 ctc1 \$0,\$10 +0+002c <[^>]*> 44c05800 ctc1 \$0,\$11 +0+0030 <[^>]*> 44c06000 ctc1 \$0,\$12 +0+0034 <[^>]*> 44c06800 ctc1 \$0,\$13 +0+0038 <[^>]*> 44c07000 ctc1 \$0,\$14 +0+003c <[^>]*> 44c07800 ctc1 \$0,\$15 +0+0040 <[^>]*> 44c08000 ctc1 \$0,\$16 +0+0044 <[^>]*> 44c08800 ctc1 \$0,\$17 +0+0048 <[^>]*> 44c09000 ctc1 \$0,\$18 +0+004c <[^>]*> 44c09800 ctc1 \$0,\$19 +0+0050 <[^>]*> 44c0a000 ctc1 \$0,\$20 +0+0054 <[^>]*> 44c0a800 ctc1 \$0,\$21 +0+0058 <[^>]*> 44c0b000 ctc1 \$0,\$22 +0+005c <[^>]*> 44c0b800 ctc1 \$0,\$23 +0+0060 <[^>]*> 44c0c000 ctc1 \$0,\$24 +0+0064 <[^>]*> 44c0c800 ctc1 \$0,c1_fccr +0+0068 <[^>]*> 44c0d000 ctc1 \$0,c1_fexr +0+006c <[^>]*> 44c0d800 ctc1 \$0,\$27 +0+0070 <[^>]*> 44c0e000 ctc1 \$0,c1_fenr +0+0074 <[^>]*> 44c0e800 ctc1 \$0,\$29 +0+0078 <[^>]*> 44c0f000 ctc1 \$0,\$30 +0+007c <[^>]*> 44c0f800 ctc1 \$0,c1_fcsr +0+0080 <[^>]*> 44400000 cfc1 \$0,c1_fir +0+0084 <[^>]*> 44400800 cfc1 \$0,c1_ufr +0+0088 <[^>]*> 44401000 cfc1 \$0,\$2 +0+008c <[^>]*> 44401800 cfc1 \$0,\$3 +0+0090 <[^>]*> 44402000 cfc1 \$0,c1_unfr +0+0094 <[^>]*> 44402800 cfc1 \$0,\$5 +0+0098 <[^>]*> 44403000 cfc1 \$0,\$6 +0+009c <[^>]*> 44403800 cfc1 \$0,\$7 +0+00a0 <[^>]*> 44404000 cfc1 \$0,\$8 +0+00a4 <[^>]*> 44404800 cfc1 \$0,\$9 +0+00a8 <[^>]*> 44405000 cfc1 \$0,\$10 +0+00ac <[^>]*> 44405800 cfc1 \$0,\$11 +0+00b0 <[^>]*> 44406000 cfc1 \$0,\$12 +0+00b4 <[^>]*> 44406800 cfc1 \$0,\$13 +0+00b8 <[^>]*> 44407000 cfc1 \$0,\$14 +0+00bc <[^>]*> 44407800 cfc1 \$0,\$15 +0+00c0 <[^>]*> 44408000 cfc1 \$0,\$16 +0+00c4 <[^>]*> 44408800 cfc1 \$0,\$17 +0+00c8 <[^>]*> 44409000 cfc1 \$0,\$18 +0+00cc <[^>]*> 44409800 cfc1 \$0,\$19 +0+00d0 <[^>]*> 4440a000 cfc1 \$0,\$20 +0+00d4 <[^>]*> 4440a800 cfc1 \$0,\$21 +0+00d8 <[^>]*> 4440b000 cfc1 \$0,\$22 +0+00dc <[^>]*> 4440b800 cfc1 \$0,\$23 +0+00e0 <[^>]*> 4440c000 cfc1 \$0,\$24 +0+00e4 <[^>]*> 4440c800 cfc1 \$0,c1_fccr +0+00e8 <[^>]*> 4440d000 cfc1 \$0,c1_fexr +0+00ec <[^>]*> 4440d800 cfc1 \$0,\$27 +0+00f0 <[^>]*> 4440e000 cfc1 \$0,c1_fenr +0+00f4 <[^>]*> 4440e800 cfc1 \$0,\$29 +0+00f8 <[^>]*> 4440f000 cfc1 \$0,\$30 +0+00fc <[^>]*> 4440f800 cfc1 \$0,c1_fcsr + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/cp1-names.s b/binutils-2.24/gas/testsuite/gas/mips/cp1-names.s new file mode 100644 index 0000000..7572354 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/cp1-names.s @@ -0,0 +1,77 @@ +# source file to test objdump's disassembly using various styles of +# CP1 register names. + + .set noreorder + .set noat + + .globl text_label .text +text_label: + + ctc1 $0, $0 + ctc1 $0, $1 + ctc1 $0, $2 + ctc1 $0, $3 + ctc1 $0, $4 + ctc1 $0, $5 + ctc1 $0, $6 + ctc1 $0, $7 + ctc1 $0, $8 + ctc1 $0, $9 + ctc1 $0, $10 + ctc1 $0, $11 + ctc1 $0, $12 + ctc1 $0, $13 + ctc1 $0, $14 + ctc1 $0, $15 + ctc1 $0, $16 + ctc1 $0, $17 + ctc1 $0, $18 + ctc1 $0, $19 + ctc1 $0, $20 + ctc1 $0, $21 + ctc1 $0, $22 + ctc1 $0, $23 + ctc1 $0, $24 + ctc1 $0, $25 + ctc1 $0, $26 + ctc1 $0, $27 + ctc1 $0, $28 + ctc1 $0, $29 + ctc1 $0, $30 + ctc1 $0, $31 + + cfc1 $0, $0 + cfc1 $0, $1 + cfc1 $0, $2 + cfc1 $0, $3 + cfc1 $0, $4 + cfc1 $0, $5 + cfc1 $0, $6 + cfc1 $0, $7 + cfc1 $0, $8 + cfc1 $0, $9 + cfc1 $0, $10 + cfc1 $0, $11 + cfc1 $0, $12 + cfc1 $0, $13 + cfc1 $0, $14 + cfc1 $0, $15 + cfc1 $0, $16 + cfc1 $0, $17 + cfc1 $0, $18 + cfc1 $0, $19 + cfc1 $0, $20 + cfc1 $0, $21 + cfc1 $0, $22 + cfc1 $0, $23 + cfc1 $0, $24 + cfc1 $0, $25 + cfc1 $0, $26 + cfc1 $0, $27 + cfc1 $0, $28 + cfc1 $0, $29 + cfc1 $0, $30 + cfc1 $0, $31 + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .space 8 diff --git a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips1.d b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips1.d index a7af692..3a3da16 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips1.d +++ b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips1.d @@ -8,3 +8,16 @@ # flags are _not_ 8 chars long. private flags = (.......|......|.....|....|...|..|.): .*\[mips1\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS1 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips2.d b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips2.d index c2c0c54..db8baf5 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips2.d +++ b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips2.d @@ -6,3 +6,16 @@ .*:.*file format.*elf.*mips.* private flags = 1.......: .*\[mips2\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips3.d b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips3.d index cf42635..1ff003c 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips3.d +++ b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips3.d @@ -6,3 +6,16 @@ .*:.*file format.*elf.*mips.* private flags = 2.......: .*\[mips3\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips32.d b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips32.d index 0c4bc93..35033f1 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips32.d +++ b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips32.d @@ -6,3 +6,16 @@ .*:.*file format.*elf.*mips.* private flags = 5.......: .*\[mips32\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS32 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips32r2.d b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips32r2.d index b0044ba..296e9c4 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips32r2.d +++ b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips32r2.d @@ -6,3 +6,16 @@ .*:.*file format.*elf.*mips.* private flags = 7.......: .*\[mips32r2\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips32r3.d b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips32r3.d new file mode 100644 index 0000000..7f7a710 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips32r3.d @@ -0,0 +1,21 @@ +# name: ELF MIPS32r3 markings +# source: empty.s +# objdump: -p +# as: -32 -march=mips32r3 + +.*:.*file format.*elf.*mips.* +private flags = 7.......: .*\[mips32r2\].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r3 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips32r5.d b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips32r5.d new file mode 100644 index 0000000..b509c67 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips32r5.d @@ -0,0 +1,21 @@ +# name: ELF MIPS32r5 markings +# source: empty.s +# objdump: -p +# as: -32 -march=mips32r5 + +.*:.*file format.*elf.*mips.* +private flags = 7.......: .*\[mips32r2\].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r5 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips4.d b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips4.d index d465582..d550e14 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips4.d +++ b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips4.d @@ -6,3 +6,16 @@ .*:.*file format.*elf.*mips.* private flags = 3.......: .*\[mips4\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS4 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips5.d b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips5.d index 39327ae..31a0f18 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips5.d +++ b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips5.d @@ -6,3 +6,16 @@ .*:.*file format.*elf.*mips.* private flags = 4.......: .*\[mips5\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS5 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips64.d b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips64.d index c3aea0f..e8c1229 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips64.d +++ b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips64.d @@ -6,3 +6,16 @@ .*:.*file format.*elf.*mips.* private flags = 6.......: .*\[mips64\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS64 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips64r2.d b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips64r2.d index aa318ce..ab580f4 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips64r2.d +++ b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips64r2.d @@ -1,8 +1,21 @@ # name: ELF MIPS64r2 markings # source: empty.s # objdump: -p -# as: -march=mips64r2 +# as: -32 -march=mips64r2 .*:.*file format.*elf.*mips.* private flags = 8.......: .*\[mips64r2\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS64r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips64r3.d b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips64r3.d new file mode 100644 index 0000000..018098c --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips64r3.d @@ -0,0 +1,21 @@ +# name: ELF MIPS64r3 markings +# source: empty.s +# objdump: -p +# as: -32 -march=mips64r3 + +.*:.*file format.*elf.*mips.* +private flags = 8.......: .*\[mips64r2\].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r3 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips64r5.d b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips64r5.d new file mode 100644 index 0000000..305d89c --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/elf_arch_mips64r5.d @@ -0,0 +1,21 @@ +# name: ELF MIPS64r5 markings +# source: empty.s +# objdump: -p +# as: -32 -march=mips64r5 + +.*:.*file format.*elf.*mips.* +private flags = 8.......: .*\[mips64r2\].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r5 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/elf_ase_micromips-2.d b/binutils-2.24/gas/testsuite/gas/mips/elf_ase_micromips-2.d index 28b7f81..e600880 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/elf_ase_micromips-2.d +++ b/binutils-2.24/gas/testsuite/gas/mips/elf_ase_micromips-2.d @@ -6,3 +6,16 @@ .*:.*file format.*mips.* private flags = [0-9a-f]*[2367abef]......: .*[[,]micromips[],].* +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + MICROMIPS ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/elf_ase_micromips.d b/binutils-2.24/gas/testsuite/gas/mips/elf_ase_micromips.d index c748dfb..13bb65a 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/elf_ase_micromips.d +++ b/binutils-2.24/gas/testsuite/gas/mips/elf_ase_micromips.d @@ -6,3 +6,16 @@ .*:.*file format.*mips.* !private flags = .*micromips.* +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/elf_ase_mips16-2.d b/binutils-2.24/gas/testsuite/gas/mips/elf_ase_mips16-2.d index 89b28b0..afd923c 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/elf_ase_mips16-2.d +++ b/binutils-2.24/gas/testsuite/gas/mips/elf_ase_mips16-2.d @@ -6,3 +6,16 @@ .*:.*file format.*mips.* private flags = [0-9a-f]*[4-7c-f]......: .*[[,]mips16[],].* +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/elf_ase_mips16.d b/binutils-2.24/gas/testsuite/gas/mips/elf_ase_mips16.d index 89fbc5b..27135f1 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/elf_ase_mips16.d +++ b/binutils-2.24/gas/testsuite/gas/mips/elf_ase_mips16.d @@ -6,3 +6,16 @@ .*:.*file format.*mips.* !private flags = .*mips16.* +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/eva.s b/binutils-2.24/gas/testsuite/gas/mips/eva.s index f7bea00..62c51e6 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/eva.s +++ b/binutils-2.24/gas/testsuite/gas/mips/eva.s @@ -230,6 +230,7 @@ test_eva: lwe $29,2147483647 lwe $30,($31) lwe $0,MYDATA +.ifndef r6 lwle $2,-256($3) lwle $4,-256 lwle $5,255($6) @@ -306,6 +307,7 @@ test_eva: lwre $19,2147483647 lwre $20,($21) lwre $22,MYDATA +.endif sbe $23,-256($24) sbe $25,-256 sbe $26,255($27) @@ -458,6 +460,7 @@ test_eva: swe $30,2147483647 swe $31,($0) swe $2,MYDATA +.ifndef r6 swle $3,-256($4) swle $5,-256 swle $6,255($7) @@ -534,6 +537,7 @@ test_eva: swre $20,2147483647 swre $21,($22) swre $23,MYDATA +.endif cachee 24,-256($25) cachee 26,-256 cachee 27,255($28) diff --git a/binutils-2.24/gas/testsuite/gas/mips/fix-rm7000-1.d b/binutils-2.24/gas/testsuite/gas/mips/fix-rm7000-1.d new file mode 100644 index 0000000..30765f6 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/fix-rm7000-1.d @@ -0,0 +1,22 @@ +#as: -mfix-rm7000 -mgp64 -mabi=64 +#objdump: -dz --prefix-addresses +#name: MIPS RM7000 workarounds test 1 +#source: fix-rm7000-1.s + +.*file format.* + +Disassembly.* + +0+0000 <[^>]*> move v0,a0 +0+0004 <[^>]*> dmult a2,v1 +0+0008 <[^>]*> nop +0+000c <[^>]*> nop +0+0010 <[^>]*> nop +0+0014 <[^>]*> ld a3,0\(s8\) +0+0018 <[^>]*> ld a0,0\(s8\) +0+001c <[^>]*> move a0,a3 +0+0020 <[^>]*> dmult v0,a3 +0+0024 <[^>]*> nop +0+0028 <[^>]*> nop +0+002c <[^>]*> nop +0+0030 <[^>]*> ld a0,0\(s8\) diff --git a/binutils-2.24/gas/testsuite/gas/mips/fix-rm7000-1.s b/binutils-2.24/gas/testsuite/gas/mips/fix-rm7000-1.s new file mode 100644 index 0000000..be7e597 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/fix-rm7000-1.s @@ -0,0 +1,10 @@ + .section .text2, "ax", @progbits + .align 2 +test1: + move $2,$4 + dmult $6,$3 + ld $7,0($fp) + ld $4,0($fp) + move $4,$7 + dmult $2,$7 + ld $4,0($fp) diff --git a/binutils-2.24/gas/testsuite/gas/mips/fix-rm7000-2.d b/binutils-2.24/gas/testsuite/gas/mips/fix-rm7000-2.d new file mode 100644 index 0000000..3ec2817 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/fix-rm7000-2.d @@ -0,0 +1,57 @@ +#as: -mfix-rm7000 +#objdump: -dz --prefix-addresses +#name: MIPS RM7000 workarounds test 2 +#source: fix-rm7000-2.s + +.*file format.* + +Disassembly.* +0+0000 <[^>]*> move v0,a0 +0+0004 <[^>]*> dmultu a1,a3 +0+0008 <[^>]*> nop +0+000c <[^>]*> nop +0+0010 <[^>]*> nop +0+0014 <[^>]*> lb a0,0\(s8\) +0+0018 <[^>]*> dmult a2,v1 +0+001c <[^>]*> nop +0+0020 <[^>]*> nop +0+0024 <[^>]*> nop +0+0028 <[^>]*> lbu a3,0\(s8\) +0+002c <[^>]*> move v0,a0 +0+0030 <[^>]*> dmultu a1,a3 +0+0034 <[^>]*> addiu a0,s8,0 +0+0038 <[^>]*> move v0,a0 +0+003c <[^>]*> dmult a2,v1 +0+0040 <[^>]*> nop +0+0044 <[^>]*> nop +0+0048 <[^>]*> nop +0+004c <[^>]*> lh a3,0\(s8\) +0+0050 <[^>]*> dmultu a1,a3 +0+0054 <[^>]*> nop +0+0058 <[^>]*> nop +0+005c <[^>]*> nop +0+0060 <[^>]*> lhu a0,0\(s8\) +0+0064 <[^>]*> dmult a2,v1 +0+0068 <[^>]*> nop +0+006c <[^>]*> nop +0+0070 <[^>]*> nop +0+0074 <[^>]*> ll a3,0\(s8\) +0+0078 <[^>]*> dmultu a1,a3 +0+007c <[^>]*> nop +0+0080 <[^>]*> nop +0+0084 <[^>]*> nop +0+0088 <[^>]*> lld a0,0\(s8\) +0+008c <[^>]*> dmultu a1,a3 +0+0090 <[^>]*> nop +0+0094 <[^>]*> nop +0+0098 <[^>]*> nop +0+009c <[^>]*> lw a0,0\(s8\) +0+00a0 <[^>]*> dmult a2,v1 +0+00a4 <[^>]*> nop +0+00a8 <[^>]*> nop +0+00ac <[^>]*> nop +0+00b0 <[^>]*> lwr a3,0\(s8\) +0+00b4 <[^>]*> dmultu a1,a3 +0+00b8 <[^>]*> nop +0+00bc <[^>]*> nop +0+00c0 <[^>]*> nop diff --git a/binutils-2.24/gas/testsuite/gas/mips/fix-rm7000-2.s b/binutils-2.24/gas/testsuite/gas/mips/fix-rm7000-2.s new file mode 100644 index 0000000..9e9ab0a --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/fix-rm7000-2.s @@ -0,0 +1,25 @@ + .section .text2, "ax", @progbits + .align 2 +test2: + move $2,$4 + dmultu $5,$7 + lb $4,0($fp) + dmult $6,$3 + lbu $7,0($fp) + move $2,$4 + dmultu $5,$7 + lca $4,0($fp) + move $2,$4 + dmult $6,$3 + lh $7,0($fp) + dmultu $5,$7 + lhu $4,0($fp) + dmult $6,$3 + ll $7,0($fp) + dmultu $5,$7 + lld $4,0($fp) + dmultu $5,$7 + lw $4,0($fp) + dmult $6,$3 + lwr $7,0($fp) + dmultu $5,$7 diff --git a/binutils-2.24/gas/testsuite/gas/mips/fpxx-oddfpreg.d b/binutils-2.24/gas/testsuite/gas/mips/fpxx-oddfpreg.d new file mode 100644 index 0000000..89f2e9b --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/fpxx-oddfpreg.d @@ -0,0 +1,12 @@ +#as: -32 -mfpxx +#objdump: -d +#name: FPXX with odd-singles test +.*: file format .* + +Disassembly of section .text: + +[ 0-9a-f]+ <.text>: +[ 0-9a-f]+: 44840800 mtc1 a0,\$f1 +[ 0-9a-f]+: 44040800 mfc1 a0,\$f1 +[ 0-9a-f]+: c4610000 lwc1 \$f1,0\(v1\) +[ 0-9a-f]+: e4610000 swc1 \$f1,0\(v1\) diff --git a/binutils-2.24/gas/testsuite/gas/mips/fpxx-oddfpreg.l b/binutils-2.24/gas/testsuite/gas/mips/fpxx-oddfpreg.l new file mode 100644 index 0000000..ae2dba7 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/fpxx-oddfpreg.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*:1: Error: unsupported access to the upper half of double-precision registers +.*:2: Error: unsupported access to the upper half of double-precision registers +.*:3: Error: unsupported access to the upper half of double-precision registers +.*:4: Error: unsupported access to the upper half of double-precision registers diff --git a/binutils-2.24/gas/testsuite/gas/mips/fpxx-oddfpreg.s b/binutils-2.24/gas/testsuite/gas/mips/fpxx-oddfpreg.s new file mode 100644 index 0000000..2136619 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/fpxx-oddfpreg.s @@ -0,0 +1,4 @@ +mtc1 $4, $f1 +mfc1 $4, $f1 +lwc1 $f1, 0($3) +swc1 $f1, 0($3) diff --git a/binutils-2.24/gas/testsuite/gas/mips/ld-zero-3.s b/binutils-2.24/gas/testsuite/gas/mips/ld-zero-3.s index 7ca414c..15d62ed 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/ld-zero-3.s +++ b/binutils-2.24/gas/testsuite/gas/mips/ld-zero-3.s @@ -2,7 +2,9 @@ foo: lwu $0, 0x12345678($2) ld $0, 0x12345678($2) +.ifndef r6 lld $0, 0x12345678($2) +.endif # Force some (non-delay-slot) zero bytes, to make 'objdump' print ... .align 4, 0 diff --git a/binutils-2.24/gas/testsuite/gas/mips/li-d.d b/binutils-2.24/gas/testsuite/gas/mips/li-d.d new file mode 100644 index 0000000..ca24570 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/li-d.d @@ -0,0 +1,31 @@ +#objdump: -d --prefix-addresses +#as: -mips64r2 +#name: MIPS li.d +#source: li-d.s + +# Test the li.d macro. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> li v(0|1),0 +[0-9a-f]+ <[^>]*> move v(1|0),zero +[0-9a-f]+ <[^>]*> li at,0 +[0-9a-f]+ <[^>]*> mtc1 at,\$f1 +[0-9a-f]+ <[^>]*> mtc1 zero,\$f0 +[0-9a-f]+ <[^>]*> li at,0 +[0-9a-f]+ <[^>]*> mtc1 at,\$f1 +[0-9a-f]+ <[^>]*> mtc1 zero,\$f0 +[0-9a-f]+ <[^>]*> ldc1 \$f0,0\(gp\) +[0-9a-f]+ <[^>]*> li at,0 +[0-9a-f]+ <[^>]*> mthc1 at,\$f0 +[0-9a-f]+ <[^>]*> mtc1 zero,\$f0 +[0-9a-f]+ <[^>]*> li at,0 +[0-9a-f]+ <[^>]*> mthc1 at,\$f0 +[0-9a-f]+ <[^>]*> mtc1 zero,\$f0 +[0-9a-f]+ <[^>]*> li at,0 +[0-9a-f]+ <[^>]*> mthc1 at,\$f0 +[0-9a-f]+ <[^>]*> mtc1 zero,\$f0 +[0-9a-f]+ <[^>]*> li at,0 +[0-9a-f]+ <[^>]*> dmtc1 at,\$f0 + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/li-d.s b/binutils-2.24/gas/testsuite/gas/mips/li-d.s new file mode 100644 index 0000000..8578097 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/li-d.s @@ -0,0 +1,24 @@ +# Source file used to test the li macro. + +foo: + .set mips1 + .set fp=32 + li.d $2, 0 + li.d $f0, 0 + .set mips2 + li.d $f0, 0 + .set fp=xx + li.d $f0, 0 + .set mips32r2 + .set fp=32 + li.d $f0, 0 + .set fp=xx + li.d $f0, 0 + .set fp=64 + li.d $f0, 0 + .set mips3 + li.d $f0, 0 + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 2 + .space 8 diff --git a/binutils-2.24/gas/testsuite/gas/mips/lui-2.l b/binutils-2.24/gas/testsuite/gas/mips/lui-2.l index ed97e85..635f97d 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/lui-2.l +++ b/binutils-2.24/gas/testsuite/gas/mips/lui-2.l @@ -1,5 +1,5 @@ .*\.s: Assembler messages: .*\.s:10: Error: invalid operands \(\*UND\* and \*UND\* sections\) for `/' -.*\.s:7: Error: can't resolve `bar' {\*UND\* section} - `foo' {\.text section} +.*\.s:7: Error: PC-relative reference to a different section .*\.s:8: Error: can't resolve `baz' {\*UND\* section} - `bar' {\*UND\* section} .*\.s:9: Error: can't resolve `\.text' {\.text section} - `baz' {\*UND\* section} diff --git a/binutils-2.24/gas/testsuite/gas/mips/micromips-insn32.d b/binutils-2.24/gas/testsuite/gas/mips/micromips-insn32.d index a28c519..c0ff2db 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/micromips-insn32.d +++ b/binutils-2.24/gas/testsuite/gas/mips/micromips-insn32.d @@ -5412,11 +5412,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 5401 1b3b ceil\.w\.s \$f0,\$f1 [ 0-9a-f]+: 57df 1b3b ceil\.w\.s \$f30,\$f31 [ 0-9a-f]+: 5442 1b3b ceil\.w\.s \$f2,\$f2 -[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0 -[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1 +[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir +[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr [ 0-9a-f]+: 54a2 103b cfc1 a1,\$2 [ 0-9a-f]+: 54a3 103b cfc1 a1,\$3 -[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4 +[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr [ 0-9a-f]+: 54a5 103b cfc1 a1,\$5 [ 0-9a-f]+: 54a6 103b cfc1 a1,\$6 [ 0-9a-f]+: 54a7 103b cfc1 a1,\$7 @@ -5437,18 +5437,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 103b cfc1 a1,\$22 [ 0-9a-f]+: 54b7 103b cfc1 a1,\$23 [ 0-9a-f]+: 54b8 103b cfc1 a1,\$24 -[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25 -[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26 +[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr [ 0-9a-f]+: 54bb 103b cfc1 a1,\$27 -[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28 +[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr [ 0-9a-f]+: 54bd 103b cfc1 a1,\$29 [ 0-9a-f]+: 54be 103b cfc1 a1,\$30 -[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31 -[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0 -[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1 +[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir +[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr [ 0-9a-f]+: 54a2 103b cfc1 a1,\$2 [ 0-9a-f]+: 54a3 103b cfc1 a1,\$3 -[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4 +[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr [ 0-9a-f]+: 54a5 103b cfc1 a1,\$5 [ 0-9a-f]+: 54a6 103b cfc1 a1,\$6 [ 0-9a-f]+: 54a7 103b cfc1 a1,\$7 @@ -5469,13 +5469,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 103b cfc1 a1,\$22 [ 0-9a-f]+: 54b7 103b cfc1 a1,\$23 [ 0-9a-f]+: 54b8 103b cfc1 a1,\$24 -[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25 -[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26 +[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr [ 0-9a-f]+: 54bb 103b cfc1 a1,\$27 -[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28 +[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr [ 0-9a-f]+: 54bd 103b cfc1 a1,\$29 [ 0-9a-f]+: 54be 103b cfc1 a1,\$30 -[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31 +[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr [ 0-9a-f]+: 00a0 cd3c cfc2 a1,\$0 [ 0-9a-f]+: 00a1 cd3c cfc2 a1,\$1 [ 0-9a-f]+: 00a2 cd3c cfc2 a1,\$2 @@ -5508,11 +5508,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 00bd cd3c cfc2 a1,\$29 [ 0-9a-f]+: 00be cd3c cfc2 a1,\$30 [ 0-9a-f]+: 00bf cd3c cfc2 a1,\$31 -[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0 -[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1 +[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir +[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr [ 0-9a-f]+: 54a2 183b ctc1 a1,\$2 [ 0-9a-f]+: 54a3 183b ctc1 a1,\$3 -[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4 +[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr [ 0-9a-f]+: 54a5 183b ctc1 a1,\$5 [ 0-9a-f]+: 54a6 183b ctc1 a1,\$6 [ 0-9a-f]+: 54a7 183b ctc1 a1,\$7 @@ -5533,18 +5533,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 183b ctc1 a1,\$22 [ 0-9a-f]+: 54b7 183b ctc1 a1,\$23 [ 0-9a-f]+: 54b8 183b ctc1 a1,\$24 -[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25 -[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26 +[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr [ 0-9a-f]+: 54bb 183b ctc1 a1,\$27 -[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28 +[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr [ 0-9a-f]+: 54bd 183b ctc1 a1,\$29 [ 0-9a-f]+: 54be 183b ctc1 a1,\$30 -[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31 -[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0 -[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1 +[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir +[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr [ 0-9a-f]+: 54a2 183b ctc1 a1,\$2 [ 0-9a-f]+: 54a3 183b ctc1 a1,\$3 -[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4 +[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr [ 0-9a-f]+: 54a5 183b ctc1 a1,\$5 [ 0-9a-f]+: 54a6 183b ctc1 a1,\$6 [ 0-9a-f]+: 54a7 183b ctc1 a1,\$7 @@ -5565,13 +5565,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 183b ctc1 a1,\$22 [ 0-9a-f]+: 54b7 183b ctc1 a1,\$23 [ 0-9a-f]+: 54b8 183b ctc1 a1,\$24 -[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25 -[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26 +[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr [ 0-9a-f]+: 54bb 183b ctc1 a1,\$27 -[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28 +[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr [ 0-9a-f]+: 54bd 183b ctc1 a1,\$29 [ 0-9a-f]+: 54be 183b ctc1 a1,\$30 -[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31 +[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr [ 0-9a-f]+: 00a0 dd3c ctc2 a1,\$0 [ 0-9a-f]+: 00a1 dd3c ctc2 a1,\$1 [ 0-9a-f]+: 00a2 dd3c ctc2 a1,\$2 @@ -6787,11 +6787,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29 [ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30 [ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31 -[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0 -[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1 +[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir +[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr [ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2 [ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3 -[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4 +[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr [ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5 [ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6 [ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7 @@ -6812,18 +6812,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22 [ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23 [ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24 -[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25 -[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26 +[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr [ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27 -[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28 +[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr [ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29 [ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30 -[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31 -[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0 -[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1 +[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir +[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr [ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2 [ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3 -[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4 +[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr [ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5 [ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6 [ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7 @@ -6844,13 +6844,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22 [ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23 [ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24 -[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25 -[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26 +[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr [ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27 -[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28 +[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr [ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29 [ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30 -[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31 +[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr [ 0-9a-f]+: 0040 6d3c dmfc2 v0,\$0 [ 0-9a-f]+: 0041 6d3c dmfc2 v0,\$1 [ 0-9a-f]+: 0042 6d3c dmfc2 v0,\$2 diff --git a/binutils-2.24/gas/testsuite/gas/mips/micromips-noinsn32.d b/binutils-2.24/gas/testsuite/gas/mips/micromips-noinsn32.d index 520c9cb..5bbaab1 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/micromips-noinsn32.d +++ b/binutils-2.24/gas/testsuite/gas/mips/micromips-noinsn32.d @@ -5391,11 +5391,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 5401 1b3b ceil\.w\.s \$f0,\$f1 [ 0-9a-f]+: 57df 1b3b ceil\.w\.s \$f30,\$f31 [ 0-9a-f]+: 5442 1b3b ceil\.w\.s \$f2,\$f2 -[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0 -[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1 +[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir +[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr [ 0-9a-f]+: 54a2 103b cfc1 a1,\$2 [ 0-9a-f]+: 54a3 103b cfc1 a1,\$3 -[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4 +[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr [ 0-9a-f]+: 54a5 103b cfc1 a1,\$5 [ 0-9a-f]+: 54a6 103b cfc1 a1,\$6 [ 0-9a-f]+: 54a7 103b cfc1 a1,\$7 @@ -5416,18 +5416,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 103b cfc1 a1,\$22 [ 0-9a-f]+: 54b7 103b cfc1 a1,\$23 [ 0-9a-f]+: 54b8 103b cfc1 a1,\$24 -[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25 -[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26 +[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr [ 0-9a-f]+: 54bb 103b cfc1 a1,\$27 -[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28 +[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr [ 0-9a-f]+: 54bd 103b cfc1 a1,\$29 [ 0-9a-f]+: 54be 103b cfc1 a1,\$30 -[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31 -[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0 -[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1 +[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir +[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr [ 0-9a-f]+: 54a2 103b cfc1 a1,\$2 [ 0-9a-f]+: 54a3 103b cfc1 a1,\$3 -[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4 +[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr [ 0-9a-f]+: 54a5 103b cfc1 a1,\$5 [ 0-9a-f]+: 54a6 103b cfc1 a1,\$6 [ 0-9a-f]+: 54a7 103b cfc1 a1,\$7 @@ -5448,13 +5448,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 103b cfc1 a1,\$22 [ 0-9a-f]+: 54b7 103b cfc1 a1,\$23 [ 0-9a-f]+: 54b8 103b cfc1 a1,\$24 -[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25 -[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26 +[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr [ 0-9a-f]+: 54bb 103b cfc1 a1,\$27 -[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28 +[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr [ 0-9a-f]+: 54bd 103b cfc1 a1,\$29 [ 0-9a-f]+: 54be 103b cfc1 a1,\$30 -[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31 +[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr [ 0-9a-f]+: 00a0 cd3c cfc2 a1,\$0 [ 0-9a-f]+: 00a1 cd3c cfc2 a1,\$1 [ 0-9a-f]+: 00a2 cd3c cfc2 a1,\$2 @@ -5487,11 +5487,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 00bd cd3c cfc2 a1,\$29 [ 0-9a-f]+: 00be cd3c cfc2 a1,\$30 [ 0-9a-f]+: 00bf cd3c cfc2 a1,\$31 -[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0 -[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1 +[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir +[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr [ 0-9a-f]+: 54a2 183b ctc1 a1,\$2 [ 0-9a-f]+: 54a3 183b ctc1 a1,\$3 -[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4 +[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr [ 0-9a-f]+: 54a5 183b ctc1 a1,\$5 [ 0-9a-f]+: 54a6 183b ctc1 a1,\$6 [ 0-9a-f]+: 54a7 183b ctc1 a1,\$7 @@ -5512,18 +5512,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 183b ctc1 a1,\$22 [ 0-9a-f]+: 54b7 183b ctc1 a1,\$23 [ 0-9a-f]+: 54b8 183b ctc1 a1,\$24 -[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25 -[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26 +[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr [ 0-9a-f]+: 54bb 183b ctc1 a1,\$27 -[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28 +[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr [ 0-9a-f]+: 54bd 183b ctc1 a1,\$29 [ 0-9a-f]+: 54be 183b ctc1 a1,\$30 -[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31 -[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0 -[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1 +[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir +[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr [ 0-9a-f]+: 54a2 183b ctc1 a1,\$2 [ 0-9a-f]+: 54a3 183b ctc1 a1,\$3 -[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4 +[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr [ 0-9a-f]+: 54a5 183b ctc1 a1,\$5 [ 0-9a-f]+: 54a6 183b ctc1 a1,\$6 [ 0-9a-f]+: 54a7 183b ctc1 a1,\$7 @@ -5544,13 +5544,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 183b ctc1 a1,\$22 [ 0-9a-f]+: 54b7 183b ctc1 a1,\$23 [ 0-9a-f]+: 54b8 183b ctc1 a1,\$24 -[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25 -[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26 +[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr [ 0-9a-f]+: 54bb 183b ctc1 a1,\$27 -[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28 +[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr [ 0-9a-f]+: 54bd 183b ctc1 a1,\$29 [ 0-9a-f]+: 54be 183b ctc1 a1,\$30 -[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31 +[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr [ 0-9a-f]+: 00a0 dd3c ctc2 a1,\$0 [ 0-9a-f]+: 00a1 dd3c ctc2 a1,\$1 [ 0-9a-f]+: 00a2 dd3c ctc2 a1,\$2 @@ -6766,11 +6766,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29 [ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30 [ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31 -[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0 -[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1 +[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir +[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr [ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2 [ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3 -[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4 +[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr [ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5 [ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6 [ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7 @@ -6791,18 +6791,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22 [ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23 [ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24 -[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25 -[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26 +[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr [ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27 -[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28 +[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr [ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29 [ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30 -[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31 -[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0 -[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1 +[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir +[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr [ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2 [ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3 -[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4 +[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr [ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5 [ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6 [ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7 @@ -6823,13 +6823,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22 [ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23 [ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24 -[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25 -[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26 +[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr [ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27 -[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28 +[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr [ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29 [ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30 -[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31 +[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr [ 0-9a-f]+: 0040 6d3c dmfc2 v0,\$0 [ 0-9a-f]+: 0041 6d3c dmfc2 v0,\$1 [ 0-9a-f]+: 0042 6d3c dmfc2 v0,\$2 diff --git a/binutils-2.24/gas/testsuite/gas/mips/micromips-trap.d b/binutils-2.24/gas/testsuite/gas/mips/micromips-trap.d index f1167a0..cfb0979 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/micromips-trap.d +++ b/binutils-2.24/gas/testsuite/gas/mips/micromips-trap.d @@ -5397,11 +5397,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 5401 1b3b ceil\.w\.s \$f0,\$f1 [ 0-9a-f]+: 57df 1b3b ceil\.w\.s \$f30,\$f31 [ 0-9a-f]+: 5442 1b3b ceil\.w\.s \$f2,\$f2 -[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0 -[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1 +[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir +[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr [ 0-9a-f]+: 54a2 103b cfc1 a1,\$2 [ 0-9a-f]+: 54a3 103b cfc1 a1,\$3 -[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4 +[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr [ 0-9a-f]+: 54a5 103b cfc1 a1,\$5 [ 0-9a-f]+: 54a6 103b cfc1 a1,\$6 [ 0-9a-f]+: 54a7 103b cfc1 a1,\$7 @@ -5422,18 +5422,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 103b cfc1 a1,\$22 [ 0-9a-f]+: 54b7 103b cfc1 a1,\$23 [ 0-9a-f]+: 54b8 103b cfc1 a1,\$24 -[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25 -[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26 +[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr [ 0-9a-f]+: 54bb 103b cfc1 a1,\$27 -[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28 +[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr [ 0-9a-f]+: 54bd 103b cfc1 a1,\$29 [ 0-9a-f]+: 54be 103b cfc1 a1,\$30 -[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31 -[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0 -[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1 +[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir +[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr [ 0-9a-f]+: 54a2 103b cfc1 a1,\$2 [ 0-9a-f]+: 54a3 103b cfc1 a1,\$3 -[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4 +[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr [ 0-9a-f]+: 54a5 103b cfc1 a1,\$5 [ 0-9a-f]+: 54a6 103b cfc1 a1,\$6 [ 0-9a-f]+: 54a7 103b cfc1 a1,\$7 @@ -5454,13 +5454,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 103b cfc1 a1,\$22 [ 0-9a-f]+: 54b7 103b cfc1 a1,\$23 [ 0-9a-f]+: 54b8 103b cfc1 a1,\$24 -[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25 -[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26 +[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr [ 0-9a-f]+: 54bb 103b cfc1 a1,\$27 -[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28 +[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr [ 0-9a-f]+: 54bd 103b cfc1 a1,\$29 [ 0-9a-f]+: 54be 103b cfc1 a1,\$30 -[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31 +[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr [ 0-9a-f]+: 00a0 cd3c cfc2 a1,\$0 [ 0-9a-f]+: 00a1 cd3c cfc2 a1,\$1 [ 0-9a-f]+: 00a2 cd3c cfc2 a1,\$2 @@ -5493,11 +5493,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 00bd cd3c cfc2 a1,\$29 [ 0-9a-f]+: 00be cd3c cfc2 a1,\$30 [ 0-9a-f]+: 00bf cd3c cfc2 a1,\$31 -[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0 -[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1 +[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir +[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr [ 0-9a-f]+: 54a2 183b ctc1 a1,\$2 [ 0-9a-f]+: 54a3 183b ctc1 a1,\$3 -[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4 +[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr [ 0-9a-f]+: 54a5 183b ctc1 a1,\$5 [ 0-9a-f]+: 54a6 183b ctc1 a1,\$6 [ 0-9a-f]+: 54a7 183b ctc1 a1,\$7 @@ -5518,18 +5518,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 183b ctc1 a1,\$22 [ 0-9a-f]+: 54b7 183b ctc1 a1,\$23 [ 0-9a-f]+: 54b8 183b ctc1 a1,\$24 -[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25 -[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26 +[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr [ 0-9a-f]+: 54bb 183b ctc1 a1,\$27 -[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28 +[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr [ 0-9a-f]+: 54bd 183b ctc1 a1,\$29 [ 0-9a-f]+: 54be 183b ctc1 a1,\$30 -[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31 -[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0 -[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1 +[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir +[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr [ 0-9a-f]+: 54a2 183b ctc1 a1,\$2 [ 0-9a-f]+: 54a3 183b ctc1 a1,\$3 -[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4 +[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr [ 0-9a-f]+: 54a5 183b ctc1 a1,\$5 [ 0-9a-f]+: 54a6 183b ctc1 a1,\$6 [ 0-9a-f]+: 54a7 183b ctc1 a1,\$7 @@ -5550,13 +5550,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 183b ctc1 a1,\$22 [ 0-9a-f]+: 54b7 183b ctc1 a1,\$23 [ 0-9a-f]+: 54b8 183b ctc1 a1,\$24 -[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25 -[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26 +[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr [ 0-9a-f]+: 54bb 183b ctc1 a1,\$27 -[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28 +[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr [ 0-9a-f]+: 54bd 183b ctc1 a1,\$29 [ 0-9a-f]+: 54be 183b ctc1 a1,\$30 -[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31 +[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr [ 0-9a-f]+: 00a0 dd3c ctc2 a1,\$0 [ 0-9a-f]+: 00a1 dd3c ctc2 a1,\$1 [ 0-9a-f]+: 00a2 dd3c ctc2 a1,\$2 @@ -6757,11 +6757,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29 [ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30 [ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31 -[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0 -[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1 +[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir +[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr [ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2 [ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3 -[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4 +[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr [ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5 [ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6 [ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7 @@ -6782,18 +6782,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22 [ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23 [ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24 -[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25 -[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26 +[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr [ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27 -[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28 +[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr [ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29 [ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30 -[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31 -[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0 -[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1 +[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir +[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr [ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2 [ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3 -[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4 +[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr [ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5 [ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6 [ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7 @@ -6814,13 +6814,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22 [ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23 [ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24 -[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25 -[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26 +[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr [ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27 -[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28 +[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr [ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29 [ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30 -[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31 +[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr [ 0-9a-f]+: 0040 6d3c dmfc2 v0,\$0 [ 0-9a-f]+: 0041 6d3c dmfc2 v0,\$1 [ 0-9a-f]+: 0042 6d3c dmfc2 v0,\$2 diff --git a/binutils-2.24/gas/testsuite/gas/mips/micromips.d b/binutils-2.24/gas/testsuite/gas/mips/micromips.d index 4821d09..e262663 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/micromips.d +++ b/binutils-2.24/gas/testsuite/gas/mips/micromips.d @@ -5469,11 +5469,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 5401 1b3b ceil\.w\.s \$f0,\$f1 [ 0-9a-f]+: 57df 1b3b ceil\.w\.s \$f30,\$f31 [ 0-9a-f]+: 5442 1b3b ceil\.w\.s \$f2,\$f2 -[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0 -[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1 +[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir +[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr [ 0-9a-f]+: 54a2 103b cfc1 a1,\$2 [ 0-9a-f]+: 54a3 103b cfc1 a1,\$3 -[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4 +[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr [ 0-9a-f]+: 54a5 103b cfc1 a1,\$5 [ 0-9a-f]+: 54a6 103b cfc1 a1,\$6 [ 0-9a-f]+: 54a7 103b cfc1 a1,\$7 @@ -5494,18 +5494,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 103b cfc1 a1,\$22 [ 0-9a-f]+: 54b7 103b cfc1 a1,\$23 [ 0-9a-f]+: 54b8 103b cfc1 a1,\$24 -[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25 -[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26 +[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr [ 0-9a-f]+: 54bb 103b cfc1 a1,\$27 -[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28 +[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr [ 0-9a-f]+: 54bd 103b cfc1 a1,\$29 [ 0-9a-f]+: 54be 103b cfc1 a1,\$30 -[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31 -[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0 -[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1 +[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir +[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr [ 0-9a-f]+: 54a2 103b cfc1 a1,\$2 [ 0-9a-f]+: 54a3 103b cfc1 a1,\$3 -[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4 +[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr [ 0-9a-f]+: 54a5 103b cfc1 a1,\$5 [ 0-9a-f]+: 54a6 103b cfc1 a1,\$6 [ 0-9a-f]+: 54a7 103b cfc1 a1,\$7 @@ -5526,13 +5526,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 103b cfc1 a1,\$22 [ 0-9a-f]+: 54b7 103b cfc1 a1,\$23 [ 0-9a-f]+: 54b8 103b cfc1 a1,\$24 -[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25 -[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26 +[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr [ 0-9a-f]+: 54bb 103b cfc1 a1,\$27 -[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28 +[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr [ 0-9a-f]+: 54bd 103b cfc1 a1,\$29 [ 0-9a-f]+: 54be 103b cfc1 a1,\$30 -[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31 +[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr [ 0-9a-f]+: 00a0 cd3c cfc2 a1,\$0 [ 0-9a-f]+: 00a1 cd3c cfc2 a1,\$1 [ 0-9a-f]+: 00a2 cd3c cfc2 a1,\$2 @@ -5565,11 +5565,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 00bd cd3c cfc2 a1,\$29 [ 0-9a-f]+: 00be cd3c cfc2 a1,\$30 [ 0-9a-f]+: 00bf cd3c cfc2 a1,\$31 -[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0 -[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1 +[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir +[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr [ 0-9a-f]+: 54a2 183b ctc1 a1,\$2 [ 0-9a-f]+: 54a3 183b ctc1 a1,\$3 -[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4 +[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr [ 0-9a-f]+: 54a5 183b ctc1 a1,\$5 [ 0-9a-f]+: 54a6 183b ctc1 a1,\$6 [ 0-9a-f]+: 54a7 183b ctc1 a1,\$7 @@ -5590,18 +5590,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 183b ctc1 a1,\$22 [ 0-9a-f]+: 54b7 183b ctc1 a1,\$23 [ 0-9a-f]+: 54b8 183b ctc1 a1,\$24 -[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25 -[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26 +[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr [ 0-9a-f]+: 54bb 183b ctc1 a1,\$27 -[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28 +[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr [ 0-9a-f]+: 54bd 183b ctc1 a1,\$29 [ 0-9a-f]+: 54be 183b ctc1 a1,\$30 -[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31 -[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0 -[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1 +[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir +[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr [ 0-9a-f]+: 54a2 183b ctc1 a1,\$2 [ 0-9a-f]+: 54a3 183b ctc1 a1,\$3 -[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4 +[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr [ 0-9a-f]+: 54a5 183b ctc1 a1,\$5 [ 0-9a-f]+: 54a6 183b ctc1 a1,\$6 [ 0-9a-f]+: 54a7 183b ctc1 a1,\$7 @@ -5622,13 +5622,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 183b ctc1 a1,\$22 [ 0-9a-f]+: 54b7 183b ctc1 a1,\$23 [ 0-9a-f]+: 54b8 183b ctc1 a1,\$24 -[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25 -[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26 +[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr [ 0-9a-f]+: 54bb 183b ctc1 a1,\$27 -[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28 +[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr [ 0-9a-f]+: 54bd 183b ctc1 a1,\$29 [ 0-9a-f]+: 54be 183b ctc1 a1,\$30 -[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31 +[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr [ 0-9a-f]+: 00a0 dd3c ctc2 a1,\$0 [ 0-9a-f]+: 00a1 dd3c ctc2 a1,\$1 [ 0-9a-f]+: 00a2 dd3c ctc2 a1,\$2 @@ -6844,11 +6844,11 @@ Disassembly of section \.text: [ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29 [ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30 [ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31 -[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0 -[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1 +[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir +[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr [ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2 [ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3 -[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4 +[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr [ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5 [ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6 [ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7 @@ -6869,18 +6869,18 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22 [ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23 [ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24 -[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25 -[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26 +[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr [ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27 -[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28 +[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr [ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29 [ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30 -[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31 -[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$0 -[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$1 +[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr +[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,c1_fir +[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,c1_ufr [ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$2 [ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$3 -[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$4 +[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,c1_unfr [ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$5 [ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$6 [ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$7 @@ -6901,13 +6901,13 @@ Disassembly of section \.text: [ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$22 [ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$23 [ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$24 -[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$25 -[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$26 +[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,c1_fccr +[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,c1_fexr [ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$27 -[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$28 +[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,c1_fenr [ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$29 [ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$30 -[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$31 +[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,c1_fcsr [ 0-9a-f]+: 0040 6d3c dmfc2 v0,\$0 [ 0-9a-f]+: 0041 6d3c dmfc2 v0,\$1 [ 0-9a-f]+: 0042 6d3c dmfc2 v0,\$2 diff --git a/binutils-2.24/gas/testsuite/gas/mips/micromips@fix-rm7000-1.d b/binutils-2.24/gas/testsuite/gas/mips/micromips@fix-rm7000-1.d new file mode 100644 index 0000000..9225fba --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/micromips@fix-rm7000-1.d @@ -0,0 +1,16 @@ +#as: -mfix-rm7000 -mgp64 -mabi=64 +#objdump: -dz --prefix-addresses +#name: MIPS RM7000 workarounds test 1 +#source: fix-rm7000-1.s + +.*file format.* + +Disassembly.* + +0+0000 <[^>]*> move v0,a0 +0+0002 <[^>]*> dmult a2,v1 +0+0006 <[^>]*> ld a3,0\(s8\) +0+000a <[^>]*> ld a0,0\(s8\) +0+000e <[^>]*> move a0,a3 +0+0010 <[^>]*> dmult v0,a3 +0+0014 <[^>]*> ld a0,0\(s8\) diff --git a/binutils-2.24/gas/testsuite/gas/mips/micromips@fix-rm7000-2.d b/binutils-2.24/gas/testsuite/gas/mips/micromips@fix-rm7000-2.d new file mode 100644 index 0000000..b95d615 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/micromips@fix-rm7000-2.d @@ -0,0 +1,31 @@ +#as: -mfix-rm7000 +#objdump: -dz --prefix-addresses +#name: MIPS RM7000 workarounds test 2 +#source: fix-rm7000-2.s + +.*file format.* + +Disassembly.* +0+0000 <[^>]*> move v0,a0 +0+0002 <[^>]*> dmultu a1,a3 +0+0006 <[^>]*> lb a0,0\(s8\) +0+000a <[^>]*> dmult a2,v1 +0+000e <[^>]*> lbu a3,0\(s8\) +0+0012 <[^>]*> move v0,a0 +0+0014 <[^>]*> dmultu a1,a3 +0+0018 <[^>]*> addiu a0,s8,0 +0+001c <[^>]*> move v0,a0 +0+001e <[^>]*> dmult a2,v1 +0+0022 <[^>]*> lh a3,0\(s8\) +0+0026 <[^>]*> dmultu a1,a3 +0+002a <[^>]*> lhu a0,0\(s8\) +0+002e <[^>]*> dmult a2,v1 +0+0032 <[^>]*> ll a3,0\(s8\) +0+0036 <[^>]*> dmultu a1,a3 +0+003a <[^>]*> lld a0,0\(s8\) +0+003e <[^>]*> dmultu a1,a3 +0+0042 <[^>]*> lw a0,0\(s8\) +0+0046 <[^>]*> dmult a2,v1 +0+004a <[^>]*> lwr a3,0\(s8\) +0+004e <[^>]*> dmultu a1,a3 +0+0052 <[^>]*> nop diff --git a/binutils-2.24/gas/testsuite/gas/mips/micromips@msa-branch.d b/binutils-2.24/gas/testsuite/gas/mips/micromips@msa-branch.d new file mode 100644 index 0000000..8b22b9e --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/micromips@msa-branch.d @@ -0,0 +1,309 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa +#name: MSA branch reorder +#as: -32 -mmsa +#source: msa-branch.s + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 8300 fffe bz\.b \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8301 fffe bz\.b \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 8302 fffe bz\.b \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 8300 fffe bz\.b \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8301 fffe bz\.b \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 8302 fffe bz\.b \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8300 fffe bz\.b \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8301 fffe bz\.b \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8302 fffe bz\.b \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 8320 fffe bz\.h \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8321 fffe bz\.h \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 8322 fffe bz\.h \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 8320 fffe bz\.h \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8321 fffe bz\.h \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 8322 fffe bz\.h \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8320 fffe bz\.h \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8321 fffe bz\.h \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8322 fffe bz\.h \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 8340 fffe bz\.w \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8341 fffe bz\.w \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 8342 fffe bz\.w \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 8340 fffe bz\.w \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8341 fffe bz\.w \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 8342 fffe bz\.w \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8340 fffe bz\.w \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8341 fffe bz\.w \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8342 fffe bz\.w \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 8360 fffe bz\.d \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8361 fffe bz\.d \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 8362 fffe bz\.d \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 8360 fffe bz\.d \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8361 fffe bz\.d \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: 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<[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 8162 fffe bz\.v \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 8160 fffe bz\.v \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8161 fffe bz\.v \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 8162 fffe bz\.v \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8160 fffe bz\.v \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8161 fffe bz\.v \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8162 fffe bz\.v \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 8380 fffe bnz\.b \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8381 fffe bnz\.b \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 8382 fffe bnz\.b \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 8380 fffe bnz\.b \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8381 fffe bnz\.b \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 8382 fffe bnz\.b \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8380 fffe bnz\.b \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8381 fffe bnz\.b \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8382 fffe bnz\.b \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 83a0 fffe bnz\.h \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83a1 fffe bnz\.h \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 83a2 fffe bnz\.h \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 83a0 fffe bnz\.h \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83a1 fffe bnz\.h \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 83a2 fffe bnz\.h \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 83a0 fffe bnz\.h \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83a1 fffe bnz\.h \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 83a2 fffe bnz\.h \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 83c0 fffe bnz\.w \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83c1 fffe bnz\.w \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 83c2 fffe bnz\.w \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 83c0 fffe bnz\.w \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83c1 fffe bnz\.w \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 83c2 fffe bnz\.w \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 83c0 fffe bnz\.w \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83c1 fffe bnz\.w \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 83c2 fffe bnz\.w \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 83e0 fffe bnz\.d \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83e1 fffe bnz\.d \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 83e2 fffe bnz\.d \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 83e0 fffe bnz\.d \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83e1 fffe bnz\.d \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 83e2 fffe bnz\.d \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 83e0 fffe bnz\.d \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83e1 fffe bnz\.d \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 83e2 fffe bnz\.d \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 81e0 fffe bnz\.v \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 81e1 fffe bnz\.v \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 81e2 fffe bnz\.v \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5aa2 080e fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 81e0 fffe bnz\.v \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 81e1 fffe bnz\.v \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 81e2 fffe bnz\.v \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5441 0030 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 81e0 fffe bnz\.v \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 81e1 fffe bnz\.v \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 81e2 fffe bnz\.v \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/micromips@msa-relax.d b/binutils-2.24/gas/testsuite/gas/mips/micromips@msa-relax.d new file mode 100644 index 0000000..cf49e20 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/micromips@msa-relax.d @@ -0,0 +1,131 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa +#name: MSA relax +#as: -32 -mmsa -relax-branch +#stderr: msa-relax.l +#source: msa-relax.s + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 8380 fffe bnz\.b \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83a1 fffe bnz\.h \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83c2 fffe bnz\.w \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83e3 fffe bnz\.d \$w3,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8304 fffe bz\.b \$w4,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8325 fffe bz\.h \$w5,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8346 fffe bz\.w \$w6,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8367 fffe bz\.d \$w7,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 81e8 fffe bnz\.v \$w8,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8169 fffe bz\.v \$w9,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 bar +[0-9a-f]+ <[^>]*> 0c00 nop + \.\.\. +[0-9a-f]+ <[^>]*> 838a fffe bnz\.b \$w10,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83ab fffe bnz\.h \$w11,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83cc fffe bnz\.w \$w12,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83ed fffe bnz\.d \$w13,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 830e fffe bz\.b \$w14,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 832f fffe bz\.h \$w15,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8350 fffe bz\.w \$w16,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8371 fffe bz\.d \$w17,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 81f2 fffe bnz\.v \$w18,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8173 fffe bz\.v \$w19,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> d400 0000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_26_S1 foo +[0-9a-f]+ <[^>]*> 0c00 nop + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/micromips@msa.d b/binutils-2.24/gas/testsuite/gas/mips/micromips@msa.d new file mode 100644 index 0000000..0ea25af --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/micromips@msa.d @@ -0,0 +1,788 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa +#name: MSA instructions +#source: msa.s +#as: -32 -mmsa --defsym insn_log2=1 + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 5802 081a sll\.b \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5825 20da sll\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 5848 399a sll\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 586b 525a sll\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 5870 6b12 slli\.b \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 5877 7b92 slli\.b \$w14,\$w15,0x7 +[0-9a-f]+ <[^>]*> 5860 8c12 slli\.h \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 586f 9c92 slli\.h \$w18,\$w19,0xf +[0-9a-f]+ <[^>]*> 5840 ad12 slli\.w \$w20,\$w21,0x0 +[0-9a-f]+ <[^>]*> 585f bd92 slli\.w \$w22,\$w23,0x1f +[0-9a-f]+ <[^>]*> 5800 ce12 slli\.d \$w24,\$w25,0x0 +[0-9a-f]+ <[^>]*> 583f de92 slli\.d \$w26,\$w27,0x3f +[0-9a-f]+ <[^>]*> 589e ef1a sra\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 58a1 07da sra\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 58c4 189a sra\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 58e7 315a sra\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 58f0 4a12 srai\.b \$w8,\$w9,0x0 +[0-9a-f]+ <[^>]*> 58f7 5a92 srai\.b \$w10,\$w11,0x7 +[0-9a-f]+ <[^>]*> 58e0 6b12 srai\.h \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 58ef 7b92 srai\.h \$w14,\$w15,0xf +[0-9a-f]+ <[^>]*> 58c0 8c12 srai\.w \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 58df 9c92 srai\.w \$w18,\$w19,0x1f +[0-9a-f]+ <[^>]*> 5880 ad12 srai\.d \$w20,\$w21,0x0 +[0-9a-f]+ <[^>]*> 58bf bd92 srai\.d \$w22,\$w23,0x3f +[0-9a-f]+ <[^>]*> 591a ce1a srl\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 593d e6da srl\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 5940 ff9a srl\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 5963 105a srl\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 5970 2912 srli\.b \$w4,\$w5,0x0 +[0-9a-f]+ <[^>]*> 5977 3992 srli\.b \$w6,\$w7,0x7 +[0-9a-f]+ <[^>]*> 5960 4a12 srli\.h \$w8,\$w9,0x0 +[0-9a-f]+ <[^>]*> 596f 5a92 srli\.h \$w10,\$w11,0xf +[0-9a-f]+ <[^>]*> 5940 6b12 srli\.w \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 595f 7b92 srli\.w \$w14,\$w15,0x1f +[0-9a-f]+ <[^>]*> 5900 8c12 srli\.d \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 593f 9c92 srli\.d \$w18,\$w19,0x3f +[0-9a-f]+ <[^>]*> 5996 ad1a bclr\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 59b9 c5da bclr\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 59dc de9a bclr\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 59ff f75a bclr\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 59f0 0812 bclri\.b \$w0,\$w1,0x0 +[0-9a-f]+ <[^>]*> 59f7 1892 bclri\.b \$w2,\$w3,0x7 +[0-9a-f]+ <[^>]*> 59e0 2912 bclri\.h \$w4,\$w5,0x0 +[0-9a-f]+ <[^>]*> 59ef 3992 bclri\.h \$w6,\$w7,0xf +[0-9a-f]+ <[^>]*> 59c0 4a12 bclri\.w \$w8,\$w9,0x0 +[0-9a-f]+ <[^>]*> 59df 5a92 bclri\.w \$w10,\$w11,0x1f +[0-9a-f]+ <[^>]*> 5980 6b12 bclri\.d \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 59bf 7b92 bclri\.d \$w14,\$w15,0x3f +[0-9a-f]+ <[^>]*> 5a12 8c1a bset\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 5a35 a4da bset\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 5a58 bd9a bset\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 5a7b d65a bset\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 5a70 ef12 bseti\.b \$w28,\$w29,0x0 +[0-9a-f]+ <[^>]*> 5a77 ff92 bseti\.b \$w30,\$w31,0x7 +[0-9a-f]+ <[^>]*> 5a60 0812 bseti\.h \$w0,\$w1,0x0 +[0-9a-f]+ <[^>]*> 5a6f 1892 bseti\.h \$w2,\$w3,0xf +[0-9a-f]+ <[^>]*> 5a40 2912 bseti\.w \$w4,\$w5,0x0 +[0-9a-f]+ <[^>]*> 5a5f 3992 bseti\.w \$w6,\$w7,0x1f +[0-9a-f]+ <[^>]*> 5a00 4a12 bseti\.d \$w8,\$w9,0x0 +[0-9a-f]+ <[^>]*> 5a3f 5a92 bseti\.d \$w10,\$w11,0x3f +[0-9a-f]+ <[^>]*> 5a8e 6b1a bneg\.b \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 5ab1 83da bneg\.h \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 5ad4 9c9a bneg\.w \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 5af7 b55a bneg\.d \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 5af0 ce12 bnegi\.b \$w24,\$w25,0x0 +[0-9a-f]+ <[^>]*> 5af7 de92 bnegi\.b \$w26,\$w27,0x7 +[0-9a-f]+ <[^>]*> 5ae0 ef12 bnegi\.h \$w28,\$w29,0x0 +[0-9a-f]+ <[^>]*> 5aef ff92 bnegi\.h \$w30,\$w31,0xf +[0-9a-f]+ <[^>]*> 5ac0 0812 bnegi\.w \$w0,\$w1,0x0 +[0-9a-f]+ <[^>]*> 5adf 1892 bnegi\.w \$w2,\$w3,0x1f +[0-9a-f]+ <[^>]*> 5a80 2912 bnegi\.d \$w4,\$w5,0x0 +[0-9a-f]+ <[^>]*> 5abf 3992 bnegi\.d \$w6,\$w7,0x3f +[0-9a-f]+ <[^>]*> 5b0a 4a1a binsl\.b \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 5b2d 62da binsl\.h \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 5b50 7b9a binsl\.w \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 5b73 945a binsl\.d \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 5b70 ad12 binsli\.b \$w20,\$w21,0x0 +[0-9a-f]+ <[^>]*> 5b77 bd92 binsli\.b \$w22,\$w23,0x7 +[0-9a-f]+ <[^>]*> 5b60 ce12 binsli\.h \$w24,\$w25,0x0 +[0-9a-f]+ <[^>]*> 5b6f de92 binsli\.h \$w26,\$w27,0xf +[0-9a-f]+ <[^>]*> 5b40 ef12 binsli\.w \$w28,\$w29,0x0 +[0-9a-f]+ <[^>]*> 5b5f ff92 binsli\.w \$w30,\$w31,0x1f +[0-9a-f]+ <[^>]*> 5b00 0812 binsli\.d \$w0,\$w1,0x0 +[0-9a-f]+ <[^>]*> 5b3f 1892 binsli\.d \$w2,\$w3,0x3f +[0-9a-f]+ <[^>]*> 5b86 291a binsr\.b \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 5ba9 41da binsr\.h \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 5bcc 5a9a binsr\.w \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 5bef 735a binsr\.d \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 5bf0 8c12 binsri\.b \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 5bf7 9c92 binsri\.b \$w18,\$w19,0x7 +[0-9a-f]+ <[^>]*> 5be0 ad12 binsri\.h \$w20,\$w21,0x0 +[0-9a-f]+ <[^>]*> 5bef bd92 binsri\.h \$w22,\$w23,0xf +[0-9a-f]+ <[^>]*> 5bc0 ce12 binsri\.w \$w24,\$w25,0x0 +[0-9a-f]+ <[^>]*> 5bdf de92 binsri\.w \$w26,\$w27,0x1f +[0-9a-f]+ <[^>]*> 5b80 ef12 binsri\.d \$w28,\$w29,0x0 +[0-9a-f]+ <[^>]*> 5bbf ff92 binsri\.d \$w30,\$w31,0x3f +[0-9a-f]+ <[^>]*> 5802 082a addv\.b \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5825 20ea addv\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 5848 39aa addv\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 586b 526a addv\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 5800 6b29 addvi\.b \$w12,\$w13,0 +[0-9a-f]+ <[^>]*> 581f 7ba9 addvi\.b \$w14,\$w15,31 +[0-9a-f]+ <[^>]*> 5820 8c29 addvi\.h \$w16,\$w17,0 +[0-9a-f]+ <[^>]*> 583f 9ca9 addvi\.h \$w18,\$w19,31 +[0-9a-f]+ <[^>]*> 5840 ad29 addvi\.w \$w20,\$w21,0 +[0-9a-f]+ <[^>]*> 585f bda9 addvi\.w \$w22,\$w23,31 +[0-9a-f]+ <[^>]*> 5860 ce29 addvi\.d \$w24,\$w25,0 +[0-9a-f]+ <[^>]*> 587f dea9 addvi\.d \$w26,\$w27,31 +[0-9a-f]+ <[^>]*> 589e ef2a subv\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 58a1 07ea subv\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 58c4 18aa subv\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 58e7 316a subv\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 5880 4a29 subvi\.b \$w8,\$w9,0 +[0-9a-f]+ <[^>]*> 589f 5aa9 subvi\.b \$w10,\$w11,31 +[0-9a-f]+ <[^>]*> 58a0 6b29 subvi\.h \$w12,\$w13,0 +[0-9a-f]+ <[^>]*> 58bf 7ba9 subvi\.h \$w14,\$w15,31 +[0-9a-f]+ <[^>]*> 58c0 8c29 subvi\.w \$w16,\$w17,0 +[0-9a-f]+ <[^>]*> 58df 9ca9 subvi\.w \$w18,\$w19,31 +[0-9a-f]+ <[^>]*> 58e0 ad29 subvi\.d \$w20,\$w21,0 +[0-9a-f]+ <[^>]*> 58ff bda9 subvi\.d \$w22,\$w23,31 +[0-9a-f]+ <[^>]*> 591a ce2a max_s\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 593d e6ea max_s\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 5940 ffaa max_s\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 5963 106a max_s\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 5910 2929 maxi_s\.b \$w4,\$w5,-16 +[0-9a-f]+ <[^>]*> 590f 39a9 maxi_s\.b \$w6,\$w7,15 +[0-9a-f]+ <[^>]*> 5930 4a29 maxi_s\.h \$w8,\$w9,-16 +[0-9a-f]+ <[^>]*> 592f 5aa9 maxi_s\.h \$w10,\$w11,15 +[0-9a-f]+ <[^>]*> 5950 6b29 maxi_s\.w \$w12,\$w13,-16 +[0-9a-f]+ <[^>]*> 594f 7ba9 maxi_s\.w \$w14,\$w15,15 +[0-9a-f]+ <[^>]*> 5970 8c29 maxi_s\.d \$w16,\$w17,-16 +[0-9a-f]+ <[^>]*> 596f 9ca9 maxi_s\.d \$w18,\$w19,15 +[0-9a-f]+ <[^>]*> 5996 ad2a max_u\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 59b9 c5ea max_u\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 59dc deaa max_u\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 59ff f76a max_u\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 5980 0829 maxi_u\.b \$w0,\$w1,0 +[0-9a-f]+ <[^>]*> 599f 18a9 maxi_u\.b \$w2,\$w3,31 +[0-9a-f]+ <[^>]*> 59a0 2929 maxi_u\.h \$w4,\$w5,0 +[0-9a-f]+ <[^>]*> 59bf 39a9 maxi_u\.h \$w6,\$w7,31 +[0-9a-f]+ <[^>]*> 59c0 4a29 maxi_u\.w \$w8,\$w9,0 +[0-9a-f]+ <[^>]*> 59df 5aa9 maxi_u\.w \$w10,\$w11,31 +[0-9a-f]+ <[^>]*> 59e0 6b29 maxi_u\.d \$w12,\$w13,0 +[0-9a-f]+ <[^>]*> 59ff 7ba9 maxi_u\.d \$w14,\$w15,31 +[0-9a-f]+ <[^>]*> 5a12 8c2a min_s\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 5a35 a4ea min_s\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 5a58 bdaa min_s\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 5a7b d66a min_s\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 5a10 ef29 mini_s\.b \$w28,\$w29,-16 +[0-9a-f]+ <[^>]*> 5a0f ffa9 mini_s\.b \$w30,\$w31,15 +[0-9a-f]+ <[^>]*> 5a30 0829 mini_s\.h \$w0,\$w1,-16 +[0-9a-f]+ <[^>]*> 5a2f 18a9 mini_s\.h \$w2,\$w3,15 +[0-9a-f]+ <[^>]*> 5a50 2929 mini_s\.w \$w4,\$w5,-16 +[0-9a-f]+ <[^>]*> 5a4f 39a9 mini_s\.w \$w6,\$w7,15 +[0-9a-f]+ <[^>]*> 5a70 4a29 mini_s\.d \$w8,\$w9,-16 +[0-9a-f]+ <[^>]*> 5a6f 5aa9 mini_s\.d \$w10,\$w11,15 +[0-9a-f]+ <[^>]*> 5a8e 6b2a min_u\.b \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 5ab1 83ea min_u\.h \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 5ad4 9caa min_u\.w \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 5af7 b56a min_u\.d \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 5a80 ce29 mini_u\.b \$w24,\$w25,0 +[0-9a-f]+ <[^>]*> 5a9f dea9 mini_u\.b \$w26,\$w27,31 +[0-9a-f]+ <[^>]*> 5aa0 ef29 mini_u\.h \$w28,\$w29,0 +[0-9a-f]+ <[^>]*> 5abf ffa9 mini_u\.h \$w30,\$w31,31 +[0-9a-f]+ <[^>]*> 5ac0 0829 mini_u\.w \$w0,\$w1,0 +[0-9a-f]+ <[^>]*> 5adf 18a9 mini_u\.w \$w2,\$w3,31 +[0-9a-f]+ <[^>]*> 5ae0 2929 mini_u\.d \$w4,\$w5,0 +[0-9a-f]+ <[^>]*> 5aff 39a9 mini_u\.d \$w6,\$w7,31 +[0-9a-f]+ <[^>]*> 5b0a 4a2a max_a\.b \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 5b2d 62ea max_a\.h \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 5b50 7baa max_a\.w \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 5b73 946a max_a\.d \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 5b96 ad2a min_a\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 5bb9 c5ea min_a\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 5bdc deaa min_a\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 5bff f76a min_a\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 5802 083a ceq\.b \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5825 20fa ceq\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 5848 39ba ceq\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 586b 527a ceq\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 5810 6b39 ceqi\.b \$w12,\$w13,-16 +[0-9a-f]+ <[^>]*> 580f 7bb9 ceqi\.b \$w14,\$w15,15 +[0-9a-f]+ <[^>]*> 5830 8c39 ceqi\.h \$w16,\$w17,-16 +[0-9a-f]+ <[^>]*> 582f 9cb9 ceqi\.h \$w18,\$w19,15 +[0-9a-f]+ <[^>]*> 5850 ad39 ceqi\.w \$w20,\$w21,-16 +[0-9a-f]+ <[^>]*> 584f bdb9 ceqi\.w \$w22,\$w23,15 +[0-9a-f]+ <[^>]*> 5870 ce39 ceqi\.d \$w24,\$w25,-16 +[0-9a-f]+ <[^>]*> 586f deb9 ceqi\.d \$w26,\$w27,15 +[0-9a-f]+ <[^>]*> 591e ef3a clt_s\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 5921 07fa clt_s\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 5944 18ba clt_s\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 5967 317a clt_s\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 5910 4a39 clti_s\.b \$w8,\$w9,-16 +[0-9a-f]+ <[^>]*> 590f 5ab9 clti_s\.b \$w10,\$w11,15 +[0-9a-f]+ <[^>]*> 5930 6b39 clti_s\.h \$w12,\$w13,-16 +[0-9a-f]+ <[^>]*> 592f 7bb9 clti_s\.h \$w14,\$w15,15 +[0-9a-f]+ <[^>]*> 5950 8c39 clti_s\.w \$w16,\$w17,-16 +[0-9a-f]+ <[^>]*> 594f 9cb9 clti_s\.w \$w18,\$w19,15 +[0-9a-f]+ <[^>]*> 5970 ad39 clti_s\.d \$w20,\$w21,-16 +[0-9a-f]+ <[^>]*> 596f bdb9 clti_s\.d \$w22,\$w23,15 +[0-9a-f]+ <[^>]*> 599a ce3a clt_u\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 59bd e6fa clt_u\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 59c0 ffba clt_u\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 59e3 107a clt_u\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 5980 2939 clti_u\.b \$w4,\$w5,0 +[0-9a-f]+ <[^>]*> 599f 39b9 clti_u\.b \$w6,\$w7,31 +[0-9a-f]+ <[^>]*> 59a0 4a39 clti_u\.h \$w8,\$w9,0 +[0-9a-f]+ <[^>]*> 59bf 5ab9 clti_u\.h \$w10,\$w11,31 +[0-9a-f]+ <[^>]*> 59c0 6b39 clti_u\.w \$w12,\$w13,0 +[0-9a-f]+ <[^>]*> 59df 7bb9 clti_u\.w \$w14,\$w15,31 +[0-9a-f]+ <[^>]*> 59e0 8c39 clti_u\.d \$w16,\$w17,0 +[0-9a-f]+ <[^>]*> 59ff 9cb9 clti_u\.d \$w18,\$w19,31 +[0-9a-f]+ <[^>]*> 5a16 ad3a cle_s\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 5a39 c5fa cle_s\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 5a5c deba cle_s\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 5a7f f77a cle_s\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 5a10 0839 clei_s\.b \$w0,\$w1,-16 +[0-9a-f]+ <[^>]*> 5a0f 18b9 clei_s\.b \$w2,\$w3,15 +[0-9a-f]+ <[^>]*> 5a30 2939 clei_s\.h \$w4,\$w5,-16 +[0-9a-f]+ <[^>]*> 5a2f 39b9 clei_s\.h \$w6,\$w7,15 +[0-9a-f]+ <[^>]*> 5a50 4a39 clei_s\.w \$w8,\$w9,-16 +[0-9a-f]+ <[^>]*> 5a4f 5ab9 clei_s\.w \$w10,\$w11,15 +[0-9a-f]+ <[^>]*> 5a70 6b39 clei_s\.d \$w12,\$w13,-16 +[0-9a-f]+ <[^>]*> 5a6f 7bb9 clei_s\.d \$w14,\$w15,15 +[0-9a-f]+ <[^>]*> 5a92 8c3a cle_u\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 5ab5 a4fa cle_u\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 5ad8 bdba cle_u\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 5afb d67a cle_u\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 5a80 ef39 clei_u\.b \$w28,\$w29,0 +[0-9a-f]+ <[^>]*> 5a9f ffb9 clei_u\.b \$w30,\$w31,31 +[0-9a-f]+ <[^>]*> 5aa0 0839 clei_u\.h \$w0,\$w1,0 +[0-9a-f]+ <[^>]*> 5abf 18b9 clei_u\.h \$w2,\$w3,31 +[0-9a-f]+ <[^>]*> 5ac0 2939 clei_u\.w \$w4,\$w5,0 +[0-9a-f]+ <[^>]*> 5adf 39b9 clei_u\.w \$w6,\$w7,31 +[0-9a-f]+ <[^>]*> 5ae0 4a39 clei_u\.d \$w8,\$w9,0 +[0-9a-f]+ <[^>]*> 5aff 5ab9 clei_u\.d \$w10,\$w11,31 +[0-9a-f]+ <[^>]*> 5a00 6b07 ld\.b \$w12,-512\(t5\) +[0-9a-f]+ <[^>]*> 59ff 7b87 ld\.b \$w14,511\(t7\) +[0-9a-f]+ <[^>]*> 5a00 8c17 ld\.h \$w16,-1024\(s1\) +[0-9a-f]+ <[^>]*> 59ff 9c97 ld\.h \$w18,1022\(s3\) +[0-9a-f]+ <[^>]*> 5a00 ad27 ld\.w \$w20,-2048\(s5\) +[0-9a-f]+ <[^>]*> 59ff bda7 ld\.w \$w22,2044\(s7\) +[0-9a-f]+ <[^>]*> 5a00 ce37 ld\.d \$w24,-4096\(t9\) +[0-9a-f]+ <[^>]*> 59ff deb7 ld\.d \$w26,4088\(k1\) +[0-9a-f]+ <[^>]*> 5a00 ef0f st\.b \$w28,-512\(sp\) +[0-9a-f]+ <[^>]*> 59ff ff8f st\.b \$w30,511\(ra\) +[0-9a-f]+ <[^>]*> 5a00 081f st\.h \$w0,-1024\(at\) +[0-9a-f]+ <[^>]*> 59ff 189f st\.h \$w2,1022\(v1\) +[0-9a-f]+ <[^>]*> 5a00 292f st\.w \$w4,-2048\(a1\) +[0-9a-f]+ <[^>]*> 59ff 39af st\.w \$w6,2044\(a3\) +[0-9a-f]+ <[^>]*> 5a00 4a3f st\.d \$w8,-4096\(t1\) +[0-9a-f]+ <[^>]*> 59ff 5abf st\.d \$w10,4088\(t3\) +[0-9a-f]+ <[^>]*> 5870 6b22 sat_s\.b \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 5877 7ba2 sat_s\.b \$w14,\$w15,0x7 +[0-9a-f]+ <[^>]*> 5860 8c22 sat_s\.h \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 586f 9ca2 sat_s\.h \$w18,\$w19,0xf +[0-9a-f]+ <[^>]*> 5840 ad22 sat_s\.w \$w20,\$w21,0x0 +[0-9a-f]+ <[^>]*> 585f bda2 sat_s\.w \$w22,\$w23,0x1f +[0-9a-f]+ <[^>]*> 5800 ce22 sat_s\.d \$w24,\$w25,0x0 +[0-9a-f]+ <[^>]*> 583f dea2 sat_s\.d \$w26,\$w27,0x3f +[0-9a-f]+ <[^>]*> 58f0 ef22 sat_u\.b \$w28,\$w29,0x0 +[0-9a-f]+ <[^>]*> 58f7 ffa2 sat_u\.b \$w30,\$w31,0x7 +[0-9a-f]+ <[^>]*> 58e0 0822 sat_u\.h \$w0,\$w1,0x0 +[0-9a-f]+ <[^>]*> 58ef 18a2 sat_u\.h \$w2,\$w3,0xf +[0-9a-f]+ <[^>]*> 58c0 2922 sat_u\.w \$w4,\$w5,0x0 +[0-9a-f]+ <[^>]*> 58df 39a2 sat_u\.w \$w6,\$w7,0x1f +[0-9a-f]+ <[^>]*> 5880 4a22 sat_u\.d \$w8,\$w9,0x0 +[0-9a-f]+ <[^>]*> 58bf 5aa2 sat_u\.d \$w10,\$w11,0x3f +[0-9a-f]+ <[^>]*> 580e 6b03 add_a\.b \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 5831 83c3 add_a\.h \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 5854 9c83 add_a\.w \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 5877 b543 add_a\.d \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 589a ce03 adds_a\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 58bd e6c3 adds_a\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 58c0 ff83 adds_a\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 58e3 1043 adds_a\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 5906 2903 adds_s\.b \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 5929 41c3 adds_s\.h \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 594c 5a83 adds_s\.w \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 596f 7343 adds_s\.d \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 5992 8c03 adds_u\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 59b5 a4c3 adds_u\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 59d8 bd83 adds_u\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 59fb d643 adds_u\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 5a1e ef03 ave_s\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 5a21 07c3 ave_s\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 5a44 1883 ave_s\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 5a67 3143 ave_s\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 5a8a 4a03 ave_u\.b \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 5aad 62c3 ave_u\.h \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 5ad0 7b83 ave_u\.w \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 5af3 9443 ave_u\.d \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 5b16 ad03 aver_s\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 5b39 c5c3 aver_s\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 5b5c de83 aver_s\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 5b7f f743 aver_s\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 5b82 0803 aver_u\.b \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5ba5 20c3 aver_u\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 5bc8 3983 aver_u\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 5beb 5243 aver_u\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 580e 6b13 subs_s\.b \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 5831 83d3 subs_s\.h \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 5854 9c93 subs_s\.w \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 5877 b553 subs_s\.d \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 589a ce13 subs_u\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 58bd e6d3 subs_u\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 58c0 ff93 subs_u\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 58e3 1053 subs_u\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 5906 2913 subsus_u\.b \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 5929 41d3 subsus_u\.h \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 594c 5a93 subsus_u\.w \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 596f 7353 subsus_u\.d \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 5992 8c13 subsuu_s\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 59b5 a4d3 subsuu_s\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 59d8 bd93 subsuu_s\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 59fb d653 subsuu_s\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 5a1e ef13 asub_s\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 5a21 07d3 asub_s\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 5a44 1893 asub_s\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 5a67 3153 asub_s\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 5a8a 4a13 asub_u\.b \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 5aad 62d3 asub_u\.h \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 5ad0 7b93 asub_u\.w \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 5af3 9453 asub_u\.d \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 5816 ad23 mulv\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 5839 c5e3 mulv\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 585c dea3 mulv\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 587f f763 mulv\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 5882 0823 maddv\.b \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 58a5 20e3 maddv\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 58c8 39a3 maddv\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 58eb 5263 maddv\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 590e 6b23 msubv\.b \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 5931 83e3 msubv\.h \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 5954 9ca3 msubv\.w \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 5977 b563 msubv\.d \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 5a1a ce23 div_s\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 5a3d e6e3 div_s\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 5a40 ffa3 div_s\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 5a63 1063 div_s\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 5a86 2923 div_u\.b \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 5aa9 41e3 div_u\.h \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 5acc 5aa3 div_u\.w \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 5aef 7363 div_u\.d \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 5b12 8c23 mod_s\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 5b35 a4e3 mod_s\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 5b58 bda3 mod_s\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 5b7b d663 mod_s\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 5b9e ef23 mod_u\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 5ba1 07e3 mod_u\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 5bc4 18a3 mod_u\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 5be7 3163 mod_u\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 582a 4a33 dotp_s\.h \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 584d 62f3 dotp_s\.w \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 5870 7bb3 dotp_s\.d \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 58b3 9473 dotp_u\.h \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 58d6 ad33 dotp_u\.w \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 58f9 c5f3 dotp_u\.d \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 593c deb3 dpadd_s\.h \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 595f f773 dpadd_s\.w \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 5962 0833 dpadd_s\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 59a5 20f3 dpadd_u\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 59c8 39b3 dpadd_u\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 59eb 5273 dpadd_u\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 5a2e 6b33 dpsub_s\.h \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 5a51 83f3 dpsub_s\.w \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 5a74 9cb3 dpsub_s\.d \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 5ab7 b573 dpsub_u\.h \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 5ada ce33 dpsub_u\.w \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 5afd e6f3 dpsub_u\.d \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 5800 ff8b sld\.b \$w30,\$w31\[zero\] +[0-9a-f]+ <[^>]*> 5823 104b sld\.h \$w1,\$w2\[v1\] +[0-9a-f]+ <[^>]*> 5846 290b sld\.w \$w4,\$w5\[a2\] +[0-9a-f]+ <[^>]*> 5869 41cb sld\.d \$w7,\$w8\[t1\] +[0-9a-f]+ <[^>]*> 5800 5a96 sldi\.b \$w10,\$w11\[0\] +[0-9a-f]+ <[^>]*> 580f 6b16 sldi\.b \$w12,\$w13\[15\] +[0-9a-f]+ <[^>]*> 5820 7b96 sldi\.h \$w14,\$w15\[0\] +[0-9a-f]+ <[^>]*> 5827 8c16 sldi\.h \$w16,\$w17\[7\] +[0-9a-f]+ <[^>]*> 5830 9c96 sldi\.w \$w18,\$w19\[0\] +[0-9a-f]+ <[^>]*> 5833 ad16 sldi\.w \$w20,\$w21\[3\] +[0-9a-f]+ <[^>]*> 5838 bd96 sldi\.d \$w22,\$w23\[0\] +[0-9a-f]+ <[^>]*> 5839 ce16 sldi\.d \$w24,\$w25\[1\] +[0-9a-f]+ <[^>]*> 589c de8b splat\.b \$w26,\$w27\[gp\] +[0-9a-f]+ <[^>]*> 58bf f74b splat\.h \$w29,\$w30\[ra\] +[0-9a-f]+ <[^>]*> 58c2 080b splat\.w \$w0,\$w1\[v0\] +[0-9a-f]+ <[^>]*> 58e5 20cb splat\.d \$w3,\$w4\[a1\] +[0-9a-f]+ <[^>]*> 5840 3996 splati\.b \$w6,\$w7\[0\] +[0-9a-f]+ <[^>]*> 584f 4a16 splati\.b \$w8,\$w9\[15\] +[0-9a-f]+ <[^>]*> 5860 5a96 splati\.h \$w10,\$w11\[0\] +[0-9a-f]+ <[^>]*> 5867 6b16 splati\.h \$w12,\$w13\[7\] +[0-9a-f]+ <[^>]*> 5870 7b96 splati\.w \$w14,\$w15\[0\] +[0-9a-f]+ <[^>]*> 5873 8c16 splati\.w \$w16,\$w17\[3\] +[0-9a-f]+ <[^>]*> 5878 9c96 splati\.d \$w18,\$w19\[0\] +[0-9a-f]+ <[^>]*> 5879 ad16 splati\.d \$w20,\$w21\[1\] +[0-9a-f]+ <[^>]*> 5918 bd8b pckev\.b \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 593b d64b pckev\.h \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 595e ef0b pckev\.w \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 5961 07cb pckev\.d \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 5984 188b pckod\.b \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 59a7 314b pckod\.h \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 59ca 4a0b pckod\.w \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 59ed 62cb pckod\.d \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 5a10 7b8b ilvl\.b \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 5a33 944b ilvl\.h \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 5a56 ad0b ilvl\.w \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 5a79 c5cb ilvl\.d \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 5a9c de8b ilvr\.b \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 5abf f74b ilvr\.h \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 5ac2 080b ilvr\.w \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5ae5 20cb ilvr\.d \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 5b08 398b ilvev\.b \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 5b2b 524b ilvev\.h \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 5b4e 6b0b ilvev\.w \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 5b71 83cb ilvev\.d \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 5b94 9c8b ilvod\.b \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 5bb7 b54b ilvod\.h \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 5bda ce0b ilvod\.w \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 5bfd e6cb ilvod\.d \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 5800 ff9b vshf\.b \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 5823 105b vshf\.h \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 5846 291b vshf\.w \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 5869 41db vshf\.d \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 588c 5a9b srar\.b \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 58af 735b srar\.h \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 58d2 8c1b srar\.w \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 58f5 a4db srar\.d \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 5970 bda2 srari\.b \$w22,\$w23,0x0 +[0-9a-f]+ <[^>]*> 5977 ce22 srari\.b \$w24,\$w25,0x7 +[0-9a-f]+ <[^>]*> 5960 dea2 srari\.h \$w26,\$w27,0x0 +[0-9a-f]+ <[^>]*> 596f ef22 srari\.h \$w28,\$w29,0xf +[0-9a-f]+ <[^>]*> 5940 ffa2 srari\.w \$w30,\$w31,0x0 +[0-9a-f]+ <[^>]*> 595f 0822 srari\.w \$w0,\$w1,0x1f +[0-9a-f]+ <[^>]*> 5900 18a2 srari\.d \$w2,\$w3,0x0 +[0-9a-f]+ <[^>]*> 593f 2922 srari\.d \$w4,\$w5,0x3f +[0-9a-f]+ <[^>]*> 5908 399b srlr\.b \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 592b 525b srlr\.h \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 594e 6b1b srlr\.w \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 5971 83db srlr\.d \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 59f0 9ca2 srlri\.b \$w18,\$w19,0x0 +[0-9a-f]+ <[^>]*> 59f7 ad22 srlri\.b \$w20,\$w21,0x7 +[0-9a-f]+ <[^>]*> 59e0 bda2 srlri\.h \$w22,\$w23,0x0 +[0-9a-f]+ <[^>]*> 59ef ce22 srlri\.h \$w24,\$w25,0xf +[0-9a-f]+ <[^>]*> 59c0 dea2 srlri\.w \$w26,\$w27,0x0 +[0-9a-f]+ <[^>]*> 59df ef22 srlri\.w \$w28,\$w29,0x1f +[0-9a-f]+ <[^>]*> 5980 ffa2 srlri\.d \$w30,\$w31,0x0 +[0-9a-f]+ <[^>]*> 59bf 0822 srlri\.d \$w0,\$w1,0x3f +[0-9a-f]+ <[^>]*> 5a24 189b hadd_s\.h \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 5a47 315b hadd_s\.w \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 5a6a 4a1b hadd_s\.d \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 5aad 62db hadd_u\.h \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 5ad0 7b9b hadd_u\.w \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 5af3 945b hadd_u\.d \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 5b36 ad1b hsub_s\.h \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 5b59 c5db hsub_s\.w \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 5b7c de9b hsub_s\.d \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 5bbf f75b hsub_u\.h \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 5bc2 081b hsub_u\.w \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5be5 20db hsub_u\.d \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 5808 39ae and\.v \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 5800 5241 andi\.b \$w9,\$w10,0x0 +[0-9a-f]+ <[^>]*> 58ff 62c1 andi\.b \$w11,\$w12,0xff +[0-9a-f]+ <[^>]*> 582f 736e or\.v \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 5900 8c01 ori\.b \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 59ff 9c81 ori\.b \$w18,\$w19,0xff +[0-9a-f]+ <[^>]*> 5856 ad2e nor\.v \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 5a00 c5c1 nori\.b \$w23,\$w24,0x0 +[0-9a-f]+ <[^>]*> 5aff d641 nori\.b \$w25,\$w26,0xff +[0-9a-f]+ <[^>]*> 587d e6ee xor\.v \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 5b00 ff81 xori\.b \$w30,\$w31,0x0 +[0-9a-f]+ <[^>]*> 5bff 0801 xori\.b \$w0,\$w1,0xff +[0-9a-f]+ <[^>]*> 5884 18ae bmnz\.v \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 5800 3151 bmnzi\.b \$w5,\$w6,0x0 +[0-9a-f]+ <[^>]*> 58ff 41d1 bmnzi\.b \$w7,\$w8,0xff +[0-9a-f]+ <[^>]*> 58ab 526e bmz\.v \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 5900 6b11 bmzi\.b \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 59ff 7b91 bmzi\.b \$w14,\$w15,0xff +[0-9a-f]+ <[^>]*> 58d2 8c2e bsel\.v \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 5a00 a4d1 bseli\.b \$w19,\$w20,0x0 +[0-9a-f]+ <[^>]*> 5aff b551 bseli\.b \$w21,\$w22,0xff +[0-9a-f]+ <[^>]*> 5800 c5e1 shf\.b \$w23,\$w24,0x0 +[0-9a-f]+ <[^>]*> 58ff d661 shf\.b \$w25,\$w26,0xff +[0-9a-f]+ <[^>]*> 5900 e6e1 shf\.h \$w27,\$w28,0x0 +[0-9a-f]+ <[^>]*> 59ff f761 shf\.h \$w29,\$w30,0xff +[0-9a-f]+ <[^>]*> 5a00 07e1 shf\.w \$w31,\$w0,0x0 +[0-9a-f]+ <[^>]*> 5aff 1061 shf\.w \$w1,\$w2,0xff +[0-9a-f]+ <[^>]*> 81e3 8000 bnz\.v \$w3,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 81e4 7fff bnz\.v \$w4,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 81e5 fffe bnz\.v \$w5,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 81e6 fffe bnz\.v \$w6,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8167 8000 bz\.v \$w7,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8168 7fff bz\.v \$w8,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8169 fffe bz\.v \$w9,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 816a fffe bz\.v \$w10,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 5b00 62ee fill\.b \$w11,t4 +[0-9a-f]+ <[^>]*> 5b01 736e fill\.h \$w13,t6 +[0-9a-f]+ <[^>]*> 5b02 83ee fill\.w \$w15,s0 +[0-9a-f]+ <[^>]*> 5b04 a4ee pcnt\.b \$w19,\$w20 +[0-9a-f]+ <[^>]*> 5b05 b56e pcnt\.h \$w21,\$w22 +[0-9a-f]+ <[^>]*> 5b06 c5ee pcnt\.w \$w23,\$w24 +[0-9a-f]+ <[^>]*> 5b07 d66e pcnt\.d \$w25,\$w26 +[0-9a-f]+ <[^>]*> 5b08 e6ee nloc\.b \$w27,\$w28 +[0-9a-f]+ <[^>]*> 5b09 f76e nloc\.h \$w29,\$w30 +[0-9a-f]+ <[^>]*> 5b0a 07ee nloc\.w \$w31,\$w0 +[0-9a-f]+ <[^>]*> 5b0b 106e nloc\.d \$w1,\$w2 +[0-9a-f]+ <[^>]*> 5b0c 20ee nlzc\.b \$w3,\$w4 +[0-9a-f]+ <[^>]*> 5b0d 316e nlzc\.h \$w5,\$w6 +[0-9a-f]+ <[^>]*> 5b0e 41ee nlzc\.w \$w7,\$w8 +[0-9a-f]+ <[^>]*> 5b0f 526e nlzc\.d \$w9,\$w10 +[0-9a-f]+ <[^>]*> 5880 62d6 copy_s\.b t3,\$w12\[0\] +[0-9a-f]+ <[^>]*> 588f 7356 copy_s\.b t5,\$w14\[15\] +[0-9a-f]+ <[^>]*> 58a0 83d6 copy_s\.h t7,\$w16\[0\] +[0-9a-f]+ <[^>]*> 58a7 9456 copy_s\.h s1,\$w18\[7\] +[0-9a-f]+ <[^>]*> 58b0 a4d6 copy_s\.w s3,\$w20\[0\] +[0-9a-f]+ <[^>]*> 58b3 b556 copy_s\.w s5,\$w22\[3\] +[0-9a-f]+ <[^>]*> 58c0 e6d6 copy_u\.b k1,\$w28\[0\] +[0-9a-f]+ <[^>]*> 58cf f756 copy_u\.b sp,\$w30\[15\] +[0-9a-f]+ <[^>]*> 58e0 07d6 copy_u\.h ra,\$w0\[0\] +[0-9a-f]+ <[^>]*> 58e7 1056 copy_u\.h at,\$w2\[7\] +[0-9a-f]+ <[^>]*> 58f0 20d6 copy_u\.w v1,\$w4\[0\] +[0-9a-f]+ <[^>]*> 58f3 3156 copy_u\.w a1,\$w6\[3\] +[0-9a-f]+ <[^>]*> 5900 62d6 insert\.b \$w11\[0\],t4 +[0-9a-f]+ <[^>]*> 590f 7356 insert\.b \$w13\[15\],t6 +[0-9a-f]+ <[^>]*> 5920 83d6 insert\.h \$w15\[0\],s0 +[0-9a-f]+ <[^>]*> 5927 9456 insert\.h \$w17\[7\],s2 +[0-9a-f]+ <[^>]*> 5930 a4d6 insert\.w \$w19\[0\],s4 +[0-9a-f]+ <[^>]*> 5933 b556 insert\.w \$w21\[3\],s6 +[0-9a-f]+ <[^>]*> 5940 e6d6 insve\.b \$w27\[0\],\$w28\[0\] +[0-9a-f]+ <[^>]*> 594f f756 insve\.b \$w29\[15\],\$w30\[0\] +[0-9a-f]+ <[^>]*> 5960 07d6 insve\.h \$w31\[0\],\$w0\[0\] +[0-9a-f]+ <[^>]*> 5967 1056 insve\.h \$w1\[7\],\$w2\[0\] +[0-9a-f]+ <[^>]*> 5970 20d6 insve\.w \$w3\[0\],\$w4\[0\] +[0-9a-f]+ <[^>]*> 5973 3156 insve\.w \$w5\[3\],\$w6\[0\] +[0-9a-f]+ <[^>]*> 5978 41d6 insve\.d \$w7\[0\],\$w8\[0\] +[0-9a-f]+ <[^>]*> 5979 5256 insve\.d \$w9\[1\],\$w10\[0\] +[0-9a-f]+ <[^>]*> 838b 8000 bnz\.b \$w11,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 838c 7fff bnz\.b \$w12,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 838d fffe bnz\.b \$w13,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 838e fffe bnz\.b \$w14,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83af 8000 bnz\.h \$w15,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83b0 7fff bnz\.h \$w16,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83b1 fffe bnz\.h \$w17,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83b2 fffe bnz\.h \$w18,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83d3 8000 bnz\.w \$w19,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83d4 7fff bnz\.w \$w20,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83d5 fffe bnz\.w \$w21,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83d6 fffe bnz\.w \$w22,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83f7 8000 bnz\.d \$w23,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83f8 7fff bnz\.d \$w24,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83f9 fffe bnz\.d \$w25,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 83fa fffe bnz\.d \$w26,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 831b 8000 bz\.b \$w27,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 831c 7fff bz\.b \$w28,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 831d fffe bz\.b \$w29,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 831e fffe bz\.b \$w30,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 833f 8000 bz\.h \$w31,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8320 7fff bz\.h \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8321 fffe bz\.h \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8322 fffe bz\.h \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8343 8000 bz\.w \$w3,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8344 7fff bz\.w \$w4,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8345 fffe bz\.w \$w5,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8346 fffe bz\.w \$w6,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8367 8000 bz\.d \$w7,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8368 7fff bz\.d \$w8,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 8369 fffe bz\.d \$w9,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .* +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 836a fffe bz\.d \$w10,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label +[0-9a-f]+ <[^>]*> 0c00 nop +[0-9a-f]+ <[^>]*> 5b10 02f9 ldi\.b \$w11,-512 +[0-9a-f]+ <[^>]*> 5b0f fb39 ldi\.b \$w12,511 +[0-9a-f]+ <[^>]*> 5b30 0379 ldi\.h \$w13,-512 +[0-9a-f]+ <[^>]*> 5b2f fbb9 ldi\.h \$w14,511 +[0-9a-f]+ <[^>]*> 5b50 03f9 ldi\.w \$w15,-512 +[0-9a-f]+ <[^>]*> 5b4f fc39 ldi\.w \$w16,511 +[0-9a-f]+ <[^>]*> 5b70 0479 ldi\.d \$w17,-512 +[0-9a-f]+ <[^>]*> 5b6f fcb9 ldi\.d \$w18,511 +[0-9a-f]+ <[^>]*> 5815 a4e6 fcaf\.w \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 5838 bda6 fcaf\.d \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 585b d666 fcun\.w \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 587e ef26 fcun\.d \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 5881 07e6 fceq\.w \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 58a4 18a6 fceq\.d \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 58c7 3166 fcueq\.w \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 58ea 4a26 fcueq\.d \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 590d 62e6 fclt\.w \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 5930 7ba6 fclt\.d \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 5953 9466 fcult\.w \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 5976 ad26 fcult\.d \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 5999 c5e6 fcle\.w \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 59bc dea6 fcle\.d \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 59df f766 fcule\.w \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 59e2 0826 fcule\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5a05 20e6 fsaf\.w \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 5a28 39a6 fsaf\.d \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 5a4b 5266 fsun\.w \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 5a6e 6b26 fsun\.d \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 5a91 83e6 fseq\.w \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 5ab4 9ca6 fseq\.d \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 5ad7 b566 fsueq\.w \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 5afa ce26 fsueq\.d \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 5b1d e6e6 fslt\.w \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 5b20 ffa6 fslt\.d \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 5b43 1066 fsult\.w \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 5b66 2926 fsult\.d \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 5b89 41e6 fsle\.w \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 5bac 5aa6 fsle\.d \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 5bcf 7366 fsule\.w \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 5bf2 8c26 fsule\.d \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 5815 a4f6 fadd\.w \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 5838 bdb6 fadd\.d \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 585b d676 fsub\.w \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 587e ef36 fsub\.d \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 5881 07f6 fmul\.w \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 58a4 18b6 fmul\.d \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 58c7 3176 fdiv\.w \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 58ea 4a36 fdiv\.d \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 590d 62f6 fmadd\.w \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 5930 7bb6 fmadd\.d \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 5953 9476 fmsub\.w \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 5976 ad36 fmsub\.d \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 59d9 c5f6 fexp2\.w \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 59fc deb6 fexp2\.d \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 5a1f f776 fexdo\.h \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 5a22 0836 fexdo\.w \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5a85 20f6 ftq\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 5aa8 39b6 ftq\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 5b0b 5276 fmin\.w \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 5b2e 6b36 fmin\.d \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 5b51 83f6 fmin_a\.w \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 5b74 9cb6 fmin_a\.d \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 5b97 b576 fmax\.w \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 5bba ce36 fmax\.d \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 5bdd e6f6 fmax_a\.w \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 5be0 ffb6 fmax_a\.d \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 5843 104e fcor\.w \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 5866 290e fcor\.d \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 5889 41ce fcune\.w \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 58ac 5a8e fcune\.d \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 58cf 734e fcne\.w \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 58f2 8c0e fcne\.d \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 5915 a4ce mul_q\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 5938 bd8e mul_q\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 595b d64e madd_q\.h \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 597e ef0e madd_q\.w \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 5981 07ce msub_q\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 59a4 188e msub_q\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 5a47 314e fsor\.w \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 5a6a 4a0e fsor\.d \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 5a8d 62ce fsune\.w \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 5ab0 7b8e fsune\.d \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 5ad3 944e fsne\.w \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 5af6 ad0e fsne\.d \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 5b19 c5ce mulr_q\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 5b3c de8e mulr_q\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 5b5f f74e maddr_q\.h \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 5b62 080e maddr_q\.w \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 5b85 20ce msubr_q\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 5ba8 398e msubr_q\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 5b20 526e fclass\.w \$w9,\$w10 +[0-9a-f]+ <[^>]*> 5b21 62ee fclass\.d \$w11,\$w12 +[0-9a-f]+ <[^>]*> 5b22 736e ftrunc_s\.w \$w13,\$w14 +[0-9a-f]+ <[^>]*> 5b23 83ee ftrunc_s\.d \$w15,\$w16 +[0-9a-f]+ <[^>]*> 5b24 946e ftrunc_u\.w \$w17,\$w18 +[0-9a-f]+ <[^>]*> 5b25 a4ee ftrunc_u\.d \$w19,\$w20 +[0-9a-f]+ <[^>]*> 5b26 b56e fsqrt\.w \$w21,\$w22 +[0-9a-f]+ <[^>]*> 5b27 c5ee fsqrt\.d \$w23,\$w24 +[0-9a-f]+ <[^>]*> 5b28 d66e frsqrt\.w \$w25,\$w26 +[0-9a-f]+ <[^>]*> 5b29 e6ee frsqrt\.d \$w27,\$w28 +[0-9a-f]+ <[^>]*> 5b2a f76e frcp\.w \$w29,\$w30 +[0-9a-f]+ <[^>]*> 5b2b 07ee frcp\.d \$w31,\$w0 +[0-9a-f]+ <[^>]*> 5b2c 106e frint\.w \$w1,\$w2 +[0-9a-f]+ <[^>]*> 5b2d 20ee frint\.d \$w3,\$w4 +[0-9a-f]+ <[^>]*> 5b2e 316e flog2\.w \$w5,\$w6 +[0-9a-f]+ <[^>]*> 5b2f 41ee flog2\.d \$w7,\$w8 +[0-9a-f]+ <[^>]*> 5b30 526e fexupl\.w \$w9,\$w10 +[0-9a-f]+ <[^>]*> 5b31 62ee fexupl\.d \$w11,\$w12 +[0-9a-f]+ <[^>]*> 5b32 736e fexupr\.w \$w13,\$w14 +[0-9a-f]+ <[^>]*> 5b33 83ee fexupr\.d \$w15,\$w16 +[0-9a-f]+ <[^>]*> 5b34 946e ffql\.w \$w17,\$w18 +[0-9a-f]+ <[^>]*> 5b35 a4ee ffql\.d \$w19,\$w20 +[0-9a-f]+ <[^>]*> 5b36 b56e ffqr\.w \$w21,\$w22 +[0-9a-f]+ <[^>]*> 5b37 c5ee ffqr\.d \$w23,\$w24 +[0-9a-f]+ <[^>]*> 5b38 d66e ftint_s\.w \$w25,\$w26 +[0-9a-f]+ <[^>]*> 5b39 e6ee ftint_s\.d \$w27,\$w28 +[0-9a-f]+ <[^>]*> 5b3a f76e ftint_u\.w \$w29,\$w30 +[0-9a-f]+ <[^>]*> 5b3b 07ee ftint_u\.d \$w31,\$w0 +[0-9a-f]+ <[^>]*> 5b3c 106e ffint_s\.w \$w1,\$w2 +[0-9a-f]+ <[^>]*> 5b3d 20ee ffint_s\.d \$w3,\$w4 +[0-9a-f]+ <[^>]*> 5b3e 316e ffint_u\.w \$w5,\$w6 +[0-9a-f]+ <[^>]*> 5b3f 41ee ffint_u\.d \$w7,\$w8 +[0-9a-f]+ <[^>]*> 583e 4816 ctcmsa msa_ir,t1 +[0-9a-f]+ <[^>]*> 583e 5056 ctcmsa msa_csr,t2 +[0-9a-f]+ <[^>]*> 583e 5896 ctcmsa msa_access,t3 +[0-9a-f]+ <[^>]*> 583e 60d6 ctcmsa msa_save,t4 +[0-9a-f]+ <[^>]*> 587e 0356 cfcmsa t5,msa_ir +[0-9a-f]+ <[^>]*> 587e 0b96 cfcmsa t6,msa_csr +[0-9a-f]+ <[^>]*> 587e 13d6 cfcmsa t7,msa_access +[0-9a-f]+ <[^>]*> 587e 1c16 cfcmsa s0,msa_save +[0-9a-f]+ <[^>]*> 58be 9456 move\.v \$w17,\$w18 +[0-9a-f]+ <[^>]*> 02b4 9820 lsa s3,s4,s5,0x1 +[0-9a-f]+ <[^>]*> 0317 b0e0 lsa s6,s7,t8,0x4 + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/micromips@msa64.d b/binutils-2.24/gas/testsuite/gas/mips/micromips@msa64.d new file mode 100644 index 0000000..d8369a8 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/micromips@msa64.d @@ -0,0 +1,18 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa +#name: MSA64 instructions +#source: msa64.s +#as: -64 -mmsa + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 5b03 946e fill\.d \$w17,s2 +[0-9a-f]+ <[^>]*> 58b8 c5d6 copy_s\.d s7,\$w24\[0\] +[0-9a-f]+ <[^>]*> 58b9 d656 copy_s\.d t9,\$w26\[1\] +[0-9a-f]+ <[^>]*> 58f8 41d6 copy_u\.d a3,\$w8\[0\] +[0-9a-f]+ <[^>]*> 58f9 5256 copy_u\.d a5,\$w10\[1\] +[0-9a-f]+ <[^>]*> 5938 c5d6 insert\.d \$w23\[0\],t8 +[0-9a-f]+ <[^>]*> 5939 d656 insert\.d \$w25\[1\],k0 +[0-9a-f]+ <[^>]*> 5b7a c820 dlsa t9,k0,k1,0x1 +[0-9a-f]+ <[^>]*> 5bdd e0e0 dlsa gp,sp,s8,0x4 + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/micromips@virt64.d b/binutils-2.24/gas/testsuite/gas/mips/micromips@virt64.d index 04e6840..6813629 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/micromips@virt64.d +++ b/binutils-2.24/gas/testsuite/gas/mips/micromips@virt64.d @@ -6,8 +6,8 @@ .*: +file format .*mips.* Disassembly of section \.text: -[0-9a-f]+ <[^>]*> 587d 00e7 dmfgc0 v1,c0_taghi -[0-9a-f]+ <[^>]*> 5974 28e7 dmfgc0 a7,\$20,5 -[0-9a-f]+ <[^>]*> 5ae2 02e7 dmtgc0 s7,c0_entrylo0 -[0-9a-f]+ <[^>]*> 58ee 12e7 dmtgc0 a3,\$14,2 +[0-9a-f]+ <[^>]*> 587d 04fc dmfgc0 v1,c0_taghi +[0-9a-f]+ <[^>]*> 5974 2cfc dmfgc0 a7,\$20,5 +[0-9a-f]+ <[^>]*> 5ae2 06fc dmtgc0 s7,c0_entrylo0 +[0-9a-f]+ <[^>]*> 58ee 16fc dmtgc0 a3,\$14,2 \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mips-gp32-fp64.l b/binutils-2.24/gas/testsuite/gas/mips/mips-gp32-fp64.l index de3f3b0..82b7b17 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/mips-gp32-fp64.l +++ b/binutils-2.24/gas/testsuite/gas/mips/mips-gp32-fp64.l @@ -1,2 +1,2 @@ -Assembler messages: -Warning: -mfp64 used with a 32-bit ABI +.*Assembler messages: +.* Warning: `fp=64' used with a 32-bit ABI diff --git a/binutils-2.24/gas/testsuite/gas/mips/mips-gp64-fp32-pic.l b/binutils-2.24/gas/testsuite/gas/mips/mips-gp64-fp32-pic.l index 2d37303..a02481a 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/mips-gp64-fp32-pic.l +++ b/binutils-2.24/gas/testsuite/gas/mips/mips-gp64-fp32-pic.l @@ -1,2 +1,2 @@ -Assembler messages: -Warning: -mfp32 used with a 64-bit ABI +.*Assembler messages: +.*:16: Warning: `fp=32' used with a 64-bit ABI diff --git a/binutils-2.24/gas/testsuite/gas/mips/mips-gp64-fp32.l b/binutils-2.24/gas/testsuite/gas/mips/mips-gp64-fp32.l index e72f085..5fd9e34 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/mips-gp64-fp32.l +++ b/binutils-2.24/gas/testsuite/gas/mips/mips-gp64-fp32.l @@ -1,5 +1,5 @@ -Assembler messages: -Warning: -mfp32 used with a 64-bit ABI +.*Assembler messages: +.* Warning: `fp=32' used with a 64-bit ABI .*:92: Warning: macro instruction expanded into multiple instructions in a branch delay slot .*:96: Warning: macro instruction expanded into multiple instructions in a branch delay slot .*:100: Warning: macro instruction expanded into multiple instructions in a branch delay slot diff --git a/binutils-2.24/gas/testsuite/gas/mips/mips.exp b/binutils-2.24/gas/testsuite/gas/mips/mips.exp index 28c30d6..347bb7d 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/mips.exp +++ b/binutils-2.24/gas/testsuite/gas/mips/mips.exp @@ -87,6 +87,10 @@ # nollsc # The CPU doesn't support ll, sc, lld and scd instructions. # +# oddspreg +# The CPU has odd-numbered single-precision registers +# available and GAS enables use of them by default. +# # as_flags: The assembler flags used when assembling tests for this # architecture. # @@ -324,6 +328,9 @@ proc run_dump_test_arch { name opts arch } { if { [ string match "octeon*" $proparch ] && $proparch != "octeon" } { lappend prefixes octeon@ } + if { [ string match "mips*r6" $proparch ]} { + lappend prefixes mipsr6@ + } foreach prefix ${prefixes} { set archname ${prefix}${name} if { [file exists "$srcdir/$subdir/${archname}.d"] } { @@ -363,9 +370,25 @@ proc run_dump_test_arches { name args } { # Invoke "run_list_test" for test NAME with additional assembler options OPTS. # Add the assembler flags that are associated with architecture ARCH. proc run_list_test_arch { name opts arch } { - global subdir + global subdir srcdir set testname "MIPS $name ([concat $opts [mips_arch_displayname $arch]])" + set proparch [lindex [mips_arch_properties $arch 0] 0] + set prefixes [list ${proparch}@ ] + if { [ string match "octeon*" $proparch ] && $proparch != "octeon" } { + lappend prefixes octeon@ + } + if { [ string match "mips*r6" $proparch ]} { + lappend prefixes mipsr6@ + } + foreach prefix ${prefixes} { + set archname ${prefix}${name} + if { [file exists "$srcdir/$subdir/${archname}.l"] } { + set name $archname + break + } + } + if [catch {run_list_test \ $name \ [concat $opts [mips_arch_as_flags $arch]] \ @@ -417,6 +440,18 @@ mips_arch_create mips32r2 32 mips32 { fpisa3 fpisa4 fpisa5 ror } \ { -march=mips32r2 -mtune=mips32r2 } \ { -mmips:isa32r2 } \ { mipsisa32r2-*-* mipsisa32r2el-*-* } +mips_arch_create mips32r3 32 mips32r2 { fpisa3 fpisa4 fpisa5 ror } \ + { -march=mips32r3 -mtune=mips32r3 } \ + { -mmips:isa32r3 } \ + { mipsisa32r3-*-* mipsisa32r3el-*-* } +mips_arch_create mips32r5 32 mips32r3 { fpisa3 fpisa4 fpisa5 ror } \ + { -march=mips32r5 -mtune=mips32r5 } \ + { -mmips:isa32r5 } \ + { mipsisa32r5-*-* mipsisa32r5el-*-* } +mips_arch_create mips32r6 32 mips32r5 { fpisa3 fpisa4 fpisa5 ror } \ + { -march=mips32r6 -mtune=mips32r6 --defsym r6=} \ + { -mmips:isa32r6 } \ + { mipsisa32r6-*-* mipsisa32r6el-*-* } mips_arch_create mips64 64 mips5 { mips32 } \ { -march=mips64 -mtune=mips64 } { -mmips:isa64 } \ { mipsisa64-*-* mipsisa64el-*-* } @@ -424,10 +459,22 @@ mips_arch_create mips64r2 64 mips64 { mips32r2 ror } \ { -march=mips64r2 -mtune=mips64r2 } \ { -mmips:isa64r2 } \ { mipsisa64r2-*-* mipsisa64r2el-*-* } +mips_arch_create mips64r3 64 mips64r2 { mips32r3 ror } \ + { -march=mips64r3 -mtune=mips64r3 } \ + { -mmips:isa64r3 } \ + { mipsisa64r3-*-* mipsisa64r3el-*-* } +mips_arch_create mips64r5 64 mips64r3 { mips32r5 ror } \ + { -march=mips64r5 -mtune=mips64r5 } \ + { -mmips:isa64r5 } \ + { mipsisa64r5-*-* mipsisa64r5el-*-* } +mips_arch_create mips64r6 64 mips64r5 { mips32r6 ror } \ + { -march=mips64r6 -mtune=mips64r6 --defsym r6=} \ + { -mmips:isa64r6 } \ + { mipsisa64r6-*-* mipsisa64r6el-*-* } mips_arch_create mips16 32 {} {} \ { -march=mips1 -mips16 } { -mmips:16 } mips_arch_create micromips 64 mips64r2 {} \ - { -march=mips64 -mmicromips } {} + { -march=mips64r2 -mmicromips } {} mips_arch_create r3000 32 mips1 {} \ { -march=r3000 -mtune=r3000 } { -mmips:3000 } mips_arch_create r3900 32 mips1 { gpr_ilocks } \ @@ -437,19 +484,19 @@ mips_arch_create r4000 64 mips3 {} \ { -march=r4000 -mtune=r4000 } { -mmips:4000 } mips_arch_create vr5400 64 mips4 { ror } \ { -march=vr5400 -mtune=vr5400 } { -mmips:5400 } -mips_arch_create sb1 64 mips64 { mips3d } \ +mips_arch_create sb1 64 mips64 { mips3d oddspreg } \ { -march=sb1 -mtune=sb1 } { -mmips:sb1 } \ { mipsisa64sb1-*-* mipsisa64sb1el-*-* } -mips_arch_create octeon 64 mips64r2 {} \ +mips_arch_create octeon 64 mips64r2 { oddspreg } \ { -march=octeon -mtune=octeon } { -mmips:octeon } \ { mips64octeon*-*-* } -mips_arch_create octeonp 64 octeon {} \ +mips_arch_create octeonp 64 octeon { oddspreg } \ { -march=octeon+ -mtune=octeon+ } { -mmips:octeon+ } \ { } -mips_arch_create octeon2 64 octeonp {} \ +mips_arch_create octeon2 64 octeonp { oddspreg } \ { -march=octeon2 -mtune=octeon2 } { -mmips:octeon2 } \ { } -mips_arch_create xlr 64 mips64 {} \ +mips_arch_create xlr 64 mips64 { oddspreg } \ { -march=xlr -mtune=xlr } { -mmips:xlr } mips_arch_create r5900 64 mips3 { gpr_ilocks singlefloat nollsc } \ { -march=r5900 -mtune=r5900 } { -mmips:5900 } \ @@ -466,10 +513,14 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "vxworks1-xgot-el" } elseif { [istarget mips*-*-*] } { set addr32 [expr [istarget mipstx39*-*-*] || [istarget mips-*-linux*] || [istarget mipsel-*-linux*]] - set has_newabi [expr [istarget *-*-irix6*] || [istarget mips*-*-linux*] || [istarget mips*-sde-elf*]] + set has_newabi [expr [istarget *-*-irix6*] || [istarget mips*-*-linux*] \ + || [istarget mips*-sde-elf*] || [istarget mips*-mti-elf*] \ + || [istarget mips*-img-elf*]] if { [istarget "mips*-*-*linux*"] || [istarget "mips*-sde-elf*"] + || [istarget "mips*-mti-elf*"] + || [istarget "mips*-img-elf*"] || [istarget "mips*-*-*bsd*"] } then { set tmips "t" } else { @@ -496,7 +547,7 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test_arches "bgeu" [mips_arch_list_matching mips1] run_dump_test_arches "blt" [mips_arch_list_matching mips1] run_dump_test_arches "bltu" [mips_arch_list_matching mips1] - run_dump_test_arches "branch-likely" [mips_arch_list_matching mips2] + run_dump_test_arches "branch-likely" [mips_arch_list_matching mips2 !mips32r6] run_dump_test_arches "branch-misc-1" [mips_arch_list_matching mips1] run_dump_test_arches "branch-misc-2" [mips_arch_list_matching mips1] run_dump_test_arches "branch-misc-2pic" [mips_arch_list_matching mips1] @@ -529,6 +580,10 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "eret-1" run_dump_test "eret-2" run_dump_test "eret-3" + run_dump_test_arches "fix-rm7000-1" \ + [mips_arch_list_matching mips3 !singlefloat !mips64r6] + run_dump_test_arches "fix-rm7000-2" \ + [mips_arch_list_matching mips3 !singlefloat !mips64r6] run_dump_test_arches "24k-branch-delay-1" \ [mips_arch_list_matching mips1] run_dump_test_arches "24k-triple-stores-1" \ @@ -630,7 +685,7 @@ if { [istarget mips*-*-vxworks*] } { [mips_arch_list_matching mips3 !singlefloat] } run_dump_test_arches "ld-zero" [mips_arch_list_matching mips1] - run_dump_test_arches "ld-zero-2" [mips_arch_list_matching mips2 !nollsc] + run_dump_test_arches "ld-zero-2" [mips_arch_list_matching mips2 !nollsc !mips32r6] run_dump_test_arches "ld-zero-3" [mips_arch_list_matching mips3 !nollsc] run_dump_test_arches "ld-zero-u" [mips_arch_list_matching micromips] run_dump_test_arches "ld-zero-q" [mips_arch_list_matching r5900] @@ -648,9 +703,9 @@ if { [istarget mips*-*-vxworks*] } { run_list_test_arches "mips4-fp" "-32 -msoft-float" \ [mips_arch_list_matching fpisa4] run_dump_test_arches "mips4-branch-likely" \ - [mips_arch_list_matching mips4] + [mips_arch_list_matching mips4 !mips32r6] run_list_test_arches "mips4-branch-likely" "-32 -msoft-float" \ - [mips_arch_list_matching mips4] + [mips_arch_list_matching mips4 !mips32r6] run_dump_test_arches "mips5-fp" "-32" \ [mips_arch_list_matching fpisa5] run_dump_test_arches "mips5-fp" "-mabi=o64" \ @@ -666,8 +721,8 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "sb" run_dump_test "trunc" run_dump_test "ulh" - run_dump_test_arches "ulh2-eb" [mips_arch_list_matching mips1] - run_dump_test_arches "ulh2-el" [mips_arch_list_matching mips1] + run_dump_test_arches "ulh2-eb" [mips_arch_list_matching mips1 !mips32r6] + run_dump_test_arches "ulh2-el" [mips_arch_list_matching mips1 !mips32r6] run_dump_test "ulh-svr4pic" run_dump_test "ulh-xgot" run_dump_test "ulw" @@ -675,19 +730,19 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "ush" run_dump_test "usw" run_dump_test "usd" - run_dump_test_arches "ulw2-eb" [mips_arch_list_matching mips1 !gpr_ilocks] - run_dump_test_arches "ulw2-eb-ilocks" [mips_arch_list_matching gpr_ilocks] - run_dump_test_arches "ulw2-el" [mips_arch_list_matching mips1 !gpr_ilocks] - run_dump_test_arches "ulw2-el-ilocks" [mips_arch_list_matching gpr_ilocks] + run_dump_test_arches "ulw2-eb" [mips_arch_list_matching mips1 !gpr_ilocks !mips32r6] + run_dump_test_arches "ulw2-eb-ilocks" [mips_arch_list_matching gpr_ilocks !mips32r6] + run_dump_test_arches "ulw2-el" [mips_arch_list_matching mips1 !gpr_ilocks !mips32r6] + run_dump_test_arches "ulw2-el-ilocks" [mips_arch_list_matching gpr_ilocks !mips32r6] - run_dump_test_arches "uld2-eb" [mips_arch_list_matching mips3] - run_dump_test_arches "uld2-el" [mips_arch_list_matching mips3] + run_dump_test_arches "uld2-eb" [mips_arch_list_matching mips3 !mips32r6] + run_dump_test_arches "uld2-el" [mips_arch_list_matching mips3 !mips32r6] run_dump_test "mips16" run_dump_test "mips16-64" run_dump_test "mips16-macro" # Check MIPS16e extensions - run_dump_test_arches "mips16e" [mips_arch_list_matching mips32 !micromips] + run_dump_test_arches "mips16e" [mips_arch_list_matching mips32 !micromips !mips32r6] # Check jalx handling run_dump_test "mips16-jalx" run_dump_test "mips-jalx" @@ -735,11 +790,11 @@ if { [istarget mips*-*-vxworks*] } { run_list_test_arches "mips32r2-fp32" "-32 -msoft-float" \ [mips_arch_list_matching mips32r2] run_list_test_arches "mips32r2-ill" "-32" \ - [mips_arch_list_matching mips32r2 gpr32] + [mips_arch_list_matching mips32r2 gpr32 !mips32r6] run_list_test_arches "mips32r2-ill-fp64" "-mabi=o64" \ - [mips_arch_list_matching mips32r2 gpr64] + [mips_arch_list_matching mips32r2 gpr64 !mips32r6] run_list_test_arches "mips32r2-ill-nofp" "-32 -msoft-float" \ - [mips_arch_list_matching mips32r2] + [mips_arch_list_matching mips32r2 !mips32r6] run_dump_test_arches "mips64" [mips_arch_list_matching mips64] run_dump_test_arches "mips64-cp2" [mips_arch_list_matching mips64 \ @@ -760,18 +815,18 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "xlr-ext" } - run_dump_test_arches "relax" [mips_arch_list_matching mips2] - run_dump_test_arches "relax-at" [mips_arch_list_matching mips2] + run_dump_test_arches "relax" [mips_arch_list_matching mips2 !mips32r6] + run_dump_test_arches "relax-at" [mips_arch_list_matching mips2 !mips32r6] run_dump_test "relax-swap1-mips1" run_dump_test "relax-swap1-mips2" run_dump_test "relax-swap2" run_dump_test_arches "relax-swap3" [mips_arch_list_all] - run_list_test_arches "relax-bc1any" "-mips3d -relax-branch" \ + run_list_test_arches "relax-bc1any" "-mips3d -mabi=o64 -relax-branch" \ [mips_arch_list_matching mips64 \ - !micromips] + !micromips !mips32r6] run_list_test_arches "relax-bposge" "-mdsp -relax-branch" \ [mips_arch_list_matching mips64r2 \ - !micromips] + !micromips !mips32r6] run_dump_test_arches "eva" [mips_arch_list_matching mips32r2 !octeon] @@ -803,8 +858,12 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "elf_arch_mips5" run_dump_test "elf_arch_mips32" run_dump_test "elf_arch_mips32r2" + run_dump_test "elf_arch_mips32r3" + run_dump_test "elf_arch_mips32r5" run_dump_test "elf_arch_mips64" run_dump_test "elf_arch_mips64r2" + run_dump_test "elf_arch_mips64r3" + run_dump_test "elf_arch_mips64r5" # Verify that ASE markings are handled properly. run_dump_test "elf_ase_mips16" @@ -965,6 +1024,18 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "cp0sel-names-mips64r2" run_dump_test "cp0sel-names-sb1" + run_dump_test "cp1-names-numeric" + run_dump_test "cp1-names-r3000" + run_dump_test "cp1-names-r4000" \ + { { {name} {(r4000)} } { {objdump} {-M cp0-names=r4000} } } + run_dump_test "cp1-names-r4000" \ + { { {name} {(r4400)} } { {objdump} {-M cp0-names=r4400} } } + run_dump_test "cp1-names-mips32" + run_dump_test "cp1-names-mips32r2" + run_dump_test "cp1-names-mips64" + run_dump_test "cp1-names-mips64r2" + run_dump_test "cp1-names-sb1" + run_dump_test "hwr-names-numeric" run_dump_test "hwr-names-mips32r2" run_dump_test "hwr-names-mips64r2" @@ -1025,9 +1096,9 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "smartmips" run_dump_test_arches "mips32-dsp" [mips_arch_list_matching mips32r2 \ - !octeon] + !octeon !mips32r6] run_dump_test_arches "mips32-dspr2" [mips_arch_list_matching mips32r2 \ - !octeon] + !octeon !mips32r6] run_dump_test "mips64-dsp" run_dump_test "mips32-mt" @@ -1074,11 +1145,11 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "mips32-sync" run_dump_test_arches "mips32r2-sync" \ [mips_arch_list_matching mips32r2] - run_dump_test_arches "alnv_ps-swap" [mips_arch_list_matching fpisa5] + run_dump_test_arches "alnv_ps-swap" [mips_arch_list_matching fpisa5 !mips32r6] run_dump_test_arches "cache" [lsort -dictionary -unique [concat \ [mips_arch_list_matching mips3] \ [mips_arch_list_matching mips32] ] ] - run_dump_test_arches "daddi" [mips_arch_list_matching mips3] + run_dump_test_arches "daddi" [mips_arch_list_matching mips3 !mips32r6] run_dump_test_arches "pref" [lsort -dictionary -unique [concat \ [mips_arch_list_matching mips4] \ [mips_arch_list_matching mips32] ] ] @@ -1142,9 +1213,178 @@ if { [istarget mips*-*-vxworks*] } { # Start with MIPS II to avoid load delay nops. run_dump_test_arches "ld-reloc" [mips_arch_list_matching mips2] - run_dump_test_arches "ulw-reloc" [mips_arch_list_matching mips2] - run_dump_test_arches "ulh-reloc" [mips_arch_list_matching mips2] + run_dump_test_arches "ulw-reloc" [mips_arch_list_matching mips2 !mips32r6] + run_dump_test_arches "ulh-reloc" [mips_arch_list_matching mips2 !mips32r6] run_dump_test "l_d-reloc" run_list_test "bltzal" + + run_dump_test_arches "msa" [mips_arch_list_matching mips32r2] + run_dump_test_arches "msa64" [mips_arch_list_matching mips64r2] + run_dump_test_arches "msa-relax" [mips_arch_list_matching mips32r2 !mips32r6] + run_dump_test_arches "msa-branch" [mips_arch_list_matching mips32r2] + + run_dump_test_arches "xpa" [mips_arch_list_matching mips32r2 !micromips] + run_dump_test_arches "r5" [mips_arch_list_matching mips32r5 !micromips] + + run_dump_test "pcrel-1" + run_dump_test "pcrel-2" + run_list_test "pcrel-3" "" "Invalid cross-section PC-relative references" + run_dump_test "pcrel-4-32" + if $has_newabi { + run_dump_test "pcrel-4-n32" + run_dump_test "pcrel-4-64" + } + + run_dump_test_arches "attr-gnu-4-0" "-32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-0" "-64" \ + [mips_arch_list_matching mips3] + run_dump_test_arches "attr-gnu-4-0" "-mfp32 -32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-0" "-mfpxx -32" \ + [mips_arch_list_matching mips2 !r5900] + run_dump_test_arches "attr-gnu-4-0" "-mfp64 -32" \ + [mips_arch_list_matching mips32r2] + run_dump_test_arches "attr-gnu-4-0" "-mfp64 -64" \ + [mips_arch_list_matching mips3] + run_dump_test_arches "attr-gnu-4-0" "-msingle-float -32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-0" "-msingle-float -64" \ + [mips_arch_list_matching mips3] + run_dump_test_arches "attr-gnu-4-0" "-msoft-float -32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-0" "-msoft-float -64" \ + [mips_arch_list_matching mips3] + run_dump_test_arches "attr-none-double" "-32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-none-double" "-64" \ + [mips_arch_list_matching mips3] + run_dump_test_arches "attr-none-o32-fpxx" \ + [mips_arch_list_matching mips2 !r5900] + run_dump_test_arches "attr-none-o32-fp64" \ + [mips_arch_list_matching mips32r2] + run_dump_test_arches "attr-none-single-float" "-32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-none-single-float" "-64" \ + [mips_arch_list_matching mips3] + run_dump_test_arches "attr-none-soft-float" "-32 -msoft-float" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-none-soft-float" "-64 -msoft-float" \ + [mips_arch_list_matching mips3] + + run_list_test_arches "attr-gnu-4-1-mfp64" "-32 -mfp64" \ + [mips_arch_list_matching mips32r2] + run_list_test_arches "attr-gnu-4-1-mfp32" "-64 -mfp32" \ + [mips_arch_list_matching mips3] + run_list_test_arches "attr-gnu-4-1-msingle-float" "-32 -msingle-float" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-1-msoft-float" "-32 -msoft-float" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-1" "-32 -mfpxx" \ + [mips_arch_list_matching mips2 !r5900] + run_dump_test_arches "attr-gnu-4-1" "-32 -mfp32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-1" "-64 -mfp64" \ + [mips_arch_list_matching mips3] + + run_list_test_arches "attr-gnu-4-2-mdouble-float" "-32 -mfp32" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-2-mdouble-float" "-32 -mfpxx" \ + [mips_arch_list_matching mips2 !r5900] + run_list_test_arches "attr-gnu-4-2-mdouble-float" "-32 -mfp64" \ + [mips_arch_list_matching mips32r2] + run_list_test_arches "attr-gnu-4-2-mdouble-float" "-64 -mfp64" \ + [mips_arch_list_matching mips3] + run_list_test_arches "attr-gnu-4-2-msoft-float" "-32 -msoft-float" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-2" "-32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-2" "-64" \ + [mips_arch_list_matching mips3] + + run_list_test_arches "attr-gnu-4-3-mhard-float" "-32 -mfp32" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-3-mhard-float" "-32 -mfpxx" \ + [mips_arch_list_matching mips2 !r5900] + run_list_test_arches "attr-gnu-4-3-mhard-float" "-32 -mfp64" \ + [mips_arch_list_matching mips32r2] + run_list_test_arches "attr-gnu-4-3-mhard-float" "-64 -mfp64" \ + [mips_arch_list_matching mips3] + run_list_test_arches "attr-gnu-4-3-mhard-float" "-32 -msingle-float" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-3" "-32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-3" "-64" \ + [mips_arch_list_matching mips3] + + run_list_test_arches "attr-gnu-4-4" "-32 -mfp32" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-4" "-32 -mfpxx" \ + [mips_arch_list_matching mips2 !r5900] + run_list_test_arches "attr-gnu-4-4" "-32 -mfp64" \ + [mips_arch_list_matching mips32r2] + run_list_test_arches "attr-gnu-4-4" "-64 -mfp64" \ + [mips_arch_list_matching mips3] + run_list_test_arches "attr-gnu-4-4" "-32 -msingle-float" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-4" "-32 -msoft-float" \ + [mips_arch_list_matching mips1] + + run_list_test_arches "attr-gnu-4-5" "-32 -mfp32" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-5" "-32 -mfp64" \ + [mips_arch_list_matching mips32r2] + run_list_test_arches "attr-gnu-4-5-64" "-64 -mfp64" \ + [mips_arch_list_matching mips3] + run_list_test_arches "attr-gnu-4-5" "-32 -msingle-float" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-5" "-32 -msoft-float" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-5" \ + [mips_arch_list_matching mips2 !r5900] + + run_list_test_arches "attr-gnu-4-6" "-32 -mfp32" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-6-64" "-64 -mfp64" \ + [mips_arch_list_matching mips3] + run_list_test_arches "attr-gnu-4-6" "-32 -msingle-float" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-6" "-32 -msoft-float" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-6" "-mfpxx" \ + [mips_arch_list_matching mips2 !r5900] + run_dump_test_arches "attr-gnu-4-6" "-mfp64" \ + [mips_arch_list_matching mips32r2] + + run_dump_test "attr-gnu-abi-fp-1" + run_dump_test "attr-gnu-abi-msa-1" + + run_dump_test "module-override" + run_dump_test "module-defer-warn1" + run_list_test "module-defer-warn2" "-32" + + foreach testopt [list -mfp32 -mfpxx -mfp64 -msingle-float -msoft-float] { + foreach cmdopt [list -mfp32 -mfpxx -mfp64 -msingle-float -msoft-float] { + run_dump_test "module${testopt}" \ + [list [list as $cmdopt] [list name ($cmdopt)]] + } + } + + run_dump_test "module-set-mfpxx" + run_list_test_arches "fpxx-oddfpreg" "-32 -mfpxx" \ + [mips_arch_list_matching mips2 !singlefloat !oddspreg] + run_list_test_arches "fpxx-oddfpreg" "-32 -mfpxx -mno-odd-spreg" \ + [mips_arch_list_matching oddspreg] + run_dump_test_arches "fpxx-oddfpreg" "-32 -mfpxx" \ + [mips_arch_list_matching oddspreg] + run_dump_test "module-check" + run_list_test "module-check-warn" "-32" + + run_dump_test "li-d" + + run_dump_test_arches "r6" [mips_arch_list_matching mips32r6 !micromips] + run_dump_test_arches "r6-64" [mips_arch_list_matching mips64r6 !micromips] + run_list_test_arches "r6-removed" [mips_arch_list_matching mips32r6] + run_list_test_arches "r6-64-removed" [mips_arch_list_matching mips64r6] } diff --git a/binutils-2.24/gas/testsuite/gas/mips/mips32-cp2.s b/binutils-2.24/gas/testsuite/gas/mips/mips32-cp2.s index 182ba87..c3bbf47 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/mips32-cp2.s +++ b/binutils-2.24/gas/testsuite/gas/mips/mips32-cp2.s @@ -8,6 +8,7 @@ text_label: # unprivileged coprocessor instructions. # these tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes. +.ifndef r6 bc2f text_label nop bc2fl text_label @@ -16,6 +17,7 @@ text_label: nop bc2tl text_label nop +.endif # XXX other BCzCond encodings not currently expressable cfc2 $1, $2 cop2 0x1234567 # disassembles as c2 ... @@ -28,6 +30,7 @@ text_label: mtc2 $8, $9, 7 +.ifndef r6 # Cop2 branches with cond code number, like bc1t/f bc2f $cc0,text_label nop @@ -37,3 +40,4 @@ text_label: nop bc2tl $cc7,text_label nop +.endif diff --git a/binutils-2.24/gas/testsuite/gas/mips/mips32.s b/binutils-2.24/gas/testsuite/gas/mips/mips32.s index 5051d5a..f401c80 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/mips32.s +++ b/binutils-2.24/gas/testsuite/gas/mips/mips32.s @@ -10,20 +10,25 @@ text_label: clo $1, $2 clz $3, $4 +.ifndef r6 madd $5, $6 maddu $7, $8 msub $9, $10 msubu $11, $12 +.endif mul $13, $14, $15 pref 4, ($16) +.ifndef r6 pref 4, 2047($17) pref 4, -2048($18) +.endif ssnop # privileged instructions cache 5, ($1) +.ifndef r6 cache 5, 2047($2) cache 5, -2048($3) .set at @@ -32,6 +37,7 @@ text_label: cache 5, 32768 cache 5, -32769 .set noat +.endif eret tlbp tlbr diff --git a/binutils-2.24/gas/testsuite/gas/mips/mips4.s b/binutils-2.24/gas/testsuite/gas/mips/mips4.s index 7f5457c..b6b7aec 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/mips4.s +++ b/binutils-2.24/gas/testsuite/gas/mips/mips4.s @@ -1,8 +1,10 @@ # Source file used to test -mips4 *non-fp* instructions. text_label: +.ifndef r6 movn $4,$6,$6 movz $4,$6,$6 +.endif # It used to be disabled due to a clash with lwc3. pref 4,0($4) diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-branch-delay-1.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-branch-delay-1.d new file mode 100644 index 0000000..928eae9 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-branch-delay-1.d @@ -0,0 +1,23 @@ +#objdump: -dr +#as: -mfix-24k -32 +#source: 24k-branch-delay-1.s +#name: 24K: Delay slot filling + +.*: +file format .*mips.* + +Disassembly of section .text: +0+ <.*>: + 0: 24620005 addiu v0,v1,5 + 4: 8c440000 lw a0,0\(v0\) + 8: ac430000 sw v1,0\(v0\) + c: ac430008 sw v1,8\(v0\) + 10: 00000000 nop + 14: ac430010 sw v1,16\(v0\) + 18: 1060ffff beqz v1,18 <.*> +[ ]*18: .*R_MIPS_PC16 .L1 + 1c: 00000000 nop + 20: 8c430008 lw v1,8\(v0\) + +0+24 <.L1>: + 24: 8c450010 lw a1,16\(v0\) + ... diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-1.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-1.d new file mode 100644 index 0000000..ca334a6 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-1.d @@ -0,0 +1,68 @@ +#objdump: -dr +#as: -mfix-24k -32 +#source: 24k-triple-stores-1.s +#name: 24K: Triple Store (Opcode Check) + +.*: +file format .*mips.* + +Disassembly of section .text: +0+ <.*>: + 0: a3a20000 sb v0,0\(sp\) + 4: a3a30008 sb v1,8\(sp\) + 8: 00000000 nop + c: a3a40010 sb a0,16\(sp\) + 10: a3a50018 sb a1,24\(sp\) + 14: 00000000 nop + 18: a3a60020 sb a2,32\(sp\) + 1c: a7a20000 sh v0,0\(sp\) + 20: a7a30008 sh v1,8\(sp\) + 24: 00000000 nop + 28: a7a40010 sh a0,16\(sp\) + 2c: a7a50018 sh a1,24\(sp\) + 30: 00000000 nop + 34: a7a60020 sh a2,32\(sp\) + 38: afa20000 sw v0,0\(sp\) + 3c: afa30008 sw v1,8\(sp\) + 40: 00000000 nop + 44: afa40010 sw a0,16\(sp\) + 48: afa50018 sw a1,24\(sp\) + 4c: 00000000 nop + 50: afa60020 sw a2,32\(sp\) + 54: 7fa20026 sc v0,0\(sp\) + 58: 00000000 nop + 5c: 7fa30426 sc v1,8\(sp\) + 60: 7fa40826 sc a0,16\(sp\) + 64: 00000000 nop + 68: 7fa50c26 sc a1,24\(sp\) + 6c: 7fa61026 sc a2,32\(sp\) + 70: 00000000 nop + 74: e7a20000 swc1 \$f2,0\(sp\) + 78: e7a30008 swc1 \$f3,8\(sp\) + 7c: 00000000 nop + 80: e7a40010 swc1 \$f4,16\(sp\) + 84: e7a50018 swc1 \$f5,24\(sp\) + 88: 00000000 nop + 8c: e7a60020 swc1 \$f6,32\(sp\) + 90: 4962e800 swc2 \$2,0\(sp\) + 94: 00000000 nop + 98: 4963e808 swc2 \$3,8\(sp\) + 9c: 4964e810 swc2 \$4,16\(sp\) + a0: 00000000 nop + a4: 4965e818 swc2 \$5,24\(sp\) + a8: 4966e820 swc2 \$6,32\(sp\) + ac: 00000000 nop + b0: f7a20000 sdc1 \$f2,0\(sp\) + b4: f7a30008 sdc1 \$f3,8\(sp\) + b8: 00000000 nop + bc: f7a40010 sdc1 \$f4,16\(sp\) + c0: f7a50018 sdc1 \$f5,24\(sp\) + c4: 00000000 nop + c8: f7a60020 sdc1 \$f6,32\(sp\) + cc: 49e2e800 sdc2 \$2,0\(sp\) + d0: 00000000 nop + d4: 49e3e808 sdc2 \$3,8\(sp\) + d8: 49e4e810 sdc2 \$4,16\(sp\) + dc: 00000000 nop + e0: 49e5e818 sdc2 \$5,24\(sp\) + e4: 49e6e820 sdc2 \$6,32\(sp\) + ... diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-2-llsc.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-2-llsc.d new file mode 100644 index 0000000..8119bce --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-2-llsc.d @@ -0,0 +1,17 @@ +#objdump: -dr +#as: -mfix-24k -32 +#source: 24k-triple-stores-2-llsc.s +#name: 24K: Triple Store (Range Check, sc) + +.*: +file format .*mips.* + +Disassembly of section .text: +0+ <.*>: + 0: 7fa21026 sc v0,32\(sp\) + 4: 7fa30426 sc v1,8\(sp\) + 8: 00000000 nop + c: 7fa4fc26 sc a0,-8\(sp\) + 10: 7fa50026 sc a1,0\(sp\) + 14: 00000000 nop + 18: 7fa61026 sc a2,32\(sp\) + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-2.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-2.d new file mode 100644 index 0000000..eb3ee96 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-2.d @@ -0,0 +1,24 @@ +#objdump: -dr +#as: -mfix-24k -32 +#source: 24k-triple-stores-2.s +#name: 24K: Triple Store (Range Check) + +.*: +file format .*mips.* + +Disassembly of section .text: +0+ <.*>: + 0: a3a20000 sb v0,0\(sp\) + 4: a3a3000a sb v1,10\(sp\) + 8: 00000000 nop + c: a3a4001f sb a0,31\(sp\) + 10: 0000000d break + 14: a7a20000 sh v0,0\(sp\) + 18: a7a3fff0 sh v1,-16\(sp\) + 1c: a7a4ffe0 sh a0,-32\(sp\) + 20: 0000000d break + 24: afa20000 sw v0,0\(sp\) + 28: afa3fff8 sw v1,-8\(sp\) + 2c: 00000000 nop + 30: afa40008 sw a0,8\(sp\) + 34: 0000000d break + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-3.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-3.d new file mode 100644 index 0000000..7e5e415 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-3.d @@ -0,0 +1,57 @@ +#objdump: -dr +#as: -mfix-24k -32 +#name: 24K: Triple Store (Double-word Check) +#source: 24k-triple-stores-3.s + +.*: +file format .*mips.* + +Disassembly of section .text: + +0+ <.*>: + 0: a3a2000b sb v0,11\(sp\) + 4: a3a3000b sb v1,11\(sp\) + 8: a3a40004 sb a0,4\(sp\) + c: 0000000d break + 10: a3a20000 sb v0,0\(sp\) + 14: a3a3000b sb v1,11\(sp\) + 18: a3a40005 sb a0,5\(sp\) + 1c: 0000000d break + 20: a3a20007 sb v0,7\(sp\) + 24: a3a3000b sb v1,11\(sp\) + 28: 00000000 nop + 2c: a3a40010 sb a0,16\(sp\) + 30: 0000000d break + 34: a1020000 sb v0,0\(t0\) + 38: a1030008 sb v1,8\(t0\) + 3c: 00000000 nop + 40: a1040009 sb a0,9\(t0\) + 44: 0000000d break + 48: a7a20000 sh v0,0\(sp\) + 4c: a7a3ffe1 sh v1,-31\(sp\) + 50: a7a4ffe2 sh a0,-30\(sp\) + 54: 0000000d break + 58: a7a20006 sh v0,6\(sp\) + 5c: a7a30008 sh v1,8\(sp\) + 60: 00000000 nop + 64: a7a40010 sh a0,16\(sp\) + 68: 0000000d break + 6c: a5020001 sh v0,1\(t0\) + 70: a5030003 sh v1,3\(t0\) + 74: 00000000 nop + 78: a504000b sh a0,11\(t0\) + 7c: 0000000d break + 80: afa20008 sw v0,8\(sp\) + 84: afa3fff8 sw v1,-8\(sp\) + 88: afa40008 sw a0,8\(sp\) + 8c: 0000000d break + 90: afa20004 sw v0,4\(sp\) + 94: afa30008 sw v1,8\(sp\) + 98: 00000000 nop + 9c: afa40010 sw a0,16\(sp\) + a0: 0000000d break + a4: ad020003 sw v0,3\(t0\) + a8: ad030007 sw v1,7\(t0\) + ac: 00000000 nop + b0: ad04000f sw a0,15\(t0\) + b4: 0000000d break + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-6.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-6.d new file mode 100644 index 0000000..271f947 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@24k-triple-stores-6.d @@ -0,0 +1,20 @@ +#objdump: -dr +#as: -mfix-24k -32 -EB +#name: 24K: Triple Store (Store Macro Check) +#source: 24k-triple-stores-6.s + +.*: +file format .*mips.* + +Disassembly of section .text: +0+ <.*>: + 0: e7a00050 swc1 \$f0,80\(sp\) + 4: e7a20058 swc1 \$f2,88\(sp\) + 8: 00000000 nop + c: e7a40060 swc1 \$f4,96\(sp\) + 10: 0000000d break + 14: f7a00050 sdc1 \$f0,80\(sp\) + 18: f7a20058 sdc1 \$f2,88\(sp\) + 1c: 00000000 nop + 20: f7a40060 sdc1 \$f4,96\(sp\) + 24: 0000000d break + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@add.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@add.d new file mode 100644 index 0000000..6d097db --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@add.d @@ -0,0 +1,12 @@ +#objdump: -dr --prefix-addresses +#name: MIPS add +#source: add.s +#as: -32 + +# Test the add macro. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> addiu a0,a0,1 +0+0004 <[^>]*> nop diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@beq.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@beq.d new file mode 100644 index 0000000..b5fec4c --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@beq.d @@ -0,0 +1,41 @@ +#objdump: -dr --prefix-addresses -mmips:4000 +#name: MIPS beq +#as: -32 +#source: beq.s + +# Test the beq macro. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> beq a0,a1,0+0000 <.*> +[ ]*0: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> beqz a0,0+0008 <.*> +[ ]*8: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> li at,1 +[0-9a-f]+ <[^>]*> beq a0,at,0+0014 <.*> +[ ]*14: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> li at,0x8000 +[0-9a-f]+ <[^>]*> beq a0,at,0+0020 <.*> +[ ]*20: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> li at,-32768 +[0-9a-f]+ <[^>]*> beq a0,at,0+002c <.*> +[ ]*2c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> lui at,0x1 +[0-9a-f]+ <[^>]*> beq a0,at,0+0038 <.*> +[ ]*38: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> lui at,0x1 +[0-9a-f]+ <[^>]*> ori at,at,0xa5a5 +[0-9a-f]+ <[^>]*> beq a0,at,0+0048 <.*> +[ ]*48: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> bnez a0,0+0050 <.*> +[ ]*50: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@bge.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@bge.d new file mode 100644 index 0000000..050bc1b --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@bge.d @@ -0,0 +1,72 @@ +#objdump: -dr --prefix-addresses -mmips:4000 +#name: MIPS bge +#as: -32 +#source: bge.s + +# Test the bge macro. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> slt at,a0,a1 +[0-9a-f]+ <[^>]*> beqz at,0+0004 <.*> +[ ]*4: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> bgez a0,0+000c <.*> +[ ]*c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> blez a1,0+0014 <.*> +[ ]*14: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> bgez a0,0+001c <.*> +[ ]*1c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> bgtz a0,0+0024 <.*> +[ ]*24: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> slti at,a0,2 +[0-9a-f]+ <[^>]*> beqz at,0+0030 <.*> +[ ]*30: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> li at,0x8000 +[0-9a-f]+ <[^>]*> slt at,a0,at +[0-9a-f]+ <[^>]*> beqz at,0+0040 <.*> +[ ]*40: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> slti at,a0,-32768 +[0-9a-f]+ <[^>]*> beqz at,0+004c <.*> +[ ]*4c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> lui at,0x1 +[0-9a-f]+ <[^>]*> slt at,a0,at +[0-9a-f]+ <[^>]*> beqz at,0+005c <.*> +[ ]*5c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> lui at,0x1 +[0-9a-f]+ <[^>]*> ori at,at,0xa5a5 +[0-9a-f]+ <[^>]*> slt at,a0,at +[0-9a-f]+ <[^>]*> beqz at,0+0070 <.*> +[ ]*70: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> slt at,a1,a0 +[0-9a-f]+ <[^>]*> bnez at,0+007c <.*> +[ ]*7c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> bgtz a0,0+0084 <.*> +[ ]*84: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> bltz a1,0+008c <.*> +[ ]*8c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> bgtz a0,0+0094 <.*> +[ ]*94: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> slt at,a0,a1 +[0-9a-f]+ <[^>]*> beqz at,0+00a0 <.*\+0xa0> +[ ]*a0: .*16 external_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> slt at,a1,a0 +[0-9a-f]+ <[^>]*> bnez at,0+00ac <.*\+0xac> +[ ]*ac: .*16 external_label +[0-9a-f]+ <[^>]*> nop + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@bgeu.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@bgeu.d new file mode 100644 index 0000000..38bdfb1 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@bgeu.d @@ -0,0 +1,63 @@ +#objdump: -dr --prefix-addresses -mmips:4000 +#name: MIPS bgeu +#as: -32 +#source: bgeu.s + +# Test the bgeu macro. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> sltu at,a0,a1 +[0-9a-f]+ <[^>]*> beqz at,0+0004 <.*> +[ ]*4: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> beq zero,a1,0+000c <.*> +[ ]*c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> bnez a0,0+0014 <.*> +[ ]*14: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> sltiu at,a0,2 +[0-9a-f]+ <[^>]*> beqz at,0+0020 <.*> +[ ]*20: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> li at,0x8000 +[0-9a-f]+ <[^>]*> sltu at,a0,at +[0-9a-f]+ <[^>]*> beqz at,0+0030 <.*> +[ ]*30: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> sltiu at,a0,-32768 +[0-9a-f]+ <[^>]*> beqz at,0+003c <.*> +[ ]*3c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> lui at,0x1 +[0-9a-f]+ <[^>]*> sltu at,a0,at +[0-9a-f]+ <[^>]*> beqz at,0+004c <.*> +[ ]*4c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> lui at,0x1 +[0-9a-f]+ <[^>]*> ori at,at,0xa5a5 +[0-9a-f]+ <[^>]*> sltu at,a0,at +[0-9a-f]+ <[^>]*> beqz at,0+0060 <.*> +[ ]*60: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> sltu at,a1,a0 +[0-9a-f]+ <[^>]*> bnez at,0+006c <.*> +[ ]*6c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> bnez a0,0+0074 <.*> +[ ]*74: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> bnez a0,0+007c <.*> +[ ]*7c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> sltu at,a0,a1 +[0-9a-f]+ <[^>]*> beqz at,0+0088 <.*\+0x88> +[ ]*88: .*16 external_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> sltu at,a1,a0 +[0-9a-f]+ <[^>]*> bnez at,0+0094 <.*\+0x94> +[ ]*94: .*16 external_label +[0-9a-f]+ <[^>]*> nop + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@blt.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@blt.d new file mode 100644 index 0000000..0f056f6 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@blt.d @@ -0,0 +1,72 @@ +#objdump: -dr --prefix-addresses -mmips:4000 +#name: MIPS blt +#as: -32 +#source: blt.s + +# Test the blt macro. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> slt at,a0,a1 +[0-9a-f]+ <[^>]*> bnez at,0+0004 <.*> +[ ]*4: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> bltz a0,0+000c <.*> +[ ]*c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> bgtz a1,0+0014 <.*> +[ ]*14: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> bltz a0,0+001c <.*> +[ ]*1c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> blez a0,0+0024 <.*> +[ ]*24: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> slti at,a0,2 +[0-9a-f]+ <[^>]*> bnez at,0+0030 <.*> +[ ]*30: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> li at,0x8000 +[0-9a-f]+ <[^>]*> slt at,a0,at +[0-9a-f]+ <[^>]*> bnez at,0+0040 <.*> +[ ]*40: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> slti at,a0,-32768 +[0-9a-f]+ <[^>]*> bnez at,0+004c <.*> +[ ]*4c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> lui at,0x1 +[0-9a-f]+ <[^>]*> slt at,a0,at +[0-9a-f]+ <[^>]*> bnez at,0+005c <.*> +[ ]*5c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> lui at,0x1 +[0-9a-f]+ <[^>]*> ori at,at,0xa5a5 +[0-9a-f]+ <[^>]*> slt at,a0,at +[0-9a-f]+ <[^>]*> bnez at,0+0070 <.*> +[ ]*70: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> slt at,a1,a0 +[0-9a-f]+ <[^>]*> beqz at,0+007c <.*> +[ ]*7c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> blez a0,0+0084 <.*> +[ ]*84: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> bgez a1,0+008c <.*> +[ ]*8c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> blez a0,0+0094 <.*> +[ ]*94: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> slt at,a0,a1 +[0-9a-f]+ <[^>]*> bnez at,0+00a0 <.*\+0xa0> +[ ]*a0: .*16 external_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> slt at,a1,a0 +[0-9a-f]+ <[^>]*> beqz at,0+00ac <.*\+0xac> +[ ]*ac: .*16 external_label +[0-9a-f]+ <[^>]*> nop + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@bltu.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@bltu.d new file mode 100644 index 0000000..24ac4e2 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@bltu.d @@ -0,0 +1,63 @@ +#objdump: -dr --prefix-addresses -mmips:4000 +#name: MIPS bltu +#as: -32 +#source: bltu.s + +# Test the bltu macro. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> sltu at,a0,a1 +[0-9a-f]+ <[^>]*> bnez at,0+0004 <.*> +[ ]*4: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> bne zero,a1,0+000c <.*> +[ ]*c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> beqz a0,0+0014 <.*> +[ ]*14: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> sltiu at,a0,2 +[0-9a-f]+ <[^>]*> bnez at,0+0020 <.*> +[ ]*20: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> li at,0x8000 +[0-9a-f]+ <[^>]*> sltu at,a0,at +[0-9a-f]+ <[^>]*> bnez at,0+0030 <.*> +[ ]*30: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> sltiu at,a0,-32768 +[0-9a-f]+ <[^>]*> bnez at,0+003c <.*> +[ ]*3c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> lui at,0x1 +[0-9a-f]+ <[^>]*> sltu at,a0,at +[0-9a-f]+ <[^>]*> bnez at,0+004c <.*> +[ ]*4c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> lui at,0x1 +[0-9a-f]+ <[^>]*> ori at,at,0xa5a5 +[0-9a-f]+ <[^>]*> sltu at,a0,at +[0-9a-f]+ <[^>]*> bnez at,0+0060 <.*> +[ ]*60: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> sltu at,a1,a0 +[0-9a-f]+ <[^>]*> beqz at,0+006c <.*> +[ ]*6c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> beqz a0,0+0074 <.*> +[ ]*74: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> beqz a0,0+007c <.*> +[ ]*7c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> sltu at,a0,a1 +[0-9a-f]+ <[^>]*> bnez at,0+0088 <.*\+0x88> +[ ]*88: .*16 external_label +[0-9a-f]+ <[^>]*> nop +[0-9a-f]+ <[^>]*> sltu at,a1,a0 +[0-9a-f]+ <[^>]*> beqz at,0+0094 <.*\+0x94> +[ ]*94: .*16 external_label +[0-9a-f]+ <[^>]*> nop + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@branch-misc-1.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@branch-misc-1.d new file mode 100644 index 0000000..11f2b71 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@branch-misc-1.d @@ -0,0 +1,35 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS branch-misc-1 +#as: -32 +#source: branch-misc-1.s + +# Test the branches to local symbols in current file. + +.*: +file format .*mips.* + +Disassembly of section .text: + \.\.\. + \.\.\. + \.\.\. +0+003c <[^>]*> 0411ffff bal 0000003c <[^>]*> +[ ]*3c: .*R_MIPS_PC16 l1 +0+0040 <[^>]*> 00000000 nop +0+0044 <[^>]*> 0411ffff bal 00000044 <[^>]*> +[ ]*44: .*R_MIPS_PC16 l2 +0+0048 <[^>]*> 00000000 nop +0+004c <[^>]*> 0411ffff bal 0000004c <[^>]*> +[ ]*4c: .*R_MIPS_PC16 l3 +0+0050 <[^>]*> 00000000 nop +0+0054 <[^>]*> 0411ffff bal 00000054 <[^>]*> +[ ]*54: .*R_MIPS_PC16 l4 +0+0058 <[^>]*> 00000000 nop +0+005c <[^>]*> 0411ffff bal 0000005c <[^>]*> +[ ]*5c: .*R_MIPS_PC16 l5 +0+0060 <[^>]*> 00000000 nop +0+0064 <[^>]*> 0411ffff bal 00000064 <[^>]*> +[ ]*64: .*R_MIPS_PC16 l6 +0+0068 <[^>]*> 00000000 nop + \.\.\. + \.\.\. + \.\.\. + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@cache.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@cache.d new file mode 100644 index 0000000..803f5de --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@cache.d @@ -0,0 +1,13 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS CACHE instruction +#source: cache.s +#as: -32 + +# Check MIPS CACHE instruction assembly. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 7c457fa5 cache 0x5,255\(v0\) +[0-9a-f]+ <[^>]*> 7c658025 cache 0x5,-256\(v1\) + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@eva.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@eva.d new file mode 100644 index 0000000..79b6030 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@eva.d @@ -0,0 +1,952 @@ +#objdump: -dr -Mgpr-names=numeric --show-raw-insn +#name: MIPS EVA +#source: eva.s +#as: -meva -32 + +# Test the EVA instructions + +.*: +file format .*mips.* + + +Disassembly of section \.text: + +[ 0-9a-f]+ <test_eva>: +[ 0-9a-f]+: 7c408028 lbue \$0,-256\(\$2\) +[ 0-9a-f]+: 7c038028 lbue \$3,-256\(\$0\) +[ 0-9a-f]+: 7ca47fa8 lbue \$4,255\(\$5\) +[ 0-9a-f]+: 7c067fa8 lbue \$6,255\(\$0\) +[ 0-9a-f]+: 2501feff addiu \$1,\$8,-257 +[ 0-9a-f]+: 7c270028 lbue \$7,0\(\$1\) +[ 0-9a-f]+: 2401feff li \$1,-257 +[ 0-9a-f]+: 7c290028 lbue \$9,0\(\$1\) +[ 0-9a-f]+: 25610100 addiu \$1,\$11,256 +[ 0-9a-f]+: 7c2a0028 lbue \$10,0\(\$1\) +[ 0-9a-f]+: 24010100 li \$1,256 +[ 0-9a-f]+: 7c2c0028 lbue \$12,0\(\$1\) +[ 0-9a-f]+: 25c1fe00 addiu \$1,\$14,-512 +[ 0-9a-f]+: 7c2d0028 lbue \$13,0\(\$1\) +[ 0-9a-f]+: 2401fe00 li \$1,-512 +[ 0-9a-f]+: 7c2f0028 lbue \$15,0\(\$1\) +[ 0-9a-f]+: 262101ff addiu \$1,\$17,511 +[ 0-9a-f]+: 7c300028 lbue \$16,0\(\$1\) +[ 0-9a-f]+: 240101ff li \$1,511 +[ 0-9a-f]+: 7c320028 lbue \$18,0\(\$1\) +[ 0-9a-f]+: 2681fc00 addiu \$1,\$20,-1024 +[ 0-9a-f]+: 7c330028 lbue \$19,0\(\$1\) +[ 0-9a-f]+: 2401fc00 li \$1,-1024 +[ 0-9a-f]+: 7c350028 lbue \$21,0\(\$1\) +[ 0-9a-f]+: 26e103ff addiu \$1,\$23,1023 +[ 0-9a-f]+: 7c360028 lbue \$22,0\(\$1\) +[ 0-9a-f]+: 240103ff li \$1,1023 +[ 0-9a-f]+: 7c380028 lbue \$24,0\(\$1\) +[ 0-9a-f]+: 2741f800 addiu \$1,\$26,-2048 +[ 0-9a-f]+: 7c390028 lbue \$25,0\(\$1\) +[ 0-9a-f]+: 2401f800 li \$1,-2048 +[ 0-9a-f]+: 7c3b0028 lbue \$27,0\(\$1\) +[ 0-9a-f]+: 27a107ff addiu \$1,\$29,2047 +[ 0-9a-f]+: 7c3c0028 lbue \$28,0\(\$1\) +[ 0-9a-f]+: 240107ff li \$1,2047 +[ 0-9a-f]+: 7c3e0028 lbue \$30,0\(\$1\) +[ 0-9a-f]+: 2401f000 li \$1,-4096 +[ 0-9a-f]+: 7c3f0028 lbue \$31,0\(\$1\) +[ 0-9a-f]+: 2401f000 li \$1,-4096 +[ 0-9a-f]+: 7c220028 lbue \$2,0\(\$1\) +[ 0-9a-f]+: 24810fff addiu \$1,\$4,4095 +[ 0-9a-f]+: 7c230028 lbue \$3,0\(\$1\) +[ 0-9a-f]+: 24010fff li \$1,4095 +[ 0-9a-f]+: 7c250028 lbue \$5,0\(\$1\) +[ 0-9a-f]+: 24e18000 addiu \$1,\$7,-32768 +[ 0-9a-f]+: 7c260028 lbue \$6,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c280028 lbue \$8,0\(\$1\) +[ 0-9a-f]+: 25417fff addiu \$1,\$10,32767 +[ 0-9a-f]+: 7c290028 lbue \$9,0\(\$1\) +[ 0-9a-f]+: 24017fff li \$1,32767 +[ 0-9a-f]+: 7c2b0028 lbue \$11,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 002d0821 addu \$1,\$1,\$13 +[ 0-9a-f]+: 7c2cffa8 lbue \$12,-1\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c2effa8 lbue \$14,-1\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 00300821 addu \$1,\$1,\$16 +[ 0-9a-f]+: 7c2f0028 lbue \$15,0\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 7c310028 lbue \$17,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 00330821 addu \$1,\$1,\$19 +[ 0-9a-f]+: 7c320028 lbue \$18,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c340028 lbue \$20,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 00360821 addu \$1,\$1,\$22 +[ 0-9a-f]+: 7c35ffa8 lbue \$21,-1\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c37ffa8 lbue \$23,-1\(\$1\) +[ 0-9a-f]+: 7f380028 lbue \$24,0\(\$25\) +[ 0-9a-f]+: 3c010000 lui \$1,0x0 + [ 0-9a-f]+: R_MIPS_HI16 MYDATA +[ 0-9a-f]+: 24210000 addiu \$1,\$1,0 + [ 0-9a-f]+: R_MIPS_LO16 MYDATA +[ 0-9a-f]+: 7c3a0028 lbue \$26,0\(\$1\) +[ 0-9a-f]+: 7f9b8029 lhue \$27,-256\(\$28\) +[ 0-9a-f]+: 7c1d8029 lhue \$29,-256\(\$0\) +[ 0-9a-f]+: 7ffe7fa9 lhue \$30,255\(\$31\) +[ 0-9a-f]+: 7c007fa9 lhue \$0,255\(\$0\) +[ 0-9a-f]+: 2461feff addiu \$1,\$3,-257 +[ 0-9a-f]+: 7c220029 lhue \$2,0\(\$1\) +[ 0-9a-f]+: 2401feff li \$1,-257 +[ 0-9a-f]+: 7c240029 lhue \$4,0\(\$1\) +[ 0-9a-f]+: 24c10100 addiu \$1,\$6,256 +[ 0-9a-f]+: 7c250029 lhue \$5,0\(\$1\) +[ 0-9a-f]+: 24010100 li \$1,256 +[ 0-9a-f]+: 7c270029 lhue \$7,0\(\$1\) +[ 0-9a-f]+: 2521fe00 addiu \$1,\$9,-512 +[ 0-9a-f]+: 7c280029 lhue \$8,0\(\$1\) +[ 0-9a-f]+: 2401fe00 li \$1,-512 +[ 0-9a-f]+: 7c2a0029 lhue \$10,0\(\$1\) +[ 0-9a-f]+: 258101ff addiu \$1,\$12,511 +[ 0-9a-f]+: 7c2b0029 lhue \$11,0\(\$1\) +[ 0-9a-f]+: 240101ff li \$1,511 +[ 0-9a-f]+: 7c2d0029 lhue \$13,0\(\$1\) +[ 0-9a-f]+: 25e1fc00 addiu \$1,\$15,-1024 +[ 0-9a-f]+: 7c2e0029 lhue \$14,0\(\$1\) +[ 0-9a-f]+: 2401fc00 li \$1,-1024 +[ 0-9a-f]+: 7c300029 lhue \$16,0\(\$1\) +[ 0-9a-f]+: 264103ff addiu \$1,\$18,1023 +[ 0-9a-f]+: 7c310029 lhue \$17,0\(\$1\) +[ 0-9a-f]+: 240103ff li \$1,1023 +[ 0-9a-f]+: 7c330029 lhue \$19,0\(\$1\) +[ 0-9a-f]+: 26a1f800 addiu \$1,\$21,-2048 +[ 0-9a-f]+: 7c340029 lhue \$20,0\(\$1\) +[ 0-9a-f]+: 2401f800 li \$1,-2048 +[ 0-9a-f]+: 7c360029 lhue \$22,0\(\$1\) +[ 0-9a-f]+: 270107ff addiu \$1,\$24,2047 +[ 0-9a-f]+: 7c370029 lhue \$23,0\(\$1\) +[ 0-9a-f]+: 240107ff li \$1,2047 +[ 0-9a-f]+: 7c390029 lhue \$25,0\(\$1\) +[ 0-9a-f]+: 2761f000 addiu \$1,\$27,-4096 +[ 0-9a-f]+: 7c3a0029 lhue \$26,0\(\$1\) +[ 0-9a-f]+: 2401f000 li \$1,-4096 +[ 0-9a-f]+: 7c3c0029 lhue \$28,0\(\$1\) +[ 0-9a-f]+: 27c10fff addiu \$1,\$30,4095 +[ 0-9a-f]+: 7c3d0029 lhue \$29,0\(\$1\) +[ 0-9a-f]+: 24010fff li \$1,4095 +[ 0-9a-f]+: 7c3f0029 lhue \$31,0\(\$1\) +[ 0-9a-f]+: 24418000 addiu \$1,\$2,-32768 +[ 0-9a-f]+: 7c200029 lhue \$0,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c230029 lhue \$3,0\(\$1\) +[ 0-9a-f]+: 24a17fff addiu \$1,\$5,32767 +[ 0-9a-f]+: 7c240029 lhue \$4,0\(\$1\) +[ 0-9a-f]+: 24017fff li \$1,32767 +[ 0-9a-f]+: 7c260029 lhue \$6,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 00280821 addu \$1,\$1,\$8 +[ 0-9a-f]+: 7c27ffa9 lhue \$7,-1\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c29ffa9 lhue \$9,-1\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 002b0821 addu \$1,\$1,\$11 +[ 0-9a-f]+: 7c2a0029 lhue \$10,0\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 7c2c0029 lhue \$12,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 002e0821 addu \$1,\$1,\$14 +[ 0-9a-f]+: 7c2d0029 lhue \$13,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c2f0029 lhue \$15,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 00310821 addu \$1,\$1,\$17 +[ 0-9a-f]+: 7c30ffa9 lhue \$16,-1\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c32ffa9 lhue \$18,-1\(\$1\) +[ 0-9a-f]+: 7e930029 lhue \$19,0\(\$20\) +[ 0-9a-f]+: 3c010000 lui \$1,0x0 + [ 0-9a-f]+: R_MIPS_HI16 MYDATA +[ 0-9a-f]+: 24210000 addiu \$1,\$1,0 + [ 0-9a-f]+: R_MIPS_LO16 MYDATA +[ 0-9a-f]+: 7c350029 lhue \$21,0\(\$1\) +[ 0-9a-f]+: 7ef6802c lbe \$22,-256\(\$23\) +[ 0-9a-f]+: 7c18802c lbe \$24,-256\(\$0\) +[ 0-9a-f]+: 7f597fac lbe \$25,255\(\$26\) +[ 0-9a-f]+: 7c1b7fac lbe \$27,255\(\$0\) +[ 0-9a-f]+: 27a1feff addiu \$1,\$29,-257 +[ 0-9a-f]+: 7c3c002c lbe \$28,0\(\$1\) +[ 0-9a-f]+: 2401feff li \$1,-257 +[ 0-9a-f]+: 7c3e002c lbe \$30,0\(\$1\) +[ 0-9a-f]+: 24010100 li \$1,256 +[ 0-9a-f]+: 7c3f002c lbe \$31,0\(\$1\) +[ 0-9a-f]+: 24010100 li \$1,256 +[ 0-9a-f]+: 7c22002c lbe \$2,0\(\$1\) +[ 0-9a-f]+: 2481fe00 addiu \$1,\$4,-512 +[ 0-9a-f]+: 7c23002c lbe \$3,0\(\$1\) +[ 0-9a-f]+: 2401fe00 li \$1,-512 +[ 0-9a-f]+: 7c25002c lbe \$5,0\(\$1\) +[ 0-9a-f]+: 24e101ff addiu \$1,\$7,511 +[ 0-9a-f]+: 7c26002c lbe \$6,0\(\$1\) +[ 0-9a-f]+: 240101ff li \$1,511 +[ 0-9a-f]+: 7c28002c lbe \$8,0\(\$1\) +[ 0-9a-f]+: 2541fc00 addiu \$1,\$10,-1024 +[ 0-9a-f]+: 7c29002c lbe \$9,0\(\$1\) +[ 0-9a-f]+: 2401fc00 li \$1,-1024 +[ 0-9a-f]+: 7c2b002c lbe \$11,0\(\$1\) +[ 0-9a-f]+: 25a103ff addiu \$1,\$13,1023 +[ 0-9a-f]+: 7c2c002c lbe \$12,0\(\$1\) +[ 0-9a-f]+: 240103ff li \$1,1023 +[ 0-9a-f]+: 7c2e002c lbe \$14,0\(\$1\) +[ 0-9a-f]+: 2601f800 addiu \$1,\$16,-2048 +[ 0-9a-f]+: 7c2f002c lbe \$15,0\(\$1\) +[ 0-9a-f]+: 2401f800 li \$1,-2048 +[ 0-9a-f]+: 7c31002c lbe \$17,0\(\$1\) +[ 0-9a-f]+: 266107ff addiu \$1,\$19,2047 +[ 0-9a-f]+: 7c32002c lbe \$18,0\(\$1\) +[ 0-9a-f]+: 240107ff li \$1,2047 +[ 0-9a-f]+: 7c34002c lbe \$20,0\(\$1\) +[ 0-9a-f]+: 26c1f000 addiu \$1,\$22,-4096 +[ 0-9a-f]+: 7c35002c lbe \$21,0\(\$1\) +[ 0-9a-f]+: 2401f000 li \$1,-4096 +[ 0-9a-f]+: 7c37002c lbe \$23,0\(\$1\) +[ 0-9a-f]+: 27210fff addiu \$1,\$25,4095 +[ 0-9a-f]+: 7c38002c lbe \$24,0\(\$1\) +[ 0-9a-f]+: 24010fff li \$1,4095 +[ 0-9a-f]+: 7c3a002c lbe \$26,0\(\$1\) +[ 0-9a-f]+: 27818000 addiu \$1,\$28,-32768 +[ 0-9a-f]+: 7c3b002c lbe \$27,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c3d002c lbe \$29,0\(\$1\) +[ 0-9a-f]+: 27e17fff addiu \$1,\$31,32767 +[ 0-9a-f]+: 7c3e002c lbe \$30,0\(\$1\) +[ 0-9a-f]+: 24017fff li \$1,32767 +[ 0-9a-f]+: 7c20002c lbe \$0,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 00230821 addu \$1,\$1,\$3 +[ 0-9a-f]+: 7c22ffac lbe \$2,-1\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c24ffac lbe \$4,-1\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 00260821 addu \$1,\$1,\$6 +[ 0-9a-f]+: 7c25002c lbe \$5,0\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 7c27002c lbe \$7,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 00290821 addu \$1,\$1,\$9 +[ 0-9a-f]+: 7c28002c lbe \$8,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c2a002c lbe \$10,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 002c0821 addu \$1,\$1,\$12 +[ 0-9a-f]+: 7c2bffac lbe \$11,-1\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c2dffac lbe \$13,-1\(\$1\) +[ 0-9a-f]+: 7dee002c lbe \$14,0\(\$15\) +[ 0-9a-f]+: 3c010000 lui \$1,0x0 + [ 0-9a-f]+: R_MIPS_HI16 MYDATA +[ 0-9a-f]+: 24210000 addiu \$1,\$1,0 + [ 0-9a-f]+: R_MIPS_LO16 MYDATA +[ 0-9a-f]+: 7c30002c lbe \$16,0\(\$1\) +[ 0-9a-f]+: 7e51802d lhe \$17,-256\(\$18\) +[ 0-9a-f]+: 7c13802d lhe \$19,-256\(\$0\) +[ 0-9a-f]+: 7eb47fad lhe \$20,255\(\$21\) +[ 0-9a-f]+: 7c167fad lhe \$22,255\(\$0\) +[ 0-9a-f]+: 2701feff addiu \$1,\$24,-257 +[ 0-9a-f]+: 7c37002d lhe \$23,0\(\$1\) +[ 0-9a-f]+: 2401feff li \$1,-257 +[ 0-9a-f]+: 7c39002d lhe \$25,0\(\$1\) +[ 0-9a-f]+: 27610100 addiu \$1,\$27,256 +[ 0-9a-f]+: 7c3a002d lhe \$26,0\(\$1\) +[ 0-9a-f]+: 24010100 li \$1,256 +[ 0-9a-f]+: 7c3c002d lhe \$28,0\(\$1\) +[ 0-9a-f]+: 27c1fe00 addiu \$1,\$30,-512 +[ 0-9a-f]+: 7c3d002d lhe \$29,0\(\$1\) +[ 0-9a-f]+: 2401fe00 li \$1,-512 +[ 0-9a-f]+: 7c3f002d lhe \$31,0\(\$1\) +[ 0-9a-f]+: 244101ff addiu \$1,\$2,511 +[ 0-9a-f]+: 7c20002d lhe \$0,0\(\$1\) +[ 0-9a-f]+: 240101ff li \$1,511 +[ 0-9a-f]+: 7c23002d lhe \$3,0\(\$1\) +[ 0-9a-f]+: 24a1fc00 addiu \$1,\$5,-1024 +[ 0-9a-f]+: 7c24002d lhe \$4,0\(\$1\) +[ 0-9a-f]+: 2401fc00 li \$1,-1024 +[ 0-9a-f]+: 7c26002d lhe \$6,0\(\$1\) +[ 0-9a-f]+: 250103ff addiu \$1,\$8,1023 +[ 0-9a-f]+: 7c27002d lhe \$7,0\(\$1\) +[ 0-9a-f]+: 240103ff li \$1,1023 +[ 0-9a-f]+: 7c29002d lhe \$9,0\(\$1\) +[ 0-9a-f]+: 2561f800 addiu \$1,\$11,-2048 +[ 0-9a-f]+: 7c2a002d lhe \$10,0\(\$1\) +[ 0-9a-f]+: 2401f800 li \$1,-2048 +[ 0-9a-f]+: 7c2c002d lhe \$12,0\(\$1\) +[ 0-9a-f]+: 25c107ff addiu \$1,\$14,2047 +[ 0-9a-f]+: 7c2d002d lhe \$13,0\(\$1\) +[ 0-9a-f]+: 240107ff li \$1,2047 +[ 0-9a-f]+: 7c2f002d lhe \$15,0\(\$1\) +[ 0-9a-f]+: 2621f000 addiu \$1,\$17,-4096 +[ 0-9a-f]+: 7c30002d lhe \$16,0\(\$1\) +[ 0-9a-f]+: 2401f000 li \$1,-4096 +[ 0-9a-f]+: 7c32002d lhe \$18,0\(\$1\) +[ 0-9a-f]+: 26810fff addiu \$1,\$20,4095 +[ 0-9a-f]+: 7c33002d lhe \$19,0\(\$1\) +[ 0-9a-f]+: 24010fff li \$1,4095 +[ 0-9a-f]+: 7c35002d lhe \$21,0\(\$1\) +[ 0-9a-f]+: 26e18000 addiu \$1,\$23,-32768 +[ 0-9a-f]+: 7c36002d lhe \$22,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c38002d lhe \$24,0\(\$1\) +[ 0-9a-f]+: 27417fff addiu \$1,\$26,32767 +[ 0-9a-f]+: 7c39002d lhe \$25,0\(\$1\) +[ 0-9a-f]+: 24017fff li \$1,32767 +[ 0-9a-f]+: 7c3b002d lhe \$27,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 003d0821 addu \$1,\$1,\$29 +[ 0-9a-f]+: 7c3cffad lhe \$28,-1\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c3effad lhe \$30,-1\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 7c3f002d lhe \$31,0\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 7c22002d lhe \$2,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 00240821 addu \$1,\$1,\$4 +[ 0-9a-f]+: 7c23002d lhe \$3,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c25002d lhe \$5,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 00270821 addu \$1,\$1,\$7 +[ 0-9a-f]+: 7c26ffad lhe \$6,-1\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c28ffad lhe \$8,-1\(\$1\) +[ 0-9a-f]+: 7d49002d lhe \$9,0\(\$10\) +[ 0-9a-f]+: 3c010000 lui \$1,0x0 + [ 0-9a-f]+: R_MIPS_HI16 MYDATA +[ 0-9a-f]+: 24210000 addiu \$1,\$1,0 + [ 0-9a-f]+: R_MIPS_LO16 MYDATA +[ 0-9a-f]+: 7c2b002d lhe \$11,0\(\$1\) +[ 0-9a-f]+: 7dac802e lle \$12,-256\(\$13\) +[ 0-9a-f]+: 7c0e802e lle \$14,-256\(\$0\) +[ 0-9a-f]+: 7e0f7fae lle \$15,255\(\$16\) +[ 0-9a-f]+: 7c117fae lle \$17,255\(\$0\) +[ 0-9a-f]+: 2661feff addiu \$1,\$19,-257 +[ 0-9a-f]+: 7c32002e lle \$18,0\(\$1\) +[ 0-9a-f]+: 2401feff li \$1,-257 +[ 0-9a-f]+: 7c34002e lle \$20,0\(\$1\) +[ 0-9a-f]+: 26c10100 addiu \$1,\$22,256 +[ 0-9a-f]+: 7c35002e lle \$21,0\(\$1\) +[ 0-9a-f]+: 24010100 li \$1,256 +[ 0-9a-f]+: 7c37002e lle \$23,0\(\$1\) +[ 0-9a-f]+: 2721fe00 addiu \$1,\$25,-512 +[ 0-9a-f]+: 7c38002e lle \$24,0\(\$1\) +[ 0-9a-f]+: 2401fe00 li \$1,-512 +[ 0-9a-f]+: 7c3a002e lle \$26,0\(\$1\) +[ 0-9a-f]+: 278101ff addiu \$1,\$28,511 +[ 0-9a-f]+: 7c3b002e lle \$27,0\(\$1\) +[ 0-9a-f]+: 240101ff li \$1,511 +[ 0-9a-f]+: 7c3d002e lle \$29,0\(\$1\) +[ 0-9a-f]+: 27e1fc00 addiu \$1,\$31,-1024 +[ 0-9a-f]+: 7c3e002e lle \$30,0\(\$1\) +[ 0-9a-f]+: 2401fc00 li \$1,-1024 +[ 0-9a-f]+: 7c20002e lle \$0,0\(\$1\) +[ 0-9a-f]+: 246103ff addiu \$1,\$3,1023 +[ 0-9a-f]+: 7c22002e lle \$2,0\(\$1\) +[ 0-9a-f]+: 240103ff li \$1,1023 +[ 0-9a-f]+: 7c24002e lle \$4,0\(\$1\) +[ 0-9a-f]+: 24c1f800 addiu \$1,\$6,-2048 +[ 0-9a-f]+: 7c25002e lle \$5,0\(\$1\) +[ 0-9a-f]+: 2401f800 li \$1,-2048 +[ 0-9a-f]+: 7c27002e lle \$7,0\(\$1\) +[ 0-9a-f]+: 252107ff addiu \$1,\$9,2047 +[ 0-9a-f]+: 7c28002e lle \$8,0\(\$1\) +[ 0-9a-f]+: 240107ff li \$1,2047 +[ 0-9a-f]+: 7c2a002e lle \$10,0\(\$1\) +[ 0-9a-f]+: 2581f000 addiu \$1,\$12,-4096 +[ 0-9a-f]+: 7c2b002e lle \$11,0\(\$1\) +[ 0-9a-f]+: 2401f000 li \$1,-4096 +[ 0-9a-f]+: 7c2d002e lle \$13,0\(\$1\) +[ 0-9a-f]+: 25e10fff addiu \$1,\$15,4095 +[ 0-9a-f]+: 7c2e002e lle \$14,0\(\$1\) +[ 0-9a-f]+: 24010fff li \$1,4095 +[ 0-9a-f]+: 7c30002e lle \$16,0\(\$1\) +[ 0-9a-f]+: 26418000 addiu \$1,\$18,-32768 +[ 0-9a-f]+: 7c31002e lle \$17,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c33002e lle \$19,0\(\$1\) +[ 0-9a-f]+: 26a17fff addiu \$1,\$21,32767 +[ 0-9a-f]+: 7c34002e lle \$20,0\(\$1\) +[ 0-9a-f]+: 24017fff li \$1,32767 +[ 0-9a-f]+: 7c36002e lle \$22,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 00380821 addu \$1,\$1,\$24 +[ 0-9a-f]+: 7c37ffae lle \$23,-1\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c39ffae lle \$25,-1\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 003b0821 addu \$1,\$1,\$27 +[ 0-9a-f]+: 7c3a002e lle \$26,0\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 7c3c002e lle \$28,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 003e0821 addu \$1,\$1,\$30 +[ 0-9a-f]+: 7c3d002e lle \$29,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c3f002e lle \$31,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 00220821 addu \$1,\$1,\$2 +[ 0-9a-f]+: 7c20ffae lle \$0,-1\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c23ffae lle \$3,-1\(\$1\) +[ 0-9a-f]+: 7ca4002e lle \$4,0\(\$5\) +[ 0-9a-f]+: 3c010000 lui \$1,0x0 + [ 0-9a-f]+: R_MIPS_HI16 MYDATA +[ 0-9a-f]+: 24210000 addiu \$1,\$1,0 + [ 0-9a-f]+: R_MIPS_LO16 MYDATA +[ 0-9a-f]+: 7c26002e lle \$6,0\(\$1\) +[ 0-9a-f]+: 7d07802f lwe \$7,-256\(\$8\) +[ 0-9a-f]+: 7c09802f lwe \$9,-256\(\$0\) +[ 0-9a-f]+: 7d6a7faf lwe \$10,255\(\$11\) +[ 0-9a-f]+: 7c0c7faf lwe \$12,255\(\$0\) +[ 0-9a-f]+: 25c1feff addiu \$1,\$14,-257 +[ 0-9a-f]+: 7c2d002f lwe \$13,0\(\$1\) +[ 0-9a-f]+: 2401feff li \$1,-257 +[ 0-9a-f]+: 7c2f002f lwe \$15,0\(\$1\) +[ 0-9a-f]+: 26210100 addiu \$1,\$17,256 +[ 0-9a-f]+: 7c30002f lwe \$16,0\(\$1\) +[ 0-9a-f]+: 24010100 li \$1,256 +[ 0-9a-f]+: 7c32002f lwe \$18,0\(\$1\) +[ 0-9a-f]+: 2681fe00 addiu \$1,\$20,-512 +[ 0-9a-f]+: 7c33002f lwe \$19,0\(\$1\) +[ 0-9a-f]+: 2401fe00 li \$1,-512 +[ 0-9a-f]+: 7c35002f lwe \$21,0\(\$1\) +[ 0-9a-f]+: 26e101ff addiu \$1,\$23,511 +[ 0-9a-f]+: 7c36002f lwe \$22,0\(\$1\) +[ 0-9a-f]+: 240101ff li \$1,511 +[ 0-9a-f]+: 7c38002f lwe \$24,0\(\$1\) +[ 0-9a-f]+: 2741fc00 addiu \$1,\$26,-1024 +[ 0-9a-f]+: 7c39002f lwe \$25,0\(\$1\) +[ 0-9a-f]+: 2401fc00 li \$1,-1024 +[ 0-9a-f]+: 7c3b002f lwe \$27,0\(\$1\) +[ 0-9a-f]+: 27a103ff addiu \$1,\$29,1023 +[ 0-9a-f]+: 7c3c002f lwe \$28,0\(\$1\) +[ 0-9a-f]+: 240103ff li \$1,1023 +[ 0-9a-f]+: 7c3e002f lwe \$30,0\(\$1\) +[ 0-9a-f]+: 2401f800 li \$1,-2048 +[ 0-9a-f]+: 7c3f002f lwe \$31,0\(\$1\) +[ 0-9a-f]+: 2401f800 li \$1,-2048 +[ 0-9a-f]+: 7c22002f lwe \$2,0\(\$1\) +[ 0-9a-f]+: 248107ff addiu \$1,\$4,2047 +[ 0-9a-f]+: 7c23002f lwe \$3,0\(\$1\) +[ 0-9a-f]+: 240107ff li \$1,2047 +[ 0-9a-f]+: 7c25002f lwe \$5,0\(\$1\) +[ 0-9a-f]+: 24e1f000 addiu \$1,\$7,-4096 +[ 0-9a-f]+: 7c26002f lwe \$6,0\(\$1\) +[ 0-9a-f]+: 2401f000 li \$1,-4096 +[ 0-9a-f]+: 7c28002f lwe \$8,0\(\$1\) +[ 0-9a-f]+: 25410fff addiu \$1,\$10,4095 +[ 0-9a-f]+: 7c29002f lwe \$9,0\(\$1\) +[ 0-9a-f]+: 24010fff li \$1,4095 +[ 0-9a-f]+: 7c2b002f lwe \$11,0\(\$1\) +[ 0-9a-f]+: 25a18000 addiu \$1,\$13,-32768 +[ 0-9a-f]+: 7c2c002f lwe \$12,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c2e002f lwe \$14,0\(\$1\) +[ 0-9a-f]+: 26017fff addiu \$1,\$16,32767 +[ 0-9a-f]+: 7c2f002f lwe \$15,0\(\$1\) +[ 0-9a-f]+: 24017fff li \$1,32767 +[ 0-9a-f]+: 7c31002f lwe \$17,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 00330821 addu \$1,\$1,\$19 +[ 0-9a-f]+: 7c32ffaf lwe \$18,-1\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c34ffaf lwe \$20,-1\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 00360821 addu \$1,\$1,\$22 +[ 0-9a-f]+: 7c35002f lwe \$21,0\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 7c37002f lwe \$23,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 00390821 addu \$1,\$1,\$25 +[ 0-9a-f]+: 7c38002f lwe \$24,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c3a002f lwe \$26,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 003c0821 addu \$1,\$1,\$28 +[ 0-9a-f]+: 7c3bffaf lwe \$27,-1\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c3dffaf lwe \$29,-1\(\$1\) +[ 0-9a-f]+: 7ffe002f lwe \$30,0\(\$31\) +[ 0-9a-f]+: 3c010000 lui \$1,0x0 + [ 0-9a-f]+: R_MIPS_HI16 MYDATA +[ 0-9a-f]+: 24210000 addiu \$1,\$1,0 + [ 0-9a-f]+: R_MIPS_LO16 MYDATA +[ 0-9a-f]+: 7c20002f lwe \$0,0\(\$1\) +[ 0-9a-f]+: 7f17801c sbe \$23,-256\(\$24\) +[ 0-9a-f]+: 7c19801c sbe \$25,-256\(\$0\) +[ 0-9a-f]+: 7f7a7f9c sbe \$26,255\(\$27\) +[ 0-9a-f]+: 7c1c7f9c sbe \$28,255\(\$0\) +[ 0-9a-f]+: 27c1feff addiu \$1,\$30,-257 +[ 0-9a-f]+: 7c3d001c sbe \$29,0\(\$1\) +[ 0-9a-f]+: 2401feff li \$1,-257 +[ 0-9a-f]+: 7c3f001c sbe \$31,0\(\$1\) +[ 0-9a-f]+: 24410100 addiu \$1,\$2,256 +[ 0-9a-f]+: 7c20001c sbe \$0,0\(\$1\) +[ 0-9a-f]+: 24010100 li \$1,256 +[ 0-9a-f]+: 7c23001c sbe \$3,0\(\$1\) +[ 0-9a-f]+: 24a1fe00 addiu \$1,\$5,-512 +[ 0-9a-f]+: 7c24001c sbe \$4,0\(\$1\) +[ 0-9a-f]+: 2401fe00 li \$1,-512 +[ 0-9a-f]+: 7c26001c sbe \$6,0\(\$1\) +[ 0-9a-f]+: 250101ff addiu \$1,\$8,511 +[ 0-9a-f]+: 7c27001c sbe \$7,0\(\$1\) +[ 0-9a-f]+: 240101ff li \$1,511 +[ 0-9a-f]+: 7c29001c sbe \$9,0\(\$1\) +[ 0-9a-f]+: 2561fc00 addiu \$1,\$11,-1024 +[ 0-9a-f]+: 7c2a001c sbe \$10,0\(\$1\) +[ 0-9a-f]+: 2401fc00 li \$1,-1024 +[ 0-9a-f]+: 7c2c001c sbe \$12,0\(\$1\) +[ 0-9a-f]+: 25c103ff addiu \$1,\$14,1023 +[ 0-9a-f]+: 7c2d001c sbe \$13,0\(\$1\) +[ 0-9a-f]+: 240103ff li \$1,1023 +[ 0-9a-f]+: 7c2f001c sbe \$15,0\(\$1\) +[ 0-9a-f]+: 2621f800 addiu \$1,\$17,-2048 +[ 0-9a-f]+: 7c30001c sbe \$16,0\(\$1\) +[ 0-9a-f]+: 2401f800 li \$1,-2048 +[ 0-9a-f]+: 7c32001c sbe \$18,0\(\$1\) +[ 0-9a-f]+: 268107ff addiu \$1,\$20,2047 +[ 0-9a-f]+: 7c33001c sbe \$19,0\(\$1\) +[ 0-9a-f]+: 240107ff li \$1,2047 +[ 0-9a-f]+: 7c35001c sbe \$21,0\(\$1\) +[ 0-9a-f]+: 26e1f000 addiu \$1,\$23,-4096 +[ 0-9a-f]+: 7c36001c sbe \$22,0\(\$1\) +[ 0-9a-f]+: 2401f000 li \$1,-4096 +[ 0-9a-f]+: 7c38001c sbe \$24,0\(\$1\) +[ 0-9a-f]+: 27410fff addiu \$1,\$26,4095 +[ 0-9a-f]+: 7c39001c sbe \$25,0\(\$1\) +[ 0-9a-f]+: 24010fff li \$1,4095 +[ 0-9a-f]+: 7c3b001c sbe \$27,0\(\$1\) +[ 0-9a-f]+: 27a18000 addiu \$1,\$29,-32768 +[ 0-9a-f]+: 7c3c001c sbe \$28,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c3e001c sbe \$30,0\(\$1\) +[ 0-9a-f]+: 24017fff li \$1,32767 +[ 0-9a-f]+: 7c3f001c sbe \$31,0\(\$1\) +[ 0-9a-f]+: 24017fff li \$1,32767 +[ 0-9a-f]+: 7c22001c sbe \$2,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 00240821 addu \$1,\$1,\$4 +[ 0-9a-f]+: 7c23ff9c sbe \$3,-1\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c25ff9c sbe \$5,-1\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 00270821 addu \$1,\$1,\$7 +[ 0-9a-f]+: 7c26001c sbe \$6,0\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 7c28001c sbe \$8,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 002a0821 addu \$1,\$1,\$10 +[ 0-9a-f]+: 7c29001c sbe \$9,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c2b001c sbe \$11,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 002d0821 addu \$1,\$1,\$13 +[ 0-9a-f]+: 7c2cff9c sbe \$12,-1\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c2eff9c sbe \$14,-1\(\$1\) +[ 0-9a-f]+: 7e0f001c sbe \$15,0\(\$16\) +[ 0-9a-f]+: 3c010000 lui \$1,0x0 + [ 0-9a-f]+: R_MIPS_HI16 MYDATA +[ 0-9a-f]+: 24210000 addiu \$1,\$1,0 + [ 0-9a-f]+: R_MIPS_LO16 MYDATA +[ 0-9a-f]+: 7c31001c sbe \$17,0\(\$1\) +[ 0-9a-f]+: 7e72801e sce \$18,-256\(\$19\) +[ 0-9a-f]+: 7c14801e sce \$20,-256\(\$0\) +[ 0-9a-f]+: 7ed57f9e sce \$21,255\(\$22\) +[ 0-9a-f]+: 7c177f9e sce \$23,255\(\$0\) +[ 0-9a-f]+: 2721feff addiu \$1,\$25,-257 +[ 0-9a-f]+: 7c38001e sce \$24,0\(\$1\) +[ 0-9a-f]+: 2401feff li \$1,-257 +[ 0-9a-f]+: 7c3a001e sce \$26,0\(\$1\) +[ 0-9a-f]+: 27810100 addiu \$1,\$28,256 +[ 0-9a-f]+: 7c3b001e sce \$27,0\(\$1\) +[ 0-9a-f]+: 24010100 li \$1,256 +[ 0-9a-f]+: 7c3d001e sce \$29,0\(\$1\) +[ 0-9a-f]+: 27e1fe00 addiu \$1,\$31,-512 +[ 0-9a-f]+: 7c3e001e sce \$30,0\(\$1\) +[ 0-9a-f]+: 2401fe00 li \$1,-512 +[ 0-9a-f]+: 7c20001e sce \$0,0\(\$1\) +[ 0-9a-f]+: 246101ff addiu \$1,\$3,511 +[ 0-9a-f]+: 7c22001e sce \$2,0\(\$1\) +[ 0-9a-f]+: 240101ff li \$1,511 +[ 0-9a-f]+: 7c24001e sce \$4,0\(\$1\) +[ 0-9a-f]+: 24c1fc00 addiu \$1,\$6,-1024 +[ 0-9a-f]+: 7c25001e sce \$5,0\(\$1\) +[ 0-9a-f]+: 2401fc00 li \$1,-1024 +[ 0-9a-f]+: 7c27001e sce \$7,0\(\$1\) +[ 0-9a-f]+: 252103ff addiu \$1,\$9,1023 +[ 0-9a-f]+: 7c28001e sce \$8,0\(\$1\) +[ 0-9a-f]+: 240103ff li \$1,1023 +[ 0-9a-f]+: 7c2a001e sce \$10,0\(\$1\) +[ 0-9a-f]+: 2581f800 addiu \$1,\$12,-2048 +[ 0-9a-f]+: 7c2b001e sce \$11,0\(\$1\) +[ 0-9a-f]+: 2401f800 li \$1,-2048 +[ 0-9a-f]+: 7c2d001e sce \$13,0\(\$1\) +[ 0-9a-f]+: 25e107ff addiu \$1,\$15,2047 +[ 0-9a-f]+: 7c2e001e sce \$14,0\(\$1\) +[ 0-9a-f]+: 240107ff li \$1,2047 +[ 0-9a-f]+: 7c30001e sce \$16,0\(\$1\) +[ 0-9a-f]+: 2641f000 addiu \$1,\$18,-4096 +[ 0-9a-f]+: 7c31001e sce \$17,0\(\$1\) +[ 0-9a-f]+: 2401f000 li \$1,-4096 +[ 0-9a-f]+: 7c33001e sce \$19,0\(\$1\) +[ 0-9a-f]+: 26a10fff addiu \$1,\$21,4095 +[ 0-9a-f]+: 7c34001e sce \$20,0\(\$1\) +[ 0-9a-f]+: 24010fff li \$1,4095 +[ 0-9a-f]+: 7c36001e sce \$22,0\(\$1\) +[ 0-9a-f]+: 27018000 addiu \$1,\$24,-32768 +[ 0-9a-f]+: 7c37001e sce \$23,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c39001e sce \$25,0\(\$1\) +[ 0-9a-f]+: 27617fff addiu \$1,\$27,32767 +[ 0-9a-f]+: 7c3a001e sce \$26,0\(\$1\) +[ 0-9a-f]+: 24017fff li \$1,32767 +[ 0-9a-f]+: 7c3c001e sce \$28,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 003e0821 addu \$1,\$1,\$30 +[ 0-9a-f]+: 7c3dff9e sce \$29,-1\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c3fff9e sce \$31,-1\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 00220821 addu \$1,\$1,\$2 +[ 0-9a-f]+: 7c20001e sce \$0,0\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 7c23001e sce \$3,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 00250821 addu \$1,\$1,\$5 +[ 0-9a-f]+: 7c24001e sce \$4,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c26001e sce \$6,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 00280821 addu \$1,\$1,\$8 +[ 0-9a-f]+: 7c27ff9e sce \$7,-1\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c29ff9e sce \$9,-1\(\$1\) +[ 0-9a-f]+: 7d6a001e sce \$10,0\(\$11\) +[ 0-9a-f]+: 3c010000 lui \$1,0x0 + [ 0-9a-f]+: R_MIPS_HI16 MYDATA +[ 0-9a-f]+: 24210000 addiu \$1,\$1,0 + [ 0-9a-f]+: R_MIPS_LO16 MYDATA +[ 0-9a-f]+: 7c2c001e sce \$12,0\(\$1\) +[ 0-9a-f]+: 7dcd801d she \$13,-256\(\$14\) +[ 0-9a-f]+: 7c0f801d she \$15,-256\(\$0\) +[ 0-9a-f]+: 7e307f9d she \$16,255\(\$17\) +[ 0-9a-f]+: 7c127f9d she \$18,255\(\$0\) +[ 0-9a-f]+: 2681feff addiu \$1,\$20,-257 +[ 0-9a-f]+: 7c33001d she \$19,0\(\$1\) +[ 0-9a-f]+: 2401feff li \$1,-257 +[ 0-9a-f]+: 7c35001d she \$21,0\(\$1\) +[ 0-9a-f]+: 26e10100 addiu \$1,\$23,256 +[ 0-9a-f]+: 7c36001d she \$22,0\(\$1\) +[ 0-9a-f]+: 24010100 li \$1,256 +[ 0-9a-f]+: 7c38001d she \$24,0\(\$1\) +[ 0-9a-f]+: 2741fe00 addiu \$1,\$26,-512 +[ 0-9a-f]+: 7c39001d she \$25,0\(\$1\) +[ 0-9a-f]+: 2401fe00 li \$1,-512 +[ 0-9a-f]+: 7c3b001d she \$27,0\(\$1\) +[ 0-9a-f]+: 27a101ff addiu \$1,\$29,511 +[ 0-9a-f]+: 7c3c001d she \$28,0\(\$1\) +[ 0-9a-f]+: 240101ff li \$1,511 +[ 0-9a-f]+: 7c3e001d she \$30,0\(\$1\) +[ 0-9a-f]+: 2401fc00 li \$1,-1024 +[ 0-9a-f]+: 7c3f001d she \$31,0\(\$1\) +[ 0-9a-f]+: 2401fc00 li \$1,-1024 +[ 0-9a-f]+: 7c22001d she \$2,0\(\$1\) +[ 0-9a-f]+: 248103ff addiu \$1,\$4,1023 +[ 0-9a-f]+: 7c23001d she \$3,0\(\$1\) +[ 0-9a-f]+: 240103ff li \$1,1023 +[ 0-9a-f]+: 7c25001d she \$5,0\(\$1\) +[ 0-9a-f]+: 24e1f800 addiu \$1,\$7,-2048 +[ 0-9a-f]+: 7c26001d she \$6,0\(\$1\) +[ 0-9a-f]+: 2401f800 li \$1,-2048 +[ 0-9a-f]+: 7c28001d she \$8,0\(\$1\) +[ 0-9a-f]+: 254107ff addiu \$1,\$10,2047 +[ 0-9a-f]+: 7c29001d she \$9,0\(\$1\) +[ 0-9a-f]+: 240107ff li \$1,2047 +[ 0-9a-f]+: 7c2b001d she \$11,0\(\$1\) +[ 0-9a-f]+: 25a1f000 addiu \$1,\$13,-4096 +[ 0-9a-f]+: 7c2c001d she \$12,0\(\$1\) +[ 0-9a-f]+: 2401f000 li \$1,-4096 +[ 0-9a-f]+: 7c2e001d she \$14,0\(\$1\) +[ 0-9a-f]+: 26010fff addiu \$1,\$16,4095 +[ 0-9a-f]+: 7c2f001d she \$15,0\(\$1\) +[ 0-9a-f]+: 24010fff li \$1,4095 +[ 0-9a-f]+: 7c31001d she \$17,0\(\$1\) +[ 0-9a-f]+: 26618000 addiu \$1,\$19,-32768 +[ 0-9a-f]+: 7c32001d she \$18,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c34001d she \$20,0\(\$1\) +[ 0-9a-f]+: 26c17fff addiu \$1,\$22,32767 +[ 0-9a-f]+: 7c35001d she \$21,0\(\$1\) +[ 0-9a-f]+: 24017fff li \$1,32767 +[ 0-9a-f]+: 7c37001d she \$23,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 00390821 addu \$1,\$1,\$25 +[ 0-9a-f]+: 7c38ff9d she \$24,-1\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c3aff9d she \$26,-1\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 003c0821 addu \$1,\$1,\$28 +[ 0-9a-f]+: 7c3b001d she \$27,0\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 7c3d001d she \$29,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 003f0821 addu \$1,\$1,\$31 +[ 0-9a-f]+: 7c3e001d she \$30,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c20001d she \$0,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 00230821 addu \$1,\$1,\$3 +[ 0-9a-f]+: 7c22ff9d she \$2,-1\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c24ff9d she \$4,-1\(\$1\) +[ 0-9a-f]+: 7cc5001d she \$5,0\(\$6\) +[ 0-9a-f]+: 3c010000 lui \$1,0x0 + [ 0-9a-f]+: R_MIPS_HI16 MYDATA +[ 0-9a-f]+: 24210000 addiu \$1,\$1,0 + [ 0-9a-f]+: R_MIPS_LO16 MYDATA +[ 0-9a-f]+: 7c27001d she \$7,0\(\$1\) +[ 0-9a-f]+: 7d28801f swe \$8,-256\(\$9\) +[ 0-9a-f]+: 7c0a801f swe \$10,-256\(\$0\) +[ 0-9a-f]+: 7d8b7f9f swe \$11,255\(\$12\) +[ 0-9a-f]+: 7c0d7f9f swe \$13,255\(\$0\) +[ 0-9a-f]+: 25e1feff addiu \$1,\$15,-257 +[ 0-9a-f]+: 7c2e001f swe \$14,0\(\$1\) +[ 0-9a-f]+: 2401feff li \$1,-257 +[ 0-9a-f]+: 7c30001f swe \$16,0\(\$1\) +[ 0-9a-f]+: 26410100 addiu \$1,\$18,256 +[ 0-9a-f]+: 7c31001f swe \$17,0\(\$1\) +[ 0-9a-f]+: 24010100 li \$1,256 +[ 0-9a-f]+: 7c33001f swe \$19,0\(\$1\) +[ 0-9a-f]+: 26a1fe00 addiu \$1,\$21,-512 +[ 0-9a-f]+: 7c34001f swe \$20,0\(\$1\) +[ 0-9a-f]+: 2401fe00 li \$1,-512 +[ 0-9a-f]+: 7c36001f swe \$22,0\(\$1\) +[ 0-9a-f]+: 270101ff addiu \$1,\$24,511 +[ 0-9a-f]+: 7c37001f swe \$23,0\(\$1\) +[ 0-9a-f]+: 240101ff li \$1,511 +[ 0-9a-f]+: 7c39001f swe \$25,0\(\$1\) +[ 0-9a-f]+: 2761fc00 addiu \$1,\$27,-1024 +[ 0-9a-f]+: 7c3a001f swe \$26,0\(\$1\) +[ 0-9a-f]+: 2401fc00 li \$1,-1024 +[ 0-9a-f]+: 7c3c001f swe \$28,0\(\$1\) +[ 0-9a-f]+: 27c103ff addiu \$1,\$30,1023 +[ 0-9a-f]+: 7c3d001f swe \$29,0\(\$1\) +[ 0-9a-f]+: 240103ff li \$1,1023 +[ 0-9a-f]+: 7c3f001f swe \$31,0\(\$1\) +[ 0-9a-f]+: 2441f800 addiu \$1,\$2,-2048 +[ 0-9a-f]+: 7c20001f swe \$0,0\(\$1\) +[ 0-9a-f]+: 2401f800 li \$1,-2048 +[ 0-9a-f]+: 7c23001f swe \$3,0\(\$1\) +[ 0-9a-f]+: 24a107ff addiu \$1,\$5,2047 +[ 0-9a-f]+: 7c24001f swe \$4,0\(\$1\) +[ 0-9a-f]+: 240107ff li \$1,2047 +[ 0-9a-f]+: 7c26001f swe \$6,0\(\$1\) +[ 0-9a-f]+: 2501f000 addiu \$1,\$8,-4096 +[ 0-9a-f]+: 7c27001f swe \$7,0\(\$1\) +[ 0-9a-f]+: 2401f000 li \$1,-4096 +[ 0-9a-f]+: 7c29001f swe \$9,0\(\$1\) +[ 0-9a-f]+: 25610fff addiu \$1,\$11,4095 +[ 0-9a-f]+: 7c2a001f swe \$10,0\(\$1\) +[ 0-9a-f]+: 24010fff li \$1,4095 +[ 0-9a-f]+: 7c2c001f swe \$12,0\(\$1\) +[ 0-9a-f]+: 25c18000 addiu \$1,\$14,-32768 +[ 0-9a-f]+: 7c2d001f swe \$13,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c2f001f swe \$15,0\(\$1\) +[ 0-9a-f]+: 26217fff addiu \$1,\$17,32767 +[ 0-9a-f]+: 7c30001f swe \$16,0\(\$1\) +[ 0-9a-f]+: 24017fff li \$1,32767 +[ 0-9a-f]+: 7c32001f swe \$18,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 00340821 addu \$1,\$1,\$20 +[ 0-9a-f]+: 7c33ff9f swe \$19,-1\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c35ff9f swe \$21,-1\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 00370821 addu \$1,\$1,\$23 +[ 0-9a-f]+: 7c36001f swe \$22,0\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 7c38001f swe \$24,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 003a0821 addu \$1,\$1,\$26 +[ 0-9a-f]+: 7c39001f swe \$25,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c3b001f swe \$27,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 003d0821 addu \$1,\$1,\$29 +[ 0-9a-f]+: 7c3cff9f swe \$28,-1\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c3eff9f swe \$30,-1\(\$1\) +[ 0-9a-f]+: 7c1f001f swe \$31,0\(\$0\) +[ 0-9a-f]+: 3c010000 lui \$1,0x0 + [ 0-9a-f]+: R_MIPS_HI16 MYDATA +[ 0-9a-f]+: 24210000 addiu \$1,\$1,0 + [ 0-9a-f]+: R_MIPS_LO16 MYDATA +[ 0-9a-f]+: 7c22001f swe \$2,0\(\$1\) +[ 0-9a-f]+: 7f38801b cachee 0x18,-256\(\$25\) +[ 0-9a-f]+: 7c1a801b cachee 0x1a,-256\(\$0\) +[ 0-9a-f]+: 7f9b7f9b cachee 0x1b,255\(\$28\) +[ 0-9a-f]+: 7c1d7f9b cachee 0x1d,255\(\$0\) +[ 0-9a-f]+: 27e1feff addiu \$1,\$31,-257 +[ 0-9a-f]+: 7c3e001b cachee 0x1e,0\(\$1\) +[ 0-9a-f]+: 2401feff li \$1,-257 +[ 0-9a-f]+: 7c20001b cachee 0x0,0\(\$1\) +[ 0-9a-f]+: 24610100 addiu \$1,\$3,256 +[ 0-9a-f]+: 7c22001b cachee 0x2,0\(\$1\) +[ 0-9a-f]+: 24010100 li \$1,256 +[ 0-9a-f]+: 7c24001b cachee 0x4,0\(\$1\) +[ 0-9a-f]+: 24c1fe00 addiu \$1,\$6,-512 +[ 0-9a-f]+: 7c25001b cachee 0x5,0\(\$1\) +[ 0-9a-f]+: 2401fe00 li \$1,-512 +[ 0-9a-f]+: 7c27001b cachee 0x7,0\(\$1\) +[ 0-9a-f]+: 252101ff addiu \$1,\$9,511 +[ 0-9a-f]+: 7c28001b cachee 0x8,0\(\$1\) +[ 0-9a-f]+: 240101ff li \$1,511 +[ 0-9a-f]+: 7c2a001b cachee 0xa,0\(\$1\) +[ 0-9a-f]+: 2581fc00 addiu \$1,\$12,-1024 +[ 0-9a-f]+: 7c2b001b cachee 0xb,0\(\$1\) +[ 0-9a-f]+: 2401fc00 li \$1,-1024 +[ 0-9a-f]+: 7c2d001b cachee 0xd,0\(\$1\) +[ 0-9a-f]+: 25e103ff addiu \$1,\$15,1023 +[ 0-9a-f]+: 7c2e001b cachee 0xe,0\(\$1\) +[ 0-9a-f]+: 240103ff li \$1,1023 +[ 0-9a-f]+: 7c30001b cachee 0x10,0\(\$1\) +[ 0-9a-f]+: 2641f800 addiu \$1,\$18,-2048 +[ 0-9a-f]+: 7c31001b cachee 0x11,0\(\$1\) +[ 0-9a-f]+: 2401f800 li \$1,-2048 +[ 0-9a-f]+: 7c33001b cachee 0x13,0\(\$1\) +[ 0-9a-f]+: 26a107ff addiu \$1,\$21,2047 +[ 0-9a-f]+: 7c34001b cachee 0x14,0\(\$1\) +[ 0-9a-f]+: 240107ff li \$1,2047 +[ 0-9a-f]+: 7c36001b cachee 0x16,0\(\$1\) +[ 0-9a-f]+: 2701f000 addiu \$1,\$24,-4096 +[ 0-9a-f]+: 7c37001b cachee 0x17,0\(\$1\) +[ 0-9a-f]+: 2401f000 li \$1,-4096 +[ 0-9a-f]+: 7c39001b cachee 0x19,0\(\$1\) +[ 0-9a-f]+: 27610fff addiu \$1,\$27,4095 +[ 0-9a-f]+: 7c3a001b cachee 0x1a,0\(\$1\) +[ 0-9a-f]+: 24010fff li \$1,4095 +[ 0-9a-f]+: 7c3c001b cachee 0x1c,0\(\$1\) +[ 0-9a-f]+: 27c18000 addiu \$1,\$30,-32768 +[ 0-9a-f]+: 7c3d001b cachee 0x1d,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c3f001b cachee 0x1f,0\(\$1\) +[ 0-9a-f]+: 24417fff addiu \$1,\$2,32767 +[ 0-9a-f]+: 7c20001b cachee 0x0,0\(\$1\) +[ 0-9a-f]+: 24017fff li \$1,32767 +[ 0-9a-f]+: 7c23001b cachee 0x3,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 00250821 addu \$1,\$1,\$5 +[ 0-9a-f]+: 7c24ff9b cachee 0x4,-1\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c26ff9b cachee 0x6,-1\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 00280821 addu \$1,\$1,\$8 +[ 0-9a-f]+: 7c27001b cachee 0x7,0\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 7c29001b cachee 0x9,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 002b0821 addu \$1,\$1,\$11 +[ 0-9a-f]+: 7c2a001b cachee 0xa,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c2c001b cachee 0xc,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 002e0821 addu \$1,\$1,\$14 +[ 0-9a-f]+: 7c2dff9b cachee 0xd,-1\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c2fff9b cachee 0xf,-1\(\$1\) +[ 0-9a-f]+: 7e30001b cachee 0x10,0\(\$17\) +[ 0-9a-f]+: 3c010000 lui \$1,0x0 + [ 0-9a-f]+: R_MIPS_HI16 MYDATA +[ 0-9a-f]+: 24210000 addiu \$1,\$1,0 + [ 0-9a-f]+: R_MIPS_LO16 MYDATA +[ 0-9a-f]+: 7c32001b cachee 0x12,0\(\$1\) +[ 0-9a-f]+: 7e938023 prefe 0x13,-256\(\$20\) +[ 0-9a-f]+: 7c158023 prefe 0x15,-256\(\$0\) +[ 0-9a-f]+: 7ef67fa3 prefe 0x16,255\(\$23\) +[ 0-9a-f]+: 7c187fa3 prefe 0x18,255\(\$0\) +[ 0-9a-f]+: 2741feff addiu \$1,\$26,-257 +[ 0-9a-f]+: 7c390023 prefe 0x19,0\(\$1\) +[ 0-9a-f]+: 2401feff li \$1,-257 +[ 0-9a-f]+: 7c3b0023 prefe 0x1b,0\(\$1\) +[ 0-9a-f]+: 27a10100 addiu \$1,\$29,256 +[ 0-9a-f]+: 7c3c0023 prefe 0x1c,0\(\$1\) +[ 0-9a-f]+: 24010100 li \$1,256 +[ 0-9a-f]+: 7c3e0023 prefe 0x1e,0\(\$1\) +[ 0-9a-f]+: 2401fe00 li \$1,-512 +[ 0-9a-f]+: 7c3f0023 prefe 0x1f,0\(\$1\) +[ 0-9a-f]+: 2401fe00 li \$1,-512 +[ 0-9a-f]+: 7c220023 prefe 0x2,0\(\$1\) +[ 0-9a-f]+: 248101ff addiu \$1,\$4,511 +[ 0-9a-f]+: 7c230023 prefe 0x3,0\(\$1\) +[ 0-9a-f]+: 240101ff li \$1,511 +[ 0-9a-f]+: 7c250023 prefe 0x5,0\(\$1\) +[ 0-9a-f]+: 24e1fc00 addiu \$1,\$7,-1024 +[ 0-9a-f]+: 7c260023 prefe 0x6,0\(\$1\) +[ 0-9a-f]+: 2401fc00 li \$1,-1024 +[ 0-9a-f]+: 7c280023 prefe 0x8,0\(\$1\) +[ 0-9a-f]+: 254103ff addiu \$1,\$10,1023 +[ 0-9a-f]+: 7c290023 prefe 0x9,0\(\$1\) +[ 0-9a-f]+: 240103ff li \$1,1023 +[ 0-9a-f]+: 7c2b0023 prefe 0xb,0\(\$1\) +[ 0-9a-f]+: 25a1f800 addiu \$1,\$13,-2048 +[ 0-9a-f]+: 7c2c0023 prefe 0xc,0\(\$1\) +[ 0-9a-f]+: 2401f800 li \$1,-2048 +[ 0-9a-f]+: 7c2e0023 prefe 0xe,0\(\$1\) +[ 0-9a-f]+: 260107ff addiu \$1,\$16,2047 +[ 0-9a-f]+: 7c2f0023 prefe 0xf,0\(\$1\) +[ 0-9a-f]+: 240107ff li \$1,2047 +[ 0-9a-f]+: 7c310023 prefe 0x11,0\(\$1\) +[ 0-9a-f]+: 2661f000 addiu \$1,\$19,-4096 +[ 0-9a-f]+: 7c320023 prefe 0x12,0\(\$1\) +[ 0-9a-f]+: 2401f000 li \$1,-4096 +[ 0-9a-f]+: 7c340023 prefe 0x14,0\(\$1\) +[ 0-9a-f]+: 26c10fff addiu \$1,\$22,4095 +[ 0-9a-f]+: 7c350023 prefe 0x15,0\(\$1\) +[ 0-9a-f]+: 24010fff li \$1,4095 +[ 0-9a-f]+: 7c370023 prefe 0x17,0\(\$1\) +[ 0-9a-f]+: 27218000 addiu \$1,\$25,-32768 +[ 0-9a-f]+: 7c380023 prefe 0x18,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c3a0023 prefe 0x1a,0\(\$1\) +[ 0-9a-f]+: 27817fff addiu \$1,\$28,32767 +[ 0-9a-f]+: 7c3b0023 prefe 0x1b,0\(\$1\) +[ 0-9a-f]+: 24017fff li \$1,32767 +[ 0-9a-f]+: 7c3d0023 prefe 0x1d,0\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 003f0821 addu \$1,\$1,\$31 +[ 0-9a-f]+: 7c3effa3 prefe 0x1e,-1\(\$1\) +[ 0-9a-f]+: 24018000 li \$1,-32768 +[ 0-9a-f]+: 7c20ffa3 prefe 0x0,-1\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 00230821 addu \$1,\$1,\$3 +[ 0-9a-f]+: 7c220023 prefe 0x2,0\(\$1\) +[ 0-9a-f]+: 34018000 li \$1,0x8000 +[ 0-9a-f]+: 7c240023 prefe 0x4,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 00260821 addu \$1,\$1,\$6 +[ 0-9a-f]+: 7c250023 prefe 0x5,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c270023 prefe 0x7,0\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 00290821 addu \$1,\$1,\$9 +[ 0-9a-f]+: 7c28ffa3 prefe 0x8,-1\(\$1\) +[ 0-9a-f]+: 3c018000 lui \$1,0x8000 +[ 0-9a-f]+: 7c2affa3 prefe 0xa,-1\(\$1\) +[ 0-9a-f]+: 7d8b0023 prefe 0xb,0\(\$12\) +[ 0-9a-f]+: 3c010000 lui \$1,0x0 + [ 0-9a-f]+: R_MIPS_HI16 MYDATA +[ 0-9a-f]+: 24210000 addiu \$1,\$1,0 + [ 0-9a-f]+: R_MIPS_LO16 MYDATA +[ 0-9a-f]+: 7c2d0023 prefe 0xd,0\(\$1\) +[ 0-9a-f]+: 24c10000 addiu \$1,\$6,0 + [ 0-9a-f]+: R_MIPS_LO16 foo +[ 0-9a-f]+: 7c250023 prefe 0x5,0\(\$1\) +#pass diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@jal-svr4pic-noreorder.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@jal-svr4pic-noreorder.d new file mode 100644 index 0000000..88b7e31 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@jal-svr4pic-noreorder.d @@ -0,0 +1,46 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS jal-svr4pic noreorder +#as: -32 -KPIC +#source: jal-svr4pic-noreorder.s + +# Test the jal macro with -KPIC and `.set noreorder'. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 3c1c0000 lui gp,0x0 +[ ]*[0-9a-f]+: R_MIPS_HI16 _gp_disp +[0-9a-f]+ <[^>]*> 279c0000 addiu gp,gp,0 +[ ]*[0-9a-f]+: R_MIPS_LO16 _gp_disp +[0-9a-f]+ <[^>]*> 0399e021 addu gp,gp,t9 +[0-9a-f]+ <[^>]*> afbc0000 sw gp,0\(sp\) +[0-9a-f]+ <[^>]*> 0320f809 jalr t9 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 8fbc0000 lw gp,0\(sp\) +[0-9a-f]+ <[^>]*> 03202009 jalr a0,t9 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 8fbc0000 lw gp,0\(sp\) +[0-9a-f]+ <[^>]*> 8f990000 lw t9,0\(gp\) +[ ]*[0-9a-f]+: R_MIPS_GOT16 .text +[0-9a-f]+ <[^>]*> 27390000 addiu t9,t9,0 +[ ]*[0-9a-f]+: R_MIPS_LO16 .text +[0-9a-f]+ <[^>]*> 0320f809 jalr t9 +[ ]*[0-9a-f]+: R_MIPS_JALR text_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 8fbc0000 lw gp,0\(sp\) +[0-9a-f]+ <[^>]*> 8f990000 lw t9,0\(gp\) +[ ]*[0-9a-f]+: R_MIPS_CALL16 weak_text_label +[0-9a-f]+ <[^>]*> 0320f809 jalr t9 +[ ]*[0-9a-f]+: R_MIPS_JALR weak_text_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 8fbc0000 lw gp,0\(sp\) +[0-9a-f]+ <[^>]*> 8f990000 lw t9,0\(gp\) +[ ]*[0-9a-f]+: R_MIPS_CALL16 external_text_label +[0-9a-f]+ <[^>]*> 0320f809 jalr t9 +[ ]*[0-9a-f]+: R_MIPS_JALR external_text_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 8fbc0000 lw gp,0\(sp\) +[0-9a-f]+ <[^>]*> 1000ffff b 0+005c <text_label\+0x5c> +[ ]*5c: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> 00000000 nop + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@jal-svr4pic.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@jal-svr4pic.d new file mode 100644 index 0000000..e0a5c0e --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@jal-svr4pic.d @@ -0,0 +1,44 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS jal-svr4pic +#as: -32 -KPIC +#source: jal-svr4pic.s + +# Test the jal macro with -KPIC. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 3c1c0000 lui gp,0x0 +[ ]*[0-9a-f]+: R_MIPS_HI16 _gp_disp +[0-9a-f]+ <[^>]*> 279c0000 addiu gp,gp,0 +[ ]*[0-9a-f]+: R_MIPS_LO16 _gp_disp +[0-9a-f]+ <[^>]*> 0399e021 addu gp,gp,t9 +[0-9a-f]+ <[^>]*> afbc0000 sw gp,0\(sp\) +[0-9a-f]+ <[^>]*> 0320f809 jalr t9 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 03202009 jalr a0,t9 +[0-9a-f]+ <[^>]*> 8fbc0000 lw gp,0\(sp\) +[0-9a-f]+ <[^>]*> 8fbc0000 lw gp,0\(sp\) +[0-9a-f]+ <[^>]*> 8f990000 lw t9,0\(gp\) +[ ]*[0-9a-f]+: R_MIPS_GOT16 .text +[0-9a-f]+ <[^>]*> 27390000 addiu t9,t9,0 +[ ]*[0-9a-f]+: R_MIPS_LO16 .text +[0-9a-f]+ <[^>]*> 0320f809 jalr t9 +[ ]*[0-9a-f]+: R_MIPS_JALR text_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 8fbc0000 lw gp,0\(sp\) +[0-9a-f]+ <[^>]*> 8f990000 lw t9,0\(gp\) +[ ]*[0-9a-f]+: R_MIPS_CALL16 weak_text_label +[0-9a-f]+ <[^>]*> 0320f809 jalr t9 +[ ]*[0-9a-f]+: R_MIPS_JALR weak_text_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 8fbc0000 lw gp,0\(sp\) +[0-9a-f]+ <[^>]*> 8f990000 lw t9,0\(gp\) +[ ]*[0-9a-f]+: R_MIPS_CALL16 external_text_label +[0-9a-f]+ <[^>]*> 0320f809 jalr t9 +[ ]*[0-9a-f]+: R_MIPS_JALR external_text_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 1000ffff b 0+0054 <text_label\+0x54> +[ ]*54: .*R_MIPS_PC16 text_label +[0-9a-f]+ <[^>]*> 8fbc0000 lw gp,0\(sp\) + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@ld-zero-3.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@ld-zero-3.d new file mode 100644 index 0000000..7203141 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@ld-zero-3.d @@ -0,0 +1,15 @@ +#objdump: -dr --prefix-addresses +#as: -mabi=o64 +#name: MIPS III load $zero +#source: ld-zero-3.s + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> lui at,0x1234 +[0-9a-f]+ <[^>]*> addu at,at,v0 +[0-9a-f]+ <[^>]*> lwu zero,22136\(at\) +[0-9a-f]+ <[^>]*> lui at,0x1234 +[0-9a-f]+ <[^>]*> addu at,at,v0 +[0-9a-f]+ <[^>]*> ld zero,22136\(at\) + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@loc-swap-dis.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@loc-swap-dis.d new file mode 100644 index 0000000..d377f6a --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@loc-swap-dis.d @@ -0,0 +1,34 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS DWARF-2 location information with branch swapping disassembly +#as: -32 +#source: loc-swap.s + +# Check branch swapping with DWARF-2 location information. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 02002021 move a0,s0 +[0-9a-f]+ <[^>]*> 00800009 jr a0 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 00800009 jr a0 +[0-9a-f]+ <[^>]*> 0200f821 move ra,s0 +[0-9a-f]+ <[^>]*> 03e00009 jr ra +[0-9a-f]+ <[^>]*> 02002021 move a0,s0 +[0-9a-f]+ <[^>]*> 0200f821 move ra,s0 +[0-9a-f]+ <[^>]*> 03e00009 jr ra +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 02002021 move a0,s0 +[0-9a-f]+ <[^>]*> 0080f809 jalr a0 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0200f821 move ra,s0 +[0-9a-f]+ <[^>]*> 0080f809 jalr a0 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 0c000000 jal 0+0000 <foo> +[ ]*[0-9a-f]+: R_MIPS_26 bar +[0-9a-f]+ <[^>]*> 02002021 move a0,s0 +[0-9a-f]+ <[^>]*> 0200f821 move ra,s0 +[0-9a-f]+ <[^>]*> 0c000000 jal 0+0000 <foo> +[ ]*[0-9a-f]+: R_MIPS_26 bar +[0-9a-f]+ <[^>]*> 00000000 nop + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips32-cp2.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips32-cp2.d new file mode 100644 index 0000000..2b7c098 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips32-cp2.d @@ -0,0 +1,20 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS MIPS32 cop2 instructions +#source: mips32-cp2.s +#as: -32 + +# Check MIPS32 cop2 instruction assembly + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 48411000 cfc2 at,\$2 +0+0004 <[^>]*> 4b234567 c2 0x1234567 +0+0008 <[^>]*> 48c21800 ctc2 v0,\$3 +0+000c <[^>]*> 48032000 mfc2 v1,\$4 +0+0010 <[^>]*> 48042800 mfc2 a0,\$5 +0+0014 <[^>]*> 48053007 mfc2 a1,\$6,7 +0+0018 <[^>]*> 48863800 mtc2 a2,\$7 +0+001c <[^>]*> 48874000 mtc2 a3,\$8 +0+0020 <[^>]*> 48884807 mtc2 t0,\$9,7 +#pass diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips32-imm.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips32-imm.d new file mode 100644 index 0000000..5a98f8d --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips32-imm.d @@ -0,0 +1,13 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS MIPS32 WAIT and SDBBP instructions +#as: -32 +#source: mips32-imm.s + +# Check MIPS32 WAIT and SDBBP instruction assembly + +.*: +file format .*mips.* + +Disassembly of section .text: +[0-9a-f]+ <[^>]*> 4359e260 wait 0x56789 +[0-9a-f]+ <[^>]*> 0159e24e sdbbp 0x56789 + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips32.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips32.d new file mode 100644 index 0000000..e7af216 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips32.d @@ -0,0 +1,32 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS MIPS32 instructions +#as: -32 +#source: mips32.s + +# Check MIPS32 instruction assembly + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 00400851 clo at,v0 +0+0004 <[^>]*> 00801850 clz v1,a0 +0+0008 <[^>]*> 01cf6898 mul t5,t6,t7 +0+000c <[^>]*> 7e040035 pref 0x4,0\(s0\) +0+0010 <[^>]*> 00000040 ssnop +0+0014 <[^>]*> 7c250025 cache 0x5,0\(at\) +0+0018 <[^>]*> 42000018 eret +0+001c <[^>]*> 42000008 tlbp +0+0020 <[^>]*> 42000001 tlbr +0+0024 <[^>]*> 42000002 tlbwi +0+0028 <[^>]*> 42000006 tlbwr +0+002c <[^>]*> 42000020 wait +0+0030 <[^>]*> 42000020 wait +0+0034 <[^>]*> 4200d160 wait 0x345 +0+0038 <[^>]*> 0000000d break +0+003c <[^>]*> 0000000d break +0+0040 <[^>]*> 0345000d break 0x345 +0+0044 <[^>]*> 0048d14d break 0x48,0x345 +0+0048 <[^>]*> 0000000e sdbbp +0+004c <[^>]*> 0000000e sdbbp +0+0050 <[^>]*> 0000d14e sdbbp 0x345 + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips32r2.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips32r2.d new file mode 100644 index 0000000..dbf680c --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips32r2.d @@ -0,0 +1,45 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric +#name: MIPS MIPS32r2 non-fp instructions +#as: -32 +#source: mips32r2.s + +# Check MIPS32 Release 2 (mips32r2) *non-fp* instruction assembly + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 000000c0 ehb +0+0004 <[^>]*> 7ca43980 ext \$4,\$5,0x6,0x8 +0+0008 <[^>]*> 7ca46984 ins \$4,\$5,0x6,0x8 +0+000c <[^>]*> 0100fc09 jalr.hb \$8 +0+0010 <[^>]*> 0120a409 jalr.hb \$20,\$9 +0+0014 <[^>]*> 01000409 jr.hb \$8 +0+0018 <[^>]*> 7c0a003b rdhwr \$10,\$0 +0+001c <[^>]*> 7c0b083b rdhwr \$11,\$1 +0+0020 <[^>]*> 7c0c103b rdhwr \$12,\$2 +0+0024 <[^>]*> 7c0d183b rdhwr \$13,\$3 +0+0028 <[^>]*> 7c0e203b rdhwr \$14,\$4 +0+002c <[^>]*> 7c0f283b rdhwr \$15,\$5 +0+0030 <[^>]*> 002acf02 ror \$25,\$10,0x1c +0+0034 <[^>]*> 002ac902 ror \$25,\$10,0x4 +0+0038 <[^>]*> 0004c823 negu \$25,\$4 +0+003c <[^>]*> 032ac846 rorv \$25,\$10,\$25 +0+0040 <[^>]*> 008ac846 rorv \$25,\$10,\$4 +0+0044 <[^>]*> 008ac846 rorv \$25,\$10,\$4 +0+0048 <[^>]*> 7c073c20 seb \$7,\$7 +0+004c <[^>]*> 7c0a4420 seb \$8,\$10 +0+0050 <[^>]*> 7c073e20 seh \$7,\$7 +0+0054 <[^>]*> 7c0a4620 seh \$8,\$10 +0+0058 <[^>]*> 055f5555 synci 21845\(\$10\) +0+005c <[^>]*> 7c0738a0 wsbh \$7,\$7 +0+0060 <[^>]*> 7c0a40a0 wsbh \$8,\$10 +0+0064 <[^>]*> 41606000 di +0+0068 <[^>]*> 41606000 di +0+006c <[^>]*> 416a6000 di \$10 +0+0070 <[^>]*> 41606020 ei +0+0074 <[^>]*> 41606020 ei +0+0078 <[^>]*> 416a6020 ei \$10 +0+007c <[^>]*> 41595000 rdpgpr \$10,\$25 +0+0080 <[^>]*> 41d95000 wrpgpr \$10,\$25 +0+0084 <[^>]*> 00000140 pause + ... diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips4-fp.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips4-fp.d new file mode 100644 index 0000000..a81a423 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips4-fp.d @@ -0,0 +1,13 @@ +#objdump: -dr --prefix-addresses +#name: MIPS mips4 fp + +# Test mips4 fp instructions. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> recip.d \$f4,\$f6 +[0-9a-f]+ <[^>]*> recip.s \$f4,\$f6 +[0-9a-f]+ <[^>]*> rsqrt.d \$f4,\$f6 +[0-9a-f]+ <[^>]*> rsqrt.s \$f4,\$f6 + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips4-fp.l b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips4-fp.l new file mode 100644 index 0000000..85aef3d --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips4-fp.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*:4: Error: opcode not supported on this processor: .* \(.*\) `recip.d \$f4,\$f6' +.*:5: Error: opcode not supported on this processor: .* \(.*\) `recip.s \$f4,\$f6' +.*:6: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.d \$f4,\$f6' +.*:7: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.s \$f4,\$f6' diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips4-fp.s b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips4-fp.s new file mode 100644 index 0000000..4d124e5 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips4-fp.s @@ -0,0 +1,11 @@ +# Source file used to test -mips4 fp instructions. + +text_label: + recip.d $f4,$f6 + recip.s $f4,$f6 + rsqrt.d $f4,$f6 + rsqrt.s $f4,$f6 + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 2 + .space 8 diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips4.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips4.d new file mode 100644 index 0000000..08b6d96 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips4.d @@ -0,0 +1,11 @@ +#objdump: -dr --prefix-addresses +#name: MIPS mips4 non-fp +#source: mips4.s + +# Test mips4 *non-fp* insturctions. + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> pref 0x4,0\(a0\) + ... diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips5-fp.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips5-fp.d new file mode 100644 index 0000000..77244fb --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips5-fp.d @@ -0,0 +1,12 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric +#name: MIPS mips5 instructions +#stderr: mipsr6@mips5-fp.l + +# Check MIPS V instruction assembly + +.*: +file format .*mips.* + +Disassembly of section \.text: +0+0000 <[^>]*> 46c09428 cvt\.s\.pl \$f16,\$f18 +0+0004 <[^>]*> 46c0a4a0 cvt\.s\.pu \$f18,\$f20 + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips5-fp.l b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips5-fp.l new file mode 100644 index 0000000..927ff97 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips5-fp.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*:4: Warning: condition code register should be even for c.eq.ps, was 3 +.*:5: Warning: condition code register should be even for movf.ps, was 3 diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips5-fp.s b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips5-fp.s new file mode 100644 index 0000000..6bee111 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips5-fp.s @@ -0,0 +1,8 @@ +# Source file used to test -mips5 instructions. + +text_label: + cvt.s.pl $f16, $f18 + cvt.s.pu $f18, $f20 + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .space 8 diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips64.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips64.d new file mode 100644 index 0000000..c9e732c --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@mips64.d @@ -0,0 +1,13 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS MIPS64 instructions +#as: -32 +#source: mips64.s + +# Check MIPS64 instruction assembly + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 00400853 dclo at,v0 +0+0004 <[^>]*> 00801852 dclz v1,a0 +#pass diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@msa-branch.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@msa-branch.d new file mode 100644 index 0000000..3466145 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@msa-branch.d @@ -0,0 +1,309 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa +#name: MSA branch reorder +#as: -32 -mmsa +#source: msa-branch.s + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4700.... bz\.b \$w0,[0-9a-f]+ <[^>]*> +[ ]*4: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4701.... bz\.b \$w1,[0-9a-f]+ <[^>]*> +[ ]*c: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4702.... bz\.b \$w2,[0-9a-f]+ <[^>]*> +[ ]*14: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4700.... bz\.b \$w0,[0-9a-f]+ <[^>]*> +[ ]*20: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4701.... bz\.b \$w1,[0-9a-f]+ <[^>]*> +[ ]*28: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4702.... bz\.b \$w2,[0-9a-f]+ <[^>]*> +[ ]*30: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4700.... bz\.b \$w0,[0-9a-f]+ <[^>]*> +[ ]*3c: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4701.... bz\.b \$w1,[0-9a-f]+ <[^>]*> +[ ]*44: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4702.... bz\.b \$w2,[0-9a-f]+ <[^>]*> +[ ]*4c: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4720.... bz\.h \$w0,[0-9a-f]+ <[^>]*> +[ ]*58: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4721.... bz\.h \$w1,[0-9a-f]+ <[^>]*> +[ ]*60: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4722.... bz\.h \$w2,[0-9a-f]+ <[^>]*> +[ ]*68: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4720.... bz\.h \$w0,[0-9a-f]+ <[^>]*> +[ ]*74: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4721.... bz\.h \$w1,[0-9a-f]+ <[^>]*> +[ ]*7c: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4722.... bz\.h \$w2,[0-9a-f]+ <[^>]*> +[ ]*84: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4720.... bz\.h \$w0,[0-9a-f]+ <[^>]*> +[ ]*90: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4721.... bz\.h \$w1,[0-9a-f]+ <[^>]*> +[ ]*98: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4722.... bz\.h \$w2,[0-9a-f]+ <[^>]*> +[ ]*a0: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4740.... bz\.w \$w0,[0-9a-f]+ <[^>]*> +[ ]*ac: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4741.... bz\.w \$w1,[0-9a-f]+ <[^>]*> +[ ]*b4: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4742.... bz\.w \$w2,[0-9a-f]+ <[^>]*> +[ ]*bc: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4740.... bz\.w \$w0,[0-9a-f]+ <[^>]*> +[ ]*c8: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4741.... bz\.w \$w1,[0-9a-f]+ <[^>]*> +[ ]*d0: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4742.... bz\.w \$w2,[0-9a-f]+ <[^>]*> +[ ]*d8: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4740.... bz\.w \$w0,[0-9a-f]+ <[^>]*> +[ ]*e4: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4741.... bz\.w \$w1,[0-9a-f]+ <[^>]*> +[ ]*ec: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4742.... bz\.w \$w2,[0-9a-f]+ <[^>]*> +[ ]*f4: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4760.... bz\.d \$w0,[0-9a-f]+ <[^>]*> +[ ]*100: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4761.... bz\.d \$w1,[0-9a-f]+ <[^>]*> +[ ]*108: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4762.... bz\.d \$w2,[0-9a-f]+ <[^>]*> +[ ]*110: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4760.... bz\.d \$w0,[0-9a-f]+ <[^>]*> +[ ]*11c: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4761.... bz\.d \$w1,[0-9a-f]+ <[^>]*> +[ ]*124: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4762.... bz\.d \$w2,[0-9a-f]+ <[^>]*> +[ ]*12c: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4760.... bz\.d \$w0,[0-9a-f]+ <[^>]*> +[ ]*138: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4761.... bz\.d \$w1,[0-9a-f]+ <[^>]*> +[ ]*140: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4762.... bz\.d \$w2,[0-9a-f]+ <[^>]*> +[ ]*148: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4560.... bz\.v \$w0,[0-9a-f]+ <[^>]*> +[ ]*154: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4561.... bz\.v \$w1,[0-9a-f]+ <[^>]*> +[ ]*15c: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4562.... bz\.v \$w2,[0-9a-f]+ <[^>]*> +[ ]*164: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4560.... bz\.v \$w0,[0-9a-f]+ <[^>]*> +[ ]*170: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4561.... bz\.v \$w1,[0-9a-f]+ <[^>]*> +[ ]*178: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4562.... bz\.v \$w2,[0-9a-f]+ <[^>]*> +[ ]*180: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4560.... bz\.v \$w0,[0-9a-f]+ <[^>]*> +[ ]*18c: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4561.... bz\.v \$w1,[0-9a-f]+ <[^>]*> +[ ]*194: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4562.... bz\.v \$w2,[0-9a-f]+ <[^>]*> +[ ]*19c: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4780.... bnz\.b \$w0,[0-9a-f]+ <[^>]*> +[ ]*1a8: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4781.... bnz\.b \$w1,[0-9a-f]+ <[^>]*> +[ ]*1b0: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4782.... bnz\.b \$w2,[0-9a-f]+ <[^>]*> +[ ]*1b8: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4780.... bnz\.b \$w0,[0-9a-f]+ <[^>]*> +[ ]*1c4: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4781.... bnz\.b \$w1,[0-9a-f]+ <[^>]*> +[ ]*1cc: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4782.... bnz\.b \$w2,[0-9a-f]+ <[^>]*> +[ ]*1d4: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4780.... bnz\.b \$w0,[0-9a-f]+ <[^>]*> +[ ]*1e0: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4781.... bnz\.b \$w1,[0-9a-f]+ <[^>]*> +[ ]*1e8: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4782.... bnz\.b \$w2,[0-9a-f]+ <[^>]*> +[ ]*1f0: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 47a0.... bnz\.h \$w0,[0-9a-f]+ <[^>]*> +[ ]*1fc: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47a1.... bnz\.h \$w1,[0-9a-f]+ <[^>]*> +[ ]*204: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 47a2.... bnz\.h \$w2,[0-9a-f]+ <[^>]*> +[ ]*20c: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 47a0.... bnz\.h \$w0,[0-9a-f]+ <[^>]*> +[ ]*218: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47a1.... bnz\.h \$w1,[0-9a-f]+ <[^>]*> +[ ]*220: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 47a2.... bnz\.h \$w2,[0-9a-f]+ <[^>]*> +[ ]*228: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 47a0.... bnz\.h \$w0,[0-9a-f]+ <[^>]*> +[ ]*234: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47a1.... bnz\.h \$w1,[0-9a-f]+ <[^>]*> +[ ]*23c: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 47a2.... bnz\.h \$w2,[0-9a-f]+ <[^>]*> +[ ]*244: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 47c0.... bnz\.w \$w0,[0-9a-f]+ <[^>]*> +[ ]*250: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47c1.... bnz\.w \$w1,[0-9a-f]+ <[^>]*> +[ ]*258: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 47c2.... bnz\.w \$w2,[0-9a-f]+ <[^>]*> +[ ]*260: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 47c0.... bnz\.w \$w0,[0-9a-f]+ <[^>]*> +[ ]*26c: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47c1.... bnz\.w \$w1,[0-9a-f]+ <[^>]*> +[ ]*274: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 47c2.... bnz\.w \$w2,[0-9a-f]+ <[^>]*> +[ ]*27c: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 47c0.... bnz\.w \$w0,[0-9a-f]+ <[^>]*> +[ ]*288: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47c1.... bnz\.w \$w1,[0-9a-f]+ <[^>]*> +[ ]*290: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 47c2.... bnz\.w \$w2,[0-9a-f]+ <[^>]*> +[ ]*298: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 47e0.... bnz\.d \$w0,[0-9a-f]+ <[^>]*> +[ ]*2a4: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47e1.... bnz\.d \$w1,[0-9a-f]+ <[^>]*> +[ ]*2ac: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 47e2.... bnz\.d \$w2,[0-9a-f]+ <[^>]*> +[ ]*2b4: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 47e0.... bnz\.d \$w0,[0-9a-f]+ <[^>]*> +[ ]*2c0: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47e1.... bnz\.d \$w1,[0-9a-f]+ <[^>]*> +[ ]*2c8: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 47e2.... bnz\.d \$w2,[0-9a-f]+ <[^>]*> +[ ]*2d0: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 47e0.... bnz\.d \$w0,[0-9a-f]+ <[^>]*> +[ ]*2dc: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47e1.... bnz\.d \$w1,[0-9a-f]+ <[^>]*> +[ ]*2e4: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 47e2.... bnz\.d \$w2,[0-9a-f]+ <[^>]*> +[ ]*2ec: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 45e0.... bnz\.v \$w0,[0-9a-f]+ <[^>]*> +[ ]*2f8: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45e1.... bnz\.v \$w1,[0-9a-f]+ <[^>]*> +[ ]*300: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 45e2.... bnz\.v \$w2,[0-9a-f]+ <[^>]*> +[ ]*308: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 45e0.... bnz\.v \$w0,[0-9a-f]+ <[^>]*> +[ ]*314: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45e1.... bnz\.v \$w1,[0-9a-f]+ <[^>]*> +[ ]*31c: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 45e2.... bnz\.v \$w2,[0-9a-f]+ <[^>]*> +[ ]*324: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 45e0.... bnz\.v \$w0,[0-9a-f]+ <[^>]*> +[ ]*330: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45e1.... bnz\.v \$w1,[0-9a-f]+ <[^>]*> +[ ]*338: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 45e2.... bnz\.v \$w2,[0-9a-f]+ <[^>]*> +[ ]*340: .*R_MIPS_PC16 test +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@msa.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@msa.d new file mode 100644 index 0000000..4471c95 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@msa.d @@ -0,0 +1,788 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa +#name: MSA instructions +#as: -32 -mmsa --defsym insn_log2=2 +#source: msa.s + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 7802080d sll\.b \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 782520cd sll\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7848398d sll\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 786b524d sll\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 78706b09 slli\.b \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 78777b89 slli\.b \$w14,\$w15,0x7 +[0-9a-f]+ <[^>]*> 78608c09 slli\.h \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 786f9c89 slli\.h \$w18,\$w19,0xf +[0-9a-f]+ <[^>]*> 7840ad09 slli\.w \$w20,\$w21,0x0 +[0-9a-f]+ <[^>]*> 785fbd89 slli\.w \$w22,\$w23,0x1f +[0-9a-f]+ <[^>]*> 7800ce09 slli\.d \$w24,\$w25,0x0 +[0-9a-f]+ <[^>]*> 783fde89 slli\.d \$w26,\$w27,0x3f +[0-9a-f]+ <[^>]*> 789eef0d sra\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 78a107cd sra\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 78c4188d sra\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 78e7314d sra\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 78f04a09 srai\.b \$w8,\$w9,0x0 +[0-9a-f]+ <[^>]*> 78f75a89 srai\.b \$w10,\$w11,0x7 +[0-9a-f]+ <[^>]*> 78e06b09 srai\.h \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 78ef7b89 srai\.h \$w14,\$w15,0xf +[0-9a-f]+ <[^>]*> 78c08c09 srai\.w \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 78df9c89 srai\.w \$w18,\$w19,0x1f +[0-9a-f]+ <[^>]*> 7880ad09 srai\.d \$w20,\$w21,0x0 +[0-9a-f]+ <[^>]*> 78bfbd89 srai\.d \$w22,\$w23,0x3f +[0-9a-f]+ <[^>]*> 791ace0d srl\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 793de6cd srl\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 7940ff8d srl\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 7963104d srl\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 79702909 srli\.b \$w4,\$w5,0x0 +[0-9a-f]+ <[^>]*> 79773989 srli\.b \$w6,\$w7,0x7 +[0-9a-f]+ <[^>]*> 79604a09 srli\.h \$w8,\$w9,0x0 +[0-9a-f]+ <[^>]*> 796f5a89 srli\.h \$w10,\$w11,0xf +[0-9a-f]+ <[^>]*> 79406b09 srli\.w \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 795f7b89 srli\.w \$w14,\$w15,0x1f +[0-9a-f]+ <[^>]*> 79008c09 srli\.d \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 793f9c89 srli\.d \$w18,\$w19,0x3f +[0-9a-f]+ <[^>]*> 7996ad0d bclr\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 79b9c5cd bclr\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 79dcde8d bclr\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 79fff74d bclr\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 79f00809 bclri\.b \$w0,\$w1,0x0 +[0-9a-f]+ <[^>]*> 79f71889 bclri\.b \$w2,\$w3,0x7 +[0-9a-f]+ <[^>]*> 79e02909 bclri\.h \$w4,\$w5,0x0 +[0-9a-f]+ <[^>]*> 79ef3989 bclri\.h \$w6,\$w7,0xf +[0-9a-f]+ <[^>]*> 79c04a09 bclri\.w \$w8,\$w9,0x0 +[0-9a-f]+ <[^>]*> 79df5a89 bclri\.w \$w10,\$w11,0x1f +[0-9a-f]+ <[^>]*> 79806b09 bclri\.d \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 79bf7b89 bclri\.d \$w14,\$w15,0x3f +[0-9a-f]+ <[^>]*> 7a128c0d bset\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 7a35a4cd bset\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 7a58bd8d bset\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 7a7bd64d bset\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 7a70ef09 bseti\.b \$w28,\$w29,0x0 +[0-9a-f]+ <[^>]*> 7a77ff89 bseti\.b \$w30,\$w31,0x7 +[0-9a-f]+ <[^>]*> 7a600809 bseti\.h \$w0,\$w1,0x0 +[0-9a-f]+ <[^>]*> 7a6f1889 bseti\.h \$w2,\$w3,0xf +[0-9a-f]+ <[^>]*> 7a402909 bseti\.w \$w4,\$w5,0x0 +[0-9a-f]+ <[^>]*> 7a5f3989 bseti\.w \$w6,\$w7,0x1f +[0-9a-f]+ <[^>]*> 7a004a09 bseti\.d \$w8,\$w9,0x0 +[0-9a-f]+ <[^>]*> 7a3f5a89 bseti\.d \$w10,\$w11,0x3f +[0-9a-f]+ <[^>]*> 7a8e6b0d bneg\.b \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 7ab183cd bneg\.h \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 7ad49c8d bneg\.w \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7af7b54d bneg\.d \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 7af0ce09 bnegi\.b \$w24,\$w25,0x0 +[0-9a-f]+ <[^>]*> 7af7de89 bnegi\.b \$w26,\$w27,0x7 +[0-9a-f]+ <[^>]*> 7ae0ef09 bnegi\.h \$w28,\$w29,0x0 +[0-9a-f]+ <[^>]*> 7aefff89 bnegi\.h \$w30,\$w31,0xf +[0-9a-f]+ <[^>]*> 7ac00809 bnegi\.w \$w0,\$w1,0x0 +[0-9a-f]+ <[^>]*> 7adf1889 bnegi\.w \$w2,\$w3,0x1f +[0-9a-f]+ <[^>]*> 7a802909 bnegi\.d \$w4,\$w5,0x0 +[0-9a-f]+ <[^>]*> 7abf3989 bnegi\.d \$w6,\$w7,0x3f +[0-9a-f]+ <[^>]*> 7b0a4a0d binsl\.b \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 7b2d62cd binsl\.h \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 7b507b8d binsl\.w \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7b73944d binsl\.d \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7b70ad09 binsli\.b \$w20,\$w21,0x0 +[0-9a-f]+ <[^>]*> 7b77bd89 binsli\.b \$w22,\$w23,0x7 +[0-9a-f]+ <[^>]*> 7b60ce09 binsli\.h \$w24,\$w25,0x0 +[0-9a-f]+ <[^>]*> 7b6fde89 binsli\.h \$w26,\$w27,0xf +[0-9a-f]+ <[^>]*> 7b40ef09 binsli\.w \$w28,\$w29,0x0 +[0-9a-f]+ <[^>]*> 7b5fff89 binsli\.w \$w30,\$w31,0x1f +[0-9a-f]+ <[^>]*> 7b000809 binsli\.d \$w0,\$w1,0x0 +[0-9a-f]+ <[^>]*> 7b3f1889 binsli\.d \$w2,\$w3,0x3f +[0-9a-f]+ <[^>]*> 7b86290d binsr\.b \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 7ba941cd binsr\.h \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 7bcc5a8d binsr\.w \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 7bef734d binsr\.d \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 7bf08c09 binsri\.b \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 7bf79c89 binsri\.b \$w18,\$w19,0x7 +[0-9a-f]+ <[^>]*> 7be0ad09 binsri\.h \$w20,\$w21,0x0 +[0-9a-f]+ <[^>]*> 7befbd89 binsri\.h \$w22,\$w23,0xf +[0-9a-f]+ <[^>]*> 7bc0ce09 binsri\.w \$w24,\$w25,0x0 +[0-9a-f]+ <[^>]*> 7bdfde89 binsri\.w \$w26,\$w27,0x1f +[0-9a-f]+ <[^>]*> 7b80ef09 binsri\.d \$w28,\$w29,0x0 +[0-9a-f]+ <[^>]*> 7bbfff89 binsri\.d \$w30,\$w31,0x3f +[0-9a-f]+ <[^>]*> 7802080e addv\.b \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 782520ce addv\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7848398e addv\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 786b524e addv\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 78006b06 addvi\.b \$w12,\$w13,0 +[0-9a-f]+ <[^>]*> 781f7b86 addvi\.b \$w14,\$w15,31 +[0-9a-f]+ <[^>]*> 78208c06 addvi\.h \$w16,\$w17,0 +[0-9a-f]+ <[^>]*> 783f9c86 addvi\.h \$w18,\$w19,31 +[0-9a-f]+ <[^>]*> 7840ad06 addvi\.w \$w20,\$w21,0 +[0-9a-f]+ <[^>]*> 785fbd86 addvi\.w \$w22,\$w23,31 +[0-9a-f]+ <[^>]*> 7860ce06 addvi\.d \$w24,\$w25,0 +[0-9a-f]+ <[^>]*> 787fde86 addvi\.d \$w26,\$w27,31 +[0-9a-f]+ <[^>]*> 789eef0e subv\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 78a107ce subv\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 78c4188e subv\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 78e7314e subv\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 78804a06 subvi\.b \$w8,\$w9,0 +[0-9a-f]+ <[^>]*> 789f5a86 subvi\.b \$w10,\$w11,31 +[0-9a-f]+ <[^>]*> 78a06b06 subvi\.h \$w12,\$w13,0 +[0-9a-f]+ <[^>]*> 78bf7b86 subvi\.h \$w14,\$w15,31 +[0-9a-f]+ <[^>]*> 78c08c06 subvi\.w \$w16,\$w17,0 +[0-9a-f]+ <[^>]*> 78df9c86 subvi\.w \$w18,\$w19,31 +[0-9a-f]+ <[^>]*> 78e0ad06 subvi\.d \$w20,\$w21,0 +[0-9a-f]+ <[^>]*> 78ffbd86 subvi\.d \$w22,\$w23,31 +[0-9a-f]+ <[^>]*> 791ace0e max_s\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 793de6ce max_s\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 7940ff8e max_s\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 7963104e max_s\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 79102906 maxi_s\.b \$w4,\$w5,-16 +[0-9a-f]+ <[^>]*> 790f3986 maxi_s\.b \$w6,\$w7,15 +[0-9a-f]+ <[^>]*> 79304a06 maxi_s\.h \$w8,\$w9,-16 +[0-9a-f]+ <[^>]*> 792f5a86 maxi_s\.h \$w10,\$w11,15 +[0-9a-f]+ <[^>]*> 79506b06 maxi_s\.w \$w12,\$w13,-16 +[0-9a-f]+ <[^>]*> 794f7b86 maxi_s\.w \$w14,\$w15,15 +[0-9a-f]+ <[^>]*> 79708c06 maxi_s\.d \$w16,\$w17,-16 +[0-9a-f]+ <[^>]*> 796f9c86 maxi_s\.d \$w18,\$w19,15 +[0-9a-f]+ <[^>]*> 7996ad0e max_u\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 79b9c5ce max_u\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 79dcde8e max_u\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 79fff74e max_u\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 79800806 maxi_u\.b \$w0,\$w1,0 +[0-9a-f]+ <[^>]*> 799f1886 maxi_u\.b \$w2,\$w3,31 +[0-9a-f]+ <[^>]*> 79a02906 maxi_u\.h \$w4,\$w5,0 +[0-9a-f]+ <[^>]*> 79bf3986 maxi_u\.h \$w6,\$w7,31 +[0-9a-f]+ <[^>]*> 79c04a06 maxi_u\.w \$w8,\$w9,0 +[0-9a-f]+ <[^>]*> 79df5a86 maxi_u\.w \$w10,\$w11,31 +[0-9a-f]+ <[^>]*> 79e06b06 maxi_u\.d \$w12,\$w13,0 +[0-9a-f]+ <[^>]*> 79ff7b86 maxi_u\.d \$w14,\$w15,31 +[0-9a-f]+ <[^>]*> 7a128c0e min_s\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 7a35a4ce min_s\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 7a58bd8e min_s\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 7a7bd64e min_s\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 7a10ef06 mini_s\.b \$w28,\$w29,-16 +[0-9a-f]+ <[^>]*> 7a0fff86 mini_s\.b \$w30,\$w31,15 +[0-9a-f]+ <[^>]*> 7a300806 mini_s\.h \$w0,\$w1,-16 +[0-9a-f]+ <[^>]*> 7a2f1886 mini_s\.h \$w2,\$w3,15 +[0-9a-f]+ <[^>]*> 7a502906 mini_s\.w \$w4,\$w5,-16 +[0-9a-f]+ <[^>]*> 7a4f3986 mini_s\.w \$w6,\$w7,15 +[0-9a-f]+ <[^>]*> 7a704a06 mini_s\.d \$w8,\$w9,-16 +[0-9a-f]+ <[^>]*> 7a6f5a86 mini_s\.d \$w10,\$w11,15 +[0-9a-f]+ <[^>]*> 7a8e6b0e min_u\.b \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 7ab183ce min_u\.h \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 7ad49c8e min_u\.w \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7af7b54e min_u\.d \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 7a80ce06 mini_u\.b \$w24,\$w25,0 +[0-9a-f]+ <[^>]*> 7a9fde86 mini_u\.b \$w26,\$w27,31 +[0-9a-f]+ <[^>]*> 7aa0ef06 mini_u\.h \$w28,\$w29,0 +[0-9a-f]+ <[^>]*> 7abfff86 mini_u\.h \$w30,\$w31,31 +[0-9a-f]+ <[^>]*> 7ac00806 mini_u\.w \$w0,\$w1,0 +[0-9a-f]+ <[^>]*> 7adf1886 mini_u\.w \$w2,\$w3,31 +[0-9a-f]+ <[^>]*> 7ae02906 mini_u\.d \$w4,\$w5,0 +[0-9a-f]+ <[^>]*> 7aff3986 mini_u\.d \$w6,\$w7,31 +[0-9a-f]+ <[^>]*> 7b0a4a0e max_a\.b \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 7b2d62ce max_a\.h \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 7b507b8e max_a\.w \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7b73944e max_a\.d \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7b96ad0e min_a\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7bb9c5ce min_a\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 7bdcde8e min_a\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 7bfff74e min_a\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 7802080f ceq\.b \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 782520cf ceq\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7848398f ceq\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 786b524f ceq\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 78106b07 ceqi\.b \$w12,\$w13,-16 +[0-9a-f]+ <[^>]*> 780f7b87 ceqi\.b \$w14,\$w15,15 +[0-9a-f]+ <[^>]*> 78308c07 ceqi\.h \$w16,\$w17,-16 +[0-9a-f]+ <[^>]*> 782f9c87 ceqi\.h \$w18,\$w19,15 +[0-9a-f]+ <[^>]*> 7850ad07 ceqi\.w \$w20,\$w21,-16 +[0-9a-f]+ <[^>]*> 784fbd87 ceqi\.w \$w22,\$w23,15 +[0-9a-f]+ <[^>]*> 7870ce07 ceqi\.d \$w24,\$w25,-16 +[0-9a-f]+ <[^>]*> 786fde87 ceqi\.d \$w26,\$w27,15 +[0-9a-f]+ <[^>]*> 791eef0f clt_s\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 792107cf clt_s\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 7944188f clt_s\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 7967314f clt_s\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 79104a07 clti_s\.b \$w8,\$w9,-16 +[0-9a-f]+ <[^>]*> 790f5a87 clti_s\.b \$w10,\$w11,15 +[0-9a-f]+ <[^>]*> 79306b07 clti_s\.h \$w12,\$w13,-16 +[0-9a-f]+ <[^>]*> 792f7b87 clti_s\.h \$w14,\$w15,15 +[0-9a-f]+ <[^>]*> 79508c07 clti_s\.w \$w16,\$w17,-16 +[0-9a-f]+ <[^>]*> 794f9c87 clti_s\.w \$w18,\$w19,15 +[0-9a-f]+ <[^>]*> 7970ad07 clti_s\.d \$w20,\$w21,-16 +[0-9a-f]+ <[^>]*> 796fbd87 clti_s\.d \$w22,\$w23,15 +[0-9a-f]+ <[^>]*> 799ace0f clt_u\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 79bde6cf clt_u\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 79c0ff8f clt_u\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 79e3104f clt_u\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 79802907 clti_u\.b \$w4,\$w5,0 +[0-9a-f]+ <[^>]*> 799f3987 clti_u\.b \$w6,\$w7,31 +[0-9a-f]+ <[^>]*> 79a04a07 clti_u\.h \$w8,\$w9,0 +[0-9a-f]+ <[^>]*> 79bf5a87 clti_u\.h \$w10,\$w11,31 +[0-9a-f]+ <[^>]*> 79c06b07 clti_u\.w \$w12,\$w13,0 +[0-9a-f]+ <[^>]*> 79df7b87 clti_u\.w \$w14,\$w15,31 +[0-9a-f]+ <[^>]*> 79e08c07 clti_u\.d \$w16,\$w17,0 +[0-9a-f]+ <[^>]*> 79ff9c87 clti_u\.d \$w18,\$w19,31 +[0-9a-f]+ <[^>]*> 7a16ad0f cle_s\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7a39c5cf cle_s\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 7a5cde8f cle_s\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 7a7ff74f cle_s\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 7a100807 clei_s\.b \$w0,\$w1,-16 +[0-9a-f]+ <[^>]*> 7a0f1887 clei_s\.b \$w2,\$w3,15 +[0-9a-f]+ <[^>]*> 7a302907 clei_s\.h \$w4,\$w5,-16 +[0-9a-f]+ <[^>]*> 7a2f3987 clei_s\.h \$w6,\$w7,15 +[0-9a-f]+ <[^>]*> 7a504a07 clei_s\.w \$w8,\$w9,-16 +[0-9a-f]+ <[^>]*> 7a4f5a87 clei_s\.w \$w10,\$w11,15 +[0-9a-f]+ <[^>]*> 7a706b07 clei_s\.d \$w12,\$w13,-16 +[0-9a-f]+ <[^>]*> 7a6f7b87 clei_s\.d \$w14,\$w15,15 +[0-9a-f]+ <[^>]*> 7a928c0f cle_u\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 7ab5a4cf cle_u\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 7ad8bd8f cle_u\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 7afbd64f cle_u\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 7a80ef07 clei_u\.b \$w28,\$w29,0 +[0-9a-f]+ <[^>]*> 7a9fff87 clei_u\.b \$w30,\$w31,31 +[0-9a-f]+ <[^>]*> 7aa00807 clei_u\.h \$w0,\$w1,0 +[0-9a-f]+ <[^>]*> 7abf1887 clei_u\.h \$w2,\$w3,31 +[0-9a-f]+ <[^>]*> 7ac02907 clei_u\.w \$w4,\$w5,0 +[0-9a-f]+ <[^>]*> 7adf3987 clei_u\.w \$w6,\$w7,31 +[0-9a-f]+ <[^>]*> 7ae04a07 clei_u\.d \$w8,\$w9,0 +[0-9a-f]+ <[^>]*> 7aff5a87 clei_u\.d \$w10,\$w11,31 +[0-9a-f]+ <[^>]*> 7a006b20 ld\.b \$w12,-512\(t5\) +[0-9a-f]+ <[^>]*> 79ff7ba0 ld\.b \$w14,511\(t7\) +[0-9a-f]+ <[^>]*> 7a008c21 ld\.h \$w16,-1024\(s1\) +[0-9a-f]+ <[^>]*> 79ff9ca1 ld\.h \$w18,1022\(s3\) +[0-9a-f]+ <[^>]*> 7a00ad22 ld\.w \$w20,-2048\(s5\) +[0-9a-f]+ <[^>]*> 79ffbda2 ld\.w \$w22,2044\(s7\) +[0-9a-f]+ <[^>]*> 7a00ce23 ld\.d \$w24,-4096\(t9\) +[0-9a-f]+ <[^>]*> 79ffdea3 ld\.d \$w26,4088\(k1\) +[0-9a-f]+ <[^>]*> 7a00ef24 st\.b \$w28,-512\(sp\) +[0-9a-f]+ <[^>]*> 79ffffa4 st\.b \$w30,511\(ra\) +[0-9a-f]+ <[^>]*> 7a000825 st\.h \$w0,-1024\(at\) +[0-9a-f]+ <[^>]*> 79ff18a5 st\.h \$w2,1022\(v1\) +[0-9a-f]+ <[^>]*> 7a002926 st\.w \$w4,-2048\(a1\) +[0-9a-f]+ <[^>]*> 79ff39a6 st\.w \$w6,2044\(a3\) +[0-9a-f]+ <[^>]*> 7a004a27 st\.d \$w8,-4096\(t1\) +[0-9a-f]+ <[^>]*> 79ff5aa7 st\.d \$w10,4088\(t3\) +[0-9a-f]+ <[^>]*> 78706b0a sat_s\.b \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 78777b8a sat_s\.b \$w14,\$w15,0x7 +[0-9a-f]+ <[^>]*> 78608c0a sat_s\.h \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 786f9c8a sat_s\.h \$w18,\$w19,0xf +[0-9a-f]+ <[^>]*> 7840ad0a sat_s\.w \$w20,\$w21,0x0 +[0-9a-f]+ <[^>]*> 785fbd8a sat_s\.w \$w22,\$w23,0x1f +[0-9a-f]+ <[^>]*> 7800ce0a sat_s\.d \$w24,\$w25,0x0 +[0-9a-f]+ <[^>]*> 783fde8a sat_s\.d \$w26,\$w27,0x3f +[0-9a-f]+ <[^>]*> 78f0ef0a sat_u\.b \$w28,\$w29,0x0 +[0-9a-f]+ <[^>]*> 78f7ff8a sat_u\.b \$w30,\$w31,0x7 +[0-9a-f]+ <[^>]*> 78e0080a sat_u\.h \$w0,\$w1,0x0 +[0-9a-f]+ <[^>]*> 78ef188a sat_u\.h \$w2,\$w3,0xf +[0-9a-f]+ <[^>]*> 78c0290a sat_u\.w \$w4,\$w5,0x0 +[0-9a-f]+ <[^>]*> 78df398a sat_u\.w \$w6,\$w7,0x1f +[0-9a-f]+ <[^>]*> 78804a0a sat_u\.d \$w8,\$w9,0x0 +[0-9a-f]+ <[^>]*> 78bf5a8a sat_u\.d \$w10,\$w11,0x3f +[0-9a-f]+ <[^>]*> 780e6b10 add_a\.b \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 783183d0 add_a\.h \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 78549c90 add_a\.w \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7877b550 add_a\.d \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 789ace10 adds_a\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 78bde6d0 adds_a\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 78c0ff90 adds_a\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 78e31050 adds_a\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 79062910 adds_s\.b \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 792941d0 adds_s\.h \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 794c5a90 adds_s\.w \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 796f7350 adds_s\.d \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 79928c10 adds_u\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 79b5a4d0 adds_u\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 79d8bd90 adds_u\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 79fbd650 adds_u\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 7a1eef10 ave_s\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 7a2107d0 ave_s\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 7a441890 ave_s\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 7a673150 ave_s\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 7a8a4a10 ave_u\.b \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 7aad62d0 ave_u\.h \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 7ad07b90 ave_u\.w \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7af39450 ave_u\.d \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7b16ad10 aver_s\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7b39c5d0 aver_s\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 7b5cde90 aver_s\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 7b7ff750 aver_s\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 7b820810 aver_u\.b \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 7ba520d0 aver_u\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7bc83990 aver_u\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 7beb5250 aver_u\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 780e6b11 subs_s\.b \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 783183d1 subs_s\.h \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 78549c91 subs_s\.w \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7877b551 subs_s\.d \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 789ace11 subs_u\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 78bde6d1 subs_u\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 78c0ff91 subs_u\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 78e31051 subs_u\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 79062911 subsus_u\.b \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 792941d1 subsus_u\.h \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 794c5a91 subsus_u\.w \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 796f7351 subsus_u\.d \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 79928c11 subsuu_s\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 79b5a4d1 subsuu_s\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 79d8bd91 subsuu_s\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 79fbd651 subsuu_s\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 7a1eef11 asub_s\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 7a2107d1 asub_s\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 7a441891 asub_s\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 7a673151 asub_s\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 7a8a4a11 asub_u\.b \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 7aad62d1 asub_u\.h \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 7ad07b91 asub_u\.w \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7af39451 asub_u\.d \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7816ad12 mulv\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7839c5d2 mulv\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 785cde92 mulv\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 787ff752 mulv\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 78820812 maddv\.b \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 78a520d2 maddv\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 78c83992 maddv\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 78eb5252 maddv\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 790e6b12 msubv\.b \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 793183d2 msubv\.h \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 79549c92 msubv\.w \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7977b552 msubv\.d \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 7a1ace12 div_s\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 7a3de6d2 div_s\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 7a40ff92 div_s\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 7a631052 div_s\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 7a862912 div_u\.b \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 7aa941d2 div_u\.h \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 7acc5a92 div_u\.w \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 7aef7352 div_u\.d \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 7b128c12 mod_s\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 7b35a4d2 mod_s\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 7b58bd92 mod_s\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 7b7bd652 mod_s\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 7b9eef12 mod_u\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 7ba107d2 mod_u\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 7bc41892 mod_u\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 7be73152 mod_u\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 782a4a13 dotp_s\.h \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 784d62d3 dotp_s\.w \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 78707b93 dotp_s\.d \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 78b39453 dotp_u\.h \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 78d6ad13 dotp_u\.w \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 78f9c5d3 dotp_u\.d \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 793cde93 dpadd_s\.h \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 795ff753 dpadd_s\.w \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 79620813 dpadd_s\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 79a520d3 dpadd_u\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 79c83993 dpadd_u\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 79eb5253 dpadd_u\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 7a2e6b13 dpsub_s\.h \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 7a5183d3 dpsub_s\.w \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 7a749c93 dpsub_s\.d \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7ab7b553 dpsub_u\.h \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 7adace13 dpsub_u\.w \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 7afde6d3 dpsub_u\.d \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 7800ff94 sld\.b \$w30,\$w31\[zero\] +[0-9a-f]+ <[^>]*> 78231054 sld\.h \$w1,\$w2\[v1\] +[0-9a-f]+ <[^>]*> 78462914 sld\.w \$w4,\$w5\[a2\] +[0-9a-f]+ <[^>]*> 786941d4 sld\.d \$w7,\$w8\[t1\] +[0-9a-f]+ <[^>]*> 78005a99 sldi\.b \$w10,\$w11\[0\] +[0-9a-f]+ <[^>]*> 780f6b19 sldi\.b \$w12,\$w13\[15\] +[0-9a-f]+ <[^>]*> 78207b99 sldi\.h \$w14,\$w15\[0\] +[0-9a-f]+ <[^>]*> 78278c19 sldi\.h \$w16,\$w17\[7\] +[0-9a-f]+ <[^>]*> 78309c99 sldi\.w \$w18,\$w19\[0\] +[0-9a-f]+ <[^>]*> 7833ad19 sldi\.w \$w20,\$w21\[3\] +[0-9a-f]+ <[^>]*> 7838bd99 sldi\.d \$w22,\$w23\[0\] +[0-9a-f]+ <[^>]*> 7839ce19 sldi\.d \$w24,\$w25\[1\] +[0-9a-f]+ <[^>]*> 789cde94 splat\.b \$w26,\$w27\[gp\] +[0-9a-f]+ <[^>]*> 78bff754 splat\.h \$w29,\$w30\[ra\] +[0-9a-f]+ <[^>]*> 78c20814 splat\.w \$w0,\$w1\[v0\] +[0-9a-f]+ <[^>]*> 78e520d4 splat\.d \$w3,\$w4\[a1\] +[0-9a-f]+ <[^>]*> 78403999 splati\.b \$w6,\$w7\[0\] +[0-9a-f]+ <[^>]*> 784f4a19 splati\.b \$w8,\$w9\[15\] +[0-9a-f]+ <[^>]*> 78605a99 splati\.h \$w10,\$w11\[0\] +[0-9a-f]+ <[^>]*> 78676b19 splati\.h \$w12,\$w13\[7\] +[0-9a-f]+ <[^>]*> 78707b99 splati\.w \$w14,\$w15\[0\] +[0-9a-f]+ <[^>]*> 78738c19 splati\.w \$w16,\$w17\[3\] +[0-9a-f]+ <[^>]*> 78789c99 splati\.d \$w18,\$w19\[0\] +[0-9a-f]+ <[^>]*> 7879ad19 splati\.d \$w20,\$w21\[1\] +[0-9a-f]+ <[^>]*> 7918bd94 pckev\.b \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 793bd654 pckev\.h \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 795eef14 pckev\.w \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 796107d4 pckev\.d \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 79841894 pckod\.b \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 79a73154 pckod\.h \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 79ca4a14 pckod\.w \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 79ed62d4 pckod\.d \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 7a107b94 ilvl\.b \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7a339454 ilvl\.h \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7a56ad14 ilvl\.w \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7a79c5d4 ilvl\.d \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 7a9cde94 ilvr\.b \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 7abff754 ilvr\.h \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 7ac20814 ilvr\.w \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 7ae520d4 ilvr\.d \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7b083994 ilvev\.b \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 7b2b5254 ilvev\.h \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 7b4e6b14 ilvev\.w \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 7b7183d4 ilvev\.d \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 7b949c94 ilvod\.b \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7bb7b554 ilvod\.h \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 7bdace14 ilvod\.w \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 7bfde6d4 ilvod\.d \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 7800ff95 vshf\.b \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 78231055 vshf\.h \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 78462915 vshf\.w \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 786941d5 vshf\.d \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 788c5a95 srar\.b \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 78af7355 srar\.h \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 78d28c15 srar\.w \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 78f5a4d5 srar\.d \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 7970bd8a srari\.b \$w22,\$w23,0x0 +[0-9a-f]+ <[^>]*> 7977ce0a srari\.b \$w24,\$w25,0x7 +[0-9a-f]+ <[^>]*> 7960de8a srari\.h \$w26,\$w27,0x0 +[0-9a-f]+ <[^>]*> 796fef0a srari\.h \$w28,\$w29,0xf +[0-9a-f]+ <[^>]*> 7940ff8a srari\.w \$w30,\$w31,0x0 +[0-9a-f]+ <[^>]*> 795f080a srari\.w \$w0,\$w1,0x1f +[0-9a-f]+ <[^>]*> 7900188a srari\.d \$w2,\$w3,0x0 +[0-9a-f]+ <[^>]*> 793f290a srari\.d \$w4,\$w5,0x3f +[0-9a-f]+ <[^>]*> 79083995 srlr\.b \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 792b5255 srlr\.h \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 794e6b15 srlr\.w \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 797183d5 srlr\.d \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 79f09c8a srlri\.b \$w18,\$w19,0x0 +[0-9a-f]+ <[^>]*> 79f7ad0a srlri\.b \$w20,\$w21,0x7 +[0-9a-f]+ <[^>]*> 79e0bd8a srlri\.h \$w22,\$w23,0x0 +[0-9a-f]+ <[^>]*> 79efce0a srlri\.h \$w24,\$w25,0xf +[0-9a-f]+ <[^>]*> 79c0de8a srlri\.w \$w26,\$w27,0x0 +[0-9a-f]+ <[^>]*> 79dfef0a srlri\.w \$w28,\$w29,0x1f +[0-9a-f]+ <[^>]*> 7980ff8a srlri\.d \$w30,\$w31,0x0 +[0-9a-f]+ <[^>]*> 79bf080a srlri\.d \$w0,\$w1,0x3f +[0-9a-f]+ <[^>]*> 7a241895 hadd_s\.h \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 7a473155 hadd_s\.w \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 7a6a4a15 hadd_s\.d \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 7aad62d5 hadd_u\.h \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 7ad07b95 hadd_u\.w \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7af39455 hadd_u\.d \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7b36ad15 hsub_s\.h \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7b59c5d5 hsub_s\.w \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 7b7cde95 hsub_s\.d \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 7bbff755 hsub_u\.h \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 7bc20815 hsub_u\.w \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 7be520d5 hsub_u\.d \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7808399e and\.v \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 78005240 andi\.b \$w9,\$w10,0x0 +[0-9a-f]+ <[^>]*> 78ff62c0 andi\.b \$w11,\$w12,0xff +[0-9a-f]+ <[^>]*> 782f735e or\.v \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 79008c00 ori\.b \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 79ff9c80 ori\.b \$w18,\$w19,0xff +[0-9a-f]+ <[^>]*> 7856ad1e nor\.v \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7a00c5c0 nori\.b \$w23,\$w24,0x0 +[0-9a-f]+ <[^>]*> 7affd640 nori\.b \$w25,\$w26,0xff +[0-9a-f]+ <[^>]*> 787de6de xor\.v \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 7b00ff80 xori\.b \$w30,\$w31,0x0 +[0-9a-f]+ <[^>]*> 7bff0800 xori\.b \$w0,\$w1,0xff +[0-9a-f]+ <[^>]*> 7884189e bmnz\.v \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 78003141 bmnzi\.b \$w5,\$w6,0x0 +[0-9a-f]+ <[^>]*> 78ff41c1 bmnzi\.b \$w7,\$w8,0xff +[0-9a-f]+ <[^>]*> 78ab525e bmz\.v \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 79006b01 bmzi\.b \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 79ff7b81 bmzi\.b \$w14,\$w15,0xff +[0-9a-f]+ <[^>]*> 78d28c1e bsel\.v \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 7a00a4c1 bseli\.b \$w19,\$w20,0x0 +[0-9a-f]+ <[^>]*> 7affb541 bseli\.b \$w21,\$w22,0xff +[0-9a-f]+ <[^>]*> 7800c5c2 shf\.b \$w23,\$w24,0x0 +[0-9a-f]+ <[^>]*> 78ffd642 shf\.b \$w25,\$w26,0xff +[0-9a-f]+ <[^>]*> 7900e6c2 shf\.h \$w27,\$w28,0x0 +[0-9a-f]+ <[^>]*> 79fff742 shf\.h \$w29,\$w30,0xff +[0-9a-f]+ <[^>]*> 7a0007c2 shf\.w \$w31,\$w0,0x0 +[0-9a-f]+ <[^>]*> 7aff1042 shf\.w \$w1,\$w2,0xff +[0-9a-f]+ <[^>]*> 45e38000 bnz\.v \$w3,[0-9a-f]+ <[^>]*> +[ ]*794: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45e47fff bnz\.v \$w4,[0-9a-f]+ <[^>]*> +[ ]*79c: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45e5ffff bnz\.v \$w5,[0-9a-f]+ <[^>]*> +[ ]*7a4: .*R_MIPS_PC16 .L1.1 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45e6ffff bnz\.v \$w6,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45678000 bz\.v \$w7,[0-9a-f]+ <[^>]*> +[ ]*7b4: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45687fff bz\.v \$w8,[0-9a-f]+ <[^>]*> +[ ]*7bc: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4569ffff bz\.v \$w9,[0-9a-f]+ <[^>]*> +[ ]*7c4: .*R_MIPS_PC16 .L1.2 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 456affff bz\.v \$w10,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 7b0062de fill\.b \$w11,t4 +[0-9a-f]+ <[^>]*> 7b01735e fill\.h \$w13,t6 +[0-9a-f]+ <[^>]*> 7b0283de fill\.w \$w15,s0 +[0-9a-f]+ <[^>]*> 7b04a4de pcnt\.b \$w19,\$w20 +[0-9a-f]+ <[^>]*> 7b05b55e pcnt\.h \$w21,\$w22 +[0-9a-f]+ <[^>]*> 7b06c5de pcnt\.w \$w23,\$w24 +[0-9a-f]+ <[^>]*> 7b07d65e pcnt\.d \$w25,\$w26 +[0-9a-f]+ <[^>]*> 7b08e6de nloc\.b \$w27,\$w28 +[0-9a-f]+ <[^>]*> 7b09f75e nloc\.h \$w29,\$w30 +[0-9a-f]+ <[^>]*> 7b0a07de nloc\.w \$w31,\$w0 +[0-9a-f]+ <[^>]*> 7b0b105e nloc\.d \$w1,\$w2 +[0-9a-f]+ <[^>]*> 7b0c20de nlzc\.b \$w3,\$w4 +[0-9a-f]+ <[^>]*> 7b0d315e nlzc\.h \$w5,\$w6 +[0-9a-f]+ <[^>]*> 7b0e41de nlzc\.w \$w7,\$w8 +[0-9a-f]+ <[^>]*> 7b0f525e nlzc\.d \$w9,\$w10 +[0-9a-f]+ <[^>]*> 788062d9 copy_s\.b t3,\$w12\[0\] +[0-9a-f]+ <[^>]*> 788f7359 copy_s\.b t5,\$w14\[15\] +[0-9a-f]+ <[^>]*> 78a083d9 copy_s\.h t7,\$w16\[0\] +[0-9a-f]+ <[^>]*> 78a79459 copy_s\.h s1,\$w18\[7\] +[0-9a-f]+ <[^>]*> 78b0a4d9 copy_s\.w s3,\$w20\[0\] +[0-9a-f]+ <[^>]*> 78b3b559 copy_s\.w s5,\$w22\[3\] +[0-9a-f]+ <[^>]*> 78c0e6d9 copy_u\.b k1,\$w28\[0\] +[0-9a-f]+ <[^>]*> 78cff759 copy_u\.b sp,\$w30\[15\] +[0-9a-f]+ <[^>]*> 78e007d9 copy_u\.h ra,\$w0\[0\] +[0-9a-f]+ <[^>]*> 78e71059 copy_u\.h at,\$w2\[7\] +[0-9a-f]+ <[^>]*> 78f020d9 copy_u\.w v1,\$w4\[0\] +[0-9a-f]+ <[^>]*> 78f33159 copy_u\.w a1,\$w6\[3\] +[0-9a-f]+ <[^>]*> 790062d9 insert\.b \$w11\[0\],t4 +[0-9a-f]+ <[^>]*> 790f7359 insert\.b \$w13\[15\],t6 +[0-9a-f]+ <[^>]*> 792083d9 insert\.h \$w15\[0\],s0 +[0-9a-f]+ <[^>]*> 79279459 insert\.h \$w17\[7\],s2 +[0-9a-f]+ <[^>]*> 7930a4d9 insert\.w \$w19\[0\],s4 +[0-9a-f]+ <[^>]*> 7933b559 insert\.w \$w21\[3\],s6 +[0-9a-f]+ <[^>]*> 7940e6d9 insve\.b \$w27\[0\],\$w28\[0\] +[0-9a-f]+ <[^>]*> 794ff759 insve\.b \$w29\[15\],\$w30\[0\] +[0-9a-f]+ <[^>]*> 796007d9 insve\.h \$w31\[0\],\$w0\[0\] +[0-9a-f]+ <[^>]*> 79671059 insve\.h \$w1\[7\],\$w2\[0\] +[0-9a-f]+ <[^>]*> 797020d9 insve\.w \$w3\[0\],\$w4\[0\] +[0-9a-f]+ <[^>]*> 79733159 insve\.w \$w5\[3\],\$w6\[0\] +[0-9a-f]+ <[^>]*> 797841d9 insve\.d \$w7\[0\],\$w8\[0\] +[0-9a-f]+ <[^>]*> 79795259 insve\.d \$w9\[1\],\$w10\[0\] +[0-9a-f]+ <[^>]*> 478b8000 bnz\.b \$w11,[0-9a-f]+ <[^>]*> +[ ]*878: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 478c7fff bnz\.b \$w12,[0-9a-f]+ <[^>]*> +[ ]*880: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 478dffff bnz\.b \$w13,[0-9a-f]+ <[^>]*> +[ ]*888: .*R_MIPS_PC16 .L1.3 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 478effff bnz\.b \$w14,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47af8000 bnz\.h \$w15,[0-9a-f]+ <[^>]*> +[ ]*898: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47b07fff bnz\.h \$w16,[0-9a-f]+ <[^>]*> +[ ]*8a0: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47b1ffff bnz\.h \$w17,[0-9a-f]+ <[^>]*> +[ ]*8a8: .*R_MIPS_PC16 .L1.4 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47b2ffff bnz\.h \$w18,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47d38000 bnz\.w \$w19,[0-9a-f]+ <[^>]*> +[ ]*8b8: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47d47fff bnz\.w \$w20,[0-9a-f]+ <[^>]*> +[ ]*8c0: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47d5ffff bnz\.w \$w21,[0-9a-f]+ <[^>]*> +[ ]*8c8: .*R_MIPS_PC16 .L1.5 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47d6ffff bnz\.w \$w22,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47f78000 bnz\.d \$w23,[0-9a-f]+ <[^>]*> +[ ]*8d8: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47f87fff bnz\.d \$w24,[0-9a-f]+ <[^>]*> +[ ]*8e0: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47f9ffff bnz\.d \$w25,[0-9a-f]+ <[^>]*> +[ ]*8e8: .*R_MIPS_PC16 .L1.6 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47faffff bnz\.d \$w26,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 471b8000 bz\.b \$w27,[0-9a-f]+ <[^>]*> +[ ]*8f8: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 471c7fff bz\.b \$w28,[0-9a-f]+ <[^>]*> +[ ]*900: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 471dffff bz\.b \$w29,[0-9a-f]+ <[^>]*> +[ ]*908: .*R_MIPS_PC16 .L1.7 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 471effff bz\.b \$w30,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 473f8000 bz\.h \$w31,[0-9a-f]+ <[^>]*> +[ ]*918: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47207fff bz\.h \$w0,[0-9a-f]+ <[^>]*> +[ ]*920: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4721ffff bz\.h \$w1,[0-9a-f]+ <[^>]*> +[ ]*928: .*R_MIPS_PC16 .L1.8 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4722ffff bz\.h \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47438000 bz\.w \$w3,[0-9a-f]+ <[^>]*> +[ ]*938: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47447fff bz\.w \$w4,[0-9a-f]+ <[^>]*> +[ ]*940: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4745ffff bz\.w \$w5,[0-9a-f]+ <[^>]*> +[ ]*948: .*R_MIPS_PC16 .L1.9 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4746ffff bz\.w \$w6,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47678000 bz\.d \$w7,[0-9a-f]+ <[^>]*> +[ ]*958: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47687fff bz\.d \$w8,[0-9a-f]+ <[^>]*> +[ ]*960: .*R_MIPS_PC16 L0. +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4769ffff bz\.d \$w9,[0-9a-f]+ <[^>]*> +[ ]*968: .*R_MIPS_PC16 .L1.10 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 476affff bz\.d \$w10,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 7b1002c7 ldi\.b \$w11,-512 +[0-9a-f]+ <[^>]*> 7b0ffb07 ldi\.b \$w12,511 +[0-9a-f]+ <[^>]*> 7b300347 ldi\.h \$w13,-512 +[0-9a-f]+ <[^>]*> 7b2ffb87 ldi\.h \$w14,511 +[0-9a-f]+ <[^>]*> 7b5003c7 ldi\.w \$w15,-512 +[0-9a-f]+ <[^>]*> 7b4ffc07 ldi\.w \$w16,511 +[0-9a-f]+ <[^>]*> 7b700447 ldi\.d \$w17,-512 +[0-9a-f]+ <[^>]*> 7b6ffc87 ldi\.d \$w18,511 +[0-9a-f]+ <[^>]*> 7815a4da fcaf\.w \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 7838bd9a fcaf\.d \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 785bd65a fcun\.w \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 787eef1a fcun\.d \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 788107da fceq\.w \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 78a4189a fceq\.d \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 78c7315a fcueq\.w \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 78ea4a1a fcueq\.d \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 790d62da fclt\.w \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 79307b9a fclt\.d \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7953945a fcult\.w \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7976ad1a fcult\.d \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7999c5da fcle\.w \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 79bcde9a fcle\.d \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 79dff75a fcule\.w \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 79e2081a fcule\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 7a0520da fsaf\.w \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7a28399a fsaf\.d \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 7a4b525a fsun\.w \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 7a6e6b1a fsun\.d \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 7a9183da fseq\.w \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 7ab49c9a fseq\.d \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7ad7b55a fsueq\.w \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 7aface1a fsueq\.d \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 7b1de6da fslt\.w \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 7b20ff9a fslt\.d \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 7b43105a fsult\.w \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 7b66291a fsult\.d \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 7b8941da fsle\.w \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 7bac5a9a fsle\.d \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 7bcf735a fsule\.w \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 7bf28c1a fsule\.d \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 7815a4db fadd\.w \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 7838bd9b fadd\.d \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 785bd65b fsub\.w \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 787eef1b fsub\.d \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 788107db fmul\.w \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 78a4189b fmul\.d \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 78c7315b fdiv\.w \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 78ea4a1b fdiv\.d \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 790d62db fmadd\.w \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 79307b9b fmadd\.d \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7953945b fmsub\.w \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7976ad1b fmsub\.d \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 79d9c5db fexp2\.w \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 79fcde9b fexp2\.d \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 7a1ff75b fexdo\.h \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 7a22081b fexdo\.w \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 7a8520db ftq\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7aa8399b ftq\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 7b0b525b fmin\.w \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 7b2e6b1b fmin\.d \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 7b5183db fmin_a\.w \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 7b749c9b fmin_a\.d \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7b97b55b fmax\.w \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 7bbace1b fmax\.d \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 7bdde6db fmax_a\.w \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 7be0ff9b fmax_a\.d \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 7843105c fcor\.w \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 7866291c fcor\.d \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 788941dc fcune\.w \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 78ac5a9c fcune\.d \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 78cf735c fcne\.w \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 78f28c1c fcne\.d \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 7915a4dc mul_q\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 7938bd9c mul_q\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 795bd65c madd_q\.h \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 797eef1c madd_q\.w \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 798107dc msub_q\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 79a4189c msub_q\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 7a47315c fsor\.w \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 7a6a4a1c fsor\.d \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 7a8d62dc fsune\.w \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 7ab07b9c fsune\.d \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7ad3945c fsne\.w \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7af6ad1c fsne\.d \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7b19c5dc mulr_q\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 7b3cde9c mulr_q\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 7b5ff75c maddr_q\.h \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 7b62081c maddr_q\.w \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 7b8520dc msubr_q\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7ba8399c msubr_q\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 7b20525e fclass\.w \$w9,\$w10 +[0-9a-f]+ <[^>]*> 7b2162de fclass\.d \$w11,\$w12 +[0-9a-f]+ <[^>]*> 7b22735e ftrunc_s\.w \$w13,\$w14 +[0-9a-f]+ <[^>]*> 7b2383de ftrunc_s\.d \$w15,\$w16 +[0-9a-f]+ <[^>]*> 7b24945e ftrunc_u\.w \$w17,\$w18 +[0-9a-f]+ <[^>]*> 7b25a4de ftrunc_u\.d \$w19,\$w20 +[0-9a-f]+ <[^>]*> 7b26b55e fsqrt\.w \$w21,\$w22 +[0-9a-f]+ <[^>]*> 7b27c5de fsqrt\.d \$w23,\$w24 +[0-9a-f]+ <[^>]*> 7b28d65e frsqrt\.w \$w25,\$w26 +[0-9a-f]+ <[^>]*> 7b29e6de frsqrt\.d \$w27,\$w28 +[0-9a-f]+ <[^>]*> 7b2af75e frcp\.w \$w29,\$w30 +[0-9a-f]+ <[^>]*> 7b2b07de frcp\.d \$w31,\$w0 +[0-9a-f]+ <[^>]*> 7b2c105e frint\.w \$w1,\$w2 +[0-9a-f]+ <[^>]*> 7b2d20de frint\.d \$w3,\$w4 +[0-9a-f]+ <[^>]*> 7b2e315e flog2\.w \$w5,\$w6 +[0-9a-f]+ <[^>]*> 7b2f41de flog2\.d \$w7,\$w8 +[0-9a-f]+ <[^>]*> 7b30525e fexupl\.w \$w9,\$w10 +[0-9a-f]+ <[^>]*> 7b3162de fexupl\.d \$w11,\$w12 +[0-9a-f]+ <[^>]*> 7b32735e fexupr\.w \$w13,\$w14 +[0-9a-f]+ <[^>]*> 7b3383de fexupr\.d \$w15,\$w16 +[0-9a-f]+ <[^>]*> 7b34945e ffql\.w \$w17,\$w18 +[0-9a-f]+ <[^>]*> 7b35a4de ffql\.d \$w19,\$w20 +[0-9a-f]+ <[^>]*> 7b36b55e ffqr\.w \$w21,\$w22 +[0-9a-f]+ <[^>]*> 7b37c5de ffqr\.d \$w23,\$w24 +[0-9a-f]+ <[^>]*> 7b38d65e ftint_s\.w \$w25,\$w26 +[0-9a-f]+ <[^>]*> 7b39e6de ftint_s\.d \$w27,\$w28 +[0-9a-f]+ <[^>]*> 7b3af75e ftint_u\.w \$w29,\$w30 +[0-9a-f]+ <[^>]*> 7b3b07de ftint_u\.d \$w31,\$w0 +[0-9a-f]+ <[^>]*> 7b3c105e ffint_s\.w \$w1,\$w2 +[0-9a-f]+ <[^>]*> 7b3d20de ffint_s\.d \$w3,\$w4 +[0-9a-f]+ <[^>]*> 7b3e315e ffint_u\.w \$w5,\$w6 +[0-9a-f]+ <[^>]*> 7b3f41de ffint_u\.d \$w7,\$w8 +[0-9a-f]+ <[^>]*> 783e4819 ctcmsa msa_ir,t1 +[0-9a-f]+ <[^>]*> 783e5059 ctcmsa msa_csr,t2 +[0-9a-f]+ <[^>]*> 783e5899 ctcmsa msa_access,t3 +[0-9a-f]+ <[^>]*> 783e60d9 ctcmsa msa_save,t4 +[0-9a-f]+ <[^>]*> 787e0359 cfcmsa t5,msa_ir +[0-9a-f]+ <[^>]*> 787e0b99 cfcmsa t6,msa_csr +[0-9a-f]+ <[^>]*> 787e13d9 cfcmsa t7,msa_access +[0-9a-f]+ <[^>]*> 787e1c19 cfcmsa s0,msa_save +[0-9a-f]+ <[^>]*> 78be9459 move\.v \$w17,\$w18 +[0-9a-f]+ <[^>]*> 02959805 lsa s3,s4,s5,0x1 +[0-9a-f]+ <[^>]*> 02f8b0c5 lsa s6,s7,t8,0x4 + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@pref.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@pref.d new file mode 100644 index 0000000..a644665 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@pref.d @@ -0,0 +1,13 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS PREF instruction +#as: -32 --defsym tpref=1 +#source: cache.s + +# Check MIPS PREF instruction assembly. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 7c457fb5 pref 0x5,255\(v0\) +[0-9a-f]+ <[^>]*> 7c658035 pref 0x5,-256\(v1\) + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/mipsr6@relax-swap3.d b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@relax-swap3.d new file mode 100644 index 0000000..a848901 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/mipsr6@relax-swap3.d @@ -0,0 +1,22 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS relaxed macro with branch swapping +#as: -32 +#source: relax-swap3.s + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 3c020000 lui v0,0x0 +[ ]*[0-9a-f]+: R_MIPS_HI16 bar +[0-9a-f]+ <[^>]*> 24420000 addiu v0,v0,0 +[ ]*[0-9a-f]+: R_MIPS_LO16 bar +[0-9a-f]+ <[^>]*> 00600009 jr v1 +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 3c020000 lui v0,0x0 +[ ]*[0-9a-f]+: R_MIPS_HI16 bar +[0-9a-f]+ <[^>]*> 24420000 addiu v0,v0,0 +[ ]*[0-9a-f]+: R_MIPS_LO16 bar +[0-9a-f]+ <[^>]*> 1060ffff beqz v1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 .L.1 +[0-9a-f]+ <[^>]*> 00000000 nop + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-check-warn.l b/binutils-2.24/gas/testsuite/gas/mips/module-check-warn.l new file mode 100644 index 0000000..2670b91 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-check-warn.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*:3: Error: `fp=64' used with a 32-bit fpu +.*:3: Warning: float register should be even, was 1 +.*:3: Warning: float register should be even, was 1 +.*:3: Warning: float register should be even, was 1 diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-check-warn.s b/binutils-2.24/gas/testsuite/gas/mips/module-check-warn.s new file mode 100644 index 0000000..ee5c3f0 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-check-warn.s @@ -0,0 +1,3 @@ +.module mips1 +.module fp=64 +add.s $f1,$f1,$f1 diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-check.d b/binutils-2.24/gas/testsuite/gas/mips/module-check.d new file mode 100644 index 0000000..516dedd --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-check.d @@ -0,0 +1,21 @@ +#as: -32 +#readelf: -A +#name: MIPS module check + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-check.s b/binutils-2.24/gas/testsuite/gas/mips/module-check.s new file mode 100644 index 0000000..09dec20 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-check.s @@ -0,0 +1,4 @@ +.module mips1 +.module fp=64 +.module mips32r2 +add.s $f1,$f1,$f1 diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-defer-warn1.d b/binutils-2.24/gas/testsuite/gas/mips/module-defer-warn1.d new file mode 100644 index 0000000..c20f367 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-defer-warn1.d @@ -0,0 +1,20 @@ +# name: .module deferred warnings +# source: module-defer-warn1.s +# objdump: -p +# as: -32 -march=mips2 -mgp64 + +.*:.*file format.*elf.*mips.* +private flags = 1.......: .*\[mips2\].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-defer-warn1.s b/binutils-2.24/gas/testsuite/gas/mips/module-defer-warn1.s new file mode 100644 index 0000000..d9cbf39 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-defer-warn1.s @@ -0,0 +1,2 @@ +.module gp=32 +addiu $2, $2, 1 diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-defer-warn2.l b/binutils-2.24/gas/testsuite/gas/mips/module-defer-warn2.l new file mode 100644 index 0000000..f03ad48 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-defer-warn2.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*:2: Error: `gp=64' used with a 32-bit processor +.*:2: Error: `fp=64' used with a 32-bit fpu diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-defer-warn2.s b/binutils-2.24/gas/testsuite/gas/mips/module-defer-warn2.s new file mode 100644 index 0000000..f7353e5 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-defer-warn2.s @@ -0,0 +1,2 @@ +.module gp=64 +addiu $2, $2, 1 diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-mfp32.d b/binutils-2.24/gas/testsuite/gas/mips/module-mfp32.d new file mode 100644 index 0000000..f5c66f6 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-mfp32.d @@ -0,0 +1,21 @@ +#as: -32 +#readelf: -A +#name: MIPS module fp=32 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS1 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-mfp32.s b/binutils-2.24/gas/testsuite/gas/mips/module-mfp32.s new file mode 100644 index 0000000..8f247b4 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-mfp32.s @@ -0,0 +1,3 @@ +.module fp=32 +.module doublefloat +.module hardfloat diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-mfp64.d b/binutils-2.24/gas/testsuite/gas/mips/module-mfp64.d new file mode 100644 index 0000000..30bc06d --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-mfp64.d @@ -0,0 +1,21 @@ +#as: -mips32r2 -32 +#readelf: -A +#name: MIPS module fp=64 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-mfp64.s b/binutils-2.24/gas/testsuite/gas/mips/module-mfp64.s new file mode 100644 index 0000000..7e4ca39 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-mfp64.s @@ -0,0 +1,3 @@ +.module fp=64 +.module doublefloat +.module hardfloat diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-mfpxx.d b/binutils-2.24/gas/testsuite/gas/mips/module-mfpxx.d new file mode 100644 index 0000000..2387eb1 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-mfpxx.d @@ -0,0 +1,21 @@ +#as: -mips32r2 -32 +#readelf: -A +#name: MIPS module fp=xx + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-mfpxx.s b/binutils-2.24/gas/testsuite/gas/mips/module-mfpxx.s new file mode 100644 index 0000000..8dd2a4c --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-mfpxx.s @@ -0,0 +1,3 @@ +.module fp=xx +.module doublefloat +.module hardfloat diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-msingle-float.d b/binutils-2.24/gas/testsuite/gas/mips/module-msingle-float.d new file mode 100644 index 0000000..588003f --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-msingle-float.d @@ -0,0 +1,21 @@ +#as: -32 +#readelf: -A +#name: MIPS module singlefloat + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS1 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-msingle-float.s b/binutils-2.24/gas/testsuite/gas/mips/module-msingle-float.s new file mode 100644 index 0000000..082cccf --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-msingle-float.s @@ -0,0 +1,3 @@ +.module fp=32 +.module singlefloat +.module hardfloat diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-msoft-float.d b/binutils-2.24/gas/testsuite/gas/mips/module-msoft-float.d new file mode 100644 index 0000000..98a9ea1 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-msoft-float.d @@ -0,0 +1,21 @@ +#as: -32 +#readelf: -A +#name: MIPS module softfloat + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS1 +GPR size: 32 +CPR1 size: 0 +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-msoft-float.s b/binutils-2.24/gas/testsuite/gas/mips/module-msoft-float.s new file mode 100644 index 0000000..4de4be7 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-msoft-float.s @@ -0,0 +1,3 @@ +.module fp=32 +.module doublefloat +.module softfloat diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-override.d b/binutils-2.24/gas/testsuite/gas/mips/module-override.d new file mode 100644 index 0000000..464eb06 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-override.d @@ -0,0 +1,20 @@ +# name: .module command line override +# source: module-override.s +# objdump: -p +# as: -32 -march=mips32r2 + +.*:.*file format.*elf.*mips.* +private flags = 1.......: .*\[mips2\].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-override.s b/binutils-2.24/gas/testsuite/gas/mips/module-override.s new file mode 100644 index 0000000..05f4a17 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-override.s @@ -0,0 +1 @@ +.module mips2 diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-set-mfpxx.d b/binutils-2.24/gas/testsuite/gas/mips/module-set-mfpxx.d new file mode 100644 index 0000000..c37157c --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-set-mfpxx.d @@ -0,0 +1,21 @@ +#as: -32 +#readelf: -A +#name: MIPS module fp=xx set + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/module-set-mfpxx.s b/binutils-2.24/gas/testsuite/gas/mips/module-set-mfpxx.s new file mode 100644 index 0000000..313d768 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/module-set-mfpxx.s @@ -0,0 +1,16 @@ +.module mips32r2 +.module fp=xx +.module doublefloat +.module hardfloat +.module oddspreg + +add.s $f1,$f1,$f1 +.set push +.set fp=32 +add.s $f1,$f1,$f1 +.set pop + +.set push +.set fp=64 +add.d $f1,$f1,$f1 +.set pop diff --git a/binutils-2.24/gas/testsuite/gas/mips/msa-branch.d b/binutils-2.24/gas/testsuite/gas/mips/msa-branch.d new file mode 100644 index 0000000..fbab5cc --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/msa-branch.d @@ -0,0 +1,218 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa +#name: MSA branch reorder +#as: -32 -mmsa + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4700.... bz\.b \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4701.... bz\.b \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4702.... bz\.b \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4700.... bz\.b \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4701.... bz\.b \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4702.... bz\.b \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4700.... bz\.b \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4701.... bz\.b \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4702.... bz\.b \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4720.... bz\.h \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4721.... bz\.h \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4722.... bz\.h \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4720.... bz\.h \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4721.... bz\.h \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4722.... bz\.h \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4720.... bz\.h \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4721.... bz\.h \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4722.... bz\.h \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4740.... bz\.w \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4741.... bz\.w \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4742.... bz\.w \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4740.... bz\.w \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4741.... bz\.w \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4742.... bz\.w \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4740.... bz\.w \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4741.... bz\.w \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4742.... bz\.w \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4760.... bz\.d \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4761.... bz\.d \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4762.... bz\.d \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4760.... bz\.d \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4761.... bz\.d \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4762.... bz\.d \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4760.... bz\.d \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4761.... bz\.d \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4762.... bz\.d \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4560.... bz\.v \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4561.... bz\.v \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4562.... bz\.v \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4560.... bz\.v \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4561.... bz\.v \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4562.... bz\.v \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4560.... bz\.v \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4561.... bz\.v \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4562.... bz\.v \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4780.... bnz\.b \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4781.... bnz\.b \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 4782.... bnz\.b \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4780.... bnz\.b \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4781.... bnz\.b \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 4782.... bnz\.b \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4780.... bnz\.b \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4781.... bnz\.b \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 4782.... bnz\.b \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 47a0.... bnz\.h \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47a1.... bnz\.h \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 47a2.... bnz\.h \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 47a0.... bnz\.h \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47a1.... bnz\.h \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 47a2.... bnz\.h \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 47a0.... bnz\.h \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47a1.... bnz\.h \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 47a2.... bnz\.h \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 47c0.... bnz\.w \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47c1.... bnz\.w \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 47c2.... bnz\.w \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 47c0.... bnz\.w \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47c1.... bnz\.w \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 47c2.... bnz\.w \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 47c0.... bnz\.w \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47c1.... bnz\.w \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 47c2.... bnz\.w \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 47e0.... bnz\.d \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47e1.... bnz\.d \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 47e2.... bnz\.d \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 47e0.... bnz\.d \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47e1.... bnz\.d \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 47e2.... bnz\.d \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 47e0.... bnz\.d \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47e1.... bnz\.d \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 47e2.... bnz\.d \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 45e0.... bnz\.v \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45e1.... bnz\.v \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 45e2.... bnz\.v \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 45e0.... bnz\.v \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45e1.... bnz\.v \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 45e2.... bnz\.v \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 45e0.... bnz\.v \$w0,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45e1.... bnz\.v \$w1,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 45e2.... bnz\.v \$w2,[0-9a-f]+ <test> +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/msa-branch.s b/binutils-2.24/gas/testsuite/gas/mips/msa-branch.s new file mode 100644 index 0000000..acf4b20 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/msa-branch.s @@ -0,0 +1,196 @@ + .text + .set reorder +test: + fsune.d $w0,$w1,$w2 + bz.b $w0, test + fsune.d $w0,$w1,$w2 + bz.b $w1, test + fsune.d $w0,$w1,$w2 + bz.b $w2, test + add.s $f0,$f1,$f2 + bz.b $w0, test + add.s $f0,$f1,$f2 + bz.b $w1, test + add.s $f0,$f1,$f2 + bz.b $w2, test + add.d $f0,$f2,$f4 + bz.b $w0, test + add.d $f0,$f2,$f4 + bz.b $w1, test + add.d $f0,$f2,$f4 + bz.b $w2, test + + fsune.d $w0,$w1,$w2 + bz.h $w0, test + fsune.d $w0,$w1,$w2 + bz.h $w1, test + fsune.d $w0,$w1,$w2 + bz.h $w2, test + add.s $f0,$f1,$f2 + bz.h $w0, test + add.s $f0,$f1,$f2 + bz.h $w1, test + add.s $f0,$f1,$f2 + bz.h $w2, test + add.d $f0,$f2,$f4 + bz.h $w0, test + add.d $f0,$f2,$f4 + bz.h $w1, test + add.d $f0,$f2,$f4 + bz.h $w2, test + + fsune.d $w0,$w1,$w2 + bz.w $w0, test + fsune.d $w0,$w1,$w2 + bz.w $w1, test + fsune.d $w0,$w1,$w2 + bz.w $w2, test + add.s $f0,$f1,$f2 + bz.w $w0, test + add.s $f0,$f1,$f2 + bz.w $w1, test + add.s $f0,$f1,$f2 + bz.w $w2, test + add.d $f0,$f2,$f4 + bz.w $w0, test + add.d $f0,$f2,$f4 + bz.w $w1, test + add.d $f0,$f2,$f4 + bz.w $w2, test + + fsune.d $w0,$w1,$w2 + bz.d $w0, test + fsune.d $w0,$w1,$w2 + bz.d $w1, test + fsune.d $w0,$w1,$w2 + bz.d $w2, test + add.s $f0,$f1,$f2 + bz.d $w0, test + add.s $f0,$f1,$f2 + bz.d $w1, test + add.s $f0,$f1,$f2 + bz.d $w2, test + add.d $f0,$f2,$f4 + bz.d $w0, test + add.d $f0,$f2,$f4 + bz.d $w1, test + add.d $f0,$f2,$f4 + bz.d $w2, test + + fsune.d $w0,$w1,$w2 + bz.v $w0, test + fsune.d $w0,$w1,$w2 + bz.v $w1, test + fsune.d $w0,$w1,$w2 + bz.v $w2, test + add.s $f0,$f1,$f2 + bz.v $w0, test + add.s $f0,$f1,$f2 + bz.v $w1, test + add.s $f0,$f1,$f2 + bz.v $w2, test + add.d $f0,$f2,$f4 + bz.v $w0, test + add.d $f0,$f2,$f4 + bz.v $w1, test + add.d $f0,$f2,$f4 + bz.v $w2, test + + fsune.d $w0,$w1,$w2 + bnz.b $w0, test + fsune.d $w0,$w1,$w2 + bnz.b $w1, test + fsune.d $w0,$w1,$w2 + bnz.b $w2, test + add.s $f0,$f1,$f2 + bnz.b $w0, test + add.s $f0,$f1,$f2 + bnz.b $w1, test + add.s $f0,$f1,$f2 + bnz.b $w2, test + add.d $f0,$f2,$f4 + bnz.b $w0, test + add.d $f0,$f2,$f4 + bnz.b $w1, test + add.d $f0,$f2,$f4 + bnz.b $w2, test + + fsune.d $w0,$w1,$w2 + bnz.h $w0, test + fsune.d $w0,$w1,$w2 + bnz.h $w1, test + fsune.d $w0,$w1,$w2 + bnz.h $w2, test + add.s $f0,$f1,$f2 + bnz.h $w0, test + add.s $f0,$f1,$f2 + bnz.h $w1, test + add.s $f0,$f1,$f2 + bnz.h $w2, test + add.d $f0,$f2,$f4 + bnz.h $w0, test + add.d $f0,$f2,$f4 + bnz.h $w1, test + add.d $f0,$f2,$f4 + bnz.h $w2, test + + fsune.d $w0,$w1,$w2 + bnz.w $w0, test + fsune.d $w0,$w1,$w2 + bnz.w $w1, test + fsune.d $w0,$w1,$w2 + bnz.w $w2, test + add.s $f0,$f1,$f2 + bnz.w $w0, test + add.s $f0,$f1,$f2 + bnz.w $w1, test + add.s $f0,$f1,$f2 + bnz.w $w2, test + add.d $f0,$f2,$f4 + bnz.w $w0, test + add.d $f0,$f2,$f4 + bnz.w $w1, test + add.d $f0,$f2,$f4 + bnz.w $w2, test + + fsune.d $w0,$w1,$w2 + bnz.d $w0, test + fsune.d $w0,$w1,$w2 + bnz.d $w1, test + fsune.d $w0,$w1,$w2 + bnz.d $w2, test + add.s $f0,$f1,$f2 + bnz.d $w0, test + add.s $f0,$f1,$f2 + bnz.d $w1, test + add.s $f0,$f1,$f2 + bnz.d $w2, test + add.d $f0,$f2,$f4 + bnz.d $w0, test + add.d $f0,$f2,$f4 + bnz.d $w1, test + add.d $f0,$f2,$f4 + bnz.d $w2, test + + fsune.d $w0,$w1,$w2 + bnz.v $w0, test + fsune.d $w0,$w1,$w2 + bnz.v $w1, test + fsune.d $w0,$w1,$w2 + bnz.v $w2, test + add.s $f0,$f1,$f2 + bnz.v $w0, test + add.s $f0,$f1,$f2 + bnz.v $w1, test + add.s $f0,$f1,$f2 + bnz.v $w2, test + add.d $f0,$f2,$f4 + bnz.v $w0, test + add.d $f0,$f2,$f4 + bnz.v $w1, test + add.d $f0,$f2,$f4 + bnz.v $w2, test + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 2 + .space 8 diff --git a/binutils-2.24/gas/testsuite/gas/mips/msa-relax.d b/binutils-2.24/gas/testsuite/gas/mips/msa-relax.d new file mode 100644 index 0000000..5dcfbb4 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/msa-relax.d @@ -0,0 +1,110 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa +#name: MSA relax +#as: -32 -mmsa -relax-branch +#stderr: msa-relax.l + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 47800002 bnz\.b \$w0,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47a10002 bnz\.h \$w1,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47c20002 bnz\.w \$w2,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47e30002 bnz\.d \$w3,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47040002 bz\.b \$w4,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47250002 bz\.h \$w5,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47460002 bz\.w \$w6,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47670002 bz\.d \$w7,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45e80002 bnz\.v \$w8,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45690002 bz\.v \$w9,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08008028 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop + \.\.\. +[0-9a-f]+ <[^>]*> 478a0002 bnz\.b \$w10,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47ab0002 bnz\.h \$w11,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47cc0002 bnz\.w \$w12,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47ed0002 bnz\.d \$w13,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 470e0002 bz\.b \$w14,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 472f0002 bz\.h \$w15,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47500002 bz\.w \$w16,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47710002 bz\.d \$w17,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45f20002 bnz\.v \$w18,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45730002 bz\.v \$w19,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 08000000 j [0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_26 \.text +[0-9a-f]+ <[^>]*> 00000000 nop + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/msa-relax.l b/binutils-2.24/gas/testsuite/gas/mips/msa-relax.l new file mode 100644 index 0000000..b25cb52 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/msa-relax.l @@ -0,0 +1,21 @@ +.*: Assembler messages: +.*:3: Warning: relaxed out-of-range branch into a jump +.*:4: Warning: relaxed out-of-range branch into a jump +.*:5: Warning: relaxed out-of-range branch into a jump +.*:6: Warning: relaxed out-of-range branch into a jump +.*:7: Warning: relaxed out-of-range branch into a jump +.*:8: Warning: relaxed out-of-range branch into a jump +.*:9: Warning: relaxed out-of-range branch into a jump +.*:10: Warning: relaxed out-of-range branch into a jump +.*:11: Warning: relaxed out-of-range branch into a jump +.*:12: Warning: relaxed out-of-range branch into a jump +.*:16: Warning: relaxed out-of-range branch into a jump +.*:17: Warning: relaxed out-of-range branch into a jump +.*:18: Warning: relaxed out-of-range branch into a jump +.*:19: Warning: relaxed out-of-range branch into a jump +.*:20: Warning: relaxed out-of-range branch into a jump +.*:21: Warning: relaxed out-of-range branch into a jump +.*:22: Warning: relaxed out-of-range branch into a jump +.*:23: Warning: relaxed out-of-range branch into a jump +.*:24: Warning: relaxed out-of-range branch into a jump +.*:25: Warning: relaxed out-of-range branch into a jump diff --git a/binutils-2.24/gas/testsuite/gas/mips/msa-relax.s b/binutils-2.24/gas/testsuite/gas/mips/msa-relax.s new file mode 100644 index 0000000..9df64f3 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/msa-relax.s @@ -0,0 +1,29 @@ + .text +foo: + bz.b $w0, bar + bz.h $w1, bar + bz.w $w2, bar + bz.d $w3, bar + bnz.b $w4, bar + bnz.h $w5, bar + bnz.w $w6, bar + bnz.d $w7, bar + bz.v $w8, bar + bnz.v $w9, bar + + .space 0x20000 # to make a 128kb loop body +bar: + bz.b $w10, foo + bz.h $w11, foo + bz.w $w12, foo + bz.d $w13, foo + bnz.b $w14, foo + bnz.h $w15, foo + bnz.w $w16, foo + bnz.d $w17, foo + bz.v $w18, foo + bnz.v $w19, foo + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 2 + .space 8 diff --git a/binutils-2.24/gas/testsuite/gas/mips/msa.d b/binutils-2.24/gas/testsuite/gas/mips/msa.d new file mode 100644 index 0000000..488fb5d --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/msa.d @@ -0,0 +1,757 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa +#name: MSA instructions +#as: -32 -mmsa --defsym insn_log2=2 + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 7802080d sll\.b \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 782520cd sll\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7848398d sll\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 786b524d sll\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 78706b09 slli\.b \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 78777b89 slli\.b \$w14,\$w15,0x7 +[0-9a-f]+ <[^>]*> 78608c09 slli\.h \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 786f9c89 slli\.h \$w18,\$w19,0xf +[0-9a-f]+ <[^>]*> 7840ad09 slli\.w \$w20,\$w21,0x0 +[0-9a-f]+ <[^>]*> 785fbd89 slli\.w \$w22,\$w23,0x1f +[0-9a-f]+ <[^>]*> 7800ce09 slli\.d \$w24,\$w25,0x0 +[0-9a-f]+ <[^>]*> 783fde89 slli\.d \$w26,\$w27,0x3f +[0-9a-f]+ <[^>]*> 789eef0d sra\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 78a107cd sra\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 78c4188d sra\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 78e7314d sra\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 78f04a09 srai\.b \$w8,\$w9,0x0 +[0-9a-f]+ <[^>]*> 78f75a89 srai\.b \$w10,\$w11,0x7 +[0-9a-f]+ <[^>]*> 78e06b09 srai\.h \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 78ef7b89 srai\.h \$w14,\$w15,0xf +[0-9a-f]+ <[^>]*> 78c08c09 srai\.w \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 78df9c89 srai\.w \$w18,\$w19,0x1f +[0-9a-f]+ <[^>]*> 7880ad09 srai\.d \$w20,\$w21,0x0 +[0-9a-f]+ <[^>]*> 78bfbd89 srai\.d \$w22,\$w23,0x3f +[0-9a-f]+ <[^>]*> 791ace0d srl\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 793de6cd srl\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 7940ff8d srl\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 7963104d srl\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 79702909 srli\.b \$w4,\$w5,0x0 +[0-9a-f]+ <[^>]*> 79773989 srli\.b \$w6,\$w7,0x7 +[0-9a-f]+ <[^>]*> 79604a09 srli\.h \$w8,\$w9,0x0 +[0-9a-f]+ <[^>]*> 796f5a89 srli\.h \$w10,\$w11,0xf +[0-9a-f]+ <[^>]*> 79406b09 srli\.w \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 795f7b89 srli\.w \$w14,\$w15,0x1f +[0-9a-f]+ <[^>]*> 79008c09 srli\.d \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 793f9c89 srli\.d \$w18,\$w19,0x3f +[0-9a-f]+ <[^>]*> 7996ad0d bclr\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 79b9c5cd bclr\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 79dcde8d bclr\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 79fff74d bclr\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 79f00809 bclri\.b \$w0,\$w1,0x0 +[0-9a-f]+ <[^>]*> 79f71889 bclri\.b \$w2,\$w3,0x7 +[0-9a-f]+ <[^>]*> 79e02909 bclri\.h \$w4,\$w5,0x0 +[0-9a-f]+ <[^>]*> 79ef3989 bclri\.h \$w6,\$w7,0xf +[0-9a-f]+ <[^>]*> 79c04a09 bclri\.w \$w8,\$w9,0x0 +[0-9a-f]+ <[^>]*> 79df5a89 bclri\.w \$w10,\$w11,0x1f +[0-9a-f]+ <[^>]*> 79806b09 bclri\.d \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 79bf7b89 bclri\.d \$w14,\$w15,0x3f +[0-9a-f]+ <[^>]*> 7a128c0d bset\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 7a35a4cd bset\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 7a58bd8d bset\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 7a7bd64d bset\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 7a70ef09 bseti\.b \$w28,\$w29,0x0 +[0-9a-f]+ <[^>]*> 7a77ff89 bseti\.b \$w30,\$w31,0x7 +[0-9a-f]+ <[^>]*> 7a600809 bseti\.h \$w0,\$w1,0x0 +[0-9a-f]+ <[^>]*> 7a6f1889 bseti\.h \$w2,\$w3,0xf +[0-9a-f]+ <[^>]*> 7a402909 bseti\.w \$w4,\$w5,0x0 +[0-9a-f]+ <[^>]*> 7a5f3989 bseti\.w \$w6,\$w7,0x1f +[0-9a-f]+ <[^>]*> 7a004a09 bseti\.d \$w8,\$w9,0x0 +[0-9a-f]+ <[^>]*> 7a3f5a89 bseti\.d \$w10,\$w11,0x3f +[0-9a-f]+ <[^>]*> 7a8e6b0d bneg\.b \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 7ab183cd bneg\.h \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 7ad49c8d bneg\.w \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7af7b54d bneg\.d \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 7af0ce09 bnegi\.b \$w24,\$w25,0x0 +[0-9a-f]+ <[^>]*> 7af7de89 bnegi\.b \$w26,\$w27,0x7 +[0-9a-f]+ <[^>]*> 7ae0ef09 bnegi\.h \$w28,\$w29,0x0 +[0-9a-f]+ <[^>]*> 7aefff89 bnegi\.h \$w30,\$w31,0xf +[0-9a-f]+ <[^>]*> 7ac00809 bnegi\.w \$w0,\$w1,0x0 +[0-9a-f]+ <[^>]*> 7adf1889 bnegi\.w \$w2,\$w3,0x1f +[0-9a-f]+ <[^>]*> 7a802909 bnegi\.d \$w4,\$w5,0x0 +[0-9a-f]+ <[^>]*> 7abf3989 bnegi\.d \$w6,\$w7,0x3f +[0-9a-f]+ <[^>]*> 7b0a4a0d binsl\.b \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 7b2d62cd binsl\.h \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 7b507b8d binsl\.w \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7b73944d binsl\.d \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7b70ad09 binsli\.b \$w20,\$w21,0x0 +[0-9a-f]+ <[^>]*> 7b77bd89 binsli\.b \$w22,\$w23,0x7 +[0-9a-f]+ <[^>]*> 7b60ce09 binsli\.h \$w24,\$w25,0x0 +[0-9a-f]+ <[^>]*> 7b6fde89 binsli\.h \$w26,\$w27,0xf +[0-9a-f]+ <[^>]*> 7b40ef09 binsli\.w \$w28,\$w29,0x0 +[0-9a-f]+ <[^>]*> 7b5fff89 binsli\.w \$w30,\$w31,0x1f +[0-9a-f]+ <[^>]*> 7b000809 binsli\.d \$w0,\$w1,0x0 +[0-9a-f]+ <[^>]*> 7b3f1889 binsli\.d \$w2,\$w3,0x3f +[0-9a-f]+ <[^>]*> 7b86290d binsr\.b \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 7ba941cd binsr\.h \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 7bcc5a8d binsr\.w \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 7bef734d binsr\.d \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 7bf08c09 binsri\.b \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 7bf79c89 binsri\.b \$w18,\$w19,0x7 +[0-9a-f]+ <[^>]*> 7be0ad09 binsri\.h \$w20,\$w21,0x0 +[0-9a-f]+ <[^>]*> 7befbd89 binsri\.h \$w22,\$w23,0xf +[0-9a-f]+ <[^>]*> 7bc0ce09 binsri\.w \$w24,\$w25,0x0 +[0-9a-f]+ <[^>]*> 7bdfde89 binsri\.w \$w26,\$w27,0x1f +[0-9a-f]+ <[^>]*> 7b80ef09 binsri\.d \$w28,\$w29,0x0 +[0-9a-f]+ <[^>]*> 7bbfff89 binsri\.d \$w30,\$w31,0x3f +[0-9a-f]+ <[^>]*> 7802080e addv\.b \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 782520ce addv\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7848398e addv\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 786b524e addv\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 78006b06 addvi\.b \$w12,\$w13,0 +[0-9a-f]+ <[^>]*> 781f7b86 addvi\.b \$w14,\$w15,31 +[0-9a-f]+ <[^>]*> 78208c06 addvi\.h \$w16,\$w17,0 +[0-9a-f]+ <[^>]*> 783f9c86 addvi\.h \$w18,\$w19,31 +[0-9a-f]+ <[^>]*> 7840ad06 addvi\.w \$w20,\$w21,0 +[0-9a-f]+ <[^>]*> 785fbd86 addvi\.w \$w22,\$w23,31 +[0-9a-f]+ <[^>]*> 7860ce06 addvi\.d \$w24,\$w25,0 +[0-9a-f]+ <[^>]*> 787fde86 addvi\.d \$w26,\$w27,31 +[0-9a-f]+ <[^>]*> 789eef0e subv\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 78a107ce subv\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 78c4188e subv\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 78e7314e subv\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 78804a06 subvi\.b \$w8,\$w9,0 +[0-9a-f]+ <[^>]*> 789f5a86 subvi\.b \$w10,\$w11,31 +[0-9a-f]+ <[^>]*> 78a06b06 subvi\.h \$w12,\$w13,0 +[0-9a-f]+ <[^>]*> 78bf7b86 subvi\.h \$w14,\$w15,31 +[0-9a-f]+ <[^>]*> 78c08c06 subvi\.w \$w16,\$w17,0 +[0-9a-f]+ <[^>]*> 78df9c86 subvi\.w \$w18,\$w19,31 +[0-9a-f]+ <[^>]*> 78e0ad06 subvi\.d \$w20,\$w21,0 +[0-9a-f]+ <[^>]*> 78ffbd86 subvi\.d \$w22,\$w23,31 +[0-9a-f]+ <[^>]*> 791ace0e max_s\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 793de6ce max_s\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 7940ff8e max_s\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 7963104e max_s\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 79102906 maxi_s\.b \$w4,\$w5,-16 +[0-9a-f]+ <[^>]*> 790f3986 maxi_s\.b \$w6,\$w7,15 +[0-9a-f]+ <[^>]*> 79304a06 maxi_s\.h \$w8,\$w9,-16 +[0-9a-f]+ <[^>]*> 792f5a86 maxi_s\.h \$w10,\$w11,15 +[0-9a-f]+ <[^>]*> 79506b06 maxi_s\.w \$w12,\$w13,-16 +[0-9a-f]+ <[^>]*> 794f7b86 maxi_s\.w \$w14,\$w15,15 +[0-9a-f]+ <[^>]*> 79708c06 maxi_s\.d \$w16,\$w17,-16 +[0-9a-f]+ <[^>]*> 796f9c86 maxi_s\.d \$w18,\$w19,15 +[0-9a-f]+ <[^>]*> 7996ad0e max_u\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 79b9c5ce max_u\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 79dcde8e max_u\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 79fff74e max_u\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 79800806 maxi_u\.b \$w0,\$w1,0 +[0-9a-f]+ <[^>]*> 799f1886 maxi_u\.b \$w2,\$w3,31 +[0-9a-f]+ <[^>]*> 79a02906 maxi_u\.h \$w4,\$w5,0 +[0-9a-f]+ <[^>]*> 79bf3986 maxi_u\.h \$w6,\$w7,31 +[0-9a-f]+ <[^>]*> 79c04a06 maxi_u\.w \$w8,\$w9,0 +[0-9a-f]+ <[^>]*> 79df5a86 maxi_u\.w \$w10,\$w11,31 +[0-9a-f]+ <[^>]*> 79e06b06 maxi_u\.d \$w12,\$w13,0 +[0-9a-f]+ <[^>]*> 79ff7b86 maxi_u\.d \$w14,\$w15,31 +[0-9a-f]+ <[^>]*> 7a128c0e min_s\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 7a35a4ce min_s\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 7a58bd8e min_s\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 7a7bd64e min_s\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 7a10ef06 mini_s\.b \$w28,\$w29,-16 +[0-9a-f]+ <[^>]*> 7a0fff86 mini_s\.b \$w30,\$w31,15 +[0-9a-f]+ <[^>]*> 7a300806 mini_s\.h \$w0,\$w1,-16 +[0-9a-f]+ <[^>]*> 7a2f1886 mini_s\.h \$w2,\$w3,15 +[0-9a-f]+ <[^>]*> 7a502906 mini_s\.w \$w4,\$w5,-16 +[0-9a-f]+ <[^>]*> 7a4f3986 mini_s\.w \$w6,\$w7,15 +[0-9a-f]+ <[^>]*> 7a704a06 mini_s\.d \$w8,\$w9,-16 +[0-9a-f]+ <[^>]*> 7a6f5a86 mini_s\.d \$w10,\$w11,15 +[0-9a-f]+ <[^>]*> 7a8e6b0e min_u\.b \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 7ab183ce min_u\.h \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 7ad49c8e min_u\.w \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7af7b54e min_u\.d \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 7a80ce06 mini_u\.b \$w24,\$w25,0 +[0-9a-f]+ <[^>]*> 7a9fde86 mini_u\.b \$w26,\$w27,31 +[0-9a-f]+ <[^>]*> 7aa0ef06 mini_u\.h \$w28,\$w29,0 +[0-9a-f]+ <[^>]*> 7abfff86 mini_u\.h \$w30,\$w31,31 +[0-9a-f]+ <[^>]*> 7ac00806 mini_u\.w \$w0,\$w1,0 +[0-9a-f]+ <[^>]*> 7adf1886 mini_u\.w \$w2,\$w3,31 +[0-9a-f]+ <[^>]*> 7ae02906 mini_u\.d \$w4,\$w5,0 +[0-9a-f]+ <[^>]*> 7aff3986 mini_u\.d \$w6,\$w7,31 +[0-9a-f]+ <[^>]*> 7b0a4a0e max_a\.b \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 7b2d62ce max_a\.h \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 7b507b8e max_a\.w \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7b73944e max_a\.d \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7b96ad0e min_a\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7bb9c5ce min_a\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 7bdcde8e min_a\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 7bfff74e min_a\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 7802080f ceq\.b \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 782520cf ceq\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7848398f ceq\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 786b524f ceq\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 78106b07 ceqi\.b \$w12,\$w13,-16 +[0-9a-f]+ <[^>]*> 780f7b87 ceqi\.b \$w14,\$w15,15 +[0-9a-f]+ <[^>]*> 78308c07 ceqi\.h \$w16,\$w17,-16 +[0-9a-f]+ <[^>]*> 782f9c87 ceqi\.h \$w18,\$w19,15 +[0-9a-f]+ <[^>]*> 7850ad07 ceqi\.w \$w20,\$w21,-16 +[0-9a-f]+ <[^>]*> 784fbd87 ceqi\.w \$w22,\$w23,15 +[0-9a-f]+ <[^>]*> 7870ce07 ceqi\.d \$w24,\$w25,-16 +[0-9a-f]+ <[^>]*> 786fde87 ceqi\.d \$w26,\$w27,15 +[0-9a-f]+ <[^>]*> 791eef0f clt_s\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 792107cf clt_s\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 7944188f clt_s\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 7967314f clt_s\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 79104a07 clti_s\.b \$w8,\$w9,-16 +[0-9a-f]+ <[^>]*> 790f5a87 clti_s\.b \$w10,\$w11,15 +[0-9a-f]+ <[^>]*> 79306b07 clti_s\.h \$w12,\$w13,-16 +[0-9a-f]+ <[^>]*> 792f7b87 clti_s\.h \$w14,\$w15,15 +[0-9a-f]+ <[^>]*> 79508c07 clti_s\.w \$w16,\$w17,-16 +[0-9a-f]+ <[^>]*> 794f9c87 clti_s\.w \$w18,\$w19,15 +[0-9a-f]+ <[^>]*> 7970ad07 clti_s\.d \$w20,\$w21,-16 +[0-9a-f]+ <[^>]*> 796fbd87 clti_s\.d \$w22,\$w23,15 +[0-9a-f]+ <[^>]*> 799ace0f clt_u\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 79bde6cf clt_u\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 79c0ff8f clt_u\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 79e3104f clt_u\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 79802907 clti_u\.b \$w4,\$w5,0 +[0-9a-f]+ <[^>]*> 799f3987 clti_u\.b \$w6,\$w7,31 +[0-9a-f]+ <[^>]*> 79a04a07 clti_u\.h \$w8,\$w9,0 +[0-9a-f]+ <[^>]*> 79bf5a87 clti_u\.h \$w10,\$w11,31 +[0-9a-f]+ <[^>]*> 79c06b07 clti_u\.w \$w12,\$w13,0 +[0-9a-f]+ <[^>]*> 79df7b87 clti_u\.w \$w14,\$w15,31 +[0-9a-f]+ <[^>]*> 79e08c07 clti_u\.d \$w16,\$w17,0 +[0-9a-f]+ <[^>]*> 79ff9c87 clti_u\.d \$w18,\$w19,31 +[0-9a-f]+ <[^>]*> 7a16ad0f cle_s\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7a39c5cf cle_s\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 7a5cde8f cle_s\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 7a7ff74f cle_s\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 7a100807 clei_s\.b \$w0,\$w1,-16 +[0-9a-f]+ <[^>]*> 7a0f1887 clei_s\.b \$w2,\$w3,15 +[0-9a-f]+ <[^>]*> 7a302907 clei_s\.h \$w4,\$w5,-16 +[0-9a-f]+ <[^>]*> 7a2f3987 clei_s\.h \$w6,\$w7,15 +[0-9a-f]+ <[^>]*> 7a504a07 clei_s\.w \$w8,\$w9,-16 +[0-9a-f]+ <[^>]*> 7a4f5a87 clei_s\.w \$w10,\$w11,15 +[0-9a-f]+ <[^>]*> 7a706b07 clei_s\.d \$w12,\$w13,-16 +[0-9a-f]+ <[^>]*> 7a6f7b87 clei_s\.d \$w14,\$w15,15 +[0-9a-f]+ <[^>]*> 7a928c0f cle_u\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 7ab5a4cf cle_u\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 7ad8bd8f cle_u\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 7afbd64f cle_u\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 7a80ef07 clei_u\.b \$w28,\$w29,0 +[0-9a-f]+ <[^>]*> 7a9fff87 clei_u\.b \$w30,\$w31,31 +[0-9a-f]+ <[^>]*> 7aa00807 clei_u\.h \$w0,\$w1,0 +[0-9a-f]+ <[^>]*> 7abf1887 clei_u\.h \$w2,\$w3,31 +[0-9a-f]+ <[^>]*> 7ac02907 clei_u\.w \$w4,\$w5,0 +[0-9a-f]+ <[^>]*> 7adf3987 clei_u\.w \$w6,\$w7,31 +[0-9a-f]+ <[^>]*> 7ae04a07 clei_u\.d \$w8,\$w9,0 +[0-9a-f]+ <[^>]*> 7aff5a87 clei_u\.d \$w10,\$w11,31 +[0-9a-f]+ <[^>]*> 7a006b20 ld\.b \$w12,-512\(t5\) +[0-9a-f]+ <[^>]*> 79ff7ba0 ld\.b \$w14,511\(t7\) +[0-9a-f]+ <[^>]*> 7a008c21 ld\.h \$w16,-1024\(s1\) +[0-9a-f]+ <[^>]*> 79ff9ca1 ld\.h \$w18,1022\(s3\) +[0-9a-f]+ <[^>]*> 7a00ad22 ld\.w \$w20,-2048\(s5\) +[0-9a-f]+ <[^>]*> 79ffbda2 ld\.w \$w22,2044\(s7\) +[0-9a-f]+ <[^>]*> 7a00ce23 ld\.d \$w24,-4096\(t9\) +[0-9a-f]+ <[^>]*> 79ffdea3 ld\.d \$w26,4088\(k1\) +[0-9a-f]+ <[^>]*> 7a00ef24 st\.b \$w28,-512\(sp\) +[0-9a-f]+ <[^>]*> 79ffffa4 st\.b \$w30,511\(ra\) +[0-9a-f]+ <[^>]*> 7a000825 st\.h \$w0,-1024\(at\) +[0-9a-f]+ <[^>]*> 79ff18a5 st\.h \$w2,1022\(v1\) +[0-9a-f]+ <[^>]*> 7a002926 st\.w \$w4,-2048\(a1\) +[0-9a-f]+ <[^>]*> 79ff39a6 st\.w \$w6,2044\(a3\) +[0-9a-f]+ <[^>]*> 7a004a27 st\.d \$w8,-4096\(t1\) +[0-9a-f]+ <[^>]*> 79ff5aa7 st\.d \$w10,4088\(t3\) +[0-9a-f]+ <[^>]*> 78706b0a sat_s\.b \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 78777b8a sat_s\.b \$w14,\$w15,0x7 +[0-9a-f]+ <[^>]*> 78608c0a sat_s\.h \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 786f9c8a sat_s\.h \$w18,\$w19,0xf +[0-9a-f]+ <[^>]*> 7840ad0a sat_s\.w \$w20,\$w21,0x0 +[0-9a-f]+ <[^>]*> 785fbd8a sat_s\.w \$w22,\$w23,0x1f +[0-9a-f]+ <[^>]*> 7800ce0a sat_s\.d \$w24,\$w25,0x0 +[0-9a-f]+ <[^>]*> 783fde8a sat_s\.d \$w26,\$w27,0x3f +[0-9a-f]+ <[^>]*> 78f0ef0a sat_u\.b \$w28,\$w29,0x0 +[0-9a-f]+ <[^>]*> 78f7ff8a sat_u\.b \$w30,\$w31,0x7 +[0-9a-f]+ <[^>]*> 78e0080a sat_u\.h \$w0,\$w1,0x0 +[0-9a-f]+ <[^>]*> 78ef188a sat_u\.h \$w2,\$w3,0xf +[0-9a-f]+ <[^>]*> 78c0290a sat_u\.w \$w4,\$w5,0x0 +[0-9a-f]+ <[^>]*> 78df398a sat_u\.w \$w6,\$w7,0x1f +[0-9a-f]+ <[^>]*> 78804a0a sat_u\.d \$w8,\$w9,0x0 +[0-9a-f]+ <[^>]*> 78bf5a8a sat_u\.d \$w10,\$w11,0x3f +[0-9a-f]+ <[^>]*> 780e6b10 add_a\.b \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 783183d0 add_a\.h \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 78549c90 add_a\.w \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7877b550 add_a\.d \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 789ace10 adds_a\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 78bde6d0 adds_a\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 78c0ff90 adds_a\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 78e31050 adds_a\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 79062910 adds_s\.b \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 792941d0 adds_s\.h \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 794c5a90 adds_s\.w \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 796f7350 adds_s\.d \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 79928c10 adds_u\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 79b5a4d0 adds_u\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 79d8bd90 adds_u\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 79fbd650 adds_u\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 7a1eef10 ave_s\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 7a2107d0 ave_s\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 7a441890 ave_s\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 7a673150 ave_s\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 7a8a4a10 ave_u\.b \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 7aad62d0 ave_u\.h \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 7ad07b90 ave_u\.w \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7af39450 ave_u\.d \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7b16ad10 aver_s\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7b39c5d0 aver_s\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 7b5cde90 aver_s\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 7b7ff750 aver_s\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 7b820810 aver_u\.b \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 7ba520d0 aver_u\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7bc83990 aver_u\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 7beb5250 aver_u\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 780e6b11 subs_s\.b \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 783183d1 subs_s\.h \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 78549c91 subs_s\.w \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7877b551 subs_s\.d \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 789ace11 subs_u\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 78bde6d1 subs_u\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 78c0ff91 subs_u\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 78e31051 subs_u\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 79062911 subsus_u\.b \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 792941d1 subsus_u\.h \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 794c5a91 subsus_u\.w \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 796f7351 subsus_u\.d \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 79928c11 subsuu_s\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 79b5a4d1 subsuu_s\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 79d8bd91 subsuu_s\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 79fbd651 subsuu_s\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 7a1eef11 asub_s\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 7a2107d1 asub_s\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 7a441891 asub_s\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 7a673151 asub_s\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 7a8a4a11 asub_u\.b \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 7aad62d1 asub_u\.h \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 7ad07b91 asub_u\.w \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7af39451 asub_u\.d \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7816ad12 mulv\.b \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7839c5d2 mulv\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 785cde92 mulv\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 787ff752 mulv\.d \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 78820812 maddv\.b \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 78a520d2 maddv\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 78c83992 maddv\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 78eb5252 maddv\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 790e6b12 msubv\.b \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 793183d2 msubv\.h \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 79549c92 msubv\.w \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7977b552 msubv\.d \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 7a1ace12 div_s\.b \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 7a3de6d2 div_s\.h \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 7a40ff92 div_s\.w \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 7a631052 div_s\.d \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 7a862912 div_u\.b \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 7aa941d2 div_u\.h \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 7acc5a92 div_u\.w \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 7aef7352 div_u\.d \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 7b128c12 mod_s\.b \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 7b35a4d2 mod_s\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 7b58bd92 mod_s\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 7b7bd652 mod_s\.d \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 7b9eef12 mod_u\.b \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 7ba107d2 mod_u\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 7bc41892 mod_u\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 7be73152 mod_u\.d \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 782a4a13 dotp_s\.h \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 784d62d3 dotp_s\.w \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 78707b93 dotp_s\.d \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 78b39453 dotp_u\.h \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 78d6ad13 dotp_u\.w \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 78f9c5d3 dotp_u\.d \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 793cde93 dpadd_s\.h \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 795ff753 dpadd_s\.w \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 79620813 dpadd_s\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 79a520d3 dpadd_u\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 79c83993 dpadd_u\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 79eb5253 dpadd_u\.d \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 7a2e6b13 dpsub_s\.h \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 7a5183d3 dpsub_s\.w \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 7a749c93 dpsub_s\.d \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7ab7b553 dpsub_u\.h \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 7adace13 dpsub_u\.w \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 7afde6d3 dpsub_u\.d \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 7800ff94 sld\.b \$w30,\$w31\[zero\] +[0-9a-f]+ <[^>]*> 78231054 sld\.h \$w1,\$w2\[v1\] +[0-9a-f]+ <[^>]*> 78462914 sld\.w \$w4,\$w5\[a2\] +[0-9a-f]+ <[^>]*> 786941d4 sld\.d \$w7,\$w8\[t1\] +[0-9a-f]+ <[^>]*> 78005a99 sldi\.b \$w10,\$w11\[0\] +[0-9a-f]+ <[^>]*> 780f6b19 sldi\.b \$w12,\$w13\[15\] +[0-9a-f]+ <[^>]*> 78207b99 sldi\.h \$w14,\$w15\[0\] +[0-9a-f]+ <[^>]*> 78278c19 sldi\.h \$w16,\$w17\[7\] +[0-9a-f]+ <[^>]*> 78309c99 sldi\.w \$w18,\$w19\[0\] +[0-9a-f]+ <[^>]*> 7833ad19 sldi\.w \$w20,\$w21\[3\] +[0-9a-f]+ <[^>]*> 7838bd99 sldi\.d \$w22,\$w23\[0\] +[0-9a-f]+ <[^>]*> 7839ce19 sldi\.d \$w24,\$w25\[1\] +[0-9a-f]+ <[^>]*> 789cde94 splat\.b \$w26,\$w27\[gp\] +[0-9a-f]+ <[^>]*> 78bff754 splat\.h \$w29,\$w30\[ra\] +[0-9a-f]+ <[^>]*> 78c20814 splat\.w \$w0,\$w1\[v0\] +[0-9a-f]+ <[^>]*> 78e520d4 splat\.d \$w3,\$w4\[a1\] +[0-9a-f]+ <[^>]*> 78403999 splati\.b \$w6,\$w7\[0\] +[0-9a-f]+ <[^>]*> 784f4a19 splati\.b \$w8,\$w9\[15\] +[0-9a-f]+ <[^>]*> 78605a99 splati\.h \$w10,\$w11\[0\] +[0-9a-f]+ <[^>]*> 78676b19 splati\.h \$w12,\$w13\[7\] +[0-9a-f]+ <[^>]*> 78707b99 splati\.w \$w14,\$w15\[0\] +[0-9a-f]+ <[^>]*> 78738c19 splati\.w \$w16,\$w17\[3\] +[0-9a-f]+ <[^>]*> 78789c99 splati\.d \$w18,\$w19\[0\] +[0-9a-f]+ <[^>]*> 7879ad19 splati\.d \$w20,\$w21\[1\] +[0-9a-f]+ <[^>]*> 7918bd94 pckev\.b \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 793bd654 pckev\.h \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 795eef14 pckev\.w \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 796107d4 pckev\.d \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 79841894 pckod\.b \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 79a73154 pckod\.h \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 79ca4a14 pckod\.w \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 79ed62d4 pckod\.d \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 7a107b94 ilvl\.b \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7a339454 ilvl\.h \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7a56ad14 ilvl\.w \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7a79c5d4 ilvl\.d \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 7a9cde94 ilvr\.b \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 7abff754 ilvr\.h \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 7ac20814 ilvr\.w \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 7ae520d4 ilvr\.d \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7b083994 ilvev\.b \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 7b2b5254 ilvev\.h \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 7b4e6b14 ilvev\.w \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 7b7183d4 ilvev\.d \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 7b949c94 ilvod\.b \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7bb7b554 ilvod\.h \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 7bdace14 ilvod\.w \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 7bfde6d4 ilvod\.d \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 7800ff95 vshf\.b \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 78231055 vshf\.h \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 78462915 vshf\.w \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 786941d5 vshf\.d \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 788c5a95 srar\.b \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 78af7355 srar\.h \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 78d28c15 srar\.w \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 78f5a4d5 srar\.d \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 7970bd8a srari\.b \$w22,\$w23,0x0 +[0-9a-f]+ <[^>]*> 7977ce0a srari\.b \$w24,\$w25,0x7 +[0-9a-f]+ <[^>]*> 7960de8a srari\.h \$w26,\$w27,0x0 +[0-9a-f]+ <[^>]*> 796fef0a srari\.h \$w28,\$w29,0xf +[0-9a-f]+ <[^>]*> 7940ff8a srari\.w \$w30,\$w31,0x0 +[0-9a-f]+ <[^>]*> 795f080a srari\.w \$w0,\$w1,0x1f +[0-9a-f]+ <[^>]*> 7900188a srari\.d \$w2,\$w3,0x0 +[0-9a-f]+ <[^>]*> 793f290a srari\.d \$w4,\$w5,0x3f +[0-9a-f]+ <[^>]*> 79083995 srlr\.b \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 792b5255 srlr\.h \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 794e6b15 srlr\.w \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 797183d5 srlr\.d \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 79f09c8a srlri\.b \$w18,\$w19,0x0 +[0-9a-f]+ <[^>]*> 79f7ad0a srlri\.b \$w20,\$w21,0x7 +[0-9a-f]+ <[^>]*> 79e0bd8a srlri\.h \$w22,\$w23,0x0 +[0-9a-f]+ <[^>]*> 79efce0a srlri\.h \$w24,\$w25,0xf +[0-9a-f]+ <[^>]*> 79c0de8a srlri\.w \$w26,\$w27,0x0 +[0-9a-f]+ <[^>]*> 79dfef0a srlri\.w \$w28,\$w29,0x1f +[0-9a-f]+ <[^>]*> 7980ff8a srlri\.d \$w30,\$w31,0x0 +[0-9a-f]+ <[^>]*> 79bf080a srlri\.d \$w0,\$w1,0x3f +[0-9a-f]+ <[^>]*> 7a241895 hadd_s\.h \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 7a473155 hadd_s\.w \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 7a6a4a15 hadd_s\.d \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 7aad62d5 hadd_u\.h \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 7ad07b95 hadd_u\.w \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7af39455 hadd_u\.d \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7b36ad15 hsub_s\.h \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7b59c5d5 hsub_s\.w \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 7b7cde95 hsub_s\.d \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 7bbff755 hsub_u\.h \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 7bc20815 hsub_u\.w \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 7be520d5 hsub_u\.d \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7808399e and\.v \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 78005240 andi\.b \$w9,\$w10,0x0 +[0-9a-f]+ <[^>]*> 78ff62c0 andi\.b \$w11,\$w12,0xff +[0-9a-f]+ <[^>]*> 782f735e or\.v \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 79008c00 ori\.b \$w16,\$w17,0x0 +[0-9a-f]+ <[^>]*> 79ff9c80 ori\.b \$w18,\$w19,0xff +[0-9a-f]+ <[^>]*> 7856ad1e nor\.v \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7a00c5c0 nori\.b \$w23,\$w24,0x0 +[0-9a-f]+ <[^>]*> 7affd640 nori\.b \$w25,\$w26,0xff +[0-9a-f]+ <[^>]*> 787de6de xor\.v \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 7b00ff80 xori\.b \$w30,\$w31,0x0 +[0-9a-f]+ <[^>]*> 7bff0800 xori\.b \$w0,\$w1,0xff +[0-9a-f]+ <[^>]*> 7884189e bmnz\.v \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 78003141 bmnzi\.b \$w5,\$w6,0x0 +[0-9a-f]+ <[^>]*> 78ff41c1 bmnzi\.b \$w7,\$w8,0xff +[0-9a-f]+ <[^>]*> 78ab525e bmz\.v \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 79006b01 bmzi\.b \$w12,\$w13,0x0 +[0-9a-f]+ <[^>]*> 79ff7b81 bmzi\.b \$w14,\$w15,0xff +[0-9a-f]+ <[^>]*> 78d28c1e bsel\.v \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 7a00a4c1 bseli\.b \$w19,\$w20,0x0 +[0-9a-f]+ <[^>]*> 7affb541 bseli\.b \$w21,\$w22,0xff +[0-9a-f]+ <[^>]*> 7800c5c2 shf\.b \$w23,\$w24,0x0 +[0-9a-f]+ <[^>]*> 78ffd642 shf\.b \$w25,\$w26,0xff +[0-9a-f]+ <[^>]*> 7900e6c2 shf\.h \$w27,\$w28,0x0 +[0-9a-f]+ <[^>]*> 79fff742 shf\.h \$w29,\$w30,0xff +[0-9a-f]+ <[^>]*> 7a0007c2 shf\.w \$w31,\$w0,0x0 +[0-9a-f]+ <[^>]*> 7aff1042 shf\.w \$w1,\$w2,0xff +[0-9a-f]+ <[^>]*> 45e38000 bnz\.v \$w3,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45e47fff bnz\.v \$w4,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45e5fffb bnz\.v \$w5,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45e6ffff bnz\.v \$w6,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45678000 bz\.v \$w7,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 45687fff bz\.v \$w8,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4569fffb bz\.v \$w9,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 456affff bz\.v \$w10,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 7b0062de fill\.b \$w11,t4 +[0-9a-f]+ <[^>]*> 7b01735e fill\.h \$w13,t6 +[0-9a-f]+ <[^>]*> 7b0283de fill\.w \$w15,s0 +[0-9a-f]+ <[^>]*> 7b04a4de pcnt\.b \$w19,\$w20 +[0-9a-f]+ <[^>]*> 7b05b55e pcnt\.h \$w21,\$w22 +[0-9a-f]+ <[^>]*> 7b06c5de pcnt\.w \$w23,\$w24 +[0-9a-f]+ <[^>]*> 7b07d65e pcnt\.d \$w25,\$w26 +[0-9a-f]+ <[^>]*> 7b08e6de nloc\.b \$w27,\$w28 +[0-9a-f]+ <[^>]*> 7b09f75e nloc\.h \$w29,\$w30 +[0-9a-f]+ <[^>]*> 7b0a07de nloc\.w \$w31,\$w0 +[0-9a-f]+ <[^>]*> 7b0b105e nloc\.d \$w1,\$w2 +[0-9a-f]+ <[^>]*> 7b0c20de nlzc\.b \$w3,\$w4 +[0-9a-f]+ <[^>]*> 7b0d315e nlzc\.h \$w5,\$w6 +[0-9a-f]+ <[^>]*> 7b0e41de nlzc\.w \$w7,\$w8 +[0-9a-f]+ <[^>]*> 7b0f525e nlzc\.d \$w9,\$w10 +[0-9a-f]+ <[^>]*> 788062d9 copy_s\.b t3,\$w12\[0\] +[0-9a-f]+ <[^>]*> 788f7359 copy_s\.b t5,\$w14\[15\] +[0-9a-f]+ <[^>]*> 78a083d9 copy_s\.h t7,\$w16\[0\] +[0-9a-f]+ <[^>]*> 78a79459 copy_s\.h s1,\$w18\[7\] +[0-9a-f]+ <[^>]*> 78b0a4d9 copy_s\.w s3,\$w20\[0\] +[0-9a-f]+ <[^>]*> 78b3b559 copy_s\.w s5,\$w22\[3\] +[0-9a-f]+ <[^>]*> 78c0e6d9 copy_u\.b k1,\$w28\[0\] +[0-9a-f]+ <[^>]*> 78cff759 copy_u\.b sp,\$w30\[15\] +[0-9a-f]+ <[^>]*> 78e007d9 copy_u\.h ra,\$w0\[0\] +[0-9a-f]+ <[^>]*> 78e71059 copy_u\.h at,\$w2\[7\] +[0-9a-f]+ <[^>]*> 78f020d9 copy_u\.w v1,\$w4\[0\] +[0-9a-f]+ <[^>]*> 78f33159 copy_u\.w a1,\$w6\[3\] +[0-9a-f]+ <[^>]*> 790062d9 insert\.b \$w11\[0\],t4 +[0-9a-f]+ <[^>]*> 790f7359 insert\.b \$w13\[15\],t6 +[0-9a-f]+ <[^>]*> 792083d9 insert\.h \$w15\[0\],s0 +[0-9a-f]+ <[^>]*> 79279459 insert\.h \$w17\[7\],s2 +[0-9a-f]+ <[^>]*> 7930a4d9 insert\.w \$w19\[0\],s4 +[0-9a-f]+ <[^>]*> 7933b559 insert\.w \$w21\[3\],s6 +[0-9a-f]+ <[^>]*> 7940e6d9 insve\.b \$w27\[0\],\$w28\[0\] +[0-9a-f]+ <[^>]*> 794ff759 insve\.b \$w29\[15\],\$w30\[0\] +[0-9a-f]+ <[^>]*> 796007d9 insve\.h \$w31\[0\],\$w0\[0\] +[0-9a-f]+ <[^>]*> 79671059 insve\.h \$w1\[7\],\$w2\[0\] +[0-9a-f]+ <[^>]*> 797020d9 insve\.w \$w3\[0\],\$w4\[0\] +[0-9a-f]+ <[^>]*> 79733159 insve\.w \$w5\[3\],\$w6\[0\] +[0-9a-f]+ <[^>]*> 797841d9 insve\.d \$w7\[0\],\$w8\[0\] +[0-9a-f]+ <[^>]*> 79795259 insve\.d \$w9\[1\],\$w10\[0\] +[0-9a-f]+ <[^>]*> 478b8000 bnz\.b \$w11,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 478c7fff bnz\.b \$w12,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 478dfffb bnz\.b \$w13,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 478effff bnz\.b \$w14,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47af8000 bnz\.h \$w15,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47b07fff bnz\.h \$w16,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47b1fffb bnz\.h \$w17,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47b2ffff bnz\.h \$w18,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47d38000 bnz\.w \$w19,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47d47fff bnz\.w \$w20,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47d5fffb bnz\.w \$w21,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47d6ffff bnz\.w \$w22,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47f78000 bnz\.d \$w23,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47f87fff bnz\.d \$w24,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47f9fffb bnz\.d \$w25,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47faffff bnz\.d \$w26,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 471b8000 bz\.b \$w27,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 471c7fff bz\.b \$w28,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 471dfffb bz\.b \$w29,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 471effff bz\.b \$w30,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 473f8000 bz\.h \$w31,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47207fff bz\.h \$w0,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4721fffb bz\.h \$w1,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4722ffff bz\.h \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47438000 bz\.w \$w3,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47447fff bz\.w \$w4,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4745fffb bz\.w \$w5,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4746ffff bz\.w \$w6,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47678000 bz\.d \$w7,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 47687fff bz\.d \$w8,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 4769fffb bz\.d \$w9,[0-9a-f]+ <[^>]*> +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 476affff bz\.d \$w10,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MIPS_PC16 external_label +[0-9a-f]+ <[^>]*> 00000000 nop +[0-9a-f]+ <[^>]*> 7b1002c7 ldi\.b \$w11,-512 +[0-9a-f]+ <[^>]*> 7b0ffb07 ldi\.b \$w12,511 +[0-9a-f]+ <[^>]*> 7b300347 ldi\.h \$w13,-512 +[0-9a-f]+ <[^>]*> 7b2ffb87 ldi\.h \$w14,511 +[0-9a-f]+ <[^>]*> 7b5003c7 ldi\.w \$w15,-512 +[0-9a-f]+ <[^>]*> 7b4ffc07 ldi\.w \$w16,511 +[0-9a-f]+ <[^>]*> 7b700447 ldi\.d \$w17,-512 +[0-9a-f]+ <[^>]*> 7b6ffc87 ldi\.d \$w18,511 +[0-9a-f]+ <[^>]*> 7815a4da fcaf\.w \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 7838bd9a fcaf\.d \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 785bd65a fcun\.w \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 787eef1a fcun\.d \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 788107da fceq\.w \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 78a4189a fceq\.d \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 78c7315a fcueq\.w \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 78ea4a1a fcueq\.d \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 790d62da fclt\.w \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 79307b9a fclt\.d \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7953945a fcult\.w \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7976ad1a fcult\.d \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7999c5da fcle\.w \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 79bcde9a fcle\.d \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 79dff75a fcule\.w \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 79e2081a fcule\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 7a0520da fsaf\.w \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7a28399a fsaf\.d \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 7a4b525a fsun\.w \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 7a6e6b1a fsun\.d \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 7a9183da fseq\.w \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 7ab49c9a fseq\.d \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7ad7b55a fsueq\.w \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 7aface1a fsueq\.d \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 7b1de6da fslt\.w \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 7b20ff9a fslt\.d \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 7b43105a fsult\.w \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 7b66291a fsult\.d \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 7b8941da fsle\.w \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 7bac5a9a fsle\.d \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 7bcf735a fsule\.w \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 7bf28c1a fsule\.d \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 7815a4db fadd\.w \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 7838bd9b fadd\.d \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 785bd65b fsub\.w \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 787eef1b fsub\.d \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 788107db fmul\.w \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 78a4189b fmul\.d \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 78c7315b fdiv\.w \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 78ea4a1b fdiv\.d \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 790d62db fmadd\.w \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 79307b9b fmadd\.d \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7953945b fmsub\.w \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7976ad1b fmsub\.d \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 79d9c5db fexp2\.w \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 79fcde9b fexp2\.d \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 7a1ff75b fexdo\.h \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 7a22081b fexdo\.w \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 7a8520db ftq\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7aa8399b ftq\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 7b0b525b fmin\.w \$w9,\$w10,\$w11 +[0-9a-f]+ <[^>]*> 7b2e6b1b fmin\.d \$w12,\$w13,\$w14 +[0-9a-f]+ <[^>]*> 7b5183db fmin_a\.w \$w15,\$w16,\$w17 +[0-9a-f]+ <[^>]*> 7b749c9b fmin_a\.d \$w18,\$w19,\$w20 +[0-9a-f]+ <[^>]*> 7b97b55b fmax\.w \$w21,\$w22,\$w23 +[0-9a-f]+ <[^>]*> 7bbace1b fmax\.d \$w24,\$w25,\$w26 +[0-9a-f]+ <[^>]*> 7bdde6db fmax_a\.w \$w27,\$w28,\$w29 +[0-9a-f]+ <[^>]*> 7be0ff9b fmax_a\.d \$w30,\$w31,\$w0 +[0-9a-f]+ <[^>]*> 7843105c fcor\.w \$w1,\$w2,\$w3 +[0-9a-f]+ <[^>]*> 7866291c fcor\.d \$w4,\$w5,\$w6 +[0-9a-f]+ <[^>]*> 788941dc fcune\.w \$w7,\$w8,\$w9 +[0-9a-f]+ <[^>]*> 78ac5a9c fcune\.d \$w10,\$w11,\$w12 +[0-9a-f]+ <[^>]*> 78cf735c fcne\.w \$w13,\$w14,\$w15 +[0-9a-f]+ <[^>]*> 78f28c1c fcne\.d \$w16,\$w17,\$w18 +[0-9a-f]+ <[^>]*> 7915a4dc mul_q\.h \$w19,\$w20,\$w21 +[0-9a-f]+ <[^>]*> 7938bd9c mul_q\.w \$w22,\$w23,\$w24 +[0-9a-f]+ <[^>]*> 795bd65c madd_q\.h \$w25,\$w26,\$w27 +[0-9a-f]+ <[^>]*> 797eef1c madd_q\.w \$w28,\$w29,\$w30 +[0-9a-f]+ <[^>]*> 798107dc msub_q\.h \$w31,\$w0,\$w1 +[0-9a-f]+ <[^>]*> 79a4189c msub_q\.w \$w2,\$w3,\$w4 +[0-9a-f]+ <[^>]*> 7a47315c fsor\.w \$w5,\$w6,\$w7 +[0-9a-f]+ <[^>]*> 7a6a4a1c fsor\.d \$w8,\$w9,\$w10 +[0-9a-f]+ <[^>]*> 7a8d62dc fsune\.w \$w11,\$w12,\$w13 +[0-9a-f]+ <[^>]*> 7ab07b9c fsune\.d \$w14,\$w15,\$w16 +[0-9a-f]+ <[^>]*> 7ad3945c fsne\.w \$w17,\$w18,\$w19 +[0-9a-f]+ <[^>]*> 7af6ad1c fsne\.d \$w20,\$w21,\$w22 +[0-9a-f]+ <[^>]*> 7b19c5dc mulr_q\.h \$w23,\$w24,\$w25 +[0-9a-f]+ <[^>]*> 7b3cde9c mulr_q\.w \$w26,\$w27,\$w28 +[0-9a-f]+ <[^>]*> 7b5ff75c maddr_q\.h \$w29,\$w30,\$w31 +[0-9a-f]+ <[^>]*> 7b62081c maddr_q\.w \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 7b8520dc msubr_q\.h \$w3,\$w4,\$w5 +[0-9a-f]+ <[^>]*> 7ba8399c msubr_q\.w \$w6,\$w7,\$w8 +[0-9a-f]+ <[^>]*> 7b20525e fclass\.w \$w9,\$w10 +[0-9a-f]+ <[^>]*> 7b2162de fclass\.d \$w11,\$w12 +[0-9a-f]+ <[^>]*> 7b22735e ftrunc_s\.w \$w13,\$w14 +[0-9a-f]+ <[^>]*> 7b2383de ftrunc_s\.d \$w15,\$w16 +[0-9a-f]+ <[^>]*> 7b24945e ftrunc_u\.w \$w17,\$w18 +[0-9a-f]+ <[^>]*> 7b25a4de ftrunc_u\.d \$w19,\$w20 +[0-9a-f]+ <[^>]*> 7b26b55e fsqrt\.w \$w21,\$w22 +[0-9a-f]+ <[^>]*> 7b27c5de fsqrt\.d \$w23,\$w24 +[0-9a-f]+ <[^>]*> 7b28d65e frsqrt\.w \$w25,\$w26 +[0-9a-f]+ <[^>]*> 7b29e6de frsqrt\.d \$w27,\$w28 +[0-9a-f]+ <[^>]*> 7b2af75e frcp\.w \$w29,\$w30 +[0-9a-f]+ <[^>]*> 7b2b07de frcp\.d \$w31,\$w0 +[0-9a-f]+ <[^>]*> 7b2c105e frint\.w \$w1,\$w2 +[0-9a-f]+ <[^>]*> 7b2d20de frint\.d \$w3,\$w4 +[0-9a-f]+ <[^>]*> 7b2e315e flog2\.w \$w5,\$w6 +[0-9a-f]+ <[^>]*> 7b2f41de flog2\.d \$w7,\$w8 +[0-9a-f]+ <[^>]*> 7b30525e fexupl\.w \$w9,\$w10 +[0-9a-f]+ <[^>]*> 7b3162de fexupl\.d \$w11,\$w12 +[0-9a-f]+ <[^>]*> 7b32735e fexupr\.w \$w13,\$w14 +[0-9a-f]+ <[^>]*> 7b3383de fexupr\.d \$w15,\$w16 +[0-9a-f]+ <[^>]*> 7b34945e ffql\.w \$w17,\$w18 +[0-9a-f]+ <[^>]*> 7b35a4de ffql\.d \$w19,\$w20 +[0-9a-f]+ <[^>]*> 7b36b55e ffqr\.w \$w21,\$w22 +[0-9a-f]+ <[^>]*> 7b37c5de ffqr\.d \$w23,\$w24 +[0-9a-f]+ <[^>]*> 7b38d65e ftint_s\.w \$w25,\$w26 +[0-9a-f]+ <[^>]*> 7b39e6de ftint_s\.d \$w27,\$w28 +[0-9a-f]+ <[^>]*> 7b3af75e ftint_u\.w \$w29,\$w30 +[0-9a-f]+ <[^>]*> 7b3b07de ftint_u\.d \$w31,\$w0 +[0-9a-f]+ <[^>]*> 7b3c105e ffint_s\.w \$w1,\$w2 +[0-9a-f]+ <[^>]*> 7b3d20de ffint_s\.d \$w3,\$w4 +[0-9a-f]+ <[^>]*> 7b3e315e ffint_u\.w \$w5,\$w6 +[0-9a-f]+ <[^>]*> 7b3f41de ffint_u\.d \$w7,\$w8 +[0-9a-f]+ <[^>]*> 783e4819 ctcmsa msa_ir,t1 +[0-9a-f]+ <[^>]*> 783e5059 ctcmsa msa_csr,t2 +[0-9a-f]+ <[^>]*> 783e5899 ctcmsa msa_access,t3 +[0-9a-f]+ <[^>]*> 783e60d9 ctcmsa msa_save,t4 +[0-9a-f]+ <[^>]*> 787e0359 cfcmsa t5,msa_ir +[0-9a-f]+ <[^>]*> 787e0b99 cfcmsa t6,msa_csr +[0-9a-f]+ <[^>]*> 787e13d9 cfcmsa t7,msa_access +[0-9a-f]+ <[^>]*> 787e1c19 cfcmsa s0,msa_save +[0-9a-f]+ <[^>]*> 78be9459 move\.v \$w17,\$w18 +[0-9a-f]+ <[^>]*> 02959805 lsa s3,s4,s5,0x1 +[0-9a-f]+ <[^>]*> 02f8b0c5 lsa s6,s7,t8,0x4 + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/msa.s b/binutils-2.24/gas/testsuite/gas/mips/msa.s new file mode 100644 index 0000000..e16b6af --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/msa.s @@ -0,0 +1,758 @@ + .text + .set noat + .set noreorder + .set nomacro +test_msa: + sll.b $w0,$w1,$w2 + sll.h $w3,$w4,$w5 + sll.w $w6,$w7,$w8 + sll.d $w9,$w10,$w11 + slli.b $w12,$w13,0 + slli.b $w14,$w15,7 + slli.h $w16,$w17,0 + slli.h $w18,$w19,15 + slli.w $w20,$w21,0 + slli.w $w22,$w23,31 + slli.d $w24,$w25,0 + slli.d $w26,$w27,63 + sra.b $w28,$w29,$w30 + sra.h $w31,$w0,$w1 + sra.w $w2,$w3,$w4 + sra.d $w5,$w6,$w7 + srai.b $w8,$w9,0 + srai.b $w10,$w11,7 + srai.h $w12,$w13,0 + srai.h $w14,$w15,15 + srai.w $w16,$w17,0 + srai.w $w18,$w19,31 + srai.d $w20,$w21,0 + srai.d $w22,$w23,63 + srl.b $w24,$w25,$w26 + srl.h $w27,$w28,$w29 + srl.w $w30,$w31,$w0 + srl.d $w1,$w2,$w3 + srli.b $w4,$w5,0 + srli.b $w6,$w7,7 + srli.h $w8,$w9,0 + srli.h $w10,$w11,15 + srli.w $w12,$w13,0 + srli.w $w14,$w15,31 + srli.d $w16,$w17,0 + srli.d $w18,$w19,63 + bclr.b $w20,$w21,$w22 + bclr.h $w23,$w24,$w25 + bclr.w $w26,$w27,$w28 + bclr.d $w29,$w30,$w31 + bclri.b $w0,$w1,0 + bclri.b $w2,$w3,7 + bclri.h $w4,$w5,0 + bclri.h $w6,$w7,15 + bclri.w $w8,$w9,0 + bclri.w $w10,$w11,31 + bclri.d $w12,$w13,0 + bclri.d $w14,$w15,63 + bset.b $w16,$w17,$w18 + bset.h $w19,$w20,$w21 + bset.w $w22,$w23,$w24 + bset.d $w25,$w26,$w27 + bseti.b $w28,$w29,0 + bseti.b $w30,$w31,7 + bseti.h $w0,$w1,0 + bseti.h $w2,$w3,15 + bseti.w $w4,$w5,0 + bseti.w $w6,$w7,31 + bseti.d $w8,$w9,0 + bseti.d $w10,$w11,63 + bneg.b $w12,$w13,$w14 + bneg.h $w15,$w16,$w17 + bneg.w $w18,$w19,$w20 + bneg.d $w21,$w22,$w23 + bnegi.b $w24,$w25,0 + bnegi.b $w26,$w27,7 + bnegi.h $w28,$w29,0 + bnegi.h $w30,$w31,15 + bnegi.w $w0,$w1,0 + bnegi.w $w2,$w3,31 + bnegi.d $w4,$w5,0 + bnegi.d $w6,$w7,63 + binsl.b $w8,$w9,$w10 + binsl.h $w11,$w12,$w13 + binsl.w $w14,$w15,$w16 + binsl.d $w17,$w18,$w19 + binsli.b $w20,$w21,0 + binsli.b $w22,$w23,7 + binsli.h $w24,$w25,0 + binsli.h $w26,$w27,15 + binsli.w $w28,$w29,0 + binsli.w $w30,$w31,31 + binsli.d $w0,$w1,0 + binsli.d $w2,$w3,63 + binsr.b $w4,$w5,$w6 + binsr.h $w7,$w8,$w9 + binsr.w $w10,$w11,$w12 + binsr.d $w13,$w14,$w15 + binsri.b $w16,$w17,0 + binsri.b $w18,$w19,7 + binsri.h $w20,$w21,0 + binsri.h $w22,$w23,15 + binsri.w $w24,$w25,0 + binsri.w $w26,$w27,31 + binsri.d $w28,$w29,0 + binsri.d $w30,$w31,63 + addv.b $w0,$w1,$w2 + addv.h $w3,$w4,$w5 + addv.w $w6,$w7,$w8 + addv.d $w9,$w10,$w11 + addvi.b $w12,$w13,0 + addvi.b $w14,$w15,31 + addvi.h $w16,$w17,0 + addvi.h $w18,$w19,31 + addvi.w $w20,$w21,0 + addvi.w $w22,$w23,31 + addvi.d $w24,$w25,0 + addvi.d $w26,$w27,31 + subv.b $w28,$w29,$w30 + subv.h $w31,$w0,$w1 + subv.w $w2,$w3,$w4 + subv.d $w5,$w6,$w7 + subvi.b $w8,$w9,0 + subvi.b $w10,$w11,31 + subvi.h $w12,$w13,0 + subvi.h $w14,$w15,31 + subvi.w $w16,$w17,0 + subvi.w $w18,$w19,31 + subvi.d $w20,$w21,0 + subvi.d $w22,$w23,31 + max_s.b $w24,$w25,$w26 + max_s.h $w27,$w28,$w29 + max_s.w $w30,$w31,$w0 + max_s.d $w1,$w2,$w3 + maxi_s.b $w4,$w5,-16 + maxi_s.b $w6,$w7,15 + maxi_s.h $w8,$w9,-16 + maxi_s.h $w10,$w11,15 + maxi_s.w $w12,$w13,-16 + maxi_s.w $w14,$w15,15 + maxi_s.d $w16,$w17,-16 + maxi_s.d $w18,$w19,15 + max_u.b $w20,$w21,$w22 + max_u.h $w23,$w24,$w25 + max_u.w $w26,$w27,$w28 + max_u.d $w29,$w30,$w31 + maxi_u.b $w0,$w1,0 + maxi_u.b $w2,$w3,31 + maxi_u.h $w4,$w5,0 + maxi_u.h $w6,$w7,31 + maxi_u.w $w8,$w9,0 + maxi_u.w $w10,$w11,31 + maxi_u.d $w12,$w13,0 + maxi_u.d $w14,$w15,31 + min_s.b $w16,$w17,$w18 + min_s.h $w19,$w20,$w21 + min_s.w $w22,$w23,$w24 + min_s.d $w25,$w26,$w27 + mini_s.b $w28,$w29,-16 + mini_s.b $w30,$w31,15 + mini_s.h $w0,$w1,-16 + mini_s.h $w2,$w3,15 + mini_s.w $w4,$w5,-16 + mini_s.w $w6,$w7,15 + mini_s.d $w8,$w9,-16 + mini_s.d $w10,$w11,15 + min_u.b $w12,$w13,$w14 + min_u.h $w15,$w16,$w17 + min_u.w $w18,$w19,$w20 + min_u.d $w21,$w22,$w23 + mini_u.b $w24,$w25,0 + mini_u.b $w26,$w27,31 + mini_u.h $w28,$w29,0 + mini_u.h $w30,$w31,31 + mini_u.w $w0,$w1,0 + mini_u.w $w2,$w3,31 + mini_u.d $w4,$w5,0 + mini_u.d $w6,$w7,31 + max_a.b $w8,$w9,$w10 + max_a.h $w11,$w12,$w13 + max_a.w $w14,$w15,$w16 + max_a.d $w17,$w18,$w19 + min_a.b $w20,$w21,$w22 + min_a.h $w23,$w24,$w25 + min_a.w $w26,$w27,$w28 + min_a.d $w29,$w30,$w31 + ceq.b $w0,$w1,$w2 + ceq.h $w3,$w4,$w5 + ceq.w $w6,$w7,$w8 + ceq.d $w9,$w10,$w11 + ceqi.b $w12,$w13,-16 + ceqi.b $w14,$w15,15 + ceqi.h $w16,$w17,-16 + ceqi.h $w18,$w19,15 + ceqi.w $w20,$w21,-16 + ceqi.w $w22,$w23,15 + ceqi.d $w24,$w25,-16 + ceqi.d $w26,$w27,15 + clt_s.b $w28,$w29,$w30 + clt_s.h $w31,$w0,$w1 + clt_s.w $w2,$w3,$w4 + clt_s.d $w5,$w6,$w7 + clti_s.b $w8,$w9,-16 + clti_s.b $w10,$w11,15 + clti_s.h $w12,$w13,-16 + clti_s.h $w14,$w15,15 + clti_s.w $w16,$w17,-16 + clti_s.w $w18,$w19,15 + clti_s.d $w20,$w21,-16 + clti_s.d $w22,$w23,15 + clt_u.b $w24,$w25,$w26 + clt_u.h $w27,$w28,$w29 + clt_u.w $w30,$w31,$w0 + clt_u.d $w1,$w2,$w3 + clti_u.b $w4,$w5,0 + clti_u.b $w6,$w7,31 + clti_u.h $w8,$w9,0 + clti_u.h $w10,$w11,31 + clti_u.w $w12,$w13,0 + clti_u.w $w14,$w15,31 + clti_u.d $w16,$w17,0 + clti_u.d $w18,$w19,31 + cle_s.b $w20,$w21,$w22 + cle_s.h $w23,$w24,$w25 + cle_s.w $w26,$w27,$w28 + cle_s.d $w29,$w30,$w31 + clei_s.b $w0,$w1,-16 + clei_s.b $w2,$w3,15 + clei_s.h $w4,$w5,-16 + clei_s.h $w6,$w7,15 + clei_s.w $w8,$w9,-16 + clei_s.w $w10,$w11,15 + clei_s.d $w12,$w13,-16 + clei_s.d $w14,$w15,15 + cle_u.b $w16,$w17,$w18 + cle_u.h $w19,$w20,$w21 + cle_u.w $w22,$w23,$w24 + cle_u.d $w25,$w26,$w27 + clei_u.b $w28,$w29,0 + clei_u.b $w30,$w31,31 + clei_u.h $w0,$w1,0 + clei_u.h $w2,$w3,31 + clei_u.w $w4,$w5,0 + clei_u.w $w6,$w7,31 + clei_u.d $w8,$w9,0 + clei_u.d $w10,$w11,31 + ld.b $w12,-512($13) + ld.b $w14,511($15) + ld.h $w16,-1024($17) + ld.h $w18,1022($19) + ld.w $w20,-2048($21) + ld.w $w22,2044($23) + ld.d $w24,-4096($25) + ld.d $w26,4088($27) + st.b $w28,-512($29) + st.b $w30,511($31) + st.h $w0,-1024($1) + st.h $w2,1022($3) + st.w $w4,-2048($5) + st.w $w6,2044($7) + st.d $w8,-4096($9) + st.d $w10,4088($11) + sat_s.b $w12,$w13,0 + sat_s.b $w14,$w15,7 + sat_s.h $w16,$w17,0 + sat_s.h $w18,$w19,15 + sat_s.w $w20,$w21,0 + sat_s.w $w22,$w23,31 + sat_s.d $w24,$w25,0 + sat_s.d $w26,$w27,63 + sat_u.b $w28,$w29,0 + sat_u.b $w30,$w31,7 + sat_u.h $w0,$w1,0 + sat_u.h $w2,$w3,15 + sat_u.w $w4,$w5,0 + sat_u.w $w6,$w7,31 + sat_u.d $w8,$w9,0 + sat_u.d $w10,$w11,63 + add_a.b $w12,$w13,$w14 + add_a.h $w15,$w16,$w17 + add_a.w $w18,$w19,$w20 + add_a.d $w21,$w22,$w23 + adds_a.b $w24,$w25,$w26 + adds_a.h $w27,$w28,$w29 + adds_a.w $w30,$w31,$w0 + adds_a.d $w1,$w2,$w3 + adds_s.b $w4,$w5,$w6 + adds_s.h $w7,$w8,$w9 + adds_s.w $w10,$w11,$w12 + adds_s.d $w13,$w14,$w15 + adds_u.b $w16,$w17,$w18 + adds_u.h $w19,$w20,$w21 + adds_u.w $w22,$w23,$w24 + adds_u.d $w25,$w26,$w27 + ave_s.b $w28,$w29,$w30 + ave_s.h $w31,$w0,$w1 + ave_s.w $w2,$w3,$w4 + ave_s.d $w5,$w6,$w7 + ave_u.b $w8,$w9,$w10 + ave_u.h $w11,$w12,$w13 + ave_u.w $w14,$w15,$w16 + ave_u.d $w17,$w18,$w19 + aver_s.b $w20,$w21,$w22 + aver_s.h $w23,$w24,$w25 + aver_s.w $w26,$w27,$w28 + aver_s.d $w29,$w30,$w31 + aver_u.b $w0,$w1,$w2 + aver_u.h $w3,$w4,$w5 + aver_u.w $w6,$w7,$w8 + aver_u.d $w9,$w10,$w11 + subs_s.b $w12,$w13,$w14 + subs_s.h $w15,$w16,$w17 + subs_s.w $w18,$w19,$w20 + subs_s.d $w21,$w22,$w23 + subs_u.b $w24,$w25,$w26 + subs_u.h $w27,$w28,$w29 + subs_u.w $w30,$w31,$w0 + subs_u.d $w1,$w2,$w3 + subsus_u.b $w4,$w5,$w6 + subsus_u.h $w7,$w8,$w9 + subsus_u.w $w10,$w11,$w12 + subsus_u.d $w13,$w14,$w15 + subsuu_s.b $w16,$w17,$w18 + subsuu_s.h $w19,$w20,$w21 + subsuu_s.w $w22,$w23,$w24 + subsuu_s.d $w25,$w26,$w27 + asub_s.b $w28,$w29,$w30 + asub_s.h $w31,$w0,$w1 + asub_s.w $w2,$w3,$w4 + asub_s.d $w5,$w6,$w7 + asub_u.b $w8,$w9,$w10 + asub_u.h $w11,$w12,$w13 + asub_u.w $w14,$w15,$w16 + asub_u.d $w17,$w18,$w19 + mulv.b $w20,$w21,$w22 + mulv.h $w23,$w24,$w25 + mulv.w $w26,$w27,$w28 + mulv.d $w29,$w30,$w31 + maddv.b $w0,$w1,$w2 + maddv.h $w3,$w4,$w5 + maddv.w $w6,$w7,$w8 + maddv.d $w9,$w10,$w11 + msubv.b $w12,$w13,$w14 + msubv.h $w15,$w16,$w17 + msubv.w $w18,$w19,$w20 + msubv.d $w21,$w22,$w23 + div_s.b $w24,$w25,$w26 + div_s.h $w27,$w28,$w29 + div_s.w $w30,$w31,$w0 + div_s.d $w1,$w2,$w3 + div_u.b $w4,$w5,$w6 + div_u.h $w7,$w8,$w9 + div_u.w $w10,$w11,$w12 + div_u.d $w13,$w14,$w15 + mod_s.b $w16,$w17,$w18 + mod_s.h $w19,$w20,$w21 + mod_s.w $w22,$w23,$w24 + mod_s.d $w25,$w26,$w27 + mod_u.b $w28,$w29,$w30 + mod_u.h $w31,$w0,$w1 + mod_u.w $w2,$w3,$w4 + mod_u.d $w5,$w6,$w7 + dotp_s.h $w8,$w9,$w10 + dotp_s.w $w11,$w12,$w13 + dotp_s.d $w14,$w15,$w16 + dotp_u.h $w17,$w18,$w19 + dotp_u.w $w20,$w21,$w22 + dotp_u.d $w23,$w24,$w25 + dpadd_s.h $w26,$w27,$w28 + dpadd_s.w $w29,$w30,$w31 + dpadd_s.d $w0,$w1,$w2 + dpadd_u.h $w3,$w4,$w5 + dpadd_u.w $w6,$w7,$w8 + dpadd_u.d $w9,$w10,$w11 + dpsub_s.h $w12,$w13,$w14 + dpsub_s.w $w15,$w16,$w17 + dpsub_s.d $w18,$w19,$w20 + dpsub_u.h $w21,$w22,$w23 + dpsub_u.w $w24,$w25,$w26 + dpsub_u.d $w27,$w28,$w29 + sld.b $w30,$w31[$0] + sld.h $w1,$w2[$3] + sld.w $w4,$w5[$6] + sld.d $w7,$w8[$9] + sldi.b $w10,$w11[0] + sldi.b $w12,$w13[15] + sldi.h $w14,$w15[0] + sldi.h $w16,$w17[7] + sldi.w $w18,$w19[0] + sldi.w $w20,$w21[3] + sldi.d $w22,$w23[0] + sldi.d $w24,$w25[1] + splat.b $w26,$w27[$28] + splat.h $w29,$w30[$31] + splat.w $w0,$w1[$2] + splat.d $w3,$w4[$5] + splati.b $w6,$w7[0] + splati.b $w8,$w9[15] + splati.h $w10,$w11[0] + splati.h $w12,$w13[7] + splati.w $w14,$w15[0] + splati.w $w16,$w17[3] + splati.d $w18,$w19[0] + splati.d $w20,$w21[1] + pckev.b $w22,$w23,$w24 + pckev.h $w25,$w26,$w27 + pckev.w $w28,$w29,$w30 + pckev.d $w31,$w0,$w1 + pckod.b $w2,$w3,$w4 + pckod.h $w5,$w6,$w7 + pckod.w $w8,$w9,$w10 + pckod.d $w11,$w12,$w13 + ilvl.b $w14,$w15,$w16 + ilvl.h $w17,$w18,$w19 + ilvl.w $w20,$w21,$w22 + ilvl.d $w23,$w24,$w25 + ilvr.b $w26,$w27,$w28 + ilvr.h $w29,$w30,$w31 + ilvr.w $w0,$w1,$w2 + ilvr.d $w3,$w4,$w5 + ilvev.b $w6,$w7,$w8 + ilvev.h $w9,$w10,$w11 + ilvev.w $w12,$w13,$w14 + ilvev.d $w15,$w16,$w17 + ilvod.b $w18,$w19,$w20 + ilvod.h $w21,$w22,$w23 + ilvod.w $w24,$w25,$w26 + ilvod.d $w27,$w28,$w29 + vshf.b $w30,$w31,$w0 + vshf.h $w1,$w2,$w3 + vshf.w $w4,$w5,$w6 + vshf.d $w7,$w8,$w9 + srar.b $w10,$w11,$w12 + srar.h $w13,$w14,$w15 + srar.w $w16,$w17,$w18 + srar.d $w19,$w20,$w21 + srari.b $w22,$w23,0 + srari.b $w24,$w25,7 + srari.h $w26,$w27,0 + srari.h $w28,$w29,15 + srari.w $w30,$w31,0 + srari.w $w0,$w1,31 + srari.d $w2,$w3,0 + srari.d $w4,$w5,63 + srlr.b $w6,$w7,$w8 + srlr.h $w9,$w10,$w11 + srlr.w $w12,$w13,$w14 + srlr.d $w15,$w16,$w17 + srlri.b $w18,$w19,0 + srlri.b $w20,$w21,7 + srlri.h $w22,$w23,0 + srlri.h $w24,$w25,15 + srlri.w $w26,$w27,0 + srlri.w $w28,$w29,31 + srlri.d $w30,$w31,0 + srlri.d $w0,$w1,63 + hadd_s.h $w2,$w3,$w4 + hadd_s.w $w5,$w6,$w7 + hadd_s.d $w8,$w9,$w10 + hadd_u.h $w11,$w12,$w13 + hadd_u.w $w14,$w15,$w16 + hadd_u.d $w17,$w18,$w19 + hsub_s.h $w20,$w21,$w22 + hsub_s.w $w23,$w24,$w25 + hsub_s.d $w26,$w27,$w28 + hsub_u.h $w29,$w30,$w31 + hsub_u.w $w0,$w1,$w2 + hsub_u.d $w3,$w4,$w5 + and.v $w6,$w7,$w8 + andi.b $w9,$w10,0 + andi.b $w11,$w12,255 + or.v $w13,$w14,$w15 + ori.b $w16,$w17,0 + ori.b $w18,$w19,255 + nor.v $w20,$w21,$w22 + nori.b $w23,$w24,0 + nori.b $w25,$w26,255 + xor.v $w27,$w28,$w29 + xori.b $w30,$w31,0 + xori.b $w0,$w1,255 + bmnz.v $w2,$w3,$w4 + bmnzi.b $w5,$w6,0 + bmnzi.b $w7,$w8,255 + bmz.v $w9,$w10,$w11 + bmzi.b $w12,$w13,0 + bmzi.b $w14,$w15,255 + bsel.v $w16,$w17,$w18 + bseli.b $w19,$w20,0 + bseli.b $w21,$w22,255 + shf.b $w23,$w24,0 + shf.b $w25,$w26,255 + shf.h $w27,$w28,0 + shf.h $w29,$w30,255 + shf.w $w31,$w0,0 + shf.w $w1,$w2,255 +1: + bnz.v $w3,. + 4 + (-32768 << insn_log2) + nop + bnz.v $w4,. + 4 + (32767 << insn_log2) + nop + bnz.v $w5,1b + nop + bnz.v $w6,external_label + nop +1: + bz.v $w7,. + 4 + (-32768 << insn_log2) + nop + bz.v $w8,. + 4 + (32767 << insn_log2) + nop + bz.v $w9,1b + nop + bz.v $w10,external_label + nop + fill.b $w11,$12 + fill.h $w13,$14 + fill.w $w15,$16 + pcnt.b $w19,$w20 + pcnt.h $w21,$w22 + pcnt.w $w23,$w24 + pcnt.d $w25,$w26 + nloc.b $w27,$w28 + nloc.h $w29,$w30 + nloc.w $w31,$w0 + nloc.d $w1,$w2 + nlzc.b $w3,$w4 + nlzc.h $w5,$w6 + nlzc.w $w7,$w8 + nlzc.d $w9,$w10 + copy_s.b $11,$w12[0] + copy_s.b $13,$w14[15] + copy_s.h $15,$w16[0] + copy_s.h $17,$w18[7] + copy_s.w $19,$w20[0] + copy_s.w $21,$w22[3] + copy_u.b $27,$w28[0] + copy_u.b $29,$w30[15] + copy_u.h $31,$w0[0] + copy_u.h $1,$w2[7] + copy_u.w $3,$w4[0] + copy_u.w $5,$w6[3] + insert.b $w11[0],$12 + insert.b $w13[15],$14 + insert.h $w15[0],$16 + insert.h $w17[7],$18 + insert.w $w19[0],$20 + insert.w $w21[3],$22 + insve.b $w27[0],$w28[0] + insve.b $w29[15],$w30[0] + insve.h $w31[0],$w0[0] + insve.h $w1[7],$w2[0] + insve.w $w3[0],$w4[0] + insve.w $w5[3],$w6[0] + insve.d $w7[0],$w8[0] + insve.d $w9[1],$w10[0] +1: + bnz.b $w11,. + 4 + (-32768 << insn_log2) + nop + bnz.b $w12,. + 4 + (32767 << insn_log2) + nop + bnz.b $w13,1b + nop + bnz.b $w14,external_label + nop +1: + bnz.h $w15,. + 4 + (-32768 << insn_log2) + nop + bnz.h $w16,. + 4 + (32767 << insn_log2) + nop + bnz.h $w17,1b + nop + bnz.h $w18,external_label + nop +1: + bnz.w $w19,. + 4 + (-32768 << insn_log2) + nop + bnz.w $w20,. + 4 + (32767 << insn_log2) + nop + bnz.w $w21,1b + nop + bnz.w $w22,external_label + nop +1: + bnz.d $w23,. + 4 + (-32768 << insn_log2) + nop + bnz.d $w24,. + 4 + (32767 << insn_log2) + nop + bnz.d $w25,1b + nop + bnz.d $w26,external_label + nop +1: + bz.b $w27,. + 4 + (-32768 << insn_log2) + nop + bz.b $w28,. + 4 + (32767 << insn_log2) + nop + bz.b $w29,1b + nop + bz.b $w30,external_label + nop +1: + bz.h $w31,. + 4 + (-32768 << insn_log2) + nop + bz.h $w0,. + 4 + (32767 << insn_log2) + nop + bz.h $w1,1b + nop + bz.h $w2,external_label + nop +1: + bz.w $w3,. + 4 + (-32768 << insn_log2) + nop + bz.w $w4,. + 4 + (32767 << insn_log2) + nop + bz.w $w5,1b + nop + bz.w $w6,external_label + nop +1: + bz.d $w7,. + 4 + (-32768 << insn_log2) + nop + bz.d $w8,. + 4 + (32767 << insn_log2) + nop + bz.d $w9,1b + nop + bz.d $w10,external_label + nop + ldi.b $w11,-512 + ldi.b $w12,511 + ldi.h $w13,-512 + ldi.h $w14,511 + ldi.w $w15,-512 + ldi.w $w16,511 + ldi.d $w17,-512 + ldi.d $w18,511 + fcaf.w $w19,$w20,$w21 + fcaf.d $w22,$w23,$w24 + fcun.w $w25,$w26,$w27 + fcun.d $w28,$w29,$w30 + fceq.w $w31,$w0,$w1 + fceq.d $w2,$w3,$w4 + fcueq.w $w5,$w6,$w7 + fcueq.d $w8,$w9,$w10 + fclt.w $w11,$w12,$w13 + fclt.d $w14,$w15,$w16 + fcult.w $w17,$w18,$w19 + fcult.d $w20,$w21,$w22 + fcle.w $w23,$w24,$w25 + fcle.d $w26,$w27,$w28 + fcule.w $w29,$w30,$w31 + fcule.d $w0,$w1,$w2 + fsaf.w $w3,$w4,$w5 + fsaf.d $w6,$w7,$w8 + fsun.w $w9,$w10,$w11 + fsun.d $w12,$w13,$w14 + fseq.w $w15,$w16,$w17 + fseq.d $w18,$w19,$w20 + fsueq.w $w21,$w22,$w23 + fsueq.d $w24,$w25,$w26 + fslt.w $w27,$w28,$w29 + fslt.d $w30,$w31,$w0 + fsult.w $w1,$w2,$w3 + fsult.d $w4,$w5,$w6 + fsle.w $w7,$w8,$w9 + fsle.d $w10,$w11,$w12 + fsule.w $w13,$w14,$w15 + fsule.d $w16,$w17,$w18 + fadd.w $w19,$w20,$w21 + fadd.d $w22,$w23,$w24 + fsub.w $w25,$w26,$w27 + fsub.d $w28,$w29,$w30 + fmul.w $w31,$w0,$w1 + fmul.d $w2,$w3,$w4 + fdiv.w $w5,$w6,$w7 + fdiv.d $w8,$w9,$w10 + fmadd.w $w11,$w12,$w13 + fmadd.d $w14,$w15,$w16 + fmsub.w $w17,$w18,$w19 + fmsub.d $w20,$w21,$w22 + fexp2.w $w23,$w24,$w25 + fexp2.d $w26,$w27,$w28 + fexdo.h $w29,$w30,$w31 + fexdo.w $w0,$w1,$w2 + ftq.h $w3,$w4,$w5 + ftq.w $w6,$w7,$w8 + fmin.w $w9,$w10,$w11 + fmin.d $w12,$w13,$w14 + fmin_a.w $w15,$w16,$w17 + fmin_a.d $w18,$w19,$w20 + fmax.w $w21,$w22,$w23 + fmax.d $w24,$w25,$w26 + fmax_a.w $w27,$w28,$w29 + fmax_a.d $w30,$w31,$w0 + fcor.w $w1,$w2,$w3 + fcor.d $w4,$w5,$w6 + fcune.w $w7,$w8,$w9 + fcune.d $w10,$w11,$w12 + fcne.w $w13,$w14,$w15 + fcne.d $w16,$w17,$w18 + mul_q.h $w19,$w20,$w21 + mul_q.w $w22,$w23,$w24 + madd_q.h $w25,$w26,$w27 + madd_q.w $w28,$w29,$w30 + msub_q.h $w31,$w0,$w1 + msub_q.w $w2,$w3,$w4 + fsor.w $w5,$w6,$w7 + fsor.d $w8,$w9,$w10 + fsune.w $w11,$w12,$w13 + fsune.d $w14,$w15,$w16 + fsne.w $w17,$w18,$w19 + fsne.d $w20,$w21,$w22 + mulr_q.h $w23,$w24,$w25 + mulr_q.w $w26,$w27,$w28 + maddr_q.h $w29,$w30,$w31 + maddr_q.w $w0,$w1,$w2 + msubr_q.h $w3,$w4,$w5 + msubr_q.w $w6,$w7,$w8 + fclass.w $w9,$w10 + fclass.d $w11,$w12 + ftrunc_s.w $w13,$w14 + ftrunc_s.d $w15,$w16 + ftrunc_u.w $w17,$w18 + ftrunc_u.d $w19,$w20 + fsqrt.w $w21,$w22 + fsqrt.d $w23,$w24 + frsqrt.w $w25,$w26 + frsqrt.d $w27,$w28 + frcp.w $w29,$w30 + frcp.d $w31,$w0 + frint.w $w1,$w2 + frint.d $w3,$w4 + flog2.w $w5,$w6 + flog2.d $w7,$w8 + fexupl.w $w9,$w10 + fexupl.d $w11,$w12 + fexupr.w $w13,$w14 + fexupr.d $w15,$w16 + ffql.w $w17,$w18 + ffql.d $w19,$w20 + ffqr.w $w21,$w22 + ffqr.d $w23,$w24 + ftint_s.w $w25,$w26 + ftint_s.d $w27,$w28 + ftint_u.w $w29,$w30 + ftint_u.d $w31,$w0 + ffint_s.w $w1,$w2 + ffint_s.d $w3,$w4 + ffint_u.w $w5,$w6 + ffint_u.d $w7,$w8 + ctcmsa $0,$9 + ctcmsa $1,$10 + ctcmsa $2,$11 + ctcmsa $3,$12 + cfcmsa $13,$0 + cfcmsa $14,$1 + cfcmsa $15,$2 + cfcmsa $16,$3 + move.v $w17,$w18 + lsa $19,$20,$21,1 + lsa $22,$23,$24,4 + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 2 + .space 8 diff --git a/binutils-2.24/gas/testsuite/gas/mips/msa64.d b/binutils-2.24/gas/testsuite/gas/mips/msa64.d new file mode 100644 index 0000000..2ade93f --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/msa64.d @@ -0,0 +1,17 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa +#name: MSA64 instructions +#as: -64 -mmsa + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 7b03945e fill\.d \$w17,s2 +[0-9a-f]+ <[^>]*> 78b8c5d9 copy_s\.d s7,\$w24\[0\] +[0-9a-f]+ <[^>]*> 78b9d659 copy_s\.d t9,\$w26\[1\] +[0-9a-f]+ <[^>]*> 78f841d9 copy_u\.d a3,\$w8\[0\] +[0-9a-f]+ <[^>]*> 78f95259 copy_u\.d a5,\$w10\[1\] +[0-9a-f]+ <[^>]*> 7938c5d9 insert\.d \$w23\[0\],t8 +[0-9a-f]+ <[^>]*> 7939d659 insert\.d \$w25\[1\],k0 +[0-9a-f]+ <[^>]*> 035bc815 dlsa t9,k0,k1,0x1 +[0-9a-f]+ <[^>]*> 03bee0d5 dlsa gp,sp,s8,0x4 + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/msa64.s b/binutils-2.24/gas/testsuite/gas/mips/msa64.s new file mode 100644 index 0000000..665220b --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/msa64.s @@ -0,0 +1,15 @@ + .text +test_msa64: + fill.d $w17,$18 + copy_s.d $23,$w24[0] + copy_s.d $25,$w26[1] + copy_u.d $7,$w8[0] + copy_u.d $9,$w10[1] + insert.d $w23[0],$24 + insert.d $w25[1],$26 + dlsa $25,$26,$27,1 + dlsa $28,$29,$30,4 + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 2 + .space 8 diff --git a/binutils-2.24/gas/testsuite/gas/mips/n32-consec.d b/binutils-2.24/gas/testsuite/gas/mips/n32-consec.d index 806857e..cce0cdb 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/n32-consec.d +++ b/binutils-2.24/gas/testsuite/gas/mips/n32-consec.d @@ -12,3 +12,14 @@ Disassembly of section .data: 0: R_MIPS_32 .data\+0x4 Disassembly of section .reginfo: ... + +Disassembly of section .MIPS.abiflags: +.* +.* + ... + +Disassembly of section .gnu.attributes: +.* +.* +.* +.* diff --git a/binutils-2.24/gas/testsuite/gas/mips/nan-2008-1.d b/binutils-2.24/gas/testsuite/gas/mips/nan-2008-1.d index 3649fd2..78556f5 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/nan-2008-1.d +++ b/binutils-2.24/gas/testsuite/gas/mips/nan-2008-1.d @@ -4,3 +4,4 @@ .*:.*file format.*mips.* private flags = [0-9a-f]*[4-7c-f]..: .*[[,]nan2008[],].* +#pass diff --git a/binutils-2.24/gas/testsuite/gas/mips/nan-2008-2.d b/binutils-2.24/gas/testsuite/gas/mips/nan-2008-2.d index e8a07ce..c98455b 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/nan-2008-2.d +++ b/binutils-2.24/gas/testsuite/gas/mips/nan-2008-2.d @@ -5,3 +5,4 @@ .*:.*file format.*mips.* private flags = [0-9a-f]*[4-7c-f]..: .*[[,]nan2008[],].* +#pass diff --git a/binutils-2.24/gas/testsuite/gas/mips/nan-2008-3.d b/binutils-2.24/gas/testsuite/gas/mips/nan-2008-3.d index 7c3c4a3..8f179fb 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/nan-2008-3.d +++ b/binutils-2.24/gas/testsuite/gas/mips/nan-2008-3.d @@ -4,3 +4,4 @@ .*:.*file format.*mips.* private flags = [0-9a-f]*[4-7c-f]..: .*[[,]nan2008[],].* +#pass diff --git a/binutils-2.24/gas/testsuite/gas/mips/nan-2008-4.d b/binutils-2.24/gas/testsuite/gas/mips/nan-2008-4.d index 22ba87f..44d5d22 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/nan-2008-4.d +++ b/binutils-2.24/gas/testsuite/gas/mips/nan-2008-4.d @@ -5,3 +5,4 @@ .*:.*file format.*mips.* private flags = [0-9a-f]*[4-7c-f]..: .*[[,]nan2008[],].* +#pass diff --git a/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-1.d b/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-1.d index 4dcb93c..a2f6d0c 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-1.d +++ b/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-1.d @@ -5,3 +5,17 @@ .*:.*file format.*mips.* #failif private flags = [0-9a-f]*[4-7c-f]..: .*[[]nan2008[]].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-2.d b/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-2.d index 6ad4dce..83c559f 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-2.d +++ b/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-2.d @@ -6,3 +6,17 @@ .*:.*file format.*mips.* #failif private flags = [0-9a-f]*[4-7c-f]..: .*[[]nan2008[]].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-3.d b/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-3.d index 649f0ee..f19d1aa 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-3.d +++ b/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-3.d @@ -5,3 +5,17 @@ .*:.*file format.*mips.* #failif private flags = [0-9a-f]*[4-7c-f]..: .*[[]nan2008[]].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-4.d b/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-4.d index 3dc00cb..c70d1d1 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-4.d +++ b/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-4.d @@ -6,3 +6,17 @@ .*:.*file format.*mips.* #failif private flags = [0-9a-f]*[4-7c-f]..: .*[[]nan2008[]].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-5.d b/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-5.d index db3a954..d3b2480 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-5.d +++ b/binutils-2.24/gas/testsuite/gas/mips/nan-legacy-5.d @@ -5,3 +5,17 @@ .*:.*file format.*mips.* #failif private flags = [0-9a-f]*[4-7c-f]..: .*[[]nan2008[]].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/pcrel-1.d b/binutils-2.24/gas/testsuite/gas/mips/pcrel-1.d new file mode 100644 index 0000000..5c9f655 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/pcrel-1.d @@ -0,0 +1,14 @@ +#objdump: -dr +#name: Locally-resolvable PC-relative code references + +.*: file format .* + +Disassembly of section .text: + +00000000 <func>: + 0: 3c040001 lui a0,0x1 + 4: 2484800c addiu a0,a0,-32756 + ... + +00008010 <foo>: +#pass diff --git a/binutils-2.24/gas/testsuite/gas/mips/pcrel-1.s b/binutils-2.24/gas/testsuite/gas/mips/pcrel-1.s new file mode 100644 index 0000000..ba93a5b --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/pcrel-1.s @@ -0,0 +1,13 @@ + .text + .ent func +func: + lui $4,%hi(foo-.) + addiu $4,%lo(foo-.) + .end func + + .space 0x8008 + + .ent foo +foo: + nop + .end foo diff --git a/binutils-2.24/gas/testsuite/gas/mips/pcrel-2.d b/binutils-2.24/gas/testsuite/gas/mips/pcrel-2.d new file mode 100644 index 0000000..e1692e0 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/pcrel-2.d @@ -0,0 +1,8 @@ +#objdump: -s +#name: Locally-resolvable PC-relative data references +#as: -EB + +#... +Contents of section \.data: + 0000 ff0f000e 0000000c 00000000 00000008 .* +#pass diff --git a/binutils-2.24/gas/testsuite/gas/mips/pcrel-2.s b/binutils-2.24/gas/testsuite/gas/mips/pcrel-2.s new file mode 100644 index 0000000..781141e --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/pcrel-2.s @@ -0,0 +1,7 @@ + .data + .byte 0xff + .byte frob-. + .half frob-. + .word frob-. + .quad frob-. +frob: diff --git a/binutils-2.24/gas/testsuite/gas/mips/pcrel-3.l b/binutils-2.24/gas/testsuite/gas/mips/pcrel-3.l new file mode 100644 index 0000000..f2bfc51 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/pcrel-3.l @@ -0,0 +1,7 @@ +.*: Assembler messages: +.*:4: Error: PC-relative reference to a different section +.*:5: Error: PC-relative reference to a different section +.*:6: Error: PC-relative reference to a different section +.*:9: Error: PC-relative reference to a different section +.*:10: Error: PC-relative reference to a different section +.*:11: Error: PC-relative reference to a different section diff --git a/binutils-2.24/gas/testsuite/gas/mips/pcrel-3.s b/binutils-2.24/gas/testsuite/gas/mips/pcrel-3.s new file mode 100644 index 0000000..6db741c --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/pcrel-3.s @@ -0,0 +1,11 @@ + .text + .ent func +func: + lui $4,%hi(foo-.) + addiu $4,%lo(foo-.) + lw $4,%got(foo-.)($gp) + .end func + + .byte foo-. + .half foo-. + .quad foo-. diff --git a/binutils-2.24/gas/testsuite/gas/mips/pcrel-4-32.d b/binutils-2.24/gas/testsuite/gas/mips/pcrel-4-32.d new file mode 100644 index 0000000..06bc52b --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/pcrel-4-32.d @@ -0,0 +1,18 @@ +#objdump: -sr +#name: Valid cross-section PC-relative references (o32) +#as: -32 -EB +#source: pcrel-4.s + +.*: file format .* + +RELOCATION RECORDS FOR \[\.data\]: +OFFSET TYPE VALUE +00000000 R_MIPS_PC32 foo +00000004 R_MIPS_PC32 foo +00000008 R_MIPS_PC32 foo +0000000c R_MIPS_PC32 foo + +#... +Contents of section \.data: + 0000 00000000 00000004 00000008 fffffff0 ................ +#pass diff --git a/binutils-2.24/gas/testsuite/gas/mips/pcrel-4-64.d b/binutils-2.24/gas/testsuite/gas/mips/pcrel-4-64.d new file mode 100644 index 0000000..931ff96 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/pcrel-4-64.d @@ -0,0 +1,21 @@ +#objdump: -r +#name: Valid cross-section PC-relative references (n64) +#as: -64 -mips3 +#source: pcrel-4.s + +.*: file format .* + +RELOCATION RECORDS FOR \[\.data\]: +OFFSET TYPE VALUE +0+000 R_MIPS_PC32 foo +0+000 R_MIPS_NONE \*ABS\* +0+000 R_MIPS_NONE \*ABS\* +0+004 R_MIPS_PC32 foo\+0x0+004 +0+004 R_MIPS_NONE \*ABS\*\+0x0+004 +0+004 R_MIPS_NONE \*ABS\*\+0x0+004 +0+008 R_MIPS_PC32 foo\+0x0+008 +0+008 R_MIPS_NONE \*ABS\*\+0x0+008 +0+008 R_MIPS_NONE \*ABS\*\+0x0+008 +0+00c R_MIPS_PC32 foo-0x0+010 +0+00c R_MIPS_NONE \*ABS\*-0x0+010 +0+00c R_MIPS_NONE \*ABS\*-0x0+010 diff --git a/binutils-2.24/gas/testsuite/gas/mips/pcrel-4-n32.d b/binutils-2.24/gas/testsuite/gas/mips/pcrel-4-n32.d new file mode 100644 index 0000000..56ec6ef --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/pcrel-4-n32.d @@ -0,0 +1,13 @@ +#objdump: -r +#name: Valid cross-section PC-relative references (n32) +#as: -n32 -mips3 +#source: pcrel-4.s + +.*: file format .* + +RELOCATION RECORDS FOR \[\.data\]: +OFFSET TYPE VALUE +00000000 R_MIPS_PC32 foo +00000004 R_MIPS_PC32 foo\+0x00000004 +00000008 R_MIPS_PC32 foo\+0x00000008 +0000000c R_MIPS_PC32 foo-0x00000010 diff --git a/binutils-2.24/gas/testsuite/gas/mips/pcrel-4.s b/binutils-2.24/gas/testsuite/gas/mips/pcrel-4.s new file mode 100644 index 0000000..8f332dc --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/pcrel-4.s @@ -0,0 +1,6 @@ + .data + .word foo-. + .word foo-(.-4) + .word foo+8-. + .word foo-.-16 + diff --git a/binutils-2.24/gas/testsuite/gas/mips/r5.d b/binutils-2.24/gas/testsuite/gas/mips/r5.d new file mode 100644 index 0000000..d1073fe --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/r5.d @@ -0,0 +1,8 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: Test MIPS32r5 instructions + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 42000058 eretnc + ... diff --git a/binutils-2.24/gas/testsuite/gas/mips/r5.s b/binutils-2.24/gas/testsuite/gas/mips/r5.s new file mode 100644 index 0000000..12260d3 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/r5.s @@ -0,0 +1,10 @@ + .text + .set noat + .set noreorder + .set nomacro +test_r5: + eretnc + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 2 + .space 8 diff --git a/binutils-2.24/gas/testsuite/gas/mips/r6-64-removed.l b/binutils-2.24/gas/testsuite/gas/mips/r6-64-removed.l new file mode 100644 index 0000000..7cd1bbb --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/r6-64-removed.l @@ -0,0 +1,14 @@ +.*: Assembler messages: +.*:2: Error: opcode not supported on this processor: .* \(.*\) `daddi \$23,\$24,1023' +.*:3: Error: invalid operands `ddiv \$2,\$4' +.*:4: Error: invalid operands `ddivu \$2,\$4' +.*:5: Error: opcode not supported on this processor: .* \(.*\) `dmult \$2,\$3' +.*:6: Error: opcode not supported on this processor: .* \(.*\) `dmultu \$2,\$3' +.*:7: Error: opcode not supported on this processor: .* \(.*\) `ldl \$2,1\(\$3\)' +.*:8: Error: opcode not supported on this processor: .* \(.*\) `ldr \$2,1\(\$3\)' +.*:9: Error: operand 2 out of range `lld \$3,32768\(\$4\)' +.*:10: Error: operand 2 out of range `lld \$3,-32769\(\$5\)' +.*:11: Error: operand 2 out of range `scd \$5,32768\(\$4\)' +.*:12: Error: operand 2 out of range `scd \$5,-32769\(\$5\)' +.*:13: Error: opcode not supported on this processor: .* \(.*\) `sdl \$2,1\(\$3\)' +.*:14: Error: opcode not supported on this processor: .* \(.*\) `sdr \$2,1\(\$3\)' diff --git a/binutils-2.24/gas/testsuite/gas/mips/r6-64-removed.s b/binutils-2.24/gas/testsuite/gas/mips/r6-64-removed.s new file mode 100644 index 0000000..4011d84 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/r6-64-removed.s @@ -0,0 +1,14 @@ + .set reorder + daddi $23,$24,1023 + ddiv $2, $4 + ddivu $2, $4 + dmult $2,$3 + dmultu $2,$3 + ldl $2, 1($3) + ldr $2, 1($3) + lld $3, 32768($4) + lld $3, -32769($5) + scd $5, 32768($4) + scd $5, -32769($5) + sdl $2, 1($3) + sdr $2, 1($3) diff --git a/binutils-2.24/gas/testsuite/gas/mips/r6-64.d b/binutils-2.24/gas/testsuite/gas/mips/r6-64.d new file mode 100644 index 0000000..a3737e7 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/r6-64.d @@ -0,0 +1,59 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS MIPSR6 64 instructions + +# Check MIPSR6 64 instructions + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 0064109c dmul v0,v1,a0 +0+0004 <[^>]*> 006410dc dmuh v0,v1,a0 +0+0008 <[^>]*> 0064109e ddiv v0,v1,a0 +0+000c <[^>]*> 0064109d dmulu v0,v1,a0 +0+0010 <[^>]*> 006410dd dmuhu v0,v1,a0 +0+0014 <[^>]*> 006410de dmod v0,v1,a0 +0+0018 <[^>]*> 0064109f ddivu v0,v1,a0 +0+001c <[^>]*> 006410df dmodu v0,v1,a0 +0+0020 <[^>]*> 00641015 dlsa v0,v1,a0,0x1 +0+0024 <[^>]*> 006410d5 dlsa v0,v1,a0,0x4 +0+0028 <[^>]*> 00601052 dclz v0,v1 +0+002c <[^>]*> 00601053 dclo v0,v1 +0+0030 <[^>]*> 7c628037 lld v0,-256\(v1\) +0+0034 <[^>]*> 7c627fb7 lld v0,255\(v1\) +0+0038 <[^>]*> 7c628027 scd v0,-256\(v1\) +0+003c <[^>]*> 7c627fa7 scd v0,255\(v1\) +0+0040 <[^>]*> 7c432224 dalign a0,v0,v1,0 +0+0044 <[^>]*> 7c432264 dalign a0,v0,v1,1 +0+0048 <[^>]*> 7c4322a4 dalign a0,v0,v1,2 +0+004c <[^>]*> 7c4322e4 dalign a0,v0,v1,3 +0+0050 <[^>]*> 7c432324 dalign a0,v0,v1,4 +0+0054 <[^>]*> 7c432364 dalign a0,v0,v1,5 +0+0058 <[^>]*> 7c4323a4 dalign a0,v0,v1,6 +0+005c <[^>]*> 7c4323e4 dalign a0,v0,v1,7 +0+0060 <[^>]*> 7c022024 dbitswap a0,v0 +0+0064 <[^>]*> 7443ffff daui v1,v0,0xffff +0+0068 <[^>]*> 0466ffff dahi v1,v1\$pc,0xffff +0+006c <[^>]*> 047effff dati v1,v1\$pc,0xffff +0+0070 <[^>]*> ec900000 lwupc a0,00000070 <[^>]*> +[ ]*70: R_MIPS_PC19_S2 .L1.1 +0+0074 <[^>]*> ec940000 lwupc a0,fff00074 <[^>]*> +[ ]*74: R_MIPS_PC19_S2 L0. +0+0078 <[^>]*> ec93ffff lwupc a0,00100074 <[^>]*> +[ ]*78: R_MIPS_PC19_S2 L0. +0+007c <[^>]*> ec940000 lwupc a0,fff0007c <[^>]*> +0+0080 <[^>]*> ec93ffff lwupc a0,0010007c <[^>]*> +0+0084 <[^>]*> 00000000 nop +0+0088 <[^>]*> ec980000 ldpc a0,00000088 <[^>]*> +[ ]*88: R_MIPS_PC18_S3 .L1.1 +0+008c <[^>]*> 00000000 nop +0+0090 <[^>]*> ec9a0000 ldpc a0,fff00090 <[^>]*> +[ ]*90: R_MIPS_PC18_S3 L0. +0+0094 <[^>]*> 00000000 nop +0+0098 <[^>]*> ec99ffff ldpc a0,00100090 <[^>]*> +[ ]*98: R_MIPS_PC18_S3 L0. +0+009c <[^>]*> 00000000 nop +0+00a0 <[^>]*> ec9a0000 ldpc a0,fff000a0 <[^>]*> +0+00a4 <[^>]*> 00000000 nop +0+00a8 <[^>]*> ec99ffff ldpc a0,001000a0 <[^>]*> +0+00ac <[^>]*> 00000000 nop + \.\.\. diff --git a/binutils-2.24/gas/testsuite/gas/mips/r6-64.s b/binutils-2.24/gas/testsuite/gas/mips/r6-64.s new file mode 100644 index 0000000..275868c --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/r6-64.s @@ -0,0 +1,55 @@ + .text + dmul $2,$3,$4 + dmuh $2,$3,$4 + ddiv $2,$3,$4 + dmulu $2,$3,$4 + dmuhu $2,$3,$4 + dmod $2,$3,$4 + ddivu $2,$3,$4 + dmodu $2,$3,$4 + + dlsa $2,$3,$4,1 + dlsa $2,$3,$4,4 + + dclz $2,$3 + dclo $2,$3 + + lld $2,-256($3) + lld $2,255($3) + scd $2,-256($3) + scd $2,255($3) + + dalign $4, $2, $3, 0 + dalign $4, $2, $3, 1 + dalign $4, $2, $3, 2 + dalign $4, $2, $3, 3 + dalign $4, $2, $3, 4 + dalign $4, $2, $3, 5 + dalign $4, $2, $3, 6 + dalign $4, $2, $3, 7 + + dbitswap $4, $2 + + daui $3, $2, 0xffff + dahi $3, $3, 0xffff + dati $3, $3, 0xffff + + lwupc $4, 1f + lwupc $4, .+(-262144 << 2) + lwupc $4, .+(262143 << 2) + lwu $4, (-262144 << 2)($pc) + lwu $4, (262143 << 2)($pc) + + .align 3 + ldpc $4, 1f + .align 3 + ldpc $4, .+(-131072 << 3) + .align 3 + ldpc $4, .+(131071 << 3) + .align 3 + ld $4, (-131072 << 3)($pc) + .align 3 + ld $4, (131071 << 3)($pc) + .align 3 +1: + nop diff --git a/binutils-2.24/gas/testsuite/gas/mips/r6-removed.l b/binutils-2.24/gas/testsuite/gas/mips/r6-removed.l new file mode 100644 index 0000000..708f0a2 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/r6-removed.l @@ -0,0 +1,208 @@ +.*: Assembler messages: +.*:3: Error: opcode not supported on this processor: .* \(.*\) `abs.ps \$f0,\$f2' +.*:4: Error: opcode not supported on this processor: .* \(.*\) `add.ps \$f0,\$f2,\$f2' +.*:5: Error: opcode not supported on this processor: .* \(.*\) `addi \$15,\$16,256' +.*:6: Error: opcode not supported on this processor: .* \(.*\) `alnv.ps \$f0,\$f2,\$f2,\$3' +.*:7: Error: opcode not supported on this processor: .* \(.*\) `bc0f 1f' +.*:8: Error: opcode not supported on this processor: .* \(.*\) `bc0fl 1f' +.*:9: Error: opcode not supported on this processor: .* \(.*\) `bc0t 1f' +.*:10: Error: opcode not supported on this processor: .* \(.*\) `bc0tl 1f' +.*:11: Error: opcode not supported on this processor: .* \(.*\) `bc1f 1f' +.*:12: Error: opcode not supported on this processor: .* \(.*\) `bc1fl 1f' +.*:13: Error: opcode not supported on this processor: .* \(.*\) `bc1t 1f' +.*:14: Error: opcode not supported on this processor: .* \(.*\) `bc1tl 1f' +.*:15: Error: opcode not supported on this processor: .* \(.*\) `bc2f 1f' +.*:16: Error: opcode not supported on this processor: .* \(.*\) `bc2fl 1f' +.*:17: Error: opcode not supported on this processor: .* \(.*\) `bc2t 1f' +.*:18: Error: opcode not supported on this processor: .* \(.*\) `bc2tl 1f' +.*:19: Error: opcode not supported on this processor: .* \(.*\) `bc3f 1f' +.*:20: Error: opcode not supported on this processor: .* \(.*\) `bc3fl 1f' +.*:21: Error: opcode not supported on this processor: .* \(.*\) `bc3t 1f' +.*:22: Error: opcode not supported on this processor: .* \(.*\) `bc3tl 1f' +.*:23: Error: opcode not supported on this processor: .* \(.*\) `beql \$28,\$29,1f' +.*:24: Error: opcode not supported on this processor: .* \(.*\) `bgezal \$4,1f' +.*:25: Error: opcode not supported on this processor: .* \(.*\) `bgezall \$28,1f' +.*:26: Error: opcode not supported on this processor: .* \(.*\) `bgezl \$28,1f' +.*:27: Error: opcode not supported on this processor: .* \(.*\) `bgtzl \$28,1f' +.*:28: Error: opcode not supported on this processor: .* \(.*\) `blezl \$28,1f' +.*:29: Error: opcode not supported on this processor: .* \(.*\) `bltzal \$4,1f' +.*:30: Error: opcode not supported on this processor: .* \(.*\) `bltzall \$28,1f' +.*:31: Error: opcode not supported on this processor: .* \(.*\) `bltzl \$28,1f' +.*:32: Error: opcode not supported on this processor: .* \(.*\) `bnel \$28,\$29,1f' +.*:33: Error: opcode not supported on this processor: .* \(.*\) `c.f.s \$f0,\$f2' +.*:34: Error: opcode not supported on this processor: .* \(.*\) `c.un.s \$f0,\$f2' +.*:35: Error: opcode not supported on this processor: .* \(.*\) `c.eq.s \$f0,\$f2' +.*:36: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.s \$f0,\$f2' +.*:37: Error: opcode not supported on this processor: .* \(.*\) `c.olt.s \$f0,\$f2' +.*:38: Error: opcode not supported on this processor: .* \(.*\) `c.ult.s \$f0,\$f2' +.*:39: Error: opcode not supported on this processor: .* \(.*\) `c.ole.s \$f0,\$f2' +.*:40: Error: opcode not supported on this processor: .* \(.*\) `c.ule.s \$f0,\$f2' +.*:41: Error: opcode not supported on this processor: .* \(.*\) `c.sf.s \$f0,\$f2' +.*:42: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.s \$f0,\$f2' +.*:43: Error: opcode not supported on this processor: .* \(.*\) `c.seq.s \$f0,\$f2' +.*:44: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.s \$f0,\$f2' +.*:45: Error: opcode not supported on this processor: .* \(.*\) `c.lt.s \$f0,\$f2' +.*:46: Error: opcode not supported on this processor: .* \(.*\) `c.nge.s \$f0,\$f2' +.*:47: Error: opcode not supported on this processor: .* \(.*\) `c.le.s \$f0,\$f2' +.*:48: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.s \$f0,\$f2' +.*:49: Error: opcode not supported on this processor: .* \(.*\) `c.f.ps \$f0,\$f2' +.*:50: Error: opcode not supported on this processor: .* \(.*\) `c.un.ps \$f0,\$f2' +.*:51: Error: opcode not supported on this processor: .* \(.*\) `c.eq.ps \$f0,\$f2' +.*:52: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.ps \$f0,\$f2' +.*:53: Error: opcode not supported on this processor: .* \(.*\) `c.olt.ps \$f0,\$f2' +.*:54: Error: opcode not supported on this processor: .* \(.*\) `c.ult.ps \$f0,\$f2' +.*:55: Error: opcode not supported on this processor: .* \(.*\) `c.ole.ps \$f0,\$f2' +.*:56: Error: opcode not supported on this processor: .* \(.*\) `c.ule.ps \$f0,\$f2' +.*:57: Error: opcode not supported on this processor: .* \(.*\) `c.sf.ps \$f0,\$f2' +.*:58: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.ps \$f0,\$f2' +.*:59: Error: opcode not supported on this processor: .* \(.*\) `c.seq.ps \$f0,\$f2' +.*:60: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.ps \$f0,\$f2' +.*:61: Error: opcode not supported on this processor: .* \(.*\) `c.lt.ps \$f0,\$f2' +.*:62: Error: opcode not supported on this processor: .* \(.*\) `c.nge.ps \$f0,\$f2' +.*:63: Error: opcode not supported on this processor: .* \(.*\) `c.le.ps \$f0,\$f2' +.*:64: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.ps \$f0,\$f2' +.*:65: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$f0,\$f2' +.*:66: Error: opcode not supported on this processor: .* \(.*\) `c.un.d \$f0,\$f2' +.*:67: Error: opcode not supported on this processor: .* \(.*\) `c.eq.d \$f0,\$f2' +.*:68: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.d \$f0,\$f2' +.*:69: Error: opcode not supported on this processor: .* \(.*\) `c.olt.d \$f0,\$f2' +.*:70: Error: opcode not supported on this processor: .* \(.*\) `c.ult.d \$f0,\$f2' +.*:71: Error: opcode not supported on this processor: .* \(.*\) `c.ole.d \$f0,\$f2' +.*:72: Error: opcode not supported on this processor: .* \(.*\) `c.ule.d \$f0,\$f2' +.*:73: Error: opcode not supported on this processor: .* \(.*\) `c.sf.d \$f0,\$f2' +.*:74: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.d \$f0,\$f2' +.*:75: Error: opcode not supported on this processor: .* \(.*\) `c.seq.d \$f0,\$f2' +.*:76: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.d \$f0,\$f2' +.*:77: Error: opcode not supported on this processor: .* \(.*\) `c.lt.d \$f0,\$f2' +.*:78: Error: opcode not supported on this processor: .* \(.*\) `c.nge.d \$f0,\$f2' +.*:79: Error: opcode not supported on this processor: .* \(.*\) `c.le.d \$f0,\$f2' +.*:80: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.d \$f0,\$f2' +.*:81: Error: opcode not supported on this processor: .* \(.*\) `c.f.s \$fcc2,\$f0,\$f2' +.*:82: Error: opcode not supported on this processor: .* \(.*\) `c.un.s \$fcc2,\$f0,\$f2' +.*:83: Error: opcode not supported on this processor: .* \(.*\) `c.eq.s \$fcc2,\$f0,\$f2' +.*:84: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.s \$fcc2,\$f0,\$f2' +.*:85: Error: opcode not supported on this processor: .* \(.*\) `c.olt.s \$fcc2,\$f0,\$f2' +.*:86: Error: opcode not supported on this processor: .* \(.*\) `c.ult.s \$fcc2,\$f0,\$f2' +.*:87: Error: opcode not supported on this processor: .* \(.*\) `c.ole.s \$fcc2,\$f0,\$f2' +.*:88: Error: opcode not supported on this processor: .* \(.*\) `c.ule.s \$fcc2,\$f0,\$f2' +.*:89: Error: opcode not supported on this processor: .* \(.*\) `c.sf.s \$fcc2,\$f0,\$f2' +.*:90: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.s \$fcc2,\$f0,\$f2' +.*:91: Error: opcode not supported on this processor: .* \(.*\) `c.seq.s \$fcc2,\$f0,\$f2' +.*:92: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.s \$fcc2,\$f0,\$f2' +.*:93: Error: opcode not supported on this processor: .* \(.*\) `c.lt.s \$fcc2,\$f0,\$f2' +.*:94: Error: opcode not supported on this processor: .* \(.*\) `c.nge.s \$fcc2,\$f0,\$f2' +.*:95: Error: opcode not supported on this processor: .* \(.*\) `c.le.s \$fcc2,\$f0,\$f2' +.*:96: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.s \$fcc2,\$f0,\$f2' +.*:97: Error: opcode not supported on this processor: .* \(.*\) `c.f.ps \$fcc2,\$f0,\$f2' +.*:98: Error: opcode not supported on this processor: .* \(.*\) `c.un.ps \$fcc2,\$f0,\$f2' +.*:99: Error: opcode not supported on this processor: .* \(.*\) `c.eq.ps \$fcc2,\$f0,\$f2' +.*:100: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.ps \$fcc2,\$f0,\$f2' +.*:101: Error: opcode not supported on this processor: .* \(.*\) `c.olt.ps \$fcc2,\$f0,\$f2' +.*:102: Error: opcode not supported on this processor: .* \(.*\) `c.ult.ps \$fcc2,\$f0,\$f2' +.*:103: Error: opcode not supported on this processor: .* \(.*\) `c.ole.ps \$fcc2,\$f0,\$f2' +.*:104: Error: opcode not supported on this processor: .* \(.*\) `c.ule.ps \$fcc2,\$f0,\$f2' +.*:105: Error: opcode not supported on this processor: .* \(.*\) `c.sf.ps \$fcc2,\$f0,\$f2' +.*:106: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.ps \$fcc2,\$f0,\$f2' +.*:107: Error: opcode not supported on this processor: .* \(.*\) `c.seq.ps \$fcc2,\$f0,\$f2' +.*:108: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.ps \$fcc2,\$f0,\$f2' +.*:109: Error: opcode not supported on this processor: .* \(.*\) `c.lt.ps \$fcc2,\$f0,\$f2' +.*:110: Error: opcode not supported on this processor: .* \(.*\) `c.nge.ps \$fcc2,\$f0,\$f2' +.*:111: Error: opcode not supported on this processor: .* \(.*\) `c.le.ps \$fcc2,\$f0,\$f2' +.*:112: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.ps \$fcc2,\$f0,\$f2' +.*:113: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$fcc2,\$f0,\$f2' +.*:114: Error: opcode not supported on this processor: .* \(.*\) `c.un.d \$fcc2,\$f0,\$f2' +.*:115: Error: opcode not supported on this processor: .* \(.*\) `c.eq.d \$fcc2,\$f0,\$f2' +.*:116: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.d \$fcc2,\$f0,\$f2' +.*:117: Error: opcode not supported on this processor: .* \(.*\) `c.olt.d \$fcc2,\$f0,\$f2' +.*:118: Error: opcode not supported on this processor: .* \(.*\) `c.ult.d \$fcc2,\$f0,\$f2' +.*:119: Error: opcode not supported on this processor: .* \(.*\) `c.ole.d \$fcc2,\$f0,\$f2' +.*:120: Error: opcode not supported on this processor: .* \(.*\) `c.ule.d \$fcc2,\$f0,\$f2' +.*:121: Error: opcode not supported on this processor: .* \(.*\) `c.sf.d \$fcc2,\$f0,\$f2' +.*:122: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.d \$fcc2,\$f0,\$f2' +.*:123: Error: opcode not supported on this processor: .* \(.*\) `c.seq.d \$fcc2,\$f0,\$f2' +.*:124: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.d \$fcc2,\$f0,\$f2' +.*:125: Error: opcode not supported on this processor: .* \(.*\) `c.lt.d \$fcc2,\$f0,\$f2' +.*:126: Error: opcode not supported on this processor: .* \(.*\) `c.nge.d \$fcc2,\$f0,\$f2' +.*:127: Error: opcode not supported on this processor: .* \(.*\) `c.le.d \$fcc2,\$f0,\$f2' +.*:128: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.d \$fcc2,\$f0,\$f2' +.*:129: Error: operand 2 out of range `cache 5,32768\(\$4\)' +.*:130: Error: operand 2 out of range `cache 5,-32769\(\$5\)' +.*:131: Error: opcode not supported on this processor: .* \(.*\) `cvt.ps.s \$f2,\$f3,\$f4' +.*:132: Error: opcode not supported on this processor: .* \(.*\) `jalx 1f' +.*:133: Error: opcode not supported on this processor: .* \(.*\) `ldxc1 \$f0,\$0\(\$2\)' +.*:134: Error: operand 2 out of range `ll \$3,32768\(\$4\)' +.*:135: Error: operand 2 out of range `ll \$3,-32769\(\$5\)' +.*:136: Error: opcode not supported on this processor: .* \(.*\) `luxc1 \$f0,\$0\(\$2\)' +.*:137: Error: opcode not supported on this processor: .* \(.*\) `lwl \$2,1\(\$3\)' +.*:138: Error: opcode not supported on this processor: .* \(.*\) `lwle \$4,0\(\$6\)' +.*:139: Error: opcode not supported on this processor: .* \(.*\) `lwr \$2,1\(\$3\)' +.*:140: Error: opcode not supported on this processor: .* \(.*\) `lwre \$4,0\(\$6\)' +.*:141: Error: opcode not supported on this processor: .* \(.*\) `lwxc1 \$f0,\$0\(\$2\)' +.*:142: Error: opcode not supported on this processor: .* \(.*\) `madd \$2,\$3' +.*:143: Error: opcode not supported on this processor: .* \(.*\) `maddu \$2,\$3' +.*:144: Error: opcode not supported on this processor: .* \(.*\) `madd.s \$f5,\$f6,\$f7,\$f8' +.*:145: Error: opcode not supported on this processor: .* \(.*\) `madd.d \$f6,\$f8,\$f10,\$f12' +.*:146: Error: opcode not supported on this processor: .* \(.*\) `madd.ps \$f6,\$f8,\$f10,\$f12' +.*:147: Error: opcode not supported on this processor: .* \(.*\) `mfhi \$2' +.*:148: Error: opcode not supported on this processor: .* \(.*\) `mflo \$2' +.*:149: Error: opcode not supported on this processor: .* \(.*\) `mov.ps \$f10,\$f20' +.*:150: Error: opcode not supported on this processor: .* \(.*\) `movf \$8,\$9,\$fcc0' +.*:151: Error: opcode not supported on this processor: .* \(.*\) `movf.s \$f8,\$f9,\$fcc0' +.*:152: Error: opcode not supported on this processor: .* \(.*\) `movf.d \$f8,\$f10,\$fcc0' +.*:153: Error: opcode not supported on this processor: .* \(.*\) `movf.ps \$f8,\$f10,\$fcc0' +.*:154: Error: opcode not supported on this processor: .* \(.*\) `movn \$2,\$3,\$4' +.*:155: Error: opcode not supported on this processor: .* \(.*\) `movn.s \$f0,\$f2,\$10' +.*:156: Error: opcode not supported on this processor: .* \(.*\) `movn.d \$f0,\$f2,\$10' +.*:157: Error: opcode not supported on this processor: .* \(.*\) `movn.ps \$f0,\$f2,\$10' +.*:158: Error: opcode not supported on this processor: .* \(.*\) `movt \$10,\$11,\$fcc2' +.*:159: Error: opcode not supported on this processor: .* \(.*\) `movt.s \$f20,\$f21,\$fcc2' +.*:160: Error: opcode not supported on this processor: .* \(.*\) `movt.d \$f20,\$f22,\$fcc2' +.*:161: Error: opcode not supported on this processor: .* \(.*\) `movt.ps \$f20,\$f22,\$fcc2' +.*:162: Error: opcode not supported on this processor: .* \(.*\) `movz \$5,\$6,\$7' +.*:163: Error: opcode not supported on this processor: .* \(.*\) `movz.s \$f0,\$f2,\$10' +.*:164: Error: opcode not supported on this processor: .* \(.*\) `movz.d \$f0,\$f2,\$10' +.*:165: Error: opcode not supported on this processor: .* \(.*\) `movz.ps \$f0,\$f2,\$10' +.*:166: Error: opcode not supported on this processor: .* \(.*\) `msub \$2,\$3' +.*:167: Error: opcode not supported on this processor: .* \(.*\) `msubu \$2,\$3' +.*:168: Error: opcode not supported on this processor: .* \(.*\) `msub.s \$f5,\$f6,\$f7,\$f8' +.*:169: Error: opcode not supported on this processor: .* \(.*\) `msub.d \$f6,\$f8,\$f10,\$f12' +.*:170: Error: opcode not supported on this processor: .* \(.*\) `msub.ps \$f6,\$f8,\$f10,\$f12' +.*:171: Error: opcode not supported on this processor: .* \(.*\) `mthi \$2' +.*:172: Error: opcode not supported on this processor: .* \(.*\) `mtlo \$2' +.*:173: Error: opcode not supported on this processor: .* \(.*\) `mul.ps \$f10,\$f20,\$f22' +.*:174: Error: opcode not supported on this processor: .* \(.*\) `mult \$2,\$3' +.*:175: Error: opcode not supported on this processor: .* \(.*\) `multu \$2,\$3' +.*:176: Error: opcode not supported on this processor: .* \(.*\) `neg.ps \$f22,\$f24' +.*:177: Error: opcode not supported on this processor: .* \(.*\) `nmadd.s \$f5,\$f6,\$f7,\$f8' +.*:178: Error: opcode not supported on this processor: .* \(.*\) `nmadd.d \$f6,\$f8,\$f10,\$f12' +.*:179: Error: opcode not supported on this processor: .* \(.*\) `nmadd.ps \$f6,\$f8,\$f10,\$f12' +.*:180: Error: opcode not supported on this processor: .* \(.*\) `nmsub.s \$f5,\$f6,\$f7,\$f8' +.*:181: Error: opcode not supported on this processor: .* \(.*\) `nmsub.d \$f6,\$f8,\$f10,\$f12' +.*:182: Error: opcode not supported on this processor: .* \(.*\) `nmsub.ps \$f6,\$f8,\$f10,\$f12' +.*:183: Error: opcode not supported on this processor: .* \(.*\) `pll.ps \$f24,\$f20,\$f26' +.*:184: Error: opcode not supported on this processor: .* \(.*\) `plu.ps \$f24,\$f20,\$f26' +.*:185: Error: opcode not supported on this processor: .* \(.*\) `pul.ps \$f24,\$f20,\$f26' +.*:186: Error: opcode not supported on this processor: .* \(.*\) `puu.ps \$f24,\$f20,\$f26' +.*:187: Error: operand 2 out of range `pref 5,32768\(\$4\)' +.*:188: Error: operand 2 out of range `pref 5,-32769\(\$5\)' +.*:189: Error: opcode not supported on this processor: .* \(.*\) `prefx 5,\$3\(\$5\)' +.*:190: Error: operand 2 out of range `sc \$5,32768\(\$4\)' +.*:191: Error: operand 2 out of range `sc \$5,-32769\(\$5\)' +.*:192: Error: operand 2 out of range `sdc2 \$5,32768\(\$4\)' +.*:193: Error: operand 2 out of range `sdc2 \$5,-32769\(\$5\)' +.*:194: Error: opcode not supported on this processor: .* \(.*\) `sdxc1 \$f0,\$0\(\$2\)' +.*:195: Error: opcode not supported on this processor: .* \(.*\) `sub.ps \$f20,\$f28,\$f26' +.*:196: Error: operand 2 out of range `swc2 \$5,32768\(\$4\)' +.*:197: Error: operand 2 out of range `swc2 \$5,-32769\(\$5\)' +.*:198: Error: opcode not supported on this processor: .* \(.*\) `suxc1 \$f0,\$0\(\$2\)' +.*:199: Error: opcode not supported on this processor: .* \(.*\) `swl \$2,1\(\$3\)' +.*:200: Error: opcode not supported on this processor: .* \(.*\) `swle \$4,0\(\$6\)' +.*:201: Error: opcode not supported on this processor: .* \(.*\) `swr \$2,1\(\$3\)' +.*:202: Error: opcode not supported on this processor: .* \(.*\) `swre \$4,0\(\$6\)' +.*:203: Error: opcode not supported on this processor: .* \(.*\) `swxc1 \$f0,\$0\(\$2\)' +.*:204: Error: opcode not supported on this processor: .* \(.*\) `teqi \$11,1024' +.*:205: Error: opcode not supported on this processor: .* \(.*\) `tgei \$11,1024' +.*:206: Error: opcode not supported on this processor: .* \(.*\) `tgeiu \$11,1024' +.*:207: Error: opcode not supported on this processor: .* \(.*\) `tlti \$11,1024' +.*:208: Error: opcode not supported on this processor: .* \(.*\) `tltiu \$11,1024' +.*:209: Error: opcode not supported on this processor: .* \(.*\) `tnei \$11,1024' diff --git a/binutils-2.24/gas/testsuite/gas/mips/r6-removed.s b/binutils-2.24/gas/testsuite/gas/mips/r6-removed.s new file mode 100644 index 0000000..b709f2d --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/r6-removed.s @@ -0,0 +1,210 @@ + .set reorder + .set eva + abs.ps $f0,$f2 + add.ps $f0,$f2,$f2 + addi $15,$16,256 + alnv.ps $f0,$f2,$f2,$3 + bc0f 1f + bc0fl 1f + bc0t 1f + bc0tl 1f + bc1f 1f + bc1fl 1f + bc1t 1f + bc1tl 1f + bc2f 1f + bc2fl 1f + bc2t 1f + bc2tl 1f + bc3f 1f + bc3fl 1f + bc3t 1f + bc3tl 1f + beql $28,$29,1f + bgezal $4,1f + bgezall $28,1f + bgezl $28,1f + bgtzl $28,1f + blezl $28,1f + bltzal $4,1f + bltzall $28,1f + bltzl $28,1f + bnel $28,$29,1f + c.f.s $f0,$f2 + c.un.s $f0,$f2 + c.eq.s $f0,$f2 + c.ueq.s $f0,$f2 + c.olt.s $f0,$f2 + c.ult.s $f0,$f2 + c.ole.s $f0,$f2 + c.ule.s $f0,$f2 + c.sf.s $f0,$f2 + c.ngle.s $f0,$f2 + c.seq.s $f0,$f2 + c.ngl.s $f0,$f2 + c.lt.s $f0,$f2 + c.nge.s $f0,$f2 + c.le.s $f0,$f2 + c.ngt.s $f0,$f2 + c.f.ps $f0,$f2 + c.un.ps $f0,$f2 + c.eq.ps $f0,$f2 + c.ueq.ps $f0,$f2 + c.olt.ps $f0,$f2 + c.ult.ps $f0,$f2 + c.ole.ps $f0,$f2 + c.ule.ps $f0,$f2 + c.sf.ps $f0,$f2 + c.ngle.ps $f0,$f2 + c.seq.ps $f0,$f2 + c.ngl.ps $f0,$f2 + c.lt.ps $f0,$f2 + c.nge.ps $f0,$f2 + c.le.ps $f0,$f2 + c.ngt.ps $f0,$f2 + c.f.d $f0,$f2 + c.un.d $f0,$f2 + c.eq.d $f0,$f2 + c.ueq.d $f0,$f2 + c.olt.d $f0,$f2 + c.ult.d $f0,$f2 + c.ole.d $f0,$f2 + c.ule.d $f0,$f2 + c.sf.d $f0,$f2 + c.ngle.d $f0,$f2 + c.seq.d $f0,$f2 + c.ngl.d $f0,$f2 + c.lt.d $f0,$f2 + c.nge.d $f0,$f2 + c.le.d $f0,$f2 + c.ngt.d $f0,$f2 + c.f.s $fcc2, $f0,$f2 + c.un.s $fcc2, $f0,$f2 + c.eq.s $fcc2, $f0,$f2 + c.ueq.s $fcc2, $f0,$f2 + c.olt.s $fcc2, $f0,$f2 + c.ult.s $fcc2, $f0,$f2 + c.ole.s $fcc2, $f0,$f2 + c.ule.s $fcc2, $f0,$f2 + c.sf.s $fcc2, $f0,$f2 + c.ngle.s $fcc2, $f0,$f2 + c.seq.s $fcc2, $f0,$f2 + c.ngl.s $fcc2, $f0,$f2 + c.lt.s $fcc2, $f0,$f2 + c.nge.s $fcc2, $f0,$f2 + c.le.s $fcc2, $f0,$f2 + c.ngt.s $fcc2, $f0,$f2 + c.f.ps $fcc2, $f0,$f2 + c.un.ps $fcc2, $f0,$f2 + c.eq.ps $fcc2, $f0,$f2 + c.ueq.ps $fcc2, $f0,$f2 + c.olt.ps $fcc2, $f0,$f2 + c.ult.ps $fcc2, $f0,$f2 + c.ole.ps $fcc2, $f0,$f2 + c.ule.ps $fcc2, $f0,$f2 + c.sf.ps $fcc2, $f0,$f2 + c.ngle.ps $fcc2, $f0,$f2 + c.seq.ps $fcc2, $f0,$f2 + c.ngl.ps $fcc2, $f0,$f2 + c.lt.ps $fcc2, $f0,$f2 + c.nge.ps $fcc2, $f0,$f2 + c.le.ps $fcc2, $f0,$f2 + c.ngt.ps $fcc2, $f0,$f2 + c.f.d $fcc2, $f0,$f2 + c.un.d $fcc2, $f0,$f2 + c.eq.d $fcc2, $f0,$f2 + c.ueq.d $fcc2, $f0,$f2 + c.olt.d $fcc2, $f0,$f2 + c.ult.d $fcc2, $f0,$f2 + c.ole.d $fcc2, $f0,$f2 + c.ule.d $fcc2, $f0,$f2 + c.sf.d $fcc2, $f0,$f2 + c.ngle.d $fcc2, $f0,$f2 + c.seq.d $fcc2, $f0,$f2 + c.ngl.d $fcc2, $f0,$f2 + c.lt.d $fcc2, $f0,$f2 + c.nge.d $fcc2, $f0,$f2 + c.le.d $fcc2, $f0,$f2 + c.ngt.d $fcc2, $f0,$f2 + cache 5, 32768($4) + cache 5, -32769($5) + cvt.ps.s $f2,$f3,$f4 + jalx 1f + ldxc1 $f0,$0($2) + ll $3, 32768($4) + ll $3, -32769($5) + luxc1 $f0,$0($2) + lwl $2, 1($3) + lwle $4,0($6) + lwr $2, 1($3) + lwre $4,0($6) + lwxc1 $f0,$0($2) + madd $2,$3 + maddu $2,$3 + madd.s $f5,$f6,$f7,$f8 + madd.d $f6,$f8,$f10,$f12 + madd.ps $f6,$f8,$f10,$f12 + mfhi $2 + mflo $2 + mov.ps $f10,$f20 + movf $8,$9,$fcc0 + movf.s $f8,$f9,$fcc0 + movf.d $f8,$f10,$fcc0 + movf.ps $f8,$f10,$fcc0 + movn $2,$3,$4 + movn.s $f0,$f2,$10 + movn.d $f0,$f2,$10 + movn.ps $f0,$f2,$10 + movt $10,$11,$fcc2 + movt.s $f20,$f21,$fcc2 + movt.d $f20,$f22,$fcc2 + movt.ps $f20,$f22,$fcc2 + movz $5,$6,$7 + movz.s $f0,$f2,$10 + movz.d $f0,$f2,$10 + movz.ps $f0,$f2,$10 + msub $2,$3 + msubu $2,$3 + msub.s $f5,$f6,$f7,$f8 + msub.d $f6,$f8,$f10,$f12 + msub.ps $f6,$f8,$f10,$f12 + mthi $2 + mtlo $2 + mul.ps $f10,$f20,$f22 + mult $2,$3 + multu $2,$3 + neg.ps $f22,$f24 + nmadd.s $f5,$f6,$f7,$f8 + nmadd.d $f6,$f8,$f10,$f12 + nmadd.ps $f6,$f8,$f10,$f12 + nmsub.s $f5,$f6,$f7,$f8 + nmsub.d $f6,$f8,$f10,$f12 + nmsub.ps $f6,$f8,$f10,$f12 + pll.ps $f24,$f20,$f26 + plu.ps $f24,$f20,$f26 + pul.ps $f24,$f20,$f26 + puu.ps $f24,$f20,$f26 + pref 5, 32768($4) + pref 5, -32769($5) + prefx 5, $3($5) + sc $5, 32768($4) + sc $5, -32769($5) + sdc2 $5, 32768($4) + sdc2 $5, -32769($5) + sdxc1 $f0,$0($2) + sub.ps $f20,$f28,$f26 + swc2 $5, 32768($4) + swc2 $5, -32769($5) + suxc1 $f0,$0($2) + swl $2, 1($3) + swle $4,0($6) + swr $2, 1($3) + swre $4,0($6) + swxc1 $f0,$0($2) + teqi $11,1024 + tgei $11,1024 + tgeiu $11,1024 + tlti $11,1024 + tltiu $11,1024 + tnei $11,1024 +1: diff --git a/binutils-2.24/gas/testsuite/gas/mips/r6.d b/binutils-2.24/gas/testsuite/gas/mips/r6.d new file mode 100644 index 0000000..29f1a02 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/r6.d @@ -0,0 +1,490 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: MIPS MIPSR6 instructions +#as: -32 + +# Check MIPSR6 instructions + +.*: +file format .*mips.* + +Disassembly of section .text: +0+0000 <[^>]*> 46020818 maddf.s \$f0,\$f1,\$f2 +0+0004 <[^>]*> 462520d8 maddf.d \$f3,\$f4,\$f5 +0+0008 <[^>]*> 46083999 msubf.s \$f6,\$f7,\$f8 +0+000c <[^>]*> 462b5259 msubf.d \$f9,\$f10,\$f11 +0+0010 <[^>]*> 46820800 cmp.af.s \$f0,\$f1,\$f2 +0+0014 <[^>]*> 46a20800 cmp.af.d \$f0,\$f1,\$f2 +0+0018 <[^>]*> 46820801 cmp.un.s \$f0,\$f1,\$f2 +0+001c <[^>]*> 46a20801 cmp.un.d \$f0,\$f1,\$f2 +0+0020 <[^>]*> 46820802 cmp.eq.s \$f0,\$f1,\$f2 +0+0024 <[^>]*> 46a20802 cmp.eq.d \$f0,\$f1,\$f2 +0+0028 <[^>]*> 46820803 cmp.ueq.s \$f0,\$f1,\$f2 +0+002c <[^>]*> 46a20803 cmp.ueq.d \$f0,\$f1,\$f2 +0+0030 <[^>]*> 46820804 cmp.lt.s \$f0,\$f1,\$f2 +0+0034 <[^>]*> 46a20804 cmp.lt.d \$f0,\$f1,\$f2 +0+0038 <[^>]*> 46820805 cmp.ult.s \$f0,\$f1,\$f2 +0+003c <[^>]*> 46a20805 cmp.ult.d \$f0,\$f1,\$f2 +0+0040 <[^>]*> 46820806 cmp.le.s \$f0,\$f1,\$f2 +0+0044 <[^>]*> 46a20806 cmp.le.d \$f0,\$f1,\$f2 +0+0048 <[^>]*> 46820807 cmp.ule.s \$f0,\$f1,\$f2 +0+004c <[^>]*> 46a20807 cmp.ule.d \$f0,\$f1,\$f2 +0+0050 <[^>]*> 46820808 cmp.saf.s \$f0,\$f1,\$f2 +0+0054 <[^>]*> 46a20808 cmp.saf.d \$f0,\$f1,\$f2 +0+0058 <[^>]*> 46820809 cmp.sun.s \$f0,\$f1,\$f2 +0+005c <[^>]*> 46a20809 cmp.sun.d \$f0,\$f1,\$f2 +0+0060 <[^>]*> 4682080a cmp.seq.s \$f0,\$f1,\$f2 +0+0064 <[^>]*> 46a2080a cmp.seq.d \$f0,\$f1,\$f2 +0+0068 <[^>]*> 4682080b cmp.sueq.s \$f0,\$f1,\$f2 +0+006c <[^>]*> 46a2080b cmp.sueq.d \$f0,\$f1,\$f2 +0+0070 <[^>]*> 4682080c cmp.slt.s \$f0,\$f1,\$f2 +0+0074 <[^>]*> 46a2080c cmp.slt.d \$f0,\$f1,\$f2 +0+0078 <[^>]*> 4682080d cmp.sult.s \$f0,\$f1,\$f2 +0+007c <[^>]*> 46a2080d cmp.sult.d \$f0,\$f1,\$f2 +0+0080 <[^>]*> 4682080e cmp.sle.s \$f0,\$f1,\$f2 +0+0084 <[^>]*> 46a2080e cmp.sle.d \$f0,\$f1,\$f2 +0+0088 <[^>]*> 4682080f cmp.sule.s \$f0,\$f1,\$f2 +0+008c <[^>]*> 46a2080f cmp.sule.d \$f0,\$f1,\$f2 +0+0090 <[^>]*> 46820811 cmp.or.s \$f0,\$f1,\$f2 +0+0094 <[^>]*> 46a20811 cmp.or.d \$f0,\$f1,\$f2 +0+0098 <[^>]*> 46820812 cmp.une.s \$f0,\$f1,\$f2 +0+009c <[^>]*> 46a20812 cmp.une.d \$f0,\$f1,\$f2 +0+00a0 <[^>]*> 46820813 cmp.ne.s \$f0,\$f1,\$f2 +0+00a4 <[^>]*> 46a20813 cmp.ne.d \$f0,\$f1,\$f2 +0+00a8 <[^>]*> 46820819 cmp.sor.s \$f0,\$f1,\$f2 +0+00ac <[^>]*> 46a20819 cmp.sor.d \$f0,\$f1,\$f2 +0+00b0 <[^>]*> 4682081a cmp.sune.s \$f0,\$f1,\$f2 +0+00b4 <[^>]*> 46a2081a cmp.sune.d \$f0,\$f1,\$f2 +0+00b8 <[^>]*> 4682081b cmp.sne.s \$f0,\$f1,\$f2 +0+00bc <[^>]*> 46a2081b cmp.sne.d \$f0,\$f1,\$f2 +0+00c0 <[^>]*> 4520ffff bc1eqz \$f0,000000c0 <[^>]*> +[ ]*c0: R_MIPS_PC16 .L1.1 +0+00c4 <[^>]*> 00000000 nop +0+00c8 <[^>]*> 453fffff bc1eqz \$f31,000000c8 <[^>]*> +[ ]*c8: R_MIPS_PC16 .L1.1 +0+00cc <[^>]*> 00000000 nop +0+00d0 <[^>]*> 453fffff bc1eqz \$f31,000000d0 <[^>]*> +[ ]*d0: R_MIPS_PC16 new +0+00d4 <[^>]*> 00000000 nop +0+00d8 <[^>]*> 453fffff bc1eqz \$f31,000000d8 <[^>]*> +[ ]*d8: R_MIPS_PC16 external_label +0+00dc <[^>]*> 00000000 nop +0+00e0 <[^>]*> 45a0ffff bc1nez \$f0,000000e0 <[^>]*> +[ ]*e0: R_MIPS_PC16 .L1.1 +0+00e4 <[^>]*> 00000000 nop +0+00e8 <[^>]*> 45bfffff bc1nez \$f31,000000e8 <[^>]*> +[ ]*e8: R_MIPS_PC16 .L1.1 +0+00ec <[^>]*> 00000000 nop +0+00f0 <[^>]*> 45bfffff bc1nez \$f31,000000f0 <[^>]*> +[ ]*f0: R_MIPS_PC16 new +0+00f4 <[^>]*> 00000000 nop +0+00f8 <[^>]*> 45bfffff bc1nez \$f31,000000f8 <[^>]*> +[ ]*f8: R_MIPS_PC16 external_label +0+00fc <[^>]*> 00000000 nop +0+0100 <[^>]*> 4920ffff bc2eqz \$0,00000100 <[^>]*> +[ ]*100: R_MIPS_PC16 .L1.1 +0+0104 <[^>]*> 00000000 nop +0+0108 <[^>]*> 493fffff bc2eqz \$31,00000108 <[^>]*> +[ ]*108: R_MIPS_PC16 .L1.1 +0+010c <[^>]*> 00000000 nop +0+0110 <[^>]*> 493fffff bc2eqz \$31,00000110 <[^>]*> +[ ]*110: R_MIPS_PC16 new +0+0114 <[^>]*> 00000000 nop +0+0118 <[^>]*> 493fffff bc2eqz \$31,00000118 <[^>]*> +[ ]*118: R_MIPS_PC16 external_label +0+011c <[^>]*> 00000000 nop +0+0120 <[^>]*> 49a0ffff bc2nez \$0,00000120 <[^>]*> +[ ]*120: R_MIPS_PC16 .L1.1 +0+0124 <[^>]*> 00000000 nop +0+0128 <[^>]*> 49bfffff bc2nez \$31,00000128 <[^>]*> +[ ]*128: R_MIPS_PC16 .L1.1 +0+012c <[^>]*> 00000000 nop +0+0130 <[^>]*> 49bfffff bc2nez \$31,00000130 <[^>]*> +[ ]*130: R_MIPS_PC16 new +0+0134 <[^>]*> 00000000 nop +0+0138 <[^>]*> 49bfffff bc2nez \$31,00000138 <[^>]*> +[ ]*138: R_MIPS_PC16 external_label +0+013c <[^>]*> 00000000 nop +0+0140 <[^>]*> 46020810 sel.s \$f0,\$f1,\$f2 +0+0144 <[^>]*> 46220810 sel.d \$f0,\$f1,\$f2 +0+0148 <[^>]*> 46020814 seleqz.s \$f0,\$f1,\$f2 +0+014c <[^>]*> 46220814 seleqz.d \$f0,\$f1,\$f2 +0+0150 <[^>]*> 46020817 selnez.s \$f0,\$f1,\$f2 +0+0154 <[^>]*> 46220817 selnez.d \$f0,\$f1,\$f2 +0+0158 <[^>]*> 00641035 seleqz v0,v1,a0 +0+015c <[^>]*> 00641037 selnez v0,v1,a0 +0+0160 <[^>]*> 00641098 mul v0,v1,a0 +0+0164 <[^>]*> 006410d8 muh v0,v1,a0 +0+0168 <[^>]*> 00641099 mulu v0,v1,a0 +0+016c <[^>]*> 006410d9 muhu v0,v1,a0 +0+0170 <[^>]*> 0064109a div v0,v1,a0 +0+0174 <[^>]*> 006410da mod v0,v1,a0 +0+0178 <[^>]*> 0064109b divu v0,v1,a0 +0+017c <[^>]*> 006410db modu v0,v1,a0 +0+0180 <[^>]*> 49422000 lwc2 \$2,0\(a0\) +0+0184 <[^>]*> 49422400 lwc2 \$2,-1024\(a0\) +0+0188 <[^>]*> 494223ff lwc2 \$2,1023\(a0\) +0+018c <[^>]*> 49622000 swc2 \$2,0\(a0\) +0+0190 <[^>]*> 49622400 swc2 \$2,-1024\(a0\) +0+0194 <[^>]*> 496223ff swc2 \$2,1023\(a0\) +0+0198 <[^>]*> 49c22000 ldc2 \$2,0\(a0\) +0+019c <[^>]*> 49c22400 ldc2 \$2,-1024\(a0\) +0+01a0 <[^>]*> 49c223ff ldc2 \$2,1023\(a0\) +0+01a4 <[^>]*> 49e22000 sdc2 \$2,0\(a0\) +0+01a8 <[^>]*> 49e22400 sdc2 \$2,-1024\(a0\) +0+01ac <[^>]*> 49e223ff sdc2 \$2,1023\(a0\) +0+01b0 <[^>]*> 00641005 lsa v0,v1,a0,0x1 +0+01b4 <[^>]*> 006410c5 lsa v0,v1,a0,0x4 +0+01b8 <[^>]*> 00601050 clz v0,v1 +0+01bc <[^>]*> 00601051 clo v0,v1 +0+01c0 <[^>]*> 0000000e sdbbp +0+01c4 <[^>]*> 0000000e sdbbp +0+01c8 <[^>]*> 0000004e sdbbp 0x1 +0+01cc <[^>]*> 03ffffce sdbbp 0xfffff +0+01d0 <[^>]*> 3c02ffff lui v0,0xffff +0+01d4 <[^>]*> 7c008035 pref 0x0,-256\(zero\) +0+01d8 <[^>]*> 7fff7fb5 pref 0x1f,255\(ra\) +0+01dc <[^>]*> 7c628036 ll v0,-256\(v1\) +0+01e0 <[^>]*> 7c627fb6 ll v0,255\(v1\) +0+01e4 <[^>]*> 7c628026 sc v0,-256\(v1\) +0+01e8 <[^>]*> 7c627fa6 sc v0,255\(v1\) +0+01ec <[^>]*> 7c608025 cache 0x0,-256\(v1\) +0+01f0 <[^>]*> 7c7f7fa5 cache 0x1f,255\(v1\) +0+01f4 <[^>]*> 7c432220 align a0,v0,v1,0 +0+01f8 <[^>]*> 7c432260 align a0,v0,v1,1 +0+01fc <[^>]*> 7c4322a0 align a0,v0,v1,2 +0+0200 <[^>]*> 7c4322e0 align a0,v0,v1,3 +0+0204 <[^>]*> 7c022020 bitswap a0,v0 +0+0208 <[^>]*> 2000ffff bovc zero,zero,00000208 <[^>]*> +[ ]*208: R_MIPS_PC16 ext +0+020c <[^>]*> 00000000 nop +0+0210 <[^>]*> 2040ffff bovc v0,zero,00000210 <[^>]*> +[ ]*210: R_MIPS_PC16 ext +0+0214 <[^>]*> 00000000 nop +0+0218 <[^>]*> 2040ffff bovc v0,zero,00000218 <[^>]*> +[ ]*218: R_MIPS_PC16 ext +0+021c <[^>]*> 00000000 nop +0+0220 <[^>]*> 2082ffff bovc a0,v0,00000220 <[^>]*> +[ ]*220: R_MIPS_PC16 ext +0+0224 <[^>]*> 00000000 nop +0+0228 <[^>]*> 2082ffff bovc a0,v0,00000228 <[^>]*> +[ ]*228: R_MIPS_PC16 ext +0+022c <[^>]*> 00000000 nop +0+0230 <[^>]*> 20828000 bovc a0,v0,fffe0234 <[^>]*> +[ ]*230: R_MIPS_PC16 L0. +0+0234 <[^>]*> 00000000 nop +0+0238 <[^>]*> 20827fff bovc a0,v0,00020238 <[^>]*> +[ ]*238: R_MIPS_PC16 L0. +0+023c <[^>]*> 00000000 nop +0+0240 <[^>]*> 2082ffff bovc a0,v0,00000240 <[^>]*> +[ ]*240: R_MIPS_PC16 .L1.2 +0+0244 <[^>]*> 00000000 nop +0+0248 <[^>]*> 2042ffff bovc v0,v0,00000248 <[^>]*> +[ ]*248: R_MIPS_PC16 ext +0+024c <[^>]*> 00000000 nop +0+0250 <[^>]*> 20428000 bovc v0,v0,fffe0254 <[^>]*> +[ ]*250: R_MIPS_PC16 L0. +0+0254 <[^>]*> 00000000 nop +0+0258 <[^>]*> 2002ffff beqzalc v0,00000258 <[^>]*> +[ ]*258: R_MIPS_PC16 ext +0+025c <[^>]*> 00000000 nop +0+0260 <[^>]*> 20028000 beqzalc v0,fffe0264 <[^>]*> +[ ]*260: R_MIPS_PC16 L0. +0+0264 <[^>]*> 00000000 nop +0+0268 <[^>]*> 20027fff beqzalc v0,00020268 <[^>]*> +[ ]*268: R_MIPS_PC16 L0. +0+026c <[^>]*> 00000000 nop +0+0270 <[^>]*> 2002ffff beqzalc v0,00000270 <[^>]*> +[ ]*270: R_MIPS_PC16 .L1.2 +0+0274 <[^>]*> 00000000 nop +0+0278 <[^>]*> 2043ffff beqc v0,v1,00000278 <[^>]*> +[ ]*278: R_MIPS_PC16 ext +0+027c <[^>]*> 00000000 nop +0+0280 <[^>]*> 2043ffff beqc v0,v1,00000280 <[^>]*> +[ ]*280: R_MIPS_PC16 ext +0+0284 <[^>]*> 00000000 nop +0+0288 <[^>]*> 20438000 beqc v0,v1,fffe028c <[^>]*> +[ ]*288: R_MIPS_PC16 L0. +0+028c <[^>]*> 00000000 nop +0+0290 <[^>]*> 20437fff beqc v0,v1,00020290 <[^>]*> +[ ]*290: R_MIPS_PC16 L0. +0+0294 <[^>]*> 00000000 nop +0+0298 <[^>]*> 2043ffff beqc v0,v1,00000298 <[^>]*> +[ ]*298: R_MIPS_PC16 .L1.2 +0+029c <[^>]*> 00000000 nop +0+02a0 <[^>]*> 6000ffff bnvc zero,zero,000002a0 <[^>]*> +[ ]*2a0: R_MIPS_PC16 ext +0+02a4 <[^>]*> 00000000 nop +0+02a8 <[^>]*> 6040ffff bnvc v0,zero,000002a8 <[^>]*> +[ ]*2a8: R_MIPS_PC16 ext +0+02ac <[^>]*> 00000000 nop +0+02b0 <[^>]*> 6040ffff bnvc v0,zero,000002b0 <[^>]*> +[ ]*2b0: R_MIPS_PC16 ext +0+02b4 <[^>]*> 00000000 nop +0+02b8 <[^>]*> 6082ffff bnvc a0,v0,000002b8 <[^>]*> +[ ]*2b8: R_MIPS_PC16 ext +0+02bc <[^>]*> 00000000 nop +0+02c0 <[^>]*> 6082ffff bnvc a0,v0,000002c0 <[^>]*> +[ ]*2c0: R_MIPS_PC16 ext +0+02c4 <[^>]*> 00000000 nop +0+02c8 <[^>]*> 60828000 bnvc a0,v0,fffe02cc <[^>]*> +[ ]*2c8: R_MIPS_PC16 L0. +0+02cc <[^>]*> 00000000 nop +0+02d0 <[^>]*> 60827fff bnvc a0,v0,000202d0 <[^>]*> +[ ]*2d0: R_MIPS_PC16 L0. +0+02d4 <[^>]*> 00000000 nop +0+02d8 <[^>]*> 6082ffff bnvc a0,v0,000002d8 <[^>]*> +[ ]*2d8: R_MIPS_PC16 .L1.2 +0+02dc <[^>]*> 00000000 nop +0+02e0 <[^>]*> 6042ffff bnvc v0,v0,000002e0 <[^>]*> +[ ]*2e0: R_MIPS_PC16 ext +0+02e4 <[^>]*> 00000000 nop +0+02e8 <[^>]*> 60428000 bnvc v0,v0,fffe02ec <[^>]*> +[ ]*2e8: R_MIPS_PC16 L0. +0+02ec <[^>]*> 00000000 nop +0+02f0 <[^>]*> 6002ffff bnezalc v0,000002f0 <[^>]*> +[ ]*2f0: R_MIPS_PC16 ext +0+02f4 <[^>]*> 00000000 nop +0+02f8 <[^>]*> 60028000 bnezalc v0,fffe02fc <[^>]*> +[ ]*2f8: R_MIPS_PC16 L0. +0+02fc <[^>]*> 00000000 nop +0+0300 <[^>]*> 60027fff bnezalc v0,00020300 <[^>]*> +[ ]*300: R_MIPS_PC16 L0. +0+0304 <[^>]*> 00000000 nop +0+0308 <[^>]*> 6002ffff bnezalc v0,00000308 <[^>]*> +[ ]*308: R_MIPS_PC16 .L1.2 +0+030c <[^>]*> 00000000 nop +0+0310 <[^>]*> 6043ffff bnec v0,v1,00000310 <[^>]*> +[ ]*310: R_MIPS_PC16 ext +0+0314 <[^>]*> 00000000 nop +0+0318 <[^>]*> 6043ffff bnec v0,v1,00000318 <[^>]*> +[ ]*318: R_MIPS_PC16 ext +0+031c <[^>]*> 00000000 nop +0+0320 <[^>]*> 60438000 bnec v0,v1,fffe0324 <[^>]*> +[ ]*320: R_MIPS_PC16 L0. +0+0324 <[^>]*> 00000000 nop +0+0328 <[^>]*> 60437fff bnec v0,v1,00020328 <[^>]*> +[ ]*328: R_MIPS_PC16 L0. +0+032c <[^>]*> 00000000 nop +0+0330 <[^>]*> 6043ffff bnec v0,v1,00000330 <[^>]*> +[ ]*330: R_MIPS_PC16 .L1.2 +0+0334 <[^>]*> 00000000 nop +0+0338 <[^>]*> 5802ffff blezc v0,00000338 <[^>]*> +[ ]*338: R_MIPS_PC16 ext +0+033c <[^>]*> 00000000 nop +0+0340 <[^>]*> 58028000 blezc v0,fffe0344 <[^>]*> +[ ]*340: R_MIPS_PC16 L0. +0+0344 <[^>]*> 00000000 nop +0+0348 <[^>]*> 58027fff blezc v0,00020348 <[^>]*> +[ ]*348: R_MIPS_PC16 L0. +0+034c <[^>]*> 00000000 nop +0+0350 <[^>]*> 5802ffff blezc v0,00000350 <[^>]*> +[ ]*350: R_MIPS_PC16 .L1.2 +0+0354 <[^>]*> 00000000 nop +0+0358 <[^>]*> 5842ffff bgezc v0,00000358 <[^>]*> +[ ]*358: R_MIPS_PC16 ext +0+035c <[^>]*> 00000000 nop +0+0360 <[^>]*> 58428000 bgezc v0,fffe0364 <[^>]*> +[ ]*360: R_MIPS_PC16 L0. +0+0364 <[^>]*> 00000000 nop +0+0368 <[^>]*> 58427fff bgezc v0,00020368 <[^>]*> +[ ]*368: R_MIPS_PC16 L0. +0+036c <[^>]*> 00000000 nop +0+0370 <[^>]*> 5842ffff bgezc v0,00000370 <[^>]*> +[ ]*370: R_MIPS_PC16 .L1.2 +0+0374 <[^>]*> 00000000 nop +0+0378 <[^>]*> 5843ffff bgec v0,v1,00000378 <[^>]*> +[ ]*378: R_MIPS_PC16 ext +0+037c <[^>]*> 00000000 nop +0+0380 <[^>]*> 58438000 bgec v0,v1,fffe0384 <[^>]*> +[ ]*380: R_MIPS_PC16 L0. +0+0384 <[^>]*> 00000000 nop +0+0388 <[^>]*> 58437fff bgec v0,v1,00020388 <[^>]*> +[ ]*388: R_MIPS_PC16 L0. +0+038c <[^>]*> 00000000 nop +0+0390 <[^>]*> 5843ffff bgec v0,v1,00000390 <[^>]*> +[ ]*390: R_MIPS_PC16 .L1.2 +0+0394 <[^>]*> 00000000 nop +0+0398 <[^>]*> 5862ffff bgec v1,v0,00000398 <[^>]*> +[ ]*398: R_MIPS_PC16 .L1.2 +0+039c <[^>]*> 00000000 nop +0+03a0 <[^>]*> 5c02ffff bgtzc v0,000003a0 <[^>]*> +[ ]*3a0: R_MIPS_PC16 ext +0+03a4 <[^>]*> 00000000 nop +0+03a8 <[^>]*> 5c028000 bgtzc v0,fffe03ac <[^>]*> +[ ]*3a8: R_MIPS_PC16 L0. +0+03ac <[^>]*> 00000000 nop +0+03b0 <[^>]*> 5c027fff bgtzc v0,000203b0 <[^>]*> +[ ]*3b0: R_MIPS_PC16 L0. +0+03b4 <[^>]*> 00000000 nop +0+03b8 <[^>]*> 5c02ffff bgtzc v0,000003b8 <[^>]*> +[ ]*3b8: R_MIPS_PC16 .L1.2 +0+03bc <[^>]*> 00000000 nop +0+03c0 <[^>]*> 5c42ffff bltzc v0,000003c0 <[^>]*> +[ ]*3c0: R_MIPS_PC16 ext +0+03c4 <[^>]*> 00000000 nop +0+03c8 <[^>]*> 5c428000 bltzc v0,fffe03cc <[^>]*> +[ ]*3c8: R_MIPS_PC16 L0. +0+03cc <[^>]*> 00000000 nop +0+03d0 <[^>]*> 5c427fff bltzc v0,000203d0 <[^>]*> +[ ]*3d0: R_MIPS_PC16 L0. +0+03d4 <[^>]*> 00000000 nop +0+03d8 <[^>]*> 5c42ffff bltzc v0,000003d8 <[^>]*> +[ ]*3d8: R_MIPS_PC16 .L1.2 +0+03dc <[^>]*> 00000000 nop +0+03e0 <[^>]*> 5c43ffff bltc v0,v1,000003e0 <[^>]*> +[ ]*3e0: R_MIPS_PC16 ext +0+03e4 <[^>]*> 00000000 nop +0+03e8 <[^>]*> 5c438000 bltc v0,v1,fffe03ec <[^>]*> +[ ]*3e8: R_MIPS_PC16 L0. +0+03ec <[^>]*> 00000000 nop +0+03f0 <[^>]*> 5c437fff bltc v0,v1,000203f0 <[^>]*> +[ ]*3f0: R_MIPS_PC16 L0. +0+03f4 <[^>]*> 00000000 nop +0+03f8 <[^>]*> 5c43ffff bltc v0,v1,000003f8 <[^>]*> +[ ]*3f8: R_MIPS_PC16 .L1.2 +0+03fc <[^>]*> 00000000 nop +0+0400 <[^>]*> 5c62ffff bltc v1,v0,00000400 <[^>]*> +[ ]*400: R_MIPS_PC16 .L1.2 +0+0404 <[^>]*> 00000000 nop +0+0408 <[^>]*> 1802ffff blezalc v0,00000408 <[^>]*> +[ ]*408: R_MIPS_PC16 ext +0+040c <[^>]*> 00000000 nop +0+0410 <[^>]*> 18028000 blezalc v0,fffe0414 <[^>]*> +[ ]*410: R_MIPS_PC16 L0. +0+0414 <[^>]*> 00000000 nop +0+0418 <[^>]*> 18027fff blezalc v0,00020418 <[^>]*> +[ ]*418: R_MIPS_PC16 L0. +0+041c <[^>]*> 00000000 nop +0+0420 <[^>]*> 1802ffff blezalc v0,00000420 <[^>]*> +[ ]*420: R_MIPS_PC16 .L1.2 +0+0424 <[^>]*> 00000000 nop +0+0428 <[^>]*> 1842ffff bgezalc v0,00000428 <[^>]*> +[ ]*428: R_MIPS_PC16 ext +0+042c <[^>]*> 00000000 nop +0+0430 <[^>]*> 18428000 bgezalc v0,fffe0434 <[^>]*> +[ ]*430: R_MIPS_PC16 L0. +0+0434 <[^>]*> 00000000 nop +0+0438 <[^>]*> 18427fff bgezalc v0,00020438 <[^>]*> +[ ]*438: R_MIPS_PC16 L0. +0+043c <[^>]*> 00000000 nop +0+0440 <[^>]*> 1842ffff bgezalc v0,00000440 <[^>]*> +[ ]*440: R_MIPS_PC16 .L1.2 +0+0444 <[^>]*> 00000000 nop +0+0448 <[^>]*> 1843ffff bgeuc v0,v1,00000448 <[^>]*> +[ ]*448: R_MIPS_PC16 ext +0+044c <[^>]*> 00000000 nop +0+0450 <[^>]*> 18438000 bgeuc v0,v1,fffe0454 <[^>]*> +[ ]*450: R_MIPS_PC16 L0. +0+0454 <[^>]*> 00000000 nop +0+0458 <[^>]*> 18437fff bgeuc v0,v1,00020458 <[^>]*> +[ ]*458: R_MIPS_PC16 L0. +0+045c <[^>]*> 00000000 nop +0+0460 <[^>]*> 1843ffff bgeuc v0,v1,00000460 <[^>]*> +[ ]*460: R_MIPS_PC16 .L1.2 +0+0464 <[^>]*> 00000000 nop +0+0468 <[^>]*> 1862ffff bgeuc v1,v0,00000468 <[^>]*> +[ ]*468: R_MIPS_PC16 .L1.2 +0+046c <[^>]*> 00000000 nop +0+0470 <[^>]*> 1c02ffff bgtzalc v0,00000470 <[^>]*> +[ ]*470: R_MIPS_PC16 ext +0+0474 <[^>]*> 00000000 nop +0+0478 <[^>]*> 1c028000 bgtzalc v0,fffe047c <[^>]*> +[ ]*478: R_MIPS_PC16 L0. +0+047c <[^>]*> 00000000 nop +0+0480 <[^>]*> 1c027fff bgtzalc v0,00020480 <[^>]*> +[ ]*480: R_MIPS_PC16 L0. +0+0484 <[^>]*> 00000000 nop +0+0488 <[^>]*> 1c02ffff bgtzalc v0,00000488 <[^>]*> +[ ]*488: R_MIPS_PC16 .L1.2 +0+048c <[^>]*> 00000000 nop +0+0490 <[^>]*> 1c42ffff bltzalc v0,00000490 <[^>]*> +[ ]*490: R_MIPS_PC16 ext +0+0494 <[^>]*> 00000000 nop +0+0498 <[^>]*> 1c428000 bltzalc v0,fffe049c <[^>]*> +[ ]*498: R_MIPS_PC16 L0. +0+049c <[^>]*> 00000000 nop +0+04a0 <[^>]*> 1c427fff bltzalc v0,000204a0 <[^>]*> +[ ]*4a0: R_MIPS_PC16 L0. +0+04a4 <[^>]*> 00000000 nop +0+04a8 <[^>]*> 1c42ffff bltzalc v0,000004a8 <[^>]*> +[ ]*4a8: R_MIPS_PC16 .L1.2 +0+04ac <[^>]*> 00000000 nop +0+04b0 <[^>]*> 1c43ffff bltuc v0,v1,000004b0 <[^>]*> +[ ]*4b0: R_MIPS_PC16 ext +0+04b4 <[^>]*> 00000000 nop +0+04b8 <[^>]*> 1c438000 bltuc v0,v1,fffe04bc <[^>]*> +[ ]*4b8: R_MIPS_PC16 L0. +0+04bc <[^>]*> 00000000 nop +0+04c0 <[^>]*> 1c437fff bltuc v0,v1,000204c0 <[^>]*> +[ ]*4c0: R_MIPS_PC16 L0. +0+04c4 <[^>]*> 00000000 nop +0+04c8 <[^>]*> 1c43ffff bltuc v0,v1,000004c8 <[^>]*> +[ ]*4c8: R_MIPS_PC16 .L1.2 +0+04cc <[^>]*> 00000000 nop +0+04d0 <[^>]*> 1c62ffff bltuc v1,v0,000004d0 <[^>]*> +[ ]*4d0: R_MIPS_PC16 .L1.2 +0+04d4 <[^>]*> 00000000 nop +0+04d8 <[^>]*> cbffffff bc 000004d8 <[^>]*> +[ ]*4d8: R_MIPS_PC26_S2 ext +0+04dc <[^>]*> ca000000 bc f80004e0 <[^>]*> +[ ]*4dc: R_MIPS_PC26_S2 L0. +0+04e0 <[^>]*> c9ffffff bc 080004e0 <[^>]*> +[ ]*4e0: R_MIPS_PC26_S2 L0. +0+04e4 <[^>]*> cbffffff bc 000004e4 <[^>]*> +[ ]*4e4: R_MIPS_PC26_S2 .L1.2 +0+04e8 <[^>]*> ebffffff balc 000004e8 <[^>]*> +[ ]*4e8: R_MIPS_PC26_S2 ext +0+04ec <[^>]*> ea000000 balc f80004f0 <[^>]*> +[ ]*4ec: R_MIPS_PC26_S2 L0. +0+04f0 <[^>]*> e9ffffff balc 080004f0 <[^>]*> +[ ]*4f0: R_MIPS_PC26_S2 L0. +0+04f4 <[^>]*> ebffffff balc 000004f4 <[^>]*> +[ ]*4f4: R_MIPS_PC26_S2 .L1.2 +0+04f8 <[^>]*> d85fffff beqzc v0,000004f8 <[^>]*> +[ ]*4f8: R_MIPS_PC21_S2 ext +0+04fc <[^>]*> 00000000 nop +0+0500 <[^>]*> d8500000 beqzc v0,ffc00504 <[^>]*> +[ ]*500: R_MIPS_PC21_S2 L0. +0+0504 <[^>]*> 00000000 nop +0+0508 <[^>]*> d84fffff beqzc v0,00400508 <[^>]*> +[ ]*508: R_MIPS_PC21_S2 L0. +0+050c <[^>]*> 00000000 nop +0+0510 <[^>]*> d85fffff beqzc v0,00000510 <[^>]*> +[ ]*510: R_MIPS_PC21_S2 .L1.2 +0+0514 <[^>]*> 00000000 nop +0+0518 <[^>]*> d8038000 jic v1,-32768 +0+051c <[^>]*> d8037fff jic v1,32767 +0+0520 <[^>]*> d81f0000 jrc ra +0+0524 <[^>]*> f85fffff bnezc v0,00000524 <[^>]*> +[ ]*524: R_MIPS_PC21_S2 ext +0+0528 <[^>]*> 00000000 nop +0+052c <[^>]*> f8500000 bnezc v0,ffc00530 <[^>]*> +[ ]*52c: R_MIPS_PC21_S2 L0. +0+0530 <[^>]*> 00000000 nop +0+0534 <[^>]*> f84fffff bnezc v0,00400534 <[^>]*> +[ ]*534: R_MIPS_PC21_S2 L0. +0+0538 <[^>]*> 00000000 nop +0+053c <[^>]*> f85fffff bnezc v0,0000053c <[^>]*> +[ ]*53c: R_MIPS_PC21_S2 .L1.2 +0+0540 <[^>]*> 00000000 nop +0+0544 <[^>]*> f8038000 jialc v1,-32768 +0+0548 <[^>]*> f8037fff jialc v1,32767 +0+054c <[^>]*> 3c43ffff aui v1,v0,0xffff +0+0550 <[^>]*> ec600000 lapc v1,00000550 <[^>]*> +[ ]*550: R_MIPS_PC19_S2 .L1.2 +0+0554 <[^>]*> ec840000 lapc a0,fff00554 <[^>]*> +[ ]*554: R_MIPS_PC19_S2 L0. +0+0558 <[^>]*> ec83ffff lapc a0,00100554 <[^>]*> +[ ]*558: R_MIPS_PC19_S2 L0. +0+055c <[^>]*> ec840000 lapc a0,fff0055c <[^>]*> +0+0560 <[^>]*> ec83ffff lapc a0,0010055c <[^>]*> +0+0564 <[^>]*> ec7effff auipc v1,0xffff +0+0568 <[^>]*> ec7fffff aluipc v1,0xffff +0+056c <[^>]*> ec880000 lwpc a0,0000056c <[^>]*> +[ ]*56c: R_MIPS_PC19_S2 .L1.2 +0+0570 <[^>]*> ec8c0000 lwpc a0,fff00570 <[^>]*> +[ ]*570: R_MIPS_PC19_S2 L0. +0+0574 <[^>]*> ec8bffff lwpc a0,00100570 <[^>]*> +[ ]*574: R_MIPS_PC19_S2 L0. +0+0578 <[^>]*> ec8c0000 lwpc a0,fff00578 <[^>]*> +0+057c <[^>]*> ec8bffff lwpc a0,00100578 <[^>]*> +0+0580 <[^>]*> 00000000 nop diff --git a/binutils-2.24/gas/testsuite/gas/mips/r6.s b/binutils-2.24/gas/testsuite/gas/mips/r6.s new file mode 100644 index 0000000..b81fba9 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/r6.s @@ -0,0 +1,259 @@ + .text + .set reorder +new: maddf.s $f0,$f1,$f2 + maddf.d $f3,$f4,$f5 + msubf.s $f6,$f7,$f8 + msubf.d $f9,$f10,$f11 + cmp.af.s $f0,$f1,$f2 + cmp.af.d $f0,$f1,$f2 + cmp.un.s $f0,$f1,$f2 + cmp.un.d $f0,$f1,$f2 + cmp.eq.s $f0,$f1,$f2 + cmp.eq.d $f0,$f1,$f2 + cmp.ueq.s $f0,$f1,$f2 + cmp.ueq.d $f0,$f1,$f2 + cmp.lt.s $f0,$f1,$f2 + cmp.lt.d $f0,$f1,$f2 + cmp.ult.s $f0,$f1,$f2 + cmp.ult.d $f0,$f1,$f2 + cmp.le.s $f0,$f1,$f2 + cmp.le.d $f0,$f1,$f2 + cmp.ule.s $f0,$f1,$f2 + cmp.ule.d $f0,$f1,$f2 + cmp.saf.s $f0,$f1,$f2 + cmp.saf.d $f0,$f1,$f2 + cmp.sun.s $f0,$f1,$f2 + cmp.sun.d $f0,$f1,$f2 + cmp.seq.s $f0,$f1,$f2 + cmp.seq.d $f0,$f1,$f2 + cmp.sueq.s $f0,$f1,$f2 + cmp.sueq.d $f0,$f1,$f2 + cmp.slt.s $f0,$f1,$f2 + cmp.slt.d $f0,$f1,$f2 + cmp.sult.s $f0,$f1,$f2 + cmp.sult.d $f0,$f1,$f2 + cmp.sle.s $f0,$f1,$f2 + cmp.sle.d $f0,$f1,$f2 + cmp.sule.s $f0,$f1,$f2 + cmp.sule.d $f0,$f1,$f2 + cmp.or.s $f0,$f1,$f2 + cmp.or.d $f0,$f1,$f2 + cmp.une.s $f0,$f1,$f2 + cmp.une.d $f0,$f1,$f2 + cmp.ne.s $f0,$f1,$f2 + cmp.ne.d $f0,$f1,$f2 + cmp.sor.s $f0,$f1,$f2 + cmp.sor.d $f0,$f1,$f2 + cmp.sune.s $f0,$f1,$f2 + cmp.sune.d $f0,$f1,$f2 + cmp.sne.s $f0,$f1,$f2 + cmp.sne.d $f0,$f1,$f2 + bc1eqz $f0,1f + bc1eqz $f31,1f + bc1eqz $f31,new + bc1eqz $f31,external_label + bc1nez $f0,1f + bc1nez $f31,1f + bc1nez $f31,new + bc1nez $f31,external_label + bc2eqz $0,1f + bc2eqz $31,1f + bc2eqz $31,new + bc2eqz $31,external_label + bc2nez $0,1f + bc2nez $31,1f + bc2nez $31,new + bc2nez $31,external_label +1: sel.s $f0,$f1,$f2 + sel.d $f0,$f1,$f2 + seleqz.s $f0,$f1,$f2 + seleqz.d $f0,$f1,$f2 + selnez.s $f0,$f1,$f2 + selnez.d $f0,$f1,$f2 + seleqz $2,$3,$4 + selnez $2,$3,$4 + mul $2,$3,$4 + muh $2,$3,$4 + mulu $2,$3,$4 + muhu $2,$3,$4 + div $2,$3,$4 + mod $2,$3,$4 + divu $2,$3,$4 + modu $2,$3,$4 + lwc2 $2,0($4) + lwc2 $2,-1024($4) + lwc2 $2,1023($4) + swc2 $2,0($4) + swc2 $2,-1024($4) + swc2 $2,1023($4) + ldc2 $2,0($4) + ldc2 $2,-1024($4) + ldc2 $2,1023($4) + sdc2 $2,0($4) + sdc2 $2,-1024($4) + sdc2 $2,1023($4) + lsa $2,$3,$4,1 + lsa $2,$3,$4,4 + clz $2,$3 + clo $2,$3 + sdbbp + sdbbp 0 + sdbbp 1 + sdbbp 1048575 + lui $2,0xffff + pref 0, -256($0) + pref 31, 255($31) + ll $2,-256($3) + ll $2,255($3) + sc $2,-256($3) + sc $2,255($3) + cache 0,-256($3) + cache 31,255($3) + + + align $4, $2, $3, 0 + align $4, $2, $3, 1 + align $4, $2, $3, 2 + align $4, $2, $3, 3 + + + bitswap $4, $2 + + bovc $0, $0, ext + bovc $2, $0, ext + bovc $0, $2, ext + bovc $2, $4, ext + bovc $4, $2, ext + bovc $2, $4, . + 4 + (-32768 << 2) + bovc $2, $4, . + 4 + (32767 << 2) + bovc $2, $4, 1f + bovc $2, $2, ext + bovc $2, $2, . + 4 + (-32768 << 2) + beqzalc $2, ext + beqzalc $2, . + 4 + (-32768 << 2) + beqzalc $2, . + 4 + (32767 << 2) + beqzalc $2, 1f + beqc $3, $2, ext + beqc $2, $3, ext + beqc $3, $2, . + 4 + (-32768 << 2) + beqc $3, $2, . + 4 + (32767 << 2) + beqc $3, $2, 1f + + bnvc $0, $0, ext + bnvc $2, $0, ext + bnvc $0, $2, ext + bnvc $2, $4, ext + bnvc $4, $2, ext + bnvc $2, $4, . + 4 + (-32768 << 2) + bnvc $2, $4, . + 4 + (32767 << 2) + bnvc $2, $4, 1f + bnvc $2, $2, ext + bnvc $2, $2, . + 4 + (-32768 << 2) + bnezalc $2, ext + bnezalc $2, . + 4 + (-32768 << 2) + bnezalc $2, . + 4 + (32767 << 2) + bnezalc $2, 1f + bnec $3, $2, ext + bnec $2, $3, ext + bnec $3, $2, . + 4 + (-32768 << 2) + bnec $3, $2, . + 4 + (32767 << 2) + bnec $3, $2, 1f + + blezc $2, ext + blezc $2, . + 4 + (-32768 << 2) + blezc $2, . + 4 + (32767 << 2) + blezc $2, 1f + bgezc $2, ext + bgezc $2, . + 4 + (-32768 << 2) + bgezc $2, . + 4 + (32767 << 2) + bgezc $2, 1f + bgec $2, $3, ext + bgec $2, $3, . + 4 + (-32768 << 2) + bgec $2, $3, . + 4 + (32767 << 2) + bgec $2, $3, 1f + bgec $3, $2, 1f + + bgtzc $2, ext + bgtzc $2, . + 4 + (-32768 << 2) + bgtzc $2, . + 4 + (32767 << 2) + bgtzc $2, 1f + bltzc $2, ext + bltzc $2, . + 4 + (-32768 << 2) + bltzc $2, . + 4 + (32767 << 2) + bltzc $2, 1f + bltc $2, $3, ext + bltc $2, $3, . + 4 + (-32768 << 2) + bltc $2, $3, . + 4 + (32767 << 2) + bltc $2, $3, 1f + bltc $3, $2, 1f + + blezalc $2, ext + blezalc $2, . + 4 + (-32768 << 2) + blezalc $2, . + 4 + (32767 << 2) + blezalc $2, 1f + bgezalc $2, ext + bgezalc $2, . + 4 + (-32768 << 2) + bgezalc $2, . + 4 + (32767 << 2) + bgezalc $2, 1f + bgeuc $2, $3, ext + bgeuc $2, $3, . + 4 + (-32768 << 2) + bgeuc $2, $3, . + 4 + (32767 << 2) + bgeuc $2, $3, 1f + bgeuc $3, $2, 1f + + bgtzalc $2, ext + bgtzalc $2, . + 4 + (-32768 << 2) + bgtzalc $2, . + 4 + (32767 << 2) + bgtzalc $2, 1f + bltzalc $2, ext + bltzalc $2, . + 4 + (-32768 << 2) + bltzalc $2, . + 4 + (32767 << 2) + bltzalc $2, 1f + bltuc $2, $3, ext + bltuc $2, $3, . + 4 + (-32768 << 2) + bltuc $2, $3, . + 4 + (32767 << 2) + bltuc $2, $3, 1f + bltuc $3, $2, 1f + + bc ext + bc . + 4 + (-33554432 << 2) + bc . + 4 + (33554431 << 2) + bc 1f + balc ext + balc . + 4 + (-33554432 << 2) + balc . + 4 + (33554431 << 2) + balc 1f + + beqzc $2, ext + beqzc $2, . + 4 + (-1048576 << 2) + beqzc $2, . + 4 + (1048575 << 2) + beqzc $2, 1f + jic $3,-32768 + jic $3,32767 + jrc $31 + + bnezc $2, ext + bnezc $2, . + 4 + (-1048576 << 2) + bnezc $2, . + 4 + (1048575 << 2) + bnezc $2, 1f + jialc $3,-32768 + jialc $3,32767 + + + aui $3, $2, 0xffff + + lapc $3, 1f + lapc $4, .+(-262144 << 2) + lapc $4, .+(262143 << 2) + addiupc $4, (-262144 << 2) + addiupc $4, (262143 << 2) + auipc $3, 0xffff + aluipc $3, 0xffff + lwpc $4, 1f + lwpc $4, .+(-262144 << 2) + lwpc $4, .+(262143 << 2) + lw $4, (-262144 << 2)($pc) + lw $4, (262143 << 2)($pc) +1: + nop + diff --git a/binutils-2.24/gas/testsuite/gas/mips/tmips16-e.d b/binutils-2.24/gas/testsuite/gas/mips/tmips16-e.d index ddd6aaa..708ff11 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/tmips16-e.d +++ b/binutils-2.24/gas/testsuite/gas/mips/tmips16-e.d @@ -15,7 +15,9 @@ SYMBOL TABLE: 0+0000004 l \.text 0+0000000 0xf0 \.L1.1 0+0000000 l d foo 0+0000000 (|foo) 0+0000000 l d \.reginfo 0+0000000 (|\.reginfo) +0+0000000 l d \.MIPS\.abiflags 0+0000000 (|\.MIPS\.abiflags) 0+0000000 l d \.(mdebug|pdr) 0+0000000 (|\.mdebug|\.pdr) +0+0000000 l d \.gnu\.attributes 0+0000000 (|\.gnu\.attributes) 0+0000000 \*UND\* 0+0000000 g1 @@ -34,6 +36,11 @@ Contents of section \.text: Contents of section \.reginfo: 0000 00010000 00000000 00000000 00000000 .* 0010 00000000 00000000 .* +Contents of section .MIPS.abiflags: + .* + .* Contents of section foo: 0000 00000000 00000008 00000000 00000003 .* 0010 00000000 00000008 00000000 00000000 .* +Contents of section .gnu.attributes: + .* diff --git a/binutils-2.24/gas/testsuite/gas/mips/tmips16-f.d b/binutils-2.24/gas/testsuite/gas/mips/tmips16-f.d index f865d1d..057122c 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/tmips16-f.d +++ b/binutils-2.24/gas/testsuite/gas/mips/tmips16-f.d @@ -14,7 +14,9 @@ SYMBOL TABLE: 0+0000002 l \.text 0+0000000 0xf0 l1 0+0000000 l d foo 0+0000000 (|foo) 0+0000000 l d \.reginfo 0+0000000 (|\.reginfo) +0+0000000 l d \.MIPS\.abiflags 0+0000000 (|\.MIPS\.abiflags) 0+0000000 l d \.(mdebug|pdr) 0+0000000 (|\.mdebug|\.pdr) +0+0000000 l d \.gnu\.attributes 0+0000000 (|\.gnu\.attributes) RELOCATION RECORDS FOR \[foo\]: @@ -27,5 +29,10 @@ Contents of section \.text: Contents of section \.reginfo: 0000 00010000 00000000 00000000 00000000 .* 0010 00000000 00000000 .* +Contents of section .MIPS.abiflags: + .* + .* Contents of section foo: 0000 00000003 00000000 00000000 00000000 .* +Contents of section .gnu.attributes: + .* diff --git a/binutils-2.24/gas/testsuite/gas/mips/tmipsel16-e.d b/binutils-2.24/gas/testsuite/gas/mips/tmipsel16-e.d index 0af3793..839446b 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/tmipsel16-e.d +++ b/binutils-2.24/gas/testsuite/gas/mips/tmipsel16-e.d @@ -15,7 +15,9 @@ SYMBOL TABLE: 0+0000004 l \.text 0+0000000 0xf0 \.L1.1 0+0000000 l d foo 0+0000000 (|foo) 0+0000000 l d \.reginfo 0+0000000 (|\.reginfo) +0+0000000 l d \.MIPS\.abiflags 0+0000000 (|\.MIPS\.abiflags) 0+0000000 l d \.(mdebug|pdr) 0+0000000 (|\.mdebug|\.pdr) +0+0000000 l d \.gnu\.attributes 0+0000000 (|\.gnu\.attributes) 0+0000000 \*UND\* 0+0000000 g1 @@ -34,6 +36,11 @@ Contents of section \.text: Contents of section \.reginfo: 0000 00000100 00000000 00000000 00000000 .* 0010 00000000 00000000 .* +Contents of section .MIPS.abiflags: + .* + .* Contents of section foo: 0000 00000000 08000000 00000000 03000000 .* 0010 00000000 08000000 00000000 00000000 .* +Contents of section .gnu.attributes: + .* diff --git a/binutils-2.24/gas/testsuite/gas/mips/tmipsel16-f.d b/binutils-2.24/gas/testsuite/gas/mips/tmipsel16-f.d index 5daa593..edc6068 100644 --- a/binutils-2.24/gas/testsuite/gas/mips/tmipsel16-f.d +++ b/binutils-2.24/gas/testsuite/gas/mips/tmipsel16-f.d @@ -14,7 +14,9 @@ SYMBOL TABLE: 0+0000002 l \.text 0+0000000 0xf0 l1 0+0000000 l d foo 0+0000000 (|foo) 0+0000000 l d \.reginfo 0+0000000 (\.reginfo) +0+0000000 l d \.MIPS\.abiflags 0+0000000 (\.MIPS\.abiflags) 0+0000000 l d \.(mdebug|pdr) 0+0000000 (\.mdebug|\.pdr) +0+0000000 l d \.gnu\.attributes 0+0000000 (\.gnu\.attributes) RELOCATION RECORDS FOR \[foo\]: @@ -27,5 +29,10 @@ Contents of section \.text: Contents of section \.reginfo: 0000 00000100 00000000 00000000 00000000 .* 0010 00000000 00000000 .* +Contents of section .MIPS.abiflags: + .* + .* Contents of section foo: 0000 03000000 00000000 00000000 00000000 .* +Contents of section .gnu.attributes: + .* diff --git a/binutils-2.24/gas/testsuite/gas/mips/xpa.d b/binutils-2.24/gas/testsuite/gas/mips/xpa.d new file mode 100644 index 0000000..f1047c9 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/xpa.d @@ -0,0 +1,24 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -Mxpa,cp0-names=mips32r2 +#name: XPA instructions +#as: -32 -mxpa + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 40420800 mfhc0 v0,c0_random +[0-9a-f]+ <[^>]*> 40428000 mfhc0 v0,c0_config +[0-9a-f]+ <[^>]*> 40420002 mfhc0 v0,c0_mvpconf0 +[0-9a-f]+ <[^>]*> 40420007 mfhc0 v0,\$0,7 +[0-9a-f]+ <[^>]*> 40c20800 mthc0 v0,c0_random +[0-9a-f]+ <[^>]*> 40c28000 mthc0 v0,c0_config +[0-9a-f]+ <[^>]*> 40c20002 mthc0 v0,c0_mvpconf0 +[0-9a-f]+ <[^>]*> 40c20007 mthc0 v0,\$0,7 +[0-9a-f]+ <[^>]*> 40620c00 mfhgc0 v0,c0_random +[0-9a-f]+ <[^>]*> 40628400 mfhgc0 v0,c0_config +[0-9a-f]+ <[^>]*> 40620402 mfhgc0 v0,c0_mvpconf0 +[0-9a-f]+ <[^>]*> 40620407 mfhgc0 v0,\$0,7 +[0-9a-f]+ <[^>]*> 40620e00 mthgc0 v0,c0_random +[0-9a-f]+ <[^>]*> 40628600 mthgc0 v0,c0_config +[0-9a-f]+ <[^>]*> 40620602 mthgc0 v0,c0_mvpconf0 +[0-9a-f]+ <[^>]*> 40620607 mthgc0 v0,\$0,7 + ... diff --git a/binutils-2.24/gas/testsuite/gas/mips/xpa.s b/binutils-2.24/gas/testsuite/gas/mips/xpa.s new file mode 100644 index 0000000..4d91f75 --- /dev/null +++ b/binutils-2.24/gas/testsuite/gas/mips/xpa.s @@ -0,0 +1,29 @@ + .text + .set noat + .set noreorder + .set nomacro +test_xpa: + + mfhc0 $2, $1 + mfhc0 $2, $16 + mfhc0 $2, $0, 2 + mfhc0 $2, $0, 7 + + mthc0 $2, $1 + mthc0 $2, $16 + mthc0 $2, $0, 2 + mthc0 $2, $0, 7 + + mfhgc0 $2, $1 + mfhgc0 $2, $16 + mfhgc0 $2, $0, 2 + mfhgc0 $2, $0, 7 + + mthgc0 $2, $1 + mthgc0 $2, $16 + mthgc0 $2, $0, 2 + mthgc0 $2, $0, 7 + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 2 + .space 8 diff --git a/binutils-2.24/include/ChangeLog b/binutils-2.24/include/ChangeLog index 17a62ba..6f099ad 100644 --- a/binutils-2.24/include/ChangeLog +++ b/binutils-2.24/include/ChangeLog @@ -1,3 +1,7 @@ +2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com> + + * opcode/mips.h (ASE_XPA): New define. + 2013-08-20 Alan Modra <amodra@gmail.com> * floatformat.h (floatformat_ibm_long_double): Delete. diff --git a/binutils-2.24/include/elf/ChangeLog b/binutils-2.24/include/elf/ChangeLog index cfc4895..6b90b78 100644 --- a/binutils-2.24/include/elf/ChangeLog +++ b/binutils-2.24/include/elf/ChangeLog @@ -1,3 +1,7 @@ +2014-02-06 Andrew Pinski <apinski@cavium.com> + + * mips.h (E_MIPS_MACH_OCTEON3): New machine flag. + 2013-11-17 H.J. Lu <hongjiu.lu@intel.com> * x86-64.h: Add R_X86_64_PC32_BND and R_X86_64_PLT32_BND. @@ -32,6 +36,11 @@ R_AARCH64_TLS_DTPMOD, R_AARCH64_TLS_DTPREL and R_AARCH64_TLS_TPREL with RELOC_MACROS_GEN_FUNC. +2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> + + * mips.h (enum): Add Tag_GNU_MIPS_ABI_MSA. + (enum): Add Val_GNU_MIPS_ABI_MSA_ANY and Val_GNU_MIPS_ABI_MSA_128. + 2013-09-17 Doug Gilmore <Doug.Gilmore@imgtec.com> * mips.h (EF_MIPS_FP64): New e_flags bit. diff --git a/binutils-2.24/include/elf/mips.h b/binutils-2.24/include/elf/mips.h index a26e3f4..cdde18b 100644 --- a/binutils-2.24/include/elf/mips.h +++ b/binutils-2.24/include/elf/mips.h @@ -89,7 +89,14 @@ START_RELOC_NUMBERS (elf_mips_reloc_type) RELOC_NUMBER (R_MIPS_TLS_TPREL_HI16, 49) RELOC_NUMBER (R_MIPS_TLS_TPREL_LO16, 50) RELOC_NUMBER (R_MIPS_GLOB_DAT, 51) - FAKE_RELOC (R_MIPS_max, 52) + /* Space to grow */ + RELOC_NUMBER (R_MIPS_PC21_S2, 60) + RELOC_NUMBER (R_MIPS_PC26_S2, 61) + RELOC_NUMBER (R_MIPS_PC18_S3, 62) + RELOC_NUMBER (R_MIPS_PC19_S2, 63) + RELOC_NUMBER (R_MIPS_PCHI16, 64) + RELOC_NUMBER (R_MIPS_PCLO16, 65) + FAKE_RELOC (R_MIPS_max, 66) /* These relocs are used for the mips16. */ FAKE_RELOC (R_MIPS16_min, 100) RELOC_NUMBER (R_MIPS16_26, 100) @@ -239,6 +246,12 @@ END_RELOC_NUMBERS (R_MIPS_maxext) /* -mips64r2 code. */ #define E_MIPS_ARCH_64R2 0x80000000 +/* -mips32r6 code. */ +#define E_MIPS_ARCH_32R6 0x90000000 + +/* -mips64r6 code. */ +#define E_MIPS_ARCH_64R6 0xa0000000 + /* The ABI of the file. Also see EF_MIPS_ABI2 above. */ #define EF_MIPS_ABI 0x0000F000 @@ -275,6 +288,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext) #define E_MIPS_MACH_OCTEON 0x008b0000 #define E_MIPS_MACH_XLR 0x008c0000 #define E_MIPS_MACH_OCTEON2 0x008d0000 +#define E_MIPS_MACH_OCTEON3 0x008e0000 #define E_MIPS_MACH_5400 0x00910000 #define E_MIPS_MACH_5900 0x00920000 #define E_MIPS_MACH_5500 0x00980000 @@ -429,6 +443,8 @@ END_RELOC_NUMBERS (R_MIPS_maxext) /* Runtime procedure descriptor table exception information (ucode) ??? */ #define SHT_MIPS_PDR_EXCEPTION 0x70000029 +/* ABI related flags section. */ +#define SHT_MIPS_ABIFLAGS 0x7000002a /* A section of type SHT_MIPS_LIBLIST contains an array of the following structure. The sh_link field is the section index of the @@ -594,6 +610,9 @@ extern void bfd_mips_elf32_swap_reginfo_out /* .MIPS.options section. */ #define PT_MIPS_OPTIONS 0x70000002 + +/* Records ABI related flags. */ +#define PT_MIPS_ABIFLAGS 0x70000003 /* Processor specific dynamic array tags. */ @@ -1049,6 +1068,58 @@ typedef struct bfd_vma ri_gp_value; } Elf64_Internal_RegInfo; +/* ABI Flags structure version 0. */ + +typedef struct +{ + /* Version of flags structure. */ + unsigned char version[2]; + /* The level of the ISA: 1-5, 32, 64. */ + unsigned char isa_level[1]; + /* The revision of ISA: 0 for MIPS V and below, 1-n otherwise. */ + unsigned char isa_rev[1]; + /* The size of general purpose registers. */ + unsigned char gpr_size[1]; + /* The size of co-processor 1 registers. */ + unsigned char cpr1_size[1]; + /* The size of co-processor 2 registers. */ + unsigned char cpr2_size[1]; + /* The floating-point ABI. */ + unsigned char fp_abi[1]; + /* Processor-specific extension. */ + unsigned char isa_ext[4]; + /* Mask of ASEs used. */ + unsigned char ases[4]; + /* Mask of general flags. */ + unsigned char flags1[4]; + unsigned char flags2[4]; +} Elf_External_ABIFlags_v0; + +typedef struct +{ + /* Version of flags structure. */ + unsigned short version; + /* The level of the ISA: 1-5, 32, 64. */ + unsigned char isa_level; + /* The revision of ISA: 0 for MIPS V and below, 1-n otherwise. */ + unsigned char isa_rev; + /* The size of general purpose registers. */ + unsigned char gpr_size; + /* The size of co-processor 1 registers. */ + unsigned char cpr1_size; + /* The size of co-processor 2 registers. */ + unsigned char cpr2_size; + /* The floating-point ABI. */ + unsigned char fp_abi; + /* Processor-specific extension. */ + unsigned long isa_ext; + /* Mask of ASEs used. */ + unsigned long ases; + /* Mask of general flags. */ + unsigned long flags1; + unsigned long flags2; +} Elf_Internal_ABIFlags_v0; + typedef struct { /* The hash value computed from the name of the corresponding @@ -1089,6 +1160,12 @@ extern void bfd_mips_elf64_swap_reginfo_in extern void bfd_mips_elf64_swap_reginfo_out (bfd *, const Elf64_Internal_RegInfo *, Elf64_External_RegInfo *); +/* MIPS ELF flags swapping routines. */ +extern void bfd_mips_elf_swap_abiflags_v0_in + (bfd *, const Elf_External_ABIFlags_v0 *, Elf_Internal_ABIFlags_v0 *); +extern void bfd_mips_elf_swap_abiflags_v0_out + (bfd *, const Elf_Internal_ABIFlags_v0 *, Elf_External_ABIFlags_v0 *); + /* Masks for the info work of an ODK_EXCEPTIONS descriptor. */ #define OEX_FPU_MIN 0x1f /* FPEs which must be enabled. */ #define OEX_FPU_MAX 0x1f00 /* FPEs which may be enabled. */ @@ -1126,6 +1203,55 @@ extern void bfd_mips_elf64_swap_reginfo_out /* Masks for the info word of an ODK_HWAND/ODK_HWOR descriptor. */ #define OHWA0_R4KEOP_CHECKED 0x00000001 #define OHWA0_R4KEOP_CLEAN 0x00000002 + +/* Values for the xxx_size bytes of an ABI flags structure. */ + +#define AFL_REG_NONE 0x00 /* No registers. */ +#define AFL_REG_32 0x01 /* 32-bit registers. */ +#define AFL_REG_64 0x02 /* 64-bit registers. */ +#define AFL_REG_128 0x03 /* 128-bit registers. */ + +/* Masks for the ases word of an ABI flags structure. */ + +#define AFL_ASE_DSP 0x00000001 /* DSP ASE. */ +#define AFL_ASE_DSPR2 0x00000002 /* DSP R2 ASE. */ +#define AFL_ASE_EVA 0x00000004 /* Enhanced VA Scheme. */ +#define AFL_ASE_MCU 0x00000008 /* MCU (MicroController) ASE. */ +#define AFL_ASE_MDMX 0x00000010 /* MDMX ASE. */ +#define AFL_ASE_MIPS3D 0x00000020 /* MIPS-3D ASE. */ +#define AFL_ASE_MT 0x00000040 /* MT ASE. */ +#define AFL_ASE_SMARTMIPS 0x00000080 /* SmartMIPS ASE. */ +#define AFL_ASE_VIRT 0x00000100 /* VZ ASE. */ +#define AFL_ASE_MSA 0x00000200 /* MSA ASE. */ +#define AFL_ASE_MIPS16 0x00000400 /* MIPS16 ASE. */ +#define AFL_ASE_MICROMIPS 0x00000800 /* MICROMIPS ASE. */ +#define AFL_ASE_XPA 0x00001000 /* XPA ASE. */ + +/* Values for the isa_ext word of an ABI flags structure. */ + +#define AFL_EXT_XLR 1 /* RMI Xlr instruction. */ +#define AFL_EXT_OCTEON2 2 /* Cavium Networks Octeon2. */ +#define AFL_EXT_OCTEONP 3 /* Cavium Networks OcteonP. */ +#define AFL_EXT_LOONGSON_3A 4 /* Loongson 3A. */ +#define AFL_EXT_OCTEON 5 /* Cavium Networks Octeon. */ +#define AFL_EXT_5900 6 /* MIPS R5900 instruction. */ +#define AFL_EXT_4650 7 /* MIPS R4650 instruction. */ +#define AFL_EXT_4010 8 /* LSI R4010 instruction. */ +#define AFL_EXT_4100 9 /* NEC VR4100 instruction. */ +#define AFL_EXT_3900 10 /* Toshiba R3900 instruction. */ +#define AFL_EXT_10000 11 /* MIPS R10000 instruction. */ +#define AFL_EXT_SB1 12 /* Broadcom SB-1 instruction. */ +#define AFL_EXT_4111 13 /* NEC VR4111/VR4181 instruction. */ +#define AFL_EXT_4120 14 /* NEC VR4120 instruction. */ +#define AFL_EXT_5400 15 /* NEC VR5400 instruction. */ +#define AFL_EXT_5500 16 /* NEC VR5500 instruction. */ +#define AFL_EXT_LOONGSON_2E 17 /* ST Microelectronics Loongson 2E. */ +#define AFL_EXT_LOONGSON_2F 18 /* ST Microelectronics Loongson 2F. */ + +/* Masks for the flags1 word of an ABI flags structure. */ +#define AFL_FLAGS1_ODDSPREG 1 /* Uses odd single-precision registers. */ + +extern unsigned int bfd_mips_isa_ext (bfd *); /* Object attribute tags. */ @@ -1135,6 +1261,9 @@ enum /* Floating-point ABI used by this object file. */ Tag_GNU_MIPS_ABI_FP = 4, + + /* MSA ABI used by this object file. */ + Tag_GNU_MIPS_ABI_MSA = 8, }; /* Object attribute values. */ @@ -1155,7 +1284,24 @@ enum Val_GNU_MIPS_ABI_FP_SOFT = 3, /* Using -mips32r2 -mfp64. */ - Val_GNU_MIPS_ABI_FP_64 = 4, + Val_GNU_MIPS_ABI_FP_OLD_64 = 4, + + /* Using -mfpxx */ + Val_GNU_MIPS_ABI_FP_XX = 5, + + /* Using -mips32r2 -mfp64. */ + Val_GNU_MIPS_ABI_FP_64 = 6, + + /* Using -mips32r2 -mfp64 -mno-odd-spreg. */ + Val_GNU_MIPS_ABI_FP_64A = 7, + + /* Values defined for Tag_GNU_MIPS_ABI_MSA. */ + + /* Not tagged or not using any ABIs affected by the differences. */ + Val_GNU_MIPS_ABI_MSA_ANY = 0, + + /* Using 128-bit MSA. */ + Val_GNU_MIPS_ABI_MSA_128 = 1, }; #endif /* _ELF_MIPS_H */ diff --git a/binutils-2.24/include/opcode/ChangeLog b/binutils-2.24/include/opcode/ChangeLog index b8a99f8..c3c1c3f 100644 --- a/binutils-2.24/include/opcode/ChangeLog +++ b/binutils-2.24/include/opcode/ChangeLog @@ -1,3 +1,36 @@ +2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com> + + * mips.h (INSN_ISA_MASK): Updated. + (INSN_ISA32R3): New define. + (INSN_ISA32R5): New define. + (INSN_ISA64R3): New define. + (INSN_ISA64R5): New define. + (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32 + INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered. + (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and + mips64r5. + (INSN_UPTO32R3): New define. + (INSN_UPTO32R5): New define. + (INSN_UPTO64R3): New define. + (INSN_UPTO64R5): New define. + (ISA_MIPS32R3): New define. + (ISA_MIPS32R5): New define. + (ISA_MIPS64R3): New define. + (ISA_MIPS64R5): New define. + (CPU_MIPS32R3): New define. + (CPU_MIPS32R5): New define. + (CPU_MIPS64R3): New define. + (CPU_MIPS64R5): New define. + +2014-05-01 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values. + +2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com> + + * mips.h: Updated description of +o, +u, +v and +w for MIPS and + microMIPS. + 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64.h (aarch64_pstatefields): Change element type to @@ -34,6 +67,19 @@ * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND. (enum aarch64_opnd): Add AARCH64_OPND_COND1. +2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> + + * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX. + (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL. + For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, + +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. + For MIPS, update extension character sequences after +. + (ASE_MSA): New define. + (ASE_MSA64): New define. + For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, + +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. + For microMIPS, update extension character sequences after +. + 2013-08-23 Yuri Chornoivan <yurchor@ukr.net> PR binutils/15834 diff --git a/binutils-2.24/include/opcode/mips.h b/binutils-2.24/include/opcode/mips.h index f21697e..41d042f 100644 --- a/binutils-2.24/include/opcode/mips.h +++ b/binutils-2.24/include/opcode/mips.h @@ -413,7 +413,20 @@ enum mips_operand_type { /* Like OP_VU0_SUFFIX, but used when the operand's value has already been set. Any suffix used here must match the previous value. */ - OP_VU0_MATCH_SUFFIX + OP_VU0_MATCH_SUFFIX, + + /* An index selected by an integer, e.g. [1]. */ + OP_IMM_INDEX, + + /* An index selected by a register, e.g. [$2]. */ + OP_REG_INDEX, + + /* The operand spans two 5-bit register fields, both of which must be set to + the source register. */ + OP_SAME_RS_RT, + + /* Described by mips_prev_operand. */ + OP_CHECK_PREV }; /* Enumerates the types of MIPS register. */ @@ -454,7 +467,13 @@ enum mips_reg_operand_type { OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R, - OP_REG_R5900_ACC + OP_REG_R5900_ACC, + + /* MSA registers $w0-$w31. */ + OP_REG_MSA, + + /* MSA control registers $0-$31. */ + OP_REG_MSA_CTRL }; /* Base class for all operands. */ @@ -543,6 +562,20 @@ struct mips_reg_operand const unsigned char *reg_map; }; +/* Describes an operand that which must match a condition based on the + previous operand. */ +struct mips_check_prev_operand +{ + struct mips_operand root; + + bfd_boolean check_less_than; + bfd_boolean check_greater_than; + bfd_boolean check_less_than_or_equal; + bfd_boolean check_greater_than_or_equal; + bfd_boolean check_not_equal; + bfd_boolean check_not_zero; +}; + /* Describes an operand that encodes a pair of registers. */ struct mips_reg_pair_operand { @@ -891,6 +924,54 @@ struct mips_opcode Enhanced VA Scheme: "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET) + MSA Extension: + "+d" 5-bit MSA register (FD) + "+e" 5-bit MSA register (FS) + "+h" 5-bit MSA register (FT) + "+k" 5-bit GPR at bit 6 + "+l" 5-bit MSA control register at bit 6 + "+n" 5-bit MSA control register at bit 11 + "+o" 4-bit vector element index at bit 16 + "+u" 3-bit vector element index at bit 16 + "+v" 2-bit vector element index at bit 16 + "+w" 1-bit vector element index at bit 16 + "+T" (-512 .. 511) << 0 at bit 16 + "+U" (-512 .. 511) << 1 at bit 16 + "+V" (-512 .. 511) << 2 at bit 16 + "+W" (-512 .. 511) << 3 at bit 16 + "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6 + "+!" 3 bit unsigned bit position at bit 16 + "+@" 4 bit unsigned bit position at bit 16 + "+#" 6 bit unsigned bit position at bit 16 + "+$" 5 bit unsigned immediate at bit 16 + "+%" 5 bit signed immediate at bit 16 + "+^" 10 bit signed immediate at bit 11 + "+&" 0 vector element index + "+*" 5-bit register vector element index at bit 16 + "+|" 8-bit mask at bit 16 + + MIPS R6: + "+:" 11-bit mask at bit 0 + "+'" 26 bit PC relative branch target address + "+"" 21 bit PC relative branch target address + "+;" 5 bit same register in both OP_*_RS and OP_*_RT + "+I" 2bit unsigned bit position at bit 6 + "+O" 3bit unsigned bit position at bit 6 + "+R" must be program counter + "-a" (-262144 .. 262143) << 2 at bit 0 + "-b" (-131072 .. 131071) << 3 at bit 0 + "-d" Same as destination register GP + "-s" 5 bit source register specifier (OP_*_RS) not $0 + "-t" 5 bit source register specifier (OP_*_RT) not $0 + "-u" 5 bit source register specifier (OP_*_RT) greater than OP_*_RS + "-v" 5 bit source register specifier (OP_*_RT) not $0 not OP_*_RS + "-w" 5 bit source register specifier (OP_*_RT) less than or equal to OP_*_RS + "-x" 5 bit source register specifier (OP_*_RT) greater than or + equal to OP_*_RS + "-y" 5 bit source register specifier (OP_*_RT) not $0 less than OP_*_RS + "-A" symbolic offset (-262144 .. 262143) << 2 at bit 0 + "-B" symbolic offset (-131072 .. 131071) << 3 at bit 0 + Other: "()" parens surrounding optional value "," separates operands @@ -898,15 +979,21 @@ struct mips_opcode Characters used so far, for quick reference when adding more: "1234567890" - "%[]<>(),+:'@!#$*&\~" + "%[]<>(),+-:'@!#$*&\~" "ABCDEFGHIJKLMNOPQRSTUVWXYZ" "abcdefghijklopqrstuvwxz" Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: "1234567890" - "ABCEFGHJKLMNPQSXZ" - "abcfgijmpqrstxyz" + "~!@#$%^&*|:'";" + "ABCEFGHIJKLMNOPQRSTUVWXZ" + "abcdefghijklmnopqrstuvwxyz" + + Extension character sequences used so far ("-" followed by the + following), for quick reference when adding more: + "AB" + "abdstuvwxy" */ /* These are the bits which may be set in the pinfo field of an @@ -934,8 +1021,8 @@ struct mips_opcode #define INSN_TLB 0x00000200 /* Reads coprocessor register other than floating point register. */ #define INSN_COP 0x00000400 -/* Instruction loads value from memory, requiring delay. */ -#define INSN_LOAD_MEMORY_DELAY 0x00000800 +/* Instruction loads value from memory. */ +#define INSN_LOAD_MEMORY 0x00000800 /* Instruction loads value from coprocessor, requiring delay. */ #define INSN_LOAD_COPROC_DELAY 0x00001000 /* Instruction has unconditional branch delay slot. */ @@ -973,6 +1060,8 @@ struct mips_opcode #define INSN_WRITE_GPR_24 0x10000000 /* A user-defined instruction. */ #define INSN_UDI 0x20000000 +/* Is mtc1, mfc1, swc1, lwc1. */ +#define INSN_FP_32_MOVE 0x40000000 /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ #define INSN_MACRO 0xffffffff @@ -1014,6 +1103,8 @@ struct mips_opcode #define INSN2_READ_GPR_16 0x00002000 /* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */ #define INSN2_VU0_CHANNEL_SUFFIX 0x00004000 +/* Instruction has a forbidden slot. */ +#define INSN2_FORBIDDEN_SLOT 0x00008000 /* Masks used to mark instructions to indicate which MIPS ISA level they were introduced in. INSN_ISA_MASK masks an enumeration that @@ -1021,7 +1112,7 @@ struct mips_opcode word constructed using these macros is a bitmask of the remaining INSN_* values below. */ -#define INSN_ISA_MASK 0x0000000ful +#define INSN_ISA_MASK 0x0000001ful /* We cannot start at zero due to ISA_UNKNOWN below. */ #define INSN_ISA1 1 @@ -1031,28 +1122,75 @@ struct mips_opcode #define INSN_ISA5 5 #define INSN_ISA32 6 #define INSN_ISA32R2 7 -#define INSN_ISA64 8 -#define INSN_ISA64R2 9 +#define INSN_ISA32R3 8 +#define INSN_ISA32R5 9 +#define INSN_ISA32R6 10 +#define INSN_ISA64 11 +#define INSN_ISA64R2 12 +#define INSN_ISA64R3 13 +#define INSN_ISA64R5 14 +#define INSN_ISA64R6 15 /* Below this point the INSN_* values correspond to combinations of ISAs. They are only for use in the opcodes table to indicate membership of a combination of ISAs that cannot be expressed using the usual inclusion ordering on the above INSN_* values. */ -#define INSN_ISA3_32 10 -#define INSN_ISA3_32R2 11 -#define INSN_ISA4_32 12 -#define INSN_ISA4_32R2 13 -#define INSN_ISA5_32R2 14 - -/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through - INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2, - this table describes whether at least one of the ISAs described by X - is/are implemented by ISA Y. (Think of Y as the ISA level supported by - a particular core and X as the ISA level(s) at which a certain instruction - is defined.) The ISA(s) described by X is/are implemented by Y iff - (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1 - is non-zero. */ -static const unsigned int mips_isa_table[] = - { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; +#define INSN_ISA3_32 16 +#define INSN_ISA3_32R2 17 +#define INSN_ISA4_32 18 +#define INSN_ISA4_32R2 19 +#define INSN_ISA5_32R2 20 + +/* The R6 definitions shown below state that they support all previous ISAs. + This is not actually true as some instructions are removed in R6. + The problem is that the removed instructions in R6 come from different + ISAs. One approach to solve this would be to describe in the membership + field of the opcode table the different ISAs an instruction belongs to. + This would require us to create a large amount of different ISA + combinations which is hard to manage. A cleaner approach (which is + implemented here) is to say that R6 is an extension of R5 and then to + deal with the removed instructions by adding instruction exclusions + for R6 in the opcode table. */ + +/* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X. */ + +#define ISAF(X) (1 << (INSN_ISA##X - 1)) +#define INSN_UPTO1 ISAF(1) +#define INSN_UPTO2 INSN_UPTO1 | ISAF(2) +#define INSN_UPTO3 INSN_UPTO2 | ISAF(3) | ISAF(3_32) | ISAF(3_32R2) +#define INSN_UPTO4 INSN_UPTO3 | ISAF(4) | ISAF(4_32) | ISAF(4_32R2) +#define INSN_UPTO5 INSN_UPTO4 | ISAF(5) | ISAF(5_32R2) +#define INSN_UPTO32 INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32) +#define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \ + | ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2) +#define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3) +#define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5) +#define INSN_UPTO32R6 INSN_UPTO32R5 | ISAF(32R6) +#define INSN_UPTO64 INSN_UPTO5 | ISAF(64) | ISAF(32) +#define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2) +#define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3) +#define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5) +#define INSN_UPTO64R6 INSN_UPTO64R5 | ISAF(64R6) | ISAF(32R6) + +/* The same information in table form: bit INSN_ISA<X> - 1 of index + INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X. */ +static const unsigned int mips_isa_table[] = { + INSN_UPTO1, + INSN_UPTO2, + INSN_UPTO3, + INSN_UPTO4, + INSN_UPTO5, + INSN_UPTO32, + INSN_UPTO32R2, + INSN_UPTO32R3, + INSN_UPTO32R5, + INSN_UPTO32R6, + INSN_UPTO64, + INSN_UPTO64R2, + INSN_UPTO64R3, + INSN_UPTO64R5, + INSN_UPTO64R6 +}; +#undef ISAF /* Masks used for Chip specific instructions. */ #define INSN_CHIP_MASK 0xc3ff0f20 @@ -1115,6 +1253,11 @@ static const unsigned int mips_isa_table[] = /* Virtualization ASE */ #define ASE_VIRT 0x00000200 #define ASE_VIRT64 0x00000400 +/* MSA Extension */ +#define ASE_MSA 0x00000800 +#define ASE_MSA64 0x00001000 +/* eXtended Physical Address (XPA) Extension. */ +#define ASE_XPA 0x00002000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ @@ -1129,8 +1272,14 @@ static const unsigned int mips_isa_table[] = #define ISA_MIPS64 INSN_ISA64 #define ISA_MIPS32R2 INSN_ISA32R2 +#define ISA_MIPS32R3 INSN_ISA32R3 +#define ISA_MIPS32R5 INSN_ISA32R5 #define ISA_MIPS64R2 INSN_ISA64R2 +#define ISA_MIPS64R3 INSN_ISA64R3 +#define ISA_MIPS64R5 INSN_ISA64R5 +#define ISA_MIPS32R6 INSN_ISA32R6 +#define ISA_MIPS64R6 INSN_ISA64R6 /* CPU defines, use instead of hardcoding processor number. Keep this in sync with bfd/archures.c in order for machine selection to work. */ @@ -1161,9 +1310,15 @@ static const unsigned int mips_isa_table[] = #define CPU_MIPS16 16 #define CPU_MIPS32 32 #define CPU_MIPS32R2 33 +#define CPU_MIPS32R3 34 +#define CPU_MIPS32R5 36 +#define CPU_MIPS32R6 37 #define CPU_MIPS5 5 #define CPU_MIPS64 64 #define CPU_MIPS64R2 65 +#define CPU_MIPS64R3 66 +#define CPU_MIPS64R5 68 +#define CPU_MIPS64R6 69 #define CPU_SB1 12310201 /* octal 'SB', 01. */ #define CPU_LOONGSON_2E 3001 #define CPU_LOONGSON_2F 3002 @@ -1239,6 +1394,13 @@ cpu_is_member (int cpu, unsigned int mask) case CPU_XLR: return (mask & INSN_XLR) != 0; + case CPU_MIPS32R6: + return (mask & INSN_ISA_MASK) == INSN_ISA32R6; + + case CPU_MIPS64R6: + return ((mask & INSN_ISA_MASK) == INSN_ISA32R6) + || ((mask & INSN_ISA_MASK) == INSN_ISA64R6); + default: return FALSE; } @@ -2044,6 +2206,33 @@ extern const int bfd_mips16_num_opcodes; microMIPS Enhanced VA Scheme: "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET) + MSA Extension: + "+d" 5-bit MSA register (FD) + "+e" 5-bit MSA register (FS) + "+h" 5-bit MSA register (FT) + "+k" 5-bit GPR at bit 6 + "+l" 5-bit MSA control register at bit 6 + "+n" 5-bit MSA control register at bit 11 + "+o" 4-bit vector element index at bit 16 + "+u" 3-bit vector element index at bit 16 + "+v" 2-bit vector element index at bit 16 + "+w" 1-bit vector element index at bit 16 + "+x" 5-bit shift amount at bit 16 + "+T" (-512 .. 511) << 0 at bit 16 + "+U" (-512 .. 511) << 1 at bit 16 + "+V" (-512 .. 511) << 2 at bit 16 + "+W" (-512 .. 511) << 3 at bit 16 + "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6 + "+!" 3 bit unsigned bit position at bit 16 + "+@" 4 bit unsigned bit position at bit 16 + "+#" 6 bit unsigned bit position at bit 16 + "+$" 5 bit unsigned immediate at bit 16 + "+%" 5 bit signed immediate at bit 16 + "+^" 10 bit signed immediate at bit 11 + "+&" 0 vector element index + "+*" 5-bit register vector element index at bit 16 + "+|" 8-bit mask at bit 16 + Other: "()" parens surrounding optional value "," separates operands @@ -2052,16 +2241,16 @@ extern const int bfd_mips16_num_opcodes; Characters used so far, for quick reference when adding more: "12345678 0" - "<>(),+.@\^|~" + "<>(),+-.@\^|~" "ABCDEFGHI KLMN RST V " "abcd f hijklmnopqrstuvw yz" Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: "" - "" - "ABCEFGH" - "ij" + "~!@#$%^&*|" + "ABCEFGHTUVW" + "dehijklnouvwx" Extension character sequences used so far ("m" followed by the following), for quick reference when adding more: @@ -2069,6 +2258,12 @@ extern const int bfd_mips16_num_opcodes; "" " BCDEFGHIJ LMNOPQ U WXYZ" " bcdefghij lmn pq st xyz" + + Extension character sequences used so far ("-" followed by the + following), for quick reference when adding more: + "" + "" + <none so far> */ extern const struct mips_operand *decode_micromips_operand (const char *); diff --git a/binutils-2.24/ld/ChangeLog b/binutils-2.24/ld/ChangeLog index 1687785..0422d81 100644 --- a/binutils-2.24/ld/ChangeLog +++ b/binutils-2.24/ld/ChangeLog @@ -1,3 +1,7 @@ +2014-04-16 Steve Ellcey <sellcey@mips.com> + + * emultempl/elf32.em: Include safe-ctype.h. + 2013-11-25 Yufeng Zhang <yufeng.zhang@arm.com> Backport from master diff --git a/binutils-2.24/ld/configure.tgt b/binutils-2.24/ld/configure.tgt index c50730b..714deab 100644 --- a/binutils-2.24/ld/configure.tgt +++ b/binutils-2.24/ld/configure.tgt @@ -454,7 +454,7 @@ mips*vr5000el-*-elf*) targ_emul=elf32l4300 ;; mips*vr5000-*-elf*) targ_emul=elf32b4300 ;; mips*el-sde-elf*) targ_emul=elf32ltsmip targ_extra_emuls="elf32btsmip elf32ltsmipn32 elf64ltsmip elf32btsmipn32 elf64btsmip" ;; -mips*-sde-elf* | mips*-mti-elf*) +mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) targ_emul=elf32btsmip targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;; mips64*el-ps2-elf*) targ_emul=elf32lr5900n32 @@ -471,6 +471,9 @@ mips*el-*-vxworks*) targ_emul=elf32elmipvxworks mips*-*-vxworks*) targ_emul=elf32ebmipvxworks targ_extra_emuls="elf32elmipvxworks" ;; mips*-*-windiss) targ_emul=elf32mipswindiss ;; +mips64*el-*android*) targ_emul=elf64ltsmip + targ_extra_emuls="elf64btsmip elf32ltsmipn32 elf32btsmipn32 elf32ltsmip elf32btsmip" + targ_extra_libpath=$targ_extra_emuls ;; mips64*el-*-linux-*) targ_emul=elf32ltsmipn32 targ_extra_emuls="elf32btsmipn32 elf32ltsmip elf32btsmip elf64ltsmip elf64btsmip" targ_extra_libpath=$targ_extra_emuls ;; diff --git a/binutils-2.24/ld/emulparams/elf32bmip.sh b/binutils-2.24/ld/emulparams/elf32bmip.sh index 2289685..c8ed5df 100644 --- a/binutils-2.24/ld/emulparams/elf32bmip.sh +++ b/binutils-2.24/ld/emulparams/elf32bmip.sh @@ -17,7 +17,8 @@ if test -z "${CREATE_SHLIB}"; then INITIAL_READONLY_SECTIONS=".interp ${RELOCATING-0} : { *(.interp) }" fi INITIAL_READONLY_SECTIONS="${INITIAL_READONLY_SECTIONS} - .reginfo ${RELOCATING-0} : { *(.reginfo) } + .MIPS.abiflags ${RELOCATING-0} : { *(.MIPS.abiflags) } + .reginfo ${RELOCATING-0} : { *(.reginfo) } " OTHER_TEXT_SECTIONS='*(.mips16.fn.*) *(.mips16.call.*)' # Unlike most targets, the MIPS backend puts all dynamic relocations diff --git a/binutils-2.24/ld/emulparams/elf32bmipn32-defs.sh b/binutils-2.24/ld/emulparams/elf32bmipn32-defs.sh index 514990b..723eac8 100644 --- a/binutils-2.24/ld/emulparams/elf32bmipn32-defs.sh +++ b/binutils-2.24/ld/emulparams/elf32bmipn32-defs.sh @@ -88,6 +88,7 @@ if test -z "${CREATE_SHLIB}"; then INITIAL_READONLY_SECTIONS=".interp ${RELOCATING-0} : { *(.interp) }" fi INITIAL_READONLY_SECTIONS="${INITIAL_READONLY_SECTIONS} + .MIPS.abiflags ${RELOCATING-0} : { *(.MIPS.abiflags) } .reginfo ${RELOCATING-0} : { *(.reginfo) }" # Discard any .MIPS.content* or .MIPS.events* sections. The linker # doesn't know how to adjust them. diff --git a/binutils-2.24/ld/emulparams/elf64bmip-defs.sh b/binutils-2.24/ld/emulparams/elf64bmip-defs.sh index 110f892..8a0522f 100644 --- a/binutils-2.24/ld/emulparams/elf64bmip-defs.sh +++ b/binutils-2.24/ld/emulparams/elf64bmip-defs.sh @@ -1,3 +1,6 @@ . ${srcdir}/emulparams/elf32bmipn32-defs.sh COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" -INITIAL_READONLY_SECTIONS=".MIPS.options : { *(.MIPS.options) }" +INITIAL_READONLY_SECTIONS=" + .MIPS.abiflags ${RELOCATING-0} : { *(.MIPS.abiflags) } + .MIPS.options : { *(.MIPS.options) } +" diff --git a/binutils-2.24/ld/emultempl/elf32.em b/binutils-2.24/ld/emultempl/elf32.em index 9a2fe89..7d5ef28 100644 --- a/binutils-2.24/ld/emultempl/elf32.em +++ b/binutils-2.24/ld/emultempl/elf32.em @@ -40,6 +40,7 @@ fragment <<EOF #include "sysdep.h" #include "bfd.h" #include "libiberty.h" +#include "safe-ctype.h" #include "filenames.h" #include "safe-ctype.h" #include "getopt.h" diff --git a/binutils-2.24/ld/ldmain.c b/binutils-2.24/ld/ldmain.c index 6a53667..0aca0c1 100644 --- a/binutils-2.24/ld/ldmain.c +++ b/binutils-2.24/ld/ldmain.c @@ -597,8 +597,10 @@ get_emulation (int argc, char **argv) || strcmp (argv[i], "-mips5") == 0 || strcmp (argv[i], "-mips32") == 0 || strcmp (argv[i], "-mips32r2") == 0 + || strcmp (argv[i], "-mips32r6") == 0 || strcmp (argv[i], "-mips64") == 0 - || strcmp (argv[i], "-mips64r2") == 0) + || strcmp (argv[i], "-mips64r2") == 0 + || strcmp (argv[i], "-mips64r6") == 0) { /* FIXME: The arguments -mips1, -mips2, -mips3, etc. are passed to the linker by some MIPS compilers. They diff --git a/binutils-2.24/ld/testsuite/ChangeLog b/binutils-2.24/ld/testsuite/ChangeLog index 342d5b2..963d096 100644 --- a/binutils-2.24/ld/testsuite/ChangeLog +++ b/binutils-2.24/ld/testsuite/ChangeLog @@ -1,3 +1,30 @@ +2014-05-28 Matthew Fortune <matthew.fortune@imgtec.com> + + * lib/ld-lib.exp: Add objcopy_objects command to run_dump_test. + This allows each input object to be optionally run through + objcopy before linking. + +2014-04-17 Kwok Cheung Yeung <kcy@codesourcery.com> + + * ld-mips-elf/elf-rel-xgot-n32.d: Update for new GOT layout. + * ld-mips-elf/elf-rel-xgot-n32-embed.d: Likewise. + * ld-mips-elf/elf-rel-xgot-n64.d: Likewise. + * ld-mips-elf/elf-rel-xgot-n64-embed.d: Likewise. + * ld-mips-elf/elf-rel-xgot-n64-linux.d: Likewise. + +2014-03-20 Richard Sandiford <rdsandiford@googlemail.com> + + * ld-elf/merge.d: Remove MIPS XFAIL. + +2014-02-18 Jack Carter <jack.carter@imgtec.com> + + * ld-mips-elf/pic-and-nonpic-3a.sd: Check DYNAMIC segment flags. + +2013-11-27 Matthew Fortune <matthew.fortune@imgtec.com> + + * ld-mips-elf/mips-elf.exp: Consider mips-mti-elf the same as + mips-sde-elf + 2013-11-19 Roland McGrath <mcgrathr@google.com> * ld-elf/ehdr_start-userdef.t: New file. @@ -75,6 +102,68 @@ * ld-x86-64/plt-nacl.pd: Update expected disassembly for PLT nop fix. * ld-x86-64/tlsdesc-nacl.pd: Likewise. +2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> + + * ld-mips-elf/attr-gnu-8-0.s, ld-mips-elf/attr-gnu-8-1.s, + ld-mips-elf/attr-gnu-8-2.s, + ld-mips-elf/attr-gnu-8-00.d, ld-mips-elf/attr-gnu-8-01.d, + ld-mips-elf/attr-gnu-8-02.d, ld-mips-elf/attr-gnu-8-10.d, + ld-mips-elf/attr-gnu-8-11.d, ld-mips-elf/attr-gnu-8-12.d, + ld-mips-elf/attr-gnu-8-20.d, ld-mips-elf/attr-gnu-8-21.d, + ld-mips-elf/attr-gnu-8-22.d: New. + * ld-mips-elf/mips-elf.exp: Run new tests. + +2013-10-13 Richard Sandiford <rdsandiford@googlemail.com> + + * lib/ld-lib.exp (default_ld_compile): Add a -I option for the source + directory. + * ld-mips-elf/compressed-plt-1.ld, ld-mips-elf/compressed-plt-1.s, + ld-mips-elf/compressed-plt-1-dyn.s, ld-mips-elf/compressed-plt-1a.s, + ld-mips-elf/compressed-plt-1b.s, ld-mips-elf/compressed-plt-1c.s, + ld-mips-elf/compressed-plt-1d.s, ld-mips-elf/compressed-plt-1e.s, + ld-mips-elf/compressed-plt-1-o32-se.rd, + ld-mips-elf/compressed-plt-1-o32-se.od, + ld-mips-elf/compressed-plt-1-o32-mips16-only.rd, + ld-mips-elf/compressed-plt-1-o32-mips16-only.od, + ld-mips-elf/compressed-plt-1-o32-umips-only.rd, + ld-mips-elf/compressed-plt-1-o32-umips-only.od, + ld-mips-elf/compressed-plt-1-o32-mips16.rd, + ld-mips-elf/compressed-plt-1-o32-mips16.od, + ld-mips-elf/compressed-plt-1-o32-mips16-got.rd, + ld-mips-elf/compressed-plt-1-o32-mips16-got.od, + ld-mips-elf/compressed-plt-1-o32-mips16-word.rd, + ld-mips-elf/compressed-plt-1-o32-mips16-word.od, + ld-mips-elf/compressed-plt-1-o32-umips.rd, + ld-mips-elf/compressed-plt-1-o32-umips.od, + ld-mips-elf/compressed-plt-1-o32-umips-got.rd, + ld-mips-elf/compressed-plt-1-o32-umips-got.od, + ld-mips-elf/compressed-plt-1-o32-umips-word.rd, + ld-mips-elf/compressed-plt-1-o32-umips-word.od, + ld-mips-elf/compressed-plt-1-n32-mips16.rd, + ld-mips-elf/compressed-plt-1-n32-mips16.od, + ld-mips-elf/compressed-plt-1-n32-umips.rd, + ld-mips-elf/compressed-plt-1-n32-umips.od: New tests. + * ld-mips-elf/mips-elf.exp: Run them. + +2013-10-13 Richard Sandiford <rdsandiford@googlemail.com> + + * ld-mips-elf/pic-and-nonpic-6-n32.ad, + ld-mips-elf/pic-and-nonpic-6-n32.dd, + ld-mips-elf/pic-and-nonpic-6-n32.gd, + ld-mips-elf/pic-and-nonpic-6-n32.nd, + ld-mips-elf/pic-and-nonpic-6-n32.rd, + ld-mips-elf/pic-and-nonpic-6-n64.ad, + ld-mips-elf/pic-and-nonpic-6-n64.dd, + ld-mips-elf/pic-and-nonpic-6-n64.gd, + ld-mips-elf/pic-and-nonpic-6-n64.nd, + ld-mips-elf/pic-and-nonpic-6-n64.rd, + ld-mips-elf/pic-and-nonpic-6-o32.ad, + ld-mips-elf/pic-and-nonpic-6-o32.dd, + ld-mips-elf/pic-and-nonpic-6-o32.gd, + ld-mips-elf/pic-and-nonpic-6-o32.nd, + ld-mips-elf/pic-and-nonpic-6-o32.rd: Fix symbol value of extf4. + No longer expect extf3, extf4 and extd2 to be in the global GOT. + 2013-10-05 Gregory Fong <gregory.0xf0@gmail.com> * ld-mips-elf/eh-frame5.d, ld-mips-elf/jalx-2.dd, diff --git a/binutils-2.24/ld/testsuite/ld-elf/group.ld b/binutils-2.24/ld/testsuite/ld-elf/group.ld index 123ab26..f8e50c3 100644 --- a/binutils-2.24/ld/testsuite/ld-elf/group.ld +++ b/binutils-2.24/ld/testsuite/ld-elf/group.ld @@ -2,5 +2,5 @@ SECTIONS { . = 0x1000; .text : { *(.text) *(.rodata.brlt) } - /DISCARD/ : { *(.dropme) *(.reginfo) } + /DISCARD/ : { *(.dropme) *(.reginfo) *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-elf/merge.d b/binutils-2.24/ld/testsuite/ld-elf/merge.d index c50de10..450ee07 100644 --- a/binutils-2.24/ld/testsuite/ld-elf/merge.d +++ b/binutils-2.24/ld/testsuite/ld-elf/merge.d @@ -4,7 +4,7 @@ #xfail: "arc-*-*" "avr-*-*" "bfin-*-*" "cr16-*-*" "cris*-*-*" "crx-*-*" "d10v-*-*" "d30v-*-*" #xfail: "dlx-*-*" "fr30-*-*" "frv-*-*" "hppa*64*-*-*" "h8300-*-*" "score-*-*" #xfail: "i370-*-*" "i860-*-*" "i960-*-*" "ip2k-*-*" "iq2000-*-*" "lm32-*-*" -#xfail: "mcore-*-*" "mn102*-*-*" "mips*-*-*" "ms1-*-*" "mep-*-*" +#xfail: "mcore-*-*" "mn102*-*-*" "ms1-*-*" "mep-*-*" #xfail: "or32-*-*" "pj-*-*" "sparc*-*-*" "tic6x-*-*" "vax-*-*" "xstormy16-*-*" #xfail: "xtensa*-*-*" "metag-*-*" diff --git a/binutils-2.24/ld/testsuite/ld-elf/orphan-region.ld b/binutils-2.24/ld/testsuite/ld-elf/orphan-region.ld index b7dfdba..2abf8bc 100644 --- a/binutils-2.24/ld/testsuite/ld-elf/orphan-region.ld +++ b/binutils-2.24/ld/testsuite/ld-elf/orphan-region.ld @@ -7,5 +7,5 @@ SECTIONS { .text : ALIGN (4) { *(.text) } > region .rodata : ALIGN (4) { *(.rodata) } > region - /DISCARD/ : { *(.reginfo) *(.trampolines) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) *(.trampolines) } } diff --git a/binutils-2.24/ld/testsuite/ld-elf/orphan.ld b/binutils-2.24/ld/testsuite/ld-elf/orphan.ld index d23222b..44eb7eb 100644 --- a/binutils-2.24/ld/testsuite/ld-elf/orphan.ld +++ b/binutils-2.24/ld/testsuite/ld-elf/orphan.ld @@ -4,5 +4,5 @@ SECTIONS .data : { *(.data) } .bss : { *(.bss) *(COMMON) } .note : { *(.note) } - /DISCARD/ : { *(.reginfo) *(.trampolines) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) *(.trampolines) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip1-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip1-ph.d new file mode 100644 index 0000000..3af3433 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip1-ph.d @@ -0,0 +1,13 @@ +#source: jr.s -mips32r2 -32 -mfp32 -EB RUN_OBJCOPY +#objcopy_objects: -R .MIPS.abiflags +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +#... +!0x70000003.* +#... +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip2-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip2-ph.d new file mode 100644 index 0000000..5c36ce0 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip2-ph.d @@ -0,0 +1,29 @@ +#source: jr.s -mips32r2 -32 -mfpxx -EB +#source: jr.s -march=octeon -32 -mfp64 -EB RUN_OBJCOPY +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-x +private flags = 808b1100: \[abi=O32\] \[mips64r2\] \[32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: Cavium Networks Octeon +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip3-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip3-ph.d new file mode 100644 index 0000000..3ad1143 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip3-ph.d @@ -0,0 +1,29 @@ +#source: jr.s -march=octeon -32 -mfp64 -EB RUN_OBJCOPY +#source: jr.s -mips32r2 -32 -mfpxx -EB +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-x +private flags = 808b1100: \[abi=O32\] \[mips64r2\] \[32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: Cavium Networks Octeon +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip4-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip4-ph.d new file mode 100644 index 0000000..d109d95 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip4-ph.d @@ -0,0 +1,33 @@ +#source: jr.s -march=octeon -32 -mfp64 -EB -mdmx RUN_OBJCOPY +#source: jr.s -mips32r2 -32 -mfpxx -EB +#source: jr.s -mips32r2 -32 -mfp64 -mmsa -EB +#source: jr.s -mips2 -32 -mfpxx -mips16 -EB RUN_OBJCOPY +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x00000... memsz 0x00000... flags r-x +private flags = 8c8b1100: \[abi=O32\] \[mips64r2\] \[mdmx\] \[mips16\] \[32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r2 +GPR size: 32 +CPR1 size: 128 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: Cavium Networks Octeon +ASEs: + MDMX ASE + MSA ASE + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip5-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip5-ph.d new file mode 100644 index 0000000..cfbda75 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip5-ph.d @@ -0,0 +1,33 @@ +#source: jr.s -mips32r2 -32 -mfpxx -EB +#source: jr.s -mips32r2 -32 -mfp64 -mmsa -EB +#source: jr.s -march=octeon -32 -mfp64 -EB -mdmx RUN_OBJCOPY +#source: jr.s -mips2 -32 -mips16 -mfpxx -EB RUN_OBJCOPY +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x00000... memsz 0x00000... flags r-x +private flags = 8c8b1100: \[abi=O32\] \[mips64r2\] \[mdmx\] \[mips16\] \[32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r2 +GPR size: 32 +CPR1 size: 128 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: Cavium Networks Octeon +ASEs: + MDMX ASE + MSA ASE + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip6-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip6-ph.d new file mode 100644 index 0000000..147df83 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip6-ph.d @@ -0,0 +1,29 @@ +#source: jr.s -mips32r3 -32 -EB RUN_OBJCOPY +#source: jr.s -mips32r2 -32 -EB +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-x +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip7-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip7-ph.d new file mode 100644 index 0000000..7ce3175 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip7-ph.d @@ -0,0 +1,29 @@ +#source: jr.s -mips32r3 -32 -EB +#source: jr.s -mips32r2 -32 -EB RUN_OBJCOPY +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-x +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r3 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip8-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip8-ph.d new file mode 100644 index 0000000..42fb0c3 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip8-ph.d @@ -0,0 +1,29 @@ +#source: jr.s -mips32r2 -32 -mfpxx -EB +#source: jr.s -mips32r2 -32 -mfp64 -EB RUN_OBJCOPY +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .gnu.attributes +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-x +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n32-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n32-ph.d new file mode 100644 index 0000000..9f424e4 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n32-ph.d @@ -0,0 +1,26 @@ +#source: attr-gnu-4-0.s -mips3 -n32 -EB +#ld: -melf32btsmipn32 -e 0 +#objdump: -p + +[^:]*: file format elf32-ntradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x100000.. paddr 0x100000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x10000000 paddr 0x10000000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 20000020: \[abi=N32\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard or soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n64-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n64-ph.d new file mode 100644 index 0000000..124f81c --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n64-ph.d @@ -0,0 +1,25 @@ +#source: attr-gnu-4-0.s -mips3 -64 -EB +#ld: -melf64btsmip -e 0 +#objdump: -p + +[^:]*: file format elf64-tradbigmips + +Program Header: +0x70000003 off 0x00000000000000b0 vaddr 0x00000001200000b0 paddr 0x00000001200000b0 align 2\*\*3 + filesz 0x0000000000000018 memsz 0x0000000000000018 flags r-- + LOAD off 0x0000000000000000 vaddr 0x0000000120000000 paddr 0x0000000120000000 align 2\*\*16 + filesz 0x00000000000000.. memsz 0x00000000000000.. flags r-- +private flags = 20000000: \[abi=64\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard or soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-ph.d new file mode 100644 index 0000000..ee50709 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-ph.d @@ -0,0 +1,26 @@ +#source: attr-gnu-4-0.s -mips32r2 -32 -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: .* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard or soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-00.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-00.d index 32bc319..d460449 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-00.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-00.d @@ -2,5 +2,16 @@ #source: attr-gnu-4-0.s #ld: -r #readelf: -A -#target: mips*-*-* +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard or soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-01.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-01.d index 7a5c7a1..168b7aa 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-01.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-01.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-1.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-02.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-02.d index f29d5d5..ec58964 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-02.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-02.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-2.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-03.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-03.d index e571e13..c254a2d 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-03.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-03.d @@ -1,9 +1,22 @@ #source: attr-gnu-4-0.s +#as: -msoft-float #source: attr-gnu-4-3.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-04.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-04.d index f8dee5c..628daee 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-04.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-04.d @@ -1,9 +1,5 @@ #source: attr-gnu-4-0.s -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #ld: -r -#readelf: -A -#target: mips*-*-* - -Attribute Section: gnu -File Attributes - Tag_GNU_MIPS_ABI_FP: Hard float \(MIPS32r2 64-bit FPU\) +#error: \A[^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-05.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-05.d index 6856df0..c3d9193 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-05.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-05.d @@ -1,9 +1,21 @@ -#source: attr-gnu-4-0.s -#source: attr-gnu-4-5.s -#ld: -r +#source: attr-gnu-4-0.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes - Tag_GNU_MIPS_ABI_FP: \?\?\? \(5\) + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-06.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-06.d new file mode 100644 index 0000000..5c640ff --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-06.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-0.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-07.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-07.d new file mode 100644 index 0000000..108e5a4 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-07.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-0.s +#source: attr-gnu-4-7.s -W +#ld: -r +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: \?\?\? \(7\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: \?\?\? \(7\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n32-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n32-ph.d new file mode 100644 index 0000000..7e502ed --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n32-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips3 -n32 -EB +#ld: -melf32btsmipn32 -e 0 +#objdump: -p + +[^:]*: file format elf32-ntradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x100000.. paddr 0x100000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x10000000 paddr 0x10000000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 20000020: \[abi=N32\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n64-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n64-ph.d new file mode 100644 index 0000000..6c5878a --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n64-ph.d @@ -0,0 +1,25 @@ +#source: empty.s -mips3 -64 -EB +#ld: -melf64btsmip -e 0 +#objdump: -p + +[^:]*: file format elf64-tradbigmips + +Program Header: +0x70000003 off 0x00000000000000b0 vaddr 0x00000001200000b0 paddr 0x00000001200000b0 align 2\*\*3 + filesz 0x0000000000000018 memsz 0x0000000000000018 flags r-- + LOAD off 0x0000000000000000 vaddr 0x0000000120000000 paddr 0x0000000120000000 align 2\*\*16 + filesz 0x00000000000000.. memsz 0x00000000000000.. flags r-- +private flags = 20000000: \[abi=64\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-ph.d new file mode 100644 index 0000000..3b517b2 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips32r2 -32 -mfp32 -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d index 7661963..3ecf33b 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d @@ -1,9 +1,42 @@ -#source: attr-gnu-4-1.s -#source: attr-gnu-4-0.s -#ld: -r -#readelf: -A -#target: mips*-*-* +#source: attr-gnu-4-1.s -EB +#source: attr-gnu-4-0.s -EB +#ld: -r -melf32btsmip +#readelf: -hA + +ELF Header: + Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00.* + Class: ELF32 + Data: 2's complement, big endian + Version: 1 \(current\) + OS/ABI: UNIX - System V + ABI Version: 0 + Type: REL \(Relocatable file\) + Machine: MIPS R3000 + Version: 0x1 + Entry point address: 0x0 + Start of program headers: 0 \(bytes into file\) + Start of section headers: ... \(bytes into file\) + Flags: .* + Size of this header: 52 \(bytes\) + Size of program headers: 0 \(bytes\) + Number of program headers: 0 + Size of section headers: 40 \(bytes\) + Number of section headers: 11 + Section header string table index: 8 Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-11.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-11.d index f70306b..f546c0a 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-11.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-11.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-1.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-12.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-12.d index c0eace6..b1b0760 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-12.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-12.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-2.s #ld: -r #warning: Warning: .* uses -mdouble-float \(set by .*\), .* uses -msingle-float -#target: mips*-*-* diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-13.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-13.d index cb30f7a..c9bf544 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-13.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-13.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-3.s #ld: -r #warning: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float -#target: mips*-*-* diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-14.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-14.d index bde387b..58cfd24 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-14.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-14.d @@ -1,5 +1,6 @@ #source: attr-gnu-4-1.s -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #ld: -r -#warning: Warning: .* uses -mdouble-float \(set by .*\), .* uses -mips32r2 -mfp64 -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -mdouble-float \(set by .*\), .* uses -mips32r2 -mfp64 \(12 callee-saved\)\n +#error: [^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-15.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-15.d index b19645f..4f4cd00 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-15.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-15.d @@ -1,10 +1,21 @@ -#source: attr-gnu-4-1.s -#source: attr-gnu-4-5.s -#ld: -r +#source: attr-gnu-4-1.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip #readelf: -A -#warning: Warning: .* uses -mdouble-float \(set by .*\), .* uses unknown floating point ABI 5 -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-16.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-16.d new file mode 100644 index 0000000..430ab91 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-16.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-1.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A +#warning: Warning: .* uses -mdouble-float \(set by .*\), .* uses -mgp32 -mfp64 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-17.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-17.d new file mode 100644 index 0000000..6d675ac --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-17.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-1.s +#source: attr-gnu-4-7.s -W +#ld: -r +#readelf: -A +#warning: Warning: .* uses -mdouble-float \(set by .*\), .* uses unknown floating point ABI 7 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n32-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n32-ph.d new file mode 100644 index 0000000..57b8653 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n32-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips3 -n32 -msingle-float -EB +#ld: -melf32btsmipn32 -e 0 +#objdump: -p + +[^:]*: file format elf32-ntradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x100000.. paddr 0x100000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x10000000 paddr 0x10000000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 20000020: \[abi=N32\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n64-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n64-ph.d new file mode 100644 index 0000000..51a84db --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n64-ph.d @@ -0,0 +1,25 @@ +#source: empty.s -mips3 -64 -msingle-float -EB +#ld: -melf64btsmip -e 0 +#objdump: -p + +[^:]*: file format elf64-tradbigmips + +Program Header: +0x70000003 off 0x00000000000000b0 vaddr 0x00000001200000b0 paddr 0x00000001200000b0 align 2\*\*3 + filesz 0x0000000000000018 memsz 0x0000000000000018 flags r-- + LOAD off 0x0000000000000000 vaddr 0x0000000120000000 paddr 0x0000000120000000 align 2\*\*16 + filesz 0x00000000000000.. memsz 0x00000000000000.. flags r-- +private flags = 20000000: \[abi=64\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-ph.d new file mode 100644 index 0000000..dcdff3e --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips32r2 -32 -msingle-float -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2.s b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2.s index 54ebf4e..4021bed 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2.s +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2.s @@ -1 +1,2 @@ +.module singlefloat .gnu_attribute 4,2 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-20.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-20.d index 3620069..ab879e7 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-20.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-20.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-0.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-21.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-21.d index 68a006f..0081c72 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-21.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-21.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-1.s #ld: -r #warning: Warning: .* uses -msingle-float \(set by .*\), .* uses -mdouble-float -#target: mips*-*-* diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-22.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-22.d index 63edea9..051c96d 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-22.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-22.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-2.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-23.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-23.d index e16226f..0b8a6fc 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-23.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-23.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-3.s #ld: -r #warning: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float -#target: mips*-*-* diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-24.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-24.d index c31bb64..e48e5bb 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-24.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-24.d @@ -1,5 +1,6 @@ #source: attr-gnu-4-2.s -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #ld: -r -#warning: Warning: .* uses -msingle-float \(set by .*\), .* uses -mips32r2 -mfp64 -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -msingle-float \(set by .*\), .* uses -mips32r2 -mfp64 \(12 callee-saved\)\n +#error: [^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-25.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-25.d index b5456ab..cc0451e 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-25.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-25.d @@ -1,10 +1,22 @@ -#source: attr-gnu-4-2.s -#source: attr-gnu-4-5.s -#ld: -r +#source: attr-gnu-4-2.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip #readelf: -A -#warning: Warning: .* uses -msingle-float \(set by .*\), .* uses unknown floating point ABI 5 -#target: mips*-*-* +#warning: Warning: .* uses -msingle-float \(set by .*\), .* uses -mfpxx Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-26.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-26.d new file mode 100644 index 0000000..ec5d1c3 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-26.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-2.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A +#warning: Warning: .* uses -msingle-float \(set by .*\), .* uses -mgp32 -mfp64 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-27.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-27.d new file mode 100644 index 0000000..8756697 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-27.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-2.s +#source: attr-gnu-4-7.s -W +#ld: -r +#readelf: -A +#warning: Warning: .* uses -msingle-float \(set by .*\), .* uses unknown floating point ABI 7 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n32-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n32-ph.d new file mode 100644 index 0000000..57b8653 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n32-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips3 -n32 -msingle-float -EB +#ld: -melf32btsmipn32 -e 0 +#objdump: -p + +[^:]*: file format elf32-ntradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x100000.. paddr 0x100000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x10000000 paddr 0x10000000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 20000020: \[abi=N32\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n64-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n64-ph.d new file mode 100644 index 0000000..0252ac5 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n64-ph.d @@ -0,0 +1,25 @@ +#source: empty.s -mips3 -64 -msoft-float -EB +#ld: -melf64btsmip -e 0 +#objdump: -p + +[^:]*: file format elf64-tradbigmips + +Program Header: +0x70000003 off 0x00000000000000b0 vaddr 0x00000001200000b0 paddr 0x00000001200000b0 align 2\*\*3 + filesz 0x0000000000000018 memsz 0x0000000000000018 flags r-- + LOAD off 0x0000000000000000 vaddr 0x0000000120000000 paddr 0x0000000120000000 align 2\*\*16 + filesz 0x00000000000000.. memsz 0x00000000000000.. flags r-- +private flags = 20000000: \[abi=64\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 0 +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-ph.d new file mode 100644 index 0000000..5b220d1 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips32r2 -32 -msoft-float -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 0 +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3.s b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3.s index 32e5f5d..0ba0b80 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3.s +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3.s @@ -1 +1,2 @@ +.module softfloat .gnu_attribute 4,3 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-30.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-30.d index cdc108e..ecf319b 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-30.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-30.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-0.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-31.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-31.d index b749e82..4fcf76f 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-31.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-31.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-1.s #ld: -r #warning: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float -#target: mips*-*-* diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-32.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-32.d index d0fd7bc..0d663c2 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-32.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-32.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-2.s #ld: -r #warning: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float -#target: mips*-*-* diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-33.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-33.d index 39eebb3..b543942 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-33.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-33.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-3.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-34.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-34.d index be24523..314515a 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-34.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-34.d @@ -1,5 +1,6 @@ #source: attr-gnu-4-3.s -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #ld: -r -#warning: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float\n +#error: [^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-35.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-35.d index bcb1e02..f54b800 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-35.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-35.d @@ -1,10 +1,22 @@ -#source: attr-gnu-4-3.s -#source: attr-gnu-4-5.s -#ld: -r +#source: attr-gnu-4-3.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip #readelf: -A -#warning: Warning: .* uses -msoft-float \(set by .*\), .* uses unknown floating point ABI 5 -#target: mips*-*-* +#warning: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-36.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-36.d new file mode 100644 index 0000000..521af48 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-36.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-3.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A +#warning: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-37.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-37.d new file mode 100644 index 0000000..7697607 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-37.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-3.s +#source: attr-gnu-4-7.s -W +#ld: -r +#readelf: -A +#warning: Warning: .* uses -msoft-float \(set by .*\), .* uses unknown floating point ABI 7 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-4-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-4-ph.d new file mode 100644 index 0000000..2551060 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-4-ph.d @@ -0,0 +1,26 @@ +#source: attr-gnu-4-4.s -mips32r2 -32 -EB -W +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001200: \[abi=O32\] \[mips32r2\] \[old fp64\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(MIPS32r2 64-bit FPU 12 callee-saved\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-40.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-40.d index 27d4571..6aa22b9 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-40.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-40.d @@ -1,9 +1,5 @@ -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #source: attr-gnu-4-0.s #ld: -r -#readelf: -A -#target: mips*-*-* - -Attribute Section: gnu -File Attributes - Tag_GNU_MIPS_ABI_FP: Hard float \(MIPS32r2 64-bit FPU\) +#error: \A[^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-41.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-41.d index b652983..7c61365 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-41.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-41.d @@ -1,5 +1,6 @@ -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #source: attr-gnu-4-1.s #ld: -r -#warning: Warning: .* uses -mips32r2 -mfp64 \(set by .*\), .* uses -mdouble-float -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -mips32r2 -mfp64 \(12 callee-saved\) \(set by .*\), .* uses -mdouble-float\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-42.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-42.d index a1b79ea..dad0421 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-42.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-42.d @@ -1,5 +1,6 @@ -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #source: attr-gnu-4-2.s #ld: -r -#warning: Warning: .* uses -mips32r2 -mfp64 \(set by .*\), .* uses -msingle-float -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -mips32r2 -mfp64 \(12 callee-saved\) \(set by .*\), .* uses -msingle-float\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-43.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-43.d index 23f40c6..f30c18e 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-43.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-43.d @@ -1,5 +1,6 @@ -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #source: attr-gnu-4-3.s #ld: -r -#warning: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-44.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-44.d index 68b03a0..f870c8a 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-44.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-44.d @@ -1,9 +1,21 @@ -#source: attr-gnu-4-4.s -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W +#source: attr-gnu-4-4.s -W #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes - Tag_GNU_MIPS_ABI_FP: Hard float \(MIPS32r2 64-bit FPU\) + Tag_GNU_MIPS_ABI_FP: Hard float \(MIPS32r2 64-bit FPU 12 callee-saved\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(MIPS32r2 64-bit FPU 12 callee-saved\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-45.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-45.d index 0d1b079..d21e66f 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-45.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-45.d @@ -1,10 +1,6 @@ -#source: attr-gnu-4-4.s -#source: attr-gnu-4-5.s -#ld: -r -#readelf: -A -#warning: Warning: .* uses -mips32r2 -mfp64 \(set by .*\), .* uses unknown floating point ABI 5 -#target: mips*-*-* - -Attribute Section: gnu -File Attributes - Tag_GNU_MIPS_ABI_FP: Hard float \(MIPS32r2 64-bit FPU\) +#source: attr-gnu-4-4.s -W -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip +#error: \A[^\n]*: Warning: .* uses -mips32r2 -mfp64 \(12 callee-saved\) \(set by .*\), .* uses -mfpxx\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-46.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-46.d new file mode 100644 index 0000000..fb8baf8 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-46.d @@ -0,0 +1,6 @@ +#source: attr-gnu-4-4.s -W -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#error: \A[^\n]*: Warning: .* uses -mips32r2 -mfp64 \(12 callee-saved\) \(set by .*\), .* uses -mgp32 -mfp64\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-47.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-47.d new file mode 100644 index 0000000..aa455ff --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-47.d @@ -0,0 +1,6 @@ +#source: attr-gnu-4-4.s -W +#source: attr-gnu-4-7.s -W +#ld: -r +#error: \A[^\n]*: Warning: .* uses -mips32r2 -mfp64 \(12 callee-saved\) \(set by .*\), .* uses unknown floating point ABI 7\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-5-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-5-ph.d new file mode 100644 index 0000000..dd4c1ef --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-5-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips32r2 -32 -mfpxx -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-5.s b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-5.s index b21ec3b..06f6c6f 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-5.s +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-5.s @@ -1 +1,3 @@ +.module mips32r2 +.module fp=xx .gnu_attribute 4,5 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-50.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-50.d new file mode 100644 index 0000000..37a43f9 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-50.d @@ -0,0 +1,41 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-0.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -hA + +ELF Header: + Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00.* + Class: ELF32 + Data: 2's complement, big endian + Version: 1 \(current\) + OS/ABI: UNIX - System V + ABI Version: 0 + Type: REL \(Relocatable file\) + Machine: MIPS R3000 + Version: 0x1 + Entry point address: 0x0 + Start of program headers: 0 \(bytes into file\) + Start of section headers: ... \(bytes into file\) + Flags: 0x70001000, o32, mips32r2 + Size of this header: 52 \(bytes\) + Size of program headers: 0 \(bytes\) + Number of program headers: 0 + Size of section headers: 40 \(bytes\) + Number of section headers: 11 + Section header string table index: 8 +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-51.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-51.d index e183d54..7610b59 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-51.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-51.d @@ -1,5 +1,21 @@ -#source: attr-gnu-4-5.s -#source: attr-gnu-4-1.s -#ld: -r -#warning: Warning: .* uses unknown floating point ABI 5 \(set by .*\), .* uses -mdouble-float -#target: mips*-*-* +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-1.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-52.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-52.d new file mode 100644 index 0000000..b36547d --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-52.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-2.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mfpxx \(set by .*\), .* uses -msingle-float diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-53.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-53.d new file mode 100644 index 0000000..7312d17 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-53.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-3.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-54.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-54.d new file mode 100644 index 0000000..a5beaf1 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-54.d @@ -0,0 +1,6 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-4.s -W -32 -EB +#ld: -r -melf32btsmip +#error: \A[^\n]*: Warning: .* uses -mfpxx \(set by .*\), .* uses -mips32r2 -mfp64 \(12 callee-saved\)\n +#error: [^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-55.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-55.d new file mode 100644 index 0000000..f3e3459 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-55.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-56.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-56.d new file mode 100644 index 0000000..856b7fc --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-56.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-57.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-57.d new file mode 100644 index 0000000..fb4906c --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-57.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-7.s -W -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mfpxx \(set by .*\), .* uses unknown floating point ABI 7 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-6-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-6-ph.d new file mode 100644 index 0000000..73ee413 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-6-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips32r2 -32 -mfp64 -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-6.s b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-6.s new file mode 100644 index 0000000..adcff8a --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-6.s @@ -0,0 +1,4 @@ +.module mips32r2 +.module gp=32 +.module fp=64 +.gnu_attribute 4,6 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-60.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-60.d new file mode 100644 index 0000000..6cedcf5 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-60.d @@ -0,0 +1,41 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-0.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -hA + +ELF Header: + Magic: 7f 45 4c 46 01 02 01 00 03 00 00 00 00 00 00 00.* + Class: ELF32 + Data: 2's complement, big endian + Version: 1 \(current\) + OS/ABI: UNIX - System V + ABI Version: 3 + Type: REL \(Relocatable file\) + Machine: MIPS R3000 + Version: 0x1 + Entry point address: 0x0 + Start of program headers: 0 \(bytes into file\) + Start of section headers: ... \(bytes into file\) + Flags: 0x70001000, o32, mips32r2 + Size of this header: 52 \(bytes\) + Size of program headers: 0 \(bytes\) + Number of program headers: 0 + Size of section headers: 40 \(bytes\) + Number of section headers: 11 + Section header string table index: 8 +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-61.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-61.d new file mode 100644 index 0000000..6e9040c --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-61.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-1.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mgp32 -mfp64 \(set by .*\), .* uses -mdouble-float diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-62.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-62.d new file mode 100644 index 0000000..5eec884 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-62.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-2.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mgp32 -mfp64 \(set by .*\), .* uses -msingle-float diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-63.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-63.d new file mode 100644 index 0000000..eb750f3 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-63.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-3.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-64.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-64.d new file mode 100644 index 0000000..a5dcb7e --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-64.d @@ -0,0 +1,6 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-4.s -W -32 -EB +#ld: -r -melf32btsmip +#error: \A[^\n]*: Warning: .* uses -mgp32 -mfp64 \(set by .*\), .* uses -mips32r2 -mfp64 \(12 callee-saved\)\n +#error: [^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-65.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-65.d new file mode 100644 index 0000000..960450d --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-65.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-66.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-66.d new file mode 100644 index 0000000..06cc2d9 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-66.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-67.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-67.d new file mode 100644 index 0000000..a138a31 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-67.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-7.s -W -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mgp32 -mfp64 \(set by .*\), .* uses unknown floating point ABI 7 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-7.s b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-7.s new file mode 100644 index 0000000..0ab9aea --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-7.s @@ -0,0 +1 @@ +.gnu_attribute 4,7 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-71.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-71.d new file mode 100644 index 0000000..ddfc242 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-71.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-7.s -W +#source: attr-gnu-4-1.s +#ld: -r +#warning: Warning: .* uses unknown floating point ABI 7 \(set by .*\), .* uses -mdouble-float diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-0.s b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-0.s new file mode 100644 index 0000000..b28c578 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-0.s @@ -0,0 +1 @@ +.gnu_attribute 8,0 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-00.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-00.d new file mode 100644 index 0000000..2f8e5f0 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-00.d @@ -0,0 +1,9 @@ +#source: attr-gnu-8-0.s +#source: attr-gnu-8-0.s +#ld: -r +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-01.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-01.d new file mode 100644 index 0000000..e2cda33 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-01.d @@ -0,0 +1,10 @@ +#source: attr-gnu-8-0.s +#source: attr-gnu-8-1.s +#ld: -r +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Tag_GNU_MIPS_ABI_MSA: 128-bit MSA +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-02.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-02.d new file mode 100644 index 0000000..54b196f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-02.d @@ -0,0 +1,10 @@ +#source: attr-gnu-8-0.s +#source: attr-gnu-8-2.s +#ld: -r +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Tag_GNU_MIPS_ABI_MSA: \?\?\? \(2\) +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-1.s b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-1.s new file mode 100644 index 0000000..81c7b7f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-1.s @@ -0,0 +1 @@ +.gnu_attribute 8,1 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-10.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-10.d new file mode 100644 index 0000000..f7c512b --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-10.d @@ -0,0 +1,10 @@ +#source: attr-gnu-8-1.s +#source: attr-gnu-8-0.s +#ld: -r +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Tag_GNU_MIPS_ABI_MSA: 128-bit MSA +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-11.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-11.d new file mode 100644 index 0000000..be87af4 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-11.d @@ -0,0 +1,10 @@ +#source: attr-gnu-8-1.s +#source: attr-gnu-8-1.s +#ld: -r +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Tag_GNU_MIPS_ABI_MSA: 128-bit MSA +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-12.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-12.d new file mode 100644 index 0000000..10249d0 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-12.d @@ -0,0 +1,4 @@ +#source: attr-gnu-8-1.s +#source: attr-gnu-8-2.s +#ld: -r +#warning: Warning: .* uses -mmsa \(set by .*\), .* uses unknown MSA ABI 2 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-2.s b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-2.s new file mode 100644 index 0000000..0f18f5f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-2.s @@ -0,0 +1 @@ +.gnu_attribute 8,2 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-20.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-20.d new file mode 100644 index 0000000..05f4da0 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-20.d @@ -0,0 +1,10 @@ +#source: attr-gnu-8-2.s +#source: attr-gnu-8-0.s +#ld: -r +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Tag_GNU_MIPS_ABI_MSA: \?\?\? \(2\) +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-21.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-21.d new file mode 100644 index 0000000..b8f0e7c --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-21.d @@ -0,0 +1,4 @@ +#source: attr-gnu-8-2.s +#source: attr-gnu-8-1.s +#ld: -r +#warning: Warning: .* uses unknown MSA ABI 2 \(set by .*\), .* uses -mmsa diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-22.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-22.d new file mode 100644 index 0000000..908ce4f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-22.d @@ -0,0 +1,10 @@ +#source: attr-gnu-8-2.s +#source: attr-gnu-8-2.s +#ld: -r +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Tag_GNU_MIPS_ABI_MSA: \?\?\? \(2\) +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-dyn.s b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-dyn.s new file mode 100644 index 0000000..a56d1c9 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-dyn.s @@ -0,0 +1,18 @@ +# Create dummy DSO functions for everything that these tests call. + + .abicalls + .option pic2 + + .set filter, -1 + + .macro test_one, name, mask + .globl \name + .ent \name +\name: + jr $31 + .end \name + .endm + + .include "compressed-plt-1.s" + + test_all diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-mips16.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-mips16.od new file mode 100644 index 0000000..c17dacb --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-mips16.od @@ -0,0 +1,411 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# At present, all n32 PLT entries use the standard encoding. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c0e1020 lui \$14,0x1020 +.*: 8dd90000 lw \$25,0\(\$14\) +.*: 25ce0000 addiu \$14,\$14,0 +.*: 030ec023 subu \$24,\$24,\$14 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90008 lw \$25,8\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80008 addiu \$24,\$15,8 + +10100030 <f_lo_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100040 <f_lo_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100050 <f_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100060 <f_lo_iu_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90018 lw \$25,24\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80018 addiu \$24,\$15,24 + +10100070 <f_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100080 <f_lo_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90020 lw \$25,32\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80020 addiu \$24,\$15,32 + +10100090 <f_iu_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90024 lw \$25,36\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80024 addiu \$24,\$15,36 + +101000a0 <f_lo_iu_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90028 lw \$25,40\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80028 addiu \$24,\$15,40 + +101000b0 <f_lo_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9002c lw \$25,44\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8002c addiu \$24,\$15,44 + +101000c0 <f_lo_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90030 lw \$25,48\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80030 addiu \$24,\$15,48 + +101000d0 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90034 lw \$25,52\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80034 addiu \$24,\$15,52 + +101000e0 <f_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90038 lw \$25,56\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80038 addiu \$24,\$15,56 + +101000f0 <f_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9003c lw \$25,60\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8003c addiu \$24,\$15,60 + +10100100 <f_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90040 lw \$25,64\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80040 addiu \$24,\$15,64 + +10100110 <f_lo_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90044 lw \$25,68\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80044 addiu \$24,\$15,68 + +10100120 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90048 lw \$25,72\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80048 addiu \$24,\$15,72 + +10100130 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9004c lw \$25,76\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8004c addiu \$24,\$15,76 + +10100140 <f_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90050 lw \$25,80\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80050 addiu \$24,\$15,80 + +10100150 <f_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90054 lw \$25,84\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80054 addiu \$24,\$15,84 + +10100160 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90058 lw \$25,88\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80058 addiu \$24,\$15,88 + +10100170 <f_iu_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9005c lw \$25,92\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8005c addiu \$24,\$15,92 + +10100180 <f_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90060 lw \$25,96\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80060 addiu \$24,\$15,96 + +10100190 <f_lo_iu_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90064 lw \$25,100\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80064 addiu \$24,\$15,100 + +101001a0 <f_lo_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90068 lw \$25,104\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80068 addiu \$24,\$15,104 + +101001b0 <f_lo_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9006c lw \$25,108\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8006c addiu \$24,\$15,108 + +101001c0 <f_lo_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90070 lw \$25,112\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80070 addiu \$24,\$15,112 + +101001d0 <f_lo@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90074 lw \$25,116\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80074 addiu \$24,\$15,116 + +Disassembly of section \.MIPS\.stubs: + +10101000 <_MIPS_STUBS_>: +# Lazy-binding stub for f_iu. +.*: 8f998010 lw \$25,-32752\(\$28\) +.*: 03e07821 move \$15,\$31 +.*: 0320f809 jalr \$25 +.*: 24180021 li \$24,33 +# Lazy-binding stub for f_ic. +.*: 8f998010 lw \$25,-32752\(\$28\) +.*: 03e07821 move \$15,\$31 +.*: 0320f809 jalr \$25 +.*: 24180020 li \$24,32 +# Lazy-binding stub for f_iu_ic. +.*: 8f998010 lw \$25,-32752\(\$28\) +.*: 03e07821 move \$15,\$31 +.*: 0320f809 jalr \$25 +.*: 2418001f li \$24,31 + \.\.\. + +Disassembly of section \.text\.a: + +10102000 <testc>: +.*: .... .... jalx [0-9a-f]+ <f_dc@plt> +.*: 6500 nop +.*: f070 9b50 lw \$2,-32656\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jalx [0-9a-f]+ <f_ic_dc@plt> +.*: 6500 nop +.*: f010 9b58 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_du_dc@plt> +.*: 6500 nop +.*: f010 9b5c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_du_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_du_ic_dc@plt> +.*: 6500 nop +.*: f030 9b40 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_iu_dc@plt> +.*: 6500 nop +.*: f070 9b4c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: .... .... jalx [0-9a-f]+ <f_iu_ic_dc@plt> +.*: 6500 nop +.*: f030 9b44 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_iu_du_dc@plt> +.*: 6500 nop +.*: f030 9b48 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 6500 nop +.*: f030 9b4c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_dc@plt> +.*: 6500 nop +.*: f030 9b50 lw \$2,-32720\(\$3\) +# ^ local GOT entry for f_lo_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_ic_dc@plt> +.*: 6500 nop +.*: f030 9b54 lw \$2,-32716\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_du_dc@plt> +.*: 6500 nop +.*: f030 9b58 lw \$2,-32712\(\$3\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 6500 nop +.*: f030 9b5c lw \$2,-32708\(\$3\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_iu_dc@plt> +.*: 6500 nop +.*: f050 9b40 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_iu_ic_dc@plt> +.*: 6500 nop +.*: f050 9b44 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 6500 nop +.*: f050 9b48 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 6500 nop +.*: f050 9b4c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: e820 jr \$31 + +Disassembly of section \.text\.b: + +10103000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c628074 lw \$2,-32652\(\$3\) +# ^ global GOT entry for f_iu +.*: 8c628050 lw \$2,-32688\(\$3\) +# ^ local GOT entry for f_iu_dc@plt +.*: 8c62806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628054 lw \$2,-32684\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628058 lw \$2,-32680\(\$3\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62805c lw \$2,-32676\(\$3\) +# ^ local GOT entry for f_lo_iu@plt +.*: 8c628060 lw \$2,-32672\(\$3\) +# ^ local GOT entry for f_lo_iu_dc@plt +.*: 8c628040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: 8c628044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628064 lw \$2,-32668\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628068 lw \$2,-32664\(\$3\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10104000 <testlo>: +.*: 240201d0 li \$2,464 +# ^ low 16 bits of f_lo@plt +.*: 24020110 li \$2,272 +# ^ low 16 bits of f_lo_dc@plt +.*: 240200b0 li \$2,176 +# ^ low 16 bits of f_lo_ic@plt +.*: 240201c0 li \$2,448 +# ^ low 16 bits of f_lo_ic_dc@plt +.*: 24020160 li \$2,352 +# ^ low 16 bits of f_lo_du@plt +.*: 240200c0 li \$2,192 +# ^ low 16 bits of f_lo_du_dc@plt +.*: 24020080 li \$2,128 +# ^ low 16 bits of f_lo_du_ic@plt +.*: 24020040 li \$2,64 +# ^ low 16 bits of f_lo_du_ic_dc@plt +.*: 24020020 li \$2,32 +# ^ low 16 bits of f_lo_iu@plt +.*: 24020060 li \$2,96 +# ^ low 16 bits of f_lo_iu_dc@plt +.*: 240200a0 li \$2,160 +# ^ low 16 bits of f_lo_iu_ic@plt +.*: 24020190 li \$2,400 +# ^ low 16 bits of f_lo_iu_ic_dc@plt +.*: 24020130 li \$2,304 +# ^ low 16 bits of f_lo_iu_du@plt +.*: 24020030 li \$2,48 +# ^ low 16 bits of f_lo_iu_du_dc@plt +.*: 240201a0 li \$2,416 +# ^ low 16 bits of f_lo_iu_du_ic@plt +.*: 240201b0 li \$2,432 +# ^ low 16 bits of f_lo_iu_du_ic_dc@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-mips16.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-mips16.rd new file mode 100644 index 0000000..82b0313 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-mips16.rd @@ -0,0 +1,167 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x1f + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 224 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo_iu_du_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 10100040 f_lo_du_ic_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100060 f_lo_iu_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_ic +10200020 [^ ]+ R_MIPS_JUMP_SLOT 10100080 f_lo_du_ic +10200024 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_dc +10200028 [^ ]+ R_MIPS_JUMP_SLOT 101000a0 f_lo_iu_ic +1020002c [^ ]+ R_MIPS_JUMP_SLOT 101000b0 f_lo_ic +10200030 [^ ]+ R_MIPS_JUMP_SLOT 101000c0 f_lo_du_dc +10200034 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du +10200038 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_ic_dc +1020003c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_ic +10200040 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_dc +10200044 [^ ]+ R_MIPS_JUMP_SLOT 10100110 f_lo_dc +10200048 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du +1020004c [^ ]+ R_MIPS_JUMP_SLOT 10100130 f_lo_iu_du +10200050 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_dc +10200054 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_ic_dc +10200058 [^ ]+ R_MIPS_JUMP_SLOT 10100160 f_lo_du +1020005c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_ic_dc +10200060 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_ic_dc +10200064 [^ ]+ R_MIPS_JUMP_SLOT 10100190 f_lo_iu_ic_dc +10200068 [^ ]+ R_MIPS_JUMP_SLOT 101001a0 f_lo_iu_du_ic +1020006c [^ ]+ R_MIPS_JUMP_SLOT 101001b0 f_lo_iu_du_ic_dc +10200070 [^ ]+ R_MIPS_JUMP_SLOT 101001c0 f_lo_ic_dc +10200074 [^ ]+ R_MIPS_JUMP_SLOT 101001d0 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# _lo symbols have their address taken, so their PLT symbols need to have +# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish +# them from old-style lazy-binding stubs. Non-_lo symbols are only called, +# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation. + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_dc +#... + .*: 10100040 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_dc + .*: 10100060 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_ic + .*: 10100080 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_dc + .*: 101000a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic + .*: 101000b0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 101000c0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_ic + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_dc + .*: 10100110 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du + .*: 10100130 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic_dc + .*: 10100160 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_ic_dc +#... + .*: 10100190 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic_dc + .*: 101001a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic + .*: 101001b0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic_dc + .*: 101001c0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 101001d0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. The symbol value +# is the address of the lazy-binding stub. + 31: 10101020 0 FUNC GLOBAL DEFAULT UND f_iu_ic + 32: 10101010 0 FUNC GLOBAL DEFAULT UND f_ic + 33: 10101000 0 FUNC GLOBAL DEFAULT UND f_iu + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 10100150 + 1020100c -32740\(gp\) 101000f0 + 10201010 -32736\(gp\) 101000e0 + 10201014 -32732\(gp\) 10100170 + 10201018 -32728\(gp\) 10100070 + 1020101c -32724\(gp\) 10100180 + 10201020 -32720\(gp\) 101000b0 + 10201024 -32716\(gp\) 101001c0 + 10201028 -32712\(gp\) 10100080 + 1020102c -32708\(gp\) 10100040 + 10201030 -32704\(gp\) 101000a0 + 10201034 -32700\(gp\) 10100190 + 10201038 -32696\(gp\) 101001a0 + 1020103c -32692\(gp\) 101001b0 + 10201040 -32688\(gp\) 10100090 + 10201044 -32684\(gp\) 10100120 + 10201048 -32680\(gp\) 10100100 + 1020104c -32676\(gp\) 10100020 + 10201050 -32672\(gp\) 10100060 + 10201054 -32668\(gp\) 10100130 + 10201058 -32664\(gp\) 10100030 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 1020105c -32660\(gp\) 10101020 10101020 FUNC UND f_iu_ic + 10201060 -32656\(gp\) 10101010 10101010 FUNC UND f_ic + 10201064 -32652\(gp\) 10101000 10101000 FUNC UND f_iu + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100020 FUNC UND f_lo_iu + 1020000c 10100000 10100030 FUNC UND f_lo_iu_du_dc + 10200010 10100000 10100040 FUNC UND f_lo_du_ic_dc + 10200014 10100000 00000000 FUNC UND f_du_dc + 10200018 10100000 10100060 FUNC UND f_lo_iu_dc + 1020001c 10100000 00000000 FUNC UND f_iu_du_ic + 10200020 10100000 10100080 FUNC UND f_lo_du_ic + 10200024 10100000 00000000 FUNC UND f_iu_dc + 10200028 10100000 101000a0 FUNC UND f_lo_iu_ic + 1020002c 10100000 101000b0 FUNC UND f_lo_ic + 10200030 10100000 101000c0 FUNC UND f_lo_du_dc + 10200034 10100000 00000000 FUNC UND f_du + 10200038 10100000 00000000 FUNC UND f_du_ic_dc + 1020003c 10100000 00000000 FUNC UND f_du_ic + 10200040 10100000 00000000 FUNC UND f_iu_du_dc + 10200044 10100000 10100110 FUNC UND f_lo_dc + 10200048 10100000 00000000 FUNC UND f_iu_du + 1020004c 10100000 10100130 FUNC UND f_lo_iu_du + 10200050 10100000 00000000 FUNC UND f_dc + 10200054 10100000 00000000 FUNC UND f_ic_dc + 10200058 10100000 10100160 FUNC UND f_lo_du + 1020005c 10100000 00000000 FUNC UND f_iu_ic_dc + 10200060 10100000 00000000 FUNC UND f_iu_du_ic_dc + 10200064 10100000 10100190 FUNC UND f_lo_iu_ic_dc + 10200068 10100000 101001a0 FUNC UND f_lo_iu_du_ic + 1020006c 10100000 101001b0 FUNC UND f_lo_iu_du_ic_dc + 10200070 10100000 101001c0 FUNC UND f_lo_ic_dc + 10200074 10100000 101001d0 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-umips.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-umips.od new file mode 100644 index 0000000..fc0d4ea --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-umips.od @@ -0,0 +1,411 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# At present, all n32 PLT entries use the standard encoding. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c0e1020 lui \$14,0x1020 +.*: 8dd90000 lw \$25,0\(\$14\) +.*: 25ce0000 addiu \$14,\$14,0 +.*: 030ec023 subu \$24,\$24,\$14 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90008 lw \$25,8\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80008 addiu \$24,\$15,8 + +10100030 <f_lo_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100040 <f_lo_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100050 <f_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100060 <f_lo_iu_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90018 lw \$25,24\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80018 addiu \$24,\$15,24 + +10100070 <f_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100080 <f_lo_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90020 lw \$25,32\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80020 addiu \$24,\$15,32 + +10100090 <f_iu_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90024 lw \$25,36\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80024 addiu \$24,\$15,36 + +101000a0 <f_lo_iu_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90028 lw \$25,40\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80028 addiu \$24,\$15,40 + +101000b0 <f_lo_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9002c lw \$25,44\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8002c addiu \$24,\$15,44 + +101000c0 <f_lo_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90030 lw \$25,48\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80030 addiu \$24,\$15,48 + +101000d0 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90034 lw \$25,52\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80034 addiu \$24,\$15,52 + +101000e0 <f_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90038 lw \$25,56\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80038 addiu \$24,\$15,56 + +101000f0 <f_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9003c lw \$25,60\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8003c addiu \$24,\$15,60 + +10100100 <f_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90040 lw \$25,64\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80040 addiu \$24,\$15,64 + +10100110 <f_lo_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90044 lw \$25,68\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80044 addiu \$24,\$15,68 + +10100120 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90048 lw \$25,72\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80048 addiu \$24,\$15,72 + +10100130 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9004c lw \$25,76\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8004c addiu \$24,\$15,76 + +10100140 <f_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90050 lw \$25,80\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80050 addiu \$24,\$15,80 + +10100150 <f_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90054 lw \$25,84\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80054 addiu \$24,\$15,84 + +10100160 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90058 lw \$25,88\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80058 addiu \$24,\$15,88 + +10100170 <f_iu_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9005c lw \$25,92\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8005c addiu \$24,\$15,92 + +10100180 <f_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90060 lw \$25,96\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80060 addiu \$24,\$15,96 + +10100190 <f_lo_iu_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90064 lw \$25,100\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80064 addiu \$24,\$15,100 + +101001a0 <f_lo_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90068 lw \$25,104\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80068 addiu \$24,\$15,104 + +101001b0 <f_lo_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9006c lw \$25,108\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8006c addiu \$24,\$15,108 + +101001c0 <f_lo_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90070 lw \$25,112\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80070 addiu \$24,\$15,112 + +101001d0 <f_lo@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90074 lw \$25,116\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80074 addiu \$24,\$15,116 + +Disassembly of section \.MIPS\.stubs: + +10101000 <_MIPS_STUBS_>: +# Lazy-binding stub for f_iu. +.*: ff3c 8010 lw \$25,-32752\(\$28\) +.*: 0dff move \$15,\$31 +.*: 45d9 jalr \$25 +.*: 3300 0021 li \$24,33 +# Lazy-binding stub for f_ic. +.*: ff3c 8010 lw \$25,-32752\(\$28\) +.*: 0dff move \$15,\$31 +.*: 45d9 jalr \$25 +.*: 3300 0020 li \$24,32 +# Lazy-binding stub for f_iu_ic. +.*: ff3c 8010 lw \$25,-32752\(\$28\) +.*: 0dff move \$15,\$31 +.*: 45d9 jalr \$25 +.*: 3300 001f li \$24,31 + \.\.\. + +Disassembly of section \.text\.a: + +10102000 <testc>: +.*: .... .... jalx [0-9a-f]+ <f_dc@plt> +.*: 0000 0000 nop +.*: fc43 8070 lw \$2,-32656\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jalx [0-9a-f]+ <f_ic_dc@plt> +.*: 0000 0000 nop +.*: fc43 8018 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_du_dc@plt> +.*: 0000 0000 nop +.*: fc43 801c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_du_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_du_ic_dc@plt> +.*: 0000 0000 nop +.*: fc43 8020 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_iu_dc@plt> +.*: 0000 0000 nop +.*: fc43 806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: .... .... jalx [0-9a-f]+ <f_iu_ic_dc@plt> +.*: 0000 0000 nop +.*: fc43 8024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_iu_du_dc@plt> +.*: 0000 0000 nop +.*: fc43 8028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 0000 0000 nop +.*: fc43 802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_dc@plt> +.*: 0000 0000 nop +.*: fc43 8030 lw \$2,-32720\(\$3\) +# ^ local GOT entry for f_lo_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_ic_dc@plt> +.*: 0000 0000 nop +.*: fc43 8034 lw \$2,-32716\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_du_dc@plt> +.*: 0000 0000 nop +.*: fc43 8038 lw \$2,-32712\(\$3\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 0000 0000 nop +.*: fc43 803c lw \$2,-32708\(\$3\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_iu_dc@plt> +.*: 0000 0000 nop +.*: fc43 8040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_iu_ic_dc@plt> +.*: 0000 0000 nop +.*: fc43 8044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 0000 0000 nop +.*: fc43 8048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 0000 0000 nop +.*: fc43 804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 459f jr \$31 + +Disassembly of section \.text\.b: + +10103000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c628074 lw \$2,-32652\(\$3\) +# ^ global GOT entry for f_iu +.*: 8c628050 lw \$2,-32688\(\$3\) +# ^ local GOT entry for f_iu_dc@plt +.*: 8c62806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628054 lw \$2,-32684\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628058 lw \$2,-32680\(\$3\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62805c lw \$2,-32676\(\$3\) +# ^ local GOT entry for f_lo_iu@plt +.*: 8c628060 lw \$2,-32672\(\$3\) +# ^ local GOT entry for f_lo_iu_dc@plt +.*: 8c628040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: 8c628044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628064 lw \$2,-32668\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628068 lw \$2,-32664\(\$3\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10104000 <testlo>: +.*: 3040 01d0 li \$2,464 +# ^ low 16 bits of f_lo@plt +.*: 3040 0110 li \$2,272 +# ^ low 16 bits of f_lo_dc@plt +.*: 3040 00b0 li \$2,176 +# ^ low 16 bits of f_lo_ic@plt +.*: 3040 01c0 li \$2,448 +# ^ low 16 bits of f_lo_ic_dc@plt +.*: 3040 0160 li \$2,352 +# ^ low 16 bits of f_lo_du@plt +.*: 3040 00c0 li \$2,192 +# ^ low 16 bits of f_lo_du_dc@plt +.*: 3040 0080 li \$2,128 +# ^ low 16 bits of f_lo_du_ic@plt +.*: 3040 0040 li \$2,64 +# ^ low 16 bits of f_lo_du_ic_dc@plt +.*: 3040 0020 li \$2,32 +# ^ low 16 bits of f_lo_iu@plt +.*: 3040 0060 li \$2,96 +# ^ low 16 bits of f_lo_iu_dc@plt +.*: 3040 00a0 li \$2,160 +# ^ low 16 bits of f_lo_iu_ic@plt +.*: 3040 0190 li \$2,400 +# ^ low 16 bits of f_lo_iu_ic_dc@plt +.*: 3040 0130 li \$2,304 +# ^ low 16 bits of f_lo_iu_du@plt +.*: 3040 0030 li \$2,48 +# ^ low 16 bits of f_lo_iu_du_dc@plt +.*: 3040 01a0 li \$2,416 +# ^ low 16 bits of f_lo_iu_du_ic@plt +.*: 3040 01b0 li \$2,432 +# ^ low 16 bits of f_lo_iu_du_ic_dc@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-umips.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-umips.rd new file mode 100644 index 0000000..d4dc838 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-umips.rd @@ -0,0 +1,167 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x1f + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 224 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo_iu_du_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 10100040 f_lo_du_ic_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100060 f_lo_iu_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_ic +10200020 [^ ]+ R_MIPS_JUMP_SLOT 10100080 f_lo_du_ic +10200024 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_dc +10200028 [^ ]+ R_MIPS_JUMP_SLOT 101000a0 f_lo_iu_ic +1020002c [^ ]+ R_MIPS_JUMP_SLOT 101000b0 f_lo_ic +10200030 [^ ]+ R_MIPS_JUMP_SLOT 101000c0 f_lo_du_dc +10200034 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du +10200038 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_ic_dc +1020003c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_ic +10200040 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_dc +10200044 [^ ]+ R_MIPS_JUMP_SLOT 10100110 f_lo_dc +10200048 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du +1020004c [^ ]+ R_MIPS_JUMP_SLOT 10100130 f_lo_iu_du +10200050 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_dc +10200054 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_ic_dc +10200058 [^ ]+ R_MIPS_JUMP_SLOT 10100160 f_lo_du +1020005c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_ic_dc +10200060 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_ic_dc +10200064 [^ ]+ R_MIPS_JUMP_SLOT 10100190 f_lo_iu_ic_dc +10200068 [^ ]+ R_MIPS_JUMP_SLOT 101001a0 f_lo_iu_du_ic +1020006c [^ ]+ R_MIPS_JUMP_SLOT 101001b0 f_lo_iu_du_ic_dc +10200070 [^ ]+ R_MIPS_JUMP_SLOT 101001c0 f_lo_ic_dc +10200074 [^ ]+ R_MIPS_JUMP_SLOT 101001d0 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# _lo symbols have their address taken, so their PLT symbols need to have +# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish +# them from old-style lazy-binding stubs. Non-_lo symbols are only called, +# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation. + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_dc +#... + .*: 10100040 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_dc + .*: 10100060 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_ic + .*: 10100080 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_dc + .*: 101000a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic + .*: 101000b0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 101000c0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_ic + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_dc + .*: 10100110 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du + .*: 10100130 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic_dc + .*: 10100160 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_ic_dc +#... + .*: 10100190 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic_dc + .*: 101001a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic + .*: 101001b0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic_dc + .*: 101001c0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 101001d0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. The symbol value +# is the address of the lazy-binding stub. + 31: 10101019 0 FUNC GLOBAL DEFAULT UND f_iu_ic + 32: 1010100d 0 FUNC GLOBAL DEFAULT UND f_ic + 33: 10101001 0 FUNC GLOBAL DEFAULT UND f_iu + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 10100150 + 1020100c -32740\(gp\) 101000f0 + 10201010 -32736\(gp\) 101000e0 + 10201014 -32732\(gp\) 10100170 + 10201018 -32728\(gp\) 10100070 + 1020101c -32724\(gp\) 10100180 + 10201020 -32720\(gp\) 101000b0 + 10201024 -32716\(gp\) 101001c0 + 10201028 -32712\(gp\) 10100080 + 1020102c -32708\(gp\) 10100040 + 10201030 -32704\(gp\) 101000a0 + 10201034 -32700\(gp\) 10100190 + 10201038 -32696\(gp\) 101001a0 + 1020103c -32692\(gp\) 101001b0 + 10201040 -32688\(gp\) 10100090 + 10201044 -32684\(gp\) 10100120 + 10201048 -32680\(gp\) 10100100 + 1020104c -32676\(gp\) 10100020 + 10201050 -32672\(gp\) 10100060 + 10201054 -32668\(gp\) 10100130 + 10201058 -32664\(gp\) 10100030 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 1020105c -32660\(gp\) 10101019 10101019 FUNC UND f_iu_ic + 10201060 -32656\(gp\) 1010100d 1010100d FUNC UND f_ic + 10201064 -32652\(gp\) 10101001 10101001 FUNC UND f_iu + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100020 FUNC UND f_lo_iu + 1020000c 10100000 10100030 FUNC UND f_lo_iu_du_dc + 10200010 10100000 10100040 FUNC UND f_lo_du_ic_dc + 10200014 10100000 00000000 FUNC UND f_du_dc + 10200018 10100000 10100060 FUNC UND f_lo_iu_dc + 1020001c 10100000 00000000 FUNC UND f_iu_du_ic + 10200020 10100000 10100080 FUNC UND f_lo_du_ic + 10200024 10100000 00000000 FUNC UND f_iu_dc + 10200028 10100000 101000a0 FUNC UND f_lo_iu_ic + 1020002c 10100000 101000b0 FUNC UND f_lo_ic + 10200030 10100000 101000c0 FUNC UND f_lo_du_dc + 10200034 10100000 00000000 FUNC UND f_du + 10200038 10100000 00000000 FUNC UND f_du_ic_dc + 1020003c 10100000 00000000 FUNC UND f_du_ic + 10200040 10100000 00000000 FUNC UND f_iu_du_dc + 10200044 10100000 10100110 FUNC UND f_lo_dc + 10200048 10100000 00000000 FUNC UND f_iu_du + 1020004c 10100000 10100130 FUNC UND f_lo_iu_du + 10200050 10100000 00000000 FUNC UND f_dc + 10200054 10100000 00000000 FUNC UND f_ic_dc + 10200058 10100000 10100160 FUNC UND f_lo_du + 1020005c 10100000 00000000 FUNC UND f_iu_ic_dc + 10200060 10100000 00000000 FUNC UND f_iu_du_ic_dc + 10200064 10100000 10100190 FUNC UND f_lo_iu_ic_dc + 10200068 10100000 101001a0 FUNC UND f_lo_iu_du_ic + 1020006c 10100000 101001b0 FUNC UND f_lo_iu_du_ic_dc + 10200070 10100000 101001c0 FUNC UND f_lo_ic_dc + 10200074 10100000 101001d0 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-got.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-got.od new file mode 100644 index 0000000..c48ef7f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-got.od @@ -0,0 +1,557 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# Only _dc (direct call from compressed code) functions should have a +# MIPS16 PLT. Note that indirect calls do not influence the choice, +# so f_ic and f_lo_ic have MIPS rather than MIPS16 PLTs. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c1c1020 lui \$28,0x1020 +.*: 8f990000 lw \$25,0\(\$28\) +.*: 279c0000 addiu \$28,\$28,0 +.*: 031cc023 subu \$24,\$24,\$28 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90008 lw \$25,8\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80008 addiu \$24,\$15,8 + +10100030 <f_lo_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100040 <f_lo_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100050 <f_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100060 <f_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100070 <f_lo_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90020 lw \$25,32\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80020 addiu \$24,\$15,32 + +10100080 <f_lo_iu_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90028 lw \$25,40\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80028 addiu \$24,\$15,40 + +10100090 <f_lo_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9002c lw \$25,44\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8002c addiu \$24,\$15,44 + +101000a0 <f_lo_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90030 lw \$25,48\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80030 addiu \$24,\$15,48 + +101000b0 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90034 lw \$25,52\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80034 addiu \$24,\$15,52 + +101000c0 <f_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90038 lw \$25,56\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80038 addiu \$24,\$15,56 + +101000d0 <f_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9003c lw \$25,60\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8003c addiu \$24,\$15,60 + +101000e0 <f_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90040 lw \$25,64\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80040 addiu \$24,\$15,64 + +101000f0 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90048 lw \$25,72\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80048 addiu \$24,\$15,72 + +10100100 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9004c lw \$25,76\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8004c addiu \$24,\$15,76 + +10100110 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90058 lw \$25,88\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80058 addiu \$24,\$15,88 + +10100120 <f_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90060 lw \$25,96\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80060 addiu \$24,\$15,96 + +10100130 <f_lo_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90068 lw \$25,104\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80068 addiu \$24,\$15,104 + +10100140 <f_lo_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9006c lw \$25,108\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8006c addiu \$24,\$15,108 + +10100150 <f_lo@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90074 lw \$25,116\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80074 addiu \$24,\$15,116 + +10100160 <f_lo_iu_du_dc@mips16plt>: +.*: b203 lw \$2,1010016c <f_lo_iu_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020000c + +10100170 <f_lo_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010017c <f_lo_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200010 + +10100180 <f_du_dc@mips16plt>: +.*: b203 lw \$2,1010018c <f_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200014 + +10100190 <f_lo_iu_dc@mips16plt>: +.*: b203 lw \$2,1010019c <f_lo_iu_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200018 + +101001a0 <f_iu_dc@mips16plt>: +.*: b203 lw \$2,101001ac <f_iu_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200024 + +101001b0 <f_lo_du_dc@mips16plt>: +.*: b203 lw \$2,101001bc <f_lo_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200030 + +101001c0 <f_du_ic_dc@mips16plt>: +.*: b203 lw \$2,101001cc <f_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200038 + +101001d0 <f_iu_du_dc@mips16plt>: +.*: b203 lw \$2,101001dc <f_iu_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200040 + +101001e0 <f_lo_dc@mips16plt>: +.*: b203 lw \$2,101001ec <f_lo_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200044 + +101001f0 <f_dc@mips16plt>: +.*: b203 lw \$2,101001fc <f_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200050 + +10100200 <f_ic_dc@mips16plt>: +.*: b203 lw \$2,1010020c <f_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200054 + +10100210 <f_iu_ic_dc@mips16plt>: +.*: b203 lw \$2,1010021c <f_iu_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020005c + +10100220 <f_iu_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010022c <f_iu_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200060 + +10100230 <f_lo_iu_ic_dc@mips16plt>: +.*: b203 lw \$2,1010023c <f_lo_iu_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200064 + +10100240 <f_lo_iu_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010024c <f_lo_iu_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020006c + +10100250 <f_lo_ic_dc@mips16plt>: +.*: b203 lw \$2,1010025c <f_lo_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200070 + +Disassembly of section \.text\.a: + +10101000 <testc>: +.*: .... .... jal [0-9a-f]+ <f_dc@mips16plt> +.*: 6500 nop +.*: f090 9b4c lw \$2,-32628\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jal [0-9a-f]+ <f_ic_dc@mips16plt> +.*: 6500 nop +.*: f010 9b58 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_du_dc@mips16plt> +.*: 6500 nop +.*: f010 9b5c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b40 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_iu_dc@mips16plt> +.*: 6500 nop +.*: f090 9b48 lw \$2,-32632\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: .... .... jal [0-9a-f]+ <f_iu_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b44 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_dc@mips16plt> +.*: 6500 nop +.*: f030 9b48 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b4c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_dc@mips16plt> +.*: 6500 nop +.*: f030 9b50 lw \$2,-32720\(\$3\) +# ^ local GOT entry for f_lo_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b54 lw \$2,-32716\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_dc@mips16plt> +.*: 6500 nop +.*: f030 9b58 lw \$2,-32712\(\$3\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b5c lw \$2,-32708\(\$3\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_dc@mips16plt> +.*: 6500 nop +.*: f050 9b40 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_ic_dc@mips16plt> +.*: 6500 nop +.*: f050 9b44 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_dc@mips16plt> +.*: 6500 nop +.*: f050 9b48 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f050 9b4c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: e820 jr \$31 + +Disassembly of section \.text\.b: + +10102000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c628090 lw \$2,-32624\(\$3\) +# ^ global GOT entry for f_iu +.*: 8c628050 lw \$2,-32688\(\$3\) +# ^ local GOT entry for f_iu_dc@mips16plt +.*: 8c628088 lw \$2,-32632\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@mips16plt +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628054 lw \$2,-32684\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628058 lw \$2,-32680\(\$3\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62805c lw \$2,-32676\(\$3\) +# ^ local GOT entry for f_lo_iu@plt +.*: 8c628060 lw \$2,-32672\(\$3\) +# ^ local GOT entry for f_lo_iu_dc@mips16plt +.*: 8c628040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: 8c628044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@mips16plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628064 lw \$2,-32668\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628068 lw \$2,-32664\(\$3\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10103000 <testlo>: +.*: 24020150 li \$2,336 +# ^ low 16 bits of f_lo@plt +.*: 240201e1 li \$2,481 +# ^ low 16 bits of f_lo_dc@mips16plt +.*: 24020090 li \$2,144 +# ^ low 16 bits of f_lo_ic@plt +.*: 24020251 li \$2,593 +# ^ low 16 bits of f_lo_ic_dc@mips16plt +.*: 24020110 li \$2,272 +# ^ low 16 bits of f_lo_du@plt +.*: 240200a0 li \$2,160 +# ^ low 16 bits of f_lo_du_dc@plt +.*: 24020070 li \$2,112 +# ^ low 16 bits of f_lo_du_ic@plt +.*: 24020040 li \$2,64 +# ^ low 16 bits of f_lo_du_ic_dc@plt +.*: 24020020 li \$2,32 +# ^ low 16 bits of f_lo_iu@plt +.*: 24020191 li \$2,401 +# ^ low 16 bits of f_lo_iu_dc@mips16plt +.*: 24020080 li \$2,128 +# ^ low 16 bits of f_lo_iu_ic@plt +.*: 24020231 li \$2,561 +# ^ low 16 bits of f_lo_iu_ic_dc@mips16plt +.*: 24020100 li \$2,256 +# ^ low 16 bits of f_lo_iu_du@plt +.*: 24020030 li \$2,48 +# ^ low 16 bits of f_lo_iu_du_dc@plt +.*: 24020130 li \$2,304 +# ^ low 16 bits of f_lo_iu_du_ic@plt +.*: 24020140 li \$2,320 +# ^ low 16 bits of f_lo_iu_du_ic_dc@plt + +Disassembly of section \.text\.d: + +10104000 <testgot>: +.*: 8f828094 lw \$2,-32620\(\$28\) +# ^ global GOT entry for f +.*: 8f82806c lw \$2,-32660\(\$28\) +# ^ local GOT entry for f_dc@mips16plt +.*: 8f82808c lw \$2,-32628\(\$28\) +# ^ global GOT entry for f_ic +.*: 8f828018 lw \$2,-32744\(\$28\) +# ^ local GOT entry for f_ic_dc@mips16plt +.*: 8f828070 lw \$2,-32656\(\$28\) +# ^ local GOT entry for f_du@plt +.*: 8f828074 lw \$2,-32652\(\$28\) +# ^ local GOT entry for f_du_dc@plt +.*: 8f82801c lw \$2,-32740\(\$28\) +# ^ local GOT entry for f_du_ic@plt +.*: 8f828020 lw \$2,-32736\(\$28\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: 8f828090 lw \$2,-32624\(\$28\) +# ^ global GOT entry for f_iu +.*: 8f828050 lw \$2,-32688\(\$28\) +# ^ local GOT entry for f_iu_dc@mips16plt +.*: 8f828088 lw \$2,-32632\(\$28\) +# ^ global GOT entry for f_iu_ic +.*: 8f828024 lw \$2,-32732\(\$28\) +# ^ local GOT entry for f_iu_ic_dc@mips16plt +.*: 8f828054 lw \$2,-32684\(\$28\) +# ^ local GOT entry for f_iu_du@plt +.*: 8f828058 lw \$2,-32680\(\$28\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: 8f828028 lw \$2,-32728\(\$28\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: 8f82802c lw \$2,-32724\(\$28\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: 8f828078 lw \$2,-32648\(\$28\) +# ^ local GOT entry for f_lo@plt +.*: 8f82807c lw \$2,-32644\(\$28\) +# ^ local GOT entry for f_lo_dc@mips16plt +.*: 8f828030 lw \$2,-32720\(\$28\) +# ^ local GOT entry for f_lo_ic@plt +.*: 8f828034 lw \$2,-32716\(\$28\) +# ^ local GOT entry for f_lo_ic_dc@mips16plt +.*: 8f828080 lw \$2,-32640\(\$28\) +# ^ local GOT entry for f_lo_du@plt +.*: 8f828084 lw \$2,-32636\(\$28\) +# ^ local GOT entry for f_lo_du_dc@plt +.*: 8f828038 lw \$2,-32712\(\$28\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: 8f82803c lw \$2,-32708\(\$28\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: 8f82805c lw \$2,-32676\(\$28\) +# ^ local GOT entry for f_lo_iu@plt +.*: 8f828060 lw \$2,-32672\(\$28\) +# ^ local GOT entry for f_lo_iu_dc@mips16plt +.*: 8f828040 lw \$2,-32704\(\$28\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: 8f828044 lw \$2,-32700\(\$28\) +# ^ local GOT entry for f_lo_iu_ic_dc@mips16plt +.*: 8f828064 lw \$2,-32668\(\$28\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: 8f828068 lw \$2,-32664\(\$28\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: 8f828048 lw \$2,-32696\(\$28\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: 8f82804c lw \$2,-32692\(\$28\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-got.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-got.rd new file mode 100644 index 0000000..db623b7 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-got.rd @@ -0,0 +1,179 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x1f + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 224 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo_iu_du_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 10100040 f_lo_du_ic_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 10100050 f_du_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100191 f_lo_iu_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 10100060 f_iu_du_ic +10200020 [^ ]+ R_MIPS_JUMP_SLOT 10100070 f_lo_du_ic +10200024 [^ ]+ R_MIPS_JUMP_SLOT 101001a1 f_iu_dc +10200028 [^ ]+ R_MIPS_JUMP_SLOT 10100080 f_lo_iu_ic +1020002c [^ ]+ R_MIPS_JUMP_SLOT 10100090 f_lo_ic +10200030 [^ ]+ R_MIPS_JUMP_SLOT 101000a0 f_lo_du_dc +10200034 [^ ]+ R_MIPS_JUMP_SLOT 101000b0 f_du +10200038 [^ ]+ R_MIPS_JUMP_SLOT 101000c0 f_du_ic_dc +1020003c [^ ]+ R_MIPS_JUMP_SLOT 101000d0 f_du_ic +10200040 [^ ]+ R_MIPS_JUMP_SLOT 101000e0 f_iu_du_dc +10200044 [^ ]+ R_MIPS_JUMP_SLOT 101001e1 f_lo_dc +10200048 [^ ]+ R_MIPS_JUMP_SLOT 101000f0 f_iu_du +1020004c [^ ]+ R_MIPS_JUMP_SLOT 10100100 f_lo_iu_du +10200050 [^ ]+ R_MIPS_JUMP_SLOT 101001f1 f_dc +10200054 [^ ]+ R_MIPS_JUMP_SLOT 10100201 f_ic_dc +10200058 [^ ]+ R_MIPS_JUMP_SLOT 10100110 f_lo_du +1020005c [^ ]+ R_MIPS_JUMP_SLOT 10100211 f_iu_ic_dc +10200060 [^ ]+ R_MIPS_JUMP_SLOT 10100120 f_iu_du_ic_dc +10200064 [^ ]+ R_MIPS_JUMP_SLOT 10100231 f_lo_iu_ic_dc +10200068 [^ ]+ R_MIPS_JUMP_SLOT 10100130 f_lo_iu_du_ic +1020006c [^ ]+ R_MIPS_JUMP_SLOT 10100140 f_lo_iu_du_ic_dc +10200070 [^ ]+ R_MIPS_JUMP_SLOT 10100251 f_lo_ic_dc +10200074 [^ ]+ R_MIPS_JUMP_SLOT 10100150 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# All symbols have their address taken, so PLT symbols need to have a nonzero +# value. They must also have STO_MIPS_PLT in order to distinguish them from +# old-style lazy-binding stubs). +# +# A MIPS16 PLT should only be used as the symbol value if the function has +# a direct MIPS16 caller (dc) and no direct MIPS caller (du). + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_dc +#... + .*: 10100040 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic_dc + .*: 10100050 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_dc + .*: 10100191 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_dc + .*: 10100060 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_ic + .*: 10100070 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic + .*: 101001a1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_dc + .*: 10100080 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic + .*: 10100090 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 101000a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_dc + .*: 101000b0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du + .*: 101000c0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_ic_dc + .*: 101000d0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_ic + .*: 101000e0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_dc + .*: 101001e1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 101000f0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du + .*: 10100100 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 101001f1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_dc + .*: 10100201 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_ic_dc + .*: 10100110 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du + .*: 10100211 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_ic_dc + .*: 10100120 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_ic_dc +#... + .*: 10100231 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic_dc + .*: 10100130 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic + .*: 10100140 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic_dc + .*: 10100251 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 10100150 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. Since the functions +# have their addresses taken, they cannot use a lazy-binding stub. +# The symbol values are therefore all zero. + 31: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_ic + 32: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic + 33: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu + 34: 00000000 0 FUNC GLOBAL DEFAULT UND f + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 10100201 + 1020100c -32740\(gp\) 101000d0 + 10201010 -32736\(gp\) 101000c0 + 10201014 -32732\(gp\) 10100211 + 10201018 -32728\(gp\) 10100060 + 1020101c -32724\(gp\) 10100120 + 10201020 -32720\(gp\) 10100090 + 10201024 -32716\(gp\) 10100251 + 10201028 -32712\(gp\) 10100070 + 1020102c -32708\(gp\) 10100040 + 10201030 -32704\(gp\) 10100080 + 10201034 -32700\(gp\) 10100231 + 10201038 -32696\(gp\) 10100130 + 1020103c -32692\(gp\) 10100140 + 10201040 -32688\(gp\) 101001a1 + 10201044 -32684\(gp\) 101000f0 + 10201048 -32680\(gp\) 101000e0 + 1020104c -32676\(gp\) 10100020 + 10201050 -32672\(gp\) 10100191 + 10201054 -32668\(gp\) 10100100 + 10201058 -32664\(gp\) 10100030 + 1020105c -32660\(gp\) 101001f1 + 10201060 -32656\(gp\) 101000b0 + 10201064 -32652\(gp\) 10100050 + 10201068 -32648\(gp\) 10100150 + 1020106c -32644\(gp\) 101001e1 + 10201070 -32640\(gp\) 10100110 + 10201074 -32636\(gp\) 101000a0 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 10201078 -32632\(gp\) 00000000 00000000 FUNC UND f_iu_ic + 1020107c -32628\(gp\) 00000000 00000000 FUNC UND f_ic + 10201080 -32624\(gp\) 00000000 00000000 FUNC UND f_iu + 10201084 -32620\(gp\) 00000000 00000000 FUNC UND f + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100020 FUNC UND f_lo_iu + 1020000c 10100000 10100030 FUNC UND f_lo_iu_du_dc + 10200010 10100000 10100040 FUNC UND f_lo_du_ic_dc + 10200014 10100000 10100050 FUNC UND f_du_dc + 10200018 10100000 10100191 FUNC UND f_lo_iu_dc + 1020001c 10100000 10100060 FUNC UND f_iu_du_ic + 10200020 10100000 10100070 FUNC UND f_lo_du_ic + 10200024 10100000 101001a1 FUNC UND f_iu_dc + 10200028 10100000 10100080 FUNC UND f_lo_iu_ic + 1020002c 10100000 10100090 FUNC UND f_lo_ic + 10200030 10100000 101000a0 FUNC UND f_lo_du_dc + 10200034 10100000 101000b0 FUNC UND f_du + 10200038 10100000 101000c0 FUNC UND f_du_ic_dc + 1020003c 10100000 101000d0 FUNC UND f_du_ic + 10200040 10100000 101000e0 FUNC UND f_iu_du_dc + 10200044 10100000 101001e1 FUNC UND f_lo_dc + 10200048 10100000 101000f0 FUNC UND f_iu_du + 1020004c 10100000 10100100 FUNC UND f_lo_iu_du + 10200050 10100000 101001f1 FUNC UND f_dc + 10200054 10100000 10100201 FUNC UND f_ic_dc + 10200058 10100000 10100110 FUNC UND f_lo_du + 1020005c 10100000 10100211 FUNC UND f_iu_ic_dc + 10200060 10100000 10100120 FUNC UND f_iu_du_ic_dc + 10200064 10100000 10100231 FUNC UND f_lo_iu_ic_dc + 10200068 10100000 10100130 FUNC UND f_lo_iu_du_ic + 1020006c 10100000 10100140 FUNC UND f_lo_iu_du_ic_dc + 10200070 10100000 10100251 FUNC UND f_lo_ic_dc + 10200074 10100000 10100150 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-only.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-only.od new file mode 100644 index 0000000..e76ca4f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-only.od @@ -0,0 +1,110 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# Only _dc (direct call from compressed code) functions should have a +# MIPS16 PLT. Note that indirect calls do not influence the choice, +# so f_ic and f_lo_ic have MIPS rather than MIPS16 PLTs. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c1c1020 lui \$28,0x1020 +.*: 8f990000 lw \$25,0\(\$28\) +.*: 279c0000 addiu \$28,\$28,0 +.*: 031cc023 subu \$24,\$24,\$28 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90008 lw \$25,8\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80008 addiu \$24,\$15,8 + +10100030 <f_lo@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100040 <f_lo_dc@mips16plt>: +.*: b203 lw \$2,1010004c <f_lo_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020000c + +10100050 <f_dc@mips16plt>: +.*: b203 lw \$2,1010005c <f_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200010 + +10100060 <f_ic_dc@mips16plt>: +.*: b203 lw \$2,1010006c <f_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200014 + +10100070 <f_lo_ic_dc@mips16plt>: +.*: b203 lw \$2,1010007c <f_lo_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200018 + +Disassembly of section \.MIPS\.stubs: + +10101000 <_MIPS_STUBS_>: +# Lazy-binding stub for f_ic. +.*: 8f998010 lw \$25,-32752\(\$28\) +.*: 03e07821 move \$15,\$31 +.*: 0320f809 jalr \$25 +.*: 24180009 li \$24,9 + \.\.\. + +Disassembly of section \.text\.a: + +10102000 <testc>: +.*: .... .... jal [0-9a-f]+ <f_dc@mips16plt> +.*: 6500 nop +.*: f030 9b44 lw \$2,-32732\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jal [0-9a-f]+ <f_ic_dc@mips16plt> +.*: 6500 nop +.*: f010 9b58 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_lo_dc@mips16plt> +.*: 6500 nop +.*: f010 9b5c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_lo_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b40 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@mips16plt +.*: e820 jr \$31 + +Disassembly of section \.text\.c: + +10103000 <testlo>: +.*: 24020030 li \$2,48 +# ^ low 16 bits of f_lo@plt +.*: 24020041 li \$2,65 +# ^ low 16 bits of f_lo_dc@mips16plt +.*: 24020020 li \$2,32 +# ^ low 16 bits of f_lo_ic@plt +.*: 24020071 li \$2,113 +# ^ low 16 bits of f_lo_ic_dc@mips16plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-only.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-only.rd new file mode 100644 index 0000000..a5d61be --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-only.rd @@ -0,0 +1,82 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x9 + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 48 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_ic +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100041 f_lo_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_ic_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100071 f_lo_ic_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# _lo symbols have their address taken, so their PLT symbols need to have +# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish +# them from old-style lazy-binding stubs. Non-_lo symbols are only called, +# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation. +# +# A MIPS16 PLT should only be used as the symbol value if the function has +# a direct MIPS16 caller (dc) and no direct MIPS caller (du). +#... + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 10100041 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic_dc +#... + .*: 10100071 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. The symbol value +# is the address of the lazy-binding stub. + 9: 10101000 0 FUNC GLOBAL DEFAULT UND f_ic + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 10100061 + 1020100c -32740\(gp\) 10100020 + 10201010 -32736\(gp\) 10100071 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 10201014 -32732\(gp\) 10101000 10101000 FUNC UND f_ic + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100020 FUNC UND f_lo_ic + 1020000c 10100000 10100041 FUNC UND f_lo_dc + 10200010 10100000 00000000 FUNC UND f_dc + 10200014 10100000 00000000 FUNC UND f_ic_dc + 10200018 10100000 10100071 FUNC UND f_lo_ic_dc + 1020001c 10100000 10100030 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-word.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-word.od new file mode 100644 index 0000000..7fc547b --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-word.od @@ -0,0 +1,489 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# Only _dc (direct call from compressed code) functions should have a +# MIPS16 PLT. Note that indirect calls do not influence the choice, +# so f_ic and f_lo_ic have MIPS rather than MIPS16 PLTs. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c1c1020 lui \$28,0x1020 +.*: 8f990000 lw \$25,0\(\$28\) +.*: 279c0000 addiu \$28,\$28,0 +.*: 031cc023 subu \$24,\$24,\$28 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90008 lw \$25,8\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80008 addiu \$24,\$15,8 + +10100030 <f_lo_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100040 <f_lo_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100050 <f_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100060 <f_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100070 <f_lo_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90020 lw \$25,32\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80020 addiu \$24,\$15,32 + +10100080 <f_lo_iu_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90028 lw \$25,40\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80028 addiu \$24,\$15,40 + +10100090 <f_lo_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9002c lw \$25,44\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8002c addiu \$24,\$15,44 + +101000a0 <f_lo_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90030 lw \$25,48\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80030 addiu \$24,\$15,48 + +101000b0 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90034 lw \$25,52\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80034 addiu \$24,\$15,52 + +101000c0 <f_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90038 lw \$25,56\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80038 addiu \$24,\$15,56 + +101000d0 <f_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9003c lw \$25,60\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8003c addiu \$24,\$15,60 + +101000e0 <f_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90040 lw \$25,64\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80040 addiu \$24,\$15,64 + +101000f0 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90048 lw \$25,72\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80048 addiu \$24,\$15,72 + +10100100 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9004c lw \$25,76\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8004c addiu \$24,\$15,76 + +10100110 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90058 lw \$25,88\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80058 addiu \$24,\$15,88 + +10100120 <f_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90060 lw \$25,96\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80060 addiu \$24,\$15,96 + +10100130 <f_lo_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90068 lw \$25,104\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80068 addiu \$24,\$15,104 + +10100140 <f_lo_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9006c lw \$25,108\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8006c addiu \$24,\$15,108 + +10100150 <f_lo@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90074 lw \$25,116\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80074 addiu \$24,\$15,116 + +10100160 <f_lo_iu_du_dc@mips16plt>: +.*: b203 lw \$2,1010016c <f_lo_iu_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020000c + +10100170 <f_lo_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010017c <f_lo_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200010 + +10100180 <f_du_dc@mips16plt>: +.*: b203 lw \$2,1010018c <f_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200014 + +10100190 <f_lo_iu_dc@mips16plt>: +.*: b203 lw \$2,1010019c <f_lo_iu_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200018 + +101001a0 <f_iu_dc@mips16plt>: +.*: b203 lw \$2,101001ac <f_iu_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200024 + +101001b0 <f_lo_du_dc@mips16plt>: +.*: b203 lw \$2,101001bc <f_lo_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200030 + +101001c0 <f_du_ic_dc@mips16plt>: +.*: b203 lw \$2,101001cc <f_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200038 + +101001d0 <f_iu_du_dc@mips16plt>: +.*: b203 lw \$2,101001dc <f_iu_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200040 + +101001e0 <f_lo_dc@mips16plt>: +.*: b203 lw \$2,101001ec <f_lo_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200044 + +101001f0 <f_dc@mips16plt>: +.*: b203 lw \$2,101001fc <f_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200050 + +10100200 <f_ic_dc@mips16plt>: +.*: b203 lw \$2,1010020c <f_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200054 + +10100210 <f_iu_ic_dc@mips16plt>: +.*: b203 lw \$2,1010021c <f_iu_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020005c + +10100220 <f_iu_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010022c <f_iu_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200060 + +10100230 <f_lo_iu_ic_dc@mips16plt>: +.*: b203 lw \$2,1010023c <f_lo_iu_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200064 + +10100240 <f_lo_iu_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010024c <f_lo_iu_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020006c + +10100250 <f_lo_ic_dc@mips16plt>: +.*: b203 lw \$2,1010025c <f_lo_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200070 + +Disassembly of section \.text\.a: + +10101000 <testc>: +.*: .... .... jal [0-9a-f]+ <f_dc@mips16plt> +.*: 6500 nop +.*: f070 9b50 lw \$2,-32656\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jal [0-9a-f]+ <f_ic_dc@mips16plt> +.*: 6500 nop +.*: f010 9b58 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_du_dc@mips16plt> +.*: 6500 nop +.*: f010 9b5c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b40 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_iu_dc@mips16plt> +.*: 6500 nop +.*: f070 9b4c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: .... .... jal [0-9a-f]+ <f_iu_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b44 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_dc@mips16plt> +.*: 6500 nop +.*: f030 9b48 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b4c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_dc@mips16plt> +.*: 6500 nop +.*: f030 9b50 lw \$2,-32720\(\$3\) +# ^ local GOT entry for f_lo_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b54 lw \$2,-32716\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_dc@mips16plt> +.*: 6500 nop +.*: f030 9b58 lw \$2,-32712\(\$3\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b5c lw \$2,-32708\(\$3\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_dc@mips16plt> +.*: 6500 nop +.*: f050 9b40 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_ic_dc@mips16plt> +.*: 6500 nop +.*: f050 9b44 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_dc@mips16plt> +.*: 6500 nop +.*: f050 9b48 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f050 9b4c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: e820 jr \$31 + +Disassembly of section \.text\.b: + +10102000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c628074 lw \$2,-32652\(\$3\) +# ^ global GOT entry for f_iu +.*: 8c628050 lw \$2,-32688\(\$3\) +# ^ local GOT entry for f_iu_dc@mips16plt +.*: 8c62806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@mips16plt +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628054 lw \$2,-32684\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628058 lw \$2,-32680\(\$3\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62805c lw \$2,-32676\(\$3\) +# ^ local GOT entry for f_lo_iu@plt +.*: 8c628060 lw \$2,-32672\(\$3\) +# ^ local GOT entry for f_lo_iu_dc@mips16plt +.*: 8c628040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: 8c628044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@mips16plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628064 lw \$2,-32668\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628068 lw \$2,-32664\(\$3\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10103000 <testlo>: +.*: 24020150 li \$2,336 +# ^ low 16 bits of f_lo@plt +.*: 240201e1 li \$2,481 +# ^ low 16 bits of f_lo_dc@mips16plt +.*: 24020090 li \$2,144 +# ^ low 16 bits of f_lo_ic@plt +.*: 24020251 li \$2,593 +# ^ low 16 bits of f_lo_ic_dc@mips16plt +.*: 24020110 li \$2,272 +# ^ low 16 bits of f_lo_du@plt +.*: 240200a0 li \$2,160 +# ^ low 16 bits of f_lo_du_dc@plt +.*: 24020070 li \$2,112 +# ^ low 16 bits of f_lo_du_ic@plt +.*: 24020040 li \$2,64 +# ^ low 16 bits of f_lo_du_ic_dc@plt +.*: 24020020 li \$2,32 +# ^ low 16 bits of f_lo_iu@plt +.*: 24020191 li \$2,401 +# ^ low 16 bits of f_lo_iu_dc@mips16plt +.*: 24020080 li \$2,128 +# ^ low 16 bits of f_lo_iu_ic@plt +.*: 24020231 li \$2,561 +# ^ low 16 bits of f_lo_iu_ic_dc@mips16plt +.*: 24020100 li \$2,256 +# ^ low 16 bits of f_lo_iu_du@plt +.*: 24020030 li \$2,48 +# ^ low 16 bits of f_lo_iu_du_dc@plt +.*: 24020130 li \$2,304 +# ^ low 16 bits of f_lo_iu_du_ic@plt +.*: 24020140 li \$2,320 +# ^ low 16 bits of f_lo_iu_du_ic_dc@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-word.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-word.rd new file mode 100644 index 0000000..3ddec9b --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-word.rd @@ -0,0 +1,198 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10202000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x1f + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10005000 + 0x00000002 \(PLTRELSZ\) 224 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.dyn' .* +# All symbols are referenced by a .word in the .data section, so pointer +# equality matters. If a PLT is needed to satisfy a direct call or %lo +# relocation, the symbol should have a nonzero value and there should be +# no dynamic relocations against it. The only relocations here are for +# undefined 0-value symbols. Note that unlike x86, we do not create a PLT +# for the uncalled symbol 'f' in order to maintain backward compatibility +# with pre-PLT ld.sos. + Offset Info Type Sym\.Value Sym\. Name +00000000 00000000 R_MIPS_NONE +10201028 00001f03 R_MIPS_REL32 00000000 f_iu_ic +10201008 00002003 R_MIPS_REL32 00000000 f_ic +10201020 00002103 R_MIPS_REL32 00000000 f_iu +10201000 00002203 R_MIPS_REL32 00000000 f + +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo_iu_du_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 10100040 f_lo_du_ic_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 10100050 f_du_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100191 f_lo_iu_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 10100060 f_iu_du_ic +10200020 [^ ]+ R_MIPS_JUMP_SLOT 10100070 f_lo_du_ic +10200024 [^ ]+ R_MIPS_JUMP_SLOT 101001a1 f_iu_dc +10200028 [^ ]+ R_MIPS_JUMP_SLOT 10100080 f_lo_iu_ic +1020002c [^ ]+ R_MIPS_JUMP_SLOT 10100090 f_lo_ic +10200030 [^ ]+ R_MIPS_JUMP_SLOT 101000a0 f_lo_du_dc +10200034 [^ ]+ R_MIPS_JUMP_SLOT 101000b0 f_du +10200038 [^ ]+ R_MIPS_JUMP_SLOT 101000c0 f_du_ic_dc +1020003c [^ ]+ R_MIPS_JUMP_SLOT 101000d0 f_du_ic +10200040 [^ ]+ R_MIPS_JUMP_SLOT 101000e0 f_iu_du_dc +10200044 [^ ]+ R_MIPS_JUMP_SLOT 101001e1 f_lo_dc +10200048 [^ ]+ R_MIPS_JUMP_SLOT 101000f0 f_iu_du +1020004c [^ ]+ R_MIPS_JUMP_SLOT 10100100 f_lo_iu_du +10200050 [^ ]+ R_MIPS_JUMP_SLOT 101001f1 f_dc +10200054 [^ ]+ R_MIPS_JUMP_SLOT 10100201 f_ic_dc +10200058 [^ ]+ R_MIPS_JUMP_SLOT 10100110 f_lo_du +1020005c [^ ]+ R_MIPS_JUMP_SLOT 10100211 f_iu_ic_dc +10200060 [^ ]+ R_MIPS_JUMP_SLOT 10100120 f_iu_du_ic_dc +10200064 [^ ]+ R_MIPS_JUMP_SLOT 10100231 f_lo_iu_ic_dc +10200068 [^ ]+ R_MIPS_JUMP_SLOT 10100130 f_lo_iu_du_ic +1020006c [^ ]+ R_MIPS_JUMP_SLOT 10100140 f_lo_iu_du_ic_dc +10200070 [^ ]+ R_MIPS_JUMP_SLOT 10100251 f_lo_ic_dc +10200074 [^ ]+ R_MIPS_JUMP_SLOT 10100150 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# All symbols have their address taken, so PLT symbols need to have a nonzero +# value. They must also have STO_MIPS_PLT in order to distinguish them from +# old-style lazy-binding stubs). +# +# A MIPS16 PLT should only be used as the symbol value if the function has +# a direct MIPS16 caller (dc) and no direct MIPS caller (du). + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_dc +#... + .*: 10100040 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic_dc + .*: 10100050 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_dc + .*: 10100191 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_dc + .*: 10100060 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_ic + .*: 10100070 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic + .*: 101001a1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_dc + .*: 10100080 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic + .*: 10100090 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 101000a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_dc + .*: 101000b0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du + .*: 101000c0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_ic_dc + .*: 101000d0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_ic + .*: 101000e0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_dc + .*: 101001e1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 101000f0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du + .*: 10100100 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 101001f1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_dc + .*: 10100201 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_ic_dc + .*: 10100110 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du + .*: 10100211 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_ic_dc + .*: 10100120 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_ic_dc +#... + .*: 10100231 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic_dc + .*: 10100130 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic + .*: 10100140 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic_dc + .*: 10100251 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 10100150 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. Since the functions +# have their addresses taken, they cannot use a lazy-binding stub. +# The symbol values are therefore all zero. + 31: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_ic + 32: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic + 33: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu + 34: 00000000 0 FUNC GLOBAL DEFAULT UND f + +Symbol table '\.symtab' .* +#... +Hex dump of section '\.data': + 0x10201000 (00000000|00000000) (101001f1|f1011010) (00000000|00000000) (10100201|01021010) .* + 0x10201010 (101000b0|b0001010) (10100050|50001010) (101000d0|d0001010) (101000c0|c0001010) .* + 0x10201020 (00000000|00000000) (101001a1|a1011010) (00000000|00000000) (10100211|11021010) .* + 0x10201030 (101000f0|f0001010) (101000e0|e0001010) (10100060|60001010) (10100120|20011010) .* + 0x10201040 (10100150|50011010) (101001e1|e1011010) (10100090|90001010) (10100251|51021010) .* + 0x10201050 (10100110|10011010) (101000a0|a0001010) (10100070|70001010) (10100040|40001010) .* + 0x10201060 (10100020|20001010) (10100191|91011010) (10100080|80001010) (10100231|31021010) .* + 0x10201070 (10100100|00011010) (10100030|30001010) (10100130|30011010) (10100140|40011010) .* + + +Primary GOT: + Canonical gp value: 10209ff0 + + Reserved entries: + Address Access Initial Purpose + 10202000 -32752\(gp\) 00000000 Lazy resolver + 10202004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10202008 -32744\(gp\) 10100201 + 1020200c -32740\(gp\) 101000d0 + 10202010 -32736\(gp\) 101000c0 + 10202014 -32732\(gp\) 10100211 + 10202018 -32728\(gp\) 10100060 + 1020201c -32724\(gp\) 10100120 + 10202020 -32720\(gp\) 10100090 + 10202024 -32716\(gp\) 10100251 + 10202028 -32712\(gp\) 10100070 + 1020202c -32708\(gp\) 10100040 + 10202030 -32704\(gp\) 10100080 + 10202034 -32700\(gp\) 10100231 + 10202038 -32696\(gp\) 10100130 + 1020203c -32692\(gp\) 10100140 + 10202040 -32688\(gp\) 101001a1 + 10202044 -32684\(gp\) 101000f0 + 10202048 -32680\(gp\) 101000e0 + 1020204c -32676\(gp\) 10100020 + 10202050 -32672\(gp\) 10100191 + 10202054 -32668\(gp\) 10100100 + 10202058 -32664\(gp\) 10100030 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 1020205c -32660\(gp\) 00000000 00000000 FUNC UND f_iu_ic + 10202060 -32656\(gp\) 00000000 00000000 FUNC UND f_ic + 10202064 -32652\(gp\) 00000000 00000000 FUNC UND f_iu + 10202068 -32648\(gp\) 00000000 00000000 FUNC UND f + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100020 FUNC UND f_lo_iu + 1020000c 10100000 10100030 FUNC UND f_lo_iu_du_dc + 10200010 10100000 10100040 FUNC UND f_lo_du_ic_dc + 10200014 10100000 10100050 FUNC UND f_du_dc + 10200018 10100000 10100191 FUNC UND f_lo_iu_dc + 1020001c 10100000 10100060 FUNC UND f_iu_du_ic + 10200020 10100000 10100070 FUNC UND f_lo_du_ic + 10200024 10100000 101001a1 FUNC UND f_iu_dc + 10200028 10100000 10100080 FUNC UND f_lo_iu_ic + 1020002c 10100000 10100090 FUNC UND f_lo_ic + 10200030 10100000 101000a0 FUNC UND f_lo_du_dc + 10200034 10100000 101000b0 FUNC UND f_du + 10200038 10100000 101000c0 FUNC UND f_du_ic_dc + 1020003c 10100000 101000d0 FUNC UND f_du_ic + 10200040 10100000 101000e0 FUNC UND f_iu_du_dc + 10200044 10100000 101001e1 FUNC UND f_lo_dc + 10200048 10100000 101000f0 FUNC UND f_iu_du + 1020004c 10100000 10100100 FUNC UND f_lo_iu_du + 10200050 10100000 101001f1 FUNC UND f_dc + 10200054 10100000 10100201 FUNC UND f_ic_dc + 10200058 10100000 10100110 FUNC UND f_lo_du + 1020005c 10100000 10100211 FUNC UND f_iu_ic_dc + 10200060 10100000 10100120 FUNC UND f_iu_du_ic_dc + 10200064 10100000 10100231 FUNC UND f_lo_iu_ic_dc + 10200068 10100000 10100130 FUNC UND f_lo_iu_du_ic + 1020006c 10100000 10100140 FUNC UND f_lo_iu_du_ic_dc + 10200070 10100000 10100251 FUNC UND f_lo_ic_dc + 10200074 10100000 10100150 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16.od new file mode 100644 index 0000000..712e651 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16.od @@ -0,0 +1,509 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# Only _dc (direct call from compressed code) functions should have a +# MIPS16 PLT. Note that indirect calls do not influence the choice, +# so f_ic and f_lo_ic have MIPS rather than MIPS16 PLTs. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c1c1020 lui \$28,0x1020 +.*: 8f990000 lw \$25,0\(\$28\) +.*: 279c0000 addiu \$28,\$28,0 +.*: 031cc023 subu \$24,\$24,\$28 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90008 lw \$25,8\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80008 addiu \$24,\$15,8 + +10100030 <f_lo_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100040 <f_lo_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100050 <f_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100060 <f_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100070 <f_lo_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90020 lw \$25,32\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80020 addiu \$24,\$15,32 + +10100080 <f_lo_iu_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90028 lw \$25,40\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80028 addiu \$24,\$15,40 + +10100090 <f_lo_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9002c lw \$25,44\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8002c addiu \$24,\$15,44 + +101000a0 <f_lo_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90030 lw \$25,48\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80030 addiu \$24,\$15,48 + +101000b0 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90034 lw \$25,52\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80034 addiu \$24,\$15,52 + +101000c0 <f_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90038 lw \$25,56\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80038 addiu \$24,\$15,56 + +101000d0 <f_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9003c lw \$25,60\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8003c addiu \$24,\$15,60 + +101000e0 <f_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90040 lw \$25,64\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80040 addiu \$24,\$15,64 + +101000f0 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90048 lw \$25,72\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80048 addiu \$24,\$15,72 + +10100100 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9004c lw \$25,76\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8004c addiu \$24,\$15,76 + +10100110 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90058 lw \$25,88\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80058 addiu \$24,\$15,88 + +10100120 <f_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90060 lw \$25,96\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80060 addiu \$24,\$15,96 + +10100130 <f_lo_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90068 lw \$25,104\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80068 addiu \$24,\$15,104 + +10100140 <f_lo_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9006c lw \$25,108\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8006c addiu \$24,\$15,108 + +10100150 <f_lo@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90074 lw \$25,116\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80074 addiu \$24,\$15,116 + +10100160 <f_lo_iu_du_dc@mips16plt>: +.*: b203 lw \$2,1010016c <f_lo_iu_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020000c + +10100170 <f_lo_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010017c <f_lo_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200010 + +10100180 <f_du_dc@mips16plt>: +.*: b203 lw \$2,1010018c <f_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200014 + +10100190 <f_lo_iu_dc@mips16plt>: +.*: b203 lw \$2,1010019c <f_lo_iu_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200018 + +101001a0 <f_iu_dc@mips16plt>: +.*: b203 lw \$2,101001ac <f_iu_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200024 + +101001b0 <f_lo_du_dc@mips16plt>: +.*: b203 lw \$2,101001bc <f_lo_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200030 + +101001c0 <f_du_ic_dc@mips16plt>: +.*: b203 lw \$2,101001cc <f_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200038 + +101001d0 <f_iu_du_dc@mips16plt>: +.*: b203 lw \$2,101001dc <f_iu_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200040 + +101001e0 <f_lo_dc@mips16plt>: +.*: b203 lw \$2,101001ec <f_lo_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200044 + +101001f0 <f_dc@mips16plt>: +.*: b203 lw \$2,101001fc <f_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200050 + +10100200 <f_ic_dc@mips16plt>: +.*: b203 lw \$2,1010020c <f_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200054 + +10100210 <f_iu_ic_dc@mips16plt>: +.*: b203 lw \$2,1010021c <f_iu_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020005c + +10100220 <f_iu_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010022c <f_iu_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200060 + +10100230 <f_lo_iu_ic_dc@mips16plt>: +.*: b203 lw \$2,1010023c <f_lo_iu_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200064 + +10100240 <f_lo_iu_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010024c <f_lo_iu_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020006c + +10100250 <f_lo_ic_dc@mips16plt>: +.*: b203 lw \$2,1010025c <f_lo_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200070 + +Disassembly of section \.MIPS\.stubs: + +10101000 <_MIPS_STUBS_>: +# Lazy-binding stub for f_iu. +.*: 8f998010 lw \$25,-32752\(\$28\) +.*: 03e07821 move \$15,\$31 +.*: 0320f809 jalr \$25 +.*: 24180021 li \$24,33 +# Lazy-binding stub for f_ic. +.*: 8f998010 lw \$25,-32752\(\$28\) +.*: 03e07821 move \$15,\$31 +.*: 0320f809 jalr \$25 +.*: 24180020 li \$24,32 +# Lazy-binding stub for f_iu_ic. +.*: 8f998010 lw \$25,-32752\(\$28\) +.*: 03e07821 move \$15,\$31 +.*: 0320f809 jalr \$25 +.*: 2418001f li \$24,31 + \.\.\. + +Disassembly of section \.text\.a: + +10102000 <testc>: +.*: .... .... jal [0-9a-f]+ <f_dc@mips16plt> +.*: 6500 nop +.*: f070 9b50 lw \$2,-32656\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jal [0-9a-f]+ <f_ic_dc@mips16plt> +.*: 6500 nop +.*: f010 9b58 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_du_dc@mips16plt> +.*: 6500 nop +.*: f010 9b5c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b40 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_iu_dc@mips16plt> +.*: 6500 nop +.*: f070 9b4c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: .... .... jal [0-9a-f]+ <f_iu_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b44 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_dc@mips16plt> +.*: 6500 nop +.*: f030 9b48 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b4c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_dc@mips16plt> +.*: 6500 nop +.*: f030 9b50 lw \$2,-32720\(\$3\) +# ^ local GOT entry for f_lo_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b54 lw \$2,-32716\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_dc@mips16plt> +.*: 6500 nop +.*: f030 9b58 lw \$2,-32712\(\$3\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b5c lw \$2,-32708\(\$3\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_dc@mips16plt> +.*: 6500 nop +.*: f050 9b40 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_ic_dc@mips16plt> +.*: 6500 nop +.*: f050 9b44 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_dc@mips16plt> +.*: 6500 nop +.*: f050 9b48 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f050 9b4c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: e820 jr \$31 + +Disassembly of section \.text\.b: + +10103000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c628074 lw \$2,-32652\(\$3\) +# ^ global GOT entry for f_iu +.*: 8c628050 lw \$2,-32688\(\$3\) +# ^ local GOT entry for f_iu_dc@mips16plt +.*: 8c62806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@mips16plt +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628054 lw \$2,-32684\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628058 lw \$2,-32680\(\$3\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62805c lw \$2,-32676\(\$3\) +# ^ local GOT entry for f_lo_iu@plt +.*: 8c628060 lw \$2,-32672\(\$3\) +# ^ local GOT entry for f_lo_iu_dc@mips16plt +.*: 8c628040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: 8c628044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@mips16plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628064 lw \$2,-32668\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628068 lw \$2,-32664\(\$3\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10104000 <testlo>: +.*: 24020150 li \$2,336 +# ^ low 16 bits of f_lo@plt +.*: 240201e1 li \$2,481 +# ^ low 16 bits of f_lo_dc@mips16plt +.*: 24020090 li \$2,144 +# ^ low 16 bits of f_lo_ic@plt +.*: 24020251 li \$2,593 +# ^ low 16 bits of f_lo_ic_dc@mips16plt +.*: 24020110 li \$2,272 +# ^ low 16 bits of f_lo_du@plt +.*: 240200a0 li \$2,160 +# ^ low 16 bits of f_lo_du_dc@plt +.*: 24020070 li \$2,112 +# ^ low 16 bits of f_lo_du_ic@plt +.*: 24020040 li \$2,64 +# ^ low 16 bits of f_lo_du_ic_dc@plt +.*: 24020020 li \$2,32 +# ^ low 16 bits of f_lo_iu@plt +.*: 24020191 li \$2,401 +# ^ low 16 bits of f_lo_iu_dc@mips16plt +.*: 24020080 li \$2,128 +# ^ low 16 bits of f_lo_iu_ic@plt +.*: 24020231 li \$2,561 +# ^ low 16 bits of f_lo_iu_ic_dc@mips16plt +.*: 24020100 li \$2,256 +# ^ low 16 bits of f_lo_iu_du@plt +.*: 24020030 li \$2,48 +# ^ low 16 bits of f_lo_iu_du_dc@plt +.*: 24020130 li \$2,304 +# ^ low 16 bits of f_lo_iu_du_ic@plt +.*: 24020140 li \$2,320 +# ^ low 16 bits of f_lo_iu_du_ic_dc@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16.rd new file mode 100644 index 0000000..dc8a7c7 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16.rd @@ -0,0 +1,170 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x1f + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 224 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo_iu_du_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 10100040 f_lo_du_ic_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100191 f_lo_iu_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_ic +10200020 [^ ]+ R_MIPS_JUMP_SLOT 10100070 f_lo_du_ic +10200024 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_dc +10200028 [^ ]+ R_MIPS_JUMP_SLOT 10100080 f_lo_iu_ic +1020002c [^ ]+ R_MIPS_JUMP_SLOT 10100090 f_lo_ic +10200030 [^ ]+ R_MIPS_JUMP_SLOT 101000a0 f_lo_du_dc +10200034 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du +10200038 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_ic_dc +1020003c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_ic +10200040 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_dc +10200044 [^ ]+ R_MIPS_JUMP_SLOT 101001e1 f_lo_dc +10200048 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du +1020004c [^ ]+ R_MIPS_JUMP_SLOT 10100100 f_lo_iu_du +10200050 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_dc +10200054 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_ic_dc +10200058 [^ ]+ R_MIPS_JUMP_SLOT 10100110 f_lo_du +1020005c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_ic_dc +10200060 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_ic_dc +10200064 [^ ]+ R_MIPS_JUMP_SLOT 10100231 f_lo_iu_ic_dc +10200068 [^ ]+ R_MIPS_JUMP_SLOT 10100130 f_lo_iu_du_ic +1020006c [^ ]+ R_MIPS_JUMP_SLOT 10100140 f_lo_iu_du_ic_dc +10200070 [^ ]+ R_MIPS_JUMP_SLOT 10100251 f_lo_ic_dc +10200074 [^ ]+ R_MIPS_JUMP_SLOT 10100150 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# _lo symbols have their address taken, so their PLT symbols need to have +# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish +# them from old-style lazy-binding stubs. Non-_lo symbols are only called, +# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation. +# +# A MIPS16 PLT should only be used as the symbol value if the function has +# a direct MIPS16 caller (dc) and no direct MIPS caller (du). + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_dc +#... + .*: 10100040 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_dc + .*: 10100191 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_ic + .*: 10100070 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_dc + .*: 10100080 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic + .*: 10100090 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 101000a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_ic + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_dc + .*: 101001e1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du + .*: 10100100 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic_dc + .*: 10100110 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_ic_dc +#... + .*: 10100231 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic_dc + .*: 10100130 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic + .*: 10100140 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic_dc + .*: 10100251 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 10100150 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. The symbol value +# is the address of the lazy-binding stub. + 31: 10101020 0 FUNC GLOBAL DEFAULT UND f_iu_ic + 32: 10101010 0 FUNC GLOBAL DEFAULT UND f_ic + 33: 10101000 0 FUNC GLOBAL DEFAULT UND f_iu + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 10100201 + 1020100c -32740\(gp\) 101000d0 + 10201010 -32736\(gp\) 101000c0 + 10201014 -32732\(gp\) 10100211 + 10201018 -32728\(gp\) 10100060 + 1020101c -32724\(gp\) 10100120 + 10201020 -32720\(gp\) 10100090 + 10201024 -32716\(gp\) 10100251 + 10201028 -32712\(gp\) 10100070 + 1020102c -32708\(gp\) 10100040 + 10201030 -32704\(gp\) 10100080 + 10201034 -32700\(gp\) 10100231 + 10201038 -32696\(gp\) 10100130 + 1020103c -32692\(gp\) 10100140 + 10201040 -32688\(gp\) 101001a1 + 10201044 -32684\(gp\) 101000f0 + 10201048 -32680\(gp\) 101000e0 + 1020104c -32676\(gp\) 10100020 + 10201050 -32672\(gp\) 10100191 + 10201054 -32668\(gp\) 10100100 + 10201058 -32664\(gp\) 10100030 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 1020105c -32660\(gp\) 10101020 10101020 FUNC UND f_iu_ic + 10201060 -32656\(gp\) 10101010 10101010 FUNC UND f_ic + 10201064 -32652\(gp\) 10101000 10101000 FUNC UND f_iu + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100020 FUNC UND f_lo_iu + 1020000c 10100000 10100030 FUNC UND f_lo_iu_du_dc + 10200010 10100000 10100040 FUNC UND f_lo_du_ic_dc + 10200014 10100000 00000000 FUNC UND f_du_dc + 10200018 10100000 10100191 FUNC UND f_lo_iu_dc + 1020001c 10100000 00000000 FUNC UND f_iu_du_ic + 10200020 10100000 10100070 FUNC UND f_lo_du_ic + 10200024 10100000 00000000 FUNC UND f_iu_dc + 10200028 10100000 10100080 FUNC UND f_lo_iu_ic + 1020002c 10100000 10100090 FUNC UND f_lo_ic + 10200030 10100000 101000a0 FUNC UND f_lo_du_dc + 10200034 10100000 00000000 FUNC UND f_du + 10200038 10100000 00000000 FUNC UND f_du_ic_dc + 1020003c 10100000 00000000 FUNC UND f_du_ic + 10200040 10100000 00000000 FUNC UND f_iu_du_dc + 10200044 10100000 101001e1 FUNC UND f_lo_dc + 10200048 10100000 00000000 FUNC UND f_iu_du + 1020004c 10100000 10100100 FUNC UND f_lo_iu_du + 10200050 10100000 00000000 FUNC UND f_dc + 10200054 10100000 00000000 FUNC UND f_ic_dc + 10200058 10100000 10100110 FUNC UND f_lo_du + 1020005c 10100000 00000000 FUNC UND f_iu_ic_dc + 10200060 10100000 00000000 FUNC UND f_iu_du_ic_dc + 10200064 10100000 10100231 FUNC UND f_lo_iu_ic_dc + 10200068 10100000 10100130 FUNC UND f_lo_iu_du_ic + 1020006c 10100000 10100140 FUNC UND f_lo_iu_du_ic_dc + 10200070 10100000 10100251 FUNC UND f_lo_ic_dc + 10200074 10100000 10100150 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-se.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-se.od new file mode 100644 index 0000000..6e0d15a --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-se.od @@ -0,0 +1,103 @@ + +.* file format .* + + +Disassembly of section \.plt: + +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c1c1020 lui \$28,0x1020 +.*: 8f990000 lw \$25,0\(\$28\) +.*: 279c0000 addiu \$28,\$28,0 +.*: 031cc023 subu \$24,\$24,\$28 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90008 lw \$25,8\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80008 addiu \$24,\$15,8 + +10100030 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100040 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100050 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100060 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90018 lw \$25,24\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80018 addiu \$24,\$15,24 + +10100070 <f_lo@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +Disassembly of section \.MIPS\.stubs: + +10101000 <_MIPS_STUBS_>: +# Lazy-binding stub for f_iu. +.*: 8f998010 lw \$25,-32752\(\$28\) +.*: 03e07821 move \$15,\$31 +.*: 0320f809 jalr \$25 +.*: 24180009 li \$24,9 + \.\.\. + +Disassembly of section \.text\.b: + +10102000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ global GOT entry for f_iu +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628018 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: 8c62801c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_lo_iu@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628020 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10103000 <testlo>: +.*: 24020070 li \$2,112 +# ^ low 16 bits of f_lo@plt +.*: 24020060 li \$2,96 +# ^ low 16 bits of f_lo_du@plt +.*: 24020020 li \$2,32 +# ^ low 16 bits of f_lo_iu@plt +.*: 24020050 li \$2,80 +# ^ low 16 bits of f_lo_iu_du@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-se.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-se.rd new file mode 100644 index 0000000..fa23221 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-se.rd @@ -0,0 +1,79 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x9 + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 48 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du +10200010 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du +10200014 [^ ]+ R_MIPS_JUMP_SLOT 10100050 f_lo_iu_du +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100060 f_lo_du +1020001c [^ ]+ R_MIPS_JUMP_SLOT 10100070 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# _lo symbols have their address taken, so their PLT symbols need to have +# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish +# them from old-style lazy-binding stubs. Non-_lo symbols are only called, +# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation. + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu +#... + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du + .*: 10100050 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 10100060 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du +#... + .*: 10100070 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. The symbol value +# is the address of the lazy-binding stub. + 9: 10101000 0 FUNC GLOBAL DEFAULT UND f_iu + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 10100040 + 1020100c -32740\(gp\) 10100020 + 10201010 -32736\(gp\) 10100050 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 10201014 -32732\(gp\) 10101000 10101000 FUNC UND f_iu + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100020 FUNC UND f_lo_iu + 1020000c 10100000 00000000 FUNC UND f_du + 10200010 10100000 00000000 FUNC UND f_iu_du + 10200014 10100000 10100050 FUNC UND f_lo_iu_du + 10200018 10100000 10100060 FUNC UND f_lo_du + 1020001c 10100000 10100070 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-got.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-got.od new file mode 100644 index 0000000..2d7b513 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-got.od @@ -0,0 +1,560 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# Only _du (direct call from uncompressed code) functions should have +# non-microMIPS PLTs. All the rest must be microMIPS. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c1c1020 lui \$28,0x1020 +.*: 8f990000 lw \$25,0\(\$28\) +.*: 279c0000 addiu \$28,\$28,0 +.*: 031cc023 subu \$24,\$24,\$28 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100030 <f_lo_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100040 <f_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100050 <f_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100060 <f_lo_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90020 lw \$25,32\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80020 addiu \$24,\$15,32 + +10100070 <f_lo_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90030 lw \$25,48\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80030 addiu \$24,\$15,48 + +10100080 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90034 lw \$25,52\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80034 addiu \$24,\$15,52 + +10100090 <f_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90038 lw \$25,56\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80038 addiu \$24,\$15,56 + +101000a0 <f_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9003c lw \$25,60\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8003c addiu \$24,\$15,60 + +101000b0 <f_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90040 lw \$25,64\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80040 addiu \$24,\$15,64 + +101000c0 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90048 lw \$25,72\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80048 addiu \$24,\$15,72 + +101000d0 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9004c lw \$25,76\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8004c addiu \$24,\$15,76 + +101000e0 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90058 lw \$25,88\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80058 addiu \$24,\$15,88 + +101000f0 <f_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90060 lw \$25,96\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80060 addiu \$24,\$15,96 + +10100100 <f_lo_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90068 lw \$25,104\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80068 addiu \$24,\$15,104 + +10100110 <f_lo_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9006c lw \$25,108\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8006c addiu \$24,\$15,108 + +10100120 <f_lo_iu@micromipsplt>: +.*: 7903 ffba addiu \$2,\$pc,1048296 +# ^ 0x10200008 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010012c <f_lo_iu_du_dc@micromipsplt>: +.*: 7903 ffb8 addiu \$2,\$pc,1048288 +# ^ 0x1020000c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100138 <f_lo_du_ic_dc@micromipsplt>: +.*: 7903 ffb6 addiu \$2,\$pc,1048280 +# ^ 0x10200010 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100144 <f_du_dc@micromipsplt>: +.*: 7903 ffb4 addiu \$2,\$pc,1048272 +# ^ 0x10200014 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100150 <f_lo_iu_dc@micromipsplt>: +.*: 7903 ffb2 addiu \$2,\$pc,1048264 +# ^ 0x10200018 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010015c <f_iu_dc@micromipsplt>: +.*: 7903 ffb2 addiu \$2,\$pc,1048264 +# ^ 0x10200024 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100168 <f_lo_iu_ic@micromipsplt>: +.*: 7903 ffb0 addiu \$2,\$pc,1048256 +# ^ 0x10200028 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100174 <f_lo_ic@micromipsplt>: +.*: 7903 ffae addiu \$2,\$pc,1048248 +# ^ 0x1020002c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100180 <f_lo_du_dc@micromipsplt>: +.*: 7903 ffac addiu \$2,\$pc,1048240 +# ^ 0x10200030 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010018c <f_du_ic_dc@micromipsplt>: +.*: 7903 ffab addiu \$2,\$pc,1048236 +# ^ 0x10200038 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100198 <f_iu_du_dc@micromipsplt>: +.*: 7903 ffaa addiu \$2,\$pc,1048232 +# ^ 0x10200040 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001a4 <f_lo_dc@micromipsplt>: +.*: 7903 ffa8 addiu \$2,\$pc,1048224 +# ^ 0x10200044 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001b0 <f_dc@micromipsplt>: +.*: 7903 ffa8 addiu \$2,\$pc,1048224 +# ^ 0x10200050 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001bc <f_ic_dc@micromipsplt>: +.*: 7903 ffa6 addiu \$2,\$pc,1048216 +# ^ 0x10200054 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001c8 <f_iu_ic_dc@micromipsplt>: +.*: 7903 ffa5 addiu \$2,\$pc,1048212 +# ^ 0x1020005c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001d4 <f_iu_du_ic_dc@micromipsplt>: +.*: 7903 ffa3 addiu \$2,\$pc,1048204 +# ^ 0x10200060 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001e0 <f_lo_iu_ic_dc@micromipsplt>: +.*: 7903 ffa1 addiu \$2,\$pc,1048196 +# ^ 0x10200064 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001ec <f_lo_iu_du_ic_dc@micromipsplt>: +.*: 7903 ffa0 addiu \$2,\$pc,1048192 +# ^ 0x1020006c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001f8 <f_lo_ic_dc@micromipsplt>: +.*: 7903 ff9e addiu \$2,\$pc,1048184 +# ^ 0x10200070 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100204 <f_lo@micromipsplt>: +.*: 7903 ff9c addiu \$2,\$pc,1048176 +# ^ 0x10200074 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +Disassembly of section \.text\.a: + +10101000 <testc>: +.*: .... .... jal [0-9a-f]+ <f_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 808c lw \$2,-32628\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jal [0-9a-f]+ <f_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8018 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 801c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8020 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_iu_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8088 lw \$2,-32632\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: .... .... jal [0-9a-f]+ <f_iu_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_iu_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8030 lw \$2,-32720\(\$3\) +# ^ local GOT entry for f_lo_ic@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8034 lw \$2,-32716\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8038 lw \$2,-32712\(\$3\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 803c lw \$2,-32708\(\$3\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 459f jr \$31 + +Disassembly of section \.text\.b: + +10102000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c628090 lw \$2,-32624\(\$3\) +# ^ global GOT entry for f_iu +.*: 8c628050 lw \$2,-32688\(\$3\) +# ^ local GOT entry for f_iu_dc@micromipsplt +.*: 8c628088 lw \$2,-32632\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@micromipsplt +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628054 lw \$2,-32684\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628058 lw \$2,-32680\(\$3\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62805c lw \$2,-32676\(\$3\) +# ^ local GOT entry for f_lo_iu@micromipsplt +.*: 8c628060 lw \$2,-32672\(\$3\) +# ^ local GOT entry for f_lo_iu_dc@micromipsplt +.*: 8c628040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@micromipsplt +.*: 8c628044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@micromipsplt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628064 lw \$2,-32668\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628068 lw \$2,-32664\(\$3\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10103000 <testlo>: +.*: 3040 0205 li \$2,517 +# ^ low 16 bits of f_lo@micromipsplt +.*: 3040 01a5 li \$2,421 +# ^ low 16 bits of f_lo_dc@micromipsplt +.*: 3040 0175 li \$2,373 +# ^ low 16 bits of f_lo_ic@micromipsplt +.*: 3040 01f9 li \$2,505 +# ^ low 16 bits of f_lo_ic_dc@micromipsplt +.*: 3040 00e0 li \$2,224 +# ^ low 16 bits of f_lo_du@plt +.*: 3040 0070 li \$2,112 +# ^ low 16 bits of f_lo_du_dc@plt +.*: 3040 0060 li \$2,96 +# ^ low 16 bits of f_lo_du_ic@plt +.*: 3040 0030 li \$2,48 +# ^ low 16 bits of f_lo_du_ic_dc@plt +.*: 3040 0121 li \$2,289 +# ^ low 16 bits of f_lo_iu@micromipsplt +.*: 3040 0151 li \$2,337 +# ^ low 16 bits of f_lo_iu_dc@micromipsplt +.*: 3040 0169 li \$2,361 +# ^ low 16 bits of f_lo_iu_ic@micromipsplt +.*: 3040 01e1 li \$2,481 +# ^ low 16 bits of f_lo_iu_ic_dc@micromipsplt +.*: 3040 00d0 li \$2,208 +# ^ low 16 bits of f_lo_iu_du@plt +.*: 3040 0020 li \$2,32 +# ^ low 16 bits of f_lo_iu_du_dc@plt +.*: 3040 0100 li \$2,256 +# ^ low 16 bits of f_lo_iu_du_ic@plt +.*: 3040 0110 li \$2,272 +# ^ low 16 bits of f_lo_iu_du_ic_dc@plt + +Disassembly of section \.text\.d: + +10104000 <testgot>: +.*: fc5c 8094 lw \$2,-32620\(\$28\) +# ^ global GOT entry for f +.*: fc5c 806c lw \$2,-32660\(\$28\) +# ^ local GOT entry for f_dc@micromipsplt +.*: fc5c 808c lw \$2,-32628\(\$28\) +# ^ global GOT entry for f_ic +.*: fc5c 8018 lw \$2,-32744\(\$28\) +# ^ local GOT entry for f_ic_dc@micromipsplt +.*: fc5c 8070 lw \$2,-32656\(\$28\) +# ^ local GOT entry for f_du@plt +.*: fc5c 8074 lw \$2,-32652\(\$28\) +# ^ local GOT entry for f_du_dc@plt +.*: fc5c 801c lw \$2,-32740\(\$28\) +# ^ local GOT entry for f_du_ic@plt +.*: fc5c 8020 lw \$2,-32736\(\$28\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: fc5c 8090 lw \$2,-32624\(\$28\) +# ^ global GOT entry for f_iu +.*: fc5c 8050 lw \$2,-32688\(\$28\) +# ^ local GOT entry for f_iu_dc@micromipsplt +.*: fc5c 8088 lw \$2,-32632\(\$28\) +# ^ global GOT entry for f_iu_ic +.*: fc5c 8024 lw \$2,-32732\(\$28\) +# ^ local GOT entry for f_iu_ic_dc@micromipsplt +.*: fc5c 8054 lw \$2,-32684\(\$28\) +# ^ local GOT entry for f_iu_du@plt +.*: fc5c 8058 lw \$2,-32680\(\$28\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: fc5c 8028 lw \$2,-32728\(\$28\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: fc5c 802c lw \$2,-32724\(\$28\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: fc5c 8078 lw \$2,-32648\(\$28\) +# ^ local GOT entry for f_lo@micromipsplt +.*: fc5c 807c lw \$2,-32644\(\$28\) +# ^ local GOT entry for f_lo_dc@micromipsplt +.*: fc5c 8030 lw \$2,-32720\(\$28\) +# ^ local GOT entry for f_lo_ic@micromipsplt +.*: fc5c 8034 lw \$2,-32716\(\$28\) +# ^ local GOT entry for f_lo_ic_dc@micromipsplt +.*: fc5c 8080 lw \$2,-32640\(\$28\) +# ^ local GOT entry for f_lo_du@plt +.*: fc5c 8084 lw \$2,-32636\(\$28\) +# ^ local GOT entry for f_lo_du_dc@plt +.*: fc5c 8038 lw \$2,-32712\(\$28\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: fc5c 803c lw \$2,-32708\(\$28\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: fc5c 805c lw \$2,-32676\(\$28\) +# ^ local GOT entry for f_lo_iu@micromipsplt +.*: fc5c 8060 lw \$2,-32672\(\$28\) +# ^ local GOT entry for f_lo_iu_dc@micromipsplt +.*: fc5c 8040 lw \$2,-32704\(\$28\) +# ^ local GOT entry for f_lo_iu_ic@micromipsplt +.*: fc5c 8044 lw \$2,-32700\(\$28\) +# ^ local GOT entry for f_lo_iu_ic_dc@micromipsplt +.*: fc5c 8064 lw \$2,-32668\(\$28\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: fc5c 8068 lw \$2,-32664\(\$28\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: fc5c 8048 lw \$2,-32696\(\$28\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: fc5c 804c lw \$2,-32692\(\$28\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-got.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-got.rd new file mode 100644 index 0000000..2a4c337 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-got.rd @@ -0,0 +1,179 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x1f + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 224 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100121 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu_du_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo_du_ic_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 10100040 f_du_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100151 f_lo_iu_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 10100050 f_iu_du_ic +10200020 [^ ]+ R_MIPS_JUMP_SLOT 10100060 f_lo_du_ic +10200024 [^ ]+ R_MIPS_JUMP_SLOT 1010015d f_iu_dc +10200028 [^ ]+ R_MIPS_JUMP_SLOT 10100169 f_lo_iu_ic +1020002c [^ ]+ R_MIPS_JUMP_SLOT 10100175 f_lo_ic +10200030 [^ ]+ R_MIPS_JUMP_SLOT 10100070 f_lo_du_dc +10200034 [^ ]+ R_MIPS_JUMP_SLOT 10100080 f_du +10200038 [^ ]+ R_MIPS_JUMP_SLOT 10100090 f_du_ic_dc +1020003c [^ ]+ R_MIPS_JUMP_SLOT 101000a0 f_du_ic +10200040 [^ ]+ R_MIPS_JUMP_SLOT 101000b0 f_iu_du_dc +10200044 [^ ]+ R_MIPS_JUMP_SLOT 101001a5 f_lo_dc +10200048 [^ ]+ R_MIPS_JUMP_SLOT 101000c0 f_iu_du +1020004c [^ ]+ R_MIPS_JUMP_SLOT 101000d0 f_lo_iu_du +10200050 [^ ]+ R_MIPS_JUMP_SLOT 101001b1 f_dc +10200054 [^ ]+ R_MIPS_JUMP_SLOT 101001bd f_ic_dc +10200058 [^ ]+ R_MIPS_JUMP_SLOT 101000e0 f_lo_du +1020005c [^ ]+ R_MIPS_JUMP_SLOT 101001c9 f_iu_ic_dc +10200060 [^ ]+ R_MIPS_JUMP_SLOT 101000f0 f_iu_du_ic_dc +10200064 [^ ]+ R_MIPS_JUMP_SLOT 101001e1 f_lo_iu_ic_dc +10200068 [^ ]+ R_MIPS_JUMP_SLOT 10100100 f_lo_iu_du_ic +1020006c [^ ]+ R_MIPS_JUMP_SLOT 10100110 f_lo_iu_du_ic_dc +10200070 [^ ]+ R_MIPS_JUMP_SLOT 101001f9 f_lo_ic_dc +10200074 [^ ]+ R_MIPS_JUMP_SLOT 10100205 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# All symbols have their address taken, so PLT symbols need to have a nonzero +# value. They must also have STO_MIPS_PLT in order to distinguish them from +# old-style lazy-binding stubs). +# +# A MIPS (as opposed to microMIPS) PLT should be used as the symbol value +# if and only if the function has a direct MIPS caller (du). + .*: 10100121 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_dc +#... + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic_dc + .*: 10100040 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_dc + .*: 10100151 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_dc + .*: 10100050 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_ic + .*: 10100060 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic + .*: 1010015d 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_dc + .*: 10100169 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic + .*: 10100175 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 10100070 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_dc + .*: 10100080 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du + .*: 10100090 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_ic_dc + .*: 101000a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_ic + .*: 101000b0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_dc + .*: 101001a5 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 101000c0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du + .*: 101000d0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 101001b1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_dc + .*: 101001bd 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_ic_dc + .*: 101000e0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du + .*: 101001c9 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_ic_dc + .*: 101000f0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_ic_dc +#... + .*: 101001e1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic_dc + .*: 10100100 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic + .*: 10100110 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic_dc + .*: 101001f9 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 10100205 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. Since the functions +# have their addresses taken, they cannot use a lazy-binding stub. +# The symbol values are therefore all zero. + 31: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_ic + 32: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic + 33: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu + 34: 00000000 0 FUNC GLOBAL DEFAULT UND f + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 101001bd + 1020100c -32740\(gp\) 101000a0 + 10201010 -32736\(gp\) 10100090 + 10201014 -32732\(gp\) 101001c9 + 10201018 -32728\(gp\) 10100050 + 1020101c -32724\(gp\) 101000f0 + 10201020 -32720\(gp\) 10100175 + 10201024 -32716\(gp\) 101001f9 + 10201028 -32712\(gp\) 10100060 + 1020102c -32708\(gp\) 10100030 + 10201030 -32704\(gp\) 10100169 + 10201034 -32700\(gp\) 101001e1 + 10201038 -32696\(gp\) 10100100 + 1020103c -32692\(gp\) 10100110 + 10201040 -32688\(gp\) 1010015d + 10201044 -32684\(gp\) 101000c0 + 10201048 -32680\(gp\) 101000b0 + 1020104c -32676\(gp\) 10100121 + 10201050 -32672\(gp\) 10100151 + 10201054 -32668\(gp\) 101000d0 + 10201058 -32664\(gp\) 10100020 + 1020105c -32660\(gp\) 101001b1 + 10201060 -32656\(gp\) 10100080 + 10201064 -32652\(gp\) 10100040 + 10201068 -32648\(gp\) 10100205 + 1020106c -32644\(gp\) 101001a5 + 10201070 -32640\(gp\) 101000e0 + 10201074 -32636\(gp\) 10100070 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 10201078 -32632\(gp\) 00000000 00000000 FUNC UND f_iu_ic + 1020107c -32628\(gp\) 00000000 00000000 FUNC UND f_ic + 10201080 -32624\(gp\) 00000000 00000000 FUNC UND f_iu + 10201084 -32620\(gp\) 00000000 00000000 FUNC UND f + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100121 FUNC UND f_lo_iu + 1020000c 10100000 10100020 FUNC UND f_lo_iu_du_dc + 10200010 10100000 10100030 FUNC UND f_lo_du_ic_dc + 10200014 10100000 10100040 FUNC UND f_du_dc + 10200018 10100000 10100151 FUNC UND f_lo_iu_dc + 1020001c 10100000 10100050 FUNC UND f_iu_du_ic + 10200020 10100000 10100060 FUNC UND f_lo_du_ic + 10200024 10100000 1010015d FUNC UND f_iu_dc + 10200028 10100000 10100169 FUNC UND f_lo_iu_ic + 1020002c 10100000 10100175 FUNC UND f_lo_ic + 10200030 10100000 10100070 FUNC UND f_lo_du_dc + 10200034 10100000 10100080 FUNC UND f_du + 10200038 10100000 10100090 FUNC UND f_du_ic_dc + 1020003c 10100000 101000a0 FUNC UND f_du_ic + 10200040 10100000 101000b0 FUNC UND f_iu_du_dc + 10200044 10100000 101001a5 FUNC UND f_lo_dc + 10200048 10100000 101000c0 FUNC UND f_iu_du + 1020004c 10100000 101000d0 FUNC UND f_lo_iu_du + 10200050 10100000 101001b1 FUNC UND f_dc + 10200054 10100000 101001bd FUNC UND f_ic_dc + 10200058 10100000 101000e0 FUNC UND f_lo_du + 1020005c 10100000 101001c9 FUNC UND f_iu_ic_dc + 10200060 10100000 101000f0 FUNC UND f_iu_du_ic_dc + 10200064 10100000 101001e1 FUNC UND f_lo_iu_ic_dc + 10200068 10100000 10100100 FUNC UND f_lo_iu_du_ic + 1020006c 10100000 10100110 FUNC UND f_lo_iu_du_ic_dc + 10200070 10100000 101001f9 FUNC UND f_lo_ic_dc + 10200074 10100000 10100205 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-only.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-only.od new file mode 100644 index 0000000..b7d7241 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-only.od @@ -0,0 +1,111 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# All entries must be microMIPS. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 7984 0000 addiu \$3,\$pc,1048576 +.*: ff23 0000 lw \$25,0\(\$3\) +.*: 0535 subu \$2,\$2,\$3 +.*: 2525 srl \$2,\$2,2 +.*: 3302 fffe addiu \$24,\$2,-2 +.*: 0dff move \$15,\$31 +.*: 45f9 jalrs \$25 +.*: 0f83 move \$28,\$3 +.*: 0c00 nop + +10100018 <f_lo_ic@micromipsplt>: +.*: 7903 fffc addiu \$2,\$pc,1048560 +# ^ 0x10200008 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100024 <f_lo_dc@micromipsplt>: +.*: 7903 fffa addiu \$2,\$pc,1048552 +# ^ 0x1020000c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100030 <f_dc@micromipsplt>: +.*: 7903 fff8 addiu \$2,\$pc,1048544 +# ^ 0x10200010 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010003c <f_ic_dc@micromipsplt>: +.*: 7903 fff6 addiu \$2,\$pc,1048536 +# ^ 0x10200014 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100048 <f_lo_ic_dc@micromipsplt>: +.*: 7903 fff4 addiu \$2,\$pc,1048528 +# ^ 0x10200018 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100054 <f_lo@micromipsplt>: +.*: 7903 fff2 addiu \$2,\$pc,1048520 +# ^ 0x1020001c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +Disassembly of section \.MIPS\.stubs: + +10101000 <_MIPS_STUBS_>: +# Lazy-binding stub for f_ic. +.*: ff3c 8010 lw \$25,-32752\(\$28\) +.*: 0dff move \$15,\$31 +.*: 45d9 jalr \$25 +.*: 3300 0009 li \$24,9 + \.\.\. + +Disassembly of section \.text\.a: + +10102000 <testc>: +.*: .... .... jal [0-9a-f]+ <f_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8024 lw \$2,-32732\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jal [0-9a-f]+ <f_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8018 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 801c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_lo_ic@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8020 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@micromipsplt +.*: 459f jr \$31 + +Disassembly of section \.text\.c: + +10103000 <testlo>: +.*: 3040 0055 li \$2,85 +# ^ low 16 bits of f_lo@micromipsplt +.*: 3040 0025 li \$2,37 +# ^ low 16 bits of f_lo_dc@micromipsplt +.*: 3040 0019 li \$2,25 +# ^ low 16 bits of f_lo_ic@micromipsplt +.*: 3040 0049 li \$2,73 +# ^ low 16 bits of f_lo_ic_dc@micromipsplt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-only.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-only.rd new file mode 100644 index 0000000..fd3e7c6 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-only.rd @@ -0,0 +1,81 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x9 + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 48 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100019 f_lo_ic +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100025 f_lo_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_ic_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100049 f_lo_ic_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 10100055 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# _lo symbols have their address taken, so their PLT symbols need to have +# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish +# them from old-style lazy-binding stubs. Non-_lo symbols are only called, +# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation. +# +# All PLTs should be microMIPS. +#... + .*: 10100019 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 10100025 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic_dc +#... + .*: 10100049 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 10100055 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. The symbol value +# is the address of the lazy-binding stub. + 9: 10101001 0 FUNC GLOBAL DEFAULT UND f_ic + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 1010003d + 1020100c -32740\(gp\) 10100019 + 10201010 -32736\(gp\) 10100049 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 10201014 -32732\(gp\) 10101001 10101001 FUNC UND f_ic + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100001 10100019 FUNC UND f_lo_ic + 1020000c 10100001 10100025 FUNC UND f_lo_dc + 10200010 10100001 00000000 FUNC UND f_dc + 10200014 10100001 00000000 FUNC UND f_ic_dc + 10200018 10100001 10100049 FUNC UND f_lo_ic_dc + 1020001c 10100001 10100055 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-word.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-word.od new file mode 100644 index 0000000..4d0572b --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-word.od @@ -0,0 +1,492 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# Only _du (direct call from uncompressed code) functions should have +# non-microMIPS PLTs. All the rest must be microMIPS. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c1c1020 lui \$28,0x1020 +.*: 8f990000 lw \$25,0\(\$28\) +.*: 279c0000 addiu \$28,\$28,0 +.*: 031cc023 subu \$24,\$24,\$28 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100030 <f_lo_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100040 <f_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100050 <f_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100060 <f_lo_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90020 lw \$25,32\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80020 addiu \$24,\$15,32 + +10100070 <f_lo_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90030 lw \$25,48\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80030 addiu \$24,\$15,48 + +10100080 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90034 lw \$25,52\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80034 addiu \$24,\$15,52 + +10100090 <f_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90038 lw \$25,56\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80038 addiu \$24,\$15,56 + +101000a0 <f_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9003c lw \$25,60\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8003c addiu \$24,\$15,60 + +101000b0 <f_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90040 lw \$25,64\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80040 addiu \$24,\$15,64 + +101000c0 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90048 lw \$25,72\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80048 addiu \$24,\$15,72 + +101000d0 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9004c lw \$25,76\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8004c addiu \$24,\$15,76 + +101000e0 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90058 lw \$25,88\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80058 addiu \$24,\$15,88 + +101000f0 <f_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90060 lw \$25,96\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80060 addiu \$24,\$15,96 + +10100100 <f_lo_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90068 lw \$25,104\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80068 addiu \$24,\$15,104 + +10100110 <f_lo_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9006c lw \$25,108\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8006c addiu \$24,\$15,108 + +10100120 <f_lo_iu@micromipsplt>: +.*: 7903 ffba addiu \$2,\$pc,1048296 +# ^ 0x10200008 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010012c <f_lo_iu_du_dc@micromipsplt>: +.*: 7903 ffb8 addiu \$2,\$pc,1048288 +# ^ 0x1020000c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100138 <f_lo_du_ic_dc@micromipsplt>: +.*: 7903 ffb6 addiu \$2,\$pc,1048280 +# ^ 0x10200010 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100144 <f_du_dc@micromipsplt>: +.*: 7903 ffb4 addiu \$2,\$pc,1048272 +# ^ 0x10200014 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100150 <f_lo_iu_dc@micromipsplt>: +.*: 7903 ffb2 addiu \$2,\$pc,1048264 +# ^ 0x10200018 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010015c <f_iu_dc@micromipsplt>: +.*: 7903 ffb2 addiu \$2,\$pc,1048264 +# ^ 0x10200024 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100168 <f_lo_iu_ic@micromipsplt>: +.*: 7903 ffb0 addiu \$2,\$pc,1048256 +# ^ 0x10200028 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100174 <f_lo_ic@micromipsplt>: +.*: 7903 ffae addiu \$2,\$pc,1048248 +# ^ 0x1020002c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100180 <f_lo_du_dc@micromipsplt>: +.*: 7903 ffac addiu \$2,\$pc,1048240 +# ^ 0x10200030 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010018c <f_du_ic_dc@micromipsplt>: +.*: 7903 ffab addiu \$2,\$pc,1048236 +# ^ 0x10200038 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100198 <f_iu_du_dc@micromipsplt>: +.*: 7903 ffaa addiu \$2,\$pc,1048232 +# ^ 0x10200040 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001a4 <f_lo_dc@micromipsplt>: +.*: 7903 ffa8 addiu \$2,\$pc,1048224 +# ^ 0x10200044 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001b0 <f_dc@micromipsplt>: +.*: 7903 ffa8 addiu \$2,\$pc,1048224 +# ^ 0x10200050 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001bc <f_ic_dc@micromipsplt>: +.*: 7903 ffa6 addiu \$2,\$pc,1048216 +# ^ 0x10200054 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001c8 <f_iu_ic_dc@micromipsplt>: +.*: 7903 ffa5 addiu \$2,\$pc,1048212 +# ^ 0x1020005c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001d4 <f_iu_du_ic_dc@micromipsplt>: +.*: 7903 ffa3 addiu \$2,\$pc,1048204 +# ^ 0x10200060 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001e0 <f_lo_iu_ic_dc@micromipsplt>: +.*: 7903 ffa1 addiu \$2,\$pc,1048196 +# ^ 0x10200064 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001ec <f_lo_iu_du_ic_dc@micromipsplt>: +.*: 7903 ffa0 addiu \$2,\$pc,1048192 +# ^ 0x1020006c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001f8 <f_lo_ic_dc@micromipsplt>: +.*: 7903 ff9e addiu \$2,\$pc,1048184 +# ^ 0x10200070 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100204 <f_lo@micromipsplt>: +.*: 7903 ff9c addiu \$2,\$pc,1048176 +# ^ 0x10200074 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +Disassembly of section \.text\.a: + +10101000 <testc>: +.*: .... .... jal [0-9a-f]+ <f_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8070 lw \$2,-32656\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jal [0-9a-f]+ <f_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8018 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 801c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8020 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_iu_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: .... .... jal [0-9a-f]+ <f_iu_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_iu_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8030 lw \$2,-32720\(\$3\) +# ^ local GOT entry for f_lo_ic@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8034 lw \$2,-32716\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8038 lw \$2,-32712\(\$3\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 803c lw \$2,-32708\(\$3\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 459f jr \$31 + +Disassembly of section \.text\.b: + +10102000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c628074 lw \$2,-32652\(\$3\) +# ^ global GOT entry for f_iu +.*: 8c628050 lw \$2,-32688\(\$3\) +# ^ local GOT entry for f_iu_dc@micromipsplt +.*: 8c62806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@micromipsplt +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628054 lw \$2,-32684\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628058 lw \$2,-32680\(\$3\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62805c lw \$2,-32676\(\$3\) +# ^ local GOT entry for f_lo_iu@micromipsplt +.*: 8c628060 lw \$2,-32672\(\$3\) +# ^ local GOT entry for f_lo_iu_dc@micromipsplt +.*: 8c628040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@micromipsplt +.*: 8c628044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@micromipsplt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628064 lw \$2,-32668\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628068 lw \$2,-32664\(\$3\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10103000 <testlo>: +.*: 3040 0205 li \$2,517 +# ^ low 16 bits of f_lo@micromipsplt +.*: 3040 01a5 li \$2,421 +# ^ low 16 bits of f_lo_dc@micromipsplt +.*: 3040 0175 li \$2,373 +# ^ low 16 bits of f_lo_ic@micromipsplt +.*: 3040 01f9 li \$2,505 +# ^ low 16 bits of f_lo_ic_dc@micromipsplt +.*: 3040 00e0 li \$2,224 +# ^ low 16 bits of f_lo_du@plt +.*: 3040 0070 li \$2,112 +# ^ low 16 bits of f_lo_du_dc@plt +.*: 3040 0060 li \$2,96 +# ^ low 16 bits of f_lo_du_ic@plt +.*: 3040 0030 li \$2,48 +# ^ low 16 bits of f_lo_du_ic_dc@plt +.*: 3040 0121 li \$2,289 +# ^ low 16 bits of f_lo_iu@micromipsplt +.*: 3040 0151 li \$2,337 +# ^ low 16 bits of f_lo_iu_dc@micromipsplt +.*: 3040 0169 li \$2,361 +# ^ low 16 bits of f_lo_iu_ic@micromipsplt +.*: 3040 01e1 li \$2,481 +# ^ low 16 bits of f_lo_iu_ic_dc@micromipsplt +.*: 3040 00d0 li \$2,208 +# ^ low 16 bits of f_lo_iu_du@plt +.*: 3040 0020 li \$2,32 +# ^ low 16 bits of f_lo_iu_du_dc@plt +.*: 3040 0100 li \$2,256 +# ^ low 16 bits of f_lo_iu_du_ic@plt +.*: 3040 0110 li \$2,272 +# ^ low 16 bits of f_lo_iu_du_ic_dc@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-word.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-word.rd new file mode 100644 index 0000000..2c872af --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-word.rd @@ -0,0 +1,198 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10202000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x1f + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10005000 + 0x00000002 \(PLTRELSZ\) 224 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.dyn' .* +# All symbols are referenced by a .word in the .data section, so pointer +# equality matters. If a PLT is needed to satisfy a direct call or %lo +# relocation, the symbol should have a nonzero value and there should be +# no dynamic relocations against it. The only relocations here are for +# undefined 0-value symbols. Note that unlike x86, we do not create a PLT +# for the uncalled symbol 'f' in order to maintain backward compatibility +# with pre-PLT ld.sos. + Offset Info Type Sym\.Value Sym\. Name +00000000 00000000 R_MIPS_NONE +10201028 00001f03 R_MIPS_REL32 00000000 f_iu_ic +10201008 00002003 R_MIPS_REL32 00000000 f_ic +10201020 00002103 R_MIPS_REL32 00000000 f_iu +10201000 00002203 R_MIPS_REL32 00000000 f + +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100121 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu_du_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo_du_ic_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 10100040 f_du_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100151 f_lo_iu_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 10100050 f_iu_du_ic +10200020 [^ ]+ R_MIPS_JUMP_SLOT 10100060 f_lo_du_ic +10200024 [^ ]+ R_MIPS_JUMP_SLOT 1010015d f_iu_dc +10200028 [^ ]+ R_MIPS_JUMP_SLOT 10100169 f_lo_iu_ic +1020002c [^ ]+ R_MIPS_JUMP_SLOT 10100175 f_lo_ic +10200030 [^ ]+ R_MIPS_JUMP_SLOT 10100070 f_lo_du_dc +10200034 [^ ]+ R_MIPS_JUMP_SLOT 10100080 f_du +10200038 [^ ]+ R_MIPS_JUMP_SLOT 10100090 f_du_ic_dc +1020003c [^ ]+ R_MIPS_JUMP_SLOT 101000a0 f_du_ic +10200040 [^ ]+ R_MIPS_JUMP_SLOT 101000b0 f_iu_du_dc +10200044 [^ ]+ R_MIPS_JUMP_SLOT 101001a5 f_lo_dc +10200048 [^ ]+ R_MIPS_JUMP_SLOT 101000c0 f_iu_du +1020004c [^ ]+ R_MIPS_JUMP_SLOT 101000d0 f_lo_iu_du +10200050 [^ ]+ R_MIPS_JUMP_SLOT 101001b1 f_dc +10200054 [^ ]+ R_MIPS_JUMP_SLOT 101001bd f_ic_dc +10200058 [^ ]+ R_MIPS_JUMP_SLOT 101000e0 f_lo_du +1020005c [^ ]+ R_MIPS_JUMP_SLOT 101001c9 f_iu_ic_dc +10200060 [^ ]+ R_MIPS_JUMP_SLOT 101000f0 f_iu_du_ic_dc +10200064 [^ ]+ R_MIPS_JUMP_SLOT 101001e1 f_lo_iu_ic_dc +10200068 [^ ]+ R_MIPS_JUMP_SLOT 10100100 f_lo_iu_du_ic +1020006c [^ ]+ R_MIPS_JUMP_SLOT 10100110 f_lo_iu_du_ic_dc +10200070 [^ ]+ R_MIPS_JUMP_SLOT 101001f9 f_lo_ic_dc +10200074 [^ ]+ R_MIPS_JUMP_SLOT 10100205 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# All symbols have their address taken, so PLT symbols need to have a nonzero +# value. They must also have STO_MIPS_PLT in order to distinguish them from +# old-style lazy-binding stubs). +# +# A MIPS (as opposed to microMIPS) PLT should be used as the symbol value +# if and only if the function has a direct MIPS caller (du). + .*: 10100121 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_dc +#... + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic_dc + .*: 10100040 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_dc + .*: 10100151 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_dc + .*: 10100050 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_ic + .*: 10100060 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic + .*: 1010015d 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_dc + .*: 10100169 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic + .*: 10100175 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 10100070 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_dc + .*: 10100080 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du + .*: 10100090 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_ic_dc + .*: 101000a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_ic + .*: 101000b0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_dc + .*: 101001a5 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 101000c0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du + .*: 101000d0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 101001b1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_dc + .*: 101001bd 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_ic_dc + .*: 101000e0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du + .*: 101001c9 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_ic_dc + .*: 101000f0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_ic_dc +#... + .*: 101001e1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic_dc + .*: 10100100 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic + .*: 10100110 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic_dc + .*: 101001f9 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 10100205 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. Since the functions +# have their addresses taken, they cannot use a lazy-binding stub. +# The symbol values are therefore all zero. + 31: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_ic + 32: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic + 33: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu + 34: 00000000 0 FUNC GLOBAL DEFAULT UND f + +Symbol table '\.symtab' .* +#... +Hex dump of section '\.data': + 0x10201000 (00000000|00000000) (101001b1|b1011010) (00000000|00000000) (101001bd|bd011010) .* + 0x10201010 (10100080|80001010) (10100040|40001010) (101000a0|a0001010) (10100090|90001010) .* + 0x10201020 (00000000|00000000) (1010015d|5d011010) (00000000|00000000) (101001c9|c9011010) .* + 0x10201030 (101000c0|c0001010) (101000b0|b0001010) (10100050|50001010) (101000f0|f0001010) .* + 0x10201040 (10100205|05021010) (101001a5|a5011010) (10100175|75011010) (101001f9|f9011010) .* + 0x10201050 (101000e0|e0001010) (10100070|70001010) (10100060|60001010) (10100030|30001010) .* + 0x10201060 (10100121|21011010) (10100151|51011010) (10100169|69011010) (101001e1|e1011010) .* + 0x10201070 (101000d0|d0001010) (10100020|20001010) (10100100|00011010) (10100110|10011010) .* + + +Primary GOT: + Canonical gp value: 10209ff0 + + Reserved entries: + Address Access Initial Purpose + 10202000 -32752\(gp\) 00000000 Lazy resolver + 10202004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10202008 -32744\(gp\) 101001bd + 1020200c -32740\(gp\) 101000a0 + 10202010 -32736\(gp\) 10100090 + 10202014 -32732\(gp\) 101001c9 + 10202018 -32728\(gp\) 10100050 + 1020201c -32724\(gp\) 101000f0 + 10202020 -32720\(gp\) 10100175 + 10202024 -32716\(gp\) 101001f9 + 10202028 -32712\(gp\) 10100060 + 1020202c -32708\(gp\) 10100030 + 10202030 -32704\(gp\) 10100169 + 10202034 -32700\(gp\) 101001e1 + 10202038 -32696\(gp\) 10100100 + 1020203c -32692\(gp\) 10100110 + 10202040 -32688\(gp\) 1010015d + 10202044 -32684\(gp\) 101000c0 + 10202048 -32680\(gp\) 101000b0 + 1020204c -32676\(gp\) 10100121 + 10202050 -32672\(gp\) 10100151 + 10202054 -32668\(gp\) 101000d0 + 10202058 -32664\(gp\) 10100020 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 1020205c -32660\(gp\) 00000000 00000000 FUNC UND f_iu_ic + 10202060 -32656\(gp\) 00000000 00000000 FUNC UND f_ic + 10202064 -32652\(gp\) 00000000 00000000 FUNC UND f_iu + 10202068 -32648\(gp\) 00000000 00000000 FUNC UND f + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100121 FUNC UND f_lo_iu + 1020000c 10100000 10100020 FUNC UND f_lo_iu_du_dc + 10200010 10100000 10100030 FUNC UND f_lo_du_ic_dc + 10200014 10100000 10100040 FUNC UND f_du_dc + 10200018 10100000 10100151 FUNC UND f_lo_iu_dc + 1020001c 10100000 10100050 FUNC UND f_iu_du_ic + 10200020 10100000 10100060 FUNC UND f_lo_du_ic + 10200024 10100000 1010015d FUNC UND f_iu_dc + 10200028 10100000 10100169 FUNC UND f_lo_iu_ic + 1020002c 10100000 10100175 FUNC UND f_lo_ic + 10200030 10100000 10100070 FUNC UND f_lo_du_dc + 10200034 10100000 10100080 FUNC UND f_du + 10200038 10100000 10100090 FUNC UND f_du_ic_dc + 1020003c 10100000 101000a0 FUNC UND f_du_ic + 10200040 10100000 101000b0 FUNC UND f_iu_du_dc + 10200044 10100000 101001a5 FUNC UND f_lo_dc + 10200048 10100000 101000c0 FUNC UND f_iu_du + 1020004c 10100000 101000d0 FUNC UND f_lo_iu_du + 10200050 10100000 101001b1 FUNC UND f_dc + 10200054 10100000 101001bd FUNC UND f_ic_dc + 10200058 10100000 101000e0 FUNC UND f_lo_du + 1020005c 10100000 101001c9 FUNC UND f_iu_ic_dc + 10200060 10100000 101000f0 FUNC UND f_iu_du_ic_dc + 10200064 10100000 101001e1 FUNC UND f_lo_iu_ic_dc + 10200068 10100000 10100100 FUNC UND f_lo_iu_du_ic + 1020006c 10100000 10100110 FUNC UND f_lo_iu_du_ic_dc + 10200070 10100000 101001f9 FUNC UND f_lo_ic_dc + 10200074 10100000 10100205 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips.od new file mode 100644 index 0000000..416509f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips.od @@ -0,0 +1,512 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# Only _du (direct call from uncompressed code) functions should have +# non-microMIPS PLTs. All the rest must be microMIPS. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c1c1020 lui \$28,0x1020 +.*: 8f990000 lw \$25,0\(\$28\) +.*: 279c0000 addiu \$28,\$28,0 +.*: 031cc023 subu \$24,\$24,\$28 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100030 <f_lo_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100040 <f_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100050 <f_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100060 <f_lo_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90020 lw \$25,32\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80020 addiu \$24,\$15,32 + +10100070 <f_lo_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90030 lw \$25,48\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80030 addiu \$24,\$15,48 + +10100080 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90034 lw \$25,52\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80034 addiu \$24,\$15,52 + +10100090 <f_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90038 lw \$25,56\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80038 addiu \$24,\$15,56 + +101000a0 <f_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9003c lw \$25,60\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8003c addiu \$24,\$15,60 + +101000b0 <f_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90040 lw \$25,64\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80040 addiu \$24,\$15,64 + +101000c0 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90048 lw \$25,72\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80048 addiu \$24,\$15,72 + +101000d0 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9004c lw \$25,76\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8004c addiu \$24,\$15,76 + +101000e0 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90058 lw \$25,88\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80058 addiu \$24,\$15,88 + +101000f0 <f_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90060 lw \$25,96\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80060 addiu \$24,\$15,96 + +10100100 <f_lo_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90068 lw \$25,104\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80068 addiu \$24,\$15,104 + +10100110 <f_lo_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9006c lw \$25,108\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8006c addiu \$24,\$15,108 + +10100120 <f_lo_iu@micromipsplt>: +.*: 7903 ffba addiu \$2,\$pc,1048296 +# ^ 0x10200008 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010012c <f_lo_iu_du_dc@micromipsplt>: +.*: 7903 ffb8 addiu \$2,\$pc,1048288 +# ^ 0x1020000c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100138 <f_lo_du_ic_dc@micromipsplt>: +.*: 7903 ffb6 addiu \$2,\$pc,1048280 +# ^ 0x10200010 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100144 <f_du_dc@micromipsplt>: +.*: 7903 ffb4 addiu \$2,\$pc,1048272 +# ^ 0x10200014 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100150 <f_lo_iu_dc@micromipsplt>: +.*: 7903 ffb2 addiu \$2,\$pc,1048264 +# ^ 0x10200018 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010015c <f_iu_dc@micromipsplt>: +.*: 7903 ffb2 addiu \$2,\$pc,1048264 +# ^ 0x10200024 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100168 <f_lo_iu_ic@micromipsplt>: +.*: 7903 ffb0 addiu \$2,\$pc,1048256 +# ^ 0x10200028 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100174 <f_lo_ic@micromipsplt>: +.*: 7903 ffae addiu \$2,\$pc,1048248 +# ^ 0x1020002c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100180 <f_lo_du_dc@micromipsplt>: +.*: 7903 ffac addiu \$2,\$pc,1048240 +# ^ 0x10200030 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010018c <f_du_ic_dc@micromipsplt>: +.*: 7903 ffab addiu \$2,\$pc,1048236 +# ^ 0x10200038 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100198 <f_iu_du_dc@micromipsplt>: +.*: 7903 ffaa addiu \$2,\$pc,1048232 +# ^ 0x10200040 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001a4 <f_lo_dc@micromipsplt>: +.*: 7903 ffa8 addiu \$2,\$pc,1048224 +# ^ 0x10200044 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001b0 <f_dc@micromipsplt>: +.*: 7903 ffa8 addiu \$2,\$pc,1048224 +# ^ 0x10200050 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001bc <f_ic_dc@micromipsplt>: +.*: 7903 ffa6 addiu \$2,\$pc,1048216 +# ^ 0x10200054 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001c8 <f_iu_ic_dc@micromipsplt>: +.*: 7903 ffa5 addiu \$2,\$pc,1048212 +# ^ 0x1020005c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001d4 <f_iu_du_ic_dc@micromipsplt>: +.*: 7903 ffa3 addiu \$2,\$pc,1048204 +# ^ 0x10200060 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001e0 <f_lo_iu_ic_dc@micromipsplt>: +.*: 7903 ffa1 addiu \$2,\$pc,1048196 +# ^ 0x10200064 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001ec <f_lo_iu_du_ic_dc@micromipsplt>: +.*: 7903 ffa0 addiu \$2,\$pc,1048192 +# ^ 0x1020006c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001f8 <f_lo_ic_dc@micromipsplt>: +.*: 7903 ff9e addiu \$2,\$pc,1048184 +# ^ 0x10200070 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100204 <f_lo@micromipsplt>: +.*: 7903 ff9c addiu \$2,\$pc,1048176 +# ^ 0x10200074 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +Disassembly of section \.MIPS\.stubs: + +10101000 <_MIPS_STUBS_>: +# Lazy-binding stub for f_iu. +.*: ff3c 8010 lw \$25,-32752\(\$28\) +.*: 0dff move \$15,\$31 +.*: 45d9 jalr \$25 +.*: 3300 0021 li \$24,33 +# Lazy-binding stub for f_ic. +.*: ff3c 8010 lw \$25,-32752\(\$28\) +.*: 0dff move \$15,\$31 +.*: 45d9 jalr \$25 +.*: 3300 0020 li \$24,32 +# Lazy-binding stub for f_iu_ic. +.*: ff3c 8010 lw \$25,-32752\(\$28\) +.*: 0dff move \$15,\$31 +.*: 45d9 jalr \$25 +.*: 3300 001f li \$24,31 + \.\.\. + +Disassembly of section \.text\.a: + +10102000 <testc>: +.*: .... .... jal [0-9a-f]+ <f_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8070 lw \$2,-32656\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jal [0-9a-f]+ <f_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8018 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 801c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8020 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_iu_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: .... .... jal [0-9a-f]+ <f_iu_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_iu_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8030 lw \$2,-32720\(\$3\) +# ^ local GOT entry for f_lo_ic@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8034 lw \$2,-32716\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8038 lw \$2,-32712\(\$3\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 803c lw \$2,-32708\(\$3\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 459f jr \$31 + +Disassembly of section \.text\.b: + +10103000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c628074 lw \$2,-32652\(\$3\) +# ^ global GOT entry for f_iu +.*: 8c628050 lw \$2,-32688\(\$3\) +# ^ local GOT entry for f_iu_dc@micromipsplt +.*: 8c62806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@micromipsplt +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628054 lw \$2,-32684\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628058 lw \$2,-32680\(\$3\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62805c lw \$2,-32676\(\$3\) +# ^ local GOT entry for f_lo_iu@micromipsplt +.*: 8c628060 lw \$2,-32672\(\$3\) +# ^ local GOT entry for f_lo_iu_dc@micromipsplt +.*: 8c628040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@micromipsplt +.*: 8c628044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@micromipsplt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628064 lw \$2,-32668\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628068 lw \$2,-32664\(\$3\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10104000 <testlo>: +.*: 3040 0205 li \$2,517 +# ^ low 16 bits of f_lo@micromipsplt +.*: 3040 01a5 li \$2,421 +# ^ low 16 bits of f_lo_dc@micromipsplt +.*: 3040 0175 li \$2,373 +# ^ low 16 bits of f_lo_ic@micromipsplt +.*: 3040 01f9 li \$2,505 +# ^ low 16 bits of f_lo_ic_dc@micromipsplt +.*: 3040 00e0 li \$2,224 +# ^ low 16 bits of f_lo_du@plt +.*: 3040 0070 li \$2,112 +# ^ low 16 bits of f_lo_du_dc@plt +.*: 3040 0060 li \$2,96 +# ^ low 16 bits of f_lo_du_ic@plt +.*: 3040 0030 li \$2,48 +# ^ low 16 bits of f_lo_du_ic_dc@plt +.*: 3040 0121 li \$2,289 +# ^ low 16 bits of f_lo_iu@micromipsplt +.*: 3040 0151 li \$2,337 +# ^ low 16 bits of f_lo_iu_dc@micromipsplt +.*: 3040 0169 li \$2,361 +# ^ low 16 bits of f_lo_iu_ic@micromipsplt +.*: 3040 01e1 li \$2,481 +# ^ low 16 bits of f_lo_iu_ic_dc@micromipsplt +.*: 3040 00d0 li \$2,208 +# ^ low 16 bits of f_lo_iu_du@plt +.*: 3040 0020 li \$2,32 +# ^ low 16 bits of f_lo_iu_du_dc@plt +.*: 3040 0100 li \$2,256 +# ^ low 16 bits of f_lo_iu_du_ic@plt +.*: 3040 0110 li \$2,272 +# ^ low 16 bits of f_lo_iu_du_ic_dc@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips.rd new file mode 100644 index 0000000..8f7d85c --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips.rd @@ -0,0 +1,170 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x1f + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 224 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100121 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu_du_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo_du_ic_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100151 f_lo_iu_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_ic +10200020 [^ ]+ R_MIPS_JUMP_SLOT 10100060 f_lo_du_ic +10200024 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_dc +10200028 [^ ]+ R_MIPS_JUMP_SLOT 10100169 f_lo_iu_ic +1020002c [^ ]+ R_MIPS_JUMP_SLOT 10100175 f_lo_ic +10200030 [^ ]+ R_MIPS_JUMP_SLOT 10100070 f_lo_du_dc +10200034 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du +10200038 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_ic_dc +1020003c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_ic +10200040 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_dc +10200044 [^ ]+ R_MIPS_JUMP_SLOT 101001a5 f_lo_dc +10200048 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du +1020004c [^ ]+ R_MIPS_JUMP_SLOT 101000d0 f_lo_iu_du +10200050 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_dc +10200054 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_ic_dc +10200058 [^ ]+ R_MIPS_JUMP_SLOT 101000e0 f_lo_du +1020005c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_ic_dc +10200060 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_ic_dc +10200064 [^ ]+ R_MIPS_JUMP_SLOT 101001e1 f_lo_iu_ic_dc +10200068 [^ ]+ R_MIPS_JUMP_SLOT 10100100 f_lo_iu_du_ic +1020006c [^ ]+ R_MIPS_JUMP_SLOT 10100110 f_lo_iu_du_ic_dc +10200070 [^ ]+ R_MIPS_JUMP_SLOT 101001f9 f_lo_ic_dc +10200074 [^ ]+ R_MIPS_JUMP_SLOT 10100205 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# _lo symbols have their address taken, so their PLT symbols need to have +# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish +# them from old-style lazy-binding stubs. Non-_lo symbols are only called, +# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation. +# +# A MIPS (as opposed to microMIPS) PLT should be used as the symbol value +# if and only if the function has a direct MIPS caller (du). + .*: 10100121 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_dc +#... + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_dc + .*: 10100151 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_ic + .*: 10100060 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_dc + .*: 10100169 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic + .*: 10100175 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 10100070 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_ic + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_dc + .*: 101001a5 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du + .*: 101000d0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic_dc + .*: 101000e0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_ic_dc +#... + .*: 101001e1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic_dc + .*: 10100100 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic + .*: 10100110 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic_dc + .*: 101001f9 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 10100205 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. The symbol value +# is the address of the lazy-binding stub. + 31: 10101019 0 FUNC GLOBAL DEFAULT UND f_iu_ic + 32: 1010100d 0 FUNC GLOBAL DEFAULT UND f_ic + 33: 10101001 0 FUNC GLOBAL DEFAULT UND f_iu + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 101001bd + 1020100c -32740\(gp\) 101000a0 + 10201010 -32736\(gp\) 10100090 + 10201014 -32732\(gp\) 101001c9 + 10201018 -32728\(gp\) 10100050 + 1020101c -32724\(gp\) 101000f0 + 10201020 -32720\(gp\) 10100175 + 10201024 -32716\(gp\) 101001f9 + 10201028 -32712\(gp\) 10100060 + 1020102c -32708\(gp\) 10100030 + 10201030 -32704\(gp\) 10100169 + 10201034 -32700\(gp\) 101001e1 + 10201038 -32696\(gp\) 10100100 + 1020103c -32692\(gp\) 10100110 + 10201040 -32688\(gp\) 1010015d + 10201044 -32684\(gp\) 101000c0 + 10201048 -32680\(gp\) 101000b0 + 1020104c -32676\(gp\) 10100121 + 10201050 -32672\(gp\) 10100151 + 10201054 -32668\(gp\) 101000d0 + 10201058 -32664\(gp\) 10100020 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 1020105c -32660\(gp\) 10101019 10101019 FUNC UND f_iu_ic + 10201060 -32656\(gp\) 1010100d 1010100d FUNC UND f_ic + 10201064 -32652\(gp\) 10101001 10101001 FUNC UND f_iu + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100121 FUNC UND f_lo_iu + 1020000c 10100000 10100020 FUNC UND f_lo_iu_du_dc + 10200010 10100000 10100030 FUNC UND f_lo_du_ic_dc + 10200014 10100000 00000000 FUNC UND f_du_dc + 10200018 10100000 10100151 FUNC UND f_lo_iu_dc + 1020001c 10100000 00000000 FUNC UND f_iu_du_ic + 10200020 10100000 10100060 FUNC UND f_lo_du_ic + 10200024 10100000 00000000 FUNC UND f_iu_dc + 10200028 10100000 10100169 FUNC UND f_lo_iu_ic + 1020002c 10100000 10100175 FUNC UND f_lo_ic + 10200030 10100000 10100070 FUNC UND f_lo_du_dc + 10200034 10100000 00000000 FUNC UND f_du + 10200038 10100000 00000000 FUNC UND f_du_ic_dc + 1020003c 10100000 00000000 FUNC UND f_du_ic + 10200040 10100000 00000000 FUNC UND f_iu_du_dc + 10200044 10100000 101001a5 FUNC UND f_lo_dc + 10200048 10100000 00000000 FUNC UND f_iu_du + 1020004c 10100000 101000d0 FUNC UND f_lo_iu_du + 10200050 10100000 00000000 FUNC UND f_dc + 10200054 10100000 00000000 FUNC UND f_ic_dc + 10200058 10100000 101000e0 FUNC UND f_lo_du + 1020005c 10100000 00000000 FUNC UND f_iu_ic_dc + 10200060 10100000 00000000 FUNC UND f_iu_du_ic_dc + 10200064 10100000 101001e1 FUNC UND f_lo_iu_ic_dc + 10200068 10100000 10100100 FUNC UND f_lo_iu_du_ic + 1020006c 10100000 10100110 FUNC UND f_lo_iu_du_ic_dc + 10200070 10100000 101001f9 FUNC UND f_lo_ic_dc + 10200074 10100000 10100205 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1.ld new file mode 100644 index 0000000..0108d0f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1.ld @@ -0,0 +1,40 @@ +SECTIONS +{ + . = 0x10000000; + .interp : { *(.interp) } + .reginfo : { *(.reginfo) } + .hash : { *(.hash) } + . = ALIGN(0x1000); + .dynsym : { *(.dynsym) } + . = ALIGN(0x1000); + .dynstr : { *(.dynstr) } + . = ALIGN(0x1000); + .dynamic : { *(.dynamic) } + . = ALIGN(0x1000); + .rel.dyn : { *(.rel.dyn) } + . = ALIGN(0x1000); + .rel.plt : { *(.rel.plt) } + . = 0x10100000; + .plt : { *(.plt) } + . = ALIGN(0x1000); + .MIPS.stubs : { *(.MIPS.stubs) } + . = ALIGN(0x1000); + .text.a : { *(.text.a) } + . = ALIGN(0x1000); + .text.b : { *(.text.b) } + . = ALIGN(0x1000); + .text.c : { *(.text.c) } + . = ALIGN(0x1000); + .text.d : { *(.text.d) } + . = 0x10200000; + .got.plt : { *(.got.plt) } + . = ALIGN(0x1000); + .data : { *(.data) } + . = ALIGN(0x1000); + _gp = . + 0x7ff0; + .got : { *(.got) } + . = ALIGN(0x1000); + .rld_map : { *(.rld_map) } + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } +} diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1.s b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1.s new file mode 100644 index 0000000..aa0b497 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1.s @@ -0,0 +1,62 @@ + .macro call_stub, name + .set push + .set nomips16 + .section .mips16.call.\name, "ax", @progbits + .ent __call_stub_\name + .type __call_stub_\name, @function +__call_stub_\name: + la $25, \name + jr $25 + .set pop + .endm + + # Flags to specify how a particular function is referenced + + .equ DC, 1 # Direct call from "compressed" code + .equ IC, 2 # Indirect call from "compressed" code + .equ DU, 4 # Direct call from "uncompressed" code + .equ IU, 8 # Indirect call from "uncompressed" code + .equ LO, 16 # Direct address reference (%lo) + + # A wrapper around a macro called test_one, which is defined by + # the file that includes this one. NAME is the name of a function + # that is referenced in the way described by FLAGS, an inclusive OR + # of the flags above. The wrapper filters out any functions whose + # FLAGS are not a subset of FILTER. + + .macro test_filter, name, flags + .if (\flags & filter) == \flags + test_one \name, \flags + .endif + .endm + + .macro test_all_dc, name, flags + test_filter \name, \flags + test_filter \name\()_dc, (\flags | DC) + .endm + + .macro test_all_ic, name, flags + test_all_dc \name, \flags + test_all_dc \name\()_ic, (\flags | IC) + .endm + + .macro test_all_du, name, flags + test_all_ic \name, \flags + test_all_ic \name\()_du, (\flags | DU) + .endm + + .macro test_all_iu, name, flags + test_all_du \name, \flags + test_all_du \name\()_iu, (\flags | IU) + .endm + + .macro test_all_lo, name, flags + test_all_iu \name, \flags + test_all_iu \name\()_lo, (\flags | LO) + .endm + + # Test all the combinations of interest. + + .macro test_all + test_all_lo f, 0 + .endm diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1a.s b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1a.s new file mode 100644 index 0000000..d5c6b4f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1a.s @@ -0,0 +1,37 @@ +# Define a function with all "compressed" (dc and ic) references. + + .abicalls + .option pic0 + + .include "compressed-plt-1.s" + + .macro test_one, name, types + .if (\types) & DC + jal \name + nop + .if micromips + .ifdef o32 + j \name + nop + .endif + .endif + .endif + .if (\types) & IC + lw $2, %call16(\name)($3) + .endif + .endm + + .if micromips + .set micromips + .else + .set mips16 + .endif + + .section .text.a, "ax", @progbits + .globl testc + .ent testc + .set noreorder +testc: + test_all + jr $31 + .end testc diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1b.s b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1b.s new file mode 100644 index 0000000..33deccb --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1b.s @@ -0,0 +1,27 @@ +# Define a function with all "uncompressed" (du and iu) references. + + .abicalls + .option pic0 + + .include "compressed-plt-1.s" + + .macro test_one, name, types + .if (\types) & DU + jal \name + nop + j \name + nop + .endif + .if (\types) & IU + lw $2, %call16(\name)($3) + .endif + .endm + + .section .text.b, "ax", @progbits + .globl testu + .ent testu + .set noreorder +testu: + test_all + jr $31 + .end testu diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1c.s b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1c.s new file mode 100644 index 0000000..651424b --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1c.s @@ -0,0 +1,24 @@ +# Define a function with all direct (%lo) references. + + .abicalls + .option pic0 + + .include "compressed-plt-1.s" + + .macro test_one, name, types + .if (\types) & LO + li $2,%lo(\name) + .endif + .endm + + .if micromips + .set micromips + .endif + + .section .text.c, "ax", @progbits + .globl testlo + .ent testlo + .set noreorder +testlo: + test_all + .end testlo diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1d.s b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1d.s new file mode 100644 index 0000000..8163c8e --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1d.s @@ -0,0 +1,22 @@ +# Create a GOT reference for every function under test. + + .abicalls + .option pic2 + + .include "compressed-plt-1.s" + + .macro test_one, name, types + lw $2,%got(\name)($gp) + .endm + + .if micromips + .set micromips + .endif + + .section .text.d, "ax", @progbits + .globl testgot + .ent testgot + .set noreorder +testgot: + test_all + .end testgot diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1e.s b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1e.s new file mode 100644 index 0000000..4084a6f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1e.s @@ -0,0 +1,13 @@ +# Create a .word reference for every function under test. + + .abicalls + .option pic2 + + .include "compressed-plt-1.s" + + .macro test_one, name, types + .word \name + .endm + + .data + test_all diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/dyn-sec64.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/dyn-sec64.ld index 4c6353a..c7af3f4 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/dyn-sec64.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/dyn-sec64.ld @@ -20,4 +20,6 @@ SECTIONS HIDDEN (_gp = ALIGN (16) + 0x7ff0); .got : { *(.got) } .data : { *(.data) } + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n32-embed.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n32-embed.d index d492998..58f23ed 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n32-embed.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n32-embed.d @@ -1,6 +1,7 @@ #name: MIPS ELF got reloc n32 #as: -march=from-abi -EB -n32 -KPIC -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s +#objcopy_objects: -R .MIPS.abiflags +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d index 535a538..174153d 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d @@ -1,6 +1,7 @@ #name: MIPS ELF got reloc n32 #as: -march=from-abi -EB -n32 -KPIC -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64-embed.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64-embed.d index f2719f0..c55900f 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64-embed.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64-embed.d @@ -1,6 +1,7 @@ #name: MIPS ELF got reloc n64 #as: -march=from-abi -EB -64 -KPIC -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64-linux.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64-linux.d index c1c3326..8e2822d 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64-linux.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64-linux.d @@ -1,6 +1,7 @@ #name: MIPS ELF got reloc n64 #as: -march=from-abi -EB -64 -KPIC -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64.d index 55dd7ae..492f76e 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64.d @@ -1,6 +1,7 @@ #name: MIPS ELF got reloc n64 #as: -march=from-abi -EB -64 -KPIC -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32-embed.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32-embed.d index 1d0c045..d6c2e85 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32-embed.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32-embed.d @@ -1,6 +1,7 @@ #name: MIPS ELF xgot reloc n32 #as: -march=from-abi -EB -n32 -KPIC -xgot -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn @@ -18,382 +19,382 @@ Disassembly of section \.text: 10000074 <fn>: 10000074: 3c050000 lui a1,0x0 10000078: 00bc2821 addu a1,a1,gp -1000007c: 8ca58018 lw a1,-32744\(a1\) +1000007c: 8ca58038 lw a1,-32712\(a1\) 10000080: 3c050000 lui a1,0x0 10000084: 00bc2821 addu a1,a1,gp -10000088: 8ca58018 lw a1,-32744\(a1\) +10000088: 8ca58038 lw a1,-32712\(a1\) 1000008c: 24a5000c addiu a1,a1,12 10000090: 3c050000 lui a1,0x0 10000094: 00bc2821 addu a1,a1,gp -10000098: 8ca58018 lw a1,-32744\(a1\) +10000098: 8ca58038 lw a1,-32712\(a1\) 1000009c: 3c010001 lui at,0x1 100000a0: 3421e240 ori at,at,0xe240 100000a4: 00a12821 addu a1,a1,at 100000a8: 3c050000 lui a1,0x0 100000ac: 00bc2821 addu a1,a1,gp -100000b0: 8ca58018 lw a1,-32744\(a1\) +100000b0: 8ca58038 lw a1,-32712\(a1\) 100000b4: 00b12821 addu a1,a1,s1 100000b8: 3c050000 lui a1,0x0 100000bc: 00bc2821 addu a1,a1,gp -100000c0: 8ca58018 lw a1,-32744\(a1\) +100000c0: 8ca58038 lw a1,-32712\(a1\) 100000c4: 24a5000c addiu a1,a1,12 100000c8: 00b12821 addu a1,a1,s1 100000cc: 3c050000 lui a1,0x0 100000d0: 00bc2821 addu a1,a1,gp -100000d4: 8ca58018 lw a1,-32744\(a1\) +100000d4: 8ca58038 lw a1,-32712\(a1\) 100000d8: 3c010001 lui at,0x1 100000dc: 3421e240 ori at,at,0xe240 100000e0: 00a12821 addu a1,a1,at 100000e4: 00b12821 addu a1,a1,s1 100000e8: 3c050000 lui a1,0x0 100000ec: 00bc2821 addu a1,a1,gp -100000f0: 8ca58018 lw a1,-32744\(a1\) +100000f0: 8ca58038 lw a1,-32712\(a1\) 100000f4: 8ca50000 lw a1,0\(a1\) 100000f8: 3c050000 lui a1,0x0 100000fc: 00bc2821 addu a1,a1,gp -10000100: 8ca58018 lw a1,-32744\(a1\) +10000100: 8ca58038 lw a1,-32712\(a1\) 10000104: 8ca5000c lw a1,12\(a1\) 10000108: 3c050000 lui a1,0x0 1000010c: 00bc2821 addu a1,a1,gp -10000110: 8ca58018 lw a1,-32744\(a1\) +10000110: 8ca58038 lw a1,-32712\(a1\) 10000114: 00b12821 addu a1,a1,s1 10000118: 8ca50000 lw a1,0\(a1\) 1000011c: 3c050000 lui a1,0x0 10000120: 00bc2821 addu a1,a1,gp -10000124: 8ca58018 lw a1,-32744\(a1\) +10000124: 8ca58038 lw a1,-32712\(a1\) 10000128: 00b12821 addu a1,a1,s1 1000012c: 8ca5000c lw a1,12\(a1\) 10000130: 3c010000 lui at,0x0 10000134: 003c0821 addu at,at,gp -10000138: 8c218018 lw at,-32744\(at\) +10000138: 8c218038 lw at,-32712\(at\) 1000013c: 00250821 addu at,at,a1 10000140: 8c250022 lw a1,34\(at\) 10000144: 3c010000 lui at,0x0 10000148: 003c0821 addu at,at,gp -1000014c: 8c218018 lw at,-32744\(at\) +1000014c: 8c218038 lw at,-32712\(at\) 10000150: 00250821 addu at,at,a1 10000154: ac250038 sw a1,56\(at\) 10000158: 3c010000 lui at,0x0 1000015c: 003c0821 addu at,at,gp -10000160: 8c218018 lw at,-32744\(at\) +10000160: 8c218038 lw at,-32712\(at\) 10000164: 88250000 lwl a1,0\(at\) 10000168: 98250003 lwr a1,3\(at\) 1000016c: 3c010000 lui at,0x0 10000170: 003c0821 addu at,at,gp -10000174: 8c218018 lw at,-32744\(at\) +10000174: 8c218038 lw at,-32712\(at\) 10000178: 2421000c addiu at,at,12 1000017c: 88250000 lwl a1,0\(at\) 10000180: 98250003 lwr a1,3\(at\) 10000184: 3c010000 lui at,0x0 10000188: 003c0821 addu at,at,gp -1000018c: 8c218018 lw at,-32744\(at\) +1000018c: 8c218038 lw at,-32712\(at\) 10000190: 00310821 addu at,at,s1 10000194: 88250000 lwl a1,0\(at\) 10000198: 98250003 lwr a1,3\(at\) 1000019c: 3c010000 lui at,0x0 100001a0: 003c0821 addu at,at,gp -100001a4: 8c218018 lw at,-32744\(at\) +100001a4: 8c218038 lw at,-32712\(at\) 100001a8: 2421000c addiu at,at,12 100001ac: 00310821 addu at,at,s1 100001b0: 88250000 lwl a1,0\(at\) 100001b4: 98250003 lwr a1,3\(at\) 100001b8: 3c010000 lui at,0x0 100001bc: 003c0821 addu at,at,gp -100001c0: 8c218018 lw at,-32744\(at\) +100001c0: 8c218038 lw at,-32712\(at\) 100001c4: 24210022 addiu at,at,34 100001c8: 00250821 addu at,at,a1 100001cc: 88250000 lwl a1,0\(at\) 100001d0: 98250003 lwr a1,3\(at\) 100001d4: 3c010000 lui at,0x0 100001d8: 003c0821 addu at,at,gp -100001dc: 8c218018 lw at,-32744\(at\) +100001dc: 8c218038 lw at,-32712\(at\) 100001e0: 24210038 addiu at,at,56 100001e4: 00250821 addu at,at,a1 100001e8: a8250000 swl a1,0\(at\) 100001ec: b8250003 swr a1,3\(at\) -100001f0: 8f85801c lw a1,-32740\(gp\) +100001f0: 8f858018 lw a1,-32744\(gp\) 100001f4: 24a506b8 addiu a1,a1,1720 -100001f8: 8f85801c lw a1,-32740\(gp\) +100001f8: 8f858018 lw a1,-32744\(gp\) 100001fc: 24a506c4 addiu a1,a1,1732 -10000200: 8f858020 lw a1,-32736\(gp\) +10000200: 8f85801c lw a1,-32740\(gp\) 10000204: 24a5e8f8 addiu a1,a1,-5896 -10000208: 8f85801c lw a1,-32740\(gp\) +10000208: 8f858018 lw a1,-32744\(gp\) 1000020c: 24a506b8 addiu a1,a1,1720 10000210: 00b12821 addu a1,a1,s1 -10000214: 8f85801c lw a1,-32740\(gp\) +10000214: 8f858018 lw a1,-32744\(gp\) 10000218: 24a506c4 addiu a1,a1,1732 1000021c: 00b12821 addu a1,a1,s1 -10000220: 8f858020 lw a1,-32736\(gp\) +10000220: 8f85801c lw a1,-32740\(gp\) 10000224: 24a5e8f8 addiu a1,a1,-5896 10000228: 00b12821 addu a1,a1,s1 -1000022c: 8f85801c lw a1,-32740\(gp\) +1000022c: 8f858018 lw a1,-32744\(gp\) 10000230: 8ca506b8 lw a1,1720\(a1\) -10000234: 8f85801c lw a1,-32740\(gp\) +10000234: 8f858018 lw a1,-32744\(gp\) 10000238: 8ca506c4 lw a1,1732\(a1\) -1000023c: 8f85801c lw a1,-32740\(gp\) +1000023c: 8f858018 lw a1,-32744\(gp\) 10000240: 00b12821 addu a1,a1,s1 10000244: 8ca506b8 lw a1,1720\(a1\) -10000248: 8f85801c lw a1,-32740\(gp\) +10000248: 8f858018 lw a1,-32744\(gp\) 1000024c: 00b12821 addu a1,a1,s1 10000250: 8ca506c4 lw a1,1732\(a1\) -10000254: 8f81801c lw at,-32740\(gp\) +10000254: 8f818018 lw at,-32744\(gp\) 10000258: 00250821 addu at,at,a1 1000025c: 8c2506da lw a1,1754\(at\) -10000260: 8f81801c lw at,-32740\(gp\) +10000260: 8f818018 lw at,-32744\(gp\) 10000264: 00250821 addu at,at,a1 10000268: ac2506f0 sw a1,1776\(at\) -1000026c: 8f81801c lw at,-32740\(gp\) +1000026c: 8f818018 lw at,-32744\(gp\) 10000270: 242106b8 addiu at,at,1720 10000274: 88250000 lwl a1,0\(at\) 10000278: 98250003 lwr a1,3\(at\) -1000027c: 8f81801c lw at,-32740\(gp\) +1000027c: 8f818018 lw at,-32744\(gp\) 10000280: 242106c4 addiu at,at,1732 10000284: 88250000 lwl a1,0\(at\) 10000288: 98250003 lwr a1,3\(at\) -1000028c: 8f81801c lw at,-32740\(gp\) +1000028c: 8f818018 lw at,-32744\(gp\) 10000290: 242106b8 addiu at,at,1720 10000294: 00310821 addu at,at,s1 10000298: 88250000 lwl a1,0\(at\) 1000029c: 98250003 lwr a1,3\(at\) -100002a0: 8f81801c lw at,-32740\(gp\) +100002a0: 8f818018 lw at,-32744\(gp\) 100002a4: 242106c4 addiu at,at,1732 100002a8: 00310821 addu at,at,s1 100002ac: 88250000 lwl a1,0\(at\) 100002b0: 98250003 lwr a1,3\(at\) -100002b4: 8f81801c lw at,-32740\(gp\) +100002b4: 8f818018 lw at,-32744\(gp\) 100002b8: 242106da addiu at,at,1754 100002bc: 00250821 addu at,at,a1 100002c0: 88250000 lwl a1,0\(at\) 100002c4: 98250003 lwr a1,3\(at\) -100002c8: 8f81801c lw at,-32740\(gp\) +100002c8: 8f818018 lw at,-32744\(gp\) 100002cc: 242106f0 addiu at,at,1776 100002d0: 00250821 addu at,at,a1 100002d4: a8250000 swl a1,0\(at\) 100002d8: b8250003 swr a1,3\(at\) 100002dc: 3c050000 lui a1,0x0 100002e0: 00bc2821 addu a1,a1,gp -100002e4: 8ca58024 lw a1,-32732\(a1\) -100002e8: 8f858028 lw a1,-32728\(gp\) +100002e4: 8ca58034 lw a1,-32716\(a1\) +100002e8: 8f858020 lw a1,-32736\(gp\) 100002ec: 24a50074 addiu a1,a1,116 100002f0: 3c190000 lui t9,0x0 100002f4: 033cc821 addu t9,t9,gp -100002f8: 8f398024 lw t9,-32732\(t9\) -100002fc: 8f998028 lw t9,-32728\(gp\) +100002f8: 8f398034 lw t9,-32716\(t9\) +100002fc: 8f998020 lw t9,-32736\(gp\) 10000300: 27390074 addiu t9,t9,116 10000304: 3c190000 lui t9,0x0 10000308: 033cc821 addu t9,t9,gp -1000030c: 8f398024 lw t9,-32732\(t9\) +1000030c: 8f398034 lw t9,-32716\(t9\) 10000310: 0411ff58 bal 10000074 <fn> 10000314: 00000000 nop -10000318: 8f998028 lw t9,-32728\(gp\) +10000318: 8f998020 lw t9,-32736\(gp\) 1000031c: 27390074 addiu t9,t9,116 10000320: 0411ff54 bal 10000074 <fn> 10000324: 00000000 nop 10000328: 3c050000 lui a1,0x0 1000032c: 00bc2821 addu a1,a1,gp -10000330: 8ca5802c lw a1,-32724\(a1\) +10000330: 8ca58030 lw a1,-32720\(a1\) 10000334: 3c050000 lui a1,0x0 10000338: 00bc2821 addu a1,a1,gp -1000033c: 8ca5802c lw a1,-32724\(a1\) +1000033c: 8ca58030 lw a1,-32720\(a1\) 10000340: 24a5000c addiu a1,a1,12 10000344: 3c050000 lui a1,0x0 10000348: 00bc2821 addu a1,a1,gp -1000034c: 8ca5802c lw a1,-32724\(a1\) +1000034c: 8ca58030 lw a1,-32720\(a1\) 10000350: 3c010001 lui at,0x1 10000354: 3421e240 ori at,at,0xe240 10000358: 00a12821 addu a1,a1,at 1000035c: 3c050000 lui a1,0x0 10000360: 00bc2821 addu a1,a1,gp -10000364: 8ca5802c lw a1,-32724\(a1\) +10000364: 8ca58030 lw a1,-32720\(a1\) 10000368: 00b12821 addu a1,a1,s1 1000036c: 3c050000 lui a1,0x0 10000370: 00bc2821 addu a1,a1,gp -10000374: 8ca5802c lw a1,-32724\(a1\) +10000374: 8ca58030 lw a1,-32720\(a1\) 10000378: 24a5000c addiu a1,a1,12 1000037c: 00b12821 addu a1,a1,s1 10000380: 3c050000 lui a1,0x0 10000384: 00bc2821 addu a1,a1,gp -10000388: 8ca5802c lw a1,-32724\(a1\) +10000388: 8ca58030 lw a1,-32720\(a1\) 1000038c: 3c010001 lui at,0x1 10000390: 3421e240 ori at,at,0xe240 10000394: 00a12821 addu a1,a1,at 10000398: 00b12821 addu a1,a1,s1 1000039c: 3c050000 lui a1,0x0 100003a0: 00bc2821 addu a1,a1,gp -100003a4: 8ca5802c lw a1,-32724\(a1\) +100003a4: 8ca58030 lw a1,-32720\(a1\) 100003a8: 8ca50000 lw a1,0\(a1\) 100003ac: 3c050000 lui a1,0x0 100003b0: 00bc2821 addu a1,a1,gp -100003b4: 8ca5802c lw a1,-32724\(a1\) +100003b4: 8ca58030 lw a1,-32720\(a1\) 100003b8: 8ca5000c lw a1,12\(a1\) 100003bc: 3c050000 lui a1,0x0 100003c0: 00bc2821 addu a1,a1,gp -100003c4: 8ca5802c lw a1,-32724\(a1\) +100003c4: 8ca58030 lw a1,-32720\(a1\) 100003c8: 00b12821 addu a1,a1,s1 100003cc: 8ca50000 lw a1,0\(a1\) 100003d0: 3c050000 lui a1,0x0 100003d4: 00bc2821 addu a1,a1,gp -100003d8: 8ca5802c lw a1,-32724\(a1\) +100003d8: 8ca58030 lw a1,-32720\(a1\) 100003dc: 00b12821 addu a1,a1,s1 100003e0: 8ca5000c lw a1,12\(a1\) 100003e4: 3c010000 lui at,0x0 100003e8: 003c0821 addu at,at,gp -100003ec: 8c21802c lw at,-32724\(at\) +100003ec: 8c218030 lw at,-32720\(at\) 100003f0: 00250821 addu at,at,a1 100003f4: 8c250022 lw a1,34\(at\) 100003f8: 3c010000 lui at,0x0 100003fc: 003c0821 addu at,at,gp -10000400: 8c21802c lw at,-32724\(at\) +10000400: 8c218030 lw at,-32720\(at\) 10000404: 00250821 addu at,at,a1 10000408: ac250038 sw a1,56\(at\) 1000040c: 3c010000 lui at,0x0 10000410: 003c0821 addu at,at,gp -10000414: 8c21802c lw at,-32724\(at\) +10000414: 8c218030 lw at,-32720\(at\) 10000418: 88250000 lwl a1,0\(at\) 1000041c: 98250003 lwr a1,3\(at\) 10000420: 3c010000 lui at,0x0 10000424: 003c0821 addu at,at,gp -10000428: 8c21802c lw at,-32724\(at\) +10000428: 8c218030 lw at,-32720\(at\) 1000042c: 2421000c addiu at,at,12 10000430: 88250000 lwl a1,0\(at\) 10000434: 98250003 lwr a1,3\(at\) 10000438: 3c010000 lui at,0x0 1000043c: 003c0821 addu at,at,gp -10000440: 8c21802c lw at,-32724\(at\) +10000440: 8c218030 lw at,-32720\(at\) 10000444: 00310821 addu at,at,s1 10000448: 88250000 lwl a1,0\(at\) 1000044c: 98250003 lwr a1,3\(at\) 10000450: 3c010000 lui at,0x0 10000454: 003c0821 addu at,at,gp -10000458: 8c21802c lw at,-32724\(at\) +10000458: 8c218030 lw at,-32720\(at\) 1000045c: 2421000c addiu at,at,12 10000460: 00310821 addu at,at,s1 10000464: 88250000 lwl a1,0\(at\) 10000468: 98250003 lwr a1,3\(at\) 1000046c: 3c010000 lui at,0x0 10000470: 003c0821 addu at,at,gp -10000474: 8c21802c lw at,-32724\(at\) +10000474: 8c218030 lw at,-32720\(at\) 10000478: 24210022 addiu at,at,34 1000047c: 00250821 addu at,at,a1 10000480: 88250000 lwl a1,0\(at\) 10000484: 98250003 lwr a1,3\(at\) 10000488: 3c010000 lui at,0x0 1000048c: 003c0821 addu at,at,gp -10000490: 8c21802c lw at,-32724\(at\) +10000490: 8c218030 lw at,-32720\(at\) 10000494: 24210038 addiu at,at,56 10000498: 00250821 addu at,at,a1 1000049c: a8250000 swl a1,0\(at\) 100004a0: b8250003 swr a1,3\(at\) -100004a4: 8f85801c lw a1,-32740\(gp\) +100004a4: 8f858018 lw a1,-32744\(gp\) 100004a8: 24a50730 addiu a1,a1,1840 -100004ac: 8f85801c lw a1,-32740\(gp\) +100004ac: 8f858018 lw a1,-32744\(gp\) 100004b0: 24a5073c addiu a1,a1,1852 -100004b4: 8f858020 lw a1,-32736\(gp\) +100004b4: 8f85801c lw a1,-32740\(gp\) 100004b8: 24a5e970 addiu a1,a1,-5776 -100004bc: 8f85801c lw a1,-32740\(gp\) +100004bc: 8f858018 lw a1,-32744\(gp\) 100004c0: 24a50730 addiu a1,a1,1840 100004c4: 00b12821 addu a1,a1,s1 -100004c8: 8f85801c lw a1,-32740\(gp\) +100004c8: 8f858018 lw a1,-32744\(gp\) 100004cc: 24a5073c addiu a1,a1,1852 100004d0: 00b12821 addu a1,a1,s1 -100004d4: 8f858020 lw a1,-32736\(gp\) +100004d4: 8f85801c lw a1,-32740\(gp\) 100004d8: 24a5e970 addiu a1,a1,-5776 100004dc: 00b12821 addu a1,a1,s1 -100004e0: 8f85801c lw a1,-32740\(gp\) +100004e0: 8f858018 lw a1,-32744\(gp\) 100004e4: 8ca50730 lw a1,1840\(a1\) -100004e8: 8f85801c lw a1,-32740\(gp\) +100004e8: 8f858018 lw a1,-32744\(gp\) 100004ec: 8ca5073c lw a1,1852\(a1\) -100004f0: 8f85801c lw a1,-32740\(gp\) +100004f0: 8f858018 lw a1,-32744\(gp\) 100004f4: 00b12821 addu a1,a1,s1 100004f8: 8ca50730 lw a1,1840\(a1\) -100004fc: 8f85801c lw a1,-32740\(gp\) +100004fc: 8f858018 lw a1,-32744\(gp\) 10000500: 00b12821 addu a1,a1,s1 10000504: 8ca5073c lw a1,1852\(a1\) -10000508: 8f81801c lw at,-32740\(gp\) +10000508: 8f818018 lw at,-32744\(gp\) 1000050c: 00250821 addu at,at,a1 10000510: 8c250752 lw a1,1874\(at\) -10000514: 8f81801c lw at,-32740\(gp\) +10000514: 8f818018 lw at,-32744\(gp\) 10000518: 00250821 addu at,at,a1 1000051c: ac250768 sw a1,1896\(at\) -10000520: 8f81801c lw at,-32740\(gp\) +10000520: 8f818018 lw at,-32744\(gp\) 10000524: 24210730 addiu at,at,1840 10000528: 88250000 lwl a1,0\(at\) 1000052c: 98250003 lwr a1,3\(at\) -10000530: 8f81801c lw at,-32740\(gp\) +10000530: 8f818018 lw at,-32744\(gp\) 10000534: 2421073c addiu at,at,1852 10000538: 88250000 lwl a1,0\(at\) 1000053c: 98250003 lwr a1,3\(at\) -10000540: 8f81801c lw at,-32740\(gp\) +10000540: 8f818018 lw at,-32744\(gp\) 10000544: 24210730 addiu at,at,1840 10000548: 00310821 addu at,at,s1 1000054c: 88250000 lwl a1,0\(at\) 10000550: 98250003 lwr a1,3\(at\) -10000554: 8f81801c lw at,-32740\(gp\) +10000554: 8f818018 lw at,-32744\(gp\) 10000558: 2421073c addiu at,at,1852 1000055c: 00310821 addu at,at,s1 10000560: 88250000 lwl a1,0\(at\) 10000564: 98250003 lwr a1,3\(at\) -10000568: 8f81801c lw at,-32740\(gp\) +10000568: 8f818018 lw at,-32744\(gp\) 1000056c: 24210752 addiu at,at,1874 10000570: 00250821 addu at,at,a1 10000574: 88250000 lwl a1,0\(at\) 10000578: 98250003 lwr a1,3\(at\) -1000057c: 8f81801c lw at,-32740\(gp\) +1000057c: 8f818018 lw at,-32744\(gp\) 10000580: 24210768 addiu at,at,1896 10000584: 00250821 addu at,at,a1 10000588: a8250000 swl a1,0\(at\) 1000058c: b8250003 swr a1,3\(at\) 10000590: 3c050000 lui a1,0x0 10000594: 00bc2821 addu a1,a1,gp -10000598: 8ca58030 lw a1,-32720\(a1\) -1000059c: 8f858028 lw a1,-32728\(gp\) +10000598: 8ca5802c lw a1,-32724\(a1\) +1000059c: 8f858020 lw a1,-32736\(gp\) 100005a0: 24a50674 addiu a1,a1,1652 100005a4: 3c190000 lui t9,0x0 100005a8: 033cc821 addu t9,t9,gp -100005ac: 8f398030 lw t9,-32720\(t9\) -100005b0: 8f998028 lw t9,-32728\(gp\) +100005ac: 8f39802c lw t9,-32724\(t9\) +100005b0: 8f998020 lw t9,-32736\(gp\) 100005b4: 27390674 addiu t9,t9,1652 100005b8: 3c190000 lui t9,0x0 100005bc: 033cc821 addu t9,t9,gp -100005c0: 8f398030 lw t9,-32720\(t9\) +100005c0: 8f39802c lw t9,-32724\(t9\) 100005c4: 0411002b bal 10000674 <fn2> 100005c8: 00000000 nop -100005cc: 8f998028 lw t9,-32728\(gp\) +100005cc: 8f998020 lw t9,-32736\(gp\) 100005d0: 27390674 addiu t9,t9,1652 100005d4: 04110027 bal 10000674 <fn2> 100005d8: 00000000 nop 100005dc: 3c050000 lui a1,0x0 100005e0: 00bc2821 addu a1,a1,gp -100005e4: 8ca58018 lw a1,-32744\(a1\) +100005e4: 8ca58038 lw a1,-32712\(a1\) 100005e8: 1000fea2 b 10000074 <fn> 100005ec: 00000000 nop 100005f0: 3c050000 lui a1,0x0 100005f4: 00bc2821 addu a1,a1,gp -100005f8: 8ca5802c lw a1,-32724\(a1\) +100005f8: 8ca58030 lw a1,-32720\(a1\) 100005fc: 8ca50000 lw a1,0\(a1\) 10000600: 1000001c b 10000674 <fn2> 10000604: 00000000 nop -10000608: 8f85801c lw a1,-32740\(gp\) +10000608: 8f858018 lw a1,-32744\(gp\) 1000060c: 24a506b8 addiu a1,a1,1720 10000610: 1000fe98 b 10000074 <fn> 10000614: 00000000 nop -10000618: 8f85801c lw a1,-32740\(gp\) +10000618: 8f858018 lw a1,-32744\(gp\) 1000061c: 24a5073c addiu a1,a1,1852 10000620: 10000014 b 10000674 <fn2> 10000624: 00000000 nop -10000628: 8f858020 lw a1,-32736\(gp\) +10000628: 8f85801c lw a1,-32740\(gp\) 1000062c: 24a5e8f8 addiu a1,a1,-5896 10000630: 1000fe90 b 10000074 <fn> 10000634: 00000000 nop -10000638: 8f85801c lw a1,-32740\(gp\) +10000638: 8f858018 lw a1,-32744\(gp\) 1000063c: 8ca50730 lw a1,1840\(a1\) 10000640: 1000000c b 10000674 <fn2> 10000644: 00000000 nop -10000648: 8f85801c lw a1,-32740\(gp\) +10000648: 8f858018 lw a1,-32744\(gp\) 1000064c: 8ca506c4 lw a1,1732\(a1\) 10000650: 1000fe88 b 10000074 <fn> 10000654: 00000000 nop -10000658: 8f81801c lw at,-32740\(gp\) +10000658: 8f818018 lw at,-32744\(gp\) 1000065c: 00250821 addu at,at,a1 10000660: 8c250752 lw a1,1874\(at\) 10000664: 10000003 b 10000674 <fn2> @@ -422,13 +423,13 @@ Disassembly of section \.got: 10010770 <_GLOBAL_OFFSET_TABLE_>: 10010770: 00000000 .* 10010774: 80000000 .* -10010778: 100106b8 .* -1001077c: 10010000 .* -10010780: 10030000 .* -10010784: 10000074 .* -10010788: 10000000 .* -1001078c: 10010730 .* -10010790: 10000674 .* -10010794: 00000000 .* -10010798: 00000000 .* +10010778: 10010000 .* +1001077c: 10030000 .* +10010780: 10000000 .* +10010784: 00000000 .* +10010788: 00000000 .* +1001078c: 10000674 .* +10010790: 10010730 .* +10010794: 10000074 .* +10010798: 100106b8 .* #pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d index 4e105aa..b202e92 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d @@ -1,6 +1,7 @@ #name: MIPS ELF xgot reloc n32 #as: -march=from-abi -EB -n32 -KPIC -xgot -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn @@ -18,382 +19,382 @@ Disassembly of section \.text: 100000b0 <fn>: 100000b0: 3c050000 lui a1,0x0 100000b4: 00bc2821 addu a1,a1,gp -100000b8: 8ca58018 lw a1,-32744\(a1\) +100000b8: 8ca58038 lw a1,-32712\(a1\) 100000bc: 3c050000 lui a1,0x0 100000c0: 00bc2821 addu a1,a1,gp -100000c4: 8ca58018 lw a1,-32744\(a1\) +100000c4: 8ca58038 lw a1,-32712\(a1\) 100000c8: 24a5000c addiu a1,a1,12 100000cc: 3c050000 lui a1,0x0 100000d0: 00bc2821 addu a1,a1,gp -100000d4: 8ca58018 lw a1,-32744\(a1\) +100000d4: 8ca58038 lw a1,-32712\(a1\) 100000d8: 3c010001 lui at,0x1 100000dc: 3421e240 ori at,at,0xe240 100000e0: 00a12821 addu a1,a1,at 100000e4: 3c050000 lui a1,0x0 100000e8: 00bc2821 addu a1,a1,gp -100000ec: 8ca58018 lw a1,-32744\(a1\) +100000ec: 8ca58038 lw a1,-32712\(a1\) 100000f0: 00b12821 addu a1,a1,s1 100000f4: 3c050000 lui a1,0x0 100000f8: 00bc2821 addu a1,a1,gp -100000fc: 8ca58018 lw a1,-32744\(a1\) +100000fc: 8ca58038 lw a1,-32712\(a1\) 10000100: 24a5000c addiu a1,a1,12 10000104: 00b12821 addu a1,a1,s1 10000108: 3c050000 lui a1,0x0 1000010c: 00bc2821 addu a1,a1,gp -10000110: 8ca58018 lw a1,-32744\(a1\) +10000110: 8ca58038 lw a1,-32712\(a1\) 10000114: 3c010001 lui at,0x1 10000118: 3421e240 ori at,at,0xe240 1000011c: 00a12821 addu a1,a1,at 10000120: 00b12821 addu a1,a1,s1 10000124: 3c050000 lui a1,0x0 10000128: 00bc2821 addu a1,a1,gp -1000012c: 8ca58018 lw a1,-32744\(a1\) +1000012c: 8ca58038 lw a1,-32712\(a1\) 10000130: 8ca50000 lw a1,0\(a1\) 10000134: 3c050000 lui a1,0x0 10000138: 00bc2821 addu a1,a1,gp -1000013c: 8ca58018 lw a1,-32744\(a1\) +1000013c: 8ca58038 lw a1,-32712\(a1\) 10000140: 8ca5000c lw a1,12\(a1\) 10000144: 3c050000 lui a1,0x0 10000148: 00bc2821 addu a1,a1,gp -1000014c: 8ca58018 lw a1,-32744\(a1\) +1000014c: 8ca58038 lw a1,-32712\(a1\) 10000150: 00b12821 addu a1,a1,s1 10000154: 8ca50000 lw a1,0\(a1\) 10000158: 3c050000 lui a1,0x0 1000015c: 00bc2821 addu a1,a1,gp -10000160: 8ca58018 lw a1,-32744\(a1\) +10000160: 8ca58038 lw a1,-32712\(a1\) 10000164: 00b12821 addu a1,a1,s1 10000168: 8ca5000c lw a1,12\(a1\) 1000016c: 3c010000 lui at,0x0 10000170: 003c0821 addu at,at,gp -10000174: 8c218018 lw at,-32744\(at\) +10000174: 8c218038 lw at,-32712\(at\) 10000178: 00250821 addu at,at,a1 1000017c: 8c250022 lw a1,34\(at\) 10000180: 3c010000 lui at,0x0 10000184: 003c0821 addu at,at,gp -10000188: 8c218018 lw at,-32744\(at\) +10000188: 8c218038 lw at,-32712\(at\) 1000018c: 00250821 addu at,at,a1 10000190: ac250038 sw a1,56\(at\) 10000194: 3c010000 lui at,0x0 10000198: 003c0821 addu at,at,gp -1000019c: 8c218018 lw at,-32744\(at\) +1000019c: 8c218038 lw at,-32712\(at\) 100001a0: 88250000 lwl a1,0\(at\) 100001a4: 98250003 lwr a1,3\(at\) 100001a8: 3c010000 lui at,0x0 100001ac: 003c0821 addu at,at,gp -100001b0: 8c218018 lw at,-32744\(at\) +100001b0: 8c218038 lw at,-32712\(at\) 100001b4: 2421000c addiu at,at,12 100001b8: 88250000 lwl a1,0\(at\) 100001bc: 98250003 lwr a1,3\(at\) 100001c0: 3c010000 lui at,0x0 100001c4: 003c0821 addu at,at,gp -100001c8: 8c218018 lw at,-32744\(at\) +100001c8: 8c218038 lw at,-32712\(at\) 100001cc: 00310821 addu at,at,s1 100001d0: 88250000 lwl a1,0\(at\) 100001d4: 98250003 lwr a1,3\(at\) 100001d8: 3c010000 lui at,0x0 100001dc: 003c0821 addu at,at,gp -100001e0: 8c218018 lw at,-32744\(at\) +100001e0: 8c218038 lw at,-32712\(at\) 100001e4: 2421000c addiu at,at,12 100001e8: 00310821 addu at,at,s1 100001ec: 88250000 lwl a1,0\(at\) 100001f0: 98250003 lwr a1,3\(at\) 100001f4: 3c010000 lui at,0x0 100001f8: 003c0821 addu at,at,gp -100001fc: 8c218018 lw at,-32744\(at\) +100001fc: 8c218038 lw at,-32712\(at\) 10000200: 24210022 addiu at,at,34 10000204: 00250821 addu at,at,a1 10000208: 88250000 lwl a1,0\(at\) 1000020c: 98250003 lwr a1,3\(at\) 10000210: 3c010000 lui at,0x0 10000214: 003c0821 addu at,at,gp -10000218: 8c218018 lw at,-32744\(at\) +10000218: 8c218038 lw at,-32712\(at\) 1000021c: 24210038 addiu at,at,56 10000220: 00250821 addu at,at,a1 10000224: a8250000 swl a1,0\(at\) 10000228: b8250003 swr a1,3\(at\) -1000022c: 8f85801c lw a1,-32740\(gp\) +1000022c: 8f858018 lw a1,-32744\(gp\) 10000230: 24a506fc addiu a1,a1,1788 -10000234: 8f85801c lw a1,-32740\(gp\) +10000234: 8f858018 lw a1,-32744\(gp\) 10000238: 24a50708 addiu a1,a1,1800 -1000023c: 8f858020 lw a1,-32736\(gp\) +1000023c: 8f85801c lw a1,-32740\(gp\) 10000240: 24a5e93c addiu a1,a1,-5828 -10000244: 8f85801c lw a1,-32740\(gp\) +10000244: 8f858018 lw a1,-32744\(gp\) 10000248: 24a506fc addiu a1,a1,1788 1000024c: 00b12821 addu a1,a1,s1 -10000250: 8f85801c lw a1,-32740\(gp\) +10000250: 8f858018 lw a1,-32744\(gp\) 10000254: 24a50708 addiu a1,a1,1800 10000258: 00b12821 addu a1,a1,s1 -1000025c: 8f858020 lw a1,-32736\(gp\) +1000025c: 8f85801c lw a1,-32740\(gp\) 10000260: 24a5e93c addiu a1,a1,-5828 10000264: 00b12821 addu a1,a1,s1 -10000268: 8f85801c lw a1,-32740\(gp\) +10000268: 8f858018 lw a1,-32744\(gp\) 1000026c: 8ca506fc lw a1,1788\(a1\) -10000270: 8f85801c lw a1,-32740\(gp\) +10000270: 8f858018 lw a1,-32744\(gp\) 10000274: 8ca50708 lw a1,1800\(a1\) -10000278: 8f85801c lw a1,-32740\(gp\) +10000278: 8f858018 lw a1,-32744\(gp\) 1000027c: 00b12821 addu a1,a1,s1 10000280: 8ca506fc lw a1,1788\(a1\) -10000284: 8f85801c lw a1,-32740\(gp\) +10000284: 8f858018 lw a1,-32744\(gp\) 10000288: 00b12821 addu a1,a1,s1 1000028c: 8ca50708 lw a1,1800\(a1\) -10000290: 8f81801c lw at,-32740\(gp\) +10000290: 8f818018 lw at,-32744\(gp\) 10000294: 00250821 addu at,at,a1 10000298: 8c25071e lw a1,1822\(at\) -1000029c: 8f81801c lw at,-32740\(gp\) +1000029c: 8f818018 lw at,-32744\(gp\) 100002a0: 00250821 addu at,at,a1 100002a4: ac250734 sw a1,1844\(at\) -100002a8: 8f81801c lw at,-32740\(gp\) +100002a8: 8f818018 lw at,-32744\(gp\) 100002ac: 242106fc addiu at,at,1788 100002b0: 88250000 lwl a1,0\(at\) 100002b4: 98250003 lwr a1,3\(at\) -100002b8: 8f81801c lw at,-32740\(gp\) +100002b8: 8f818018 lw at,-32744\(gp\) 100002bc: 24210708 addiu at,at,1800 100002c0: 88250000 lwl a1,0\(at\) 100002c4: 98250003 lwr a1,3\(at\) -100002c8: 8f81801c lw at,-32740\(gp\) +100002c8: 8f818018 lw at,-32744\(gp\) 100002cc: 242106fc addiu at,at,1788 100002d0: 00310821 addu at,at,s1 100002d4: 88250000 lwl a1,0\(at\) 100002d8: 98250003 lwr a1,3\(at\) -100002dc: 8f81801c lw at,-32740\(gp\) +100002dc: 8f818018 lw at,-32744\(gp\) 100002e0: 24210708 addiu at,at,1800 100002e4: 00310821 addu at,at,s1 100002e8: 88250000 lwl a1,0\(at\) 100002ec: 98250003 lwr a1,3\(at\) -100002f0: 8f81801c lw at,-32740\(gp\) +100002f0: 8f818018 lw at,-32744\(gp\) 100002f4: 2421071e addiu at,at,1822 100002f8: 00250821 addu at,at,a1 100002fc: 88250000 lwl a1,0\(at\) 10000300: 98250003 lwr a1,3\(at\) -10000304: 8f81801c lw at,-32740\(gp\) +10000304: 8f818018 lw at,-32744\(gp\) 10000308: 24210734 addiu at,at,1844 1000030c: 00250821 addu at,at,a1 10000310: a8250000 swl a1,0\(at\) 10000314: b8250003 swr a1,3\(at\) 10000318: 3c050000 lui a1,0x0 1000031c: 00bc2821 addu a1,a1,gp -10000320: 8ca58024 lw a1,-32732\(a1\) -10000324: 8f858028 lw a1,-32728\(gp\) +10000320: 8ca58034 lw a1,-32716\(a1\) +10000324: 8f858020 lw a1,-32736\(gp\) 10000328: 24a500b0 addiu a1,a1,176 1000032c: 3c190000 lui t9,0x0 10000330: 033cc821 addu t9,t9,gp -10000334: 8f398024 lw t9,-32732\(t9\) -10000338: 8f998028 lw t9,-32728\(gp\) +10000334: 8f398034 lw t9,-32716\(t9\) +10000338: 8f998020 lw t9,-32736\(gp\) 1000033c: 273900b0 addiu t9,t9,176 10000340: 3c190000 lui t9,0x0 10000344: 033cc821 addu t9,t9,gp -10000348: 8f398024 lw t9,-32732\(t9\) +10000348: 8f398034 lw t9,-32716\(t9\) 1000034c: 0411ff58 bal 100000b0 <fn> 10000350: 00000000 nop -10000354: 8f998028 lw t9,-32728\(gp\) +10000354: 8f998020 lw t9,-32736\(gp\) 10000358: 273900b0 addiu t9,t9,176 1000035c: 0411ff54 bal 100000b0 <fn> 10000360: 00000000 nop 10000364: 3c050000 lui a1,0x0 10000368: 00bc2821 addu a1,a1,gp -1000036c: 8ca5802c lw a1,-32724\(a1\) +1000036c: 8ca58030 lw a1,-32720\(a1\) 10000370: 3c050000 lui a1,0x0 10000374: 00bc2821 addu a1,a1,gp -10000378: 8ca5802c lw a1,-32724\(a1\) +10000378: 8ca58030 lw a1,-32720\(a1\) 1000037c: 24a5000c addiu a1,a1,12 10000380: 3c050000 lui a1,0x0 10000384: 00bc2821 addu a1,a1,gp -10000388: 8ca5802c lw a1,-32724\(a1\) +10000388: 8ca58030 lw a1,-32720\(a1\) 1000038c: 3c010001 lui at,0x1 10000390: 3421e240 ori at,at,0xe240 10000394: 00a12821 addu a1,a1,at 10000398: 3c050000 lui a1,0x0 1000039c: 00bc2821 addu a1,a1,gp -100003a0: 8ca5802c lw a1,-32724\(a1\) +100003a0: 8ca58030 lw a1,-32720\(a1\) 100003a4: 00b12821 addu a1,a1,s1 100003a8: 3c050000 lui a1,0x0 100003ac: 00bc2821 addu a1,a1,gp -100003b0: 8ca5802c lw a1,-32724\(a1\) +100003b0: 8ca58030 lw a1,-32720\(a1\) 100003b4: 24a5000c addiu a1,a1,12 100003b8: 00b12821 addu a1,a1,s1 100003bc: 3c050000 lui a1,0x0 100003c0: 00bc2821 addu a1,a1,gp -100003c4: 8ca5802c lw a1,-32724\(a1\) +100003c4: 8ca58030 lw a1,-32720\(a1\) 100003c8: 3c010001 lui at,0x1 100003cc: 3421e240 ori at,at,0xe240 100003d0: 00a12821 addu a1,a1,at 100003d4: 00b12821 addu a1,a1,s1 100003d8: 3c050000 lui a1,0x0 100003dc: 00bc2821 addu a1,a1,gp -100003e0: 8ca5802c lw a1,-32724\(a1\) +100003e0: 8ca58030 lw a1,-32720\(a1\) 100003e4: 8ca50000 lw a1,0\(a1\) 100003e8: 3c050000 lui a1,0x0 100003ec: 00bc2821 addu a1,a1,gp -100003f0: 8ca5802c lw a1,-32724\(a1\) +100003f0: 8ca58030 lw a1,-32720\(a1\) 100003f4: 8ca5000c lw a1,12\(a1\) 100003f8: 3c050000 lui a1,0x0 100003fc: 00bc2821 addu a1,a1,gp -10000400: 8ca5802c lw a1,-32724\(a1\) +10000400: 8ca58030 lw a1,-32720\(a1\) 10000404: 00b12821 addu a1,a1,s1 10000408: 8ca50000 lw a1,0\(a1\) 1000040c: 3c050000 lui a1,0x0 10000410: 00bc2821 addu a1,a1,gp -10000414: 8ca5802c lw a1,-32724\(a1\) +10000414: 8ca58030 lw a1,-32720\(a1\) 10000418: 00b12821 addu a1,a1,s1 1000041c: 8ca5000c lw a1,12\(a1\) 10000420: 3c010000 lui at,0x0 10000424: 003c0821 addu at,at,gp -10000428: 8c21802c lw at,-32724\(at\) +10000428: 8c218030 lw at,-32720\(at\) 1000042c: 00250821 addu at,at,a1 10000430: 8c250022 lw a1,34\(at\) 10000434: 3c010000 lui at,0x0 10000438: 003c0821 addu at,at,gp -1000043c: 8c21802c lw at,-32724\(at\) +1000043c: 8c218030 lw at,-32720\(at\) 10000440: 00250821 addu at,at,a1 10000444: ac250038 sw a1,56\(at\) 10000448: 3c010000 lui at,0x0 1000044c: 003c0821 addu at,at,gp -10000450: 8c21802c lw at,-32724\(at\) +10000450: 8c218030 lw at,-32720\(at\) 10000454: 88250000 lwl a1,0\(at\) 10000458: 98250003 lwr a1,3\(at\) 1000045c: 3c010000 lui at,0x0 10000460: 003c0821 addu at,at,gp -10000464: 8c21802c lw at,-32724\(at\) +10000464: 8c218030 lw at,-32720\(at\) 10000468: 2421000c addiu at,at,12 1000046c: 88250000 lwl a1,0\(at\) 10000470: 98250003 lwr a1,3\(at\) 10000474: 3c010000 lui at,0x0 10000478: 003c0821 addu at,at,gp -1000047c: 8c21802c lw at,-32724\(at\) +1000047c: 8c218030 lw at,-32720\(at\) 10000480: 00310821 addu at,at,s1 10000484: 88250000 lwl a1,0\(at\) 10000488: 98250003 lwr a1,3\(at\) 1000048c: 3c010000 lui at,0x0 10000490: 003c0821 addu at,at,gp -10000494: 8c21802c lw at,-32724\(at\) +10000494: 8c218030 lw at,-32720\(at\) 10000498: 2421000c addiu at,at,12 1000049c: 00310821 addu at,at,s1 100004a0: 88250000 lwl a1,0\(at\) 100004a4: 98250003 lwr a1,3\(at\) 100004a8: 3c010000 lui at,0x0 100004ac: 003c0821 addu at,at,gp -100004b0: 8c21802c lw at,-32724\(at\) +100004b0: 8c218030 lw at,-32720\(at\) 100004b4: 24210022 addiu at,at,34 100004b8: 00250821 addu at,at,a1 100004bc: 88250000 lwl a1,0\(at\) 100004c0: 98250003 lwr a1,3\(at\) 100004c4: 3c010000 lui at,0x0 100004c8: 003c0821 addu at,at,gp -100004cc: 8c21802c lw at,-32724\(at\) +100004cc: 8c218030 lw at,-32720\(at\) 100004d0: 24210038 addiu at,at,56 100004d4: 00250821 addu at,at,a1 100004d8: a8250000 swl a1,0\(at\) 100004dc: b8250003 swr a1,3\(at\) -100004e0: 8f85801c lw a1,-32740\(gp\) +100004e0: 8f858018 lw a1,-32744\(gp\) 100004e4: 24a50774 addiu a1,a1,1908 -100004e8: 8f85801c lw a1,-32740\(gp\) +100004e8: 8f858018 lw a1,-32744\(gp\) 100004ec: 24a50780 addiu a1,a1,1920 -100004f0: 8f858020 lw a1,-32736\(gp\) +100004f0: 8f85801c lw a1,-32740\(gp\) 100004f4: 24a5e9b4 addiu a1,a1,-5708 -100004f8: 8f85801c lw a1,-32740\(gp\) +100004f8: 8f858018 lw a1,-32744\(gp\) 100004fc: 24a50774 addiu a1,a1,1908 10000500: 00b12821 addu a1,a1,s1 -10000504: 8f85801c lw a1,-32740\(gp\) +10000504: 8f858018 lw a1,-32744\(gp\) 10000508: 24a50780 addiu a1,a1,1920 1000050c: 00b12821 addu a1,a1,s1 -10000510: 8f858020 lw a1,-32736\(gp\) +10000510: 8f85801c lw a1,-32740\(gp\) 10000514: 24a5e9b4 addiu a1,a1,-5708 10000518: 00b12821 addu a1,a1,s1 -1000051c: 8f85801c lw a1,-32740\(gp\) +1000051c: 8f858018 lw a1,-32744\(gp\) 10000520: 8ca50774 lw a1,1908\(a1\) -10000524: 8f85801c lw a1,-32740\(gp\) +10000524: 8f858018 lw a1,-32744\(gp\) 10000528: 8ca50780 lw a1,1920\(a1\) -1000052c: 8f85801c lw a1,-32740\(gp\) +1000052c: 8f858018 lw a1,-32744\(gp\) 10000530: 00b12821 addu a1,a1,s1 10000534: 8ca50774 lw a1,1908\(a1\) -10000538: 8f85801c lw a1,-32740\(gp\) +10000538: 8f858018 lw a1,-32744\(gp\) 1000053c: 00b12821 addu a1,a1,s1 10000540: 8ca50780 lw a1,1920\(a1\) -10000544: 8f81801c lw at,-32740\(gp\) +10000544: 8f818018 lw at,-32744\(gp\) 10000548: 00250821 addu at,at,a1 1000054c: 8c250796 lw a1,1942\(at\) -10000550: 8f81801c lw at,-32740\(gp\) +10000550: 8f818018 lw at,-32744\(gp\) 10000554: 00250821 addu at,at,a1 10000558: ac2507ac sw a1,1964\(at\) -1000055c: 8f81801c lw at,-32740\(gp\) +1000055c: 8f818018 lw at,-32744\(gp\) 10000560: 24210774 addiu at,at,1908 10000564: 88250000 lwl a1,0\(at\) 10000568: 98250003 lwr a1,3\(at\) -1000056c: 8f81801c lw at,-32740\(gp\) +1000056c: 8f818018 lw at,-32744\(gp\) 10000570: 24210780 addiu at,at,1920 10000574: 88250000 lwl a1,0\(at\) 10000578: 98250003 lwr a1,3\(at\) -1000057c: 8f81801c lw at,-32740\(gp\) +1000057c: 8f818018 lw at,-32744\(gp\) 10000580: 24210774 addiu at,at,1908 10000584: 00310821 addu at,at,s1 10000588: 88250000 lwl a1,0\(at\) 1000058c: 98250003 lwr a1,3\(at\) -10000590: 8f81801c lw at,-32740\(gp\) +10000590: 8f818018 lw at,-32744\(gp\) 10000594: 24210780 addiu at,at,1920 10000598: 00310821 addu at,at,s1 1000059c: 88250000 lwl a1,0\(at\) 100005a0: 98250003 lwr a1,3\(at\) -100005a4: 8f81801c lw at,-32740\(gp\) +100005a4: 8f818018 lw at,-32744\(gp\) 100005a8: 24210796 addiu at,at,1942 100005ac: 00250821 addu at,at,a1 100005b0: 88250000 lwl a1,0\(at\) 100005b4: 98250003 lwr a1,3\(at\) -100005b8: 8f81801c lw at,-32740\(gp\) +100005b8: 8f818018 lw at,-32744\(gp\) 100005bc: 242107ac addiu at,at,1964 100005c0: 00250821 addu at,at,a1 100005c4: a8250000 swl a1,0\(at\) 100005c8: b8250003 swr a1,3\(at\) 100005cc: 3c050000 lui a1,0x0 100005d0: 00bc2821 addu a1,a1,gp -100005d4: 8ca58030 lw a1,-32720\(a1\) -100005d8: 8f858028 lw a1,-32728\(gp\) +100005d4: 8ca5802c lw a1,-32724\(a1\) +100005d8: 8f858020 lw a1,-32736\(gp\) 100005dc: 24a506b0 addiu a1,a1,1712 100005e0: 3c190000 lui t9,0x0 100005e4: 033cc821 addu t9,t9,gp -100005e8: 8f398030 lw t9,-32720\(t9\) -100005ec: 8f998028 lw t9,-32728\(gp\) +100005e8: 8f39802c lw t9,-32724\(t9\) +100005ec: 8f998020 lw t9,-32736\(gp\) 100005f0: 273906b0 addiu t9,t9,1712 100005f4: 3c190000 lui t9,0x0 100005f8: 033cc821 addu t9,t9,gp -100005fc: 8f398030 lw t9,-32720\(t9\) +100005fc: 8f39802c lw t9,-32724\(t9\) 10000600: 0411002b bal 100006b0 <fn2> 10000604: 00000000 nop -10000608: 8f998028 lw t9,-32728\(gp\) +10000608: 8f998020 lw t9,-32736\(gp\) 1000060c: 273906b0 addiu t9,t9,1712 10000610: 04110027 bal 100006b0 <fn2> 10000614: 00000000 nop 10000618: 3c050000 lui a1,0x0 1000061c: 00bc2821 addu a1,a1,gp -10000620: 8ca58018 lw a1,-32744\(a1\) +10000620: 8ca58038 lw a1,-32712\(a1\) 10000624: 1000fea2 b 100000b0 <fn> 10000628: 00000000 nop 1000062c: 3c050000 lui a1,0x0 10000630: 00bc2821 addu a1,a1,gp -10000634: 8ca5802c lw a1,-32724\(a1\) +10000634: 8ca58030 lw a1,-32720\(a1\) 10000638: 8ca50000 lw a1,0\(a1\) 1000063c: 1000001c b 100006b0 <fn2> 10000640: 00000000 nop -10000644: 8f85801c lw a1,-32740\(gp\) +10000644: 8f858018 lw a1,-32744\(gp\) 10000648: 24a506fc addiu a1,a1,1788 1000064c: 1000fe98 b 100000b0 <fn> 10000650: 00000000 nop -10000654: 8f85801c lw a1,-32740\(gp\) +10000654: 8f858018 lw a1,-32744\(gp\) 10000658: 24a50780 addiu a1,a1,1920 1000065c: 10000014 b 100006b0 <fn2> 10000660: 00000000 nop -10000664: 8f858020 lw a1,-32736\(gp\) +10000664: 8f85801c lw a1,-32740\(gp\) 10000668: 24a5e93c addiu a1,a1,-5828 1000066c: 1000fe90 b 100000b0 <fn> 10000670: 00000000 nop -10000674: 8f85801c lw a1,-32740\(gp\) +10000674: 8f858018 lw a1,-32744\(gp\) 10000678: 8ca50774 lw a1,1908\(a1\) 1000067c: 1000000c b 100006b0 <fn2> 10000680: 00000000 nop -10000684: 8f85801c lw a1,-32740\(gp\) +10000684: 8f858018 lw a1,-32744\(gp\) 10000688: 8ca50708 lw a1,1800\(a1\) 1000068c: 1000fe88 b 100000b0 <fn> 10000690: 00000000 nop -10000694: 8f81801c lw at,-32740\(gp\) +10000694: 8f818018 lw at,-32744\(gp\) 10000698: 00250821 addu at,at,a1 1000069c: 8c250796 lw a1,1942\(at\) 100006a0: 10000003 b 100006b0 <fn2> @@ -422,13 +423,13 @@ Disassembly of section \.got: 100107b0 <_GLOBAL_OFFSET_TABLE_>: 100107b0: 00000000 .* 100107b4: 80000000 .* -100107b8: 100106fc .* -100107bc: 10010000 .* -100107c0: 10030000 .* -100107c4: 100000b0 .* -100107c8: 10000000 .* -100107cc: 10010774 .* -100107d0: 100006b0 .* -100107d4: 00000000 .* -100107d8: 00000000 .* +100107b8: 10010000 .* +100107bc: 10030000 .* +100107c0: 10000000 .* +100107c4: 00000000 .* +100107c8: 00000000 .* +100107cc: 100006b0 .* +100107d0: 10010774 .* +100107d4: 100000b0 .* +100107d8: 100106fc .* #pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-embed.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-embed.d index 6da691c..bdacf78 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-embed.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-embed.d @@ -1,6 +1,7 @@ #name: MIPS ELF xgot reloc n64 #as: -march=from-abi -EB -64 -KPIC -xgot -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn @@ -21,382 +22,382 @@ Disassembly of section \.text: 00000001200000b0 <fn>: 1200000b0: 3c050000 lui a1,0x0 1200000b4: 00bc282d daddu a1,a1,gp - 1200000b8: dca58020 ld a1,-32736\(a1\) + 1200000b8: dca58060 ld a1,-32672\(a1\) 1200000bc: 3c050000 lui a1,0x0 1200000c0: 00bc282d daddu a1,a1,gp - 1200000c4: dca58020 ld a1,-32736\(a1\) + 1200000c4: dca58060 ld a1,-32672\(a1\) 1200000c8: 64a5000c daddiu a1,a1,12 1200000cc: 3c050000 lui a1,0x0 1200000d0: 00bc282d daddu a1,a1,gp - 1200000d4: dca58020 ld a1,-32736\(a1\) + 1200000d4: dca58060 ld a1,-32672\(a1\) 1200000d8: 3c010001 lui at,0x1 1200000dc: 3421e240 ori at,at,0xe240 1200000e0: 00a1282d daddu a1,a1,at 1200000e4: 3c050000 lui a1,0x0 1200000e8: 00bc282d daddu a1,a1,gp - 1200000ec: dca58020 ld a1,-32736\(a1\) + 1200000ec: dca58060 ld a1,-32672\(a1\) 1200000f0: 00b1282d daddu a1,a1,s1 1200000f4: 3c050000 lui a1,0x0 1200000f8: 00bc282d daddu a1,a1,gp - 1200000fc: dca58020 ld a1,-32736\(a1\) + 1200000fc: dca58060 ld a1,-32672\(a1\) 120000100: 64a5000c daddiu a1,a1,12 120000104: 00b1282d daddu a1,a1,s1 120000108: 3c050000 lui a1,0x0 12000010c: 00bc282d daddu a1,a1,gp - 120000110: dca58020 ld a1,-32736\(a1\) + 120000110: dca58060 ld a1,-32672\(a1\) 120000114: 3c010001 lui at,0x1 120000118: 3421e240 ori at,at,0xe240 12000011c: 00a1282d daddu a1,a1,at 120000120: 00b1282d daddu a1,a1,s1 120000124: 3c050000 lui a1,0x0 120000128: 00bc282d daddu a1,a1,gp - 12000012c: dca58020 ld a1,-32736\(a1\) + 12000012c: dca58060 ld a1,-32672\(a1\) 120000130: dca50000 ld a1,0\(a1\) 120000134: 3c050000 lui a1,0x0 120000138: 00bc282d daddu a1,a1,gp - 12000013c: dca58020 ld a1,-32736\(a1\) + 12000013c: dca58060 ld a1,-32672\(a1\) 120000140: dca5000c ld a1,12\(a1\) 120000144: 3c050000 lui a1,0x0 120000148: 00bc282d daddu a1,a1,gp - 12000014c: dca58020 ld a1,-32736\(a1\) + 12000014c: dca58060 ld a1,-32672\(a1\) 120000150: 00b1282d daddu a1,a1,s1 120000154: dca50000 ld a1,0\(a1\) 120000158: 3c050000 lui a1,0x0 12000015c: 00bc282d daddu a1,a1,gp - 120000160: dca58020 ld a1,-32736\(a1\) + 120000160: dca58060 ld a1,-32672\(a1\) 120000164: 00b1282d daddu a1,a1,s1 120000168: dca5000c ld a1,12\(a1\) 12000016c: 3c010000 lui at,0x0 120000170: 003c082d daddu at,at,gp - 120000174: dc218020 ld at,-32736\(at\) + 120000174: dc218060 ld at,-32672\(at\) 120000178: 0025082d daddu at,at,a1 12000017c: dc250022 ld a1,34\(at\) 120000180: 3c010000 lui at,0x0 120000184: 003c082d daddu at,at,gp - 120000188: dc218020 ld at,-32736\(at\) + 120000188: dc218060 ld at,-32672\(at\) 12000018c: 0025082d daddu at,at,a1 120000190: fc250038 sd a1,56\(at\) 120000194: 3c010000 lui at,0x0 120000198: 003c082d daddu at,at,gp - 12000019c: dc218020 ld at,-32736\(at\) + 12000019c: dc218060 ld at,-32672\(at\) 1200001a0: 88250000 lwl a1,0\(at\) 1200001a4: 98250003 lwr a1,3\(at\) 1200001a8: 3c010000 lui at,0x0 1200001ac: 003c082d daddu at,at,gp - 1200001b0: dc218020 ld at,-32736\(at\) + 1200001b0: dc218060 ld at,-32672\(at\) 1200001b4: 6421000c daddiu at,at,12 1200001b8: 88250000 lwl a1,0\(at\) 1200001bc: 98250003 lwr a1,3\(at\) 1200001c0: 3c010000 lui at,0x0 1200001c4: 003c082d daddu at,at,gp - 1200001c8: dc218020 ld at,-32736\(at\) + 1200001c8: dc218060 ld at,-32672\(at\) 1200001cc: 0031082d daddu at,at,s1 1200001d0: 88250000 lwl a1,0\(at\) 1200001d4: 98250003 lwr a1,3\(at\) 1200001d8: 3c010000 lui at,0x0 1200001dc: 003c082d daddu at,at,gp - 1200001e0: dc218020 ld at,-32736\(at\) + 1200001e0: dc218060 ld at,-32672\(at\) 1200001e4: 6421000c daddiu at,at,12 1200001e8: 0031082d daddu at,at,s1 1200001ec: 88250000 lwl a1,0\(at\) 1200001f0: 98250003 lwr a1,3\(at\) 1200001f4: 3c010000 lui at,0x0 1200001f8: 003c082d daddu at,at,gp - 1200001fc: dc218020 ld at,-32736\(at\) + 1200001fc: dc218060 ld at,-32672\(at\) 120000200: 64210022 daddiu at,at,34 120000204: 0025082d daddu at,at,a1 120000208: 88250000 lwl a1,0\(at\) 12000020c: 98250003 lwr a1,3\(at\) 120000210: 3c010000 lui at,0x0 120000214: 003c082d daddu at,at,gp - 120000218: dc218020 ld at,-32736\(at\) + 120000218: dc218060 ld at,-32672\(at\) 12000021c: 64210038 daddiu at,at,56 120000220: 0025082d daddu at,at,a1 120000224: a8250000 swl a1,0\(at\) 120000228: b8250003 swr a1,3\(at\) - 12000022c: df858028 ld a1,-32728\(gp\) + 12000022c: df858020 ld a1,-32736\(gp\) 120000230: 64a506f4 daddiu a1,a1,1780 - 120000234: df858028 ld a1,-32728\(gp\) + 120000234: df858020 ld a1,-32736\(gp\) 120000238: 64a50700 daddiu a1,a1,1792 - 12000023c: df858030 ld a1,-32720\(gp\) + 12000023c: df858028 ld a1,-32728\(gp\) 120000240: 64a5e934 daddiu a1,a1,-5836 - 120000244: df858028 ld a1,-32728\(gp\) + 120000244: df858020 ld a1,-32736\(gp\) 120000248: 64a506f4 daddiu a1,a1,1780 12000024c: 00b1282d daddu a1,a1,s1 - 120000250: df858028 ld a1,-32728\(gp\) + 120000250: df858020 ld a1,-32736\(gp\) 120000254: 64a50700 daddiu a1,a1,1792 120000258: 00b1282d daddu a1,a1,s1 - 12000025c: df858030 ld a1,-32720\(gp\) + 12000025c: df858028 ld a1,-32728\(gp\) 120000260: 64a5e934 daddiu a1,a1,-5836 120000264: 00b1282d daddu a1,a1,s1 - 120000268: df858028 ld a1,-32728\(gp\) + 120000268: df858020 ld a1,-32736\(gp\) 12000026c: dca506f4 ld a1,1780\(a1\) - 120000270: df858028 ld a1,-32728\(gp\) + 120000270: df858020 ld a1,-32736\(gp\) 120000274: dca50700 ld a1,1792\(a1\) - 120000278: df858028 ld a1,-32728\(gp\) + 120000278: df858020 ld a1,-32736\(gp\) 12000027c: 00b1282d daddu a1,a1,s1 120000280: dca506f4 ld a1,1780\(a1\) - 120000284: df858028 ld a1,-32728\(gp\) + 120000284: df858020 ld a1,-32736\(gp\) 120000288: 00b1282d daddu a1,a1,s1 12000028c: dca50700 ld a1,1792\(a1\) - 120000290: df818028 ld at,-32728\(gp\) + 120000290: df818020 ld at,-32736\(gp\) 120000294: 0025082d daddu at,at,a1 120000298: dc250716 ld a1,1814\(at\) - 12000029c: df818028 ld at,-32728\(gp\) + 12000029c: df818020 ld at,-32736\(gp\) 1200002a0: 0025082d daddu at,at,a1 1200002a4: fc25072c sd a1,1836\(at\) - 1200002a8: df818028 ld at,-32728\(gp\) + 1200002a8: df818020 ld at,-32736\(gp\) 1200002ac: 642106f4 daddiu at,at,1780 1200002b0: 88250000 lwl a1,0\(at\) 1200002b4: 98250003 lwr a1,3\(at\) - 1200002b8: df818028 ld at,-32728\(gp\) + 1200002b8: df818020 ld at,-32736\(gp\) 1200002bc: 64210700 daddiu at,at,1792 1200002c0: 88250000 lwl a1,0\(at\) 1200002c4: 98250003 lwr a1,3\(at\) - 1200002c8: df818028 ld at,-32728\(gp\) + 1200002c8: df818020 ld at,-32736\(gp\) 1200002cc: 642106f4 daddiu at,at,1780 1200002d0: 0031082d daddu at,at,s1 1200002d4: 88250000 lwl a1,0\(at\) 1200002d8: 98250003 lwr a1,3\(at\) - 1200002dc: df818028 ld at,-32728\(gp\) + 1200002dc: df818020 ld at,-32736\(gp\) 1200002e0: 64210700 daddiu at,at,1792 1200002e4: 0031082d daddu at,at,s1 1200002e8: 88250000 lwl a1,0\(at\) 1200002ec: 98250003 lwr a1,3\(at\) - 1200002f0: df818028 ld at,-32728\(gp\) + 1200002f0: df818020 ld at,-32736\(gp\) 1200002f4: 64210716 daddiu at,at,1814 1200002f8: 0025082d daddu at,at,a1 1200002fc: 88250000 lwl a1,0\(at\) 120000300: 98250003 lwr a1,3\(at\) - 120000304: df818028 ld at,-32728\(gp\) + 120000304: df818020 ld at,-32736\(gp\) 120000308: 6421072c daddiu at,at,1836 12000030c: 0025082d daddu at,at,a1 120000310: a8250000 swl a1,0\(at\) 120000314: b8250003 swr a1,3\(at\) 120000318: 3c050000 lui a1,0x0 12000031c: 00bc282d daddu a1,a1,gp - 120000320: dca58038 ld a1,-32712\(a1\) - 120000324: df858040 ld a1,-32704\(gp\) + 120000320: dca58058 ld a1,-32680\(a1\) + 120000324: df858030 ld a1,-32720\(gp\) 120000328: 64a500b0 daddiu a1,a1,176 12000032c: 3c190000 lui t9,0x0 120000330: 033cc82d daddu t9,t9,gp - 120000334: df398038 ld t9,-32712\(t9\) - 120000338: df998040 ld t9,-32704\(gp\) + 120000334: df398058 ld t9,-32680\(t9\) + 120000338: df998030 ld t9,-32720\(gp\) 12000033c: 673900b0 daddiu t9,t9,176 120000340: 3c190000 lui t9,0x0 120000344: 033cc82d daddu t9,t9,gp - 120000348: df398038 ld t9,-32712\(t9\) + 120000348: df398058 ld t9,-32680\(t9\) 12000034c: 0411ff58 bal 1200000b0 <fn> 120000350: 00000000 nop - 120000354: df998040 ld t9,-32704\(gp\) + 120000354: df998030 ld t9,-32720\(gp\) 120000358: 673900b0 daddiu t9,t9,176 12000035c: 0411ff54 bal 1200000b0 <fn> 120000360: 00000000 nop 120000364: 3c050000 lui a1,0x0 120000368: 00bc282d daddu a1,a1,gp - 12000036c: dca58048 ld a1,-32696\(a1\) + 12000036c: dca58050 ld a1,-32688\(a1\) 120000370: 3c050000 lui a1,0x0 120000374: 00bc282d daddu a1,a1,gp - 120000378: dca58048 ld a1,-32696\(a1\) + 120000378: dca58050 ld a1,-32688\(a1\) 12000037c: 64a5000c daddiu a1,a1,12 120000380: 3c050000 lui a1,0x0 120000384: 00bc282d daddu a1,a1,gp - 120000388: dca58048 ld a1,-32696\(a1\) + 120000388: dca58050 ld a1,-32688\(a1\) 12000038c: 3c010001 lui at,0x1 120000390: 3421e240 ori at,at,0xe240 120000394: 00a1282d daddu a1,a1,at 120000398: 3c050000 lui a1,0x0 12000039c: 00bc282d daddu a1,a1,gp - 1200003a0: dca58048 ld a1,-32696\(a1\) + 1200003a0: dca58050 ld a1,-32688\(a1\) 1200003a4: 00b1282d daddu a1,a1,s1 1200003a8: 3c050000 lui a1,0x0 1200003ac: 00bc282d daddu a1,a1,gp - 1200003b0: dca58048 ld a1,-32696\(a1\) + 1200003b0: dca58050 ld a1,-32688\(a1\) 1200003b4: 64a5000c daddiu a1,a1,12 1200003b8: 00b1282d daddu a1,a1,s1 1200003bc: 3c050000 lui a1,0x0 1200003c0: 00bc282d daddu a1,a1,gp - 1200003c4: dca58048 ld a1,-32696\(a1\) + 1200003c4: dca58050 ld a1,-32688\(a1\) 1200003c8: 3c010001 lui at,0x1 1200003cc: 3421e240 ori at,at,0xe240 1200003d0: 00a1282d daddu a1,a1,at 1200003d4: 00b1282d daddu a1,a1,s1 1200003d8: 3c050000 lui a1,0x0 1200003dc: 00bc282d daddu a1,a1,gp - 1200003e0: dca58048 ld a1,-32696\(a1\) + 1200003e0: dca58050 ld a1,-32688\(a1\) 1200003e4: dca50000 ld a1,0\(a1\) 1200003e8: 3c050000 lui a1,0x0 1200003ec: 00bc282d daddu a1,a1,gp - 1200003f0: dca58048 ld a1,-32696\(a1\) + 1200003f0: dca58050 ld a1,-32688\(a1\) 1200003f4: dca5000c ld a1,12\(a1\) 1200003f8: 3c050000 lui a1,0x0 1200003fc: 00bc282d daddu a1,a1,gp - 120000400: dca58048 ld a1,-32696\(a1\) + 120000400: dca58050 ld a1,-32688\(a1\) 120000404: 00b1282d daddu a1,a1,s1 120000408: dca50000 ld a1,0\(a1\) 12000040c: 3c050000 lui a1,0x0 120000410: 00bc282d daddu a1,a1,gp - 120000414: dca58048 ld a1,-32696\(a1\) + 120000414: dca58050 ld a1,-32688\(a1\) 120000418: 00b1282d daddu a1,a1,s1 12000041c: dca5000c ld a1,12\(a1\) 120000420: 3c010000 lui at,0x0 120000424: 003c082d daddu at,at,gp - 120000428: dc218048 ld at,-32696\(at\) + 120000428: dc218050 ld at,-32688\(at\) 12000042c: 0025082d daddu at,at,a1 120000430: dc250022 ld a1,34\(at\) 120000434: 3c010000 lui at,0x0 120000438: 003c082d daddu at,at,gp - 12000043c: dc218048 ld at,-32696\(at\) + 12000043c: dc218050 ld at,-32688\(at\) 120000440: 0025082d daddu at,at,a1 120000444: fc250038 sd a1,56\(at\) 120000448: 3c010000 lui at,0x0 12000044c: 003c082d daddu at,at,gp - 120000450: dc218048 ld at,-32696\(at\) + 120000450: dc218050 ld at,-32688\(at\) 120000454: 88250000 lwl a1,0\(at\) 120000458: 98250003 lwr a1,3\(at\) 12000045c: 3c010000 lui at,0x0 120000460: 003c082d daddu at,at,gp - 120000464: dc218048 ld at,-32696\(at\) + 120000464: dc218050 ld at,-32688\(at\) 120000468: 6421000c daddiu at,at,12 12000046c: 88250000 lwl a1,0\(at\) 120000470: 98250003 lwr a1,3\(at\) 120000474: 3c010000 lui at,0x0 120000478: 003c082d daddu at,at,gp - 12000047c: dc218048 ld at,-32696\(at\) + 12000047c: dc218050 ld at,-32688\(at\) 120000480: 0031082d daddu at,at,s1 120000484: 88250000 lwl a1,0\(at\) 120000488: 98250003 lwr a1,3\(at\) 12000048c: 3c010000 lui at,0x0 120000490: 003c082d daddu at,at,gp - 120000494: dc218048 ld at,-32696\(at\) + 120000494: dc218050 ld at,-32688\(at\) 120000498: 6421000c daddiu at,at,12 12000049c: 0031082d daddu at,at,s1 1200004a0: 88250000 lwl a1,0\(at\) 1200004a4: 98250003 lwr a1,3\(at\) 1200004a8: 3c010000 lui at,0x0 1200004ac: 003c082d daddu at,at,gp - 1200004b0: dc218048 ld at,-32696\(at\) + 1200004b0: dc218050 ld at,-32688\(at\) 1200004b4: 64210022 daddiu at,at,34 1200004b8: 0025082d daddu at,at,a1 1200004bc: 88250000 lwl a1,0\(at\) 1200004c0: 98250003 lwr a1,3\(at\) 1200004c4: 3c010000 lui at,0x0 1200004c8: 003c082d daddu at,at,gp - 1200004cc: dc218048 ld at,-32696\(at\) + 1200004cc: dc218050 ld at,-32688\(at\) 1200004d0: 64210038 daddiu at,at,56 1200004d4: 0025082d daddu at,at,a1 1200004d8: a8250000 swl a1,0\(at\) 1200004dc: b8250003 swr a1,3\(at\) - 1200004e0: df858028 ld a1,-32728\(gp\) + 1200004e0: df858020 ld a1,-32736\(gp\) 1200004e4: 64a5076c daddiu a1,a1,1900 - 1200004e8: df858028 ld a1,-32728\(gp\) + 1200004e8: df858020 ld a1,-32736\(gp\) 1200004ec: 64a50778 daddiu a1,a1,1912 - 1200004f0: df858030 ld a1,-32720\(gp\) + 1200004f0: df858028 ld a1,-32728\(gp\) 1200004f4: 64a5e9ac daddiu a1,a1,-5716 - 1200004f8: df858028 ld a1,-32728\(gp\) + 1200004f8: df858020 ld a1,-32736\(gp\) 1200004fc: 64a5076c daddiu a1,a1,1900 120000500: 00b1282d daddu a1,a1,s1 - 120000504: df858028 ld a1,-32728\(gp\) + 120000504: df858020 ld a1,-32736\(gp\) 120000508: 64a50778 daddiu a1,a1,1912 12000050c: 00b1282d daddu a1,a1,s1 - 120000510: df858030 ld a1,-32720\(gp\) + 120000510: df858028 ld a1,-32728\(gp\) 120000514: 64a5e9ac daddiu a1,a1,-5716 120000518: 00b1282d daddu a1,a1,s1 - 12000051c: df858028 ld a1,-32728\(gp\) + 12000051c: df858020 ld a1,-32736\(gp\) 120000520: dca5076c ld a1,1900\(a1\) - 120000524: df858028 ld a1,-32728\(gp\) + 120000524: df858020 ld a1,-32736\(gp\) 120000528: dca50778 ld a1,1912\(a1\) - 12000052c: df858028 ld a1,-32728\(gp\) + 12000052c: df858020 ld a1,-32736\(gp\) 120000530: 00b1282d daddu a1,a1,s1 120000534: dca5076c ld a1,1900\(a1\) - 120000538: df858028 ld a1,-32728\(gp\) + 120000538: df858020 ld a1,-32736\(gp\) 12000053c: 00b1282d daddu a1,a1,s1 120000540: dca50778 ld a1,1912\(a1\) - 120000544: df818028 ld at,-32728\(gp\) + 120000544: df818020 ld at,-32736\(gp\) 120000548: 0025082d daddu at,at,a1 12000054c: dc25078e ld a1,1934\(at\) - 120000550: df818028 ld at,-32728\(gp\) + 120000550: df818020 ld at,-32736\(gp\) 120000554: 0025082d daddu at,at,a1 120000558: fc2507a4 sd a1,1956\(at\) - 12000055c: df818028 ld at,-32728\(gp\) + 12000055c: df818020 ld at,-32736\(gp\) 120000560: 6421076c daddiu at,at,1900 120000564: 88250000 lwl a1,0\(at\) 120000568: 98250003 lwr a1,3\(at\) - 12000056c: df818028 ld at,-32728\(gp\) + 12000056c: df818020 ld at,-32736\(gp\) 120000570: 64210778 daddiu at,at,1912 120000574: 88250000 lwl a1,0\(at\) 120000578: 98250003 lwr a1,3\(at\) - 12000057c: df818028 ld at,-32728\(gp\) + 12000057c: df818020 ld at,-32736\(gp\) 120000580: 6421076c daddiu at,at,1900 120000584: 0031082d daddu at,at,s1 120000588: 88250000 lwl a1,0\(at\) 12000058c: 98250003 lwr a1,3\(at\) - 120000590: df818028 ld at,-32728\(gp\) + 120000590: df818020 ld at,-32736\(gp\) 120000594: 64210778 daddiu at,at,1912 120000598: 0031082d daddu at,at,s1 12000059c: 88250000 lwl a1,0\(at\) 1200005a0: 98250003 lwr a1,3\(at\) - 1200005a4: df818028 ld at,-32728\(gp\) + 1200005a4: df818020 ld at,-32736\(gp\) 1200005a8: 6421078e daddiu at,at,1934 1200005ac: 0025082d daddu at,at,a1 1200005b0: 88250000 lwl a1,0\(at\) 1200005b4: 98250003 lwr a1,3\(at\) - 1200005b8: df818028 ld at,-32728\(gp\) + 1200005b8: df818020 ld at,-32736\(gp\) 1200005bc: 642107a4 daddiu at,at,1956 1200005c0: 0025082d daddu at,at,a1 1200005c4: a8250000 swl a1,0\(at\) 1200005c8: b8250003 swr a1,3\(at\) 1200005cc: 3c050000 lui a1,0x0 1200005d0: 00bc282d daddu a1,a1,gp - 1200005d4: dca58050 ld a1,-32688\(a1\) - 1200005d8: df858040 ld a1,-32704\(gp\) + 1200005d4: dca58048 ld a1,-32696\(a1\) + 1200005d8: df858030 ld a1,-32720\(gp\) 1200005dc: 64a506b0 daddiu a1,a1,1712 1200005e0: 3c190000 lui t9,0x0 1200005e4: 033cc82d daddu t9,t9,gp - 1200005e8: df398050 ld t9,-32688\(t9\) - 1200005ec: df998040 ld t9,-32704\(gp\) + 1200005e8: df398048 ld t9,-32696\(t9\) + 1200005ec: df998030 ld t9,-32720\(gp\) 1200005f0: 673906b0 daddiu t9,t9,1712 1200005f4: 3c190000 lui t9,0x0 1200005f8: 033cc82d daddu t9,t9,gp - 1200005fc: df398050 ld t9,-32688\(t9\) + 1200005fc: df398048 ld t9,-32696\(t9\) 120000600: 0411002b bal 1200006b0 <fn2> 120000604: 00000000 nop - 120000608: df998040 ld t9,-32704\(gp\) + 120000608: df998030 ld t9,-32720\(gp\) 12000060c: 673906b0 daddiu t9,t9,1712 120000610: 04110027 bal 1200006b0 <fn2> 120000614: 00000000 nop 120000618: 3c050000 lui a1,0x0 12000061c: 00bc282d daddu a1,a1,gp - 120000620: dca58020 ld a1,-32736\(a1\) + 120000620: dca58060 ld a1,-32672\(a1\) 120000624: 1000fea2 b 1200000b0 <fn> 120000628: 00000000 nop 12000062c: 3c050000 lui a1,0x0 120000630: 00bc282d daddu a1,a1,gp - 120000634: dca58048 ld a1,-32696\(a1\) + 120000634: dca58050 ld a1,-32688\(a1\) 120000638: dca50000 ld a1,0\(a1\) 12000063c: 1000001c b 1200006b0 <fn2> 120000640: 00000000 nop - 120000644: df858028 ld a1,-32728\(gp\) + 120000644: df858020 ld a1,-32736\(gp\) 120000648: 64a506f4 daddiu a1,a1,1780 12000064c: 1000fe98 b 1200000b0 <fn> 120000650: 00000000 nop - 120000654: df858028 ld a1,-32728\(gp\) + 120000654: df858020 ld a1,-32736\(gp\) 120000658: 64a50778 daddiu a1,a1,1912 12000065c: 10000014 b 1200006b0 <fn2> 120000660: 00000000 nop - 120000664: df858030 ld a1,-32720\(gp\) + 120000664: df858028 ld a1,-32728\(gp\) 120000668: 64a5e934 daddiu a1,a1,-5836 12000066c: 1000fe90 b 1200000b0 <fn> 120000670: 00000000 nop - 120000674: df858028 ld a1,-32728\(gp\) + 120000674: df858020 ld a1,-32736\(gp\) 120000678: dca5076c ld a1,1900\(a1\) 12000067c: 1000000c b 1200006b0 <fn2> 120000680: 00000000 nop - 120000684: df858028 ld a1,-32728\(gp\) + 120000684: df858020 ld a1,-32736\(gp\) 120000688: dca50700 ld a1,1792\(a1\) 12000068c: 1000fe88 b 1200000b0 <fn> 120000690: 00000000 nop - 120000694: df818028 ld at,-32728\(gp\) + 120000694: df818020 ld at,-32736\(gp\) 120000698: 0025082d daddu at,at,a1 12000069c: dc25078e ld a1,1934\(at\) 1200006a0: 10000003 b 1200006b0 <fn2> @@ -427,18 +428,18 @@ Disassembly of section \.got: 1200107b8: 80000000 .* 1200107bc: 00000000 .* 1200107c0: 00000001 .* - 1200107c4: 200106f4 .* + 1200107c4: 20010000 .* 1200107c8: 00000001 .* - 1200107cc: 20010000 .* + 1200107cc: 20030000 .* 1200107d0: 00000001 .* - 1200107d4: 20030000 .* - 1200107d8: 00000001 .* - 1200107dc: 200000b0 .* - 1200107e0: 00000001 .* - 1200107e4: 20000000 .* + 1200107d4: 20000000 .* + \.\.\. 1200107e8: 00000001 .* - 1200107ec: 2001076c .* + 1200107ec: 200006b0 .* 1200107f0: 00000001 .* - 1200107f4: 200006b0 .* - \.\.\. + 1200107f4: 2001076c .* + 1200107f8: 00000001 .* + 1200107fc: 200000b0 .* + 120010800: 00000001 .* + 120010804: 200106f4 .* #pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d index be446f0..fd21487 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d @@ -1,6 +1,7 @@ #name: MIPS ELF xgot reloc n64 #as: -march=from-abi -EB -64 -KPIC -xgot -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn @@ -21,382 +22,382 @@ Disassembly of section \.text: 00000001200000e0 <fn>: 1200000e0: 3c050000 lui a1,0x0 1200000e4: 00bc282d daddu a1,a1,gp - 1200000e8: dca58020 ld a1,-32736\(a1\) + 1200000e8: dca58060 ld a1,-32672\(a1\) 1200000ec: 3c050000 lui a1,0x0 1200000f0: 00bc282d daddu a1,a1,gp - 1200000f4: dca58020 ld a1,-32736\(a1\) + 1200000f4: dca58060 ld a1,-32672\(a1\) 1200000f8: 64a5000c daddiu a1,a1,12 1200000fc: 3c050000 lui a1,0x0 120000100: 00bc282d daddu a1,a1,gp - 120000104: dca58020 ld a1,-32736\(a1\) + 120000104: dca58060 ld a1,-32672\(a1\) 120000108: 3c010001 lui at,0x1 12000010c: 3421e240 ori at,at,0xe240 120000110: 00a1282d daddu a1,a1,at 120000114: 3c050000 lui a1,0x0 120000118: 00bc282d daddu a1,a1,gp - 12000011c: dca58020 ld a1,-32736\(a1\) + 12000011c: dca58060 ld a1,-32672\(a1\) 120000120: 00b1282d daddu a1,a1,s1 120000124: 3c050000 lui a1,0x0 120000128: 00bc282d daddu a1,a1,gp - 12000012c: dca58020 ld a1,-32736\(a1\) + 12000012c: dca58060 ld a1,-32672\(a1\) 120000130: 64a5000c daddiu a1,a1,12 120000134: 00b1282d daddu a1,a1,s1 120000138: 3c050000 lui a1,0x0 12000013c: 00bc282d daddu a1,a1,gp - 120000140: dca58020 ld a1,-32736\(a1\) + 120000140: dca58060 ld a1,-32672\(a1\) 120000144: 3c010001 lui at,0x1 120000148: 3421e240 ori at,at,0xe240 12000014c: 00a1282d daddu a1,a1,at 120000150: 00b1282d daddu a1,a1,s1 120000154: 3c050000 lui a1,0x0 120000158: 00bc282d daddu a1,a1,gp - 12000015c: dca58020 ld a1,-32736\(a1\) + 12000015c: dca58060 ld a1,-32672\(a1\) 120000160: dca50000 ld a1,0\(a1\) 120000164: 3c050000 lui a1,0x0 120000168: 00bc282d daddu a1,a1,gp - 12000016c: dca58020 ld a1,-32736\(a1\) + 12000016c: dca58060 ld a1,-32672\(a1\) 120000170: dca5000c ld a1,12\(a1\) 120000174: 3c050000 lui a1,0x0 120000178: 00bc282d daddu a1,a1,gp - 12000017c: dca58020 ld a1,-32736\(a1\) + 12000017c: dca58060 ld a1,-32672\(a1\) 120000180: 00b1282d daddu a1,a1,s1 120000184: dca50000 ld a1,0\(a1\) 120000188: 3c050000 lui a1,0x0 12000018c: 00bc282d daddu a1,a1,gp - 120000190: dca58020 ld a1,-32736\(a1\) + 120000190: dca58060 ld a1,-32672\(a1\) 120000194: 00b1282d daddu a1,a1,s1 120000198: dca5000c ld a1,12\(a1\) 12000019c: 3c010000 lui at,0x0 1200001a0: 003c082d daddu at,at,gp - 1200001a4: dc218020 ld at,-32736\(at\) + 1200001a4: dc218060 ld at,-32672\(at\) 1200001a8: 0025082d daddu at,at,a1 1200001ac: dc250022 ld a1,34\(at\) 1200001b0: 3c010000 lui at,0x0 1200001b4: 003c082d daddu at,at,gp - 1200001b8: dc218020 ld at,-32736\(at\) + 1200001b8: dc218060 ld at,-32672\(at\) 1200001bc: 0025082d daddu at,at,a1 1200001c0: fc250038 sd a1,56\(at\) 1200001c4: 3c010000 lui at,0x0 1200001c8: 003c082d daddu at,at,gp - 1200001cc: dc218020 ld at,-32736\(at\) + 1200001cc: dc218060 ld at,-32672\(at\) 1200001d0: 88250000 lwl a1,0\(at\) 1200001d4: 98250003 lwr a1,3\(at\) 1200001d8: 3c010000 lui at,0x0 1200001dc: 003c082d daddu at,at,gp - 1200001e0: dc218020 ld at,-32736\(at\) + 1200001e0: dc218060 ld at,-32672\(at\) 1200001e4: 6421000c daddiu at,at,12 1200001e8: 88250000 lwl a1,0\(at\) 1200001ec: 98250003 lwr a1,3\(at\) 1200001f0: 3c010000 lui at,0x0 1200001f4: 003c082d daddu at,at,gp - 1200001f8: dc218020 ld at,-32736\(at\) + 1200001f8: dc218060 ld at,-32672\(at\) 1200001fc: 0031082d daddu at,at,s1 120000200: 88250000 lwl a1,0\(at\) 120000204: 98250003 lwr a1,3\(at\) 120000208: 3c010000 lui at,0x0 12000020c: 003c082d daddu at,at,gp - 120000210: dc218020 ld at,-32736\(at\) + 120000210: dc218060 ld at,-32672\(at\) 120000214: 6421000c daddiu at,at,12 120000218: 0031082d daddu at,at,s1 12000021c: 88250000 lwl a1,0\(at\) 120000220: 98250003 lwr a1,3\(at\) 120000224: 3c010000 lui at,0x0 120000228: 003c082d daddu at,at,gp - 12000022c: dc218020 ld at,-32736\(at\) + 12000022c: dc218060 ld at,-32672\(at\) 120000230: 64210022 daddiu at,at,34 120000234: 0025082d daddu at,at,a1 120000238: 88250000 lwl a1,0\(at\) 12000023c: 98250003 lwr a1,3\(at\) 120000240: 3c010000 lui at,0x0 120000244: 003c082d daddu at,at,gp - 120000248: dc218020 ld at,-32736\(at\) + 120000248: dc218060 ld at,-32672\(at\) 12000024c: 64210038 daddiu at,at,56 120000250: 0025082d daddu at,at,a1 120000254: a8250000 swl a1,0\(at\) 120000258: b8250003 swr a1,3\(at\) - 12000025c: df858028 ld a1,-32728\(gp\) + 12000025c: df858020 ld a1,-32736\(gp\) 120000260: 64a5072c daddiu a1,a1,1836 - 120000264: df858028 ld a1,-32728\(gp\) + 120000264: df858020 ld a1,-32736\(gp\) 120000268: 64a50738 daddiu a1,a1,1848 - 12000026c: df858030 ld a1,-32720\(gp\) + 12000026c: df858028 ld a1,-32728\(gp\) 120000270: 64a5e96c daddiu a1,a1,-5780 - 120000274: df858028 ld a1,-32728\(gp\) + 120000274: df858020 ld a1,-32736\(gp\) 120000278: 64a5072c daddiu a1,a1,1836 12000027c: 00b1282d daddu a1,a1,s1 - 120000280: df858028 ld a1,-32728\(gp\) + 120000280: df858020 ld a1,-32736\(gp\) 120000284: 64a50738 daddiu a1,a1,1848 120000288: 00b1282d daddu a1,a1,s1 - 12000028c: df858030 ld a1,-32720\(gp\) + 12000028c: df858028 ld a1,-32728\(gp\) 120000290: 64a5e96c daddiu a1,a1,-5780 120000294: 00b1282d daddu a1,a1,s1 - 120000298: df858028 ld a1,-32728\(gp\) + 120000298: df858020 ld a1,-32736\(gp\) 12000029c: dca5072c ld a1,1836\(a1\) - 1200002a0: df858028 ld a1,-32728\(gp\) + 1200002a0: df858020 ld a1,-32736\(gp\) 1200002a4: dca50738 ld a1,1848\(a1\) - 1200002a8: df858028 ld a1,-32728\(gp\) + 1200002a8: df858020 ld a1,-32736\(gp\) 1200002ac: 00b1282d daddu a1,a1,s1 1200002b0: dca5072c ld a1,1836\(a1\) - 1200002b4: df858028 ld a1,-32728\(gp\) + 1200002b4: df858020 ld a1,-32736\(gp\) 1200002b8: 00b1282d daddu a1,a1,s1 1200002bc: dca50738 ld a1,1848\(a1\) - 1200002c0: df818028 ld at,-32728\(gp\) + 1200002c0: df818020 ld at,-32736\(gp\) 1200002c4: 0025082d daddu at,at,a1 1200002c8: dc25074e ld a1,1870\(at\) - 1200002cc: df818028 ld at,-32728\(gp\) + 1200002cc: df818020 ld at,-32736\(gp\) 1200002d0: 0025082d daddu at,at,a1 1200002d4: fc250764 sd a1,1892\(at\) - 1200002d8: df818028 ld at,-32728\(gp\) + 1200002d8: df818020 ld at,-32736\(gp\) 1200002dc: 6421072c daddiu at,at,1836 1200002e0: 88250000 lwl a1,0\(at\) 1200002e4: 98250003 lwr a1,3\(at\) - 1200002e8: df818028 ld at,-32728\(gp\) + 1200002e8: df818020 ld at,-32736\(gp\) 1200002ec: 64210738 daddiu at,at,1848 1200002f0: 88250000 lwl a1,0\(at\) 1200002f4: 98250003 lwr a1,3\(at\) - 1200002f8: df818028 ld at,-32728\(gp\) + 1200002f8: df818020 ld at,-32736\(gp\) 1200002fc: 6421072c daddiu at,at,1836 120000300: 0031082d daddu at,at,s1 120000304: 88250000 lwl a1,0\(at\) 120000308: 98250003 lwr a1,3\(at\) - 12000030c: df818028 ld at,-32728\(gp\) + 12000030c: df818020 ld at,-32736\(gp\) 120000310: 64210738 daddiu at,at,1848 120000314: 0031082d daddu at,at,s1 120000318: 88250000 lwl a1,0\(at\) 12000031c: 98250003 lwr a1,3\(at\) - 120000320: df818028 ld at,-32728\(gp\) + 120000320: df818020 ld at,-32736\(gp\) 120000324: 6421074e daddiu at,at,1870 120000328: 0025082d daddu at,at,a1 12000032c: 88250000 lwl a1,0\(at\) 120000330: 98250003 lwr a1,3\(at\) - 120000334: df818028 ld at,-32728\(gp\) + 120000334: df818020 ld at,-32736\(gp\) 120000338: 64210764 daddiu at,at,1892 12000033c: 0025082d daddu at,at,a1 120000340: a8250000 swl a1,0\(at\) 120000344: b8250003 swr a1,3\(at\) 120000348: 3c050000 lui a1,0x0 12000034c: 00bc282d daddu a1,a1,gp - 120000350: dca58038 ld a1,-32712\(a1\) - 120000354: df858040 ld a1,-32704\(gp\) + 120000350: dca58058 ld a1,-32680\(a1\) + 120000354: df858030 ld a1,-32720\(gp\) 120000358: 64a500e0 daddiu a1,a1,224 12000035c: 3c190000 lui t9,0x0 120000360: 033cc82d daddu t9,t9,gp - 120000364: df398038 ld t9,-32712\(t9\) - 120000368: df998040 ld t9,-32704\(gp\) + 120000364: df398058 ld t9,-32680\(t9\) + 120000368: df998030 ld t9,-32720\(gp\) 12000036c: 673900e0 daddiu t9,t9,224 120000370: 3c190000 lui t9,0x0 120000374: 033cc82d daddu t9,t9,gp - 120000378: df398038 ld t9,-32712\(t9\) + 120000378: df398058 ld t9,-32680\(t9\) 12000037c: 0411ff58 bal 1200000e0 <fn> 120000380: 00000000 nop - 120000384: df998040 ld t9,-32704\(gp\) + 120000384: df998030 ld t9,-32720\(gp\) 120000388: 673900e0 daddiu t9,t9,224 12000038c: 0411ff54 bal 1200000e0 <fn> 120000390: 00000000 nop 120000394: 3c050000 lui a1,0x0 120000398: 00bc282d daddu a1,a1,gp - 12000039c: dca58048 ld a1,-32696\(a1\) + 12000039c: dca58050 ld a1,-32688\(a1\) 1200003a0: 3c050000 lui a1,0x0 1200003a4: 00bc282d daddu a1,a1,gp - 1200003a8: dca58048 ld a1,-32696\(a1\) + 1200003a8: dca58050 ld a1,-32688\(a1\) 1200003ac: 64a5000c daddiu a1,a1,12 1200003b0: 3c050000 lui a1,0x0 1200003b4: 00bc282d daddu a1,a1,gp - 1200003b8: dca58048 ld a1,-32696\(a1\) + 1200003b8: dca58050 ld a1,-32688\(a1\) 1200003bc: 3c010001 lui at,0x1 1200003c0: 3421e240 ori at,at,0xe240 1200003c4: 00a1282d daddu a1,a1,at 1200003c8: 3c050000 lui a1,0x0 1200003cc: 00bc282d daddu a1,a1,gp - 1200003d0: dca58048 ld a1,-32696\(a1\) + 1200003d0: dca58050 ld a1,-32688\(a1\) 1200003d4: 00b1282d daddu a1,a1,s1 1200003d8: 3c050000 lui a1,0x0 1200003dc: 00bc282d daddu a1,a1,gp - 1200003e0: dca58048 ld a1,-32696\(a1\) + 1200003e0: dca58050 ld a1,-32688\(a1\) 1200003e4: 64a5000c daddiu a1,a1,12 1200003e8: 00b1282d daddu a1,a1,s1 1200003ec: 3c050000 lui a1,0x0 1200003f0: 00bc282d daddu a1,a1,gp - 1200003f4: dca58048 ld a1,-32696\(a1\) + 1200003f4: dca58050 ld a1,-32688\(a1\) 1200003f8: 3c010001 lui at,0x1 1200003fc: 3421e240 ori at,at,0xe240 120000400: 00a1282d daddu a1,a1,at 120000404: 00b1282d daddu a1,a1,s1 120000408: 3c050000 lui a1,0x0 12000040c: 00bc282d daddu a1,a1,gp - 120000410: dca58048 ld a1,-32696\(a1\) + 120000410: dca58050 ld a1,-32688\(a1\) 120000414: dca50000 ld a1,0\(a1\) 120000418: 3c050000 lui a1,0x0 12000041c: 00bc282d daddu a1,a1,gp - 120000420: dca58048 ld a1,-32696\(a1\) + 120000420: dca58050 ld a1,-32688\(a1\) 120000424: dca5000c ld a1,12\(a1\) 120000428: 3c050000 lui a1,0x0 12000042c: 00bc282d daddu a1,a1,gp - 120000430: dca58048 ld a1,-32696\(a1\) + 120000430: dca58050 ld a1,-32688\(a1\) 120000434: 00b1282d daddu a1,a1,s1 120000438: dca50000 ld a1,0\(a1\) 12000043c: 3c050000 lui a1,0x0 120000440: 00bc282d daddu a1,a1,gp - 120000444: dca58048 ld a1,-32696\(a1\) + 120000444: dca58050 ld a1,-32688\(a1\) 120000448: 00b1282d daddu a1,a1,s1 12000044c: dca5000c ld a1,12\(a1\) 120000450: 3c010000 lui at,0x0 120000454: 003c082d daddu at,at,gp - 120000458: dc218048 ld at,-32696\(at\) + 120000458: dc218050 ld at,-32688\(at\) 12000045c: 0025082d daddu at,at,a1 120000460: dc250022 ld a1,34\(at\) 120000464: 3c010000 lui at,0x0 120000468: 003c082d daddu at,at,gp - 12000046c: dc218048 ld at,-32696\(at\) + 12000046c: dc218050 ld at,-32688\(at\) 120000470: 0025082d daddu at,at,a1 120000474: fc250038 sd a1,56\(at\) 120000478: 3c010000 lui at,0x0 12000047c: 003c082d daddu at,at,gp - 120000480: dc218048 ld at,-32696\(at\) + 120000480: dc218050 ld at,-32688\(at\) 120000484: 88250000 lwl a1,0\(at\) 120000488: 98250003 lwr a1,3\(at\) 12000048c: 3c010000 lui at,0x0 120000490: 003c082d daddu at,at,gp - 120000494: dc218048 ld at,-32696\(at\) + 120000494: dc218050 ld at,-32688\(at\) 120000498: 6421000c daddiu at,at,12 12000049c: 88250000 lwl a1,0\(at\) 1200004a0: 98250003 lwr a1,3\(at\) 1200004a4: 3c010000 lui at,0x0 1200004a8: 003c082d daddu at,at,gp - 1200004ac: dc218048 ld at,-32696\(at\) + 1200004ac: dc218050 ld at,-32688\(at\) 1200004b0: 0031082d daddu at,at,s1 1200004b4: 88250000 lwl a1,0\(at\) 1200004b8: 98250003 lwr a1,3\(at\) 1200004bc: 3c010000 lui at,0x0 1200004c0: 003c082d daddu at,at,gp - 1200004c4: dc218048 ld at,-32696\(at\) + 1200004c4: dc218050 ld at,-32688\(at\) 1200004c8: 6421000c daddiu at,at,12 1200004cc: 0031082d daddu at,at,s1 1200004d0: 88250000 lwl a1,0\(at\) 1200004d4: 98250003 lwr a1,3\(at\) 1200004d8: 3c010000 lui at,0x0 1200004dc: 003c082d daddu at,at,gp - 1200004e0: dc218048 ld at,-32696\(at\) + 1200004e0: dc218050 ld at,-32688\(at\) 1200004e4: 64210022 daddiu at,at,34 1200004e8: 0025082d daddu at,at,a1 1200004ec: 88250000 lwl a1,0\(at\) 1200004f0: 98250003 lwr a1,3\(at\) 1200004f4: 3c010000 lui at,0x0 1200004f8: 003c082d daddu at,at,gp - 1200004fc: dc218048 ld at,-32696\(at\) + 1200004fc: dc218050 ld at,-32688\(at\) 120000500: 64210038 daddiu at,at,56 120000504: 0025082d daddu at,at,a1 120000508: a8250000 swl a1,0\(at\) 12000050c: b8250003 swr a1,3\(at\) - 120000510: df858028 ld a1,-32728\(gp\) + 120000510: df858020 ld a1,-32736\(gp\) 120000514: 64a507a4 daddiu a1,a1,1956 - 120000518: df858028 ld a1,-32728\(gp\) + 120000518: df858020 ld a1,-32736\(gp\) 12000051c: 64a507b0 daddiu a1,a1,1968 - 120000520: df858030 ld a1,-32720\(gp\) + 120000520: df858028 ld a1,-32728\(gp\) 120000524: 64a5e9e4 daddiu a1,a1,-5660 - 120000528: df858028 ld a1,-32728\(gp\) + 120000528: df858020 ld a1,-32736\(gp\) 12000052c: 64a507a4 daddiu a1,a1,1956 120000530: 00b1282d daddu a1,a1,s1 - 120000534: df858028 ld a1,-32728\(gp\) + 120000534: df858020 ld a1,-32736\(gp\) 120000538: 64a507b0 daddiu a1,a1,1968 12000053c: 00b1282d daddu a1,a1,s1 - 120000540: df858030 ld a1,-32720\(gp\) + 120000540: df858028 ld a1,-32728\(gp\) 120000544: 64a5e9e4 daddiu a1,a1,-5660 120000548: 00b1282d daddu a1,a1,s1 - 12000054c: df858028 ld a1,-32728\(gp\) + 12000054c: df858020 ld a1,-32736\(gp\) 120000550: dca507a4 ld a1,1956\(a1\) - 120000554: df858028 ld a1,-32728\(gp\) + 120000554: df858020 ld a1,-32736\(gp\) 120000558: dca507b0 ld a1,1968\(a1\) - 12000055c: df858028 ld a1,-32728\(gp\) + 12000055c: df858020 ld a1,-32736\(gp\) 120000560: 00b1282d daddu a1,a1,s1 120000564: dca507a4 ld a1,1956\(a1\) - 120000568: df858028 ld a1,-32728\(gp\) + 120000568: df858020 ld a1,-32736\(gp\) 12000056c: 00b1282d daddu a1,a1,s1 120000570: dca507b0 ld a1,1968\(a1\) - 120000574: df818028 ld at,-32728\(gp\) + 120000574: df818020 ld at,-32736\(gp\) 120000578: 0025082d daddu at,at,a1 12000057c: dc2507c6 ld a1,1990\(at\) - 120000580: df818028 ld at,-32728\(gp\) + 120000580: df818020 ld at,-32736\(gp\) 120000584: 0025082d daddu at,at,a1 120000588: fc2507dc sd a1,2012\(at\) - 12000058c: df818028 ld at,-32728\(gp\) + 12000058c: df818020 ld at,-32736\(gp\) 120000590: 642107a4 daddiu at,at,1956 120000594: 88250000 lwl a1,0\(at\) 120000598: 98250003 lwr a1,3\(at\) - 12000059c: df818028 ld at,-32728\(gp\) + 12000059c: df818020 ld at,-32736\(gp\) 1200005a0: 642107b0 daddiu at,at,1968 1200005a4: 88250000 lwl a1,0\(at\) 1200005a8: 98250003 lwr a1,3\(at\) - 1200005ac: df818028 ld at,-32728\(gp\) + 1200005ac: df818020 ld at,-32736\(gp\) 1200005b0: 642107a4 daddiu at,at,1956 1200005b4: 0031082d daddu at,at,s1 1200005b8: 88250000 lwl a1,0\(at\) 1200005bc: 98250003 lwr a1,3\(at\) - 1200005c0: df818028 ld at,-32728\(gp\) + 1200005c0: df818020 ld at,-32736\(gp\) 1200005c4: 642107b0 daddiu at,at,1968 1200005c8: 0031082d daddu at,at,s1 1200005cc: 88250000 lwl a1,0\(at\) 1200005d0: 98250003 lwr a1,3\(at\) - 1200005d4: df818028 ld at,-32728\(gp\) + 1200005d4: df818020 ld at,-32736\(gp\) 1200005d8: 642107c6 daddiu at,at,1990 1200005dc: 0025082d daddu at,at,a1 1200005e0: 88250000 lwl a1,0\(at\) 1200005e4: 98250003 lwr a1,3\(at\) - 1200005e8: df818028 ld at,-32728\(gp\) + 1200005e8: df818020 ld at,-32736\(gp\) 1200005ec: 642107dc daddiu at,at,2012 1200005f0: 0025082d daddu at,at,a1 1200005f4: a8250000 swl a1,0\(at\) 1200005f8: b8250003 swr a1,3\(at\) 1200005fc: 3c050000 lui a1,0x0 120000600: 00bc282d daddu a1,a1,gp - 120000604: dca58050 ld a1,-32688\(a1\) - 120000608: df858040 ld a1,-32704\(gp\) + 120000604: dca58048 ld a1,-32696\(a1\) + 120000608: df858030 ld a1,-32720\(gp\) 12000060c: 64a506e0 daddiu a1,a1,1760 120000610: 3c190000 lui t9,0x0 120000614: 033cc82d daddu t9,t9,gp - 120000618: df398050 ld t9,-32688\(t9\) - 12000061c: df998040 ld t9,-32704\(gp\) + 120000618: df398048 ld t9,-32696\(t9\) + 12000061c: df998030 ld t9,-32720\(gp\) 120000620: 673906e0 daddiu t9,t9,1760 120000624: 3c190000 lui t9,0x0 120000628: 033cc82d daddu t9,t9,gp - 12000062c: df398050 ld t9,-32688\(t9\) + 12000062c: df398048 ld t9,-32696\(t9\) 120000630: 0411002b bal 1200006e0 <fn2> 120000634: 00000000 nop - 120000638: df998040 ld t9,-32704\(gp\) + 120000638: df998030 ld t9,-32720\(gp\) 12000063c: 673906e0 daddiu t9,t9,1760 120000640: 04110027 bal 1200006e0 <fn2> 120000644: 00000000 nop 120000648: 3c050000 lui a1,0x0 12000064c: 00bc282d daddu a1,a1,gp - 120000650: dca58020 ld a1,-32736\(a1\) + 120000650: dca58060 ld a1,-32672\(a1\) 120000654: 1000fea2 b 1200000e0 <fn> 120000658: 00000000 nop 12000065c: 3c050000 lui a1,0x0 120000660: 00bc282d daddu a1,a1,gp - 120000664: dca58048 ld a1,-32696\(a1\) + 120000664: dca58050 ld a1,-32688\(a1\) 120000668: dca50000 ld a1,0\(a1\) 12000066c: 1000001c b 1200006e0 <fn2> 120000670: 00000000 nop - 120000674: df858028 ld a1,-32728\(gp\) + 120000674: df858020 ld a1,-32736\(gp\) 120000678: 64a5072c daddiu a1,a1,1836 12000067c: 1000fe98 b 1200000e0 <fn> 120000680: 00000000 nop - 120000684: df858028 ld a1,-32728\(gp\) + 120000684: df858020 ld a1,-32736\(gp\) 120000688: 64a507b0 daddiu a1,a1,1968 12000068c: 10000014 b 1200006e0 <fn2> 120000690: 00000000 nop - 120000694: df858030 ld a1,-32720\(gp\) + 120000694: df858028 ld a1,-32728\(gp\) 120000698: 64a5e96c daddiu a1,a1,-5780 12000069c: 1000fe90 b 1200000e0 <fn> 1200006a0: 00000000 nop - 1200006a4: df858028 ld a1,-32728\(gp\) + 1200006a4: df858020 ld a1,-32736\(gp\) 1200006a8: dca507a4 ld a1,1956\(a1\) 1200006ac: 1000000c b 1200006e0 <fn2> 1200006b0: 00000000 nop - 1200006b4: df858028 ld a1,-32728\(gp\) + 1200006b4: df858020 ld a1,-32736\(gp\) 1200006b8: dca50738 ld a1,1848\(a1\) 1200006bc: 1000fe88 b 1200000e0 <fn> 1200006c0: 00000000 nop - 1200006c4: df818028 ld at,-32728\(gp\) + 1200006c4: df818020 ld at,-32736\(gp\) 1200006c8: 0025082d daddu at,at,a1 1200006cc: dc2507c6 ld a1,1990\(at\) 1200006d0: 10000003 b 1200006e0 <fn2> @@ -427,18 +428,18 @@ Disassembly of section \.got: 1200107e8: 80000000 .* 1200107ec: 00000000 .* 1200107f0: 00000001 .* - 1200107f4: 2001072c .* + 1200107f4: 20010000 .* 1200107f8: 00000001 .* - 1200107fc: 20010000 .* + 1200107fc: 20030000 .* 120010800: 00000001 .* - 120010804: 20030000 .* - 120010808: 00000001 .* - 12001080c: 200000e0 .* - 120010810: 00000001 .* - 120010814: 20000000 .* + 120010804: 20000000 .* + \.\.\. 120010818: 00000001 .* - 12001081c: 200107a4 .* + 12001081c: 200006e0 .* 120010820: 00000001 .* - 120010824: 200006e0 .* - \.\.\. + 120010824: 200107a4 .* + 120010828: 00000001 .* + 12001082c: 200000e0 .* + 120010830: 00000001 .* + 120010834: 2001072c .* #pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d index 6a9ea40..348b718 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d @@ -1,6 +1,7 @@ #name: MIPS ELF xgot reloc n64 #as: -march=from-abi -EB -64 -KPIC -xgot -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn @@ -19,382 +20,382 @@ Disassembly of section \.text: 0000000010000110 <fn>: 10000110: 3c050000 lui a1,0x0 10000114: 00bc282d daddu a1,a1,gp - 10000118: dca58020 ld a1,-32736\(a1\) + 10000118: dca58060 ld a1,-32672\(a1\) 1000011c: 3c050000 lui a1,0x0 10000120: 00bc282d daddu a1,a1,gp - 10000124: dca58020 ld a1,-32736\(a1\) + 10000124: dca58060 ld a1,-32672\(a1\) 10000128: 64a5000c daddiu a1,a1,12 1000012c: 3c050000 lui a1,0x0 10000130: 00bc282d daddu a1,a1,gp - 10000134: dca58020 ld a1,-32736\(a1\) + 10000134: dca58060 ld a1,-32672\(a1\) 10000138: 3c010001 lui at,0x1 1000013c: 3421e240 ori at,at,0xe240 10000140: 00a1282d daddu a1,a1,at 10000144: 3c050000 lui a1,0x0 10000148: 00bc282d daddu a1,a1,gp - 1000014c: dca58020 ld a1,-32736\(a1\) + 1000014c: dca58060 ld a1,-32672\(a1\) 10000150: 00b1282d daddu a1,a1,s1 10000154: 3c050000 lui a1,0x0 10000158: 00bc282d daddu a1,a1,gp - 1000015c: dca58020 ld a1,-32736\(a1\) + 1000015c: dca58060 ld a1,-32672\(a1\) 10000160: 64a5000c daddiu a1,a1,12 10000164: 00b1282d daddu a1,a1,s1 10000168: 3c050000 lui a1,0x0 1000016c: 00bc282d daddu a1,a1,gp - 10000170: dca58020 ld a1,-32736\(a1\) + 10000170: dca58060 ld a1,-32672\(a1\) 10000174: 3c010001 lui at,0x1 10000178: 3421e240 ori at,at,0xe240 1000017c: 00a1282d daddu a1,a1,at 10000180: 00b1282d daddu a1,a1,s1 10000184: 3c050000 lui a1,0x0 10000188: 00bc282d daddu a1,a1,gp - 1000018c: dca58020 ld a1,-32736\(a1\) + 1000018c: dca58060 ld a1,-32672\(a1\) 10000190: dca50000 ld a1,0\(a1\) 10000194: 3c050000 lui a1,0x0 10000198: 00bc282d daddu a1,a1,gp - 1000019c: dca58020 ld a1,-32736\(a1\) + 1000019c: dca58060 ld a1,-32672\(a1\) 100001a0: dca5000c ld a1,12\(a1\) 100001a4: 3c050000 lui a1,0x0 100001a8: 00bc282d daddu a1,a1,gp - 100001ac: dca58020 ld a1,-32736\(a1\) + 100001ac: dca58060 ld a1,-32672\(a1\) 100001b0: 00b1282d daddu a1,a1,s1 100001b4: dca50000 ld a1,0\(a1\) 100001b8: 3c050000 lui a1,0x0 100001bc: 00bc282d daddu a1,a1,gp - 100001c0: dca58020 ld a1,-32736\(a1\) + 100001c0: dca58060 ld a1,-32672\(a1\) 100001c4: 00b1282d daddu a1,a1,s1 100001c8: dca5000c ld a1,12\(a1\) 100001cc: 3c010000 lui at,0x0 100001d0: 003c082d daddu at,at,gp - 100001d4: dc218020 ld at,-32736\(at\) + 100001d4: dc218060 ld at,-32672\(at\) 100001d8: 0025082d daddu at,at,a1 100001dc: dc250022 ld a1,34\(at\) 100001e0: 3c010000 lui at,0x0 100001e4: 003c082d daddu at,at,gp - 100001e8: dc218020 ld at,-32736\(at\) + 100001e8: dc218060 ld at,-32672\(at\) 100001ec: 0025082d daddu at,at,a1 100001f0: fc250038 sd a1,56\(at\) 100001f4: 3c010000 lui at,0x0 100001f8: 003c082d daddu at,at,gp - 100001fc: dc218020 ld at,-32736\(at\) + 100001fc: dc218060 ld at,-32672\(at\) 10000200: 88250000 lwl a1,0\(at\) 10000204: 98250003 lwr a1,3\(at\) 10000208: 3c010000 lui at,0x0 1000020c: 003c082d daddu at,at,gp - 10000210: dc218020 ld at,-32736\(at\) + 10000210: dc218060 ld at,-32672\(at\) 10000214: 6421000c daddiu at,at,12 10000218: 88250000 lwl a1,0\(at\) 1000021c: 98250003 lwr a1,3\(at\) 10000220: 3c010000 lui at,0x0 10000224: 003c082d daddu at,at,gp - 10000228: dc218020 ld at,-32736\(at\) + 10000228: dc218060 ld at,-32672\(at\) 1000022c: 0031082d daddu at,at,s1 10000230: 88250000 lwl a1,0\(at\) 10000234: 98250003 lwr a1,3\(at\) 10000238: 3c010000 lui at,0x0 1000023c: 003c082d daddu at,at,gp - 10000240: dc218020 ld at,-32736\(at\) + 10000240: dc218060 ld at,-32672\(at\) 10000244: 6421000c daddiu at,at,12 10000248: 0031082d daddu at,at,s1 1000024c: 88250000 lwl a1,0\(at\) 10000250: 98250003 lwr a1,3\(at\) 10000254: 3c010000 lui at,0x0 10000258: 003c082d daddu at,at,gp - 1000025c: dc218020 ld at,-32736\(at\) + 1000025c: dc218060 ld at,-32672\(at\) 10000260: 64210022 daddiu at,at,34 10000264: 0025082d daddu at,at,a1 10000268: 88250000 lwl a1,0\(at\) 1000026c: 98250003 lwr a1,3\(at\) 10000270: 3c010000 lui at,0x0 10000274: 003c082d daddu at,at,gp - 10000278: dc218020 ld at,-32736\(at\) + 10000278: dc218060 ld at,-32672\(at\) 1000027c: 64210038 daddiu at,at,56 10000280: 0025082d daddu at,at,a1 10000284: a8250000 swl a1,0\(at\) 10000288: b8250003 swr a1,3\(at\) - 1000028c: df858028 ld a1,-32728\(gp\) + 1000028c: df858020 ld a1,-32736\(gp\) 10000290: 64a5075c daddiu a1,a1,1884 - 10000294: df858028 ld a1,-32728\(gp\) + 10000294: df858020 ld a1,-32736\(gp\) 10000298: 64a50768 daddiu a1,a1,1896 - 1000029c: df858030 ld a1,-32720\(gp\) + 1000029c: df858028 ld a1,-32728\(gp\) 100002a0: 64a5e99c daddiu a1,a1,-5732 - 100002a4: df858028 ld a1,-32728\(gp\) + 100002a4: df858020 ld a1,-32736\(gp\) 100002a8: 64a5075c daddiu a1,a1,1884 100002ac: 00b1282d daddu a1,a1,s1 - 100002b0: df858028 ld a1,-32728\(gp\) + 100002b0: df858020 ld a1,-32736\(gp\) 100002b4: 64a50768 daddiu a1,a1,1896 100002b8: 00b1282d daddu a1,a1,s1 - 100002bc: df858030 ld a1,-32720\(gp\) + 100002bc: df858028 ld a1,-32728\(gp\) 100002c0: 64a5e99c daddiu a1,a1,-5732 100002c4: 00b1282d daddu a1,a1,s1 - 100002c8: df858028 ld a1,-32728\(gp\) + 100002c8: df858020 ld a1,-32736\(gp\) 100002cc: dca5075c ld a1,1884\(a1\) - 100002d0: df858028 ld a1,-32728\(gp\) + 100002d0: df858020 ld a1,-32736\(gp\) 100002d4: dca50768 ld a1,1896\(a1\) - 100002d8: df858028 ld a1,-32728\(gp\) + 100002d8: df858020 ld a1,-32736\(gp\) 100002dc: 00b1282d daddu a1,a1,s1 100002e0: dca5075c ld a1,1884\(a1\) - 100002e4: df858028 ld a1,-32728\(gp\) + 100002e4: df858020 ld a1,-32736\(gp\) 100002e8: 00b1282d daddu a1,a1,s1 100002ec: dca50768 ld a1,1896\(a1\) - 100002f0: df818028 ld at,-32728\(gp\) + 100002f0: df818020 ld at,-32736\(gp\) 100002f4: 0025082d daddu at,at,a1 100002f8: dc25077e ld a1,1918\(at\) - 100002fc: df818028 ld at,-32728\(gp\) + 100002fc: df818020 ld at,-32736\(gp\) 10000300: 0025082d daddu at,at,a1 10000304: fc250794 sd a1,1940\(at\) - 10000308: df818028 ld at,-32728\(gp\) + 10000308: df818020 ld at,-32736\(gp\) 1000030c: 6421075c daddiu at,at,1884 10000310: 88250000 lwl a1,0\(at\) 10000314: 98250003 lwr a1,3\(at\) - 10000318: df818028 ld at,-32728\(gp\) + 10000318: df818020 ld at,-32736\(gp\) 1000031c: 64210768 daddiu at,at,1896 10000320: 88250000 lwl a1,0\(at\) 10000324: 98250003 lwr a1,3\(at\) - 10000328: df818028 ld at,-32728\(gp\) + 10000328: df818020 ld at,-32736\(gp\) 1000032c: 6421075c daddiu at,at,1884 10000330: 0031082d daddu at,at,s1 10000334: 88250000 lwl a1,0\(at\) 10000338: 98250003 lwr a1,3\(at\) - 1000033c: df818028 ld at,-32728\(gp\) + 1000033c: df818020 ld at,-32736\(gp\) 10000340: 64210768 daddiu at,at,1896 10000344: 0031082d daddu at,at,s1 10000348: 88250000 lwl a1,0\(at\) 1000034c: 98250003 lwr a1,3\(at\) - 10000350: df818028 ld at,-32728\(gp\) + 10000350: df818020 ld at,-32736\(gp\) 10000354: 6421077e daddiu at,at,1918 10000358: 0025082d daddu at,at,a1 1000035c: 88250000 lwl a1,0\(at\) 10000360: 98250003 lwr a1,3\(at\) - 10000364: df818028 ld at,-32728\(gp\) + 10000364: df818020 ld at,-32736\(gp\) 10000368: 64210794 daddiu at,at,1940 1000036c: 0025082d daddu at,at,a1 10000370: a8250000 swl a1,0\(at\) 10000374: b8250003 swr a1,3\(at\) 10000378: 3c050000 lui a1,0x0 1000037c: 00bc282d daddu a1,a1,gp - 10000380: dca58038 ld a1,-32712\(a1\) - 10000384: df858040 ld a1,-32704\(gp\) + 10000380: dca58058 ld a1,-32680\(a1\) + 10000384: df858030 ld a1,-32720\(gp\) 10000388: 64a50110 daddiu a1,a1,272 1000038c: 3c190000 lui t9,0x0 10000390: 033cc82d daddu t9,t9,gp - 10000394: df398038 ld t9,-32712\(t9\) - 10000398: df998040 ld t9,-32704\(gp\) + 10000394: df398058 ld t9,-32680\(t9\) + 10000398: df998030 ld t9,-32720\(gp\) 1000039c: 67390110 daddiu t9,t9,272 100003a0: 3c190000 lui t9,0x0 100003a4: 033cc82d daddu t9,t9,gp - 100003a8: df398038 ld t9,-32712\(t9\) + 100003a8: df398058 ld t9,-32680\(t9\) 100003ac: 0411ff58 bal 10000110 <fn> 100003b0: 00000000 nop - 100003b4: df998040 ld t9,-32704\(gp\) + 100003b4: df998030 ld t9,-32720\(gp\) 100003b8: 67390110 daddiu t9,t9,272 100003bc: 0411ff54 bal 10000110 <fn> 100003c0: 00000000 nop 100003c4: 3c050000 lui a1,0x0 100003c8: 00bc282d daddu a1,a1,gp - 100003cc: dca58048 ld a1,-32696\(a1\) + 100003cc: dca58050 ld a1,-32688\(a1\) 100003d0: 3c050000 lui a1,0x0 100003d4: 00bc282d daddu a1,a1,gp - 100003d8: dca58048 ld a1,-32696\(a1\) + 100003d8: dca58050 ld a1,-32688\(a1\) 100003dc: 64a5000c daddiu a1,a1,12 100003e0: 3c050000 lui a1,0x0 100003e4: 00bc282d daddu a1,a1,gp - 100003e8: dca58048 ld a1,-32696\(a1\) + 100003e8: dca58050 ld a1,-32688\(a1\) 100003ec: 3c010001 lui at,0x1 100003f0: 3421e240 ori at,at,0xe240 100003f4: 00a1282d daddu a1,a1,at 100003f8: 3c050000 lui a1,0x0 100003fc: 00bc282d daddu a1,a1,gp - 10000400: dca58048 ld a1,-32696\(a1\) + 10000400: dca58050 ld a1,-32688\(a1\) 10000404: 00b1282d daddu a1,a1,s1 10000408: 3c050000 lui a1,0x0 1000040c: 00bc282d daddu a1,a1,gp - 10000410: dca58048 ld a1,-32696\(a1\) + 10000410: dca58050 ld a1,-32688\(a1\) 10000414: 64a5000c daddiu a1,a1,12 10000418: 00b1282d daddu a1,a1,s1 1000041c: 3c050000 lui a1,0x0 10000420: 00bc282d daddu a1,a1,gp - 10000424: dca58048 ld a1,-32696\(a1\) + 10000424: dca58050 ld a1,-32688\(a1\) 10000428: 3c010001 lui at,0x1 1000042c: 3421e240 ori at,at,0xe240 10000430: 00a1282d daddu a1,a1,at 10000434: 00b1282d daddu a1,a1,s1 10000438: 3c050000 lui a1,0x0 1000043c: 00bc282d daddu a1,a1,gp - 10000440: dca58048 ld a1,-32696\(a1\) + 10000440: dca58050 ld a1,-32688\(a1\) 10000444: dca50000 ld a1,0\(a1\) 10000448: 3c050000 lui a1,0x0 1000044c: 00bc282d daddu a1,a1,gp - 10000450: dca58048 ld a1,-32696\(a1\) + 10000450: dca58050 ld a1,-32688\(a1\) 10000454: dca5000c ld a1,12\(a1\) 10000458: 3c050000 lui a1,0x0 1000045c: 00bc282d daddu a1,a1,gp - 10000460: dca58048 ld a1,-32696\(a1\) + 10000460: dca58050 ld a1,-32688\(a1\) 10000464: 00b1282d daddu a1,a1,s1 10000468: dca50000 ld a1,0\(a1\) 1000046c: 3c050000 lui a1,0x0 10000470: 00bc282d daddu a1,a1,gp - 10000474: dca58048 ld a1,-32696\(a1\) + 10000474: dca58050 ld a1,-32688\(a1\) 10000478: 00b1282d daddu a1,a1,s1 1000047c: dca5000c ld a1,12\(a1\) 10000480: 3c010000 lui at,0x0 10000484: 003c082d daddu at,at,gp - 10000488: dc218048 ld at,-32696\(at\) + 10000488: dc218050 ld at,-32688\(at\) 1000048c: 0025082d daddu at,at,a1 10000490: dc250022 ld a1,34\(at\) 10000494: 3c010000 lui at,0x0 10000498: 003c082d daddu at,at,gp - 1000049c: dc218048 ld at,-32696\(at\) + 1000049c: dc218050 ld at,-32688\(at\) 100004a0: 0025082d daddu at,at,a1 100004a4: fc250038 sd a1,56\(at\) 100004a8: 3c010000 lui at,0x0 100004ac: 003c082d daddu at,at,gp - 100004b0: dc218048 ld at,-32696\(at\) + 100004b0: dc218050 ld at,-32688\(at\) 100004b4: 88250000 lwl a1,0\(at\) 100004b8: 98250003 lwr a1,3\(at\) 100004bc: 3c010000 lui at,0x0 100004c0: 003c082d daddu at,at,gp - 100004c4: dc218048 ld at,-32696\(at\) + 100004c4: dc218050 ld at,-32688\(at\) 100004c8: 6421000c daddiu at,at,12 100004cc: 88250000 lwl a1,0\(at\) 100004d0: 98250003 lwr a1,3\(at\) 100004d4: 3c010000 lui at,0x0 100004d8: 003c082d daddu at,at,gp - 100004dc: dc218048 ld at,-32696\(at\) + 100004dc: dc218050 ld at,-32688\(at\) 100004e0: 0031082d daddu at,at,s1 100004e4: 88250000 lwl a1,0\(at\) 100004e8: 98250003 lwr a1,3\(at\) 100004ec: 3c010000 lui at,0x0 100004f0: 003c082d daddu at,at,gp - 100004f4: dc218048 ld at,-32696\(at\) + 100004f4: dc218050 ld at,-32688\(at\) 100004f8: 6421000c daddiu at,at,12 100004fc: 0031082d daddu at,at,s1 10000500: 88250000 lwl a1,0\(at\) 10000504: 98250003 lwr a1,3\(at\) 10000508: 3c010000 lui at,0x0 1000050c: 003c082d daddu at,at,gp - 10000510: dc218048 ld at,-32696\(at\) + 10000510: dc218050 ld at,-32688\(at\) 10000514: 64210022 daddiu at,at,34 10000518: 0025082d daddu at,at,a1 1000051c: 88250000 lwl a1,0\(at\) 10000520: 98250003 lwr a1,3\(at\) 10000524: 3c010000 lui at,0x0 10000528: 003c082d daddu at,at,gp - 1000052c: dc218048 ld at,-32696\(at\) + 1000052c: dc218050 ld at,-32688\(at\) 10000530: 64210038 daddiu at,at,56 10000534: 0025082d daddu at,at,a1 10000538: a8250000 swl a1,0\(at\) 1000053c: b8250003 swr a1,3\(at\) - 10000540: df858028 ld a1,-32728\(gp\) + 10000540: df858020 ld a1,-32736\(gp\) 10000544: 64a507d4 daddiu a1,a1,2004 - 10000548: df858028 ld a1,-32728\(gp\) + 10000548: df858020 ld a1,-32736\(gp\) 1000054c: 64a507e0 daddiu a1,a1,2016 - 10000550: df858030 ld a1,-32720\(gp\) + 10000550: df858028 ld a1,-32728\(gp\) 10000554: 64a5ea14 daddiu a1,a1,-5612 - 10000558: df858028 ld a1,-32728\(gp\) + 10000558: df858020 ld a1,-32736\(gp\) 1000055c: 64a507d4 daddiu a1,a1,2004 10000560: 00b1282d daddu a1,a1,s1 - 10000564: df858028 ld a1,-32728\(gp\) + 10000564: df858020 ld a1,-32736\(gp\) 10000568: 64a507e0 daddiu a1,a1,2016 1000056c: 00b1282d daddu a1,a1,s1 - 10000570: df858030 ld a1,-32720\(gp\) + 10000570: df858028 ld a1,-32728\(gp\) 10000574: 64a5ea14 daddiu a1,a1,-5612 10000578: 00b1282d daddu a1,a1,s1 - 1000057c: df858028 ld a1,-32728\(gp\) + 1000057c: df858020 ld a1,-32736\(gp\) 10000580: dca507d4 ld a1,2004\(a1\) - 10000584: df858028 ld a1,-32728\(gp\) + 10000584: df858020 ld a1,-32736\(gp\) 10000588: dca507e0 ld a1,2016\(a1\) - 1000058c: df858028 ld a1,-32728\(gp\) + 1000058c: df858020 ld a1,-32736\(gp\) 10000590: 00b1282d daddu a1,a1,s1 10000594: dca507d4 ld a1,2004\(a1\) - 10000598: df858028 ld a1,-32728\(gp\) + 10000598: df858020 ld a1,-32736\(gp\) 1000059c: 00b1282d daddu a1,a1,s1 100005a0: dca507e0 ld a1,2016\(a1\) - 100005a4: df818028 ld at,-32728\(gp\) + 100005a4: df818020 ld at,-32736\(gp\) 100005a8: 0025082d daddu at,at,a1 100005ac: dc2507f6 ld a1,2038\(at\) - 100005b0: df818028 ld at,-32728\(gp\) + 100005b0: df818020 ld at,-32736\(gp\) 100005b4: 0025082d daddu at,at,a1 100005b8: fc25080c sd a1,2060\(at\) - 100005bc: df818028 ld at,-32728\(gp\) + 100005bc: df818020 ld at,-32736\(gp\) 100005c0: 642107d4 daddiu at,at,2004 100005c4: 88250000 lwl a1,0\(at\) 100005c8: 98250003 lwr a1,3\(at\) - 100005cc: df818028 ld at,-32728\(gp\) + 100005cc: df818020 ld at,-32736\(gp\) 100005d0: 642107e0 daddiu at,at,2016 100005d4: 88250000 lwl a1,0\(at\) 100005d8: 98250003 lwr a1,3\(at\) - 100005dc: df818028 ld at,-32728\(gp\) + 100005dc: df818020 ld at,-32736\(gp\) 100005e0: 642107d4 daddiu at,at,2004 100005e4: 0031082d daddu at,at,s1 100005e8: 88250000 lwl a1,0\(at\) 100005ec: 98250003 lwr a1,3\(at\) - 100005f0: df818028 ld at,-32728\(gp\) + 100005f0: df818020 ld at,-32736\(gp\) 100005f4: 642107e0 daddiu at,at,2016 100005f8: 0031082d daddu at,at,s1 100005fc: 88250000 lwl a1,0\(at\) 10000600: 98250003 lwr a1,3\(at\) - 10000604: df818028 ld at,-32728\(gp\) + 10000604: df818020 ld at,-32736\(gp\) 10000608: 642107f6 daddiu at,at,2038 1000060c: 0025082d daddu at,at,a1 10000610: 88250000 lwl a1,0\(at\) 10000614: 98250003 lwr a1,3\(at\) - 10000618: df818028 ld at,-32728\(gp\) + 10000618: df818020 ld at,-32736\(gp\) 1000061c: 6421080c daddiu at,at,2060 10000620: 0025082d daddu at,at,a1 10000624: a8250000 swl a1,0\(at\) 10000628: b8250003 swr a1,3\(at\) 1000062c: 3c050000 lui a1,0x0 10000630: 00bc282d daddu a1,a1,gp - 10000634: dca58050 ld a1,-32688\(a1\) - 10000638: df858040 ld a1,-32704\(gp\) + 10000634: dca58048 ld a1,-32696\(a1\) + 10000638: df858030 ld a1,-32720\(gp\) 1000063c: 64a50710 daddiu a1,a1,1808 10000640: 3c190000 lui t9,0x0 10000644: 033cc82d daddu t9,t9,gp - 10000648: df398050 ld t9,-32688\(t9\) - 1000064c: df998040 ld t9,-32704\(gp\) + 10000648: df398048 ld t9,-32696\(t9\) + 1000064c: df998030 ld t9,-32720\(gp\) 10000650: 67390710 daddiu t9,t9,1808 10000654: 3c190000 lui t9,0x0 10000658: 033cc82d daddu t9,t9,gp - 1000065c: df398050 ld t9,-32688\(t9\) + 1000065c: df398048 ld t9,-32696\(t9\) 10000660: 0411002b bal 10000710 <fn2> 10000664: 00000000 nop - 10000668: df998040 ld t9,-32704\(gp\) + 10000668: df998030 ld t9,-32720\(gp\) 1000066c: 67390710 daddiu t9,t9,1808 10000670: 04110027 bal 10000710 <fn2> 10000674: 00000000 nop 10000678: 3c050000 lui a1,0x0 1000067c: 00bc282d daddu a1,a1,gp - 10000680: dca58020 ld a1,-32736\(a1\) + 10000680: dca58060 ld a1,-32672\(a1\) 10000684: 1000fea2 b 10000110 <fn> 10000688: 00000000 nop 1000068c: 3c050000 lui a1,0x0 10000690: 00bc282d daddu a1,a1,gp - 10000694: dca58048 ld a1,-32696\(a1\) + 10000694: dca58050 ld a1,-32688\(a1\) 10000698: dca50000 ld a1,0\(a1\) 1000069c: 1000001c b 10000710 <fn2> 100006a0: 00000000 nop - 100006a4: df858028 ld a1,-32728\(gp\) + 100006a4: df858020 ld a1,-32736\(gp\) 100006a8: 64a5075c daddiu a1,a1,1884 100006ac: 1000fe98 b 10000110 <fn> 100006b0: 00000000 nop - 100006b4: df858028 ld a1,-32728\(gp\) + 100006b4: df858020 ld a1,-32736\(gp\) 100006b8: 64a507e0 daddiu a1,a1,2016 100006bc: 10000014 b 10000710 <fn2> 100006c0: 00000000 nop - 100006c4: df858030 ld a1,-32720\(gp\) + 100006c4: df858028 ld a1,-32728\(gp\) 100006c8: 64a5e99c daddiu a1,a1,-5732 100006cc: 1000fe90 b 10000110 <fn> 100006d0: 00000000 nop - 100006d4: df858028 ld a1,-32728\(gp\) + 100006d4: df858020 ld a1,-32736\(gp\) 100006d8: dca507d4 ld a1,2004\(a1\) 100006dc: 1000000c b 10000710 <fn2> 100006e0: 00000000 nop - 100006e4: df858028 ld a1,-32728\(gp\) + 100006e4: df858020 ld a1,-32736\(gp\) 100006e8: dca50768 ld a1,1896\(a1\) 100006ec: 1000fe88 b 10000110 <fn> 100006f0: 00000000 nop - 100006f4: df818028 ld at,-32728\(gp\) + 100006f4: df818020 ld at,-32736\(gp\) 100006f8: 0025082d daddu at,at,a1 100006fc: dc2507f6 ld a1,2038\(at\) 10000700: 10000003 b 10000710 <fn2> @@ -422,18 +423,17 @@ Disassembly of section \.got: \.\.\. 10010818: 80000000 .* \.\.\. - 10010824: 1001075c .* + 10010824: 10010000 .* 10010828: 00000000 .* - 1001082c: 10010000 .* + 1001082c: 10030000 .* 10010830: 00000000 .* - 10010834: 10030000 .* + 10010834: 10000000 .* 10010838: 00000000 .* - 1001083c: 10000110 .* - 10010840: 00000000 .* - 10010844: 10000000 .* - 10010848: 00000000 .* - 1001084c: 100107d4 .* + \.\.\. + 1001084c: 10000710 .* 10010850: 00000000 .* - 10010854: 10000710 .* + 10010854: 100107d4 .* 10010858: 00000000 .* - \.\.\. + 1001085c: 10000110 .* + 10010860: 00000000 .* + 10010864: 1001075c .* diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/got-dump-1.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/got-dump-1.ld index ba228f5..e8a40f1 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/got-dump-1.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/got-dump-1.ld @@ -16,4 +16,6 @@ SECTIONS .data : { *(.data) } HIDDEN (_gp = ALIGN (16) + 0x7ff0); .got : { *(.got) } + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/got-dump-2.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/got-dump-2.ld index 0e237de..d7ba691 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/got-dump-2.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/got-dump-2.ld @@ -15,4 +15,6 @@ SECTIONS .data : { *(.data) } HIDDEN (_gp = ALIGN (16) + 0x7ff0); .got : { *(.got) } + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/got-page-1.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/got-page-1.ld index 3197c9b..cfe7c1f 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/got-page-1.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/got-page-1.ld @@ -22,7 +22,7 @@ SECTIONS . = ALIGN (0x400); .bss : { *(.bss .bss.*) } - /DISCARD/ : { *(.reginfo) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } } VERSION diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/jalx-2.dd b/binutils-2.24/ld/testsuite/ld-mips-elf/jalx-2.dd index 50ebdb8..69985f6 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/jalx-2.dd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/jalx-2.dd @@ -28,7 +28,7 @@ Disassembly of section \.text: 4400034: f89e 0020 sw a0,32\(s8\) 4400038: f8be 0024 sw a1,36\(s8\) 440003c: 41a2 0440 lui v0,0x440 - 4400040: 3082 0260 addiu a0,v0,608 + 4400040: 3082 0280 addiu a0,v0,640 4400044: f620 004c jal 4400098 <printf@micromipsplt> 4400048: 0000 0000 nop 440004c: f620 0010 jal 4400020 <internal_function> diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/mips-dyn.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/mips-dyn.ld index e4f90d2..c59cc0f 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/mips-dyn.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/mips-dyn.ld @@ -219,5 +219,5 @@ SECTIONS .debug_varnames 0 : { *(.debug_varnames) } .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } - /DISCARD/ : { *(.note.GNU-stack) } + /DISCARD/ : { *(.note.GNU-stack) *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/mips-elf.exp b/binutils-2.24/ld/testsuite/ld-mips-elf/mips-elf.exp index 827181b..b715898 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/mips-elf.exp +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/mips-elf.exp @@ -55,7 +55,9 @@ if {![istarget mips*-*-*] || ![is_elf_format]} { set has_newabi [expr [istarget *-*-irix6*] \ || [istarget mips*-*-linux*] \ - || [istarget mips*-sde-elf*]] + || [istarget mips*-sde-elf*] \ + || [istarget mips*-mti-elf*] \ + || [istarget mips*-img-elf*]] set linux_gnu [expr [istarget mips*-*-linux*]] set embedded_elf [expr [istarget mips*-*-elf]] @@ -78,7 +80,8 @@ if { [istarget *-*-irix6*] } { set abi_asflags(o32) "-32 -EB" set abi_ldflags(o32) -melf32btsmip_fbsd } -if { [istarget mips*-*-linux*] || [istarget mips*-sde-elf*] } { +if { [istarget mips*-*-linux*] || [istarget mips*-sde-elf*] + || [istarget mips*-mti-elf*] || [istarget mips*-img-elf*]} { set abi_ldflags(n32) -melf32btsmipn32 set abi_ldflags(n64) -melf64btsmip } elseif { [istarget mips64*-*freebsd*] } { @@ -633,37 +636,47 @@ run_ld_link_tests $mips16_intermix_test run_dump_test "mips16-local-stubs-1" -run_dump_test "attr-gnu-4-00" -run_dump_test "attr-gnu-4-01" -run_dump_test "attr-gnu-4-02" -run_dump_test "attr-gnu-4-03" -run_dump_test "attr-gnu-4-04" -run_dump_test "attr-gnu-4-05" -run_dump_test "attr-gnu-4-10" -run_dump_test "attr-gnu-4-11" -run_dump_test "attr-gnu-4-12" -run_dump_test "attr-gnu-4-13" -run_dump_test "attr-gnu-4-14" -run_dump_test "attr-gnu-4-15" -run_dump_test "attr-gnu-4-20" -run_dump_test "attr-gnu-4-21" -run_dump_test "attr-gnu-4-22" -run_dump_test "attr-gnu-4-23" -run_dump_test "attr-gnu-4-24" -run_dump_test "attr-gnu-4-25" -run_dump_test "attr-gnu-4-30" -run_dump_test "attr-gnu-4-31" -run_dump_test "attr-gnu-4-32" -run_dump_test "attr-gnu-4-33" -run_dump_test "attr-gnu-4-34" -run_dump_test "attr-gnu-4-35" -run_dump_test "attr-gnu-4-40" -run_dump_test "attr-gnu-4-41" -run_dump_test "attr-gnu-4-42" -run_dump_test "attr-gnu-4-43" -run_dump_test "attr-gnu-4-44" -run_dump_test "attr-gnu-4-45" -run_dump_test "attr-gnu-4-51" +foreach firstfpabi [list 0 1 2 3 4 5 6] { + foreach secondfpabi [list 0 1 2 3 4 5 6 7] { + run_dump_test "attr-gnu-4-${firstfpabi}${secondfpabi}" + } +} +run_dump_test "attr-gnu-4-71" + +run_dump_test "attr-gnu-8-00" +run_dump_test "attr-gnu-8-01" +run_dump_test "attr-gnu-8-02" +run_dump_test "attr-gnu-8-10" +run_dump_test "attr-gnu-8-11" +run_dump_test "attr-gnu-8-12" +run_dump_test "attr-gnu-8-20" +run_dump_test "attr-gnu-8-21" +run_dump_test "attr-gnu-8-22" + +run_dump_test "attr-gnu-4-0-ph" +run_dump_test "attr-gnu-4-1-ph" +run_dump_test "attr-gnu-4-2-ph" +run_dump_test "attr-gnu-4-3-ph" +run_dump_test "attr-gnu-4-4-ph" +run_dump_test "attr-gnu-4-5-ph" +run_dump_test "attr-gnu-4-6-ph" +run_dump_test "attr-gnu-4-0-n32-ph" +run_dump_test "attr-gnu-4-1-n32-ph" +run_dump_test "attr-gnu-4-2-n32-ph" +run_dump_test "attr-gnu-4-3-n32-ph" +run_dump_test "attr-gnu-4-0-n64-ph" +run_dump_test "attr-gnu-4-1-n64-ph" +run_dump_test "attr-gnu-4-2-n64-ph" +run_dump_test "attr-gnu-4-3-n64-ph" + +run_dump_test "abiflags-strip1-ph" +run_dump_test "abiflags-strip2-ph" +run_dump_test "abiflags-strip3-ph" +run_dump_test "abiflags-strip4-ph" +run_dump_test "abiflags-strip5-ph" +run_dump_test "abiflags-strip6-ph" +run_dump_test "abiflags-strip7-ph" +run_dump_test "abiflags-strip8-ph" run_dump_test "nan-legacy" run_dump_test "nan-2008" @@ -751,3 +764,89 @@ foreach { abi } $abis { [list "objdump -d jalr3.dd"] \ "jalr3-${abi}"]] } + +run_dump_test "attr-gnu-8-00" +run_dump_test "attr-gnu-8-01" +run_dump_test "attr-gnu-8-02" +run_dump_test "attr-gnu-8-10" +run_dump_test "attr-gnu-8-11" +run_dump_test "attr-gnu-8-12" +run_dump_test "attr-gnu-8-20" +run_dump_test "attr-gnu-8-21" +run_dump_test "attr-gnu-8-22" + +proc build_mips_plt_lib { abi } { + global abi_asflags + global abi_ldflags + + run_ld_link_tests [list \ + [list "Shared $abi library for compressed PLT tests" \ + "-shared $abi_ldflags($abi)" "" \ + "$abi_asflags($abi)" \ + { compressed-plt-1-dyn.s } \ + {} \ + "compressed-plt-1-${abi}-dyn.so"]] +} + +proc run_mips_plt_test { name abi filter micromips suffix {extra {}} } { + global abi_asflags + global abi_ldflags + + set as_flags "$abi_asflags($abi) --defsym filter=$filter" + append as_flags " --defsym micromips=$micromips --defsym $abi=1" + if {[string equal $abi o32]} { + append as_flags " -march=mips2" + } + set ld_flags "$abi_ldflags($abi) -T compressed-plt-1.ld" + set dynobj "tmpdir/compressed-plt-1-${abi}-dyn.so" + set files [list] + if { $filter & 3 } { + lappend files compressed-plt-1a.s + } + if { $filter & 12 } { + lappend files compressed-plt-1b.s + } + if { $filter & 16 } { + lappend files compressed-plt-1c.s + } + eval [list lappend files] $extra + set readelf_flags "-A --syms --relocs -d" + if { [string match "*word*" $suffix] } { + append readelf_flags " -x.data" + } + set objdump_flags "-d -Mgpr-names=numeric" + set basename "compressed-plt-1-${abi}-${suffix}" + run_ld_link_tests [list \ + [list "$name" $ld_flags $dynobj \ + "$as_flags" $files \ + [list [list readelf $readelf_flags ${basename}.rd] \ + [list objdump $objdump_flags ${basename}.od]] \ + $basename]] +} + +if { $linux_gnu } { + build_mips_plt_lib o32 + run_mips_plt_test "o32 PLTs for standard encoding" o32 28 0 se + run_mips_plt_test "o32 PLTs for MIPS16 encoding" o32 19 0 mips16-only + run_mips_plt_test "o32 PLTs for microMIPS encoding" o32 19 1 umips-only + run_mips_plt_test "o32 PLTs for mixed MIPS and MIPS16" \ + o32 -1 0 mips16 + run_mips_plt_test "o32 PLTs for mixed MIPS and MIPS16 with %got" \ + o32 -1 0 mips16-got compressed-plt-1d.s + run_mips_plt_test "o32 PLTs for mixed MIPS and MIPS16 with .word" \ + o32 -1 0 mips16-word compressed-plt-1e.s + run_mips_plt_test "o32 PLTs for mixed MIPS and microMIPS" \ + o32 -1 1 umips + run_mips_plt_test "o32 PLTs for mixed MIPS and microMIPS with %got" \ + o32 -1 1 umips-got compressed-plt-1d.s + run_mips_plt_test "o32 PLTs for mixed MIPS and microMIPS with .word" \ + o32 -1 1 umips-word compressed-plt-1e.s + + if $has_newabi { + build_mips_plt_lib n32 + run_mips_plt_test "n32 PLTs for mixed MIPS and MIPS16" \ + n32 -1 0 mips16 + run_mips_plt_test "n32 PLTs for mixed MIPS and microMIPS" \ + n32 -1 1 umips + } +} diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/mips-lib.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/mips-lib.ld index 5073d9f..8e75c77 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/mips-lib.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/mips-lib.ld @@ -214,5 +214,5 @@ SECTIONS .debug_varnames 0 : { *(.debug_varnames) } .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } - /DISCARD/ : { *(.note.GNU-stack) } + /DISCARD/ : { *(.note.GNU-stack) *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-1.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-1.gd index b8d8b34..cca758e 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-1.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-1.gd @@ -1,4 +1,21 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: .* +ASEs: + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + Primary GOT: Canonical gp value: 00057ff0 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-2.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-2.gd index c291bc8..269ae38 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-2.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-2.gd @@ -1,4 +1,21 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: .* +ASEs: + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + Primary GOT: Canonical gp value: 00057ff0 @@ -16,8 +33,8 @@ Primary GOT: Global entries: Address Access Initial Sym\.Val\. Type Ndx Name - 00050018 -32728\(gp\) 00040574 00040574 FUNC 6 used6 - 0005001c -32724\(gp\) 00040598 00040598 FUNC 6 used7 - 00050020 -32720\(gp\) 00040550 00040550 FUNC 6 used5 - 00050024 -32716\(gp\) 0004052c 0004052c FUNC 6 used4 + 00050018 -32728\(gp\) 00040574 00040574 FUNC 7 used6 + 0005001c -32724\(gp\) 00040598 00040598 FUNC 7 used7 + 00050020 -32720\(gp\) 00040550 00040550 FUNC 7 used5 + 00050024 -32716\(gp\) 0004052c 0004052c FUNC 7 used4 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-3.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-3.gd index 9297fe6..141c4e6 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-3.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-3.gd @@ -1,4 +1,21 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: .* +ASEs: + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + Primary GOT: Canonical gp value: 00057ff0 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-4a.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-4a.gd index 1ab835e..55c8e1c 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-4a.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-4a.gd @@ -1,4 +1,21 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: .* +ASEs: + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + Primary GOT: Canonical gp value: 00057ff0 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/multi-got-no-shared.d b/binutils-2.24/ld/testsuite/ld-mips-elf/multi-got-no-shared.d index 25af107..a3e1bb2 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/multi-got-no-shared.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/multi-got-no-shared.d @@ -8,11 +8,11 @@ .*: +file format.* Disassembly of section \.text: -004000b0 <[^>]*> 3c1c0043 lui gp,0x43 -004000b4 <[^>]*> 279c9ff0 addiu gp,gp,-24592 -004000b8 <[^>]*> afbc0008 sw gp,8\(sp\) +004000f0 <[^>]*> 3c1c0043 lui gp,0x43 +004000f4 <[^>]*> 279c9ff0 addiu gp,gp,-24592 +004000f8 <[^>]*> afbc0008 sw gp,8\(sp\) #... -00408d60 <[^>]*> 3c1c0043 lui gp,0x43 -00408d64 <[^>]*> 279c2c98 addiu gp,gp,11416 -00408d68 <[^>]*> afbc0008 sw gp,8\(sp\) +00408da0 <[^>]*> 3c1c0043 lui gp,0x43 +00408da4 <[^>]*> 279c2c98 addiu gp,gp,11416 +00408da8 <[^>]*> afbc0008 sw gp,8\(sp\) #pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/nan-2008.d b/binutils-2.24/ld/testsuite/ld-mips-elf/nan-2008.d index aa20049..30ea837 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/nan-2008.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/nan-2008.d @@ -5,3 +5,4 @@ .*:.*file format.*mips.* private flags = [0-9a-f]*[4-7c-f]..: .*[[,]nan2008[],].* +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/nan-legacy.d b/binutils-2.24/ld/testsuite/ld-mips-elf/nan-legacy.d index 081abcf..8dacc06 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/nan-legacy.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/nan-legacy.d @@ -4,5 +4,5 @@ #objdump: -p .*:.*file format.*mips.* -#failif -private flags = [0-9a-f]*[4-7c-f]..: .*[[]nan2008[]].* +!private flags = [0-9a-f]*[4-7c-f]..: .*[[]nan2008[]].* +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.gd index aa9579b..b0f7b1e 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.gd @@ -1,4 +1,8 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Primary GOT: Canonical gp value: 000183f0 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.ld index 81d0d8a..f2db79a 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.ld @@ -20,4 +20,6 @@ SECTIONS . = ALIGN (0x400); HIDDEN (_gp = . + 0x7ff0); .got : { *(.got) } + + /DISCARD/ : { *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd index 58b50c3..b178bdf 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd @@ -8,7 +8,7 @@ Program Headers: * REGINFO * [^ ]+ * 0x0+00000 * 0x0+00000 [^ ]+ * [^ ]+ * R * 0x.* * LOAD * [^ ]+ * 0x0+00000 * 0x0+00000 [^ ]+ * [^ ]+ * R E * 0x.* * LOAD * [^ ]+ * 0x0+10000 * 0x0+10000 [^ ]+ * [^ ]+ * RW * 0x.* - * DYNAMIC * [^ ]+ * 0x0+00400 * 0x0+00400 .* + * DYNAMIC * [^ ]+ * 0x0+00400 * 0x0+00400 [^ ]+ * [^ ]+ * R * 0x.* * NULL * .* *Section to Segment mapping: diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.gd index 6d3d677..e96e87f 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.gd @@ -1,4 +1,8 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Primary GOT: Canonical gp value: 000a7ff0 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ld index 693bbdd..ab64ea6 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ld @@ -32,4 +32,6 @@ SECTIONS . = 0xa1000; .data : { *(.data) } + + /DISCARD/ : { *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ld index bae9fd8..102c851 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ld @@ -30,4 +30,6 @@ SECTIONS . = 0xa2000; .bss : { *(.dynbss) } + + /DISCARD/ : { *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.gd index 6919a69..6d46b4f 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.gd @@ -1,4 +1,8 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Primary GOT: Canonical gp value: 000a7ff0 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ld index b3ae77d..b76ceff 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ld @@ -35,4 +35,6 @@ SECTIONS . = 0xa2000; .bss : { *(.dynbss) } + + /DISCARD/ : { *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.ad b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.ad index fab5581..5df3c6c 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.ad +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.ad @@ -16,10 +16,10 @@ Dynamic section at offset .* contains .*: 0x70000001 \(MIPS_RLD_VERSION\) * 1 0x70000005 \(MIPS_FLAGS\) * NOTPOT 0x70000006 \(MIPS_BASE_ADDRESS\) * 0x40000 - 0x7000000a \(MIPS_LOCAL_GOTNO\) * 2 + 0x7000000a \(MIPS_LOCAL_GOTNO\) * 5 0x70000011 \(MIPS_SYMTABNO\) * 12 0x70000012 \(MIPS_UNREFEXTNO\) * .* - 0x70000013 \(MIPS_GOTSYM\) * 0x5 + 0x70000013 \(MIPS_GOTSYM\) * 0x8 0x00000014 \(PLTREL\) * REL 0x00000017 \(JMPREL\) * 0x43028 0x00000002 \(PLTRELSZ\) * 24 \(bytes\) diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd index df8d02a..276d874 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd @@ -2,13 +2,13 @@ # # -32752: lazy resolution function # -32748: reserved for module pointer -# -32744: extf2's GOT entry (undefined 0) -# -32740: extf3's GOT entry (PLT entry) -# -32736: extd2's GOT entry (copy reloc) -# -32732: extf1's GOT entry (.MIPS.stubs entry) -# -32728: extd1's GOT entry (undefined 0) -# -32724: extf4's GOT entry (PLT entry) -# -32620: extd4's GOT entry (undefined 0, reloc only) +# -32744: extd2's local GOT entry (copy reloc) +# -32740: extf3's local GOT entry (PLT entry) +# -32736: extf4's local GOT entry (PLT entry) +# -32732: extf2's global GOT entry (undefined 0) +# -32728: extf1's global GOT entry (.MIPS.stubs entry) +# -32724: extd1's global GOT entry (undefined 0) +# -32720: extd4's global GOT entry (undefined 0, reloc only) .* @@ -61,14 +61,14 @@ Disassembly of section \.text: 44020: 3c1c0006 lui gp,0x6 44024: 0399e021 addu gp,gp,t9 44028: 279c3fd0 addiu gp,gp,16336 - 4402c: 8f998024 lw t9,-32732\(gp\) - 44030: 8f848018 lw a0,-32744\(gp\) - 44034: 8f858028 lw a1,-32728\(gp\) + 4402c: 8f998028 lw t9,-32728\(gp\) + 44030: 8f848024 lw a0,-32732\(gp\) + 44034: 8f85802c lw a1,-32724\(gp\) 44038: 0320f809 jalr t9 - 4403c: 8f868020 lw a2,-32736\(gp\) + 4403c: 8f868018 lw a2,-32744\(gp\) 44040: 8f99801c lw t9,-32740\(gp\) 44044: 03200008 jr t9 - 44048: 8f84802c lw a0,-32724\(gp\) + 44048: 8f848020 lw a0,-32736\(gp\) 0004404c <f3>: 4404c: 03e00008 jr ra @@ -98,5 +98,5 @@ Disassembly of section \.MIPS\.stubs: 440a0: 8f998010 lw t9,-32752\(gp\) 440a4: 03e07821 move t3,ra 440a8: 0320f809 jalr t9 - 440ac: 24180008 li t8,8 + 440ac: 24180009 li t8,9 \.\.\. diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.gd index 8b6b5a0..d5d1b42 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.gd @@ -7,14 +7,17 @@ Primary GOT: 000a0000 -32752\(gp\) 00000000 Lazy resolver 000a0004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + Local entries: + Address Access Initial + 000a0008 -32744\(gp\) 000a2000 + 000a000c -32740\(gp\) 00043080 + 000a0010 -32736\(gp\) 00043060 + Global entries: Address Access Initial Sym\.Val\. Type Ndx Name - 000a0008 -32744\(gp\) 00000000 00000000 FUNC UND extf2 - 000a000c -32740\(gp\) 00000000 00000000 FUNC UND extf3 - 000a0010 -32736\(gp\) 000a2000 000a2000 OBJECT 16 extd2 - 000a0014 -32732\(gp\) 000440a0 000440a0 FUNC UND extf1 - 000a0018 -32728\(gp\) 00000000 00000000 OBJECT UND extd1 - 000a001c -32724\(gp\) 00000000 00000000 FUNC UND extf4 + 000a0014 -32732\(gp\) 00000000 00000000 FUNC UND extf2 + 000a0018 -32728\(gp\) 000440a0 000440a0 FUNC UND extf1 + 000a001c -32724\(gp\) 00000000 00000000 OBJECT UND extd1 000a0020 -32720\(gp\) 00000000 00000000 OBJECT UND extd4 @@ -27,6 +30,6 @@ PLT GOT: Entries: Address Initial Sym.Val. Type Ndx Name - 00081008 00043040 00000000 FUNC UND extf4 + 00081008 00043040 00043060 FUNC UND extf4 0008100c 00043040 00000000 FUNC UND extf5 00081010 00043040 00000000 FUNC UND extf3 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.nd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.nd index 07bfa6b..f93c741 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.nd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.nd @@ -1,17 +1,40 @@ Symbol table '\.dynsym' contains .*: +# +# extf4 is referenced by a JAL and .word. The former requires a PLT entry +# and the latter requires pointer equality, which means a symbol value is +# needed. #... -.*: 00000000 +0 +FUNC +GLOBAL +DEFAULT +UND +extf5 +.*: 0+43060 +0 +FUNC +GLOBAL +DEFAULT \[MIPS PLT\] +UND +extf4 +# +# extf5 is called but does not have its address taken. It needs a PLT +# but no symbol value should be set. +#... +.*: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf5 +# +# extd2 is referenced by %got, .word and %hi/%lo. The last pair forces +# a copy reloc. +# +.*: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2 +# +# extf3 is referenced by a JAL and a GOT CALL reloc. The JAL forces a PLT +# that the GOT CALL reloc will also use, but pointer equality isn't needed +# and so no symbol value should be set. +# +.*: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3 +# +# extd3 is referenced by .word and %hi/%lo. The latter pair forces +# a copy reloc. +#... +.*: 0+a2018 +28 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd3 +# # The index on the next line should correspond to MIPS_GOTSYM, # and the remaining symbols should have the same order as the # GOT layout given in the *.dd dump. -#... - *5: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2 - *6: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3 - *7: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2 - *8: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1 - *9: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1 - *10: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4 +# + *8: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2 + *9: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1 + *10: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1 *11: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4 #pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.rd index 0fd5b7e..afeae98 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.rd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.rd @@ -2,13 +2,13 @@ Relocation section '\.rel\.dyn' at offset .* contains .*: * Offset * Info * Type * Sym\.Value * Sym\. Name 00000000 * 00000000 * R_MIPS_NONE * -000a2018 * [^ ]*7e * R_MIPS_COPY * 000a2018 * extd3 000a2000 * [^ ]*7e * R_MIPS_COPY * 000a2000 * extd2 +000a2018 * [^ ]*7e * R_MIPS_COPY * 000a2018 * extd3 000a1000 * [^ ]*03 * R_MIPS_REL32 * 00000000 * extd1 000a1014 * [^ ]*03 * R_MIPS_REL32 * 00000000 * extd4 Relocation section '\.rel\.plt' at offset .* contains .*: * Offset * Info * Type * Sym\.Value * Sym\. Name -00081008 * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf4 +00081008 * [^ ]*7f * R_MIPS_JUMP_SLOT * 00043060 * extf4 0008100c * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf5 00081010 * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf3 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.ad b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.ad index 5550483..d8fc300 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.ad +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.ad @@ -16,10 +16,10 @@ Dynamic section at offset .* contains .*: 0x0+70000001 \(MIPS_RLD_VERSION\) * 1 0x0+70000005 \(MIPS_FLAGS\) * NOTPOT 0x0+70000006 \(MIPS_BASE_ADDRESS\) * 0x40000 - 0x0+7000000a \(MIPS_LOCAL_GOTNO\) * 2 + 0x0+7000000a \(MIPS_LOCAL_GOTNO\) * 5 0x0+70000011 \(MIPS_SYMTABNO\) * 12 0x0+70000012 \(MIPS_UNREFEXTNO\) * .* - 0x0+70000013 \(MIPS_GOTSYM\) * 0x5 + 0x0+70000013 \(MIPS_GOTSYM\) * 0x8 0x0+00000014 \(PLTREL\) * REL 0x0+00000017 \(JMPREL\) * 0x43050 0x0+00000002 \(PLTRELSZ\) * 48 \(bytes\) diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd index 2480623..fbb3615 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd @@ -1,14 +1,14 @@ # GOT layout: # # -32752: lazy resolution function -# -32744: reserved for module pointer -# -32736: extf2's GOT entry (undefined 0) -# -32728: extf3's GOT entry (PLT entry) -# -32720: extd2's GOT entry (copy reloc) -# -32712: extf1's GOT entry (.MIPS.stubs entry) -# -32704: extd1's GOT entry (undefined 0) -# -32696: extf4's GOT entry (PLT entry) -# -32688: extd4's GOT entry (undefined 0, reloc only) +# -32748: reserved for module pointer +# -32744: extd2's local GOT entry (copy reloc) +# -32740: extf3's local GOT entry (PLT entry) +# -32736: extf4's local GOT entry (PLT entry) +# -32732: extf2's global GOT entry (undefined 0) +# -32728: extf1's global GOT entry (.MIPS.stubs entry) +# -32724: extd1's global GOT entry (undefined 0) +# -32720: extd4's global GOT entry (undefined 0, reloc only) .* @@ -61,14 +61,14 @@ Disassembly of section \.text: 44020: 3c1c0006 lui gp,0x6 44024: 0399e021 addu gp,gp,t9 44028: 279c3fd0 addiu gp,gp,16336 - 4402c: df998038 ld t9,-32712\(gp\) - 44030: df848020 ld a0,-32736\(gp\) - 44034: df858040 ld a1,-32704\(gp\) + 4402c: df998040 ld t9,-32704\(gp\) + 44030: df848038 ld a0,-32712\(gp\) + 44034: df858048 ld a1,-32696\(gp\) 44038: 0320f809 jalr t9 - 4403c: df868030 ld a2,-32720\(gp\) + 4403c: df868020 ld a2,-32736\(gp\) 44040: df998028 ld t9,-32728\(gp\) 44044: 03200008 jr t9 - 44048: df848048 ld a0,-32696\(gp\) + 44048: df848030 ld a0,-32720\(gp\) 0+4404c <f3>: 4404c: 03e00008 jr ra @@ -98,5 +98,5 @@ Disassembly of section \.MIPS\.stubs: 440a0: df998010 ld t9,-32752\(gp\) 440a4: 03e0782d move t3,ra 440a8: 0320f809 jalr t9 - 440ac: 64180008 daddiu t8,zero,8 + 440ac: 64180009 daddiu t8,zero,9 \.\.\. diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.gd index 767d150..46cbcdd 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.gd @@ -1,32 +1,35 @@ Primary GOT: - Canonical gp value: 00000000000a7ff0 + Canonical gp value: 0+0a7ff0 Reserved entries: - Address Access Initial Purpose - 00000000000a0000 -32752\(gp\) 0000000000000000 Lazy resolver - 00000000000a0008 -32744\(gp\) 8000000000000000 Module pointer \(GNU extension\) + * Address * Access * Initial Purpose + 0+0a0000 -32752\(gp\) 0+ Lazy resolver + 0+0a0008 -32744\(gp\) 8000000000000000 Module pointer \(GNU extension\) + + Local entries: + * Address * Access * Initial + 0+0a0010 -32736\(gp\) 0+0a2000 + 0+0a0018 -32728\(gp\) 0+0430c0 + 0+0a0020 -32720\(gp\) 0+0430a0 Global entries: - Address Access Initial Sym\.Val\. Type Ndx Name - 00000000000a0010 -32736\(gp\) 0000000000000000 0000000000000000 FUNC UND extf2 - 00000000000a0018 -32728\(gp\) 0000000000000000 0000000000000000 FUNC UND extf3 - 00000000000a0020 -32720\(gp\) 00000000000a2000 00000000000a2000 OBJECT 16 extd2 - 00000000000a0028 -32712\(gp\) 00000000000440a0 00000000000440a0 FUNC UND extf1 - 00000000000a0030 -32704\(gp\) 0000000000000000 0000000000000000 OBJECT UND extd1 - 00000000000a0038 -32696\(gp\) 0000000000000000 0000000000000000 FUNC UND extf4 - 00000000000a0040 -32688\(gp\) 0000000000000000 0000000000000000 OBJECT UND extd4 + * Address * Access * Initial * Sym\.Val\. * Type * Ndx Name + 0+0a0028 -32712\(gp\) 0+000000 0+000000 FUNC UND extf2 + 0+0a0030 -32704\(gp\) 0+0440a0 0+0440a0 FUNC UND extf1 + 0+0a0038 -32696\(gp\) 0+000000 0+000000 OBJECT UND extd1 + 0+0a0040 -32688\(gp\) 0+000000 0+000000 OBJECT UND extd4 PLT GOT: Reserved entries: - Address Initial Purpose - 0000000000081000 0000000000000000 PLT lazy resolver - 0000000000081008 0000000000000000 Module pointer + * Address * Initial * Purpose + 0+081000 0+ PLT lazy resolver + 0+081008 0+ Module pointer Entries: - Address Initial Sym.Val. Type Ndx Name - 0000000000081010 0000000000043080 0000000000000000 FUNC UND extf4 - 0000000000081018 0000000000043080 0000000000000000 FUNC UND extf5 - 0000000000081020 0000000000043080 0000000000000000 FUNC UND extf3 + * Address * Initial * Sym.Val. * Type * Ndx Name + 0+081010 0+043080 0+0430a0 FUNC UND extf4 + 0+081018 0+043080 0+000000 FUNC UND extf5 + 0+081020 0+043080 0+000000 FUNC UND extf3 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.nd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.nd index 867389b..63b3fc4 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.nd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.nd @@ -1,17 +1,40 @@ Symbol table '\.dynsym' contains .*: +# +# extf4 is referenced by a JAL and .word. The former requires a PLT entry +# and the latter requires pointer equality, which means a symbol value is +# needed. +#... +.*: 0+430a0 +0 +FUNC +GLOBAL +DEFAULT \[MIPS PLT\] +UND +extf4 +# +# extf5 is called but does not have its address taken. It needs a PLT +# but no symbol value should be set. #... .*: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf5 +# +# extd2 is referenced by %got, .word and %hi/%lo. The last pair forces +# a copy reloc. +# +.*: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2 +# +# extf3 is referenced by a JAL and a GOT CALL reloc. The JAL forces a PLT +# that the GOT CALL reloc will also use, but pointer equality isn't needed +# and so no symbol value should be set. +# +.*: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3 +# +# extd3 is referenced by .word and %hi/%lo. The latter pair forces +# a copy reloc. +#... +.*: 0+a2018 +28 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd3 +# # The index on the next line should correspond to MIPS_GOTSYM, # and the remaining symbols should have the same order as the # GOT layout given in the *.dd dump. -#... - *5: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2 - *6: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3 - *7: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2 - *8: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1 - *9: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1 - *10: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4 +# + *8: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2 + *9: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1 + *10: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1 *11: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4 #pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.rd index 666785e..2b25b0a 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.rd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.rd @@ -4,10 +4,10 @@ Relocation section '\.rel\.dyn' at offset .* contains .*: 0+00000 * 0+ * R_MIPS_NONE * *Type2: R_MIPS_NONE * *Type3: R_MIPS_NONE * -0+a2018 * [^ ]*7e * R_MIPS_COPY * 0+a2018 * extd3 +0+a2000 * [^ ]*7e * R_MIPS_COPY * 0+a2000 * extd2 *Type2: R_MIPS_NONE * *Type3: R_MIPS_NONE * -0+a2000 * [^ ]*7e * R_MIPS_COPY * 0+a2000 * extd2 +0+a2018 * [^ ]*7e * R_MIPS_COPY * 0+a2018 * extd3 *Type2: R_MIPS_NONE * *Type3: R_MIPS_NONE * 0+a1000 * [^ ]*03 * R_MIPS_REL32 * 0+00000 * extd1 @@ -19,7 +19,7 @@ Relocation section '\.rel\.dyn' at offset .* contains .*: Relocation section '\.rel\.plt' at offset .* contains .*: * Offset * Info * Type * Sym\. Value * Sym\. Name -0+81010 * [^ ]*7f * R_MIPS_JUMP_SLOT * 0+00000 * extf4 +0+81010 * [^ ]*7f * R_MIPS_JUMP_SLOT * 0+430a0 * extf4 *Type2: R_MIPS_NONE * *Type3: R_MIPS_NONE * 0+81018 * [^ ]*7f * R_MIPS_JUMP_SLOT * 0+00000 * extf5 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.ad b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.ad index fab5581..5df3c6c 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.ad +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.ad @@ -16,10 +16,10 @@ Dynamic section at offset .* contains .*: 0x70000001 \(MIPS_RLD_VERSION\) * 1 0x70000005 \(MIPS_FLAGS\) * NOTPOT 0x70000006 \(MIPS_BASE_ADDRESS\) * 0x40000 - 0x7000000a \(MIPS_LOCAL_GOTNO\) * 2 + 0x7000000a \(MIPS_LOCAL_GOTNO\) * 5 0x70000011 \(MIPS_SYMTABNO\) * 12 0x70000012 \(MIPS_UNREFEXTNO\) * .* - 0x70000013 \(MIPS_GOTSYM\) * 0x5 + 0x70000013 \(MIPS_GOTSYM\) * 0x8 0x00000014 \(PLTREL\) * REL 0x00000017 \(JMPREL\) * 0x43028 0x00000002 \(PLTRELSZ\) * 24 \(bytes\) diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd index 7f101ac..e10a0af 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd @@ -2,13 +2,13 @@ # # -32752: lazy resolution function # -32748: reserved for module pointer -# -32744: extf2's GOT entry (undefined 0) -# -32740: extf3's GOT entry (PLT entry) -# -32736: extd2's GOT entry (copy reloc) -# -32732: extf1's GOT entry (.MIPS.stubs entry) -# -32728: extd1's GOT entry (undefined 0) -# -32724: extf4's GOT entry (PLT entry) -# -32620: extd4's GOT entry (undefined 0, reloc only) +# -32744: extd2's local GOT entry (copy reloc) +# -32740: extf3's local GOT entry (PLT entry) +# -32736: extf4's local GOT entry (PLT entry) +# -32732: extf2's global GOT entry (undefined 0) +# -32728: extf1's global GOT entry (.MIPS.stubs entry) +# -32724: extd1's global GOT entry (undefined 0) +# -32720: extd4's global GOT entry (undefined 0, reloc only) .* @@ -61,14 +61,14 @@ Disassembly of section \.text: 44020: 3c1c0006 lui gp,0x6 44024: 279c3fd0 addiu gp,gp,16336 44028: 0399e021 addu gp,gp,t9 - 4402c: 8f998024 lw t9,-32732\(gp\) - 44030: 8f848018 lw a0,-32744\(gp\) - 44034: 8f858028 lw a1,-32728\(gp\) + 4402c: 8f998028 lw t9,-32728\(gp\) + 44030: 8f848024 lw a0,-32732\(gp\) + 44034: 8f85802c lw a1,-32724\(gp\) 44038: 0320f809 jalr t9 - 4403c: 8f868020 lw a2,-32736\(gp\) + 4403c: 8f868018 lw a2,-32744\(gp\) 44040: 8f99801c lw t9,-32740\(gp\) 44044: 03200008 jr t9 - 44048: 8f84802c lw a0,-32724\(gp\) + 44048: 8f848020 lw a0,-32736\(gp\) 0004404c <f3>: 4404c: 03e00008 jr ra @@ -98,5 +98,5 @@ Disassembly of section \.MIPS\.stubs: 440a0: 8f998010 lw t9,-32752\(gp\) 440a4: 03e07821 move t7,ra 440a8: 0320f809 jalr t9 - 440ac: 24180008 li t8,8 + 440ac: 24180009 li t8,9 \.\.\. diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.gd index 8b6b5a0..d5d1b42 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.gd @@ -7,14 +7,17 @@ Primary GOT: 000a0000 -32752\(gp\) 00000000 Lazy resolver 000a0004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + Local entries: + Address Access Initial + 000a0008 -32744\(gp\) 000a2000 + 000a000c -32740\(gp\) 00043080 + 000a0010 -32736\(gp\) 00043060 + Global entries: Address Access Initial Sym\.Val\. Type Ndx Name - 000a0008 -32744\(gp\) 00000000 00000000 FUNC UND extf2 - 000a000c -32740\(gp\) 00000000 00000000 FUNC UND extf3 - 000a0010 -32736\(gp\) 000a2000 000a2000 OBJECT 16 extd2 - 000a0014 -32732\(gp\) 000440a0 000440a0 FUNC UND extf1 - 000a0018 -32728\(gp\) 00000000 00000000 OBJECT UND extd1 - 000a001c -32724\(gp\) 00000000 00000000 FUNC UND extf4 + 000a0014 -32732\(gp\) 00000000 00000000 FUNC UND extf2 + 000a0018 -32728\(gp\) 000440a0 000440a0 FUNC UND extf1 + 000a001c -32724\(gp\) 00000000 00000000 OBJECT UND extd1 000a0020 -32720\(gp\) 00000000 00000000 OBJECT UND extd4 @@ -27,6 +30,6 @@ PLT GOT: Entries: Address Initial Sym.Val. Type Ndx Name - 00081008 00043040 00000000 FUNC UND extf4 + 00081008 00043040 00043060 FUNC UND extf4 0008100c 00043040 00000000 FUNC UND extf5 00081010 00043040 00000000 FUNC UND extf3 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.nd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.nd index 07bfa6b..f93c741 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.nd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.nd @@ -1,17 +1,40 @@ Symbol table '\.dynsym' contains .*: +# +# extf4 is referenced by a JAL and .word. The former requires a PLT entry +# and the latter requires pointer equality, which means a symbol value is +# needed. #... -.*: 00000000 +0 +FUNC +GLOBAL +DEFAULT +UND +extf5 +.*: 0+43060 +0 +FUNC +GLOBAL +DEFAULT \[MIPS PLT\] +UND +extf4 +# +# extf5 is called but does not have its address taken. It needs a PLT +# but no symbol value should be set. +#... +.*: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf5 +# +# extd2 is referenced by %got, .word and %hi/%lo. The last pair forces +# a copy reloc. +# +.*: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2 +# +# extf3 is referenced by a JAL and a GOT CALL reloc. The JAL forces a PLT +# that the GOT CALL reloc will also use, but pointer equality isn't needed +# and so no symbol value should be set. +# +.*: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3 +# +# extd3 is referenced by .word and %hi/%lo. The latter pair forces +# a copy reloc. +#... +.*: 0+a2018 +28 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd3 +# # The index on the next line should correspond to MIPS_GOTSYM, # and the remaining symbols should have the same order as the # GOT layout given in the *.dd dump. -#... - *5: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2 - *6: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3 - *7: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2 - *8: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1 - *9: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1 - *10: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4 +# + *8: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2 + *9: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1 + *10: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1 *11: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4 #pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.rd index 0fd5b7e..afeae98 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.rd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.rd @@ -2,13 +2,13 @@ Relocation section '\.rel\.dyn' at offset .* contains .*: * Offset * Info * Type * Sym\.Value * Sym\. Name 00000000 * 00000000 * R_MIPS_NONE * -000a2018 * [^ ]*7e * R_MIPS_COPY * 000a2018 * extd3 000a2000 * [^ ]*7e * R_MIPS_COPY * 000a2000 * extd2 +000a2018 * [^ ]*7e * R_MIPS_COPY * 000a2018 * extd3 000a1000 * [^ ]*03 * R_MIPS_REL32 * 00000000 * extd1 000a1014 * [^ ]*03 * R_MIPS_REL32 * 00000000 * extd4 Relocation section '\.rel\.plt' at offset .* contains .*: * Offset * Info * Type * Sym\.Value * Sym\. Name -00081008 * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf4 +00081008 * [^ ]*7f * R_MIPS_JUMP_SLOT * 00043060 * extf4 0008100c * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf5 00081010 * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf3 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6.ld index d9f276b..c819816 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6.ld @@ -37,4 +37,6 @@ SECTIONS . = 0xa2000; .bss : { *(.dynbss) } + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/region1.t b/binutils-2.24/ld/testsuite/ld-mips-elf/region1.t index 13077ab..1f20e56 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/region1.t +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/region1.t @@ -9,4 +9,6 @@ SECTIONS .text : { *(.text) } > TEXTMEM .data : { *(.data) } > DATAMEM .bss : { *(.bss) } > DATAMEM + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/rel32-n32.d b/binutils-2.24/ld/testsuite/ld-mips-elf/rel32-n32.d index 43c2632..9951615 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/rel32-n32.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/rel32-n32.d @@ -10,6 +10,6 @@ Relocation section '.rel.dyn' at offset .* contains 2 entries: [0-9a-f ]+R_MIPS_REL32 Hex dump of section '.text': - 0x000002a0 00000000 00000000 00000000 00000000 ................ - 0x000002b0 000002b0 00000000 00000000 00000000 ................ - 0x000002c0 00000000 00000000 00000000 00000000 ................ + 0x000002e0 00000000 00000000 00000000 00000000 ................ + 0x000002f0 000002f0 00000000 00000000 00000000 ................ + 0x00000300 00000000 00000000 00000000 00000000 ................ diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/rel32-o32.d b/binutils-2.24/ld/testsuite/ld-mips-elf/rel32-o32.d index 0103d79..742cdaa 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/rel32-o32.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/rel32-o32.d @@ -10,6 +10,6 @@ Relocation section '.rel.dyn' at offset .* contains 2 entries: [0-9a-f ]+R_MIPS_REL32 Hex dump of section '.text': - 0x000002a0 00000000 00000000 00000000 00000000 ................ - 0x000002b0 000002b0 00000000 00000000 00000000 ................ - 0x000002c0 00000000 00000000 00000000 00000000 ................ + 0x000002e0 00000000 00000000 00000000 00000000 ................ + 0x000002f0 000002f0 00000000 00000000 00000000 ................ + 0x00000300 00000000 00000000 00000000 00000000 ................ diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/rel64.d b/binutils-2.24/ld/testsuite/ld-mips-elf/rel64.d index 89df314..01bffa3 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/rel64.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/rel64.d @@ -14,6 +14,6 @@ Relocation section '.rel.dyn' at offset .* contains 2 entries: +Type3: R_MIPS_NONE Hex dump of section '.text': - 0x00000400 00000000 00000000 00000000 00000000 ................ - 0x00000410 00000000 00000410 00000000 00000000 ................ - 0x00000420 00000000 00000000 00000000 00000000 ................ + 0x00000450 00000000 00000000 00000000 00000000 ................ + 0x00000460 00000000 00000460 00000000 00000000 ................ + 0x00000470 00000000 00000000 00000000 00000000 ................ diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld index 0a58e6f..dec5ca1 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld @@ -13,5 +13,5 @@ SECTIONS HIDDEN (_gp = . + 0x7ff0); .got : { *(.got) } - /DISCARD/ : { *(.reginfo) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/tls-hidden3.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/tls-hidden3.ld index 8e0d0aa..5609a4b 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/tls-hidden3.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/tls-hidden3.ld @@ -19,7 +19,7 @@ SECTIONS . = ALIGN (0x400); .tdata : { *(.tdata) } - /DISCARD/ : { *(.reginfo) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } } VERSION diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/tls-multi-got-1.r b/binutils-2.24/ld/testsuite/ld-mips-elf/tls-multi-got-1.r index aea3d2d..45bd791 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/tls-multi-got-1.r +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/tls-multi-got-1.r @@ -15,7 +15,7 @@ Dynamic section at offset .* contains 18 entries: 0x70000006 \(MIPS_BASE_ADDRESS\) 0x0 0x7000000a \(MIPS_LOCAL_GOTNO\) 2 0x70000011 \(MIPS_SYMTABNO\) 20011 - 0x70000012 \(MIPS_UNREFEXTNO\) 10 + 0x70000012 \(MIPS_UNREFEXTNO\) 11 0x70000013 \(MIPS_GOTSYM\) 0xb 0x0000001e \(FLAGS\) STATIC_TLS 0x00000000 \(NULL\) 0x0 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/vxworks1.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/vxworks1.ld index 8fe3c48..d9f8621 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/vxworks1.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/vxworks1.ld @@ -28,5 +28,5 @@ SECTIONS . = ALIGN (0x400); .bss : { *(.bss) *(.dynbss) } - /DISCARD/ : { *(.reginfo) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-scripts/overlay-size.t b/binutils-2.24/ld/testsuite/ld-scripts/overlay-size.t index 0d9af35..68c0986 100644 --- a/binutils-2.24/ld/testsuite/ld-scripts/overlay-size.t +++ b/binutils-2.24/ld/testsuite/ld-scripts/overlay-size.t @@ -60,5 +60,5 @@ SECTIONS end_of_data_overlays = . ; . = 0x8000; - /DISCARD/ : { *(.reginfo) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/lib/ld-lib.exp b/binutils-2.24/ld/testsuite/lib/ld-lib.exp index 64ac7b2..d1d8d21 100644 --- a/binutils-2.24/ld/testsuite/lib/ld-lib.exp +++ b/binutils-2.24/ld/testsuite/lib/ld-lib.exp @@ -331,10 +331,12 @@ proc default_ld_compile { cc source object } { proc default_ld_assemble { as in_flags source object } { global ASFLAGS global host_triplet + global srcdir + global subdir if ![info exists ASFLAGS] { set ASFLAGS "" } - set flags [big_or_little_endian] + set flags "[big_or_little_endian] -I$srcdir/$subdir" set exec_output [run_host_cmd "$as" "$flags $in_flags $ASFLAGS -o $object $source"] set exec_output [prune_warnings $exec_output] if [string match "" $exec_output] then { @@ -489,6 +491,11 @@ proc ld_simple_link_defsyms {} { # ld_after_inputfiles: FLAGS # Similar to "ld", but put after all input files. # +# objcopy_objects: FLAGS +# Run objcopy with the specified flags after assembling any source +# that has the special marker RUN_OBJCOPY in the source specific +# flags. +# # objcopy_linked_file: FLAGS # Run objcopy on the linked file with the specified flags. # This lets you transform the linked file using objcopy, before the @@ -597,6 +604,7 @@ proc run_dump_test { name {extra_options {}} } { set opts(error) {} set opts(warning) {} set opts(objcopy_linked_file) {} + set opts(objcopy_objects) {} foreach i $opt_array { set opt_name [lindex $i 0] @@ -776,6 +784,12 @@ proc run_dump_test { name {extra_options {}} } { for { set i 0 } { $i < [llength $sourcefiles] } { incr i } { set sourcefile [lindex $sourcefiles $i] set sourceasflags [lindex $asflags $i] + set run_objcopy_objects 0 + + if { [string match "*RUN_OBJCOPY*" $sourceasflags] } { + set run_objcopy_objects 1 + } + regsub "RUN_OBJCOPY" $sourceasflags "" sourceasflags set objfile "tmpdir/dump$i.o" catch "exec rm -f $objfile" exec_output @@ -799,6 +813,30 @@ proc run_dump_test { name {extra_options {}} } { fail $testname return } + + if { $run_objcopy_objects } { + set cmd "$OBJCOPY $opts(objcopy_objects) $objfile" + + send_log "$cmd\n" + set cmdret [remote_exec host [concat sh -c [list "$cmd 2>&1"]] \ + "" "/dev/null" "objcopy.tmp"] + remote_upload host "objcopy.tmp" + set comp_output [prune_warnings [file_contents "objcopy.tmp"]] + remote_file host delete "objcopy.tmp" + remote_file build delete "objcopy.tmp" + + if { [lindex $cmdret 0] != 0 \ + || ![string match "" $comp_output] } { + send_log "$comp_output\n" + verbose "$comp_output" 3 + + set exitstat "succeeded" + if { $cmdret != 0 } { set exitstat "failed" } + verbose -log "$exitstat with: <$comp_output>" + fail $testname + return + } + } } set expmsg $opts(error) diff --git a/binutils-2.24/opcodes/ChangeLog b/binutils-2.24/opcodes/ChangeLog index 0b72d5b..57f66a7 100644 --- a/binutils-2.24/opcodes/ChangeLog +++ b/binutils-2.24/opcodes/ChangeLog @@ -1,7 +1,72 @@ +2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com> + + * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction. + (I34): New define. + (I36): New define. + (I66): New define. + (I68): New define. + * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and + mips64r5. + (parse_mips_dis_option): Update MSA and virtualization support to + allow mips64r3 and mips64r5. + +2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com> + + * mips-opc.c (G3): Remove I4. + +2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com> + + * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2 + to allow the MIPS XPA ASE. + (parse_mips_dis_option): Process the -Mxpa option. + * mips-opc.c (XPA): New define. + (mips_builtin_opcodes): Add MIPS XPA instructions and move the + locations of the ctc0 and cfc0 instructions. + +2014-03-04 Heiher <r@hev.cc> + + * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A. + +2014-03-04 Richard Sandiford <rdsandiford@googlemail.com> + + * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions + so that they come after the Loongson extensions. + +2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com> + + * mips-dis.c: Add mips_cp1_names pointer. + (mips_cp1_names_numeric): New array. + (mips_cp1_names_mips3264): New array. + (mips_arch_choice): Add cp1_names. + (mips_arch_choices): Add relevant cp1 register name array to each of + the elements. + (set_default_mips_dis_options): Add support for setting up the + mips_cp1_names pointer. + (parse_mips_dis_option): Add support for the cp1-names command line + variable. Also setup the mips_cp1_names pointer. + (print_reg): Print out name of the cp1 register. + +2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com> + + * micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u, + +v and +w. + (micromips_opcodes): Reduced element index range for sldi, splati, + copy_s, copy_u, insert and insve instructions. + * opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u, + +v and +w. + (mips_builtin_opcodes): Reduced element index range for sldi, splati, + copy_s, copy_u, insert and insve instructions. + 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-opc.c (aarch64_pstatefields): Update. +2013-11-19 Catherine Moore <clm@codesourcery.com> + + * micromips-opc.c (LM): Define. + (micromips_opcodes): Add LM to load instructions. + * mips-opc.c (prefe): Add LM attribute. + 2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com> Revert @@ -14,6 +79,11 @@ (aarch64_sys_reg_readonly_p): New function. (aarch64_sys_reg_writeonly_p): Ditto. +2013-11-15 Maciej W. Rozycki <macro@codesourcery.com> + + * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and + "mtcr". + 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-opc.c (CPENT): New define. @@ -56,6 +126,28 @@ (operand_general_constraint_met_p): Replace set_other_error with set_syntax_error. +2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> + + * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W, + +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x, + +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. + (MSA): New define. + (MSA64): New define. + (micromips_opcodes): Add MSA instructions. + * mips-dis.c (msa_control_names): New array. + (mips_abi_choice): Add ASE_MSA to mips32r2. + Remove ASE_MDMX from mips64r2. + Add ASE_MSA and ASE_MSA64 to mips64r2. + (parse_mips_dis_option): Handle -Mmsa. + (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL. + (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX. + (print_mips_disassembler_options): Print -Mmsa. + * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k, + +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. + (MSA): New define. + (MSA64): New define. + (mips_builtin_op): Add MSA instructions. + 2013-10-12 Jan Beulich <jbeulich@suse.com> * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the @@ -85,6 +177,10 @@ * v850-dis.c (v850_cacheop_codes, v850_prefop_codes): Remove duplicate const qualifier. +2013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com> + + * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0. + 2013-09-20 Alan Modra <amodra@gmail.com> * configure: Regenerate. diff --git a/binutils-2.24/opcodes/micromips-opc.c b/binutils-2.24/opcodes/micromips-opc.c index fa6efb5..06f6da2 100644 --- a/binutils-2.24/opcodes/micromips-opc.c +++ b/binutils-2.24/opcodes/micromips-opc.c @@ -107,9 +107,35 @@ decode_micromips_operand (const char *p) case 'F': MSB (5, 11, 33, TRUE, 64); /* (33 .. 64), 64-bit op */ case 'G': MSB (5, 11, 33, FALSE, 64); /* (33 .. 64), 64-bit op */ case 'H': MSB (5, 11, 1, FALSE, 64); /* (1 .. 32), 64-bit op */ + case 'T': INT_ADJ (10, 16, 511, 0, FALSE); /* (-512 .. 511) << 0 */ + case 'U': INT_ADJ (10, 16, 511, 1, FALSE); /* (-512 .. 511) << 1 */ + case 'V': INT_ADJ (10, 16, 511, 2, FALSE); /* (-512 .. 511) << 2 */ + case 'W': INT_ADJ (10, 16, 511, 3, FALSE); /* (-512 .. 511) << 3 */ + case 'd': REG (5, 6, MSA); + case 'e': REG (5, 11, MSA); + case 'h': REG (5, 16, MSA); case 'i': JALX (26, 0, 2); case 'j': SINT (9, 0); + case 'k': REG (5, 6, GP); + case 'l': REG (5, 6, MSA_CTRL); + case 'n': REG (5, 11, MSA_CTRL); + case 'o': SPECIAL (4, 16, IMM_INDEX); + case 'u': SPECIAL (3, 16, IMM_INDEX); + case 'v': SPECIAL (2, 16, IMM_INDEX); + case 'w': SPECIAL (1, 16, IMM_INDEX); + case 'x': BIT (5, 16, 0); /* (0 .. 31) */ + + case '~': BIT (2, 6, 1); /* (1 .. 4) */ + case '!': BIT (3, 16, 0); /* (0 .. 7) */ + case '@': BIT (4, 16, 0); /* (0 .. 15) */ + case '#': BIT (6, 16, 0); /* (0 .. 63) */ + case '$': UINT (5, 16); /* (0 .. 31) */ + case '%': SINT (5, 16); /* (-16 .. 15) */ + case '^': SINT (10, 11); /* (-512 .. 511) */ + case '&': SPECIAL (0, 0, IMM_INDEX); + case '*': SPECIAL (5, 16, REG_INDEX); + case '|': BIT (8, 16, 0); /* (0 .. 255) */ } break; @@ -174,9 +200,11 @@ decode_micromips_operand (const char *p) #define CBD INSN_COND_BRANCH_DELAY #define NODS INSN_NO_DELAY_SLOT #define TRAP INSN_NO_DELAY_SLOT +#define LM INSN_LOAD_MEMORY #define SM INSN_STORE_MEMORY #define BD16 INSN2_BRANCH_DELAY_16BIT /* Used in pinfo2. */ #define BD32 INSN2_BRANCH_DELAY_32BIT /* Used in pinfo2. */ +#define F32M INSN_FP_32_MOVE #define WR_1 INSN_WRITE_1 #define WR_2 INSN_WRITE_2 @@ -246,15 +274,19 @@ decode_micromips_operand (const char *p) #define IVIRT ASE_VIRT #define IVIRT64 ASE_VIRT64 +/* MSA support. */ +#define MSA ASE_MSA +#define MSA64 ASE_MSA64 + const struct mips_opcode micromips_opcodes[] = { /* These instructions appear first so that the disassembler will find them first. The assemblers uses a hash table based on the instruction name anyhow. */ /* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */ -{"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_3, 0, I1, 0, 0 }, +{"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_3|LM, 0, I1, 0, 0 }, {"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"prefx", "h,t(b)", 0x540001a0, 0xfc0007ff, RD_2|RD_3|FP_S, 0, I1, 0, 0 }, +{"prefx", "h,t(b)", 0x540001a0, 0xfc0007ff, RD_2|RD_3|FP_S|LM, 0, I1, 0, 0 }, {"nop", "", 0x0c00, 0xffff, 0, INSN2_ALIAS, I1, 0, 0 }, {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ {"ssnop", "", 0x00000800, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ @@ -284,7 +316,7 @@ const struct mips_opcode micromips_opcodes[] = {"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, {"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, {"abs.ps", "T,V", 0x5400437b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, -{"aclr", "\\,~(b)", 0x2000b000, 0xff00f000, RD_3|SM|NODS, 0, 0, MC, 0 }, +{"aclr", "\\,~(b)", 0x2000b000, 0xff00f000, RD_3|LM|SM|NODS, 0, 0, MC, 0 }, {"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC, 0 }, {"add", "d,v,t", 0x00000110, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1, 0, 0 }, @@ -316,7 +348,7 @@ const struct mips_opcode micromips_opcodes[] = {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1, 0, 0 }, {"andi", "md,mc,mC", 0x2c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, {"andi", "t,r,i", 0xd0000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, -{"aset", "\\,~(b)", 0x20003000, 0xff00f000, RD_3|SM|NODS, 0, 0, MC, 0 }, +{"aset", "\\,~(b)", 0x20003000, 0xff00f000, RD_3|LM|SM|NODS, 0, 0, MC, 0 }, {"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC, 0 }, /* b is at the top of the table. */ /* bal is at the top of the table. */ @@ -586,12 +618,12 @@ const struct mips_opcode micromips_opcodes[] = {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3, 0, 0 }, {"dmfc0", "t,G", 0x580000fc, 0xfc00ffff, WR_1|RD_C0, 0, I3, 0, 0 }, {"dmfc0", "t,G,H", 0x580000fc, 0xfc00c7ff, WR_1|RD_C0, 0, I3, 0, 0 }, -{"dmfgc0", "t,G", 0x580000e7, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, -{"dmfgc0", "t,G,H", 0x580000e7, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, +{"dmfgc0", "t,G", 0x580004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, +{"dmfgc0", "t,G,H", 0x580004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT64, 0 }, {"dmtc0", "t,G", 0x580002fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, I3, 0, 0 }, {"dmtc0", "t,G,H", 0x580002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, I3, 0, 0 }, -{"dmtgc0", "t,G", 0x580002e7, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, -{"dmtgc0", "t,G,H", 0x580002e7, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, +{"dmtgc0", "t,G", 0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, +{"dmtgc0", "t,G,H", 0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, {"dmfc1", "t,S", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I3, 0, 0 }, {"dmfc1", "t,G", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I3, 0, 0 }, {"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S, 0, I3, 0, 0 }, @@ -711,78 +743,78 @@ const struct mips_opcode micromips_opcodes[] = {"jals", "a", 0x74000000, 0xfc000000, WR_31|UBD, BD16, I1, 0, 0 }, {"jalx", "+i", 0xf0000000, 0xfc000000, WR_31|UBD, BD32, I1, 0, 0 }, {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lb", "t,o(b)", 0x1c000000, 0xfc000000, WR_1|RD_3, 0, I1, 0, 0 }, +{"lb", "t,o(b)", 0x1c000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lbu", "md,mG(ml)", 0x0800, 0xfc00, WR_1|RD_3, 0, I1, 0, 0 }, -{"lbu", "t,o(b)", 0x14000000, 0xfc000000, WR_1|RD_3, 0, I1, 0, 0 }, +{"lbu", "md,mG(ml)", 0x0800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{"lbu", "t,o(b)", 0x14000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1, 0, 0 }, {"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1, 0, 0 }, /* The macro has to be first to handle o32 correctly. */ {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3, 0, I3, 0, 0 }, -{"ldc1", "T,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D, 0, I1, 0, 0 }, -{"ldc1", "E,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D, 0, I1, 0, 0 }, +{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 }, +{"ldc1", "T,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D|LM, 0, I1, 0, 0 }, +{"ldc1", "E,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D|LM, 0, I1, 0, 0 }, {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, -{"ldc2", "E,~(b)", 0x20002000, 0xfc00f000, RD_3|WR_CC, 0, I1, 0, 0 }, +{"ldc2", "E,~(b)", 0x20002000, 0xfc00f000, RD_3|WR_CC|LM, 0, I1, 0, 0 }, {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"l.d", "T,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D, 0, I1, 0, 0 }, /* ldc1 */ +{"l.d", "T,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D|LM, 0, I1, 0, 0 }, /* ldc1 */ {"l.d", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, -{"ldl", "t,~(b)", 0x60004000, 0xfc00f000, WR_1|RD_3, 0, I3, 0, 0 }, +{"ldl", "t,~(b)", 0x60004000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 }, {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"ldm", "n,~(b)", 0x20007000, 0xfc00f000, RD_3, 0, I3, 0, 0 }, +{"ldm", "n,~(b)", 0x20007000, 0xfc00f000, RD_3|LM, 0, I3, 0, 0 }, {"ldm", "n,A(b)", 0, (int) M_LDM_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"ldp", "t,~(b)", 0x20004000, 0xfc00f000, WR_1|RD_3, 0, I3, 0, 0 }, +{"ldp", "t,~(b)", 0x20004000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 }, {"ldp", "t,A(b)", 0, (int) M_LDP_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"ldr", "t,~(b)", 0x60005000, 0xfc00f000, WR_1|RD_3, 0, I3, 0, 0 }, +{"ldr", "t,~(b)", 0x60005000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 }, {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"ldxc1", "D,t(b)", 0x540000c8, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, -{"lh", "t,o(b)", 0x3c000000, 0xfc000000, WR_1|RD_3, 0, I1, 0, 0 }, +{"ldxc1", "D,t(b)", 0x540000c8, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D|LM, 0, I1, 0, 0 }, +{"lh", "t,o(b)", 0x3c000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lhu", "md,mH(ml)", 0x2800, 0xfc00, WR_1|RD_3, 0, I1, 0, 0 }, -{"lhu", "t,o(b)", 0x34000000, 0xfc000000, WR_1|RD_3, 0, I1, 0, 0 }, +{"lhu", "md,mH(ml)", 0x2800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{"lhu", "t,o(b)", 0x34000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1, 0, 0 }, /* li is at the start of the table. */ {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"ll", "t,~(b)", 0x60003000, 0xfc00f000, WR_1|RD_3, 0, I1, 0, 0 }, +{"ll", "t,~(b)", 0x60003000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 }, {"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lld", "t,~(b)", 0x60007000, 0xfc00f000, WR_1|RD_3, 0, I3, 0, 0 }, +{"lld", "t,~(b)", 0x60007000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 }, {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, 0, 0 }, {"lui", "s,u", 0x41a00000, 0xffe00000, WR_1, 0, I1, 0, 0 }, -{"luxc1", "D,t(b)", 0x54000148, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 }, -{"lw", "md,mJ(ml)", 0x6800, 0xfc00, WR_1|RD_3, 0, I1, 0, 0 }, -{"lw", "mp,mU(ms)", 0x4800, 0xfc00, WR_1|RD_3, 0, I1, 0, 0 }, /* lwsp */ -{"lw", "md,mA(ma)", 0x6400, 0xfc00, WR_1|RD_3, 0, I1, 0, 0 }, /* lwgp */ -{"lw", "t,o(b)", 0xfc000000, 0xfc000000, WR_1|RD_3, 0, I1, 0, 0 }, +{"luxc1", "D,t(b)", 0x54000148, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D|LM, 0, I1, 0, 0 }, +{"lw", "md,mJ(ml)", 0x6800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{"lw", "mp,mU(ms)", 0x4800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, /* lwsp */ +{"lw", "md,mA(ma)", 0x6400, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, /* lwgp */ +{"lw", "t,o(b)", 0xfc000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lwc1", "T,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S, 0, I1, 0, 0 }, -{"lwc1", "E,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S, 0, I1, 0, 0 }, +{"lwc1", "T,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S|LM|F32M, 0, I1, 0, 0 }, +{"lwc1", "E,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S|LM|F32M, 0, I1, 0, 0 }, {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"lwc2", "E,~(b)", 0x20000000, 0xfc00f000, RD_3|WR_CC, 0, I1, 0, 0 }, +{"lwc2", "E,~(b)", 0x20000000, 0xfc00f000, RD_3|WR_CC|LM, 0, I1, 0, 0 }, {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"l.s", "T,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S, 0, I1, 0, 0 }, /* lwc1 */ +{"l.s", "T,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S|LM|F32M, 0, I1, 0, 0 }, /* lwc1 */ {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"lwl", "t,~(b)", 0x60000000, 0xfc00f000, WR_1|RD_3, 0, I1, 0, 0 }, +{"lwl", "t,~(b)", 0x60000000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 }, {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lcache", "t,~(b)", 0x60000000, 0xfc00f000, WR_1|RD_3, 0, I1, 0, 0 }, /* same */ +{"lcache", "t,~(b)", 0x60000000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 }, /* same */ {"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lwm", "mN,mJ(ms)", 0x4500, 0xffc0, RD_3|NODS, 0, I1, 0, 0 }, -{"lwm", "n,~(b)", 0x20005000, 0xfc00f000, RD_3|NODS, 0, I1, 0, 0 }, +{"lwm", "mN,mJ(ms)", 0x4500, 0xffc0, RD_3|NODS|LM, 0, I1, 0, 0 }, +{"lwm", "n,~(b)", 0x20005000, 0xfc00f000, RD_3|NODS|LM, 0, I1, 0, 0 }, {"lwm", "n,A(b)", 0, (int) M_LWM_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lwp", "t,~(b)", 0x20001000, 0xfc00f000, WR_1|RD_3|NODS, 0, I1, 0, 0 }, +{"lwp", "t,~(b)", 0x20001000, 0xfc00f000, WR_1|RD_3|NODS|LM, 0, I1, 0, 0 }, {"lwp", "t,A(b)", 0, (int) M_LWP_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lwr", "t,~(b)", 0x60001000, 0xfc00f000, WR_1|RD_3, 0, I1, 0, 0 }, +{"lwr", "t,~(b)", 0x60001000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 }, {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lwu", "t,~(b)", 0x6000e000, 0xfc00f000, WR_1|RD_3, 0, I3, 0, 0 }, +{"lwu", "t,~(b)", 0x6000e000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 }, {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"lwxc1", "D,t(b)", 0x54000048, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, +{"lwxc1", "D,t(b)", 0x54000048, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S|LM|F32M, 0, I1, 0, 0 }, {"flush", "t,~(b)", 0x60001000, 0xfc00f000, WR_1|RD_3, 0, I1, 0, 0 }, /* same */ {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lwxs", "d,t(b)", 0x00000118, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, +{"lwxs", "d,t(b)", 0x00000118, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, I1, 0, 0 }, {"madd", "s,t", 0x0000cb3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, 0 }, {"madd", "7,s,t", 0x00000abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"madd.d", "D,R,S,T", 0x54000009, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 }, @@ -792,8 +824,8 @@ const struct mips_opcode micromips_opcodes[] = {"maddu", "7,s,t", 0x00001abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"mfc0", "t,G", 0x000000fc, 0xfc00ffff, WR_1|RD_C0, 0, I1, 0, 0 }, {"mfc0", "t,G,H", 0x000000fc, 0xfc00c7ff, WR_1|RD_C0, 0, I1, 0, 0 }, -{"mfc1", "t,S", 0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"mfc1", "t,G", 0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{"mfc1", "t,S", 0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|F32M, 0, I1, 0, 0 }, +{"mfc1", "t,G", 0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|F32M, 0, I1, 0, 0 }, {"mfc2", "t,G", 0x00004d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 }, {"mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT, 0 }, {"mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT, 0 }, @@ -838,8 +870,8 @@ const struct mips_opcode micromips_opcodes[] = {"msubu", "7,s,t", 0x00003abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"mtc0", "t,G", 0x000002fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, I1, 0, 0 }, {"mtc0", "t,G,H", 0x000002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, I1, 0, 0 }, -{"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S, 0, I1, 0, 0 }, -{"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S, 0, I1, 0, 0 }, +{"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|F32M, 0, I1, 0, 0 }, +{"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|F32M, 0, I1, 0, 0 }, {"mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, {"mtgc0", "t,G", 0x000006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 }, {"mtgc0", "t,G,H", 0x000006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 }, @@ -1006,13 +1038,13 @@ const struct mips_opcode micromips_opcodes[] = {"sw", "mp,mU(ms)", 0xc800, 0xfc00, RD_1|RD_3|SM, 0, I1, 0, 0 }, /* swsp */ {"sw", "t,o(b)", 0xf8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"swc1", "T,o(b)", 0x98000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, -{"swc1", "E,o(b)", 0x98000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, +{"swc1", "T,o(b)", 0x98000000, 0xfc000000, RD_1|RD_3|SM|FP_S|F32M, 0, I1, 0, 0 }, +{"swc1", "E,o(b)", 0x98000000, 0xfc000000, RD_1|RD_3|SM|FP_S|F32M, 0, I1, 0, 0 }, {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"swc2", "E,~(b)", 0x20008000, 0xfc00f000, RD_3|RD_C2|SM, 0, I1, 0, 0 }, {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"s.s", "T,o(b)", 0x98000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, /* swc1 */ +{"s.s", "T,o(b)", 0x98000000, 0xfc000000, RD_1|RD_3|SM|FP_S|F32M, 0, I1, 0, 0 }, /* swc1 */ {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"swl", "t,~(b)", 0x60008000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, 0 }, {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, 0 }, @@ -1027,7 +1059,7 @@ const struct mips_opcode micromips_opcodes[] = {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, 0 }, {"invalidate", "t,~(b)", 0x60009000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, 0 }, /* same */ {"invalidate", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"swxc1", "D,t(b)", 0x54000088, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S, 0, I1, 0, 0 }, +{"swxc1", "D,t(b)", 0x54000088, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S|F32M, 0, I1, 0, 0 }, {"sync_acquire", "", 0x00116b7c, 0xffffffff, NODS, 0, I1, 0, 0 }, {"sync_mb", "", 0x00106b7c, 0xffffffff, NODS, 0, I1, 0, 0 }, {"sync_release", "", 0x00126b7c, 0xffffffff, NODS, 0, I1, 0, 0 }, @@ -1101,21 +1133,21 @@ const struct mips_opcode micromips_opcodes[] = {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1, 0, 0 }, {"xori", "t,r,i", 0x70000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, /* microMIPS Enhanced VA Scheme */ -{"lbue", "t,+j(b)", 0x60006000, 0xfc00fe00, WR_1|RD_3, 0, 0, EVA, 0 }, +{"lbue", "t,+j(b)", 0x60006000, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, {"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lhue", "t,+j(b)", 0x60006200, 0xfc00fe00, WR_1|RD_3, 0, 0, EVA, 0 }, +{"lhue", "t,+j(b)", 0x60006200, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, {"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lbe", "t,+j(b)", 0x60006800, 0xfc00fe00, WR_1|RD_3, 0, 0, EVA, 0 }, +{"lbe", "t,+j(b)", 0x60006800, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, {"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lhe", "t,+j(b)", 0x60006a00, 0xfc00fe00, WR_1|RD_3, 0, 0, EVA, 0 }, +{"lhe", "t,+j(b)", 0x60006a00, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, {"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lle", "t,+j(b)", 0x60006c00, 0xfc00fe00, WR_1|RD_3, 0, 0, EVA, 0 }, +{"lle", "t,+j(b)", 0x60006c00, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, {"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lwe", "t,+j(b)", 0x60006e00, 0xfc00fe00, WR_1|RD_3, 0, 0, EVA, 0 }, +{"lwe", "t,+j(b)", 0x60006e00, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, {"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lwle", "t,+j(b)", 0x60006400, 0xfc00fe00, WR_1|RD_3, 0, 0, EVA, 0 }, +{"lwle", "t,+j(b)", 0x60006400, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, {"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lwre", "t,+j(b)", 0x60006600, 0xfc00fe00, WR_1|RD_3, 0, 0, EVA, 0 }, +{"lwre", "t,+j(b)", 0x60006600, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 }, {"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"sbe", "t,+j(b)", 0x6000a800, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 }, {"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, @@ -1131,7 +1163,7 @@ const struct mips_opcode micromips_opcodes[] = {"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"cachee", "k,+j(b)", 0x6000a600, 0xfc00fe00, RD_3, 0, 0, EVA, 0 }, {"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA, 0 }, -{"prefe", "k,+j(b)", 0x6000a400, 0xfc00fe00, RD_3, 0, 0, EVA, 0 }, +{"prefe", "k,+j(b)", 0x6000a400, 0xfc00fe00, RD_3|LM, 0, 0, EVA, 0 }, {"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA, 0 }, /* MIPS DSP ASE. */ {"absq_s.ph", "t,s", 0x0000113c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, @@ -1175,9 +1207,9 @@ const struct mips_opcode micromips_opcodes[] = {"extrv.w", "t,7,s", 0x00000ebc, 0xfc003fff, WR_1|RD_3|RD_a, 0, 0, D32, 0 }, {"extr.w", "t,7,6", 0x00000e7c, 0xfc003fff, WR_1|RD_a, 0, 0, D32, 0 }, {"insv", "t,s", 0x0000413c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 }, -{"lbux", "d,t(b)", 0x00000225, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"lhx", "d,t(b)", 0x00000165, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, -{"lwx", "d,t(b)", 0x000001a5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, +{"lbux", "d,t(b)", 0x00000225, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, D32, 0 }, +{"lhx", "d,t(b)", 0x00000165, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, D32, 0 }, +{"lwx", "d,t(b)", 0x000001a5, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, D32, 0 }, {"maq_sa.w.phl", "7,s,t", 0x00003a7c, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"maq_sa.w.phr", "7,s,t", 0x00002a7c, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"maq_s.w.phl", "7,s,t", 0x00001a7c, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, @@ -1287,6 +1319,539 @@ const struct mips_opcode micromips_opcodes[] = {"subqh_r.ph", "d,s,t", 0x0000064d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, {"subqh.w", "d,s,t", 0x0000028d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, {"subqh_r.w", "d,s,t", 0x0000068d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D33, 0 }, +/* MSA Extension. */ +{"sll.b", "+d,+e,+h", 0x5800001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sll.h", "+d,+e,+h", 0x5820001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sll.w", "+d,+e,+h", 0x5840001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sll.d", "+d,+e,+h", 0x5860001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"slli.b", "+d,+e,+!", 0x58700012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"slli.h", "+d,+e,+@", 0x58600012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"slli.w", "+d,+e,+x", 0x58400012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"slli.d", "+d,+e,+#", 0x58000012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"sra.b", "+d,+e,+h", 0x5880001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sra.h", "+d,+e,+h", 0x58a0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sra.w", "+d,+e,+h", 0x58c0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sra.d", "+d,+e,+h", 0x58e0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srai.b", "+d,+e,+!", 0x58f00012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srai.h", "+d,+e,+@", 0x58e00012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srai.w", "+d,+e,+x", 0x58c00012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srai.d", "+d,+e,+#", 0x58800012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srl.b", "+d,+e,+h", 0x5900001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srl.h", "+d,+e,+h", 0x5920001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srl.w", "+d,+e,+h", 0x5940001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srl.d", "+d,+e,+h", 0x5960001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srli.b", "+d,+e,+!", 0x59700012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srli.h", "+d,+e,+@", 0x59600012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srli.w", "+d,+e,+x", 0x59400012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srli.d", "+d,+e,+#", 0x59000012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bclr.b", "+d,+e,+h", 0x5980001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bclr.h", "+d,+e,+h", 0x59a0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bclr.w", "+d,+e,+h", 0x59c0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bclr.d", "+d,+e,+h", 0x59e0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bclri.b", "+d,+e,+!", 0x59f00012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bclri.h", "+d,+e,+@", 0x59e00012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bclri.w", "+d,+e,+x", 0x59c00012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bclri.d", "+d,+e,+#", 0x59800012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bset.b", "+d,+e,+h", 0x5a00001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bset.h", "+d,+e,+h", 0x5a20001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bset.w", "+d,+e,+h", 0x5a40001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bset.d", "+d,+e,+h", 0x5a60001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bseti.b", "+d,+e,+!", 0x5a700012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bseti.h", "+d,+e,+@", 0x5a600012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bseti.w", "+d,+e,+x", 0x5a400012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bseti.d", "+d,+e,+#", 0x5a000012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bneg.b", "+d,+e,+h", 0x5a80001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bneg.h", "+d,+e,+h", 0x5aa0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bneg.w", "+d,+e,+h", 0x5ac0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bneg.d", "+d,+e,+h", 0x5ae0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bnegi.b", "+d,+e,+!", 0x5af00012, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bnegi.h", "+d,+e,+@", 0x5ae00012, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bnegi.w", "+d,+e,+x", 0x5ac00012, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bnegi.d", "+d,+e,+#", 0x5a800012, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"binsl.b", "+d,+e,+h", 0x5b00001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"binsl.h", "+d,+e,+h", 0x5b20001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"binsl.w", "+d,+e,+h", 0x5b40001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"binsl.d", "+d,+e,+h", 0x5b60001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"binsli.b", "+d,+e,+!", 0x5b700012, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"binsli.h", "+d,+e,+@", 0x5b600012, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"binsli.w", "+d,+e,+x", 0x5b400012, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"binsli.d", "+d,+e,+#", 0x5b000012, 0xffc0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"binsr.b", "+d,+e,+h", 0x5b80001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"binsr.h", "+d,+e,+h", 0x5ba0001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"binsr.w", "+d,+e,+h", 0x5bc0001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"binsr.d", "+d,+e,+h", 0x5be0001a, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"binsri.b", "+d,+e,+!", 0x5bf00012, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"binsri.h", "+d,+e,+@", 0x5be00012, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"binsri.w", "+d,+e,+x", 0x5bc00012, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"binsri.d", "+d,+e,+#", 0x5b800012, 0xffc0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"addv.b", "+d,+e,+h", 0x5800002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"addv.h", "+d,+e,+h", 0x5820002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"addv.w", "+d,+e,+h", 0x5840002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"addv.d", "+d,+e,+h", 0x5860002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"addvi.b", "+d,+e,+$", 0x58000029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"addvi.h", "+d,+e,+$", 0x58200029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"addvi.w", "+d,+e,+$", 0x58400029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"addvi.d", "+d,+e,+$", 0x58600029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"subv.b", "+d,+e,+h", 0x5880002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subv.h", "+d,+e,+h", 0x58a0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subv.w", "+d,+e,+h", 0x58c0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subv.d", "+d,+e,+h", 0x58e0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subvi.b", "+d,+e,+$", 0x58800029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"subvi.h", "+d,+e,+$", 0x58a00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"subvi.w", "+d,+e,+$", 0x58c00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"subvi.d", "+d,+e,+$", 0x58e00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"max_s.b", "+d,+e,+h", 0x5900002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_s.h", "+d,+e,+h", 0x5920002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_s.w", "+d,+e,+h", 0x5940002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_s.d", "+d,+e,+h", 0x5960002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"maxi_s.b", "+d,+e,+%", 0x59000029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"maxi_s.h", "+d,+e,+%", 0x59200029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"maxi_s.w", "+d,+e,+%", 0x59400029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"maxi_s.d", "+d,+e,+%", 0x59600029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"max_u.b", "+d,+e,+h", 0x5980002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_u.h", "+d,+e,+h", 0x59a0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_u.w", "+d,+e,+h", 0x59c0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_u.d", "+d,+e,+h", 0x59e0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"maxi_u.b", "+d,+e,+$", 0x59800029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"maxi_u.h", "+d,+e,+$", 0x59a00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"maxi_u.w", "+d,+e,+$", 0x59c00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"maxi_u.d", "+d,+e,+$", 0x59e00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"min_s.b", "+d,+e,+h", 0x5a00002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_s.h", "+d,+e,+h", 0x5a20002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_s.w", "+d,+e,+h", 0x5a40002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_s.d", "+d,+e,+h", 0x5a60002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mini_s.b", "+d,+e,+%", 0x5a000029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"mini_s.h", "+d,+e,+%", 0x5a200029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"mini_s.w", "+d,+e,+%", 0x5a400029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"mini_s.d", "+d,+e,+%", 0x5a600029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"min_u.b", "+d,+e,+h", 0x5a80002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_u.h", "+d,+e,+h", 0x5aa0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_u.w", "+d,+e,+h", 0x5ac0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_u.d", "+d,+e,+h", 0x5ae0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mini_u.b", "+d,+e,+$", 0x5a800029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"mini_u.h", "+d,+e,+$", 0x5aa00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"mini_u.w", "+d,+e,+$", 0x5ac00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"mini_u.d", "+d,+e,+$", 0x5ae00029, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"max_a.b", "+d,+e,+h", 0x5b00002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_a.h", "+d,+e,+h", 0x5b20002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_a.w", "+d,+e,+h", 0x5b40002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_a.d", "+d,+e,+h", 0x5b60002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_a.b", "+d,+e,+h", 0x5b80002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_a.h", "+d,+e,+h", 0x5ba0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_a.w", "+d,+e,+h", 0x5bc0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_a.d", "+d,+e,+h", 0x5be0002a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ceq.b", "+d,+e,+h", 0x5800003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ceq.h", "+d,+e,+h", 0x5820003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ceq.w", "+d,+e,+h", 0x5840003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ceq.d", "+d,+e,+h", 0x5860003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ceqi.b", "+d,+e,+%", 0x58000039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ceqi.h", "+d,+e,+%", 0x58200039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ceqi.w", "+d,+e,+%", 0x58400039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ceqi.d", "+d,+e,+%", 0x58600039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clt_s.b", "+d,+e,+h", 0x5900003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clt_s.h", "+d,+e,+h", 0x5920003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clt_s.w", "+d,+e,+h", 0x5940003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clt_s.d", "+d,+e,+h", 0x5960003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clti_s.b", "+d,+e,+%", 0x59000039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clti_s.h", "+d,+e,+%", 0x59200039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clti_s.w", "+d,+e,+%", 0x59400039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clti_s.d", "+d,+e,+%", 0x59600039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clt_u.b", "+d,+e,+h", 0x5980003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clt_u.h", "+d,+e,+h", 0x59a0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clt_u.w", "+d,+e,+h", 0x59c0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clt_u.d", "+d,+e,+h", 0x59e0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clti_u.b", "+d,+e,+$", 0x59800039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clti_u.h", "+d,+e,+$", 0x59a00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clti_u.w", "+d,+e,+$", 0x59c00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clti_u.d", "+d,+e,+$", 0x59e00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"cle_s.b", "+d,+e,+h", 0x5a00003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"cle_s.h", "+d,+e,+h", 0x5a20003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"cle_s.w", "+d,+e,+h", 0x5a40003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"cle_s.d", "+d,+e,+h", 0x5a60003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clei_s.b", "+d,+e,+%", 0x5a000039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clei_s.h", "+d,+e,+%", 0x5a200039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clei_s.w", "+d,+e,+%", 0x5a400039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clei_s.d", "+d,+e,+%", 0x5a600039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"cle_u.b", "+d,+e,+h", 0x5a80003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"cle_u.h", "+d,+e,+h", 0x5aa0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"cle_u.w", "+d,+e,+h", 0x5ac0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"cle_u.d", "+d,+e,+h", 0x5ae0003a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clei_u.b", "+d,+e,+$", 0x5a800039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clei_u.h", "+d,+e,+$", 0x5aa00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clei_u.w", "+d,+e,+$", 0x5ac00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clei_u.d", "+d,+e,+$", 0x5ae00039, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ld.b", "+d,+T(d)", 0x58000007, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, +{"ld.h", "+d,+U(d)", 0x58000017, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, +{"ld.w", "+d,+V(d)", 0x58000027, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, +{"ld.d", "+d,+W(d)", 0x58000037, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, +{"st.b", "+d,+T(d)", 0x5800000f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, +{"st.h", "+d,+U(d)", 0x5800001f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, +{"st.w", "+d,+V(d)", 0x5800002f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, +{"st.d", "+d,+W(d)", 0x5800003f, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, +{"sat_s.b", "+d,+e,+!", 0x58700022, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"sat_s.h", "+d,+e,+@", 0x58600022, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"sat_s.w", "+d,+e,+x", 0x58400022, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"sat_s.d", "+d,+e,+#", 0x58000022, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"sat_u.b", "+d,+e,+!", 0x58f00022, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"sat_u.h", "+d,+e,+@", 0x58e00022, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"sat_u.w", "+d,+e,+x", 0x58c00022, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"sat_u.d", "+d,+e,+#", 0x58800022, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"add_a.b", "+d,+e,+h", 0x58000003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"add_a.h", "+d,+e,+h", 0x58200003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"add_a.w", "+d,+e,+h", 0x58400003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"add_a.d", "+d,+e,+h", 0x58600003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_a.b", "+d,+e,+h", 0x58800003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_a.h", "+d,+e,+h", 0x58a00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_a.w", "+d,+e,+h", 0x58c00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_a.d", "+d,+e,+h", 0x58e00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_s.b", "+d,+e,+h", 0x59000003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_s.h", "+d,+e,+h", 0x59200003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_s.w", "+d,+e,+h", 0x59400003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_s.d", "+d,+e,+h", 0x59600003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_u.b", "+d,+e,+h", 0x59800003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_u.h", "+d,+e,+h", 0x59a00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_u.w", "+d,+e,+h", 0x59c00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_u.d", "+d,+e,+h", 0x59e00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ave_s.b", "+d,+e,+h", 0x5a000003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ave_s.h", "+d,+e,+h", 0x5a200003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ave_s.w", "+d,+e,+h", 0x5a400003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ave_s.d", "+d,+e,+h", 0x5a600003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ave_u.b", "+d,+e,+h", 0x5a800003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ave_u.h", "+d,+e,+h", 0x5aa00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ave_u.w", "+d,+e,+h", 0x5ac00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ave_u.d", "+d,+e,+h", 0x5ae00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"aver_s.b", "+d,+e,+h", 0x5b000003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"aver_s.h", "+d,+e,+h", 0x5b200003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"aver_s.w", "+d,+e,+h", 0x5b400003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"aver_s.d", "+d,+e,+h", 0x5b600003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"aver_u.b", "+d,+e,+h", 0x5b800003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"aver_u.h", "+d,+e,+h", 0x5ba00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"aver_u.w", "+d,+e,+h", 0x5bc00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"aver_u.d", "+d,+e,+h", 0x5be00003, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subs_s.b", "+d,+e,+h", 0x58000013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subs_s.h", "+d,+e,+h", 0x58200013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subs_s.w", "+d,+e,+h", 0x58400013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subs_s.d", "+d,+e,+h", 0x58600013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subs_u.b", "+d,+e,+h", 0x58800013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subs_u.h", "+d,+e,+h", 0x58a00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subs_u.w", "+d,+e,+h", 0x58c00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subs_u.d", "+d,+e,+h", 0x58e00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subsus_u.b", "+d,+e,+h", 0x59000013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subsus_u.h", "+d,+e,+h", 0x59200013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subsus_u.w", "+d,+e,+h", 0x59400013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subsus_u.d", "+d,+e,+h", 0x59600013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subsuu_s.b", "+d,+e,+h", 0x59800013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subsuu_s.h", "+d,+e,+h", 0x59a00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subsuu_s.w", "+d,+e,+h", 0x59c00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subsuu_s.d", "+d,+e,+h", 0x59e00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"asub_s.b", "+d,+e,+h", 0x5a000013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"asub_s.h", "+d,+e,+h", 0x5a200013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"asub_s.w", "+d,+e,+h", 0x5a400013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"asub_s.d", "+d,+e,+h", 0x5a600013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"asub_u.b", "+d,+e,+h", 0x5a800013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"asub_u.h", "+d,+e,+h", 0x5aa00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"asub_u.w", "+d,+e,+h", 0x5ac00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"asub_u.d", "+d,+e,+h", 0x5ae00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mulv.b", "+d,+e,+h", 0x58000023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mulv.h", "+d,+e,+h", 0x58200023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mulv.w", "+d,+e,+h", 0x58400023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mulv.d", "+d,+e,+h", 0x58600023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"maddv.b", "+d,+e,+h", 0x58800023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"maddv.h", "+d,+e,+h", 0x58a00023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"maddv.w", "+d,+e,+h", 0x58c00023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"maddv.d", "+d,+e,+h", 0x58e00023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"msubv.b", "+d,+e,+h", 0x59000023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"msubv.h", "+d,+e,+h", 0x59200023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"msubv.w", "+d,+e,+h", 0x59400023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"msubv.d", "+d,+e,+h", 0x59600023, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"div_s.b", "+d,+e,+h", 0x5a000023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"div_s.h", "+d,+e,+h", 0x5a200023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"div_s.w", "+d,+e,+h", 0x5a400023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"div_s.d", "+d,+e,+h", 0x5a600023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"div_u.b", "+d,+e,+h", 0x5a800023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"div_u.h", "+d,+e,+h", 0x5aa00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"div_u.w", "+d,+e,+h", 0x5ac00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"div_u.d", "+d,+e,+h", 0x5ae00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mod_s.b", "+d,+e,+h", 0x5b000023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mod_s.h", "+d,+e,+h", 0x5b200023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mod_s.w", "+d,+e,+h", 0x5b400023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mod_s.d", "+d,+e,+h", 0x5b600023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mod_u.b", "+d,+e,+h", 0x5b800023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mod_u.h", "+d,+e,+h", 0x5ba00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mod_u.w", "+d,+e,+h", 0x5bc00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mod_u.d", "+d,+e,+h", 0x5be00023, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dotp_s.h", "+d,+e,+h", 0x58200033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dotp_s.w", "+d,+e,+h", 0x58400033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dotp_s.d", "+d,+e,+h", 0x58600033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dotp_u.h", "+d,+e,+h", 0x58a00033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dotp_u.w", "+d,+e,+h", 0x58c00033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dotp_u.d", "+d,+e,+h", 0x58e00033, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpadd_s.h", "+d,+e,+h", 0x59200033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpadd_s.w", "+d,+e,+h", 0x59400033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpadd_s.d", "+d,+e,+h", 0x59600033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpadd_u.h", "+d,+e,+h", 0x59a00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpadd_u.w", "+d,+e,+h", 0x59c00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpadd_u.d", "+d,+e,+h", 0x59e00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpsub_s.h", "+d,+e,+h", 0x5a200033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpsub_s.w", "+d,+e,+h", 0x5a400033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpsub_s.d", "+d,+e,+h", 0x5a600033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpsub_u.h", "+d,+e,+h", 0x5aa00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpsub_u.w", "+d,+e,+h", 0x5ac00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpsub_u.d", "+d,+e,+h", 0x5ae00033, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sld.b", "+d,+e+*", 0x5800000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sld.h", "+d,+e+*", 0x5820000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sld.w", "+d,+e+*", 0x5840000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sld.d", "+d,+e+*", 0x5860000b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sldi.b", "+d,+e+o", 0x58000016, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"sldi.h", "+d,+e+u", 0x58200016, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"sldi.w", "+d,+e+v", 0x58300016, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"sldi.d", "+d,+e+w", 0x58380016, 0xfffe003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"splat.b", "+d,+e+*", 0x5880000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"splat.h", "+d,+e+*", 0x58a0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"splat.w", "+d,+e+*", 0x58c0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"splat.d", "+d,+e+*", 0x58e0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"splati.b", "+d,+e+o", 0x58400016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"splati.h", "+d,+e+u", 0x58600016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"splati.w", "+d,+e+v", 0x58700016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"splati.d", "+d,+e+w", 0x58780016, 0xfffe003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"pckev.b", "+d,+e,+h", 0x5900000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"pckev.h", "+d,+e,+h", 0x5920000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"pckev.w", "+d,+e,+h", 0x5940000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"pckev.d", "+d,+e,+h", 0x5960000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"pckod.b", "+d,+e,+h", 0x5980000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"pckod.h", "+d,+e,+h", 0x59a0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"pckod.w", "+d,+e,+h", 0x59c0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"pckod.d", "+d,+e,+h", 0x59e0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvl.b", "+d,+e,+h", 0x5a00000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvl.h", "+d,+e,+h", 0x5a20000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvl.w", "+d,+e,+h", 0x5a40000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvl.d", "+d,+e,+h", 0x5a60000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvr.b", "+d,+e,+h", 0x5a80000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvr.h", "+d,+e,+h", 0x5aa0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvr.w", "+d,+e,+h", 0x5ac0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvr.d", "+d,+e,+h", 0x5ae0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvev.b", "+d,+e,+h", 0x5b00000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvev.h", "+d,+e,+h", 0x5b20000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvev.w", "+d,+e,+h", 0x5b40000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvev.d", "+d,+e,+h", 0x5b60000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvod.b", "+d,+e,+h", 0x5b80000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvod.h", "+d,+e,+h", 0x5ba0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvod.w", "+d,+e,+h", 0x5bc0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvod.d", "+d,+e,+h", 0x5be0000b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"vshf.b", "+d,+e,+h", 0x5800001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"vshf.h", "+d,+e,+h", 0x5820001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"vshf.w", "+d,+e,+h", 0x5840001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"vshf.d", "+d,+e,+h", 0x5860001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srar.b", "+d,+e,+h", 0x5880001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srar.h", "+d,+e,+h", 0x58a0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srar.w", "+d,+e,+h", 0x58c0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srar.d", "+d,+e,+h", 0x58e0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srari.b", "+d,+e,+!", 0x59700022, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srari.h", "+d,+e,+@", 0x59600022, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srari.w", "+d,+e,+x", 0x59400022, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srari.d", "+d,+e,+#", 0x59000022, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srlr.b", "+d,+e,+h", 0x5900001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srlr.h", "+d,+e,+h", 0x5920001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srlr.w", "+d,+e,+h", 0x5940001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srlr.d", "+d,+e,+h", 0x5960001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srlri.b", "+d,+e,+!", 0x59f00022, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srlri.h", "+d,+e,+@", 0x59e00022, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srlri.w", "+d,+e,+x", 0x59c00022, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srlri.d", "+d,+e,+#", 0x59800022, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"hadd_s.h", "+d,+e,+h", 0x5a20001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hadd_s.w", "+d,+e,+h", 0x5a40001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hadd_s.d", "+d,+e,+h", 0x5a60001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hadd_u.h", "+d,+e,+h", 0x5aa0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hadd_u.w", "+d,+e,+h", 0x5ac0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hadd_u.d", "+d,+e,+h", 0x5ae0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hsub_s.h", "+d,+e,+h", 0x5b20001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hsub_s.w", "+d,+e,+h", 0x5b40001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hsub_s.d", "+d,+e,+h", 0x5b60001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hsub_u.h", "+d,+e,+h", 0x5ba0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hsub_u.w", "+d,+e,+h", 0x5bc0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hsub_u.d", "+d,+e,+h", 0x5be0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"and.v", "+d,+e,+h", 0x5800002e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"andi.b", "+d,+e,+|", 0x58000001, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"or.v", "+d,+e,+h", 0x5820002e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ori.b", "+d,+e,+|", 0x59000001, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nor.v", "+d,+e,+h", 0x5840002e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"nori.b", "+d,+e,+|", 0x5a000001, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"xor.v", "+d,+e,+h", 0x5860002e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"xori.b", "+d,+e,+|", 0x5b000001, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bmnz.v", "+d,+e,+h", 0x5880002e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bmnzi.b", "+d,+e,+|", 0x58000011, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"bmz.v", "+d,+e,+h", 0x58a0002e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bmzi.b", "+d,+e,+|", 0x59000011, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"bsel.v", "+d,+e,+h", 0x58c0002e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bseli.b", "+d,+e,+|", 0x5a000011, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"shf.b", "+d,+e,+|", 0x58000021, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"shf.h", "+d,+e,+|", 0x59000021, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"shf.w", "+d,+e,+|", 0x5a000021, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bnz.v", "+h,p", 0x81e00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"bz.v", "+h,p", 0x81600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"fill.b", "+d,d", 0x5b00002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fill.h", "+d,d", 0x5b01002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fill.w", "+d,d", 0x5b02002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fill.d", "+d,d", 0x5b03002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA64, 0 }, +{"pcnt.b", "+d,+e", 0x5b04002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"pcnt.h", "+d,+e", 0x5b05002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"pcnt.w", "+d,+e", 0x5b06002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"pcnt.d", "+d,+e", 0x5b07002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nloc.b", "+d,+e", 0x5b08002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nloc.h", "+d,+e", 0x5b09002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nloc.w", "+d,+e", 0x5b0a002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nloc.d", "+d,+e", 0x5b0b002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nlzc.b", "+d,+e", 0x5b0c002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nlzc.h", "+d,+e", 0x5b0d002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nlzc.w", "+d,+e", 0x5b0e002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nlzc.d", "+d,+e", 0x5b0f002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_s.b", "+k,+e+o", 0x58800016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_s.h", "+k,+e+u", 0x58a00016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_s.w", "+k,+e+v", 0x58b00016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_s.d", "+k,+e+w", 0x58b80016, 0xfffe003f, WR_1|RD_2, 0, 0, MSA64, 0 }, +{"copy_u.b", "+k,+e+o", 0x58c00016, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_u.h", "+k,+e+u", 0x58e00016, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_u.w", "+k,+e+v", 0x58f00016, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_u.d", "+k,+e+w", 0x58f80016, 0xfffe003f, WR_1|RD_2, 0, 0, MSA64, 0 }, +{"insert.b", "+d+o,d", 0x59000016, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insert.h", "+d+u,d", 0x59200016, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insert.w", "+d+v,d", 0x59300016, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insert.d", "+d+w,d", 0x59380016, 0xfffe003f, MOD_1|RD_3, 0, 0, MSA64, 0 }, +{"insve.b", "+d+o,+e+&", 0x59400016, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insve.h", "+d+u,+e+&", 0x59600016, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insve.w", "+d+v,+e+&", 0x59700016, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insve.d", "+d+w,+e+&", 0x59780016, 0xfffe003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"bnz.b", "+h,p", 0x83800000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"bnz.h", "+h,p", 0x83a00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"bnz.w", "+h,p", 0x83c00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"bnz.d", "+h,p", 0x83e00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"bz.b", "+h,p", 0x83000000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"bz.h", "+h,p", 0x83200000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"bz.w", "+h,p", 0x83400000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"bz.d", "+h,p", 0x83600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"ldi.b", "+d,+^", 0x5b000039, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, +{"ldi.h", "+d,+^", 0x5b200039, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, +{"ldi.w", "+d,+^", 0x5b400039, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, +{"ldi.d", "+d,+^", 0x5b600039, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, +{"fcaf.w", "+d,+e,+h", 0x58000026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcaf.d", "+d,+e,+h", 0x58200026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcun.w", "+d,+e,+h", 0x58400026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcun.d", "+d,+e,+h", 0x58600026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fceq.w", "+d,+e,+h", 0x58800026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fceq.d", "+d,+e,+h", 0x58a00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcueq.w", "+d,+e,+h", 0x58c00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcueq.d", "+d,+e,+h", 0x58e00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fclt.w", "+d,+e,+h", 0x59000026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fclt.d", "+d,+e,+h", 0x59200026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcult.w", "+d,+e,+h", 0x59400026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcult.d", "+d,+e,+h", 0x59600026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcle.w", "+d,+e,+h", 0x59800026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcle.d", "+d,+e,+h", 0x59a00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcule.w", "+d,+e,+h", 0x59c00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcule.d", "+d,+e,+h", 0x59e00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsaf.w", "+d,+e,+h", 0x5a000026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsaf.d", "+d,+e,+h", 0x5a200026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsun.w", "+d,+e,+h", 0x5a400026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsun.d", "+d,+e,+h", 0x5a600026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fseq.w", "+d,+e,+h", 0x5a800026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fseq.d", "+d,+e,+h", 0x5aa00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsueq.w", "+d,+e,+h", 0x5ac00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsueq.d", "+d,+e,+h", 0x5ae00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fslt.w", "+d,+e,+h", 0x5b000026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fslt.d", "+d,+e,+h", 0x5b200026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsult.w", "+d,+e,+h", 0x5b400026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsult.d", "+d,+e,+h", 0x5b600026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsle.w", "+d,+e,+h", 0x5b800026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsle.d", "+d,+e,+h", 0x5ba00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsule.w", "+d,+e,+h", 0x5bc00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsule.d", "+d,+e,+h", 0x5be00026, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fadd.w", "+d,+e,+h", 0x58000036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fadd.d", "+d,+e,+h", 0x58200036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsub.w", "+d,+e,+h", 0x58400036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsub.d", "+d,+e,+h", 0x58600036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmul.w", "+d,+e,+h", 0x58800036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmul.d", "+d,+e,+h", 0x58a00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fdiv.w", "+d,+e,+h", 0x58c00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fdiv.d", "+d,+e,+h", 0x58e00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmadd.w", "+d,+e,+h", 0x59000036, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmadd.d", "+d,+e,+h", 0x59200036, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmsub.w", "+d,+e,+h", 0x59400036, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmsub.d", "+d,+e,+h", 0x59600036, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fexp2.w", "+d,+e,+h", 0x59c00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fexp2.d", "+d,+e,+h", 0x59e00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fexdo.h", "+d,+e,+h", 0x5a000036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fexdo.w", "+d,+e,+h", 0x5a200036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ftq.h", "+d,+e,+h", 0x5a800036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ftq.w", "+d,+e,+h", 0x5aa00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmin.w", "+d,+e,+h", 0x5b000036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmin.d", "+d,+e,+h", 0x5b200036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmin_a.w", "+d,+e,+h", 0x5b400036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmin_a.d", "+d,+e,+h", 0x5b600036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmax.w", "+d,+e,+h", 0x5b800036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmax.d", "+d,+e,+h", 0x5ba00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmax_a.w", "+d,+e,+h", 0x5bc00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmax_a.d", "+d,+e,+h", 0x5be00036, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcor.w", "+d,+e,+h", 0x5840000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcor.d", "+d,+e,+h", 0x5860000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcune.w", "+d,+e,+h", 0x5880000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcune.d", "+d,+e,+h", 0x58a0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcne.w", "+d,+e,+h", 0x58c0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcne.d", "+d,+e,+h", 0x58e0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mul_q.h", "+d,+e,+h", 0x5900000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mul_q.w", "+d,+e,+h", 0x5920000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"madd_q.h", "+d,+e,+h", 0x5940000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"madd_q.w", "+d,+e,+h", 0x5960000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"msub_q.h", "+d,+e,+h", 0x5980000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"msub_q.w", "+d,+e,+h", 0x59a0000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsor.w", "+d,+e,+h", 0x5a40000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsor.d", "+d,+e,+h", 0x5a60000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsune.w", "+d,+e,+h", 0x5a80000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsune.d", "+d,+e,+h", 0x5aa0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsne.w", "+d,+e,+h", 0x5ac0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsne.d", "+d,+e,+h", 0x5ae0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mulr_q.h", "+d,+e,+h", 0x5b00000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mulr_q.w", "+d,+e,+h", 0x5b20000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"maddr_q.h", "+d,+e,+h", 0x5b40000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"maddr_q.w", "+d,+e,+h", 0x5b60000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"msubr_q.h", "+d,+e,+h", 0x5b80000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"msubr_q.w", "+d,+e,+h", 0x5ba0000e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fclass.w", "+d,+e", 0x5b20002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fclass.d", "+d,+e", 0x5b21002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ftrunc_s.w", "+d,+e", 0x5b22002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ftrunc_s.d", "+d,+e", 0x5b23002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ftrunc_u.w", "+d,+e", 0x5b24002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ftrunc_u.d", "+d,+e", 0x5b25002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fsqrt.w", "+d,+e", 0x5b26002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fsqrt.d", "+d,+e", 0x5b27002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"frsqrt.w", "+d,+e", 0x5b28002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"frsqrt.d", "+d,+e", 0x5b29002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"frcp.w", "+d,+e", 0x5b2a002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"frcp.d", "+d,+e", 0x5b2b002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"frint.w", "+d,+e", 0x5b2c002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"frint.d", "+d,+e", 0x5b2d002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"flog2.w", "+d,+e", 0x5b2e002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"flog2.d", "+d,+e", 0x5b2f002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fexupl.w", "+d,+e", 0x5b30002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fexupl.d", "+d,+e", 0x5b31002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fexupr.w", "+d,+e", 0x5b32002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fexupr.d", "+d,+e", 0x5b33002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ffql.w", "+d,+e", 0x5b34002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ffql.d", "+d,+e", 0x5b35002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ffqr.w", "+d,+e", 0x5b36002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ffqr.d", "+d,+e", 0x5b37002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ftint_s.w", "+d,+e", 0x5b38002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ftint_s.d", "+d,+e", 0x5b39002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ftint_u.w", "+d,+e", 0x5b3a002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ftint_u.d", "+d,+e", 0x5b3b002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ffint_s.w", "+d,+e", 0x5b3c002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ffint_s.d", "+d,+e", 0x5b3d002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ffint_u.w", "+d,+e", 0x5b3e002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ffint_u.d", "+d,+e", 0x5b3f002e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ctcmsa", "+l,d", 0x583e0016, 0xffff003f, RD_2, 0, 0, MSA, 0 }, +{"cfcmsa", "+k,+n", 0x587e0016, 0xffff003f, WR_1, 0, 0, MSA, 0 }, +{"move.v", "+d,+e", 0x58be0016, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"lsa", "d,v,t,+~", 0x00000020, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dlsa", "d,v,t,+~", 0x58000020, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA64, 0 }, }; const int bfd_micromips_num_opcodes = diff --git a/binutils-2.24/opcodes/mips-dis.c b/binutils-2.24/opcodes/mips-dis.c index dce4d86..fdc97ff 100644 --- a/binutils-2.24/opcodes/mips-dis.c +++ b/binutils-2.24/opcodes/mips-dis.c @@ -115,6 +115,14 @@ static const char * const mips_cp0_names_numeric[32] = "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" }; +static const char * const mips_cp1_names_numeric[32] = +{ + "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", + "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" +}; + static const char * const mips_cp0_names_r3000[32] = { "c0_index", "c0_random", "c0_entrylo", "$3", @@ -175,6 +183,18 @@ static const char * const mips_cp0_names_mips3264[32] = "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", }; +static const char * const mips_cp1_names_mips3264[32] = +{ + "c1_fir", "c1_ufr", "$2", "$3", + "c1_unfr", "$5", "$6", "$7", + "$8", "$9", "$10", "$11", + "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", + "$20", "$21", "$22", "$23", + "$24", "c1_fccr", "c1_fexr", "$27", + "c1_fenr", "$29", "$30", "c1_fcsr" +}; + static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] = { { 16, 1, "c0_config1" }, @@ -401,6 +421,15 @@ static const char * const mips_hwr_names_mips3264r2[32] = "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" }; +static const char * const msa_control_names[32] = +{ + "msa_ir", "msa_csr", "msa_access", "msa_save", + "msa_modify", "msa_request", "msa_map", "msa_unmap", + "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" +}; + struct mips_abi_choice { const char * name; @@ -427,62 +456,88 @@ struct mips_arch_choice const char * const *cp0_names; const struct mips_cp0sel_name *cp0sel_names; unsigned int cp0sel_names_len; + const char * const *cp1_names; const char * const *hwr_names; }; const struct mips_arch_choice mips_arch_choices[] = { { "numeric", 0, 0, 0, 0, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, 0, - mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_r3000, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, 0, - mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, 0, - mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_r4000, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r5900", 1, bfd_mach_mips5900, CPU_R5900, ISA_MIPS3, 0, - mips_cp0_names_r5900, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_r5900, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r14000", 1, bfd_mach_mips14000, CPU_R14000, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "r16000", 1, bfd_mach_mips16000, CPU_R16000, ISA_MIPS4, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. Note that MIPS-3D and MDMX are not applicable to MIPS32. (See @@ -493,66 +548,113 @@ const struct mips_arch_choice mips_arch_choices[] = ISA_MIPS32, ASE_SMARTMIPS, mips_cp0_names_mips3264, mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), - mips_hwr_names_numeric }, + mips_cp1_names_mips3264, mips_hwr_names_numeric }, { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, ISA_MIPS32R2, (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D - | ASE_MT | ASE_MCU | ASE_VIRT), + | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips32r3", 1, bfd_mach_mipsisa32r3, CPU_MIPS32R3, + ISA_MIPS32R3, + (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D + | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips32r5", 1, bfd_mach_mipsisa32r5, CPU_MIPS32R5, + ISA_MIPS32R5, + (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D + | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), - mips_hwr_names_mips3264r2 }, + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6, + ISA_MIPS32R6, + (ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, ISA_MIPS64, ASE_MIPS3D | ASE_MDMX, mips_cp0_names_mips3264, mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), - mips_hwr_names_numeric }, + mips_cp1_names_mips3264, mips_hwr_names_numeric }, { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, ISA_MIPS64R2, (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT - | ASE_MDMX | ASE_MCU | ASE_VIRT | ASE_VIRT64), + | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips64r3", 1, bfd_mach_mipsisa64r3, CPU_MIPS64R3, + ISA_MIPS64R3, + (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT + | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips64r5", 1, bfd_mach_mipsisa64r5, CPU_MIPS64R5, + ISA_MIPS64R5, + (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT + | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips64r6", 1, bfd_mach_mipsisa64r6, CPU_MIPS64R6, + ISA_MIPS64R6, + (ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64 + | ASE_MCU | ASE_MT), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), - mips_hwr_names_mips3264r2 }, + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, ISA_MIPS64 | INSN_SB1, ASE_MIPS3D, mips_cp0_names_sb1, mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), - mips_hwr_names_numeric }, + mips_cp1_names_mips3264, mips_hwr_names_numeric }, { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E, ISA_MIPS3 | INSN_LOONGSON_2E, 0, mips_cp0_names_numeric, - NULL, 0, mips_hwr_names_numeric }, + NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F, ISA_MIPS3 | INSN_LOONGSON_2F, 0, mips_cp0_names_numeric, - NULL, 0, mips_hwr_names_numeric }, + NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A, - ISA_MIPS64 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric, - NULL, 0, mips_hwr_names_numeric }, + ISA_MIPS64R2 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric, + NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON, ISA_MIPS64R2 | INSN_OCTEON, 0, mips_cp0_names_numeric, NULL, 0, - mips_hwr_names_numeric }, + mips_cp1_names_mips3264, mips_hwr_names_numeric }, { "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP, ISA_MIPS64R2 | INSN_OCTEONP, 0, mips_cp0_names_numeric, - NULL, 0, mips_hwr_names_numeric }, + NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, { "octeon2", 1, bfd_mach_mips_octeon2, CPU_OCTEON2, ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric, - NULL, 0, mips_hwr_names_numeric }, + NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR, ISA_MIPS64 | INSN_XLR, 0, mips_cp0_names_xlr, mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), - mips_hwr_names_numeric }, + mips_cp1_names_mips3264, mips_hwr_names_numeric }, /* XLP is mostly like XLR, with the prominent exception it is being MIPS64R2. */ @@ -560,12 +662,13 @@ const struct mips_arch_choice mips_arch_choices[] = ISA_MIPS64R2 | INSN_XLR, 0, mips_cp0_names_xlr, mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr), - mips_hwr_names_numeric }, + mips_cp1_names_mips3264, mips_hwr_names_numeric }, /* This entry, mips16, is here only for ISA/processor selection; do not print its name. */ { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, 0, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, + mips_hwr_names_numeric }, }; /* ISA and processor type to disassemble for, and register names to use. @@ -580,6 +683,7 @@ static const char * const *mips_fpr_names; static const char * const *mips_cp0_names; static const struct mips_cp0sel_name *mips_cp0sel_names; static int mips_cp0sel_names_len; +static const char * const *mips_cp1_names; static const char * const *mips_hwr_names; /* Other options */ @@ -685,6 +789,7 @@ set_default_mips_dis_options (struct disassemble_info *info) mips_cp0_names = mips_cp0_names_numeric; mips_cp0sel_names = NULL; mips_cp0sel_names_len = 0; + mips_cp1_names = mips_cp1_names_numeric; mips_hwr_names = mips_hwr_names_numeric; no_aliases = 0; @@ -718,6 +823,7 @@ set_default_mips_dis_options (struct disassemble_info *info) mips_cp0_names = chosen_arch->cp0_names; mips_cp0sel_names = chosen_arch->cp0sel_names; mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; + mips_cp1_names = chosen_arch->cp1_names; mips_hwr_names = chosen_arch->hwr_names; } #endif @@ -738,13 +844,34 @@ parse_mips_dis_option (const char *option, unsigned int len) return; } + if (CONST_STRNEQ (option, "msa")) + { + mips_ase |= ASE_MSA; + if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2 + || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R3 + || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R5 + || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6) + mips_ase |= ASE_MSA64; + return; + } + if (CONST_STRNEQ (option, "virt")) { mips_ase |= ASE_VIRT; - if (mips_isa & ISA_MIPS64R2) + if (mips_isa & ISA_MIPS64R2 + || mips_isa & ISA_MIPS64R3 + || mips_isa & ISA_MIPS64R5 + || mips_isa & ISA_MIPS64R6) mips_ase |= ASE_VIRT64; return; } + + if (CONST_STRNEQ (option, "xpa")) + { + mips_ase |= ASE_XPA; + return; + } + /* Look for the = that delimits the end of the option name. */ for (i = 0; i < len; i++) @@ -793,6 +920,15 @@ parse_mips_dis_option (const char *option, unsigned int len) return; } + if (strncmp ("cp1-names", option, optionlen) == 0 + && strlen ("cp1-names") == optionlen) + { + chosen_arch = choose_arch_by_name (val, vallen); + if (chosen_arch != NULL) + mips_cp1_names = chosen_arch->cp1_names; + return; + } + if (strncmp ("hwr-names", option, optionlen) == 0 && strlen ("hwr-names") == optionlen) { @@ -821,6 +957,7 @@ parse_mips_dis_option (const char *option, unsigned int len) mips_cp0_names = chosen_arch->cp0_names; mips_cp0sel_names = chosen_arch->cp0sel_names; mips_cp0sel_names_len = chosen_arch->cp0sel_names_len; + mips_cp1_names = chosen_arch->cp1_names; mips_hwr_names = chosen_arch->hwr_names; } return; @@ -910,6 +1047,8 @@ print_reg (struct disassemble_info *info, const struct mips_opcode *opcode, case OP_REG_COPRO: if (opcode->name[strlen (opcode->name) - 1] == '0') info->fprintf_func (info->stream, "%s", mips_cp0_names[regno]); + else if (opcode->name[strlen (opcode->name) - 1] == '1') + info->fprintf_func (info->stream, "%s", mips_cp1_names[regno]); else info->fprintf_func (info->stream, "$%d", regno); break; @@ -941,6 +1080,15 @@ print_reg (struct disassemble_info *info, const struct mips_opcode *opcode, case OP_REG_R5900_ACC: info->fprintf_func (info->stream, "$ACC"); break; + + case OP_REG_MSA: + info->fprintf_func (info->stream, "$w%d", regno); + break; + + case OP_REG_MSA_CTRL: + info->fprintf_func (info->stream, "%s", msa_control_names[regno]); + break; + } } @@ -955,6 +1103,8 @@ struct mips_print_arg_state { OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG. */ enum mips_reg_operand_type last_reg_type; unsigned int last_regno; + unsigned int dest_regno; + unsigned int seen_dest; }; /* Initialize STATE for the start of an instruction. */ @@ -984,11 +1134,28 @@ print_vu0_channel (struct disassemble_info *info, abort (); } +/* Record information about a register operand */ + +static void +mips_seen_register (struct mips_print_arg_state *state, + unsigned int regno, + enum mips_reg_operand_type reg_type) +{ + state->last_reg_type = reg_type; + state->last_regno = regno; + + if (!state->seen_dest) + { + state->seen_dest = 1; + state->dest_regno = regno; + } +} + /* Print operand OPERAND of OPCODE, using STATE to track inter-operand state. UVAL is the encoding of the operand (shifted into bit 0) and BASE_PC is the base address for OP_PCREL operands. */ -static void +static bfd_boolean print_insn_arg (struct disassemble_info *info, struct mips_print_arg_state *state, const struct mips_opcode *opcode, @@ -1050,8 +1217,7 @@ print_insn_arg (struct disassemble_info *info, uval = mips_decode_reg_operand (reg_op, uval); print_reg (info, opcode, reg_op->reg_type, uval); - state->last_reg_type = reg_op->reg_type; - state->last_regno = uval; + mips_seen_register (state, uval, reg_op->reg_type); } break; @@ -1117,6 +1283,40 @@ print_insn_arg (struct disassemble_info *info, } break; + case OP_SAME_RS_RT: + { + unsigned int reg1, reg2; + + reg1 = uval & 31; + reg2 = uval >> 5; + + if (reg1 == reg2 && reg1 != 0) + infprintf (is, "%s", mips_gpr_names[reg1]); + else + return FALSE; + } + break; + + case OP_CHECK_PREV: + { + const struct mips_check_prev_operand *prev_op; + + prev_op = (const struct mips_check_prev_operand *) operand; + + if ((prev_op->check_not_zero && uval == 0) + || (prev_op->check_not_equal && uval == state->last_regno) + || (prev_op->check_greater_than_or_equal && uval < state->last_regno) + || (prev_op->check_less_than_or_equal && uval > state->last_regno) + || (prev_op->check_less_than && uval >= state->last_regno) + || (prev_op->check_greater_than && uval <= state->last_regno)) + return FALSE; + else + infprintf (is, "%s", mips_gpr_names[uval]); + + mips_seen_register (state, uval, OP_REG_GP); + } + break; + case OP_LWM_SWM_LIST: if (operand->size == 2) { @@ -1239,8 +1439,7 @@ print_insn_arg (struct disassemble_info *info, break; case OP_REPEAT_DEST_REG: - /* Should always match OP_REPEAT_PREV_REG first. */ - abort (); + print_reg (info, opcode, state->last_reg_type, state->dest_regno); case OP_PC: infprintf (is, "$pc"); @@ -1250,18 +1449,31 @@ print_insn_arg (struct disassemble_info *info, case OP_VU0_MATCH_SUFFIX: print_vu0_channel (info, operand, uval); break; + + case OP_IMM_INDEX: + infprintf (is, "[%d]", uval); + break; + + case OP_REG_INDEX: + infprintf (is, "["); + print_reg (info, opcode, OP_REG_GP, uval); + infprintf (is, "]"); + break; } + + return TRUE; } /* Print the arguments for INSN, which is described by OPCODE. Use DECODE_OPERAND to get the encoding of each operand. Use BASE_PC - as the base of OP_PCREL operands. */ + as the base of OP_PCREL operands, adjusting by LENGTH if the OP_PCREL + operand is for a branch or jump. */ -static void +static bfd_boolean print_insn_args (struct disassemble_info *info, const struct mips_opcode *opcode, const struct mips_operand *(*decode_operand) (const char *), - unsigned int insn, bfd_vma base_pc) + unsigned int insn, bfd_vma insn_pc, unsigned int length) { const fprintf_ftype infprintf = info->fprintf_func; void *is = info->stream; @@ -1293,7 +1505,7 @@ print_insn_args (struct disassemble_info *info, infprintf (is, _("# internal error, undefined operand in `%s %s'"), opcode->name, opcode->args); - return; + return TRUE; } if (operand->type == OP_REG && s[1] == ',' @@ -1323,15 +1535,65 @@ print_insn_args (struct disassemble_info *info, infprintf (is, "$%d,%d", reg, sel); } else - print_insn_arg (info, &state, opcode, operand, base_pc, - mips_extract_operand (operand, insn)); - if (*s == 'm' || *s == '+') + { + bfd_vma base_pc = insn_pc; + + /* Adjust the PC relative base so that branch/jump insns use + the following PC as the base but genuinely PC relative + operands use the current PC. */ + if (operand->type == OP_PCREL) + { + const struct mips_pcrel_operand *pcrel_op; + + pcrel_op = (const struct mips_pcrel_operand *) operand; + /* The include_isa_bit flag is sufficient to distinguish + branch/jump from other PC relative operands. */ + if (pcrel_op->include_isa_bit) + base_pc += length; + } + + if (!print_insn_arg (info, &state, opcode, operand, base_pc, + mips_extract_operand (operand, insn))) + return FALSE; + + } + if (*s == 'm' || *s == '+' || *s == '-') ++s; break; } } + return TRUE; } + +#define DIS_BUF_SIZE 1000 + +/* line_dis_buf is written to by fprintf_dis_buf, and line_dis_ptr + records where in the array to write to. */ +static char line_dis_buf[DIS_BUF_SIZE]; +static char *line_dis_ptr; + +/* Fake a fprintf call by appending the string created from FORMAT to + the disassembly buffer (line_dis_buf) rather than to outputting it + to FILE. + This function is used by the print_insn_* functions to verify that + all the arguments to an instruction are valid before outputting its + disassembly. */ +static int +fprintf_dis_buf (void * file ATTRIBUTE_UNUSED, const char* format, ...) +{ + int chars; + va_list ap; + va_start (ap, format); + chars = vsnprintf (line_dis_ptr, + DIS_BUF_SIZE - (line_dis_ptr - line_dis_buf), format, ap); + line_dis_ptr += chars; + va_end (ap); + return chars; +} + +#undef DIS_BUF_SIZE + /* Print the mips instruction at address MEMADDR in debugged memory, on using INFO. Returns length of the instruction, in bytes, which is always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if @@ -1345,7 +1607,8 @@ print_insn_mips (bfd_vma memaddr, #define GET_OP(insn, field) \ (((insn) >> OP_SH_##field) & OP_MASK_##field) static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; - const fprintf_ftype infprintf = info->fprintf_func; + fprintf_ftype infprintf = info->fprintf_func; + const fprintf_ftype infprintf_prev = info->fprintf_func; const struct mips_opcode *op; static bfd_boolean init = 0; void *is = info->stream; @@ -1382,18 +1645,27 @@ print_insn_mips (bfd_vma memaddr, info->target = 0; info->target2 = 0; + /* Switch over to use the fprintf function that writes to the + disassembled buffer. */ + info->fprintf_func = fprintf_dis_buf; + infprintf = fprintf_dis_buf; + op = mips_hash[GET_OP (word, OP)]; if (op != NULL) { for (; op < &mips_opcodes[NUMOPCODES]; op++) { + line_dis_ptr = line_dis_buf; + *line_dis_ptr = '\0'; if (op->pinfo != INSN_MACRO && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) && (word & op->mask) == op->match) { - /* We always allow to disassemble the jalx instruction. */ + /* We always disassemble the jalx instruction, except for MIPS r6. */ if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor) - && strcmp (op->name, "jalx")) + && (strcmp (op->name, "jalx") + || (mips_isa & INSN_ISA_MASK) == ISA_MIPS32R6 + || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6)) continue; /* Figure out instruction type and branch delay information. */ @@ -1415,7 +1687,7 @@ print_insn_mips (bfd_vma memaddr, info->branch_delay_insns = 1; } else if ((op->pinfo & (INSN_STORE_MEMORY - | INSN_LOAD_MEMORY_DELAY)) != 0) + | INSN_LOAD_MEMORY)) != 0) info->insn_type = dis_dref; infprintf (is, "%s", op->name); @@ -1431,10 +1703,15 @@ print_insn_mips (bfd_vma memaddr, if (op->args[0]) { infprintf (is, "\t"); - print_insn_args (info, op, decode_mips_operand, word, - memaddr + 4); + if (!print_insn_args (info, op, decode_mips_operand, word, + memaddr, 4)) + continue; } + /* Restore the original fprintf function and use it to write + out the disassembled buffer. */ + info->fprintf_func = infprintf_prev; + info->fprintf_func (is, "%s", line_dis_buf); return INSNLEN; } } @@ -1442,14 +1719,16 @@ print_insn_mips (bfd_vma memaddr, #undef GET_OP /* Handle undefined instructions. */ + /* Restore the original fprintf function. */ + info->fprintf_func = infprintf_prev; info->insn_type = dis_noninsn; - infprintf (is, "0x%x", word); + info->fprintf_func (is, "0x%x", word); return INSNLEN; } /* Disassemble an operand for a mips16 instruction. */ -static void +static bfd_boolean print_mips16_insn_arg (struct disassemble_info *info, struct mips_print_arg_state *state, const struct mips_opcode *opcode, @@ -1462,6 +1741,7 @@ print_mips16_insn_arg (struct disassemble_info *info, const struct mips_operand *operand, *ext_operand; unsigned int uval; bfd_vma baseaddr; + bfd_boolean result = TRUE; if (!use_extend) extend = 0; @@ -1481,7 +1761,7 @@ print_mips16_insn_arg (struct disassemble_info *info, /* xgettext:c-format */ infprintf (is, _("# internal error, undefined operand in `%s %s'"), opcode->name, opcode->args); - return; + return TRUE; } if (operand->type == OP_SAVE_RESTORE_LIST) @@ -1625,9 +1905,10 @@ print_mips16_insn_arg (struct disassemble_info *info, } } - print_insn_arg (info, state, opcode, operand, baseaddr + 1, uval); + result = print_insn_arg (info, state, opcode, operand, baseaddr + 1, uval); break; } + return result; } @@ -1652,7 +1933,8 @@ is_mips16_plt_tail (struct disassemble_info *info, bfd_vma addr) static int print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) { - const fprintf_ftype infprintf = info->fprintf_func; + fprintf_ftype infprintf = info->fprintf_func; + const fprintf_ftype infprintf_prev = info->fprintf_func; int status; bfd_byte buffer[4]; int length; @@ -1742,11 +2024,19 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) length += 2; } + + /* Switch over to use the fprintf function that writes to the + disassembled buffer. */ + info->fprintf_func = fprintf_dis_buf; + infprintf = fprintf_dis_buf; + /* FIXME: Should probably use a hash table on the major opcode here. */ opend = mips16_opcodes + bfd_mips16_num_opcodes; for (op = mips16_opcodes; op < opend; op++) { + line_dis_ptr = line_dis_buf; + *line_dis_ptr = '\0'; if (op->pinfo != INSN_MACRO && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) && (insn & op->mask) == op->match) @@ -1784,6 +2074,7 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) infprintf (is, "\t"); init_print_arg_state (&state); + bfd_boolean args_ok = TRUE; for (s = op->args; *s != '\0'; s++) { if (*s == ',' @@ -1802,9 +2093,15 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) ++s; continue; } - print_mips16_insn_arg (info, &state, op, *s, memaddr, insn, - use_extend, extend, s[1] == '('); + if (!print_mips16_insn_arg (info, &state, op, *s, memaddr, insn, + use_extend, extend, s[1] == '(')) + { + args_ok = FALSE; + break; + } } + if (!args_ok) + continue; /* Figure out branch instruction type and delay slot information. */ if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) @@ -1820,11 +2117,18 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) else if ((op->pinfo2 & INSN2_COND_BRANCH) != 0) info->insn_type = dis_condbranch; + /* Restore the original fprintf function and use it to write + out the disassembled buffer. */ + info->fprintf_func = infprintf_prev; + info->fprintf_func (is, "%s", line_dis_buf); return length; } } #undef GET_OP + /* Restore the original fprintf function. */ + info->fprintf_func = infprintf_prev; + infprintf = infprintf_prev; if (use_extend) infprintf (is, "0x%x", extend | 0xf000); infprintf (is, "0x%x", insn); @@ -1838,7 +2142,8 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) static int print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) { - const fprintf_ftype infprintf = info->fprintf_func; + fprintf_ftype infprintf = info->fprintf_func; + const fprintf_ftype infprintf_prev = info->fprintf_func; const struct mips_opcode *op, *opend; void *is = info->stream; bfd_byte buffer[2]; @@ -1927,11 +2232,19 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) length += 2; } + + /* Switch over to use the fprintf function that writes to the + disassembled buffer. */ + info->fprintf_func = fprintf_dis_buf; + infprintf = fprintf_dis_buf; + /* FIXME: Should probably use a hash table on the major opcode here. */ opend = micromips_opcodes + bfd_micromips_num_opcodes; for (op = micromips_opcodes; op < opend; op++) { + line_dis_ptr = line_dis_buf; + *line_dis_ptr = '\0'; if (op->pinfo != INSN_MACRO && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) && (insn & op->mask) == op->match @@ -1943,8 +2256,9 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) if (op->args[0]) { infprintf (is, "\t"); - print_insn_args (info, op, decode_micromips_operand, insn, - memaddr + length + 1); + if (!print_insn_args (info, op, decode_micromips_operand, insn, + memaddr + 1, length)) + continue; } /* Figure out instruction type and branch delay information. */ @@ -1968,14 +2282,20 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) info->insn_type = dis_condbranch; } else if ((op->pinfo - & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY_DELAY)) != 0) + & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY)) != 0) info->insn_type = dis_dref; + /* Restore the original fprintf function and use it to write + out the disassembled buffer. */ + info->fprintf_func = infprintf_prev; + info->fprintf_func (is, "%s", line_dis_buf); return length; } } - infprintf (is, "0x%x", insn); + /* Restore the original fprintf function. */ + info->fprintf_func = infprintf_prev; + info->fprintf_func (is, "0x%x", insn); info->insn_type = dis_noninsn; return length; @@ -2094,9 +2414,15 @@ The following MIPS specific disassembler options are supported for use\n\ with the -M switch (multiple options should be separated by commas):\n")); fprintf (stream, _("\n\ + msa Recognize MSA instructions.\n")); + + fprintf (stream, _("\n\ virt Recognize the virtualization ASE instructions.\n")); fprintf (stream, _("\n\ + xpa Recognize the eXtended Physical Address (XPA) ASE instructions.\n")); + + fprintf (stream, _("\n\ gpr-names=ABI Print GPR names according to specified ABI.\n\ Default: based on binary being disassembled.\n")); diff --git a/binutils-2.24/opcodes/mips-formats.h b/binutils-2.24/opcodes/mips-formats.h index 4b5aaaf..fc580d8 100644 --- a/binutils-2.24/opcodes/mips-formats.h +++ b/binutils-2.24/opcodes/mips-formats.h @@ -134,3 +134,11 @@ static const struct mips_operand op = { OP_##TYPE, SIZE, LSB }; \ return &op; \ } + +#define PREV_CHECK(SIZE, LSB, LT, GT, LE, GE, NEQ, NOT_ZERO) \ + { \ + static const struct mips_check_prev_operand op = { \ + { OP_CHECK_PREV, SIZE, LSB }, LT, GT, LE, GE, NEQ, NOT_ZERO \ + }; \ + return &op.root; \ + } diff --git a/binutils-2.24/opcodes/mips-opc.c b/binutils-2.24/opcodes/mips-opc.c index 6bdf60c..d1e7fb9 100644 --- a/binutils-2.24/opcodes/mips-opc.c +++ b/binutils-2.24/opcodes/mips-opc.c @@ -42,6 +42,24 @@ decode_mips_operand (const char *p) { switch (p[0]) { + case '-': + switch (p[1]) + { + case 'a': INT_ADJ (19, 0, 262143, 2, FALSE); + case 'b': INT_ADJ (18, 0, 131071, 3, FALSE); + case 'd': SPECIAL (0, 0, REPEAT_DEST_REG); + case 's': PREV_CHECK (5, 21, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE); + case 't': PREV_CHECK (5, 16, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE); + case 'u': PREV_CHECK (5, 16, FALSE, TRUE, FALSE, FALSE, FALSE, FALSE); + case 'v': PREV_CHECK (5, 16, FALSE, FALSE, FALSE, FALSE, TRUE, TRUE); + case 'w': PREV_CHECK (5, 16, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE); + case 'x': PREV_CHECK (5, 21, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE); + case 'y': PREV_CHECK (5, 21, TRUE, FALSE, FALSE, FALSE, FALSE, TRUE); + case 'A': PCREL (19, 0, TRUE, 2, 2, FALSE, FALSE); + case 'B': PCREL (18, 0, TRUE, 3, 3, FALSE, FALSE); + } + break; + case '+': switch (p[1]) { @@ -63,33 +81,65 @@ decode_mips_operand (const char *p) case 'F': MSB (5, 11, 33, TRUE, 64); /* (33 .. 64), 64-bit op */ case 'G': MSB (5, 11, 33, FALSE, 64); /* (33 .. 64), 64-bit op */ case 'H': MSB (5, 11, 1, FALSE, 64); /* (1 .. 32), 64-bit op */ + case 'I': UINT (2, 6); case 'J': HINT (10, 11); case 'K': SPECIAL (4, 21, VU0_MATCH_SUFFIX); case 'L': SPECIAL (2, 21, VU0_SUFFIX); case 'M': SPECIAL (2, 23, VU0_SUFFIX); case 'N': SPECIAL (2, 0, VU0_MATCH_SUFFIX); + case 'O': UINT (3, 6); case 'P': BIT (5, 6, 32); /* (32 .. 63) */ case 'Q': SINT (10, 6); + case 'R': SPECIAL (0, 0, PC); case 'S': MSB (5, 11, 0, FALSE, 63); /* (0 .. 31), 64-bit op */ + case 'T': INT_ADJ (10, 16, 511, 0, FALSE); /* (-512 .. 511) << 0 */ + case 'U': INT_ADJ (10, 16, 511, 1, FALSE); /* (-512 .. 511) << 1 */ + case 'V': INT_ADJ (10, 16, 511, 2, FALSE); /* (-512 .. 511) << 2 */ + case 'W': INT_ADJ (10, 16, 511, 3, FALSE); /* (-512 .. 511) << 3 */ case 'X': BIT (5, 16, 32); /* (32 .. 63) */ case 'Z': REG (5, 0, FP); case 'a': SINT (8, 6); case 'b': SINT (8, 3); case 'c': INT_ADJ (9, 6, 255, 4, FALSE); /* (-256 .. 255) << 4 */ + case 'd': REG (5, 6, MSA); + case 'e': REG (5, 11, MSA); case 'f': INT_ADJ (15, 6, 32767, 3, TRUE); case 'g': SINT (5, 6); + case 'h': REG (5, 16, MSA); case 'i': JALX (26, 0, 2); case 'j': SINT (9, 7); + case 'k': REG (5, 6, GP); + case 'l': REG (5, 6, MSA_CTRL); case 'm': REG (0, 0, R5900_ACC); + case 'n': REG (5, 11, MSA_CTRL); + case 'o': SPECIAL (4, 16, IMM_INDEX); case 'p': BIT (5, 6, 0); /* (0 .. 31), 32-bit op */ case 'q': REG (0, 0, R5900_Q); case 'r': REG (0, 0, R5900_R); case 's': MSB (5, 11, 0, FALSE, 31); /* (0 .. 31) */ case 't': REG (5, 16, COPRO); + case 'u': SPECIAL (3, 16, IMM_INDEX); + case 'v': SPECIAL (2, 16, IMM_INDEX); + case 'w': SPECIAL (1, 16, IMM_INDEX); case 'x': BIT (5, 16, 0); /* (0 .. 31) */ case 'y': REG (0, 0, R5900_I); case 'z': REG (5, 0, GP); + + case '~': BIT (2, 6, 1); /* (1 .. 4) */ + case '!': BIT (3, 16, 0); /* (0 .. 7) */ + case '@': BIT (4, 16, 0); /* (0 .. 15) */ + case '#': BIT (6, 16, 0); /* (0 .. 63) */ + case '$': UINT (5, 16); /* (0 .. 31) */ + case '%': SINT (5, 16); /* (-16 .. 15) */ + case '^': SINT (10, 11); /* (-512 .. 511) */ + case '&': SPECIAL (0, 0, IMM_INDEX); + case '*': SPECIAL (5, 16, REG_INDEX); + case '|': BIT (8, 16, 0); /* (0 .. 255) */ + case ':': SINT (11, 0); + case '\'': BRANCH (26, 0, 2); + case '"': BRANCH (21, 0, 2); + case ';': SPECIAL (10, 16, SAME_RS_RT); } break; @@ -167,16 +217,17 @@ decode_mips_operand (const char *p) /* Short hand so the lines aren't too long. */ -#define LDD INSN_LOAD_MEMORY_DELAY #define LCD INSN_LOAD_COPROC_DELAY #define UBD INSN_UNCOND_BRANCH_DELAY #define CBD INSN_COND_BRANCH_DELAY #define COD INSN_COPROC_MOVE_DELAY -#define CLD INSN_COPROC_MEMORY_DELAY +#define CLD (INSN_LOAD_MEMORY|INSN_COPROC_MEMORY_DELAY) #define CBL INSN_COND_BRANCH_LIKELY #define NODS INSN_NO_DELAY_SLOT #define TRAP INSN_NO_DELAY_SLOT +#define LM INSN_LOAD_MEMORY #define SM INSN_STORE_MEMORY +#define F32M INSN_FP_32_MOVE #define WR_1 INSN_WRITE_1 #define WR_2 INSN_WRITE_2 @@ -218,6 +269,9 @@ decode_mips_operand (const char *p) #define WR_MACC INSN2_WRITE_MDMX_ACC #define RD_MACC INSN2_READ_MDMX_ACC +#define RD_pc INSN2_READ_PC +#define FS INSN2_FORBIDDEN_SLOT + #define I1 INSN_ISA1 #define I2 INSN_ISA2 #define I3 INSN_ISA3 @@ -226,7 +280,13 @@ decode_mips_operand (const char *p) #define I32 INSN_ISA32 #define I64 INSN_ISA64 #define I33 INSN_ISA32R2 +#define I34 INSN_ISA32R3 +#define I36 INSN_ISA32R5 +#define I37 INSN_ISA32R6 #define I65 INSN_ISA64R2 +#define I66 INSN_ISA64R3 +#define I68 INSN_ISA64R5 +#define I69 INSN_ISA64R6 #define I3_32 INSN_ISA3_32 #define I3_33 INSN_ISA3_32R2 #define I4_32 INSN_ISA4_32 @@ -273,9 +333,7 @@ decode_mips_operand (const char *p) #define G2 (T3 \ ) -#define G3 (I4 \ - |EE \ - ) +#define G3 EE /* 64 bit CPU with 32 bit FPU (single float). */ #define SF EE @@ -332,6 +390,13 @@ decode_mips_operand (const char *p) /* TLB invalidate instruction support. */ #define TLBINV ASE_EVA +/* MSA support. */ +#define MSA ASE_MSA +#define MSA64 ASE_MSA64 + +/* eXtended Physical Address (XPA) support. */ +#define XPA ASE_XPA + /* The order of overloaded instructions matters. Label arguments and register arguments look the same. Instructions that can have either for arguments must apear in the correct order in this table for the @@ -351,9 +416,10 @@ const struct mips_opcode mips_builtin_opcodes[] = them first. The assemblers uses a hash table based on the instruction name anyhow. */ /* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */ -{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_3, 0, I4_32|G3, 0, 0 }, -{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I4_32|G3, 0, 0 }, -{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_2|RD_3|FP_S, 0, I4_33, 0, 0 }, +{"pref", "k,+j(b)", 0x7c000035, 0xfc00007f, RD_3, 0, I37, 0, 0 }, +{"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_3|LM, 0, I4_32|G3, 0, I37 }, +{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I4_32|G3, 0, I37 }, +{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_2|RD_3|FP_S|LM, 0, I4_33, 0, I37 }, {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ {"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ {"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */ @@ -366,7 +432,12 @@ const struct mips_opcode mips_builtin_opcodes[] = {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 },/* or */ {"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 },/* beq 0,0 */ {"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, 0 },/* bgez 0 */ +{"nal", "p", 0x04100000, 0xffff0000, WR_31|CBD, INSN2_ALIAS, I1, 0, 0 },/* bltzal 0 */ {"bal", "p", 0x04110000, 0xffff0000, WR_31|UBD, INSN2_ALIAS, I1, 0, 0 },/* bgezal 0*/ +{"bc", "+'", 0xc8000000, 0xfc000000, NODS, 0, I37, 0, 0 }, +{"balc", "+'", 0xe8000000, 0xfc000000, WR_31|NODS, 0, I37, 0, 0 }, +{"lapc", "s,-A", 0xec000000, 0xfc180000, WR_1|RD_pc, 0, I37, 0, 0 }, +{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1, 0, 0 }, /* Loongson specific instructions. Loongson 3A redefines the Coprocessor 2 instructions. Put them here so that disassembler will find them first. @@ -377,14 +448,14 @@ const struct mips_opcode mips_builtin_opcodes[] = {"ramri", "d,s", 0x700000f5, 0xfc1f07ff, WR_1|RD_2, 0, IL3A, 0, 0 }, {"gsle", "s,t", 0x70000026, 0xfc00ffff, RD_1|RD_2, 0, IL3A, 0, 0 }, {"gsgt", "s,t", 0x70000027, 0xfc00ffff, RD_1|RD_2, 0, IL3A, 0, 0 }, -{"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, -{"gslbgt", "t,b,d", 0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, -{"gslhle", "t,b,d", 0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, -{"gslhgt", "t,b,d", 0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, -{"gslwle", "t,b,d", 0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, -{"gslwgt", "t,b,d", 0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, -{"gsldle", "t,b,d", 0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, -{"gsldgt", "t,b,d", 0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, +{"gslble", "t,b,d", 0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, +{"gslbgt", "t,b,d", 0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, +{"gslhle", "t,b,d", 0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, +{"gslhgt", "t,b,d", 0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, +{"gslwle", "t,b,d", 0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, +{"gslwgt", "t,b,d", 0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, +{"gsldle", "t,b,d", 0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, +{"gsldgt", "t,b,d", 0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, {"gssble", "t,b,d", 0xe8000010, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, {"gssbgt", "t,b,d", 0xe8000011, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, {"gsshle", "t,b,d", 0xe8000012, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, @@ -393,37 +464,37 @@ const struct mips_opcode mips_builtin_opcodes[] = {"gsswgt", "t,b,d", 0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, {"gssdle", "t,b,d", 0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, {"gssdgt", "t,b,d", 0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, -{"gslwlec1", "T,b,d", 0xc8000018, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, -{"gslwgtc1", "T,b,d", 0xc8000019, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, -{"gsldlec1", "T,b,d", 0xc800001a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, -{"gsldgtc1", "T,b,d", 0xc800001b, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IL3A, 0, 0 }, +{"gslwlec1", "T,b,d", 0xc8000018, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, +{"gslwgtc1", "T,b,d", 0xc8000019, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, +{"gsldlec1", "T,b,d", 0xc800001a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, +{"gsldgtc1", "T,b,d", 0xc800001b, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IL3A, 0, 0 }, {"gsswlec1", "T,b,d", 0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, {"gsswgtc1", "T,b,d", 0xe800001d, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, {"gssdlec1", "T,b,d", 0xe800001e, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, {"gssdgtc1", "T,b,d", 0xe800001f, 0xfc0007ff, RD_1|RD_2|RD_3|SM, 0, IL3A, 0, 0 }, -{"gslwlc1", "T,+a(b)", 0xc8000004, 0xfc00c03f, WR_1|RD_3|LDD, 0, IL3A, 0, 0 }, -{"gslwrc1", "T,+a(b)", 0xc8000005, 0xfc00c03f, WR_1|RD_3|LDD, 0, IL3A, 0, 0 }, -{"gsldlc1", "T,+a(b)", 0xc8000006, 0xfc00c03f, WR_1|RD_3|LDD, 0, IL3A, 0, 0 }, -{"gsldrc1", "T,+a(b)", 0xc8000007, 0xfc00c03f, WR_1|RD_3|LDD, 0, IL3A, 0, 0 }, +{"gslwlc1", "T,+a(b)", 0xc8000004, 0xfc00c03f, WR_1|RD_3|LM, 0, IL3A, 0, 0 }, +{"gslwrc1", "T,+a(b)", 0xc8000005, 0xfc00c03f, WR_1|RD_3|LM, 0, IL3A, 0, 0 }, +{"gsldlc1", "T,+a(b)", 0xc8000006, 0xfc00c03f, WR_1|RD_3|LM, 0, IL3A, 0, 0 }, +{"gsldrc1", "T,+a(b)", 0xc8000007, 0xfc00c03f, WR_1|RD_3|LM, 0, IL3A, 0, 0 }, {"gsswlc1", "T,+a(b)", 0xe8000004, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 }, {"gsswrc1", "T,+a(b)", 0xe8000005, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 }, {"gssdlc1", "T,+a(b)", 0xe8000006, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 }, {"gssdrc1", "T,+a(b)", 0xe8000007, 0xfc00c03f, RD_1|RD_3|SM, 0, IL3A, 0, 0 }, -{"gslbx", "t,+b(b,d)", 0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LDD, 0, IL3A, 0, 0 }, -{"gslhx", "t,+b(b,d)", 0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LDD, 0, IL3A, 0, 0 }, -{"gslwx", "t,+b(b,d)", 0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LDD, 0, IL3A, 0, 0 }, -{"gsldx", "t,+b(b,d)", 0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LDD, 0, IL3A, 0, 0 }, +{"gslbx", "t,+b(b,d)", 0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 }, +{"gslhx", "t,+b(b,d)", 0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 }, +{"gslwx", "t,+b(b,d)", 0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 }, +{"gsldx", "t,+b(b,d)", 0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 }, {"gssbx", "t,+b(b,d)", 0xf8000000, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, {"gsshx", "t,+b(b,d)", 0xf8000001, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, {"gsswx", "t,+b(b,d)", 0xf8000002, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, {"gssdx", "t,+b(b,d)", 0xf8000003, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, -{"gslwxc1", "T,+b(b,d)", 0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LDD, 0, IL3A, 0, 0 }, -{"gsldxc1", "T,+b(b,d)", 0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LDD, 0, IL3A, 0, 0 }, +{"gslwxc1", "T,+b(b,d)", 0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 }, +{"gsldxc1", "T,+b(b,d)", 0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LM, 0, IL3A, 0, 0 }, {"gsswxc1", "T,+b(b,d)", 0xf8000006, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, {"gssdxc1", "T,+b(b,d)", 0xf8000007, 0xfc000007, RD_1|RD_3|RD_4|SM, 0, IL3A, 0, 0 }, -{"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LDD, 0, IL3A, 0, 0 }, +{"gslq", "+z,t,+c(b)", 0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, IL3A, 0, 0 }, {"gssq", "+z,t,+c(b)", 0xe8000020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, IL3A, 0, 0 }, -{"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LDD, 0, IL3A, 0, 0 }, +{"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM, 0, IL3A, 0, 0 }, {"gssqc1", "+Z,T,+c(b)", 0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, IL3A, 0, 0 }, /* R5900 VU0 Macromode instructions. */ @@ -560,26 +631,27 @@ const struct mips_opcode mips_builtin_opcodes[] = {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 }, {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF }, -{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_1|RD_2|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_1|RD_2|FP_D, 0, I5_33|IL2F, 0, I37 }, {"abs.ps", "D,V", 0x45600005, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, -{"aclr", "\\,~(b)", 0x04070000, 0xfc1f8000, RD_3|SM|NODS, 0, 0, MC, 0 }, +{"aclr", "\\,~(b)", 0x04070000, 0xfc1f8000, RD_3|LM|SM|NODS, 0, 0, MC, 0 }, {"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC, 0 }, {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1, 0, 0 }, +{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1, 0, I37 }, {"add", "D,S,T", 0x45c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, {"add", "D,S,T", 0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F|IL3A, 0, 0 }, {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, {"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, {"add.ob", "D,S,Q", 0x4800000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33|IL2F, 0, I37 }, {"add.ps", "D,V,T", 0x45600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, {"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, {"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, {"adda.s", "S,T", 0x46000018, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, -{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, +{"addi", "t,r,j", 0x20000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, I37 }, {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, +{"addiupc", "s,-a", 0xec000000, 0xfc180000, WR_1|RD_pc, 0, I37, 0, 0 }, {"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, {"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, {"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, M3D, 0 }, @@ -590,7 +662,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, 0 }, +{"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 }, {"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, SB1, MX, 0 }, {"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, 0, MX, 0 }, {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, @@ -601,7 +673,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"and.ob", "D,S,Q", 0x4800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, {"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 }, -{"aset", "\\,~(b)", 0x04078000, 0xfc1f8000, RD_3|SM|NODS, 0, 0, MC, 0 }, +{"aset", "\\,~(b)", 0x04078000, 0xfc1f8000, RD_3|LM|SM|NODS, 0, 0, MC, 0 }, {"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC, 0 }, {"baddu", "d,v,t", 0x70000028, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, /* b is at the top of the table. */ @@ -617,198 +689,200 @@ const struct mips_opcode mips_builtin_opcodes[] = {"bc1any2t", "N,p", 0x45210000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 }, {"bc1any4f", "N,p", 0x45400000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 }, {"bc1any4t", "N,p", 0x45410000, 0xffe30000, RD_CC|CBD|FP_S, 0, 0, M3D, 0 }, -{"bc1f", "p", 0x45000000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, 0 }, -{"bc1f", "N,p", 0x45000000, 0xffe30000, RD_CC|CBD|FP_S, 0, I4_32, 0, 0 }, -{"bc1fl", "p", 0x45020000, 0xffff0000, RD_CC|CBL|FP_S, 0, I2|T3, 0, 0 }, -{"bc1fl", "N,p", 0x45020000, 0xffe30000, RD_CC|CBL|FP_S, 0, I4_32, 0, 0 }, -{"bc1t", "p", 0x45010000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, 0 }, -{"bc1t", "N,p", 0x45010000, 0xffe30000, RD_CC|CBD|FP_S, 0, I4_32, 0, 0 }, -{"bc1tl", "p", 0x45030000, 0xffff0000, RD_CC|CBL|FP_S, 0, I2|T3, 0, 0 }, -{"bc1tl", "N,p", 0x45030000, 0xffe30000, RD_CC|CBL|FP_S, 0, I4_32, 0, 0 }, +{"bc1eqz", "T,p", 0x45200000, 0xffe00000, RD_1|CBD|FP_S, 0, I37, 0, 0 }, +{"bc1f", "p", 0x45000000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, I37 }, +{"bc1f", "N,p", 0x45000000, 0xffe30000, RD_CC|CBD|FP_S, 0, I4_32, 0, I37 }, +{"bc1fl", "p", 0x45020000, 0xffff0000, RD_CC|CBL|FP_S, 0, I2|T3, 0, I37 }, +{"bc1fl", "N,p", 0x45020000, 0xffe30000, RD_CC|CBL|FP_S, 0, I4_32, 0, I37 }, +{"bc1nez", "T,p", 0x45a00000, 0xffe00000, RD_1|CBD|FP_S, 0, I37, 0, 0 }, +{"bc1t", "p", 0x45010000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, I37 }, +{"bc1t", "N,p", 0x45010000, 0xffe30000, RD_CC|CBD|FP_S, 0, I4_32, 0, I37 }, +{"bc1tl", "p", 0x45030000, 0xffff0000, RD_CC|CBL|FP_S, 0, I2|T3, 0, I37 }, +{"bc1tl", "N,p", 0x45030000, 0xffe30000, RD_CC|CBL|FP_S, 0, I4_32, 0, I37 }, /* bc2* are at the bottom of the table. */ /* bc3* are at the bottom of the table. */ {"beqz", "s,p", 0x10000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, -{"beqzl", "s,p", 0x50000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, 0 }, +{"beqzl", "s,p", 0x50000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, {"beq", "s,t,p", 0x10000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 }, {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 }, -{"beql", "s,t,p", 0x50000000, 0xfc000000, RD_1|RD_2|CBL, 0, I2|T3, 0, 0 }, -{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, +{"beql", "s,t,p", 0x50000000, 0xfc000000, RD_1|RD_2|CBL, 0, I2|T3, 0, I37 }, +{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 }, {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3, 0, 0 }, -{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, +{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3, 0, I37 }, +{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 }, {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3, 0, 0 }, -{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, +{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3, 0, I37 }, +{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, {"bgez", "s,p", 0x04010000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, -{"bgezl", "s,p", 0x04030000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, 0 }, -{"bgezal", "s,p", 0x04110000, 0xfc1f0000, RD_1|WR_31|CBD, 0, I1, 0, 0 }, -{"bgezall", "s,p", 0x04130000, 0xfc1f0000, RD_1|WR_31|CBL, 0, I2|T3, 0, 0 }, +{"bgezl", "s,p", 0x04030000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, +{"bgezal", "s,p", 0x04110000, 0xfc1f0000, RD_1|WR_31|CBD, 0, I1, 0, I37 }, +{"bgezall", "s,p", 0x04130000, 0xfc1f0000, RD_1|WR_31|CBL, 0, I2|T3, 0, I37 }, {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 }, {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3, 0, 0 }, -{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, +{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3, 0, I37 }, +{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 }, {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3, 0, 0 }, -{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, +{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3, 0, I37 }, +{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, -{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, 0 }, +{"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 }, {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3, 0, 0 }, -{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, +{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3, 0, I37 }, +{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 }, {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3, 0, 0 }, -{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, +{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3, 0, I37 }, +{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, {"blez", "s,p", 0x18000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, -{"blezl", "s,p", 0x58000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, 0 }, +{"blezl", "s,p", 0x58000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 }, {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3, 0, 0 }, -{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, +{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3, 0, I37 }, +{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 }, {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3, 0, 0 }, -{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, +{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3, 0, I37 }, +{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, {"bltz", "s,p", 0x04000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, -{"bltzl", "s,p", 0x04020000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, 0 }, -{"bltzal", "s,p", 0x04100000, 0xfc1f0000, RD_1|WR_31|CBD, 0, I1, 0, 0 }, -{"bltzall", "s,p", 0x04120000, 0xfc1f0000, RD_1|WR_31|CBL, 0, I2|T3, 0, 0 }, +{"bltzl", "s,p", 0x04020000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, +{"bltzal", "s,p", 0x04100000, 0xfc1f0000, RD_1|WR_31|CBD, 0, I1, 0, I37 }, +{"bltzall", "s,p", 0x04120000, 0xfc1f0000, RD_1|WR_31|CBL, 0, I2|T3, 0, I37 }, {"bnez", "s,p", 0x14000000, 0xfc1f0000, RD_1|CBD, 0, I1, 0, 0 }, -{"bnezl", "s,p", 0x54000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, 0 }, +{"bnezl", "s,p", 0x54000000, 0xfc1f0000, RD_1|CBL, 0, I2|T3, 0, I37 }, {"bne", "s,t,p", 0x14000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 }, {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 }, -{"bnel", "s,t,p", 0x54000000, 0xfc000000, RD_1|RD_2|CBL, 0, I2|T3, 0, 0 }, -{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3, 0, 0 }, +{"bnel", "s,t,p", 0x54000000, 0xfc000000, RD_1|RD_2|CBL, 0, I2|T3, 0, I37 }, +{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3, 0, I37 }, {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1, 0, 0 }, {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1, 0, 0 }, {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1, 0, 0 }, -{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, -{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, -{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, -{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 }, +{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, {"c.f.ps", "S,T", 0x45600030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, -{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, -{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, -{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, -{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, -{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, {"c.un.ps", "S,T", 0x45600031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, -{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, -{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, -{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 }, -{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, +{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 }, +{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, {"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, SB1, MX, 0 }, {"c.eq.ob", "S,Q", 0x48000001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, N54, 0, 0 }, -{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, {"c.eq.ps", "S,T", 0x45600032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, +{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, {"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, MX, 0 }, -{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, -{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, -{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, -{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, -{"c.ueq.ps", "S,T", 0x46c00033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{"c.ueq.ps", "S,T", 0x46c00033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, {"c.ueq.ps", "S,T", 0x45600033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.ueq.ps", "M,S,T", 0x46c00033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, -{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, -{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, -{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, -{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, -{"c.olt.ps", "S,T", 0x46c00034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"c.ueq.ps", "M,S,T", 0x46c00033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{"c.olt.ps", "S,T", 0x46c00034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, {"c.olt.ps", "S,T", 0x45600034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.olt.ps", "M,S,T", 0x46c00034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, -{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, -{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, -{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, -{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, -{"c.ult.ps", "S,T", 0x46c00035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"c.olt.ps", "M,S,T", 0x46c00034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{"c.ult.ps", "S,T", 0x46c00035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, {"c.ult.ps", "S,T", 0x45600035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.ult.ps", "M,S,T", 0x46c00035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, -{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, -{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, -{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, -{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, -{"c.ole.ps", "S,T", 0x46c00036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"c.ult.ps", "M,S,T", 0x46c00035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{"c.ole.ps", "S,T", 0x46c00036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, {"c.ole.ps", "S,T", 0x45600036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.ole.ps", "M,S,T", 0x46c00036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, -{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, -{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, -{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, -{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, -{"c.ule.ps", "S,T", 0x46c00037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"c.ole.ps", "M,S,T", 0x46c00036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{"c.ule.ps", "S,T", 0x46c00037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, {"c.ule.ps", "S,T", 0x45600037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.ule.ps", "M,S,T", 0x46c00037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, -{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, -{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, -{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, -{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, -{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"c.ule.ps", "M,S,T", 0x46c00037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, {"c.sf.ps", "S,T", 0x45600038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, -{"c.ngle.d", "S,T", 0x46200039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, -{"c.ngle.d", "M,S,T", 0x46200039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, -{"c.ngle.s", "S,T", 0x46000039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, -{"c.ngle.s", "M,S,T", 0x46000039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, -{"c.ngle.ps", "S,T", 0x46c00039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{"c.ngle.d", "S,T", 0x46200039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{"c.ngle.d", "M,S,T", 0x46200039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{"c.ngle.s", "S,T", 0x46000039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{"c.ngle.s", "M,S,T", 0x46000039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{"c.ngle.ps", "S,T", 0x46c00039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, {"c.ngle.ps", "S,T", 0x45600039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.ngle.ps", "M,S,T", 0x46c00039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, -{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, -{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, -{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, -{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, -{"c.seq.ps", "S,T", 0x46c0003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"c.ngle.ps", "M,S,T", 0x46c00039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{"c.seq.ps", "S,T", 0x46c0003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, {"c.seq.ps", "S,T", 0x4560003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.seq.ps", "M,S,T", 0x46c0003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, -{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, -{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, -{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, -{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, -{"c.ngl.ps", "S,T", 0x46c0003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"c.seq.ps", "M,S,T", 0x46c0003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{"c.ngl.ps", "S,T", 0x46c0003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, {"c.ngl.ps", "S,T", 0x4560003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.ngl.ps", "M,S,T", 0x46c0003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, -{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, -{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, +{"c.ngl.ps", "M,S,T", 0x46c0003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, {"c.lt.s", "S,T", 0x46000034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, EE, 0, 0 }, -{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, -{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, +{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, {"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, SB1, MX, 0 }, {"c.lt.ob", "S,Q", 0x48000004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, N54, 0, 0 }, -{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, {"c.lt.ps", "S,T", 0x4560003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, +{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, {"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, MX, 0 }, -{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, -{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, -{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, -{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, -{"c.nge.ps", "S,T", 0x46c0003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{"c.nge.ps", "S,T", 0x46c0003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, {"c.nge.ps", "S,T", 0x4560003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.nge.ps", "M,S,T", 0x46c0003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, -{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, -{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, +{"c.nge.ps", "M,S,T", 0x46c0003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, +{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, {"c.le.s", "S,T", 0x46000036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, EE, 0, 0 }, -{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, -{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, +{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, {"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, SB1, MX, 0 }, {"c.le.ob", "S,Q", 0x48000005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, N54, 0, 0 }, -{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, {"c.le.ps", "S,T", 0x4560003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, +{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, {"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D, 0, 0, MX, 0 }, -{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF }, -{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, 0 }, -{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE }, -{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, 0 }, -{"c.ngt.ps", "S,T", 0x46c0003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, SF|I37 }, +{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I4_32, 0, I37 }, +{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, EE|I37 }, +{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, I4_32, 0, I37 }, +{"c.ngt.ps", "S,T", 0x46c0003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, I5_33|IL2F, 0, I37 }, {"c.ngt.ps", "S,T", 0x4560003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, -{"c.ngt.ps", "M,S,T", 0x46c0003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, 0 }, +{"c.ngt.ps", "M,S,T", 0x46c0003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, I5_33, 0, I37 }, {"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D, 0, 0, M3D, 0 }, {"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S, 0, 0, M3D, 0 }, @@ -862,15 +936,16 @@ const struct mips_opcode mips_builtin_opcodes[] = {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1, 0, 0 }, {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1, 0, 0 }, {"wb", "o(b)", 0xbc040000, 0xfc1f0000, RD_2|SM, 0, L1, 0, 0 }, -{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_3, 0, I3_32|T3, 0, 0}, -{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3_32|T3, 0, 0}, +{"cache", "k,+j(b)", 0x7c000025, 0xfc00007f, RD_3, 0, I37, 0, 0 }, +{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_3, 0, I3_32|T3, 0, I37 }, +{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3_32|T3, 0, I37 }, {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, EE }, -{"cfc0", "t,G", 0x40400000, 0xffe007ff, WR_1|RD_C0|LCD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"cfc1", "t,G", 0x44400000, 0xffe007ff, WR_1|RD_C1|LCD|FP_S, 0, I1, 0, 0 }, -{"cfc1", "t,S", 0x44400000, 0xffe007ff, WR_1|RD_C1|LCD|FP_S, 0, I1, 0, 0 }, +/* cfc0 is at the bottom of the table. */ +{"cfc1", "t,G", 0x44400000, 0xffe007ff, WR_1|RD_C1|LCD, 0, I1, 0, 0 }, +{"cfc1", "t,S", 0x44400000, 0xffe007ff, WR_1|RD_C1|LCD, 0, I1, 0, 0 }, /* cfc2 is at the bottom of the table. */ /* cfc3 is at the bottom of the table. */ {"cftc1", "d,E", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LCD|FP_S, 0, 0, MT32, 0 }, @@ -879,11 +954,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {"cins32", "t,r,+p,+s", 0x70000033, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, {"cins", "t,r,+P,+S", 0x70000033, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, /* cins32 */ {"cins", "t,r,+p,+S", 0x70000032, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, -{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, 0 }, -{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, 0 }, -{"ctc0", "t,G", 0x40c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S, 0, I1, 0, 0 }, -{"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S, 0, I1, 0, 0 }, +{"clo", "d,s", 0x00000051, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 }, +{"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, +{"clz", "d,s", 0x00000050, 0xfc1f07ff, WR_1|RD_2, 0, I37, 0, 0 }, +{"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, I37 }, +/* ctc0 is at the bottom of the table. */ +{"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, 0 }, +{"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, 0 }, /* ctc2 is at the bottom of the table. */ /* ctc3 is at the bottom of the table. */ {"cttc1", "t,g", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|COD|FP_S, 0, 0, MT32, 0 }, @@ -902,21 +979,23 @@ const struct mips_opcode mips_builtin_opcodes[] = {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF }, {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, EE }, {"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, 0, M3D, 0 }, -{"cvt.ps.s", "D,V,T", 0x46000026, 0xffe0003f, WR_1|RD_2|RD_3|FP_S|FP_D, 0, I5_33, 0, 0 }, +{"cvt.ps.s", "D,V,T", 0x46000026, 0xffe0003f, WR_1|RD_2|RD_3|FP_S|FP_D, 0, I5_33, 0, I37 }, {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, 0, M3D, 0 }, {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3, 0, 0 }, {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, 0 }, +{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, I69 }, {"dadd", "D,S,T", 0x45e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"dadd", "D,S,T", 0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, -{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, +{"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, I69 }, {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 }, {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, {"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 }, {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 }, -{"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, 0 }, -{"dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, 0 }, +{"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, +{"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 }, +{"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, +{"dclz", "U,s", 0x70000024, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 }, /* dctr and dctw are used on the r5000. */ {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_2, 0, I3, 0, 0 }, @@ -927,13 +1006,17 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, {"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_1|RD_2, 0, I65, 0, 0 }, /* For ddiv, see the comments about div. */ -{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32 }, -{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, M32 }, -{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3, 0, M32 }, +{"dmod", "d,s,t", 0x000000de, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, +{"ddiv", "d,s,t", 0x0000009e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, +{"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32|I69 }, +{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, M32|I69 }, +{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3, 0, M32|I69 }, /* For ddivu, see the comments about div. */ -{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32 }, -{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, M32 }, -{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3, 0, M32 }, +{"dmodu", "d,s,t", 0x000000df, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, +{"ddivu", "d,s,t", 0x0000009f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, +{"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32|I69 }, +{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, M32|I69 }, +{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3, 0, M32|I69 }, {"di", "", 0x42000039, 0xffffffff, WR_C0, 0, EE, 0, 0 }, {"di", "", 0x41606000, 0xffffffff, WR_C0, 0, I33, 0, 0 }, {"di", "t", 0x41606000, 0xffe0ffff, WR_1|WR_C0, 0, I33, 0, 0 }, @@ -946,20 +1029,24 @@ const struct mips_opcode mips_builtin_opcodes[] = though the first operand appeared twice (the first operand is both a source and a destination). To get the div machine instruction, you must use an explicit destination of $0. */ -{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, -{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_2|WR_HILO, 0, I1, 0, 0 }, -{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 }, -{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1, 0, 0 }, +{"mod", "d,v,t", 0x000000da, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, +{"modu", "d,v,t", 0x000000db, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, +{"div", "d,v,t", 0x0000009a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, +{"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, I37 }, +{"div", "z,t", 0x0000001a, 0xffe0ffff, RD_2|WR_HILO, 0, I1, 0, I37 }, +{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, I37 }, +{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1, 0, I37 }, {"div1", "z,s,t", 0x7000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, EE, 0, 0 }, {"div1", "z,t", 0x7000001a, 0xffe0ffff, RD_2|WR_HILO, 0, EE, 0, 0 }, {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, {"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, 0, 0 }, /* For divu, see the comments about div. */ -{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, -{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_2|WR_HILO, 0, I1, 0, 0 }, -{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 }, -{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1, 0, 0 }, +{"divu", "d,v,t", 0x0000009b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, +{"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, I37 }, +{"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_2|WR_HILO, 0, I1, 0, I37 }, +{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, I37 }, +{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1, 0, I37 }, {"divu1", "z,s,t", 0x7000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, EE, 0, 0 }, {"divu1", "z,t", 0x7000001b, 0xffe0ffff, RD_2|WR_HILO, 0, EE, 0, 0 }, {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3, 0, 0 }, @@ -994,24 +1081,28 @@ const struct mips_opcode mips_builtin_opcodes[] = /* dmtc2 is at the bottom of the table. */ /* dmfc3 is at the bottom of the table. */ /* dmtc3 is at the bottom of the table. */ +{"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, +{"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, {"dmul", "d,v,t", 0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, IOCT, 0, 0 }, -{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32 }, -{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3, 0, M32 }, -{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3, 0, M32 }, -{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3, 0, M32 }, -{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3, 0, M32 }, -{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3, 0, M32 }, -{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, M32 }, -{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, M32 }, +{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, M32|I69 }, +{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3, 0, M32|I69 }, +{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3, 0, M32|I69 }, +{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3, 0, M32|I69 }, +{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3, 0, M32|I69 }, +{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3, 0, M32|I69 }, +{"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, M32|I69 }, +{"dmulu", "d,s,t", 0x0000009d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, +{"dmuhu", "d,s,t", 0x000000dd, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, +{"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, M32|I69 }, {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsub 0 */ {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsubu 0*/ {"dpop", "d,v", 0x7000002d, 0xfc1f07ff, WR_1|RD_2, 0, IOCT, 0, 0 }, -{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32 }, -{"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, M32 }, -{"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3, 0, M32 }, -{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32 }, -{"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, M32 }, -{"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3, 0, M32 }, +{"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32|I69 }, +{"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, M32|I69 }, +{"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3, 0, M32|I69 }, +{"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, M32|I69 }, +{"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, M32|I69 }, +{"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3, 0, M32|I69 }, {"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5, 0, 0 }, {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3, 0, 0 }, {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3, 0, 0 }, @@ -1050,7 +1141,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dsrl", "D,S,T", 0x45a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"dsrl", "D,S,T", 0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, -{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3, 0, 0 }, +{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3, 0, I69 }, {"dsub", "D,S,T", 0x45e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"dsub", "D,S,T", 0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F|IL3A, 0, 0 }, {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, @@ -1063,6 +1154,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, 0, MT32, 0 }, {"emt", "t", 0x41600be1, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, {"eret", "", 0x42000018, 0xffffffff, NODS, 0, I3_32, 0, 0 }, +{"eretnc", "", 0x42000058, 0xffffffff, NODS, 0, I36, 0, 0 }, {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, 0, MT32, 0 }, {"evpe", "t", 0x41600021, 0xffe0ffff, WR_1|TRAP, 0, 0, MT32, 0 }, {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_1|RD_2, 0, I33, 0, 0 }, @@ -1078,11 +1170,15 @@ const struct mips_opcode mips_builtin_opcodes[] = {"hypcall", "+J", 0x42000028, 0xffe007ff, TRAP, 0, 0, IVIRT, 0 }, {"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_1|RD_2, 0, I33, 0, 0 }, {"iret", "", 0x42000038, 0xffffffff, NODS, 0, 0, MC, 0 }, -{"jr", "s", 0x00000008, 0xfc1fffff, RD_1|UBD, 0, I1, 0, 0 }, +{"jr", "s", 0x00000009, 0xfc1fffff, RD_1|UBD, INSN2_ALIAS, I37, 0, 0 }, /* jalr $0 */ +{"jr", "s", 0x00000008, 0xfc1fffff, RD_1|UBD, 0, I1, 0, I37 }, +/* MIPS R6 jic appears before beqzc and jialc appears before bnezc */ /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with the same hazard barrier effect. */ -{"jr.hb", "s", 0x00000408, 0xfc1fffff, RD_1|UBD, 0, I32, 0, 0 }, -{"j", "s", 0x00000008, 0xfc1fffff, RD_1|UBD, 0, I1, 0, 0 }, /* jr */ +{"jr.hb", "s", 0x00000409, 0xfc1fffff, RD_1|UBD, INSN2_ALIAS, I37, 0, 0 }, /* jalr.hb $0 */ +{"jr.hb", "s", 0x00000408, 0xfc1fffff, RD_1|UBD, 0, I32, 0, I37 }, +{"j", "s", 0x00000009, 0xfc1fffff, RD_1|UBD, INSN2_ALIAS, I37, 0, 0 }, /* jalr $0 */ +{"j", "s", 0x00000008, 0xfc1fffff, RD_1|UBD, 0, I1, 0, I37 }, /* jr */ /* SVR4 PIC code requires special handling for j, so it must be a macro. */ {"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1, 0, 0 }, @@ -1105,99 +1201,108 @@ const struct mips_opcode mips_builtin_opcodes[] = assembler, but will never match user input (because the line above will match first). */ {"jal", "a", 0x0c000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 }, -{"jalx", "+i", 0x74000000, 0xfc000000, WR_31|UBD, 0, I1, 0, 0 }, -{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"laa", "d,(b),t", 0x7000049f, 0xfc0007ff, WR_1|RD_2|RD_3|LDD|SM, 0, IOCT2, 0, 0 }, -{"laad", "d,(b),t", 0x700004df, 0xfc0007ff, WR_1|RD_2|RD_3|LDD|SM, 0, IOCT2, 0, 0 }, -{"lac", "d,(b)", 0x7000039f, 0xfc1f07ff, WR_1|RD_2|LDD|SM, 0, IOCT2, 0, 0 }, -{"lacd", "d,(b)", 0x700003df, 0xfc1f07ff, WR_1|RD_2|LDD|SM, 0, IOCT2, 0, 0 }, -{"lad", "d,(b)", 0x7000019f, 0xfc1f07ff, WR_1|RD_2|LDD|SM, 0, IOCT2, 0, 0 }, -{"ladd", "d,(b)", 0x700001df, 0xfc1f07ff, WR_1|RD_2|LDD|SM, 0, IOCT2, 0, 0 }, -{"lai", "d,(b)", 0x7000009f, 0xfc1f07ff, WR_1|RD_2|LDD|SM, 0, IOCT2, 0, 0 }, -{"laid", "d,(b)", 0x700000df, 0xfc1f07ff, WR_1|RD_2|LDD|SM, 0, IOCT2, 0, 0 }, -{"las", "d,(b)", 0x7000029f, 0xfc1f07ff, WR_1|RD_2|LDD|SM, 0, IOCT2, 0, 0 }, -{"lasd", "d,(b)", 0x700002df, 0xfc1f07ff, WR_1|RD_2|LDD|SM, 0, IOCT2, 0, 0 }, -{"law", "d,(b),t", 0x7000059f, 0xfc0007ff, WR_1|RD_2|RD_3|LDD|SM, 0, IOCT2, 0, 0 }, -{"lawd", "d,(b),t", 0x700005df, 0xfc0007ff, WR_1|RD_2|RD_3|LDD|SM, 0, IOCT2, 0, 0 }, -{"lb", "t,o(b)", 0x80000000, 0xfc000000, WR_1|RD_3|LDD, 0, I1, 0, 0 }, +{"jalx", "+i", 0x74000000, 0xfc000000, WR_31|UBD, 0, I1, 0, I37 }, +{"laa", "d,(b),t", 0x7000049f, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM, 0, IOCT2, 0, 0 }, +{"laad", "d,(b),t", 0x700004df, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM, 0, IOCT2, 0, 0 }, +{"lac", "d,(b)", 0x7000039f, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, +{"lacd", "d,(b)", 0x700003df, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, +{"lad", "d,(b)", 0x7000019f, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, +{"ladd", "d,(b)", 0x700001df, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, +{"lai", "d,(b)", 0x7000009f, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, +{"laid", "d,(b)", 0x700000df, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, +{"las", "d,(b)", 0x7000029f, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, +{"lasd", "d,(b)", 0x700002df, 0xfc1f07ff, WR_1|RD_2|LM|SM, 0, IOCT2, 0, 0 }, +{"law", "d,(b),t", 0x7000059f, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM, 0, IOCT2, 0, 0 }, +{"lawd", "d,(b),t", 0x700005df, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM, 0, IOCT2, 0, 0 }, +{"lb", "t,o(b)", 0x80000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lbu", "t,o(b)", 0x90000000, 0xfc000000, WR_1|RD_3|LDD, 0, I1, 0, 0 }, +{"lbu", "t,o(b)", 0x90000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lbx", "d,t(b)", 0x7c00058a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IOCT2, 0, 0 }, -{"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IOCT2, D32, 0}, -{"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IOCT2, D64, 0}, -{"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IOCT2, D32, 0}, -{"lhux", "d,t(b)", 0x7c00050a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IOCT2, 0, 0 }, -{"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IOCT2, D32, 0}, -{"lwux", "d,t(b)", 0x7c00040a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, IOCT2, 0, 0 }, +{"lbx", "d,t(b)", 0x7c00058a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, 0, 0 }, +{"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, D32, 0}, +{"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, D64, 0}, +{"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, D32, 0}, +{"lhux", "d,t(b)", 0x7c00050a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, 0, 0 }, +{"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, D32, 0}, +{"lwux", "d,t(b)", 0x7c00040a, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, IOCT2, 0, 0 }, {"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1, 0, 0 }, +{"ldpc", "s,-B", 0xec180000, 0xfc1c0000, WR_1|RD_pc, 0, I69, 0, 0 }, /* The macro has to be first to handle o32 correctly. */ +{"ld", "s,-b(+R)", 0xec180000, 0xfc1c0000, WR_1|RD_pc, 0, I69, 0, 0 }, {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3, 0, I3, 0, 0 }, -{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, -{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, -{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, +{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 }, +{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, +{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, +{"ldaddd", "t,b", 0x70000012, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D, 0, I2, 0, SF }, /* ldc1 */ {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, -{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, -{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, +{"ldc2", "E,+:(d)", 0x49c00000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, +{"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE|I37 }, {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, -{"ldl", "t,o(b)", 0x68000000, 0xfc000000, WR_1|RD_3|LDD, 0, I3, 0, 0 }, -{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, WR_1|RD_3|LDD, 0, I3, 0, 0 }, -{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, WR_1|RD_2|RD_3|LDD|FP_D, 0, I4_33, 0, 0 }, -{"lh", "t,o(b)", 0x84000000, 0xfc000000, WR_1|RD_3|LDD, 0, I1, 0, 0 }, +{"ldl", "t,o(b)", 0x68000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, I69 }, +{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, I69 }, +{"ldr", "t,o(b)", 0x6c000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, I69 }, +{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3, 0, I69 }, +{"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_D, 0, I4_33, 0, I37 }, +{"lh", "t,o(b)", 0x84000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lhu", "t,o(b)", 0x94000000, 0xfc000000, WR_1|RD_3|LDD, 0, I1, 0, 0 }, +{"lhu", "t,o(b)", 0x94000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1, 0, 0 }, /* li is at the start of the table. */ {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, INSN2_M_FP_D, I1, 0, SF }, {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1, 0, SF }, {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"ll", "t,o(b)", 0xc0000000, 0xfc000000, WR_1|RD_3|LDD, 0, I2, 0, EE }, -{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2, 0, EE }, -{"lld", "t,o(b)", 0xd0000000, 0xfc000000, WR_1|RD_3|LDD, 0, I3, 0, EE }, -{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, 0, EE }, -{"lq", "t,o(b)", 0x78000000, 0xfc000000, WR_1|RD_3, 0, MMI, 0, 0 }, +{"ll", "t,+j(b)", 0x7c000036, 0xfc00007f, WR_1|RD_3|LM, 0, I37, 0, 0 }, +{"ll", "t,o(b)", 0xc0000000, 0xfc000000, WR_1|RD_3|LM, 0, I2, 0, EE|I37 }, +{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2, 0, EE|I37 }, +{"lld", "t,+j(b)", 0x7c000037, 0xfc00007f, WR_1|RD_3|LM, 0, I69, 0, 0 }, +{"lld", "t,o(b)", 0xd0000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, EE|I69 }, +{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, 0, EE|I69 }, +{"lq", "t,o(b)", 0x78000000, 0xfc000000, WR_1|RD_3|LM, 0, MMI, 0, 0 }, {"lq", "t,A(b)", 0, (int) M_LQ_AB, INSN_MACRO, 0, MMI, 0, 0 }, -{"lqc2", "+7,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_C2, 0, EE, 0, 0 }, +{"lqc2", "+7,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_C2|LM, 0, EE, 0, 0 }, {"lqc2", "+7,A(b)", 0, (int) M_LQC2_AB, INSN_MACRO, 0, EE, 0, 0 }, {"lui", "t,u", 0x3c000000, 0xffe00000, WR_1, 0, I1, 0, 0 }, -{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, WR_1|RD_2|RD_3|LDD|FP_D, 0, I5_33|N55, 0, 0}, -{"lw", "t,o(b)", 0x8c000000, 0xfc000000, WR_1|RD_3|LDD, 0, I1, 0, 0 }, +{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_D, 0, I5_33|N55, 0, I37}, +{"lwpc", "s,-A", 0xec080000, 0xfc180000, WR_1|RD_pc|LM, 0, I37, 0, 0 }, +{"lw", "t,o(b)", 0x8c000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 }, +{"lw", "s,-a(+R)", 0xec080000, 0xfc180000, WR_1|RD_pc|LM, 0, I37, 0, 0 }, {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 }, -{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 }, +{"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S|F32M,0, I1, 0, 0 }, +{"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S|F32M,0, I1, 0, 0 }, {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S, 0, I1, 0, 0 }, /* lwc1 */ +{"l.s", "T,o(b)", 0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S|F32M,0, I1, 0, 0 }, /* lwc1 */ {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"lwl", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LDD, 0, I1, 0, 0 }, -{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"lcache", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LDD, 0, I2, 0, 0 }, /* same */ -{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2, 0, 0 }, /* as lwl */ -{"lwr", "t,o(b)", 0x98000000, 0xfc000000, WR_1|RD_3|LDD, 0, I1, 0, 0 }, -{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"flush", "t,o(b)", 0x98000000, 0xfc000000, WR_1|RD_3|LDD, 0, I2, 0, 0 }, /* same */ -{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2, 0, 0 }, /* as lwr */ +{"lwc2", "E,+:(d)", 0x49400000, 0xffe00000, RD_3|WR_C2|CLD, 0, I37, 0, 0 }, +{"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, RD_3|WR_CC|CLD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"lwl", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, I37 }, +{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, I37 }, +{"lcache", "t,o(b)", 0x88000000, 0xfc000000, WR_1|RD_3|LM, 0, I2, 0, I37 }, /* same */ +{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2, 0, I37 }, /* as lwl */ +{"lwr", "t,o(b)", 0x98000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, I37 }, +{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, I37 }, +{"flush", "t,o(b)", 0x98000000, 0xfc000000, WR_1|RD_3|LM, 0, I2, 0, I37 }, /* same */ +{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2, 0, I37 }, /* as lwr */ {"fork", "d,s,t", 0x7c000008, 0xfc0007ff, WR_1|RD_2|RD_3|TRAP, 0, 0, MT32, 0 }, -{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|LDD, 0, I3, 0, 0 }, +{"lwupc", "s,-A", 0xec100000, 0xfc180000, WR_1|RD_pc, 0, I69, 0, 0 }, +{"lwu", "t,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 }, +{"lwu" , "s,-a(+R)", 0xec100000, 0xfc180000, WR_1|RD_pc, 0, I69, 0, 0 }, {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, WR_1|RD_2|RD_3|LDD|FP_S, 0, I4_33, 0, 0 }, -{"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, WR_1|RD_2|RD_3|LDD, 0, 0, SMT, 0 }, +{"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_S|F32M, 0, I4_33, 0, I37 }, +{"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, 0, SMT, 0 }, {"macc", "d,s,t", 0x00000028, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, {"macc", "d,s,t", 0x00000158, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, {"maccs", "d,s,t", 0x00000428, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, @@ -1212,18 +1317,18 @@ const struct mips_opcode mips_builtin_opcodes[] = {"maccus", "d,s,t", 0x00000468, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N412, 0, 0 }, {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, P3, 0, 0 }, {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, P3, 0, 0 }, -{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, 0 }, +{"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, {"madd.d", "D,S,T", 0x46200018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"madd.d", "D,S,T", 0x72200018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, -{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, 0 }, +{"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, I37 }, {"madd.s", "D,S,T", 0x46000018, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, {"madd.s", "D,S,T", 0x72000018, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F, 0, 0 }, {"madd.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, -{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, 0 }, +{"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 }, {"madd.ps", "D,S,T", 0x45600018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"madd.ps", "D,S,T", 0x72c00018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, -{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, 0 }, +{"madd", "s,t", 0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, I37 }, {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, G1, 0, 0 }, {"madd", "7,s,t", 0x70000000, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"madd", "d,s,t", 0x70000000, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, G1, 0, 0 }, @@ -1232,7 +1337,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"madda.s", "S,T", 0x4600001e, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, {"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, 0, SMT, 0 }, {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, -{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, 0 }, +{"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, I37 }, {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, G1, 0, 0 }, {"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, G1, 0, 0 }, @@ -1243,6 +1348,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"max.ob", "D,S,Q", 0x48000007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, {"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, {"max.s", "D,S,T", 0x46000028, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, +{"max.s", "D,S,T", 0x4600001e, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, {"mfbpc", "t", 0x4000c000, 0xffe0ffff, WR_1|RD_C0|LCD, 0, EE, 0, 0 }, {"mfdab", "t", 0x4000c004, 0xffe0ffff, WR_1|RD_C0|LCD, 0, EE, 0, 0 }, {"mfdabm", "t", 0x4000c005, 0xffe0ffff, WR_1|RD_C0|LCD, 0, EE, 0, 0 }, @@ -1273,58 +1379,63 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, WR_1|RD_C0|LCD, 0, I32, 0, 0 }, {"mfgc0", "t,G", 0x40600000, 0xffe007ff, WR_1|RD_C0|LCD, 0, 0, IVIRT, 0 }, {"mfgc0", "t,G,H", 0x40600000, 0xffe007f8, WR_1|RD_C0|LCD, 0, 0, IVIRT, 0 }, -{"mfc1", "t,S", 0x44000000, 0xffe007ff, WR_1|RD_2|LCD|FP_S, 0, I1, 0, 0 }, -{"mfc1", "t,G", 0x44000000, 0xffe007ff, WR_1|RD_2|LCD|FP_S, 0, I1, 0, 0 }, +{"mfhc0", "t,G", 0x40400000, 0xffe007ff, WR_1|RD_C0|LCD, 0, I33, XPA, 0 }, +{"mfhc0", "t,G,H", 0x40400000, 0xffe007f8, WR_1|RD_C0|LCD, 0, I33, XPA, 0 }, +{"mfhgc0", "t,G", 0x40600400, 0xffe007ff, WR_1|RD_C0|LCD, 0, I33, IVIRT|XPA, 0 }, +{"mfhgc0", "t,G,H", 0x40600400, 0xffe007f8, WR_1|RD_C0|LCD, 0, I33, IVIRT|XPA, 0 }, +{"mfc1", "t,S", 0x44000000, 0xffe007ff, WR_1|RD_2|LCD|FP_S|F32M,0, I1, 0, 0 }, +{"mfc1", "t,G", 0x44000000, 0xffe007ff, WR_1|RD_2|LCD|FP_S|F32M,0, I1, 0, 0 }, {"mfhc1", "t,S", 0x44600000, 0xffe007ff, WR_1|RD_2|LCD|FP_D, 0, I33, 0, 0 }, {"mfhc1", "t,G", 0x44600000, 0xffe007ff, WR_1|RD_2|LCD|FP_D, 0, I33, 0, 0 }, /* mfc2 is at the bottom of the table. */ /* mfhc2 is at the bottom of the table. */ /* mfc3 is at the bottom of the table. */ {"mfdr", "t,G", 0x7000003d, 0xffe007ff, WR_1|RD_C0|LCD, 0, N5, 0, 0 }, -{"mfhi", "d", 0x00000010, 0xffff07ff, WR_1|RD_HI, 0, I1, 0, 0 }, +{"mfhi", "d", 0x00000010, 0xffff07ff, WR_1|RD_HI, 0, I1, 0, I37 }, {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_1|RD_HI, 0, 0, D32, 0 }, {"mfhi1", "d", 0x70000010, 0xffff07ff, WR_1|RD_HI, 0, EE, 0, 0 }, -{"mflo", "d", 0x00000012, 0xffff07ff, WR_1|RD_LO, 0, I1, 0, 0 }, +{"mflo", "d", 0x00000012, 0xffff07ff, WR_1|RD_LO, 0, I1, 0, I37 }, {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_1|RD_LO, 0, 0, D32, 0 }, {"mflo1", "d", 0x70000012, 0xffff07ff, WR_1|RD_LO, 0, EE, 0, 0 }, {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_1|MOD_HILO, 0, 0, SMT, 0 }, -{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1, 0, XLR, 0, 0 }, +{"mfcr", "t,s", 0x70000018, 0xfc00ffff, WR_1|RD_2, 0, XLR, 0, 0 }, {"mfsa", "d", 0x00000028, 0xffff07ff, WR_1, 0, EE, 0, 0 }, {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, {"min.ob", "D,S,Q", 0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, {"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, {"min.s", "D,S,T", 0x46000029, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, +{"min.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF }, {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_1|RD_2|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_1|RD_2|FP_D, 0, I5_33|IL2F, 0, I37 }, {"mov.ps", "D,S", 0x45600006, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, -{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I4_32, 0, 0 }, -{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I4_32, 0, 0 }, +{"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I4_32, 0, I37 }, +{"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I4_32, 0, I37 }, {"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, -{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S, 0, I4_32, 0, 0 }, -{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I5_33, 0, 0 }, -{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I4_32|IL2E|IL2F|EE, 0, 0 }, +{"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S, 0, I4_32, 0, I37 }, +{"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I5_33, 0, I37 }, +{"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I4_32|IL2E|IL2F|EE, 0, I37 }, {"movnz", "d,v,t", 0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E|IL2F|IL3A, 0, 0 }, {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_1|RD_2, 0, L1, 0, 0 }, -{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I4_32, 0, 0 }, +{"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I4_32, 0, I37 }, {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, {"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I4_32, 0, 0 }, -{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, 0 }, -{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I4_32, 0, 0 }, -{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I4_32, 0, 0 }, +{"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I4_32, 0, I37 }, +{"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, +{"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I4_32, 0, I37 }, +{"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I4_32, 0, I37 }, {"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, SB1, MX, 0 }, -{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S, 0, I4_32, 0, 0 }, -{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I5_33, 0, 0 }, -{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I4_32|IL2E|IL2F|EE, 0, 0 }, +{"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S, 0, I4_32, 0, I37 }, +{"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D, 0, I5_33, 0, I37 }, +{"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I4_32|IL2E|IL2F|EE, 0, I37 }, {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_1|RD_2, 0, L1, 0, 0 }, -{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I4_32, 0, 0 }, +{"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I4_32, 0, I37 }, {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, {"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, -{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I4_32, 0, 0 }, -{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, 0 }, +{"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I4_32, 0, I37 }, +{"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, {"msac", "d,s,t", 0x000001d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, {"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, {"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, @@ -1336,22 +1447,22 @@ const struct mips_opcode mips_builtin_opcodes[] = {"msgld", "t", 0, (int) M_MSGLD_T, INSN_MACRO, 0, XLR, 0, 0 }, {"msgwait", "", 0, (int) M_MSGWAIT, INSN_MACRO, 0, XLR, 0, 0 }, {"msgwait", "t", 0, (int) M_MSGWAIT_T,INSN_MACRO, 0, XLR, 0, 0 }, -{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, 0 }, +{"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, {"msub.d", "D,S,T", 0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"msub.d", "D,S,T", 0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, -{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, 0 }, +{"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, I37 }, {"msub.s", "D,S,T", 0x46000019, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, {"msub.s", "D,S,T", 0x72000019, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F, 0, 0 }, {"msub.s", "D,S,T", 0x4600001d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, EE, 0, 0 }, -{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, 0 }, +{"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 }, {"msub.ps", "D,S,T", 0x45600019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"msub.ps", "D,S,T", 0x72c00019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, -{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, 0 }, +{"msub", "s,t", 0x70000004, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, I37 }, {"msub", "7,s,t", 0x70000004, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"msuba.s", "S,T", 0x4600001f, 0xffe007ff, RD_1|RD_2|FP_S, 0, EE, 0, 0 }, {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, L1, 0, 0 }, -{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, 0 }, +{"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I32|N55, 0, I37 }, {"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"mtbpc", "t", 0x4080c000, 0xffe0ffff, RD_1|WR_C0|COD, 0, EE, 0, 0 }, {"mtdab", "t", 0x4080c004, 0xffe0ffff, RD_1|WR_C0|COD, 0, EE, 0, 0 }, @@ -1366,22 +1477,26 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, RD_1|WR_C0|WR_CC|COD, 0, I32, 0, 0 }, {"mtgc0", "t,G", 0x40600200, 0xffe007ff, RD_1|WR_C0|WR_CC|COD, 0, 0, IVIRT, 0 }, {"mtgc0", "t,G,H", 0x40600200, 0xffe007f8, RD_1|WR_C0|WR_CC|COD, 0, 0, IVIRT, 0 }, -{"mtc1", "t,S", 0x44800000, 0xffe007ff, RD_1|WR_2|COD|FP_S, 0, I1, 0, 0 }, -{"mtc1", "t,G", 0x44800000, 0xffe007ff, RD_1|WR_2|COD|FP_S, 0, I1, 0, 0 }, +{"mthc0", "t,G", 0x40c00000, 0xffe007ff, RD_1|WR_C0|WR_CC|COD, 0, I33, XPA, 0 }, +{"mthc0", "t,G,H", 0x40c00000, 0xffe007f8, RD_1|WR_C0|WR_CC|COD, 0, I33, XPA, 0 }, +{"mthgc0", "t,G", 0x40600600, 0xffe007ff, RD_1|WR_C0|WR_CC|COD, 0, I33, IVIRT|XPA, 0 }, +{"mthgc0", "t,G,H", 0x40600600, 0xffe007f8, RD_1|WR_C0|WR_CC|COD, 0, I33, IVIRT|XPA, 0 }, +{"mtc1", "t,S", 0x44800000, 0xffe007ff, RD_1|WR_2|COD|FP_S|F32M,0, I1, 0, 0 }, +{"mtc1", "t,G", 0x44800000, 0xffe007ff, RD_1|WR_2|COD|FP_S|F32M,0, I1, 0, 0 }, {"mthc1", "t,S", 0x44e00000, 0xffe007ff, RD_1|WR_2|COD|FP_D, 0, I33, 0, 0 }, {"mthc1", "t,G", 0x44e00000, 0xffe007ff, RD_1|WR_2|COD|FP_D, 0, I33, 0, 0 }, /* mtc2 is at the bottom of the table. */ /* mthc2 is at the bottom of the table. */ /* mtc3 is at the bottom of the table. */ {"mtdr", "t,G", 0x7080003d, 0xffe007ff, RD_1|WR_C0|COD, 0, N5, 0, 0 }, -{"mthi", "s", 0x00000011, 0xfc1fffff, RD_1|WR_HI, 0, I1, 0, 0 }, +{"mthi", "s", 0x00000011, 0xfc1fffff, RD_1|WR_HI, 0, I1, 0, I37 }, {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_1|WR_HI, 0, 0, D32, 0 }, {"mthi1", "s", 0x70000011, 0xfc1fffff, RD_1|WR_HI, 0, EE, 0, 0 }, -{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_1|WR_LO, 0, I1, 0, 0 }, +{"mtlo", "s", 0x00000013, 0xfc1fffff, RD_1|WR_LO, 0, I1, 0, I37 }, {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_1|WR_LO, 0, 0, D32, 0 }, {"mtlo1", "s", 0x70000013, 0xfc1fffff, RD_1|WR_LO, 0, EE, 0, 0 }, {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 }, -{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1, 0, XLR, 0, 0 }, +{"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1|RD_2, 0, XLR, 0, 0 }, {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, {"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, @@ -1412,13 +1527,16 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, {"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, {"mul.ob", "D,S,Q", 0x48000030, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33|IL2F, 0, I37 }, {"mul.ps", "D,V,T", 0x45600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, -{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, I32|P3|N55, 0, 0}, +{"muh", "d,v,t", 0x000000d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, +{"muhu", "d,v,t", 0x000000d9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, +{"mul", "d,v,t", 0x00000098, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, +{"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, I32|P3|N55, 0, I37}, {"mul", "d,s,t", 0x00000058, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N54, 0, 0 }, -{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, 0 }, -{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1, 0, 0 }, +{"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1, 0, I37 }, +{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1, 0, I37 }, {"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, {"mula.ob", "S,Q", 0x48000033, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, {"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, @@ -1428,10 +1546,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, {"mull.ob", "S,Q", 0x48000433, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, {"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, -{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1, 0, 0 }, -{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1, 0, 0 }, -{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1, 0, 0 }, -{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1, 0, 0 }, +{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1, 0, I37 }, +{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1, 0, I37 }, +{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1, 0, I37 }, +{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1, 0, I37 }, {"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, M3D, 0 }, {"muls", "d,s,t", 0x000000d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, {"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, @@ -1443,40 +1561,41 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, {"mulsl.ob", "S,Q", 0x48000432, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, N54, 0, 0 }, {"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, 0, MX, 0 }, -{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, I1, 0, 0 }, +{"mult", "s,t", 0x00000018, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, I1, 0, I37 }, {"mult", "7,s,t", 0x00000018, 0xfc00e7ff, RD_2|RD_3|WR_a, 0, 0, D32, 0 }, {"mult", "d,s,t", 0x00000018, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, G1, 0, 0 }, {"mult1", "s,t", 0x70000018, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, EE, 0, 0 }, {"mult1", "d,s,t", 0x70000018, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, EE, 0, 0 }, {"multp", "s,t", 0x00000459, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, 0, SMT, 0 }, -{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, I1, 0, 0 }, +{"multu", "s,t", 0x00000019, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, I1, 0, I37 }, {"multu", "7,s,t", 0x00000019, 0xfc00e7ff, RD_2|RD_3|WR_a, 0, 0, D32, 0 }, {"multu", "d,s,t", 0x00000019, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, G1, 0, 0 }, {"multu1", "s,t", 0x70000019, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0, EE, 0, 0 }, {"multu1", "d,s,t", 0x70000019, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0, EE, 0, 0 }, +{"mulu", "d,v,t", 0x00000099, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0}, {"mulu", "d,s,t", 0x00000059, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, N5, 0, 0 }, {"neg", "d,w", 0x00000022, 0xffe007ff, WR_1|RD_2, 0, I1, 0, 0 }, /* sub 0 */ {"negu", "d,w", 0x00000023, 0xffe007ff, WR_1|RD_2, 0, I1, 0, 0 }, /* subu 0 */ {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF }, {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_1|RD_2|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_1|RD_2|FP_D, 0, I5_33|IL2F, 0, I37 }, {"neg.ps", "D,V", 0x45600007, 0xffff003f, WR_1|RD_2|FP_D, 0, IL2E, 0, 0 }, -{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, 0 }, +{"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, {"nmadd.d", "D,S,T", 0x4620001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"nmadd.d", "D,S,T", 0x7220001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, -{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, 0 }, +{"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, I37 }, {"nmadd.s", "D,S,T", 0x4600001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, {"nmadd.s", "D,S,T", 0x7200001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F, 0, 0 }, -{"nmadd.ps", "D,R,S,T", 0x4c000036, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, 0 }, +{"nmadd.ps", "D,R,S,T", 0x4c000036, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 }, {"nmadd.ps", "D,S,T", 0x4560001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"nmadd.ps", "D,S,T", 0x72c0001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, -{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, 0 }, +{"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I4_33, 0, I37 }, {"nmsub.d", "D,S,T", 0x4620001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"nmsub.d", "D,S,T", 0x7220001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, -{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, 0 }, +{"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I4_33, 0, I37 }, {"nmsub.s", "D,S,T", 0x4600001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, {"nmsub.s", "D,S,T", 0x7200001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F, 0, 0 }, -{"nmsub.ps", "D,R,S,T", 0x4c00003e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, 0 }, +{"nmsub.ps", "D,R,S,T", 0x4c00003e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I5_33, 0, I37 }, {"nmsub.ps", "D,S,T", 0x4560001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"nmsub.ps", "D,S,T", 0x72c0001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2F, 0, 0 }, /* nop is at the start of the table. */ @@ -1541,8 +1660,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, {"pinteh", "d,s,t", 0x700002a9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, {"pinth", "d,s,t", 0x70000289, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, -{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, 0 }, -{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, 0 }, +{"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, +{"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, {"plzcw", "d,s", 0x70000004, 0xfc1f07ff, WR_1|RD_2, 0, MMI, 0, 0 }, {"pmaddh", "d,s,t", 0x70000409, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, MMI, 0, 0 }, {"pmadduw", "d,s,t", 0x70000029, 0xfc0007ff, WR_1|RD_2|RD_3|MOD_HILO, 0, MMI, 0, 0 }, @@ -1584,8 +1703,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"psubuw", "d,s,t", 0x70000468, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, {"pxor", "d,s,t", 0x700004c9, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, /* pref and prefx are at the start of the table. */ -{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, 0 }, -{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, 0 }, +{"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, +{"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33, 0, I37 }, {"pperm", "s,t", 0x70000481, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, 0, SMT, 0 }, {"qfsrv", "d,s,t", 0x700006e8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, MMI, 0, 0 }, {"qmac.00", "s,t", 0x70000412, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, IOCT2, 0, 0 }, @@ -1614,12 +1733,12 @@ const struct mips_opcode mips_builtin_opcodes[] = {"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, 0, M3D, 0 }, {"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, M3D, 0 }, {"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, 0, M3D, 0 }, -{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, -{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 }, -{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1, 0, 0 }, -{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 }, -{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 }, -{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1, 0, 0 }, +{"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO, INSN2_ALIAS, I1, 0, I37 }, +{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, I37 }, +{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1, 0, I37 }, +{"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO, INSN2_ALIAS, I1, 0, I37 }, +{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, I37 }, +{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1, 0, I37 }, {"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_1, 0, I33, 0, 0 }, {"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_1, 0, I33, 0, 0 }, /* rfe is moved below as it now conflicts with tlbgp */ @@ -1664,33 +1783,38 @@ const struct mips_opcode mips_builtin_opcodes[] = {"saad", "t,(b)", 0x70000019, 0xfc00ffff, RD_1|RD_2|SM, 0, IOCTP, 0, 0 }, {"sb", "t,o(b)", 0xa0000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"sc", "t,o(b)", 0xe0000000, 0xfc000000, MOD_1|RD_3|SM, 0, I2, 0, EE }, -{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2, 0, EE }, -{"scd", "t,o(b)", 0xf0000000, 0xfc000000, MOD_1|RD_3|SM, 0, I3, 0, EE }, -{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3, 0, EE }, +{"sc", "t,+j(b)", 0x7c000026, 0xfc00007f, MOD_1|RD_3|SM, 0, I37, 0, 0 }, +{"sc", "t,o(b)", 0xe0000000, 0xfc000000, MOD_1|RD_3|SM, 0, I2, 0, EE|I37 }, +{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2, 0, EE|I37 }, +{"scd", "t,+j(b)", 0x7c000027, 0xfc00007f, MOD_1|RD_3|SM, 0, I69, 0, 0 }, +{"scd", "t,o(b)", 0xf0000000, 0xfc000000, MOD_1|RD_3|SM, 0, I3, 0, EE|I69 }, +{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3, 0, EE|I69 }, /* The macro has to be first to handle o32 correctly. */ {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1, 0, 0 }, {"sd", "t,o(b)", 0xfc000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, 0 }, {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2, 0, 0 }, {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2, 0, 0 }, {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2, 0, 0 }, -{"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32, 0, 0 }, -{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32, 0, 0 }, +{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, I37, 0, 0 }, +{"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32, 0, I37 }, +{"sdbbp", "B", 0x0000000e, 0xfc00003f, TRAP, 0, I37, 0, 0 }, +{"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32, 0, I37 }, {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I2, 0, SF }, {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I2, 0, SF }, {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I2, 0, SF }, -{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, -{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, +{"sdc2", "E,+:(d)", 0x49e00000, 0xffe00000, RD_3|RD_C2|SM, 0, I37, 0, 0 }, +{"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I2, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE|I37 }, {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, RD_3|RD_C3|SM, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2, 0, IOCT|IOCTP|IOCT2|EE }, {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I2, 0, SF }, {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 }, -{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, 0 }, -{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, 0 }, -{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I4_33, 0, 0 }, +{"sdl", "t,o(b)", 0xb0000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, I69 }, +{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3, 0, I69 }, +{"sdr", "t,o(b)", 0xb4000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, I69 }, +{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3, 0, I69 }, +{"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I4_33, 0, I37 }, {"seb", "d,w", 0x7c000420, 0xffe007ff, WR_1|RD_2, 0, I33, 0, 0 }, {"seh", "d,w", 0x7c000620, 0xffe007ff, WR_1|RD_2, 0, I33, 0, 0 }, {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_1|RD_2|RD_3, 0, L1, 0, 0 }, @@ -1779,14 +1903,14 @@ const struct mips_opcode mips_builtin_opcodes[] = /* ssnop is at the start of the table. */ {"standby", "", 0x42000021, 0xffffffff, 0, 0, V1, 0, 0 }, {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 }, -{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1, 0, 0 }, +{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1, 0, I37 }, {"sub", "D,S,T", 0x45c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, {"sub", "D,S,T", 0x4b40000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F|IL3A, 0, 0 }, {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, SF }, {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 }, {"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, SB1, MX, 0 }, {"sub.ob", "D,S,Q", 0x4800000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, N54, 0, 0 }, -{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33|IL2F, 0, 0 }, +{"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I5_33|IL2F, 0, I37 }, {"sub.ps", "D,V,T", 0x45600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, IL2E, 0, 0 }, {"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D, 0, 0, MX, 0 }, {"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_1|RD_2|FP_D, WR_MACC, SB1, MX, 0 }, @@ -1799,33 +1923,34 @@ const struct mips_opcode mips_builtin_opcodes[] = {"subu", "D,S,T", 0x45800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2E, 0, 0 }, {"subu", "D,S,T", 0x4b00000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, IL2F|IL3A, 0, 0 }, {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1, 0, 0 }, -{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, 0}, +{"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I5_33|N55, 0, I37}, {"sw", "t,o(b)", 0xac000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, -{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, -{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|SM, 0, XLR, 0, 0 }, -{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, -{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, +{"swapw", "t,b", 0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, +{"swapwu", "t,b", 0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, +{"swapd", "t,b", 0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM, 0, XLR, 0, 0 }, +{"swc0", "E,o(b)", 0xe0000000, 0xfc000000, RD_3|RD_C0|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{"swc1", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S|F32M, 0, I1, 0, 0 }, +{"swc1", "E,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S|F32M, 0, I1, 0, 0 }, {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, /* swc1 */ +{"s.s", "T,o(b)", 0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S|F32M, 0, I1, 0, 0 }, /* swc1 */ {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 }, -{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"swc3", "E,o(b)", 0xec000000, 0xfc000000, RD_3|RD_C3|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"swl", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, -{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3, 0, I2, 0, 0 }, /* same */ -{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2, 0, 0 }, /* as swl */ -{"swr", "t,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 }, -{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"invalidate", "t,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3, 0, I2, 0, 0 }, /* same */ -{"invalidate", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I2, 0, 0 }, /* as swr */ -{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S, 0, I4_33, 0, 0 }, +{"swc2", "E,+:(d)", 0x49600000, 0xffe00000, RD_3|RD_C2|SM, 0, I37, 0, 0 }, +{"swc2", "E,o(b)", 0xe8000000, 0xfc000000, RD_3|RD_C2|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"swc3", "E,o(b)", 0xec000000, 0xfc000000, RD_3|RD_C3|SM, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"swl", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, I37 }, +{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, I37 }, +{"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_1|RD_3, 0, I2, 0, I37 }, /* same */ +{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2, 0, I37 }, /* as swl */ +{"swr", "t,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, I37 }, +{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, I37 }, +{"invalidate", "t,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3, 0, I2, 0, I37 }, /* same */ +{"invalidate", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I2, 0, I37 }, /* as swr */ +{"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S|F32M, 0, I4_33, 0, I37 }, {"synciobdma", "", 0x0000008f, 0xffffffff, NODS, 0, IOCT, 0, 0 }, {"syncs", "", 0x0000018f, 0xffffffff, NODS, 0, IOCT, 0, 0 }, {"syncw", "", 0x0000010f, 0xffffffff, NODS, 0, IOCT, 0, 0 }, @@ -1842,20 +1967,20 @@ const struct mips_opcode mips_builtin_opcodes[] = {"synci", "o(b)", 0x041f0000, 0xfc1f0000, RD_2|SM, 0, I33, 0, 0 }, {"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1, 0, 0 }, {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1, 0, 0 }, -{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, +{"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, /* teqi */ +{"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* teqi */ {"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, +{"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, /* tgei */ +{"tge", "s,j", 0x04080000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tgei */ {"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, +{"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, /* tgeiu */ +{"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tgeiu */ {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2, 0, 0 }, {"tlbinv", "", 0x42000003, 0xffffffff, INSN_TLB, 0, 0, TLBINV, 0 }, {"tlbinvf", "", 0x42000004, 0xffffffff, INSN_TLB, 0, 0, TLBINV, 0 }, @@ -1869,20 +1994,20 @@ const struct mips_opcode mips_builtin_opcodes[] = {"tlbginvf", "", 0x4200000c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, {"tlbgwr", "", 0x4200000e, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, {"tlbgp", "", 0x42000010, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 }, -{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, +{"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, /* tlti */ +{"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tlti */ {"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, +{"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, /* tltiu */ +{"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tltiu */ {"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2, 0, 0 }, -{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, +{"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_1|RD_2|TRAP, 0, I2, 0, 0 }, -{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, 0 }, /* tnei */ +{"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_1|TRAP, 0, I2, 0, I37 }, /* tnei */ {"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2, 0, 0 }, {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 }, @@ -1893,13 +2018,13 @@ const struct mips_opcode mips_builtin_opcodes[] = {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, EE }, {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, EE }, {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, INSN2_M_FP_S, I1, 0, EE }, -{"uld", "t,A(b)", 0, (int) M_ULD_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"ulh", "t,A(b)", 0, (int) M_ULH_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"ulhu", "t,A(b)", 0, (int) M_ULHU_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"ulw", "t,A(b)", 0, (int) M_ULW_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"usd", "t,A(b)", 0, (int) M_USD_AB, INSN_MACRO, 0, I3, 0, 0 }, -{"ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1, 0, 0 }, -{"usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1, 0, 0 }, +{"uld", "t,A(b)", 0, (int) M_ULD_AB, INSN_MACRO, 0, I3, 0, I69 }, +{"ulh", "t,A(b)", 0, (int) M_ULH_AB, INSN_MACRO, 0, I1, 0, I37 }, +{"ulhu", "t,A(b)", 0, (int) M_ULHU_AB, INSN_MACRO, 0, I1, 0, I37 }, +{"ulw", "t,A(b)", 0, (int) M_ULW_AB, INSN_MACRO, 0, I1, 0, I37 }, +{"usd", "t,A(b)", 0, (int) M_USD_AB, INSN_MACRO, 0, I3, 0, I69 }, +{"ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1, 0, I37 }, +{"usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1, 0, I37 }, {"v3mulu", "d,v,t", 0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, {"vmm0", "d,v,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, {"vmulu", "d,v,t", 0x7000000f, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IOCT, 0, 0 }, @@ -1927,82 +2052,24 @@ const struct mips_opcode mips_builtin_opcodes[] = {"zcb", "(b)", 0x7000071f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 }, {"zcbt", "(b)", 0x7000075f, 0xfc1fffff, RD_1|SM, 0, IOCT2, 0, 0 }, -/* User Defined Instruction. */ -{"udi0", "s,t,d,+1", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi0", "s,+3", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi0", "+4", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi1", "s,t,d,+1", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi1", "s,t,+2", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi1", "s,+3", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi1", "+4", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi2", "s,t,d,+1", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi2", "s,t,+2", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi2", "s,+3", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi2", "+4", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi3", "s,t,d,+1", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi3", "s,t,+2", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi3", "s,+3", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi3", "+4", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi4", "s,t,d,+1", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi4", "s,t,+2", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi4", "s,+3", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi4", "+4", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi5", "s,t,d,+1", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi5", "s,t,+2", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi5", "s,+3", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi5", "+4", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi6", "s,t,d,+1", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi6", "s,t,+2", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi6", "s,+3", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi6", "+4", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi7", "s,t,d,+1", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi7", "s,t,+2", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi7", "s,+3", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi7", "+4", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi8", "s,t,d,+1", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi8", "s,t,+2", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi8", "s,+3", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi8", "+4", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi9", "s,t,d,+1", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi9", "s,t,+2", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi9", "s,+3", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi9", "+4", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi10", "s,t,d,+1", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi10", "s,+3", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi10", "+4", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi11", "s,t,d,+1", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi11", "s,+3", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi11", "+4", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi12", "s,t,d,+1", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi12", "s,+3", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi12", "+4", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi13", "s,t,d,+1", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi13", "s,+3", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi13", "+4", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi14", "s,t,d,+1", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi14", "s,+3", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi14", "+4", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi15", "s,t,d,+1", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi15", "s,+3", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, -{"udi15", "+4", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, +/* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the + mfhc0 and mthc0 XPA instructions, so they have been placed here + to allow the XPA instructions to take precedence. */ +{"ctc0", "t,G", 0x40c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, +{"cfc0", "t,G", 0x40400000, 0xffe007ff, WR_1|RD_C0|LCD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format instructions so they are here for the latters to take precedence. */ -{"bc2f", "p", 0x49000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"bc2f", "N,p", 0x49000000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2 }, -{"bc2fl", "p", 0x49020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2 }, -{"bc2fl", "N,p", 0x49020000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2 }, -{"bc2t", "p", 0x49010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"bc2t", "N,p", 0x49010000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2 }, -{"bc2tl", "p", 0x49030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2 }, -{"bc2tl", "N,p", 0x49030000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2 }, +{"bc2eqz", "E,p", 0x49200000, 0xffe00000, RD_C2|CBD, 0, I37, 0, 0 }, +{"bc2f", "p", 0x49000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{"bc2f", "N,p", 0x49000000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 }, +{"bc2fl", "p", 0x49020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 }, +{"bc2fl", "N,p", 0x49020000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 }, +{"bc2nez", "E,p", 0x49a00000, 0xffe00000, RD_C2|CBD, 0, I37, 0, 0 }, +{"bc2t", "p", 0x49010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{"bc2t", "N,p", 0x49010000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 }, +{"bc2tl", "p", 0x49030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 }, +{"bc2tl", "N,p", 0x49030000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2|I37 }, {"cfc2", "t,G", 0x48400000, 0xffe007ff, WR_1|RD_C2|LCD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, {"cfc2", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LCD, 0, EE, 0, 0 }, {"cfc2.i", "t,+9", 0x48400001, 0xffe007ff, WR_1|RD_C2|LCD, 0, EE, 0, 0 }, @@ -2035,18 +2102,18 @@ const struct mips_opcode mips_builtin_opcodes[] = {"qmtc2.ni", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 }, /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X instructions, so they are here for the latters to take precedence. */ -{"bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE }, -{"bc3t", "p", 0x4d010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE }, -{"cfc3", "t,G", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LCD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, WR_1|RD_C3|LCD, 0, I3, 0, IOCT|IOCTP|IOCT2|EE }, -{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, RD_1|WR_C3|WR_CC|COD, 0, I3, 0, IOCT|IOCTP|IOCT2|EE }, -{"mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LCD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, WR_1|RD_C3|LCD, 0, I32, 0, IOCT|IOCTP|IOCT2|EE }, -{"mtc3", "t,G", 0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE }, -{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|COD, 0, I32, 0, IOCT|IOCTP|IOCT2|EE }, +{"bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"bc3fl", "p", 0x4d020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"bc3t", "p", 0x4d010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"bc3tl", "p", 0x4d030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"cfc3", "t,G", 0x4c400000, 0xffe007ff, WR_1|RD_C3|LCD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"ctc3", "t,G", 0x4cc00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"dmfc3", "t,G", 0x4c200000, 0xffe007ff, WR_1|RD_C3|LCD, 0, I3, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, RD_1|WR_C3|WR_CC|COD, 0, I3, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"mfc3", "t,G", 0x4c000000, 0xffe007ff, WR_1|RD_C3|LCD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, WR_1|RD_C3|LCD, 0, I32, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"mtc3", "t,G", 0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE|I37 }, +{"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|COD, 0, I32, 0, IOCT|IOCTP|IOCT2|EE|I37 }, /* Conflicts with the 4650's "mul" instruction. Nobody's using the 4010 any more, so move this insn out of the way. If the object @@ -2333,10 +2400,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, RD_2|RD_3|MOD_a, 0, 0, D33, 0 }, /* Move bc0* after mftr and mttr to avoid opcode collision. */ -{"bc0f", "p", 0x41000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"bc0fl", "p", 0x41020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2 }, -{"bc0t", "p", 0x41010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2 }, -{"bc0tl", "p", 0x41030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2 }, +{"bc0f", "p", 0x41000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{"bc0fl", "p", 0x41020000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 }, +{"bc0t", "p", 0x41010000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|I37 }, +{"bc0tl", "p", 0x41030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2|I37 }, /* ST Microelectronics Loongson-2E and -2F. */ {"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2E, 0, 0 }, {"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, IL2F, 0, 0 }, @@ -2509,22 +2576,22 @@ const struct mips_opcode mips_builtin_opcodes[] = {"sequ", "S,T", 0x46800032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2E, 0, 0 }, {"sequ", "S,T", 0x4b80000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D, 0, IL2F|IL3A, 0, 0 }, /* MIPS Enhanced VA Scheme */ -{"lbue", "t,+j(b)", 0x7c000028, 0xfc00007f, WR_1|RD_3|LDD, 0, 0, EVA, 0 }, +{"lbue", "t,+j(b)", 0x7c000028, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, {"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lhue", "t,+j(b)", 0x7c000029, 0xfc00007f, WR_1|RD_3|LDD, 0, 0, EVA, 0 }, +{"lhue", "t,+j(b)", 0x7c000029, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, {"lhue", "t,A(b)", 0, (int) M_LHUE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lbe", "t,+j(b)", 0x7c00002c, 0xfc00007f, WR_1|RD_3|LDD, 0, 0, EVA, 0 }, +{"lbe", "t,+j(b)", 0x7c00002c, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, {"lbe", "t,A(b)", 0, (int) M_LBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lhe", "t,+j(b)", 0x7c00002d, 0xfc00007f, WR_1|RD_3|LDD, 0, 0, EVA, 0 }, +{"lhe", "t,+j(b)", 0x7c00002d, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, {"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lle", "t,+j(b)", 0x7c00002e, 0xfc00007f, WR_1|RD_3|LDD, 0, 0, EVA, 0 }, +{"lle", "t,+j(b)", 0x7c00002e, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, {"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lwe", "t,+j(b)", 0x7c00002f, 0xfc00007f, WR_1|RD_3|LDD, 0, 0, EVA, 0 }, +{"lwe", "t,+j(b)", 0x7c00002f, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 }, {"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lwle", "t,+j(b)", 0x7c000019, 0xfc00007f, WR_1|RD_3|LDD, 0, 0, EVA, 0 }, -{"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"lwre", "t,+j(b)", 0x7c00001a, 0xfc00007f, WR_1|RD_3|LDD, 0, 0, EVA, 0 }, -{"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{"lwle", "t,+j(b)", 0x7c000019, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, I37 }, +{"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA, I37 }, +{"lwre", "t,+j(b)", 0x7c00001a, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, I37 }, +{"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA, I37 }, {"sbe", "t,+j(b)", 0x7c00001c, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 }, {"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"sce", "t,+j(b)", 0x7c00001e, 0xfc00007f, MOD_1|RD_3|SM, 0, 0, EVA, 0 }, @@ -2533,14 +2600,729 @@ const struct mips_opcode mips_builtin_opcodes[] = {"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA, 0 }, {"swe", "t,+j(b)", 0x7c00001f, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 }, {"swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"swle", "t,+j(b)", 0x7c000021, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 }, -{"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA, 0 }, -{"swre", "t,+j(b)", 0x7c000022, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 }, -{"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +{"swle", "t,+j(b)", 0x7c000021, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, I37 }, +{"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA, I37 }, +{"swre", "t,+j(b)", 0x7c000022, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, I37 }, +{"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA, I37 }, {"cachee", "k,+j(b)", 0x7c00001b, 0xfc00007f, RD_3, 0, 0, EVA, 0 }, {"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA, 0 }, -{"prefe", "k,+j(b)", 0x7c000023, 0xfc00007f, RD_3, 0, 0, EVA, 0 }, +{"prefe", "k,+j(b)", 0x7c000023, 0xfc00007f, RD_3|LM, 0, 0, EVA, 0 }, {"prefe", "k,A(b)", 0, (int) M_PREFE_AB, INSN_MACRO, 0, 0, EVA, 0 }, +/* MSA Extension. */ +{"sll.b", "+d,+e,+h", 0x7800000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sll.h", "+d,+e,+h", 0x7820000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sll.w", "+d,+e,+h", 0x7840000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sll.d", "+d,+e,+h", 0x7860000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"slli.b", "+d,+e,+!", 0x78700009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"slli.h", "+d,+e,+@", 0x78600009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"slli.w", "+d,+e,+x", 0x78400009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"slli.d", "+d,+e,+#", 0x78000009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"sra.b", "+d,+e,+h", 0x7880000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sra.h", "+d,+e,+h", 0x78a0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sra.w", "+d,+e,+h", 0x78c0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sra.d", "+d,+e,+h", 0x78e0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srai.b", "+d,+e,+!", 0x78f00009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srai.h", "+d,+e,+@", 0x78e00009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srai.w", "+d,+e,+x", 0x78c00009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srai.d", "+d,+e,+#", 0x78800009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srl.b", "+d,+e,+h", 0x7900000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srl.h", "+d,+e,+h", 0x7920000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srl.w", "+d,+e,+h", 0x7940000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srl.d", "+d,+e,+h", 0x7960000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srli.b", "+d,+e,+!", 0x79700009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srli.h", "+d,+e,+@", 0x79600009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srli.w", "+d,+e,+x", 0x79400009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srli.d", "+d,+e,+#", 0x79000009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bclr.b", "+d,+e,+h", 0x7980000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bclr.h", "+d,+e,+h", 0x79a0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bclr.w", "+d,+e,+h", 0x79c0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bclr.d", "+d,+e,+h", 0x79e0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bclri.b", "+d,+e,+!", 0x79f00009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bclri.h", "+d,+e,+@", 0x79e00009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bclri.w", "+d,+e,+x", 0x79c00009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bclri.d", "+d,+e,+#", 0x79800009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bset.b", "+d,+e,+h", 0x7a00000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bset.h", "+d,+e,+h", 0x7a20000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bset.w", "+d,+e,+h", 0x7a40000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bset.d", "+d,+e,+h", 0x7a60000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bseti.b", "+d,+e,+!", 0x7a700009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bseti.h", "+d,+e,+@", 0x7a600009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bseti.w", "+d,+e,+x", 0x7a400009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bseti.d", "+d,+e,+#", 0x7a000009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bneg.b", "+d,+e,+h", 0x7a80000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bneg.h", "+d,+e,+h", 0x7aa0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bneg.w", "+d,+e,+h", 0x7ac0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bneg.d", "+d,+e,+h", 0x7ae0000d, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bnegi.b", "+d,+e,+!", 0x7af00009, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bnegi.h", "+d,+e,+@", 0x7ae00009, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bnegi.w", "+d,+e,+x", 0x7ac00009, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bnegi.d", "+d,+e,+#", 0x7a800009, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"binsl.b", "+d,+e,+h", 0x7b00000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"binsl.h", "+d,+e,+h", 0x7b20000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"binsl.w", "+d,+e,+h", 0x7b40000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"binsl.d", "+d,+e,+h", 0x7b60000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"binsli.b", "+d,+e,+!", 0x7b700009, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"binsli.h", "+d,+e,+@", 0x7b600009, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"binsli.w", "+d,+e,+x", 0x7b400009, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"binsli.d", "+d,+e,+#", 0x7b000009, 0xffc0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"binsr.b", "+d,+e,+h", 0x7b80000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"binsr.h", "+d,+e,+h", 0x7ba0000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"binsr.w", "+d,+e,+h", 0x7bc0000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"binsr.d", "+d,+e,+h", 0x7be0000d, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"binsri.b", "+d,+e,+!", 0x7bf00009, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"binsri.h", "+d,+e,+@", 0x7be00009, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"binsri.w", "+d,+e,+x", 0x7bc00009, 0xffe0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"binsri.d", "+d,+e,+#", 0x7b800009, 0xffc0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"addv.b", "+d,+e,+h", 0x7800000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"addv.h", "+d,+e,+h", 0x7820000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"addv.w", "+d,+e,+h", 0x7840000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"addv.d", "+d,+e,+h", 0x7860000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"addvi.b", "+d,+e,+$", 0x78000006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"addvi.h", "+d,+e,+$", 0x78200006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"addvi.w", "+d,+e,+$", 0x78400006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"addvi.d", "+d,+e,+$", 0x78600006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"subv.b", "+d,+e,+h", 0x7880000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subv.h", "+d,+e,+h", 0x78a0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subv.w", "+d,+e,+h", 0x78c0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subv.d", "+d,+e,+h", 0x78e0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subvi.b", "+d,+e,+$", 0x78800006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"subvi.h", "+d,+e,+$", 0x78a00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"subvi.w", "+d,+e,+$", 0x78c00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"subvi.d", "+d,+e,+$", 0x78e00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"max_s.b", "+d,+e,+h", 0x7900000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_s.h", "+d,+e,+h", 0x7920000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_s.w", "+d,+e,+h", 0x7940000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_s.d", "+d,+e,+h", 0x7960000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"maxi_s.b", "+d,+e,+%", 0x79000006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"maxi_s.h", "+d,+e,+%", 0x79200006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"maxi_s.w", "+d,+e,+%", 0x79400006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"maxi_s.d", "+d,+e,+%", 0x79600006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"max_u.b", "+d,+e,+h", 0x7980000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_u.h", "+d,+e,+h", 0x79a0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_u.w", "+d,+e,+h", 0x79c0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_u.d", "+d,+e,+h", 0x79e0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"maxi_u.b", "+d,+e,+$", 0x79800006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"maxi_u.h", "+d,+e,+$", 0x79a00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"maxi_u.w", "+d,+e,+$", 0x79c00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"maxi_u.d", "+d,+e,+$", 0x79e00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"min_s.b", "+d,+e,+h", 0x7a00000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_s.h", "+d,+e,+h", 0x7a20000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_s.w", "+d,+e,+h", 0x7a40000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_s.d", "+d,+e,+h", 0x7a60000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mini_s.b", "+d,+e,+%", 0x7a000006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"mini_s.h", "+d,+e,+%", 0x7a200006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"mini_s.w", "+d,+e,+%", 0x7a400006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"mini_s.d", "+d,+e,+%", 0x7a600006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"min_u.b", "+d,+e,+h", 0x7a80000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_u.h", "+d,+e,+h", 0x7aa0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_u.w", "+d,+e,+h", 0x7ac0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_u.d", "+d,+e,+h", 0x7ae0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mini_u.b", "+d,+e,+$", 0x7a800006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"mini_u.h", "+d,+e,+$", 0x7aa00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"mini_u.w", "+d,+e,+$", 0x7ac00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"mini_u.d", "+d,+e,+$", 0x7ae00006, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"max_a.b", "+d,+e,+h", 0x7b00000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_a.h", "+d,+e,+h", 0x7b20000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_a.w", "+d,+e,+h", 0x7b40000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"max_a.d", "+d,+e,+h", 0x7b60000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_a.b", "+d,+e,+h", 0x7b80000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_a.h", "+d,+e,+h", 0x7ba0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_a.w", "+d,+e,+h", 0x7bc0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"min_a.d", "+d,+e,+h", 0x7be0000e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ceq.b", "+d,+e,+h", 0x7800000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ceq.h", "+d,+e,+h", 0x7820000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ceq.w", "+d,+e,+h", 0x7840000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ceq.d", "+d,+e,+h", 0x7860000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ceqi.b", "+d,+e,+%", 0x78000007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ceqi.h", "+d,+e,+%", 0x78200007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ceqi.w", "+d,+e,+%", 0x78400007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ceqi.d", "+d,+e,+%", 0x78600007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clt_s.b", "+d,+e,+h", 0x7900000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clt_s.h", "+d,+e,+h", 0x7920000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clt_s.w", "+d,+e,+h", 0x7940000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clt_s.d", "+d,+e,+h", 0x7960000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clti_s.b", "+d,+e,+%", 0x79000007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clti_s.h", "+d,+e,+%", 0x79200007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clti_s.w", "+d,+e,+%", 0x79400007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clti_s.d", "+d,+e,+%", 0x79600007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clt_u.b", "+d,+e,+h", 0x7980000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clt_u.h", "+d,+e,+h", 0x79a0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clt_u.w", "+d,+e,+h", 0x79c0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clt_u.d", "+d,+e,+h", 0x79e0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clti_u.b", "+d,+e,+$", 0x79800007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clti_u.h", "+d,+e,+$", 0x79a00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clti_u.w", "+d,+e,+$", 0x79c00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clti_u.d", "+d,+e,+$", 0x79e00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"cle_s.b", "+d,+e,+h", 0x7a00000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"cle_s.h", "+d,+e,+h", 0x7a20000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"cle_s.w", "+d,+e,+h", 0x7a40000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"cle_s.d", "+d,+e,+h", 0x7a60000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clei_s.b", "+d,+e,+%", 0x7a000007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clei_s.h", "+d,+e,+%", 0x7a200007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clei_s.w", "+d,+e,+%", 0x7a400007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clei_s.d", "+d,+e,+%", 0x7a600007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"cle_u.b", "+d,+e,+h", 0x7a80000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"cle_u.h", "+d,+e,+h", 0x7aa0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"cle_u.w", "+d,+e,+h", 0x7ac0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"cle_u.d", "+d,+e,+h", 0x7ae0000f, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"clei_u.b", "+d,+e,+$", 0x7a800007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clei_u.h", "+d,+e,+$", 0x7aa00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clei_u.w", "+d,+e,+$", 0x7ac00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"clei_u.d", "+d,+e,+$", 0x7ae00007, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ld.b", "+d,+T(d)", 0x78000020, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, +{"ld.h", "+d,+U(d)", 0x78000021, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, +{"ld.w", "+d,+V(d)", 0x78000022, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, +{"ld.d", "+d,+W(d)", 0x78000023, 0xfc00003f, WR_1|RD_3|LM, 0, 0, MSA, 0 }, +{"st.b", "+d,+T(d)", 0x78000024, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, +{"st.h", "+d,+U(d)", 0x78000025, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, +{"st.w", "+d,+V(d)", 0x78000026, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, +{"st.d", "+d,+W(d)", 0x78000027, 0xfc00003f, RD_1|RD_3|SM, 0, 0, MSA, 0 }, +{"sat_s.b", "+d,+e,+!", 0x7870000a, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"sat_s.h", "+d,+e,+@", 0x7860000a, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"sat_s.w", "+d,+e,+x", 0x7840000a, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"sat_s.d", "+d,+e,+#", 0x7800000a, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"sat_u.b", "+d,+e,+!", 0x78f0000a, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"sat_u.h", "+d,+e,+@", 0x78e0000a, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"sat_u.w", "+d,+e,+x", 0x78c0000a, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"sat_u.d", "+d,+e,+#", 0x7880000a, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"add_a.b", "+d,+e,+h", 0x78000010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"add_a.h", "+d,+e,+h", 0x78200010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"add_a.w", "+d,+e,+h", 0x78400010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"add_a.d", "+d,+e,+h", 0x78600010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_a.b", "+d,+e,+h", 0x78800010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_a.h", "+d,+e,+h", 0x78a00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_a.w", "+d,+e,+h", 0x78c00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_a.d", "+d,+e,+h", 0x78e00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_s.b", "+d,+e,+h", 0x79000010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_s.h", "+d,+e,+h", 0x79200010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_s.w", "+d,+e,+h", 0x79400010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_s.d", "+d,+e,+h", 0x79600010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_u.b", "+d,+e,+h", 0x79800010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_u.h", "+d,+e,+h", 0x79a00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_u.w", "+d,+e,+h", 0x79c00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"adds_u.d", "+d,+e,+h", 0x79e00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ave_s.b", "+d,+e,+h", 0x7a000010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ave_s.h", "+d,+e,+h", 0x7a200010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ave_s.w", "+d,+e,+h", 0x7a400010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ave_s.d", "+d,+e,+h", 0x7a600010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ave_u.b", "+d,+e,+h", 0x7a800010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ave_u.h", "+d,+e,+h", 0x7aa00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ave_u.w", "+d,+e,+h", 0x7ac00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ave_u.d", "+d,+e,+h", 0x7ae00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"aver_s.b", "+d,+e,+h", 0x7b000010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"aver_s.h", "+d,+e,+h", 0x7b200010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"aver_s.w", "+d,+e,+h", 0x7b400010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"aver_s.d", "+d,+e,+h", 0x7b600010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"aver_u.b", "+d,+e,+h", 0x7b800010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"aver_u.h", "+d,+e,+h", 0x7ba00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"aver_u.w", "+d,+e,+h", 0x7bc00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"aver_u.d", "+d,+e,+h", 0x7be00010, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subs_s.b", "+d,+e,+h", 0x78000011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subs_s.h", "+d,+e,+h", 0x78200011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subs_s.w", "+d,+e,+h", 0x78400011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subs_s.d", "+d,+e,+h", 0x78600011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subs_u.b", "+d,+e,+h", 0x78800011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subs_u.h", "+d,+e,+h", 0x78a00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subs_u.w", "+d,+e,+h", 0x78c00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subs_u.d", "+d,+e,+h", 0x78e00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subsus_u.b", "+d,+e,+h", 0x79000011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subsus_u.h", "+d,+e,+h", 0x79200011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subsus_u.w", "+d,+e,+h", 0x79400011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subsus_u.d", "+d,+e,+h", 0x79600011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subsuu_s.b", "+d,+e,+h", 0x79800011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subsuu_s.h", "+d,+e,+h", 0x79a00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subsuu_s.w", "+d,+e,+h", 0x79c00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"subsuu_s.d", "+d,+e,+h", 0x79e00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"asub_s.b", "+d,+e,+h", 0x7a000011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"asub_s.h", "+d,+e,+h", 0x7a200011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"asub_s.w", "+d,+e,+h", 0x7a400011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"asub_s.d", "+d,+e,+h", 0x7a600011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"asub_u.b", "+d,+e,+h", 0x7a800011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"asub_u.h", "+d,+e,+h", 0x7aa00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"asub_u.w", "+d,+e,+h", 0x7ac00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"asub_u.d", "+d,+e,+h", 0x7ae00011, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mulv.b", "+d,+e,+h", 0x78000012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mulv.h", "+d,+e,+h", 0x78200012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mulv.w", "+d,+e,+h", 0x78400012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mulv.d", "+d,+e,+h", 0x78600012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"maddv.b", "+d,+e,+h", 0x78800012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"maddv.h", "+d,+e,+h", 0x78a00012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"maddv.w", "+d,+e,+h", 0x78c00012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"maddv.d", "+d,+e,+h", 0x78e00012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"msubv.b", "+d,+e,+h", 0x79000012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"msubv.h", "+d,+e,+h", 0x79200012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"msubv.w", "+d,+e,+h", 0x79400012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"msubv.d", "+d,+e,+h", 0x79600012, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"div_s.b", "+d,+e,+h", 0x7a000012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"div_s.h", "+d,+e,+h", 0x7a200012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"div_s.w", "+d,+e,+h", 0x7a400012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"div_s.d", "+d,+e,+h", 0x7a600012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"div_u.b", "+d,+e,+h", 0x7a800012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"div_u.h", "+d,+e,+h", 0x7aa00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"div_u.w", "+d,+e,+h", 0x7ac00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"div_u.d", "+d,+e,+h", 0x7ae00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mod_s.b", "+d,+e,+h", 0x7b000012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mod_s.h", "+d,+e,+h", 0x7b200012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mod_s.w", "+d,+e,+h", 0x7b400012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mod_s.d", "+d,+e,+h", 0x7b600012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mod_u.b", "+d,+e,+h", 0x7b800012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mod_u.h", "+d,+e,+h", 0x7ba00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mod_u.w", "+d,+e,+h", 0x7bc00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mod_u.d", "+d,+e,+h", 0x7be00012, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dotp_s.h", "+d,+e,+h", 0x78200013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dotp_s.w", "+d,+e,+h", 0x78400013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dotp_s.d", "+d,+e,+h", 0x78600013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dotp_u.h", "+d,+e,+h", 0x78a00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dotp_u.w", "+d,+e,+h", 0x78c00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dotp_u.d", "+d,+e,+h", 0x78e00013, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpadd_s.h", "+d,+e,+h", 0x79200013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpadd_s.w", "+d,+e,+h", 0x79400013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpadd_s.d", "+d,+e,+h", 0x79600013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpadd_u.h", "+d,+e,+h", 0x79a00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpadd_u.w", "+d,+e,+h", 0x79c00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpadd_u.d", "+d,+e,+h", 0x79e00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpsub_s.h", "+d,+e,+h", 0x7a200013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpsub_s.w", "+d,+e,+h", 0x7a400013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpsub_s.d", "+d,+e,+h", 0x7a600013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpsub_u.h", "+d,+e,+h", 0x7aa00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpsub_u.w", "+d,+e,+h", 0x7ac00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"dpsub_u.d", "+d,+e,+h", 0x7ae00013, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sld.b", "+d,+e+*", 0x78000014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sld.h", "+d,+e+*", 0x78200014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sld.w", "+d,+e+*", 0x78400014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sld.d", "+d,+e+*", 0x78600014, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"sldi.b", "+d,+e+o", 0x78000019, 0xfff0003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"sldi.h", "+d,+e+u", 0x78200019, 0xfff8003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"sldi.w", "+d,+e+v", 0x78300019, 0xfffc003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"sldi.d", "+d,+e+w", 0x78380019, 0xfffe003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"splat.b", "+d,+e+*", 0x78800014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"splat.h", "+d,+e+*", 0x78a00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"splat.w", "+d,+e+*", 0x78c00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"splat.d", "+d,+e+*", 0x78e00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"splati.b", "+d,+e+o", 0x78400019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"splati.h", "+d,+e+u", 0x78600019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"splati.w", "+d,+e+v", 0x78700019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"splati.d", "+d,+e+w", 0x78780019, 0xfffe003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"pckev.b", "+d,+e,+h", 0x79000014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"pckev.h", "+d,+e,+h", 0x79200014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"pckev.w", "+d,+e,+h", 0x79400014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"pckev.d", "+d,+e,+h", 0x79600014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"pckod.b", "+d,+e,+h", 0x79800014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"pckod.h", "+d,+e,+h", 0x79a00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"pckod.w", "+d,+e,+h", 0x79c00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"pckod.d", "+d,+e,+h", 0x79e00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvl.b", "+d,+e,+h", 0x7a000014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvl.h", "+d,+e,+h", 0x7a200014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvl.w", "+d,+e,+h", 0x7a400014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvl.d", "+d,+e,+h", 0x7a600014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvr.b", "+d,+e,+h", 0x7a800014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvr.h", "+d,+e,+h", 0x7aa00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvr.w", "+d,+e,+h", 0x7ac00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvr.d", "+d,+e,+h", 0x7ae00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvev.b", "+d,+e,+h", 0x7b000014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvev.h", "+d,+e,+h", 0x7b200014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvev.w", "+d,+e,+h", 0x7b400014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvev.d", "+d,+e,+h", 0x7b600014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvod.b", "+d,+e,+h", 0x7b800014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvod.h", "+d,+e,+h", 0x7ba00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvod.w", "+d,+e,+h", 0x7bc00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ilvod.d", "+d,+e,+h", 0x7be00014, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"vshf.b", "+d,+e,+h", 0x78000015, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"vshf.h", "+d,+e,+h", 0x78200015, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"vshf.w", "+d,+e,+h", 0x78400015, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"vshf.d", "+d,+e,+h", 0x78600015, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srar.b", "+d,+e,+h", 0x78800015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srar.h", "+d,+e,+h", 0x78a00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srar.w", "+d,+e,+h", 0x78c00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srar.d", "+d,+e,+h", 0x78e00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srari.b", "+d,+e,+!", 0x7970000a, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srari.h", "+d,+e,+@", 0x7960000a, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srari.w", "+d,+e,+x", 0x7940000a, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srari.d", "+d,+e,+#", 0x7900000a, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srlr.b", "+d,+e,+h", 0x79000015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srlr.h", "+d,+e,+h", 0x79200015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srlr.w", "+d,+e,+h", 0x79400015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srlr.d", "+d,+e,+h", 0x79600015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"srlri.b", "+d,+e,+!", 0x79f0000a, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srlri.h", "+d,+e,+@", 0x79e0000a, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srlri.w", "+d,+e,+x", 0x79c0000a, 0xffe0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"srlri.d", "+d,+e,+#", 0x7980000a, 0xffc0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"hadd_s.h", "+d,+e,+h", 0x7a200015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hadd_s.w", "+d,+e,+h", 0x7a400015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hadd_s.d", "+d,+e,+h", 0x7a600015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hadd_u.h", "+d,+e,+h", 0x7aa00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hadd_u.w", "+d,+e,+h", 0x7ac00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hadd_u.d", "+d,+e,+h", 0x7ae00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hsub_s.h", "+d,+e,+h", 0x7b200015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hsub_s.w", "+d,+e,+h", 0x7b400015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hsub_s.d", "+d,+e,+h", 0x7b600015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hsub_u.h", "+d,+e,+h", 0x7ba00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hsub_u.w", "+d,+e,+h", 0x7bc00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"hsub_u.d", "+d,+e,+h", 0x7be00015, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"and.v", "+d,+e,+h", 0x7800001e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"andi.b", "+d,+e,+|", 0x78000000, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"or.v", "+d,+e,+h", 0x7820001e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ori.b", "+d,+e,+|", 0x79000000, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nor.v", "+d,+e,+h", 0x7840001e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"nori.b", "+d,+e,+|", 0x7a000000, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"xor.v", "+d,+e,+h", 0x7860001e, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"xori.b", "+d,+e,+|", 0x7b000000, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bmnz.v", "+d,+e,+h", 0x7880001e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bmnzi.b", "+d,+e,+|", 0x78000001, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"bmz.v", "+d,+e,+h", 0x78a0001e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bmzi.b", "+d,+e,+|", 0x79000001, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"bsel.v", "+d,+e,+h", 0x78c0001e, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"bseli.b", "+d,+e,+|", 0x7a000001, 0xff00003f, MOD_1|RD_2, 0, 0, MSA, 0 }, +{"shf.b", "+d,+e,+|", 0x78000002, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"shf.h", "+d,+e,+|", 0x79000002, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"shf.w", "+d,+e,+|", 0x7a000002, 0xff00003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"bnz.v", "+h,p", 0x45e00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"bz.v", "+h,p", 0x45600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"fill.b", "+d,d", 0x7b00001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fill.h", "+d,d", 0x7b01001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fill.w", "+d,d", 0x7b02001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fill.d", "+d,d", 0x7b03001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA64, 0 }, +{"pcnt.b", "+d,+e", 0x7b04001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"pcnt.h", "+d,+e", 0x7b05001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"pcnt.w", "+d,+e", 0x7b06001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"pcnt.d", "+d,+e", 0x7b07001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nloc.b", "+d,+e", 0x7b08001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nloc.h", "+d,+e", 0x7b09001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nloc.w", "+d,+e", 0x7b0a001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nloc.d", "+d,+e", 0x7b0b001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nlzc.b", "+d,+e", 0x7b0c001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nlzc.h", "+d,+e", 0x7b0d001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nlzc.w", "+d,+e", 0x7b0e001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"nlzc.d", "+d,+e", 0x7b0f001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_s.b", "+k,+e+o", 0x78800019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_s.h", "+k,+e+u", 0x78a00019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_s.w", "+k,+e+v", 0x78b00019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_s.d", "+k,+e+w", 0x78b80019, 0xfffe003f, WR_1|RD_2, 0, 0, MSA64, 0 }, +{"copy_u.b", "+k,+e+o", 0x78c00019, 0xfff0003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_u.h", "+k,+e+u", 0x78e00019, 0xfff8003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_u.w", "+k,+e+v", 0x78f00019, 0xfffc003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"copy_u.d", "+k,+e+w", 0x78f80019, 0xfffe003f, WR_1|RD_2, 0, 0, MSA64, 0 }, +{"insert.b", "+d+o,d", 0x79000019, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insert.h", "+d+u,d", 0x79200019, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insert.w", "+d+v,d", 0x79300019, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insert.d", "+d+w,d", 0x79380019, 0xfffe003f, MOD_1|RD_3, 0, 0, MSA64, 0 }, +{"insve.b", "+d+o,+e+&", 0x79400019, 0xfff0003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insve.h", "+d+u,+e+&", 0x79600019, 0xfff8003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insve.w", "+d+v,+e+&", 0x79700019, 0xfffc003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"insve.d", "+d+w,+e+&", 0x79780019, 0xfffe003f, MOD_1|RD_3, 0, 0, MSA, 0 }, +{"bnz.b", "+h,p", 0x47800000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"bnz.h", "+h,p", 0x47a00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"bnz.w", "+h,p", 0x47c00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"bnz.d", "+h,p", 0x47e00000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"bz.b", "+h,p", 0x47000000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"bz.h", "+h,p", 0x47200000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"bz.w", "+h,p", 0x47400000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"bz.d", "+h,p", 0x47600000, 0xffe00000, RD_1|CBD, 0, 0, MSA, 0 }, +{"ldi.b", "+d,+^", 0x7b000007, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, +{"ldi.h", "+d,+^", 0x7b200007, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, +{"ldi.w", "+d,+^", 0x7b400007, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, +{"ldi.d", "+d,+^", 0x7b600007, 0xffe0003f, WR_1, 0, 0, MSA, 0 }, +{"fcaf.w", "+d,+e,+h", 0x7800001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcaf.d", "+d,+e,+h", 0x7820001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcun.w", "+d,+e,+h", 0x7840001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcun.d", "+d,+e,+h", 0x7860001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fceq.w", "+d,+e,+h", 0x7880001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fceq.d", "+d,+e,+h", 0x78a0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcueq.w", "+d,+e,+h", 0x78c0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcueq.d", "+d,+e,+h", 0x78e0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fclt.w", "+d,+e,+h", 0x7900001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fclt.d", "+d,+e,+h", 0x7920001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcult.w", "+d,+e,+h", 0x7940001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcult.d", "+d,+e,+h", 0x7960001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcle.w", "+d,+e,+h", 0x7980001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcle.d", "+d,+e,+h", 0x79a0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcule.w", "+d,+e,+h", 0x79c0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcule.d", "+d,+e,+h", 0x79e0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsaf.w", "+d,+e,+h", 0x7a00001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsaf.d", "+d,+e,+h", 0x7a20001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsun.w", "+d,+e,+h", 0x7a40001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsun.d", "+d,+e,+h", 0x7a60001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fseq.w", "+d,+e,+h", 0x7a80001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fseq.d", "+d,+e,+h", 0x7aa0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsueq.w", "+d,+e,+h", 0x7ac0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsueq.d", "+d,+e,+h", 0x7ae0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fslt.w", "+d,+e,+h", 0x7b00001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fslt.d", "+d,+e,+h", 0x7b20001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsult.w", "+d,+e,+h", 0x7b40001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsult.d", "+d,+e,+h", 0x7b60001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsle.w", "+d,+e,+h", 0x7b80001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsle.d", "+d,+e,+h", 0x7ba0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsule.w", "+d,+e,+h", 0x7bc0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsule.d", "+d,+e,+h", 0x7be0001a, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fadd.w", "+d,+e,+h", 0x7800001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fadd.d", "+d,+e,+h", 0x7820001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsub.w", "+d,+e,+h", 0x7840001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsub.d", "+d,+e,+h", 0x7860001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmul.w", "+d,+e,+h", 0x7880001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmul.d", "+d,+e,+h", 0x78a0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fdiv.w", "+d,+e,+h", 0x78c0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fdiv.d", "+d,+e,+h", 0x78e0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmadd.w", "+d,+e,+h", 0x7900001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmadd.d", "+d,+e,+h", 0x7920001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmsub.w", "+d,+e,+h", 0x7940001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmsub.d", "+d,+e,+h", 0x7960001b, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fexp2.w", "+d,+e,+h", 0x79c0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fexp2.d", "+d,+e,+h", 0x79e0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fexdo.h", "+d,+e,+h", 0x7a00001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fexdo.w", "+d,+e,+h", 0x7a20001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ftq.h", "+d,+e,+h", 0x7a80001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"ftq.w", "+d,+e,+h", 0x7aa0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmin.w", "+d,+e,+h", 0x7b00001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmin.d", "+d,+e,+h", 0x7b20001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmin_a.w", "+d,+e,+h", 0x7b40001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmin_a.d", "+d,+e,+h", 0x7b60001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmax.w", "+d,+e,+h", 0x7b80001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmax.d", "+d,+e,+h", 0x7ba0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmax_a.w", "+d,+e,+h", 0x7bc0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fmax_a.d", "+d,+e,+h", 0x7be0001b, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcor.w", "+d,+e,+h", 0x7840001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcor.d", "+d,+e,+h", 0x7860001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcune.w", "+d,+e,+h", 0x7880001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcune.d", "+d,+e,+h", 0x78a0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcne.w", "+d,+e,+h", 0x78c0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fcne.d", "+d,+e,+h", 0x78e0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mul_q.h", "+d,+e,+h", 0x7900001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mul_q.w", "+d,+e,+h", 0x7920001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"madd_q.h", "+d,+e,+h", 0x7940001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"madd_q.w", "+d,+e,+h", 0x7960001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"msub_q.h", "+d,+e,+h", 0x7980001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"msub_q.w", "+d,+e,+h", 0x79a0001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsor.w", "+d,+e,+h", 0x7a40001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsor.d", "+d,+e,+h", 0x7a60001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsune.w", "+d,+e,+h", 0x7a80001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsune.d", "+d,+e,+h", 0x7aa0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsne.w", "+d,+e,+h", 0x7ac0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fsne.d", "+d,+e,+h", 0x7ae0001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mulr_q.h", "+d,+e,+h", 0x7b00001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"mulr_q.w", "+d,+e,+h", 0x7b20001c, 0xffe0003f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"maddr_q.h", "+d,+e,+h", 0x7b40001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"maddr_q.w", "+d,+e,+h", 0x7b60001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"msubr_q.h", "+d,+e,+h", 0x7b80001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"msubr_q.w", "+d,+e,+h", 0x7ba0001c, 0xffe0003f, MOD_1|RD_2|RD_3, 0, 0, MSA, 0 }, +{"fclass.w", "+d,+e", 0x7b20001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fclass.d", "+d,+e", 0x7b21001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ftrunc_s.w", "+d,+e", 0x7b22001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ftrunc_s.d", "+d,+e", 0x7b23001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ftrunc_u.w", "+d,+e", 0x7b24001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ftrunc_u.d", "+d,+e", 0x7b25001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fsqrt.w", "+d,+e", 0x7b26001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fsqrt.d", "+d,+e", 0x7b27001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"frsqrt.w", "+d,+e", 0x7b28001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"frsqrt.d", "+d,+e", 0x7b29001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"frcp.w", "+d,+e", 0x7b2a001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"frcp.d", "+d,+e", 0x7b2b001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"frint.w", "+d,+e", 0x7b2c001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"frint.d", "+d,+e", 0x7b2d001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"flog2.w", "+d,+e", 0x7b2e001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"flog2.d", "+d,+e", 0x7b2f001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fexupl.w", "+d,+e", 0x7b30001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fexupl.d", "+d,+e", 0x7b31001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fexupr.w", "+d,+e", 0x7b32001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"fexupr.d", "+d,+e", 0x7b33001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ffql.w", "+d,+e", 0x7b34001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ffql.d", "+d,+e", 0x7b35001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ffqr.w", "+d,+e", 0x7b36001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ffqr.d", "+d,+e", 0x7b37001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ftint_s.w", "+d,+e", 0x7b38001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ftint_s.d", "+d,+e", 0x7b39001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ftint_u.w", "+d,+e", 0x7b3a001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ftint_u.d", "+d,+e", 0x7b3b001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ffint_s.w", "+d,+e", 0x7b3c001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ffint_s.d", "+d,+e", 0x7b3d001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ffint_u.w", "+d,+e", 0x7b3e001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ffint_u.d", "+d,+e", 0x7b3f001e, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, +{"ctcmsa", "+l,d", 0x783e0019, 0xffff003f, RD_2|COD, 0, 0, MSA, 0 }, +{"cfcmsa", "+k,+n", 0x787e0019, 0xffff003f, WR_1|COD, 0, 0, MSA, 0 }, +{"move.v", "+d,+e", 0x78be0019, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 }, + +/* User Defined Instruction. */ +{"udi0", "s,t,d,+1", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi0", "s,t,+2", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi0", "s,+3", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi0", "+4", 0x70000010, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi1", "s,t,d,+1", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi1", "s,t,+2", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi1", "s,+3", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi1", "+4", 0x70000011, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi2", "s,t,d,+1", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi2", "s,t,+2", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi2", "s,+3", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi2", "+4", 0x70000012, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi3", "s,t,d,+1", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi3", "s,t,+2", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi3", "s,+3", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi3", "+4", 0x70000013, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi4", "s,t,d,+1", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi4", "s,t,+2", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi4", "s,+3", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi4", "+4", 0x70000014, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi5", "s,t,d,+1", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi5", "s,t,+2", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi5", "s,+3", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi5", "+4", 0x70000015, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi6", "s,t,d,+1", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi6", "s,t,+2", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi6", "s,+3", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi6", "+4", 0x70000016, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi7", "s,t,d,+1", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi7", "s,t,+2", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi7", "s,+3", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi7", "+4", 0x70000017, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi8", "s,t,d,+1", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi8", "s,t,+2", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi8", "s,+3", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi8", "+4", 0x70000018, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi9", "s,t,d,+1", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi9", "s,t,+2", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi9", "s,+3", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi9", "+4", 0x70000019, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi10", "s,t,d,+1", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi10", "s,+3", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi10", "+4", 0x7000001a, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi11", "s,t,d,+1", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi11", "s,+3", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi11", "+4", 0x7000001b, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi12", "s,t,d,+1", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi12", "s,+3", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi12", "+4", 0x7000001c, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi13", "s,t,d,+1", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi13", "s,+3", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi13", "+4", 0x7000001d, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi14", "s,t,d,+1", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi14", "s,+3", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi14", "+4", 0x7000001e, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi15", "s,t,d,+1", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi15", "s,+3", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"udi15", "+4", 0x7000001f, 0xfc00003f, UDI, 0, I33, 0, 0 }, +{"lsa", "d,v,t,+~", 0x00000005, 0xfc00073f, WR_1|RD_2|RD_3, 0, I37, MSA, 0 }, +{"dlsa", "d,v,t,+~", 0x00000015, 0xfc00073f, WR_1|RD_2|RD_3, 0, I69, MSA64, 0 }, +/* MIPS r6. */ + +{"aui", "t,s,u", 0x3c000000, 0xfc000000, WR_1|RD_2, 0, I37, 0, 0 }, +{"auipc", "s,u", 0xec1e0000, 0xfc1f0000, WR_1|RD_pc, 0, I37, 0, 0 }, +{"daui", "t,s,u", 0x74000000, 0xfc000000, WR_1|RD_2, 0, I37, 0, 0 }, +{"dahi", "s,-d,u", 0x04060000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 }, +{"dati", "s,-d,u", 0x041e0000, 0xfc1f0000, MOD_1, 0, I69, 0, 0 }, + +{"align", "d,s,t,+I", 0x7c000220, 0xfc00073f, WR_1|RD_2|RD_3, 0, I37, 0, 0 }, +{"dalign", "d,s,t,+O", 0x7c000224, 0xfc00063f, WR_1|RD_2|RD_3, 0, I69, 0, 0 }, +{"bitswap", "d,t", 0x7c000020, 0xffe007ff, WR_1|RD_2, 0, I37, 0, 0 }, +{"dbitswap", "d,t", 0x7c000024, 0xffe007ff, WR_1|RD_2, 0, I69, 0, 0 }, + +{"bovc", "s,-w,p", 0x20000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, +{"bovc", "t,-x,p", 0x20000000, 0xfc000000, RD_1|RD_2|NODS, FS|INSN2_ALIAS, I37, 0, 0 }, +{"beqzalc", "-t,p", 0x20000000, 0xffe00000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, +{"beqc", "-s,-u,p", 0x20000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, +{"beqc", "t,-y,p", 0x20000000, 0xfc000000, RD_1|RD_2|NODS, FS|INSN2_ALIAS, I37, 0, 0 }, +{"bnvc", "s,-w,p", 0x60000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, +{"bnvc", "t,-x,p", 0x60000000, 0xfc000000, RD_1|RD_2|NODS, FS|INSN2_ALIAS, I37, 0, 0 }, +{"bnezalc", "-t,p", 0x60000000, 0xffe00000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, +{"bnec", "-s,-u,p", 0x60000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, +{"bnec", "t,-y,p", 0x60000000, 0xfc000000, RD_1|RD_2|NODS, FS|INSN2_ALIAS, I37, 0, 0 }, + +{"blezc", "-t,p", 0x58000000, 0xffe00000, RD_1|NODS, FS, I37, 0, 0 }, +{"bgezc", "+;,p", 0x58000000, 0xfc000000, RD_1|NODS, FS, I37, 0, 0 }, +{"bgec", "-s,-v,p", 0x58000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, +{"bgtzc", "-t,p", 0x5c000000, 0xffe00000, RD_1|NODS, FS, I37, 0, 0 }, +{"bltzc", "+;,p", 0x5c000000, 0xfc000000, RD_1|NODS, FS, I37, 0, 0 }, +{"bltc", "-s,-v,p", 0x5c000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, +{"blezalc", "-t,p", 0x18000000, 0xffe00000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, +{"bgezalc", "+;,p", 0x18000000, 0xfc000000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, +{"bgeuc", "-s,-v,p", 0x18000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, +{"bgtzalc", "-t,p", 0x1c000000, 0xffe00000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, +{"bltzalc", "+;,p", 0x1c000000, 0xfc000000, RD_1|WR_31|NODS, FS, I37, 0, 0 }, +{"bltuc", "-s,-v,p", 0x1c000000, 0xfc000000, RD_1|RD_2|NODS, FS, I37, 0, 0 }, + +{"beqzc", "-s,+\"", 0xd8000000, 0xfc000000, RD_1|NODS, FS, I37, 0, 0 }, +{"jrc", "t", 0xd8000000, 0xffe0ffff, RD_1|NODS, INSN2_ALIAS, I37, 0, 0 }, +{"jic", "t,j", 0xd8000000, 0xffe00000, RD_1|NODS, 0, I37, 0, 0 }, + +{"bnezc", "-s,+\"", 0xf8000000, 0xfc000000, RD_1|NODS, FS, I37, 0, 0 }, +{"jialc", "t,j", 0xf8000000, 0xffe00000, RD_1|NODS, 0, I37, 0, 0 }, + +{"cmp.af.s", "D,S,T", 0x46800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.af.d", "D,S,T", 0x46a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.eq.s", "D,S,T", 0x46800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.eq.d", "D,S,T", 0x46a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.le.s", "D,S,T", 0x46800006, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.le.d", "D,S,T", 0x46a00006, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.lt.s", "D,S,T", 0x46800004, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.lt.d", "D,S,T", 0x46a00004, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.ne.s", "D,S,T", 0x46800013, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.ne.d", "D,S,T", 0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.or.s", "D,S,T", 0x46800011, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.or.d", "D,S,T", 0x46a00011, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.ueq.s", "D,S,T", 0x46800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.ueq.d", "D,S,T", 0x46a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.ule.s", "D,S,T", 0x46800007, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.ule.d", "D,S,T", 0x46a00007, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.ult.s", "D,S,T", 0x46800005, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.ult.d", "D,S,T", 0x46a00005, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.un.s", "D,S,T", 0x46800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.un.d", "D,S,T", 0x46a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.une.s", "D,S,T", 0x46800012, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.une.d", "D,S,T", 0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.saf.s", "D,S,T", 0x46800008, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.saf.d", "D,S,T", 0x46a00008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.seq.s", "D,S,T", 0x4680000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.seq.d", "D,S,T", 0x46a0000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.sle.s", "D,S,T", 0x4680000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.sle.d", "D,S,T", 0x46a0000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.slt.s", "D,S,T", 0x4680000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.slt.d", "D,S,T", 0x46a0000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.sne.s", "D,S,T", 0x4680001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.sne.d", "D,S,T", 0x46a0001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.sor.s", "D,S,T", 0x46800019, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.sor.d", "D,S,T", 0x46a00019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.sueq.s", "D,S,T", 0x4680000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.sueq.d", "D,S,T", 0x46a0000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.sule.s", "D,S,T", 0x4680000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.sule.d", "D,S,T", 0x46a0000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.sult.s", "D,S,T", 0x4680000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.sult.d", "D,S,T", 0x46a0000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"cmp.sun.s", "D,S,T", 0x46800009, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.sun.d", "D,S,T", 0x46a00009, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.sune.s", "D,S,T", 0x4680001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"cmp.sune.d", "D,S,T", 0x46a0001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, + +{"maddf.s", "D,S,T", 0x46000018, 0xffe0003f, MOD_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"msubf.s", "D,S,T", 0x46000019, 0xffe0003f, MOD_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"maddf.d", "D,S,T", 0x46200018, 0xffe0003f, MOD_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"msubf.d", "D,S,T", 0x46200019, 0xffe0003f, MOD_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, + +{"rint.s", "D,S", 0x4600001a, 0xffff003f, WR_1|RD_2|FP_S, 0, I37, 0, 0 }, +{"rint.d", "D,S", 0x4620001a, 0xffff003f, WR_1|RD_2|FP_D, 0, I37, 0, 0 }, +{"class.s", "D,S", 0x4600001b, 0xffff003f, WR_1|RD_2|FP_S, 0, I37, 0, 0 }, +{"class.d", "D,S", 0x4620001b, 0xffff003f, WR_1|RD_2|FP_D, 0, I37, 0, 0 }, +{"min.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"max.d", "D,S,T", 0x4620001e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"mina.s", "D,S,T", 0x4600001d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"mina.d", "D,S,T", 0x4620001d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"maxa.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"maxa.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, + +{"sel.s", "D,S,T", 0x46000010, 0xffe0003f, MOD_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"sel.d", "D,S,T", 0x46200010, 0xffe0003f, MOD_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"selnez", "d,s,t", 0x00000037, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0 }, +{"selnez.s", "D,S,T", 0x46000017, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"selnez.d", "D,S,T", 0x46200017, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, +{"seleqz", "d,s,t", 0x00000035, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0 }, +{"seleqz.s", "D,S,T", 0x46000014, 0xffe0003f, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 }, +{"seleqz.d", "D,S,T", 0x46200014, 0xffe0003f, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 }, + +{"aluipc", "s,u", 0xec1f0000, 0xfc1f0000, WR_1|RD_pc, 0, I37, 0, 0 }, + /* No hazard protection on coprocessor instructions--they shouldn't change the state of the processor and if they do it's up to the user to put in nops as necessary. These are at the end so that the |