diff options
Diffstat (limited to 'binutils-2.24/include/elf')
| -rw-r--r-- | binutils-2.24/include/elf/ChangeLog | 9 | ||||
| -rw-r--r-- | binutils-2.24/include/elf/mips.h | 150 |
2 files changed, 157 insertions, 2 deletions
diff --git a/binutils-2.24/include/elf/ChangeLog b/binutils-2.24/include/elf/ChangeLog index cfc4895..6b90b78 100644 --- a/binutils-2.24/include/elf/ChangeLog +++ b/binutils-2.24/include/elf/ChangeLog @@ -1,3 +1,7 @@ +2014-02-06 Andrew Pinski <apinski@cavium.com> + + * mips.h (E_MIPS_MACH_OCTEON3): New machine flag. + 2013-11-17 H.J. Lu <hongjiu.lu@intel.com> * x86-64.h: Add R_X86_64_PC32_BND and R_X86_64_PLT32_BND. @@ -32,6 +36,11 @@ R_AARCH64_TLS_DTPMOD, R_AARCH64_TLS_DTPREL and R_AARCH64_TLS_TPREL with RELOC_MACROS_GEN_FUNC. +2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> + + * mips.h (enum): Add Tag_GNU_MIPS_ABI_MSA. + (enum): Add Val_GNU_MIPS_ABI_MSA_ANY and Val_GNU_MIPS_ABI_MSA_128. + 2013-09-17 Doug Gilmore <Doug.Gilmore@imgtec.com> * mips.h (EF_MIPS_FP64): New e_flags bit. diff --git a/binutils-2.24/include/elf/mips.h b/binutils-2.24/include/elf/mips.h index a26e3f4..cdde18b 100644 --- a/binutils-2.24/include/elf/mips.h +++ b/binutils-2.24/include/elf/mips.h @@ -89,7 +89,14 @@ START_RELOC_NUMBERS (elf_mips_reloc_type) RELOC_NUMBER (R_MIPS_TLS_TPREL_HI16, 49) RELOC_NUMBER (R_MIPS_TLS_TPREL_LO16, 50) RELOC_NUMBER (R_MIPS_GLOB_DAT, 51) - FAKE_RELOC (R_MIPS_max, 52) + /* Space to grow */ + RELOC_NUMBER (R_MIPS_PC21_S2, 60) + RELOC_NUMBER (R_MIPS_PC26_S2, 61) + RELOC_NUMBER (R_MIPS_PC18_S3, 62) + RELOC_NUMBER (R_MIPS_PC19_S2, 63) + RELOC_NUMBER (R_MIPS_PCHI16, 64) + RELOC_NUMBER (R_MIPS_PCLO16, 65) + FAKE_RELOC (R_MIPS_max, 66) /* These relocs are used for the mips16. */ FAKE_RELOC (R_MIPS16_min, 100) RELOC_NUMBER (R_MIPS16_26, 100) @@ -239,6 +246,12 @@ END_RELOC_NUMBERS (R_MIPS_maxext) /* -mips64r2 code. */ #define E_MIPS_ARCH_64R2 0x80000000 +/* -mips32r6 code. */ +#define E_MIPS_ARCH_32R6 0x90000000 + +/* -mips64r6 code. */ +#define E_MIPS_ARCH_64R6 0xa0000000 + /* The ABI of the file. Also see EF_MIPS_ABI2 above. */ #define EF_MIPS_ABI 0x0000F000 @@ -275,6 +288,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext) #define E_MIPS_MACH_OCTEON 0x008b0000 #define E_MIPS_MACH_XLR 0x008c0000 #define E_MIPS_MACH_OCTEON2 0x008d0000 +#define E_MIPS_MACH_OCTEON3 0x008e0000 #define E_MIPS_MACH_5400 0x00910000 #define E_MIPS_MACH_5900 0x00920000 #define E_MIPS_MACH_5500 0x00980000 @@ -429,6 +443,8 @@ END_RELOC_NUMBERS (R_MIPS_maxext) /* Runtime procedure descriptor table exception information (ucode) ??? */ #define SHT_MIPS_PDR_EXCEPTION 0x70000029 +/* ABI related flags section. */ +#define SHT_MIPS_ABIFLAGS 0x7000002a /* A section of type SHT_MIPS_LIBLIST contains an array of the following structure. The sh_link field is the section index of the @@ -594,6 +610,9 @@ extern void bfd_mips_elf32_swap_reginfo_out /* .MIPS.options section. */ #define PT_MIPS_OPTIONS 0x70000002 + +/* Records ABI related flags. */ +#define PT_MIPS_ABIFLAGS 0x70000003 /* Processor specific dynamic array tags. */ @@ -1049,6 +1068,58 @@ typedef struct bfd_vma ri_gp_value; } Elf64_Internal_RegInfo; +/* ABI Flags structure version 0. */ + +typedef struct +{ + /* Version of flags structure. */ + unsigned char version[2]; + /* The level of the ISA: 1-5, 32, 64. */ + unsigned char isa_level[1]; + /* The revision of ISA: 0 for MIPS V and below, 1-n otherwise. */ + unsigned char isa_rev[1]; + /* The size of general purpose registers. */ + unsigned char gpr_size[1]; + /* The size of co-processor 1 registers. */ + unsigned char cpr1_size[1]; + /* The size of co-processor 2 registers. */ + unsigned char cpr2_size[1]; + /* The floating-point ABI. */ + unsigned char fp_abi[1]; + /* Processor-specific extension. */ + unsigned char isa_ext[4]; + /* Mask of ASEs used. */ + unsigned char ases[4]; + /* Mask of general flags. */ + unsigned char flags1[4]; + unsigned char flags2[4]; +} Elf_External_ABIFlags_v0; + +typedef struct +{ + /* Version of flags structure. */ + unsigned short version; + /* The level of the ISA: 1-5, 32, 64. */ + unsigned char isa_level; + /* The revision of ISA: 0 for MIPS V and below, 1-n otherwise. */ + unsigned char isa_rev; + /* The size of general purpose registers. */ + unsigned char gpr_size; + /* The size of co-processor 1 registers. */ + unsigned char cpr1_size; + /* The size of co-processor 2 registers. */ + unsigned char cpr2_size; + /* The floating-point ABI. */ + unsigned char fp_abi; + /* Processor-specific extension. */ + unsigned long isa_ext; + /* Mask of ASEs used. */ + unsigned long ases; + /* Mask of general flags. */ + unsigned long flags1; + unsigned long flags2; +} Elf_Internal_ABIFlags_v0; + typedef struct { /* The hash value computed from the name of the corresponding @@ -1089,6 +1160,12 @@ extern void bfd_mips_elf64_swap_reginfo_in extern void bfd_mips_elf64_swap_reginfo_out (bfd *, const Elf64_Internal_RegInfo *, Elf64_External_RegInfo *); +/* MIPS ELF flags swapping routines. */ +extern void bfd_mips_elf_swap_abiflags_v0_in + (bfd *, const Elf_External_ABIFlags_v0 *, Elf_Internal_ABIFlags_v0 *); +extern void bfd_mips_elf_swap_abiflags_v0_out + (bfd *, const Elf_Internal_ABIFlags_v0 *, Elf_External_ABIFlags_v0 *); + /* Masks for the info work of an ODK_EXCEPTIONS descriptor. */ #define OEX_FPU_MIN 0x1f /* FPEs which must be enabled. */ #define OEX_FPU_MAX 0x1f00 /* FPEs which may be enabled. */ @@ -1126,6 +1203,55 @@ extern void bfd_mips_elf64_swap_reginfo_out /* Masks for the info word of an ODK_HWAND/ODK_HWOR descriptor. */ #define OHWA0_R4KEOP_CHECKED 0x00000001 #define OHWA0_R4KEOP_CLEAN 0x00000002 + +/* Values for the xxx_size bytes of an ABI flags structure. */ + +#define AFL_REG_NONE 0x00 /* No registers. */ +#define AFL_REG_32 0x01 /* 32-bit registers. */ +#define AFL_REG_64 0x02 /* 64-bit registers. */ +#define AFL_REG_128 0x03 /* 128-bit registers. */ + +/* Masks for the ases word of an ABI flags structure. */ + +#define AFL_ASE_DSP 0x00000001 /* DSP ASE. */ +#define AFL_ASE_DSPR2 0x00000002 /* DSP R2 ASE. */ +#define AFL_ASE_EVA 0x00000004 /* Enhanced VA Scheme. */ +#define AFL_ASE_MCU 0x00000008 /* MCU (MicroController) ASE. */ +#define AFL_ASE_MDMX 0x00000010 /* MDMX ASE. */ +#define AFL_ASE_MIPS3D 0x00000020 /* MIPS-3D ASE. */ +#define AFL_ASE_MT 0x00000040 /* MT ASE. */ +#define AFL_ASE_SMARTMIPS 0x00000080 /* SmartMIPS ASE. */ +#define AFL_ASE_VIRT 0x00000100 /* VZ ASE. */ +#define AFL_ASE_MSA 0x00000200 /* MSA ASE. */ +#define AFL_ASE_MIPS16 0x00000400 /* MIPS16 ASE. */ +#define AFL_ASE_MICROMIPS 0x00000800 /* MICROMIPS ASE. */ +#define AFL_ASE_XPA 0x00001000 /* XPA ASE. */ + +/* Values for the isa_ext word of an ABI flags structure. */ + +#define AFL_EXT_XLR 1 /* RMI Xlr instruction. */ +#define AFL_EXT_OCTEON2 2 /* Cavium Networks Octeon2. */ +#define AFL_EXT_OCTEONP 3 /* Cavium Networks OcteonP. */ +#define AFL_EXT_LOONGSON_3A 4 /* Loongson 3A. */ +#define AFL_EXT_OCTEON 5 /* Cavium Networks Octeon. */ +#define AFL_EXT_5900 6 /* MIPS R5900 instruction. */ +#define AFL_EXT_4650 7 /* MIPS R4650 instruction. */ +#define AFL_EXT_4010 8 /* LSI R4010 instruction. */ +#define AFL_EXT_4100 9 /* NEC VR4100 instruction. */ +#define AFL_EXT_3900 10 /* Toshiba R3900 instruction. */ +#define AFL_EXT_10000 11 /* MIPS R10000 instruction. */ +#define AFL_EXT_SB1 12 /* Broadcom SB-1 instruction. */ +#define AFL_EXT_4111 13 /* NEC VR4111/VR4181 instruction. */ +#define AFL_EXT_4120 14 /* NEC VR4120 instruction. */ +#define AFL_EXT_5400 15 /* NEC VR5400 instruction. */ +#define AFL_EXT_5500 16 /* NEC VR5500 instruction. */ +#define AFL_EXT_LOONGSON_2E 17 /* ST Microelectronics Loongson 2E. */ +#define AFL_EXT_LOONGSON_2F 18 /* ST Microelectronics Loongson 2F. */ + +/* Masks for the flags1 word of an ABI flags structure. */ +#define AFL_FLAGS1_ODDSPREG 1 /* Uses odd single-precision registers. */ + +extern unsigned int bfd_mips_isa_ext (bfd *); /* Object attribute tags. */ @@ -1135,6 +1261,9 @@ enum /* Floating-point ABI used by this object file. */ Tag_GNU_MIPS_ABI_FP = 4, + + /* MSA ABI used by this object file. */ + Tag_GNU_MIPS_ABI_MSA = 8, }; /* Object attribute values. */ @@ -1155,7 +1284,24 @@ enum Val_GNU_MIPS_ABI_FP_SOFT = 3, /* Using -mips32r2 -mfp64. */ - Val_GNU_MIPS_ABI_FP_64 = 4, + Val_GNU_MIPS_ABI_FP_OLD_64 = 4, + + /* Using -mfpxx */ + Val_GNU_MIPS_ABI_FP_XX = 5, + + /* Using -mips32r2 -mfp64. */ + Val_GNU_MIPS_ABI_FP_64 = 6, + + /* Using -mips32r2 -mfp64 -mno-odd-spreg. */ + Val_GNU_MIPS_ABI_FP_64A = 7, + + /* Values defined for Tag_GNU_MIPS_ABI_MSA. */ + + /* Not tagged or not using any ABIs affected by the differences. */ + Val_GNU_MIPS_ABI_MSA_ANY = 0, + + /* Using 128-bit MSA. */ + Val_GNU_MIPS_ABI_MSA_128 = 1, }; #endif /* _ELF_MIPS_H */ |