diff options
Diffstat (limited to 'binutils-2.24/include')
| -rw-r--r-- | binutils-2.24/include/ChangeLog | 4 | ||||
| -rw-r--r-- | binutils-2.24/include/elf/ChangeLog | 9 | ||||
| -rw-r--r-- | binutils-2.24/include/elf/mips.h | 150 | ||||
| -rw-r--r-- | binutils-2.24/include/opcode/ChangeLog | 46 | ||||
| -rw-r--r-- | binutils-2.24/include/opcode/mips.h | 255 |
5 files changed, 432 insertions, 32 deletions
diff --git a/binutils-2.24/include/ChangeLog b/binutils-2.24/include/ChangeLog index 17a62ba..6f099ad 100644 --- a/binutils-2.24/include/ChangeLog +++ b/binutils-2.24/include/ChangeLog @@ -1,3 +1,7 @@ +2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com> + + * opcode/mips.h (ASE_XPA): New define. + 2013-08-20 Alan Modra <amodra@gmail.com> * floatformat.h (floatformat_ibm_long_double): Delete. diff --git a/binutils-2.24/include/elf/ChangeLog b/binutils-2.24/include/elf/ChangeLog index cfc4895..6b90b78 100644 --- a/binutils-2.24/include/elf/ChangeLog +++ b/binutils-2.24/include/elf/ChangeLog @@ -1,3 +1,7 @@ +2014-02-06 Andrew Pinski <apinski@cavium.com> + + * mips.h (E_MIPS_MACH_OCTEON3): New machine flag. + 2013-11-17 H.J. Lu <hongjiu.lu@intel.com> * x86-64.h: Add R_X86_64_PC32_BND and R_X86_64_PLT32_BND. @@ -32,6 +36,11 @@ R_AARCH64_TLS_DTPMOD, R_AARCH64_TLS_DTPREL and R_AARCH64_TLS_TPREL with RELOC_MACROS_GEN_FUNC. +2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> + + * mips.h (enum): Add Tag_GNU_MIPS_ABI_MSA. + (enum): Add Val_GNU_MIPS_ABI_MSA_ANY and Val_GNU_MIPS_ABI_MSA_128. + 2013-09-17 Doug Gilmore <Doug.Gilmore@imgtec.com> * mips.h (EF_MIPS_FP64): New e_flags bit. diff --git a/binutils-2.24/include/elf/mips.h b/binutils-2.24/include/elf/mips.h index a26e3f4..cdde18b 100644 --- a/binutils-2.24/include/elf/mips.h +++ b/binutils-2.24/include/elf/mips.h @@ -89,7 +89,14 @@ START_RELOC_NUMBERS (elf_mips_reloc_type) RELOC_NUMBER (R_MIPS_TLS_TPREL_HI16, 49) RELOC_NUMBER (R_MIPS_TLS_TPREL_LO16, 50) RELOC_NUMBER (R_MIPS_GLOB_DAT, 51) - FAKE_RELOC (R_MIPS_max, 52) + /* Space to grow */ + RELOC_NUMBER (R_MIPS_PC21_S2, 60) + RELOC_NUMBER (R_MIPS_PC26_S2, 61) + RELOC_NUMBER (R_MIPS_PC18_S3, 62) + RELOC_NUMBER (R_MIPS_PC19_S2, 63) + RELOC_NUMBER (R_MIPS_PCHI16, 64) + RELOC_NUMBER (R_MIPS_PCLO16, 65) + FAKE_RELOC (R_MIPS_max, 66) /* These relocs are used for the mips16. */ FAKE_RELOC (R_MIPS16_min, 100) RELOC_NUMBER (R_MIPS16_26, 100) @@ -239,6 +246,12 @@ END_RELOC_NUMBERS (R_MIPS_maxext) /* -mips64r2 code. */ #define E_MIPS_ARCH_64R2 0x80000000 +/* -mips32r6 code. */ +#define E_MIPS_ARCH_32R6 0x90000000 + +/* -mips64r6 code. */ +#define E_MIPS_ARCH_64R6 0xa0000000 + /* The ABI of the file. Also see EF_MIPS_ABI2 above. */ #define EF_MIPS_ABI 0x0000F000 @@ -275,6 +288,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext) #define E_MIPS_MACH_OCTEON 0x008b0000 #define E_MIPS_MACH_XLR 0x008c0000 #define E_MIPS_MACH_OCTEON2 0x008d0000 +#define E_MIPS_MACH_OCTEON3 0x008e0000 #define E_MIPS_MACH_5400 0x00910000 #define E_MIPS_MACH_5900 0x00920000 #define E_MIPS_MACH_5500 0x00980000 @@ -429,6 +443,8 @@ END_RELOC_NUMBERS (R_MIPS_maxext) /* Runtime procedure descriptor table exception information (ucode) ??? */ #define SHT_MIPS_PDR_EXCEPTION 0x70000029 +/* ABI related flags section. */ +#define SHT_MIPS_ABIFLAGS 0x7000002a /* A section of type SHT_MIPS_LIBLIST contains an array of the following structure. The sh_link field is the section index of the @@ -594,6 +610,9 @@ extern void bfd_mips_elf32_swap_reginfo_out /* .MIPS.options section. */ #define PT_MIPS_OPTIONS 0x70000002 + +/* Records ABI related flags. */ +#define PT_MIPS_ABIFLAGS 0x70000003 /* Processor specific dynamic array tags. */ @@ -1049,6 +1068,58 @@ typedef struct bfd_vma ri_gp_value; } Elf64_Internal_RegInfo; +/* ABI Flags structure version 0. */ + +typedef struct +{ + /* Version of flags structure. */ + unsigned char version[2]; + /* The level of the ISA: 1-5, 32, 64. */ + unsigned char isa_level[1]; + /* The revision of ISA: 0 for MIPS V and below, 1-n otherwise. */ + unsigned char isa_rev[1]; + /* The size of general purpose registers. */ + unsigned char gpr_size[1]; + /* The size of co-processor 1 registers. */ + unsigned char cpr1_size[1]; + /* The size of co-processor 2 registers. */ + unsigned char cpr2_size[1]; + /* The floating-point ABI. */ + unsigned char fp_abi[1]; + /* Processor-specific extension. */ + unsigned char isa_ext[4]; + /* Mask of ASEs used. */ + unsigned char ases[4]; + /* Mask of general flags. */ + unsigned char flags1[4]; + unsigned char flags2[4]; +} Elf_External_ABIFlags_v0; + +typedef struct +{ + /* Version of flags structure. */ + unsigned short version; + /* The level of the ISA: 1-5, 32, 64. */ + unsigned char isa_level; + /* The revision of ISA: 0 for MIPS V and below, 1-n otherwise. */ + unsigned char isa_rev; + /* The size of general purpose registers. */ + unsigned char gpr_size; + /* The size of co-processor 1 registers. */ + unsigned char cpr1_size; + /* The size of co-processor 2 registers. */ + unsigned char cpr2_size; + /* The floating-point ABI. */ + unsigned char fp_abi; + /* Processor-specific extension. */ + unsigned long isa_ext; + /* Mask of ASEs used. */ + unsigned long ases; + /* Mask of general flags. */ + unsigned long flags1; + unsigned long flags2; +} Elf_Internal_ABIFlags_v0; + typedef struct { /* The hash value computed from the name of the corresponding @@ -1089,6 +1160,12 @@ extern void bfd_mips_elf64_swap_reginfo_in extern void bfd_mips_elf64_swap_reginfo_out (bfd *, const Elf64_Internal_RegInfo *, Elf64_External_RegInfo *); +/* MIPS ELF flags swapping routines. */ +extern void bfd_mips_elf_swap_abiflags_v0_in + (bfd *, const Elf_External_ABIFlags_v0 *, Elf_Internal_ABIFlags_v0 *); +extern void bfd_mips_elf_swap_abiflags_v0_out + (bfd *, const Elf_Internal_ABIFlags_v0 *, Elf_External_ABIFlags_v0 *); + /* Masks for the info work of an ODK_EXCEPTIONS descriptor. */ #define OEX_FPU_MIN 0x1f /* FPEs which must be enabled. */ #define OEX_FPU_MAX 0x1f00 /* FPEs which may be enabled. */ @@ -1126,6 +1203,55 @@ extern void bfd_mips_elf64_swap_reginfo_out /* Masks for the info word of an ODK_HWAND/ODK_HWOR descriptor. */ #define OHWA0_R4KEOP_CHECKED 0x00000001 #define OHWA0_R4KEOP_CLEAN 0x00000002 + +/* Values for the xxx_size bytes of an ABI flags structure. */ + +#define AFL_REG_NONE 0x00 /* No registers. */ +#define AFL_REG_32 0x01 /* 32-bit registers. */ +#define AFL_REG_64 0x02 /* 64-bit registers. */ +#define AFL_REG_128 0x03 /* 128-bit registers. */ + +/* Masks for the ases word of an ABI flags structure. */ + +#define AFL_ASE_DSP 0x00000001 /* DSP ASE. */ +#define AFL_ASE_DSPR2 0x00000002 /* DSP R2 ASE. */ +#define AFL_ASE_EVA 0x00000004 /* Enhanced VA Scheme. */ +#define AFL_ASE_MCU 0x00000008 /* MCU (MicroController) ASE. */ +#define AFL_ASE_MDMX 0x00000010 /* MDMX ASE. */ +#define AFL_ASE_MIPS3D 0x00000020 /* MIPS-3D ASE. */ +#define AFL_ASE_MT 0x00000040 /* MT ASE. */ +#define AFL_ASE_SMARTMIPS 0x00000080 /* SmartMIPS ASE. */ +#define AFL_ASE_VIRT 0x00000100 /* VZ ASE. */ +#define AFL_ASE_MSA 0x00000200 /* MSA ASE. */ +#define AFL_ASE_MIPS16 0x00000400 /* MIPS16 ASE. */ +#define AFL_ASE_MICROMIPS 0x00000800 /* MICROMIPS ASE. */ +#define AFL_ASE_XPA 0x00001000 /* XPA ASE. */ + +/* Values for the isa_ext word of an ABI flags structure. */ + +#define AFL_EXT_XLR 1 /* RMI Xlr instruction. */ +#define AFL_EXT_OCTEON2 2 /* Cavium Networks Octeon2. */ +#define AFL_EXT_OCTEONP 3 /* Cavium Networks OcteonP. */ +#define AFL_EXT_LOONGSON_3A 4 /* Loongson 3A. */ +#define AFL_EXT_OCTEON 5 /* Cavium Networks Octeon. */ +#define AFL_EXT_5900 6 /* MIPS R5900 instruction. */ +#define AFL_EXT_4650 7 /* MIPS R4650 instruction. */ +#define AFL_EXT_4010 8 /* LSI R4010 instruction. */ +#define AFL_EXT_4100 9 /* NEC VR4100 instruction. */ +#define AFL_EXT_3900 10 /* Toshiba R3900 instruction. */ +#define AFL_EXT_10000 11 /* MIPS R10000 instruction. */ +#define AFL_EXT_SB1 12 /* Broadcom SB-1 instruction. */ +#define AFL_EXT_4111 13 /* NEC VR4111/VR4181 instruction. */ +#define AFL_EXT_4120 14 /* NEC VR4120 instruction. */ +#define AFL_EXT_5400 15 /* NEC VR5400 instruction. */ +#define AFL_EXT_5500 16 /* NEC VR5500 instruction. */ +#define AFL_EXT_LOONGSON_2E 17 /* ST Microelectronics Loongson 2E. */ +#define AFL_EXT_LOONGSON_2F 18 /* ST Microelectronics Loongson 2F. */ + +/* Masks for the flags1 word of an ABI flags structure. */ +#define AFL_FLAGS1_ODDSPREG 1 /* Uses odd single-precision registers. */ + +extern unsigned int bfd_mips_isa_ext (bfd *); /* Object attribute tags. */ @@ -1135,6 +1261,9 @@ enum /* Floating-point ABI used by this object file. */ Tag_GNU_MIPS_ABI_FP = 4, + + /* MSA ABI used by this object file. */ + Tag_GNU_MIPS_ABI_MSA = 8, }; /* Object attribute values. */ @@ -1155,7 +1284,24 @@ enum Val_GNU_MIPS_ABI_FP_SOFT = 3, /* Using -mips32r2 -mfp64. */ - Val_GNU_MIPS_ABI_FP_64 = 4, + Val_GNU_MIPS_ABI_FP_OLD_64 = 4, + + /* Using -mfpxx */ + Val_GNU_MIPS_ABI_FP_XX = 5, + + /* Using -mips32r2 -mfp64. */ + Val_GNU_MIPS_ABI_FP_64 = 6, + + /* Using -mips32r2 -mfp64 -mno-odd-spreg. */ + Val_GNU_MIPS_ABI_FP_64A = 7, + + /* Values defined for Tag_GNU_MIPS_ABI_MSA. */ + + /* Not tagged or not using any ABIs affected by the differences. */ + Val_GNU_MIPS_ABI_MSA_ANY = 0, + + /* Using 128-bit MSA. */ + Val_GNU_MIPS_ABI_MSA_128 = 1, }; #endif /* _ELF_MIPS_H */ diff --git a/binutils-2.24/include/opcode/ChangeLog b/binutils-2.24/include/opcode/ChangeLog index b8a99f8..c3c1c3f 100644 --- a/binutils-2.24/include/opcode/ChangeLog +++ b/binutils-2.24/include/opcode/ChangeLog @@ -1,3 +1,36 @@ +2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com> + + * mips.h (INSN_ISA_MASK): Updated. + (INSN_ISA32R3): New define. + (INSN_ISA32R5): New define. + (INSN_ISA64R3): New define. + (INSN_ISA64R5): New define. + (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32 + INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered. + (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and + mips64r5. + (INSN_UPTO32R3): New define. + (INSN_UPTO32R5): New define. + (INSN_UPTO64R3): New define. + (INSN_UPTO64R5): New define. + (ISA_MIPS32R3): New define. + (ISA_MIPS32R5): New define. + (ISA_MIPS64R3): New define. + (ISA_MIPS64R5): New define. + (CPU_MIPS32R3): New define. + (CPU_MIPS32R5): New define. + (CPU_MIPS64R3): New define. + (CPU_MIPS64R5): New define. + +2014-05-01 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values. + +2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com> + + * mips.h: Updated description of +o, +u, +v and +w for MIPS and + microMIPS. + 2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64.h (aarch64_pstatefields): Change element type to @@ -34,6 +67,19 @@ * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND. (enum aarch64_opnd): Add AARCH64_OPND_COND1. +2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> + + * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX. + (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL. + For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, + +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. + For MIPS, update extension character sequences after +. + (ASE_MSA): New define. + (ASE_MSA64): New define. + For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, + +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. + For microMIPS, update extension character sequences after +. + 2013-08-23 Yuri Chornoivan <yurchor@ukr.net> PR binutils/15834 diff --git a/binutils-2.24/include/opcode/mips.h b/binutils-2.24/include/opcode/mips.h index f21697e..41d042f 100644 --- a/binutils-2.24/include/opcode/mips.h +++ b/binutils-2.24/include/opcode/mips.h @@ -413,7 +413,20 @@ enum mips_operand_type { /* Like OP_VU0_SUFFIX, but used when the operand's value has already been set. Any suffix used here must match the previous value. */ - OP_VU0_MATCH_SUFFIX + OP_VU0_MATCH_SUFFIX, + + /* An index selected by an integer, e.g. [1]. */ + OP_IMM_INDEX, + + /* An index selected by a register, e.g. [$2]. */ + OP_REG_INDEX, + + /* The operand spans two 5-bit register fields, both of which must be set to + the source register. */ + OP_SAME_RS_RT, + + /* Described by mips_prev_operand. */ + OP_CHECK_PREV }; /* Enumerates the types of MIPS register. */ @@ -454,7 +467,13 @@ enum mips_reg_operand_type { OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R, - OP_REG_R5900_ACC + OP_REG_R5900_ACC, + + /* MSA registers $w0-$w31. */ + OP_REG_MSA, + + /* MSA control registers $0-$31. */ + OP_REG_MSA_CTRL }; /* Base class for all operands. */ @@ -543,6 +562,20 @@ struct mips_reg_operand const unsigned char *reg_map; }; +/* Describes an operand that which must match a condition based on the + previous operand. */ +struct mips_check_prev_operand +{ + struct mips_operand root; + + bfd_boolean check_less_than; + bfd_boolean check_greater_than; + bfd_boolean check_less_than_or_equal; + bfd_boolean check_greater_than_or_equal; + bfd_boolean check_not_equal; + bfd_boolean check_not_zero; +}; + /* Describes an operand that encodes a pair of registers. */ struct mips_reg_pair_operand { @@ -891,6 +924,54 @@ struct mips_opcode Enhanced VA Scheme: "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET) + MSA Extension: + "+d" 5-bit MSA register (FD) + "+e" 5-bit MSA register (FS) + "+h" 5-bit MSA register (FT) + "+k" 5-bit GPR at bit 6 + "+l" 5-bit MSA control register at bit 6 + "+n" 5-bit MSA control register at bit 11 + "+o" 4-bit vector element index at bit 16 + "+u" 3-bit vector element index at bit 16 + "+v" 2-bit vector element index at bit 16 + "+w" 1-bit vector element index at bit 16 + "+T" (-512 .. 511) << 0 at bit 16 + "+U" (-512 .. 511) << 1 at bit 16 + "+V" (-512 .. 511) << 2 at bit 16 + "+W" (-512 .. 511) << 3 at bit 16 + "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6 + "+!" 3 bit unsigned bit position at bit 16 + "+@" 4 bit unsigned bit position at bit 16 + "+#" 6 bit unsigned bit position at bit 16 + "+$" 5 bit unsigned immediate at bit 16 + "+%" 5 bit signed immediate at bit 16 + "+^" 10 bit signed immediate at bit 11 + "+&" 0 vector element index + "+*" 5-bit register vector element index at bit 16 + "+|" 8-bit mask at bit 16 + + MIPS R6: + "+:" 11-bit mask at bit 0 + "+'" 26 bit PC relative branch target address + "+"" 21 bit PC relative branch target address + "+;" 5 bit same register in both OP_*_RS and OP_*_RT + "+I" 2bit unsigned bit position at bit 6 + "+O" 3bit unsigned bit position at bit 6 + "+R" must be program counter + "-a" (-262144 .. 262143) << 2 at bit 0 + "-b" (-131072 .. 131071) << 3 at bit 0 + "-d" Same as destination register GP + "-s" 5 bit source register specifier (OP_*_RS) not $0 + "-t" 5 bit source register specifier (OP_*_RT) not $0 + "-u" 5 bit source register specifier (OP_*_RT) greater than OP_*_RS + "-v" 5 bit source register specifier (OP_*_RT) not $0 not OP_*_RS + "-w" 5 bit source register specifier (OP_*_RT) less than or equal to OP_*_RS + "-x" 5 bit source register specifier (OP_*_RT) greater than or + equal to OP_*_RS + "-y" 5 bit source register specifier (OP_*_RT) not $0 less than OP_*_RS + "-A" symbolic offset (-262144 .. 262143) << 2 at bit 0 + "-B" symbolic offset (-131072 .. 131071) << 3 at bit 0 + Other: "()" parens surrounding optional value "," separates operands @@ -898,15 +979,21 @@ struct mips_opcode Characters used so far, for quick reference when adding more: "1234567890" - "%[]<>(),+:'@!#$*&\~" + "%[]<>(),+-:'@!#$*&\~" "ABCDEFGHIJKLMNOPQRSTUVWXYZ" "abcdefghijklopqrstuvwxz" Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: "1234567890" - "ABCEFGHJKLMNPQSXZ" - "abcfgijmpqrstxyz" + "~!@#$%^&*|:'";" + "ABCEFGHIJKLMNOPQRSTUVWXZ" + "abcdefghijklmnopqrstuvwxyz" + + Extension character sequences used so far ("-" followed by the + following), for quick reference when adding more: + "AB" + "abdstuvwxy" */ /* These are the bits which may be set in the pinfo field of an @@ -934,8 +1021,8 @@ struct mips_opcode #define INSN_TLB 0x00000200 /* Reads coprocessor register other than floating point register. */ #define INSN_COP 0x00000400 -/* Instruction loads value from memory, requiring delay. */ -#define INSN_LOAD_MEMORY_DELAY 0x00000800 +/* Instruction loads value from memory. */ +#define INSN_LOAD_MEMORY 0x00000800 /* Instruction loads value from coprocessor, requiring delay. */ #define INSN_LOAD_COPROC_DELAY 0x00001000 /* Instruction has unconditional branch delay slot. */ @@ -973,6 +1060,8 @@ struct mips_opcode #define INSN_WRITE_GPR_24 0x10000000 /* A user-defined instruction. */ #define INSN_UDI 0x20000000 +/* Is mtc1, mfc1, swc1, lwc1. */ +#define INSN_FP_32_MOVE 0x40000000 /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ #define INSN_MACRO 0xffffffff @@ -1014,6 +1103,8 @@ struct mips_opcode #define INSN2_READ_GPR_16 0x00002000 /* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */ #define INSN2_VU0_CHANNEL_SUFFIX 0x00004000 +/* Instruction has a forbidden slot. */ +#define INSN2_FORBIDDEN_SLOT 0x00008000 /* Masks used to mark instructions to indicate which MIPS ISA level they were introduced in. INSN_ISA_MASK masks an enumeration that @@ -1021,7 +1112,7 @@ struct mips_opcode word constructed using these macros is a bitmask of the remaining INSN_* values below. */ -#define INSN_ISA_MASK 0x0000000ful +#define INSN_ISA_MASK 0x0000001ful /* We cannot start at zero due to ISA_UNKNOWN below. */ #define INSN_ISA1 1 @@ -1031,28 +1122,75 @@ struct mips_opcode #define INSN_ISA5 5 #define INSN_ISA32 6 #define INSN_ISA32R2 7 -#define INSN_ISA64 8 -#define INSN_ISA64R2 9 +#define INSN_ISA32R3 8 +#define INSN_ISA32R5 9 +#define INSN_ISA32R6 10 +#define INSN_ISA64 11 +#define INSN_ISA64R2 12 +#define INSN_ISA64R3 13 +#define INSN_ISA64R5 14 +#define INSN_ISA64R6 15 /* Below this point the INSN_* values correspond to combinations of ISAs. They are only for use in the opcodes table to indicate membership of a combination of ISAs that cannot be expressed using the usual inclusion ordering on the above INSN_* values. */ -#define INSN_ISA3_32 10 -#define INSN_ISA3_32R2 11 -#define INSN_ISA4_32 12 -#define INSN_ISA4_32R2 13 -#define INSN_ISA5_32R2 14 - -/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through - INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2, - this table describes whether at least one of the ISAs described by X - is/are implemented by ISA Y. (Think of Y as the ISA level supported by - a particular core and X as the ISA level(s) at which a certain instruction - is defined.) The ISA(s) described by X is/are implemented by Y iff - (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1 - is non-zero. */ -static const unsigned int mips_isa_table[] = - { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; +#define INSN_ISA3_32 16 +#define INSN_ISA3_32R2 17 +#define INSN_ISA4_32 18 +#define INSN_ISA4_32R2 19 +#define INSN_ISA5_32R2 20 + +/* The R6 definitions shown below state that they support all previous ISAs. + This is not actually true as some instructions are removed in R6. + The problem is that the removed instructions in R6 come from different + ISAs. One approach to solve this would be to describe in the membership + field of the opcode table the different ISAs an instruction belongs to. + This would require us to create a large amount of different ISA + combinations which is hard to manage. A cleaner approach (which is + implemented here) is to say that R6 is an extension of R5 and then to + deal with the removed instructions by adding instruction exclusions + for R6 in the opcode table. */ + +/* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X. */ + +#define ISAF(X) (1 << (INSN_ISA##X - 1)) +#define INSN_UPTO1 ISAF(1) +#define INSN_UPTO2 INSN_UPTO1 | ISAF(2) +#define INSN_UPTO3 INSN_UPTO2 | ISAF(3) | ISAF(3_32) | ISAF(3_32R2) +#define INSN_UPTO4 INSN_UPTO3 | ISAF(4) | ISAF(4_32) | ISAF(4_32R2) +#define INSN_UPTO5 INSN_UPTO4 | ISAF(5) | ISAF(5_32R2) +#define INSN_UPTO32 INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32) +#define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \ + | ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2) +#define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3) +#define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5) +#define INSN_UPTO32R6 INSN_UPTO32R5 | ISAF(32R6) +#define INSN_UPTO64 INSN_UPTO5 | ISAF(64) | ISAF(32) +#define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2) +#define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3) +#define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5) +#define INSN_UPTO64R6 INSN_UPTO64R5 | ISAF(64R6) | ISAF(32R6) + +/* The same information in table form: bit INSN_ISA<X> - 1 of index + INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X. */ +static const unsigned int mips_isa_table[] = { + INSN_UPTO1, + INSN_UPTO2, + INSN_UPTO3, + INSN_UPTO4, + INSN_UPTO5, + INSN_UPTO32, + INSN_UPTO32R2, + INSN_UPTO32R3, + INSN_UPTO32R5, + INSN_UPTO32R6, + INSN_UPTO64, + INSN_UPTO64R2, + INSN_UPTO64R3, + INSN_UPTO64R5, + INSN_UPTO64R6 +}; +#undef ISAF /* Masks used for Chip specific instructions. */ #define INSN_CHIP_MASK 0xc3ff0f20 @@ -1115,6 +1253,11 @@ static const unsigned int mips_isa_table[] = /* Virtualization ASE */ #define ASE_VIRT 0x00000200 #define ASE_VIRT64 0x00000400 +/* MSA Extension */ +#define ASE_MSA 0x00000800 +#define ASE_MSA64 0x00001000 +/* eXtended Physical Address (XPA) Extension. */ +#define ASE_XPA 0x00002000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ @@ -1129,8 +1272,14 @@ static const unsigned int mips_isa_table[] = #define ISA_MIPS64 INSN_ISA64 #define ISA_MIPS32R2 INSN_ISA32R2 +#define ISA_MIPS32R3 INSN_ISA32R3 +#define ISA_MIPS32R5 INSN_ISA32R5 #define ISA_MIPS64R2 INSN_ISA64R2 +#define ISA_MIPS64R3 INSN_ISA64R3 +#define ISA_MIPS64R5 INSN_ISA64R5 +#define ISA_MIPS32R6 INSN_ISA32R6 +#define ISA_MIPS64R6 INSN_ISA64R6 /* CPU defines, use instead of hardcoding processor number. Keep this in sync with bfd/archures.c in order for machine selection to work. */ @@ -1161,9 +1310,15 @@ static const unsigned int mips_isa_table[] = #define CPU_MIPS16 16 #define CPU_MIPS32 32 #define CPU_MIPS32R2 33 +#define CPU_MIPS32R3 34 +#define CPU_MIPS32R5 36 +#define CPU_MIPS32R6 37 #define CPU_MIPS5 5 #define CPU_MIPS64 64 #define CPU_MIPS64R2 65 +#define CPU_MIPS64R3 66 +#define CPU_MIPS64R5 68 +#define CPU_MIPS64R6 69 #define CPU_SB1 12310201 /* octal 'SB', 01. */ #define CPU_LOONGSON_2E 3001 #define CPU_LOONGSON_2F 3002 @@ -1239,6 +1394,13 @@ cpu_is_member (int cpu, unsigned int mask) case CPU_XLR: return (mask & INSN_XLR) != 0; + case CPU_MIPS32R6: + return (mask & INSN_ISA_MASK) == INSN_ISA32R6; + + case CPU_MIPS64R6: + return ((mask & INSN_ISA_MASK) == INSN_ISA32R6) + || ((mask & INSN_ISA_MASK) == INSN_ISA64R6); + default: return FALSE; } @@ -2044,6 +2206,33 @@ extern const int bfd_mips16_num_opcodes; microMIPS Enhanced VA Scheme: "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET) + MSA Extension: + "+d" 5-bit MSA register (FD) + "+e" 5-bit MSA register (FS) + "+h" 5-bit MSA register (FT) + "+k" 5-bit GPR at bit 6 + "+l" 5-bit MSA control register at bit 6 + "+n" 5-bit MSA control register at bit 11 + "+o" 4-bit vector element index at bit 16 + "+u" 3-bit vector element index at bit 16 + "+v" 2-bit vector element index at bit 16 + "+w" 1-bit vector element index at bit 16 + "+x" 5-bit shift amount at bit 16 + "+T" (-512 .. 511) << 0 at bit 16 + "+U" (-512 .. 511) << 1 at bit 16 + "+V" (-512 .. 511) << 2 at bit 16 + "+W" (-512 .. 511) << 3 at bit 16 + "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6 + "+!" 3 bit unsigned bit position at bit 16 + "+@" 4 bit unsigned bit position at bit 16 + "+#" 6 bit unsigned bit position at bit 16 + "+$" 5 bit unsigned immediate at bit 16 + "+%" 5 bit signed immediate at bit 16 + "+^" 10 bit signed immediate at bit 11 + "+&" 0 vector element index + "+*" 5-bit register vector element index at bit 16 + "+|" 8-bit mask at bit 16 + Other: "()" parens surrounding optional value "," separates operands @@ -2052,16 +2241,16 @@ extern const int bfd_mips16_num_opcodes; Characters used so far, for quick reference when adding more: "12345678 0" - "<>(),+.@\^|~" + "<>(),+-.@\^|~" "ABCDEFGHI KLMN RST V " "abcd f hijklmnopqrstuvw yz" Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: "" - "" - "ABCEFGH" - "ij" + "~!@#$%^&*|" + "ABCEFGHTUVW" + "dehijklnouvwx" Extension character sequences used so far ("m" followed by the following), for quick reference when adding more: @@ -2069,6 +2258,12 @@ extern const int bfd_mips16_num_opcodes; "" " BCDEFGHIJ LMNOPQ U WXYZ" " bcdefghij lmn pq st xyz" + + Extension character sequences used so far ("-" followed by the + following), for quick reference when adding more: + "" + "" + <none so far> */ extern const struct mips_operand *decode_micromips_operand (const char *); |