diff options
Diffstat (limited to 'gcc-4.6/gcc/config/sparc/sparc.md')
| -rw-r--r-- | gcc-4.6/gcc/config/sparc/sparc.md | 92 |
1 files changed, 56 insertions, 36 deletions
diff --git a/gcc-4.6/gcc/config/sparc/sparc.md b/gcc-4.6/gcc/config/sparc/sparc.md index 1ff599d..37e3585 100644 --- a/gcc-4.6/gcc/config/sparc/sparc.md +++ b/gcc-4.6/gcc/config/sparc/sparc.md @@ -28,6 +28,7 @@ [(UNSPEC_MOVE_PIC 0) (UNSPEC_UPDATE_RETURN 1) (UNSPEC_LOAD_PCREL_SYM 2) + (UNSPEC_FRAME_BLOCKAGE 3) (UNSPEC_MOVE_PIC_LABEL 5) (UNSPEC_SETH44 6) (UNSPEC_SETM44 7) @@ -1813,8 +1814,8 @@ }) (define_insn "*movsf_insn" - [(set (match_operand:V32 0 "nonimmediate_operand" "=d,f,*r,*r,*r,f,*r,m,m") - (match_operand:V32 1 "input_operand" "GY,f,*rRY,Q,S,m,m,f,*rGY"))] + [(set (match_operand:V32 0 "nonimmediate_operand" "=d,f, *r,*r,*r,f,*r,m, m") + (match_operand:V32 1 "input_operand" "GY,f,*rRY, Q, S,m, m,f,*rGY"))] "TARGET_FPU && (register_operand (operands[0], <V32:MODE>mode) || register_or_zero_operand (operands[1], <V32:MODE>mode))" @@ -1861,8 +1862,8 @@ ;; when -mno-fpu. (define_insn "*movsf_insn_no_fpu" - [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r,m") - (match_operand:SF 1 "input_operand" "rR,Q,S,m,rG"))] + [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r, m") + (match_operand:SF 1 "input_operand" "rR,Q,S,m,rG"))] "! TARGET_FPU && (register_operand (operands[0], SFmode) || register_or_zero_operand (operands[1], SFmode))" @@ -1948,8 +1949,8 @@ ;; Be careful, fmovd does not exist when !v9. (define_insn "*movdf_insn_sp32" - [(set (match_operand:DF 0 "nonimmediate_operand" "=e,W,U,T,o,e,*r,o,e,o") - (match_operand:DF 1 "input_operand" "W#F,e,T,U,G,e,*rFo,*r,o#F,e"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "= e,W,U,T,o,e, *r, o, e,o") + (match_operand:DF 1 "input_operand" "W#F,e,T,U,G,e,*rFo,*r,o#F,e"))] "TARGET_FPU && ! TARGET_V9 && (register_operand (operands[0], DFmode) @@ -1969,8 +1970,8 @@ (set_attr "length" "*,*,*,*,2,2,2,2,2,2")]) (define_insn "*movdf_insn_sp32_no_fpu" - [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o,r,o") - (match_operand:DF 1 "input_operand" "T,U,G,ro,r"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o, r,o") + (match_operand:DF 1 "input_operand" " T,U,G,ro,r"))] "! TARGET_FPU && ! TARGET_V9 && (register_operand (operands[0], DFmode) @@ -1986,8 +1987,8 @@ ;; We have available v9 double floats but not 64-bit integer registers. (define_insn "*movdf_insn_sp32_v9" - [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,T,W,U,T,f,*r,o") - (match_operand:V64 1 "input_operand" "GY,e,W#F,GY,e,T,U,o#F,*roGYDF,*rGYf"))] + [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e, e, T,W,U,T, f, *r, o") + (match_operand:V64 1 "input_operand" "GY,e,W#F,GY,e,T,U,o#F,*roFD,*rGYf"))] "TARGET_FPU && TARGET_V9 && ! TARGET_ARCH64 @@ -2009,8 +2010,8 @@ (set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")]) (define_insn "*movdf_insn_sp32_v9_no_fpu" - [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o") - (match_operand:DF 1 "input_operand" "T,U,G,ro,rG"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T, r, o") + (match_operand:DF 1 "input_operand" " T,U,G,ro,rG"))] "! TARGET_FPU && TARGET_V9 && ! TARGET_ARCH64 @@ -2027,8 +2028,8 @@ ;; We have available both v9 double floats and 64-bit integer registers. (define_insn "*movdf_insn_sp64" - [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,W,*r,*r,m,*r") - (match_operand:V64 1 "input_operand" "GY,e,W#F,e,*rGY,m,*rGY,DF"))] + [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e, e,W, *r,*r, m,*r") + (match_operand:V64 1 "input_operand" "GY,e,W#F,e,*rGY, m,*rGY,FD"))] "TARGET_FPU && TARGET_ARCH64 && (register_operand (operands[0], <V64:MODE>mode) @@ -2047,8 +2048,8 @@ (set_attr "fptype" "double,double,*,*,*,*,*,*")]) (define_insn "*movdf_insn_sp64_no_fpu" - [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m") - (match_operand:DF 1 "input_operand" "r,m,rG"))] + [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r, m") + (match_operand:DF 1 "input_operand" "r,m,rG"))] "! TARGET_FPU && TARGET_ARCH64 && (register_operand (operands[0], DFmode) @@ -2288,8 +2289,8 @@ }) (define_insn "*movtf_insn_sp32" - [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,o,U,r") - (match_operand:TF 1 "input_operand" "G,oe,GeUr,o,roG"))] + [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e, o,U, r") + (match_operand:TF 1 "input_operand" " G,oe,GeUr,o,roG"))] "TARGET_FPU && ! TARGET_ARCH64 && (register_operand (operands[0], TFmode) @@ -2302,8 +2303,8 @@ ;; when -mno-fpu. (define_insn "*movtf_insn_sp32_no_fpu" - [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o,r,o") - (match_operand:TF 1 "input_operand" "G,o,U,roG,r"))] + [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o, r,o") + (match_operand:TF 1 "input_operand" " G,o,U,roG,r"))] "! TARGET_FPU && ! TARGET_ARCH64 && (register_operand (operands[0], TFmode) @@ -2312,8 +2313,8 @@ [(set_attr "length" "4")]) (define_insn "*movtf_insn_sp64" - [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,o,r") - (match_operand:TF 1 "input_operand" "G,oe,Ger,roG"))] + [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e, o, r") + (match_operand:TF 1 "input_operand" "G,oe,Ger,roG"))] "TARGET_FPU && TARGET_ARCH64 && ! TARGET_HARD_QUAD @@ -2323,8 +2324,8 @@ [(set_attr "length" "2")]) (define_insn "*movtf_insn_sp64_hq" - [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,e,m,o,r") - (match_operand:TF 1 "input_operand" "G,e,m,e,rG,roG"))] + [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,e,m, o, r") + (match_operand:TF 1 "input_operand" "G,e,m,e,rG,roG"))] "TARGET_FPU && TARGET_ARCH64 && TARGET_HARD_QUAD @@ -2341,8 +2342,8 @@ (set_attr "length" "2,*,*,*,2,2")]) (define_insn "*movtf_insn_sp64_no_fpu" - [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o") - (match_operand:TF 1 "input_operand" "orG,rG"))] + [(set (match_operand:TF 0 "nonimmediate_operand" "= r, o") + (match_operand:TF 1 "input_operand" "orG,rG"))] "! TARGET_FPU && TARGET_ARCH64 && (register_operand (operands[0], TFmode) @@ -2484,11 +2485,9 @@ (match_operand:I 3 "arith10_operand" "")))] "TARGET_V9 && !(<I:MODE>mode == DImode && TARGET_ARCH32)" { - enum rtx_code code = GET_CODE (operands[1]); rtx cc_reg; - if (GET_MODE (XEXP (operands[1], 0)) == DImode - && ! TARGET_ARCH64) + if (GET_MODE (XEXP (operands[1], 0)) == DImode && !TARGET_ARCH64) FAIL; if (GET_MODE (XEXP (operands[1], 0)) == TFmode && !TARGET_HARD_QUAD) @@ -2499,12 +2498,14 @@ if (XEXP (operands[1], 1) == const0_rtx && GET_CODE (XEXP (operands[1], 0)) == REG && GET_MODE (XEXP (operands[1], 0)) == DImode - && v9_regcmp_p (code)) + && v9_regcmp_p (GET_CODE (operands[1]))) cc_reg = XEXP (operands[1], 0); else cc_reg = gen_compare_reg (operands[1]); - operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); + operands[1] + = gen_rtx_fmt_ee (GET_CODE (operands[1]), GET_MODE (cc_reg), cc_reg, + const0_rtx); }) (define_expand "mov<F:mode>cc" @@ -2514,11 +2515,9 @@ (match_operand:F 3 "register_operand" "")))] "TARGET_V9 && TARGET_FPU" { - enum rtx_code code = GET_CODE (operands[1]); rtx cc_reg; - if (GET_MODE (XEXP (operands[1], 0)) == DImode - && ! TARGET_ARCH64) + if (GET_MODE (XEXP (operands[1], 0)) == DImode && !TARGET_ARCH64) FAIL; if (GET_MODE (XEXP (operands[1], 0)) == TFmode && !TARGET_HARD_QUAD) @@ -2529,12 +2528,14 @@ if (XEXP (operands[1], 1) == const0_rtx && GET_CODE (XEXP (operands[1], 0)) == REG && GET_MODE (XEXP (operands[1], 0)) == DImode - && v9_regcmp_p (code)) + && v9_regcmp_p (GET_CODE (operands[1]))) cc_reg = XEXP (operands[1], 0); else cc_reg = gen_compare_reg (operands[1]); - operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); + operands[1] + = gen_rtx_fmt_ee (GET_CODE (operands[1]), GET_MODE (cc_reg), cc_reg, + const0_rtx); }) ;; Conditional move define_insns @@ -6338,6 +6339,25 @@ "" [(set_attr "length" "0")]) +;; Do not schedule instructions accessing memory before this point. + +(define_expand "frame_blockage" + [(set (match_dup 0) + (unspec:BLK [(match_dup 1)] UNSPEC_FRAME_BLOCKAGE))] + "" +{ + operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); + MEM_VOLATILE_P (operands[0]) = 1; + operands[1] = stack_pointer_rtx; +}) + +(define_insn "*frame_blockage<P:mode>" + [(set (match_operand:BLK 0 "" "") + (unspec:BLK [(match_operand:P 1 "" "")] UNSPEC_FRAME_BLOCKAGE))] + "" + "" + [(set_attr "length" "0")]) + (define_expand "probe_stack" [(set (match_operand 0 "memory_operand" "") (const_int 0))] "" |