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-rw-r--r--gcc-4.6/gcc/config/sparc/freebsd.h2
-rw-r--r--gcc-4.6/gcc/config/sparc/linux.h2
-rw-r--r--gcc-4.6/gcc/config/sparc/linux64.h2
-rw-r--r--gcc-4.6/gcc/config/sparc/sol2.h2
-rw-r--r--gcc-4.6/gcc/config/sparc/sp-elf.h2
-rw-r--r--gcc-4.6/gcc/config/sparc/sp64-elf.h2
-rw-r--r--gcc-4.6/gcc/config/sparc/sparc.c115
-rw-r--r--gcc-4.6/gcc/config/sparc/sparc.h1
-rw-r--r--gcc-4.6/gcc/config/sparc/sparc.md92
-rw-r--r--gcc-4.6/gcc/config/sparc/sparc.opt5
10 files changed, 182 insertions, 43 deletions
diff --git a/gcc-4.6/gcc/config/sparc/freebsd.h b/gcc-4.6/gcc/config/sparc/freebsd.h
index f7e53f2..76c27d3 100644
--- a/gcc-4.6/gcc/config/sparc/freebsd.h
+++ b/gcc-4.6/gcc/config/sparc/freebsd.h
@@ -169,7 +169,7 @@ along with GCC; see the file COPYING3. If not see
#undef ENDFILE_SPEC
#define ENDFILE_SPEC \
- "%{ffast-math|funsafe-math-optimizations:crtfastmath.o%s} " \
+ "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} " \
FBSD_ENDFILE_SPEC
/* We use GNU ld so undefine this so that attribute((init_priority)) works. */
diff --git a/gcc-4.6/gcc/config/sparc/linux.h b/gcc-4.6/gcc/config/sparc/linux.h
index b37ccce..acdbcb9 100644
--- a/gcc-4.6/gcc/config/sparc/linux.h
+++ b/gcc-4.6/gcc/config/sparc/linux.h
@@ -37,7 +37,7 @@ along with GCC; see the file COPYING3. If not see
#undef ENDFILE_SPEC
#define ENDFILE_SPEC \
"%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s\
- %{ffast-math|funsafe-math-optimizations:crtfastmath.o%s}"
+ %{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s}"
/* This is for -profile to use -lc_p instead of -lc. */
#undef CC1_SPEC
diff --git a/gcc-4.6/gcc/config/sparc/linux64.h b/gcc-4.6/gcc/config/sparc/linux64.h
index a4c67dc..3886358 100644
--- a/gcc-4.6/gcc/config/sparc/linux64.h
+++ b/gcc-4.6/gcc/config/sparc/linux64.h
@@ -59,7 +59,7 @@ along with GCC; see the file COPYING3. If not see
#undef ENDFILE_SPEC
#define ENDFILE_SPEC \
"%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s\
- %{ffast-math|funsafe-math-optimizations:crtfastmath.o%s}"
+ %{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s}"
#undef TARGET_VERSION
#define TARGET_VERSION fprintf (stderr, " (sparc64 GNU/Linux with ELF)");
diff --git a/gcc-4.6/gcc/config/sparc/sol2.h b/gcc-4.6/gcc/config/sparc/sol2.h
index 49d1525..4c8edaf 100644
--- a/gcc-4.6/gcc/config/sparc/sol2.h
+++ b/gcc-4.6/gcc/config/sparc/sol2.h
@@ -119,7 +119,7 @@ along with GCC; see the file COPYING3. If not see
#undef ENDFILE_SPEC
#define ENDFILE_SPEC \
- "%{ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \
+ "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \
crtend.o%s crtn.o%s"
/* Select a format to encode pointers in exception handling data. CODE
diff --git a/gcc-4.6/gcc/config/sparc/sp-elf.h b/gcc-4.6/gcc/config/sparc/sp-elf.h
index 6c0797f..d78eba3 100644
--- a/gcc-4.6/gcc/config/sparc/sp-elf.h
+++ b/gcc-4.6/gcc/config/sparc/sp-elf.h
@@ -38,7 +38,7 @@ along with GCC; see the file COPYING3. If not see
#undef ENDFILE_SPEC
#define ENDFILE_SPEC \
- "%{ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \
+ "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \
crtend.o%s crtn.o%s"
/* Don't set the target flags, this is done by the linker script */
diff --git a/gcc-4.6/gcc/config/sparc/sp64-elf.h b/gcc-4.6/gcc/config/sparc/sp64-elf.h
index c15e9ad..b219693 100644
--- a/gcc-4.6/gcc/config/sparc/sp64-elf.h
+++ b/gcc-4.6/gcc/config/sparc/sp64-elf.h
@@ -58,7 +58,7 @@ along with GCC; see the file COPYING3. If not see
#undef ENDFILE_SPEC
#define ENDFILE_SPEC \
- "%{ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \
+ "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \
crtend.o%s crtn.o%s"
/* Use the default (for now). */
diff --git a/gcc-4.6/gcc/config/sparc/sparc.c b/gcc-4.6/gcc/config/sparc/sparc.c
index 753028f..c93c25b 100644
--- a/gcc-4.6/gcc/config/sparc/sparc.c
+++ b/gcc-4.6/gcc/config/sparc/sparc.c
@@ -415,6 +415,7 @@ static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
HOST_WIDE_INT, tree);
static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT,
HOST_WIDE_INT, const_tree);
+static void sparc_reorg (void);
static struct machine_function * sparc_init_machine_status (void);
static bool sparc_cannot_force_const_mem (rtx);
static rtx sparc_tls_get_addr (void);
@@ -568,6 +569,9 @@ static const struct default_options sparc_option_optimization_table[] =
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
+#undef TARGET_MACHINE_DEPENDENT_REORG
+#define TARGET_MACHINE_DEPENDENT_REORG sparc_reorg
+
#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS sparc_rtx_costs
#undef TARGET_ADDRESS_COST
@@ -4565,8 +4569,9 @@ sparc_expand_prologue (void)
else if (actual_fsize <= 8192)
{
insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
- /* %sp is still the CFA register. */
RTX_FRAME_RELATED_P (insn) = 1;
+
+ /* %sp is still the CFA register. */
insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize)));
}
@@ -4588,8 +4593,18 @@ sparc_expand_prologue (void)
else if (actual_fsize <= 8192)
{
insn = emit_insn (gen_save_register_window (GEN_INT (-4096)));
+
/* %sp is not the CFA register anymore. */
emit_insn (gen_stack_pointer_inc (GEN_INT (4096-actual_fsize)));
+
+ /* Make sure no %fp-based store is issued until after the frame is
+ established. The offset between the frame pointer and the stack
+ pointer is calculated relative to the value of the stack pointer
+ at the end of the function prologue, and moving instructions that
+ access the stack via the frame pointer between the instructions
+ that decrement the stack pointer could result in accessing the
+ register window save area, which is volatile. */
+ emit_insn (gen_frame_blockage ());
}
else
{
@@ -9423,6 +9438,104 @@ sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
return (vcall_offset >= -32768 || ! fixed_regs[5]);
}
+/* We use the machine specific reorg pass to enable workarounds for errata. */
+
+static void
+sparc_reorg (void)
+{
+ rtx insn, next;
+
+ /* The only erratum we handle for now is that of the AT697F processor. */
+ if (!sparc_fix_at697f)
+ return;
+
+ /* We need to have the (essentially) final form of the insn stream in order
+ to properly detect the various hazards. Run delay slot scheduling. */
+ if (optimize > 0 && flag_delayed_branch)
+ dbr_schedule (get_insns ());
+
+ /* Now look for specific patterns in the insn stream. */
+ for (insn = get_insns (); insn; insn = next)
+ {
+ bool insert_nop = false;
+ rtx set;
+
+ /* Look for a single-word load into an odd-numbered FP register. */
+ if (NONJUMP_INSN_P (insn)
+ && (set = single_set (insn)) != NULL_RTX
+ && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4
+ && MEM_P (SET_SRC (set))
+ && REG_P (SET_DEST (set))
+ && REGNO (SET_DEST (set)) > 31
+ && REGNO (SET_DEST (set)) % 2 != 0)
+ {
+ /* The wrong dependency is on the enclosing double register. */
+ unsigned int x = REGNO (SET_DEST (set)) - 1;
+ unsigned int src1, src2, dest;
+ int code;
+
+ /* If the insn has a delay slot, then it cannot be problematic. */
+ next = next_active_insn (insn);
+ if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE)
+ code = -1;
+ else
+ {
+ extract_insn (next);
+ code = INSN_CODE (next);
+ }
+
+ switch (code)
+ {
+ case CODE_FOR_adddf3:
+ case CODE_FOR_subdf3:
+ case CODE_FOR_muldf3:
+ case CODE_FOR_divdf3:
+ dest = REGNO (recog_data.operand[0]);
+ src1 = REGNO (recog_data.operand[1]);
+ src2 = REGNO (recog_data.operand[2]);
+ if (src1 != src2)
+ {
+ /* Case [1-4]:
+ ld [address], %fx+1
+ FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
+ if ((src1 == x || src2 == x)
+ && (dest == src1 || dest == src2))
+ insert_nop = true;
+ }
+ else
+ {
+ /* Case 5:
+ ld [address], %fx+1
+ FPOPd %fx, %fx, %fx */
+ if (src1 == x
+ && dest == src1
+ && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3))
+ insert_nop = true;
+ }
+ break;
+
+ case CODE_FOR_sqrtdf2:
+ dest = REGNO (recog_data.operand[0]);
+ src1 = REGNO (recog_data.operand[1]);
+ /* Case 6:
+ ld [address], %fx+1
+ fsqrtd %fx, %fx */
+ if (src1 == x && dest == src1)
+ insert_nop = true;
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ next = NEXT_INSN (insn);
+
+ if (insert_nop)
+ emit_insn_after (gen_nop (), insn);
+ }
+}
+
/* How to allocate a 'struct machine_function'. */
static struct machine_function *
diff --git a/gcc-4.6/gcc/config/sparc/sparc.h b/gcc-4.6/gcc/config/sparc/sparc.h
index 297844f..24e0a2e 100644
--- a/gcc-4.6/gcc/config/sparc/sparc.h
+++ b/gcc-4.6/gcc/config/sparc/sparc.h
@@ -408,6 +408,7 @@ extern enum cmodel sparc_cmodel;
%{mcpu=sparclite:-Asparclite} \
%{mcpu=sparclite86x:-Asparclite} \
%{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
+%{mcpu=v8:-Av8} \
%{mv8plus:-Av8plus} \
%{mcpu=v9:-Av9} \
%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
diff --git a/gcc-4.6/gcc/config/sparc/sparc.md b/gcc-4.6/gcc/config/sparc/sparc.md
index 1ff599d..37e3585 100644
--- a/gcc-4.6/gcc/config/sparc/sparc.md
+++ b/gcc-4.6/gcc/config/sparc/sparc.md
@@ -28,6 +28,7 @@
[(UNSPEC_MOVE_PIC 0)
(UNSPEC_UPDATE_RETURN 1)
(UNSPEC_LOAD_PCREL_SYM 2)
+ (UNSPEC_FRAME_BLOCKAGE 3)
(UNSPEC_MOVE_PIC_LABEL 5)
(UNSPEC_SETH44 6)
(UNSPEC_SETM44 7)
@@ -1813,8 +1814,8 @@
})
(define_insn "*movsf_insn"
- [(set (match_operand:V32 0 "nonimmediate_operand" "=d,f,*r,*r,*r,f,*r,m,m")
- (match_operand:V32 1 "input_operand" "GY,f,*rRY,Q,S,m,m,f,*rGY"))]
+ [(set (match_operand:V32 0 "nonimmediate_operand" "=d,f, *r,*r,*r,f,*r,m, m")
+ (match_operand:V32 1 "input_operand" "GY,f,*rRY, Q, S,m, m,f,*rGY"))]
"TARGET_FPU
&& (register_operand (operands[0], <V32:MODE>mode)
|| register_or_zero_operand (operands[1], <V32:MODE>mode))"
@@ -1861,8 +1862,8 @@
;; when -mno-fpu.
(define_insn "*movsf_insn_no_fpu"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r,m")
- (match_operand:SF 1 "input_operand" "rR,Q,S,m,rG"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r, m")
+ (match_operand:SF 1 "input_operand" "rR,Q,S,m,rG"))]
"! TARGET_FPU
&& (register_operand (operands[0], SFmode)
|| register_or_zero_operand (operands[1], SFmode))"
@@ -1948,8 +1949,8 @@
;; Be careful, fmovd does not exist when !v9.
(define_insn "*movdf_insn_sp32"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=e,W,U,T,o,e,*r,o,e,o")
- (match_operand:DF 1 "input_operand" "W#F,e,T,U,G,e,*rFo,*r,o#F,e"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "= e,W,U,T,o,e, *r, o, e,o")
+ (match_operand:DF 1 "input_operand" "W#F,e,T,U,G,e,*rFo,*r,o#F,e"))]
"TARGET_FPU
&& ! TARGET_V9
&& (register_operand (operands[0], DFmode)
@@ -1969,8 +1970,8 @@
(set_attr "length" "*,*,*,*,2,2,2,2,2,2")])
(define_insn "*movdf_insn_sp32_no_fpu"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o,r,o")
- (match_operand:DF 1 "input_operand" "T,U,G,ro,r"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o, r,o")
+ (match_operand:DF 1 "input_operand" " T,U,G,ro,r"))]
"! TARGET_FPU
&& ! TARGET_V9
&& (register_operand (operands[0], DFmode)
@@ -1986,8 +1987,8 @@
;; We have available v9 double floats but not 64-bit integer registers.
(define_insn "*movdf_insn_sp32_v9"
- [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,T,W,U,T,f,*r,o")
- (match_operand:V64 1 "input_operand" "GY,e,W#F,GY,e,T,U,o#F,*roGYDF,*rGYf"))]
+ [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e, e, T,W,U,T, f, *r, o")
+ (match_operand:V64 1 "input_operand" "GY,e,W#F,GY,e,T,U,o#F,*roFD,*rGYf"))]
"TARGET_FPU
&& TARGET_V9
&& ! TARGET_ARCH64
@@ -2009,8 +2010,8 @@
(set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")])
(define_insn "*movdf_insn_sp32_v9_no_fpu"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o")
- (match_operand:DF 1 "input_operand" "T,U,G,ro,rG"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T, r, o")
+ (match_operand:DF 1 "input_operand" " T,U,G,ro,rG"))]
"! TARGET_FPU
&& TARGET_V9
&& ! TARGET_ARCH64
@@ -2027,8 +2028,8 @@
;; We have available both v9 double floats and 64-bit integer registers.
(define_insn "*movdf_insn_sp64"
- [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e,e,W,*r,*r,m,*r")
- (match_operand:V64 1 "input_operand" "GY,e,W#F,e,*rGY,m,*rGY,DF"))]
+ [(set (match_operand:V64 0 "nonimmediate_operand" "=b,e, e,W, *r,*r, m,*r")
+ (match_operand:V64 1 "input_operand" "GY,e,W#F,e,*rGY, m,*rGY,FD"))]
"TARGET_FPU
&& TARGET_ARCH64
&& (register_operand (operands[0], <V64:MODE>mode)
@@ -2047,8 +2048,8 @@
(set_attr "fptype" "double,double,*,*,*,*,*,*")])
(define_insn "*movdf_insn_sp64_no_fpu"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
- (match_operand:DF 1 "input_operand" "r,m,rG"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r, m")
+ (match_operand:DF 1 "input_operand" "r,m,rG"))]
"! TARGET_FPU
&& TARGET_ARCH64
&& (register_operand (operands[0], DFmode)
@@ -2288,8 +2289,8 @@
})
(define_insn "*movtf_insn_sp32"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,o,U,r")
- (match_operand:TF 1 "input_operand" "G,oe,GeUr,o,roG"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e, o,U, r")
+ (match_operand:TF 1 "input_operand" " G,oe,GeUr,o,roG"))]
"TARGET_FPU
&& ! TARGET_ARCH64
&& (register_operand (operands[0], TFmode)
@@ -2302,8 +2303,8 @@
;; when -mno-fpu.
(define_insn "*movtf_insn_sp32_no_fpu"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o,r,o")
- (match_operand:TF 1 "input_operand" "G,o,U,roG,r"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=o,U,o, r,o")
+ (match_operand:TF 1 "input_operand" " G,o,U,roG,r"))]
"! TARGET_FPU
&& ! TARGET_ARCH64
&& (register_operand (operands[0], TFmode)
@@ -2312,8 +2313,8 @@
[(set_attr "length" "4")])
(define_insn "*movtf_insn_sp64"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,o,r")
- (match_operand:TF 1 "input_operand" "G,oe,Ger,roG"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=b, e, o, r")
+ (match_operand:TF 1 "input_operand" "G,oe,Ger,roG"))]
"TARGET_FPU
&& TARGET_ARCH64
&& ! TARGET_HARD_QUAD
@@ -2323,8 +2324,8 @@
[(set_attr "length" "2")])
(define_insn "*movtf_insn_sp64_hq"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,e,m,o,r")
- (match_operand:TF 1 "input_operand" "G,e,m,e,rG,roG"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "=b,e,e,m, o, r")
+ (match_operand:TF 1 "input_operand" "G,e,m,e,rG,roG"))]
"TARGET_FPU
&& TARGET_ARCH64
&& TARGET_HARD_QUAD
@@ -2341,8 +2342,8 @@
(set_attr "length" "2,*,*,*,2,2")])
(define_insn "*movtf_insn_sp64_no_fpu"
- [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
- (match_operand:TF 1 "input_operand" "orG,rG"))]
+ [(set (match_operand:TF 0 "nonimmediate_operand" "= r, o")
+ (match_operand:TF 1 "input_operand" "orG,rG"))]
"! TARGET_FPU
&& TARGET_ARCH64
&& (register_operand (operands[0], TFmode)
@@ -2484,11 +2485,9 @@
(match_operand:I 3 "arith10_operand" "")))]
"TARGET_V9 && !(<I:MODE>mode == DImode && TARGET_ARCH32)"
{
- enum rtx_code code = GET_CODE (operands[1]);
rtx cc_reg;
- if (GET_MODE (XEXP (operands[1], 0)) == DImode
- && ! TARGET_ARCH64)
+ if (GET_MODE (XEXP (operands[1], 0)) == DImode && !TARGET_ARCH64)
FAIL;
if (GET_MODE (XEXP (operands[1], 0)) == TFmode && !TARGET_HARD_QUAD)
@@ -2499,12 +2498,14 @@
if (XEXP (operands[1], 1) == const0_rtx
&& GET_CODE (XEXP (operands[1], 0)) == REG
&& GET_MODE (XEXP (operands[1], 0)) == DImode
- && v9_regcmp_p (code))
+ && v9_regcmp_p (GET_CODE (operands[1])))
cc_reg = XEXP (operands[1], 0);
else
cc_reg = gen_compare_reg (operands[1]);
- operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
+ operands[1]
+ = gen_rtx_fmt_ee (GET_CODE (operands[1]), GET_MODE (cc_reg), cc_reg,
+ const0_rtx);
})
(define_expand "mov<F:mode>cc"
@@ -2514,11 +2515,9 @@
(match_operand:F 3 "register_operand" "")))]
"TARGET_V9 && TARGET_FPU"
{
- enum rtx_code code = GET_CODE (operands[1]);
rtx cc_reg;
- if (GET_MODE (XEXP (operands[1], 0)) == DImode
- && ! TARGET_ARCH64)
+ if (GET_MODE (XEXP (operands[1], 0)) == DImode && !TARGET_ARCH64)
FAIL;
if (GET_MODE (XEXP (operands[1], 0)) == TFmode && !TARGET_HARD_QUAD)
@@ -2529,12 +2528,14 @@
if (XEXP (operands[1], 1) == const0_rtx
&& GET_CODE (XEXP (operands[1], 0)) == REG
&& GET_MODE (XEXP (operands[1], 0)) == DImode
- && v9_regcmp_p (code))
+ && v9_regcmp_p (GET_CODE (operands[1])))
cc_reg = XEXP (operands[1], 0);
else
cc_reg = gen_compare_reg (operands[1]);
- operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx);
+ operands[1]
+ = gen_rtx_fmt_ee (GET_CODE (operands[1]), GET_MODE (cc_reg), cc_reg,
+ const0_rtx);
})
;; Conditional move define_insns
@@ -6338,6 +6339,25 @@
""
[(set_attr "length" "0")])
+;; Do not schedule instructions accessing memory before this point.
+
+(define_expand "frame_blockage"
+ [(set (match_dup 0)
+ (unspec:BLK [(match_dup 1)] UNSPEC_FRAME_BLOCKAGE))]
+ ""
+{
+ operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
+ MEM_VOLATILE_P (operands[0]) = 1;
+ operands[1] = stack_pointer_rtx;
+})
+
+(define_insn "*frame_blockage<P:mode>"
+ [(set (match_operand:BLK 0 "" "")
+ (unspec:BLK [(match_operand:P 1 "" "")] UNSPEC_FRAME_BLOCKAGE))]
+ ""
+ ""
+ [(set_attr "length" "0")])
+
(define_expand "probe_stack"
[(set (match_operand 0 "memory_operand" "") (const_int 0))]
""
diff --git a/gcc-4.6/gcc/config/sparc/sparc.opt b/gcc-4.6/gcc/config/sparc/sparc.opt
index 295acdd..a97cad1 100644
--- a/gcc-4.6/gcc/config/sparc/sparc.opt
+++ b/gcc-4.6/gcc/config/sparc/sparc.opt
@@ -98,6 +98,11 @@ mstd-struct-return
Target Report RejectNegative Var(sparc_std_struct_return)
Enable strict 32-bit psABI struct return checking.
+mfix-at697f
+Target Report RejectNegative Var(sparc_fix_at697f)
+Enable workaround for single erratum of AT697F processor
+(corresponding to erratum #13 of AT697E processor)
+
Mask(LITTLE_ENDIAN)
;; Generate code for little-endian
generated by cgit v1.1 at 2025-08-18 13:08:52 +0000