Several fixes:

(1) Avoid hard-coding some register numbers.
(2) Fix some incorrect branch opcodes.
(3) Don't try to move int register to float register!
(4) If an operand being forwarded is a constant and it doesn't fit
    into the immed field of the copy machine instruction, then
    generate a load-constant instead of a copy.
(5) Use (unsigned long) 0 for copying a pointer via "add 0, ptr -> ptr2".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@683 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 1301 insertions, 1222 deletions

diff --git a/lib/Target/SparcV9/SparcV9InstrSelection.cpp b/lib/Target/SparcV9/SparcV9InstrSelection.cpp
index ca46798..e7cdbc0 100644
--- a/lib/Target/SparcV9/SparcV9InstrSelection.cpp
+++ b/lib/Target/SparcV9/SparcV9InstrSelection.cpp
@@ -4,6 +4,7 @@
 //	SparcInstrSelection.cpp
 // 
 // Purpose:
+//      BURS instruction selection for SPARC V9 architecture.      
 //	
 // History:
 //	7/02/01	 -  Vikram Adve  -  Created
@@ -27,8 +28,8 @@
 
 // to be used later
 struct BranchPattern {
-  bool	        flipCondition; // should the sense of the test be reversed
-  BasicBlock*	targetBB;      // which basic block to branch to
+  bool          flipCondition; // should the sense of the test be reversed
+  BasicBlock*   targetBB;      // which basic block to branch to
   MachineInstr* extraBranch;   // if neither branch is fall-through, then this
                                // BA must be inserted after the cond'l one
 };
@@ -36,68 +37,12 @@ struct BranchPattern {
 //************************* Forward Declarations ***************************/
 
 
-static MachineOpCode ChooseBprInstruction   (const InstructionNode* instrNode);
-
-static MachineOpCode ChooseBccInstruction   (const InstructionNode* instrNode,
-					     bool& isFPBranch);
-
-static MachineOpCode ChooseBpccInstruction  (const InstructionNode* instrNode,
-					     const BinaryOperator* setCCInst);
-
-static MachineOpCode ChooseBFpccInstruction (const InstructionNode* instrNode,
-					     const BinaryOperator* setCCInst);
-
-static MachineOpCode ChooseMovFpccInstruction(const InstructionNode*);
-
-static MachineOpCode ChooseMovpccAfterSub   (const InstructionNode* instrNode,
-					     bool& mustClearReg,
-					     int& valueToMove);
-
-static MachineOpCode ChooseConvertToFloatInstr(const InstructionNode*,
-					       const Type* opType);
-
-static MachineOpCode ChooseConvertToIntInstr(const InstructionNode* instrNode,
-					     const Type* opType);
-
-static MachineOpCode ChooseAddInstruction   (const InstructionNode* instrNode);
-
-static MachineOpCode ChooseSubInstruction   (const InstructionNode* instrNode);
-
-static MachineOpCode ChooseFcmpInstruction  (const InstructionNode* instrNode);
-
-static MachineOpCode ChooseMulInstruction   (const InstructionNode* instrNode,
-					     bool checkCasts);
-
-static MachineOpCode ChooseDivInstruction   (const InstructionNode* instrNode);
-
-static MachineOpCode ChooseLoadInstruction  (const Type* resultType);
-
-static MachineOpCode ChooseStoreInstruction (const Type* valueType);
-
-static void		SetOperandsForMemInstr(MachineInstr* minstr,
-					 const InstructionNode* vmInstrNode,
-					 const TargetMachine& target);
-
-static void		SetMemOperands_Internal	(MachineInstr* minstr,
-					 const InstructionNode* vmInstrNode,
-					 Value* ptrVal,
-					 Value* arrayOffsetVal,
-					 const vector<ConstPoolVal*>& idxVec,
-					 const TargetMachine& target);
-
-static unsigned		FixConstantOperands(const InstructionNode* vmInstrNode,
-					    MachineInstr** mvec,
-					    unsigned numInstr,
-					    TargetMachine& target);
-
-static MachineInstr*	MakeLoadConstInstr(Instruction* vmInstr,
-					   Value* val,
-					   TmpInstruction*& tmpReg,
-					   MachineInstr*& getMinstr2);
-
-static void		ForwardOperand	(InstructionNode* treeNode,
-					 InstrTreeNode*   parent,
-					 int operandNum);
+static void SetMemOperands_Internal     (MachineInstr* minstr,
+                                         const InstructionNode* vmInstrNode,
+                                         Value* ptrVal,
+                                         Value* arrayOffsetVal,
+                                         const vector<ConstPoolVal*>& idxVec,
+                                         const TargetMachine& target);
 
 
 //************************ Internal Functions ******************************/
@@ -105,31 +50,37 @@ static void		ForwardOperand	(InstructionNode* treeNode,
 // Convenience function to get the value of an integer constant, for an
 // appropriate integer or non-integer type that can be held in an integer.
 // The type of the argument must be the following:
-//	Signed or unsigned integer
-//	Boolean
-//	Pointer
+//      Signed or unsigned integer
+//      Boolean
+//      Pointer
 // 
 // isValidConstant is set to true if a valid constant was found.
 // 
 static int64_t
 GetConstantValueAsSignedInt(const Value *V,
-			    bool &isValidConstant)
+                            bool &isValidConstant)
 {
-  if (!V->isConstant()) { isValidConstant = false; return 0; }
+  if (!V->isConstant())
+    {
+      isValidConstant = false;
+      return 0;
+    }
+  
   isValidConstant = true;
   
   if (V->getType() == Type::BoolTy)
-    return ((ConstPoolBool*)V)->getValue();
-  if (V->getType()->isIntegral()) {
-    if (V->getType()->isSigned())
-      return ((ConstPoolSInt*)V)->getValue();
-    
-    assert(V->getType()->isUnsigned());
-    uint64_t Val = ((ConstPoolUInt*)V)->getValue();
-
-    if (Val < INT64_MAX)     // then safe to cast to signed
-      return (int64_t)Val;
-  }
+    return (int64_t) ((ConstPoolBool*)V)->getValue();
+  
+  if (V->getType()->isIntegral())
+    {
+      if (V->getType()->isSigned())
+        return ((ConstPoolSInt*)V)->getValue();
+      
+      assert(V->getType()->isUnsigned());
+      uint64_t Val = ((ConstPoolUInt*)V)->getValue();
+      if (Val < INT64_MAX)     // then safe to cast to signed
+        return (int64_t)Val;
+    }
 
   isValidConstant = false;
   return 0;
@@ -150,10 +101,7 @@ ThisIsAChainRule(int eruleno)
   switch(eruleno)
     {
     case 111:	// stmt:  reg
-    case 112:	// stmt:  boolconst
     case 113:	// stmt:  bool
-    case 121:
-    case 122:
     case 123:
     case 124:
     case 125:
@@ -165,11 +113,9 @@ ThisIsAChainRule(int eruleno)
     case 131:
     case 132:
     case 133:
-    case 153:
     case 155:
     case 221:
     case 222:
-    case 232:
     case 241:
     case 242:
     case 243:
@@ -209,25 +155,8 @@ ChooseBprInstruction(const InstructionNode* instrNode)
 
 
 static inline MachineOpCode 
-ChooseBccInstruction(const InstructionNode* instrNode,
-		     bool& isFPBranch)
-{
-  InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild();
-  BinaryOperator* setCCInstr = (BinaryOperator*) setCCNode->getInstruction();
-  const Type* setCCType = setCCInstr->getOperand(0)->getType();
-  
-  isFPBranch = (setCCType == Type::FloatTy || setCCType == Type::DoubleTy); 
-  
-  if (isFPBranch) 
-    return ChooseBFpccInstruction(instrNode, setCCInstr);
-  else
-    return ChooseBpccInstruction(instrNode, setCCInstr);
-}
-
-
-static inline MachineOpCode 
 ChooseBpccInstruction(const InstructionNode* instrNode,
-		      const BinaryOperator* setCCInstr)
+                      const BinaryOperator* setCCInstr)
 {
   MachineOpCode opCode = INVALID_OPCODE;
   
@@ -236,32 +165,32 @@ ChooseBpccInstruction(const InstructionNode* instrNode,
   if (isSigned)
     {
       switch(setCCInstr->getOpcode())
-	{
-	case Instruction::SetEQ: opCode = BE;  break;
-	case Instruction::SetNE: opCode = BNE; break;
-	case Instruction::SetLE: opCode = BLE; break;
-	case Instruction::SetGE: opCode = BGE; break;
-	case Instruction::SetLT: opCode = BL;  break;
-	case Instruction::SetGT: opCode = BG;  break;
-	default:
-	  assert(0 && "Unrecognized VM instruction!");
-	  break; 
-	}
+        {
+        case Instruction::SetEQ: opCode = BE;  break;
+        case Instruction::SetNE: opCode = BNE; break;
+        case Instruction::SetLE: opCode = BLE; break;
+        case Instruction::SetGE: opCode = BGE; break;
+        case Instruction::SetLT: opCode = BL;  break;
+        case Instruction::SetGT: opCode = BG;  break;
+        default:
+          assert(0 && "Unrecognized VM instruction!");
+          break; 
+        }
     }
   else
     {
       switch(setCCInstr->getOpcode())
-	{
-	case Instruction::SetEQ: opCode = BE;   break;
-	case Instruction::SetNE: opCode = BNE;  break;
-	case Instruction::SetLE: opCode = BLEU; break;
-	case Instruction::SetGE: opCode = BCC;  break;
-	case Instruction::SetLT: opCode = BCS;  break;
-	case Instruction::SetGT: opCode = BGU;  break;
-	default:
-	  assert(0 && "Unrecognized VM instruction!");
-	  break; 
-	}
+        {
+        case Instruction::SetEQ: opCode = BE;   break;
+        case Instruction::SetNE: opCode = BNE;  break;
+        case Instruction::SetLE: opCode = BLEU; break;
+        case Instruction::SetGE: opCode = BCC;  break;
+        case Instruction::SetLT: opCode = BCS;  break;
+        case Instruction::SetGT: opCode = BGU;  break;
+        default:
+          assert(0 && "Unrecognized VM instruction!");
+          break; 
+        }
     }
   
   return opCode;
@@ -269,7 +198,7 @@ ChooseBpccInstruction(const InstructionNode* instrNode,
 
 static inline MachineOpCode 
 ChooseBFpccInstruction(const InstructionNode* instrNode,
-		       const BinaryOperator* setCCInstr)
+                       const BinaryOperator* setCCInstr)
 {
   MachineOpCode opCode = INVALID_OPCODE;
   
@@ -291,6 +220,23 @@ ChooseBFpccInstruction(const InstructionNode* instrNode,
 
 
 static inline MachineOpCode 
+ChooseBccInstruction(const InstructionNode* instrNode,
+                     bool& isFPBranch)
+{
+  InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild();
+  BinaryOperator* setCCInstr = (BinaryOperator*) setCCNode->getInstruction();
+  const Type* setCCType = setCCInstr->getOperand(0)->getType();
+  
+  isFPBranch = (setCCType == Type::FloatTy || setCCType == Type::DoubleTy); 
+  
+  if (isFPBranch) 
+    return ChooseBFpccInstruction(instrNode, setCCInstr);
+  else
+    return ChooseBpccInstruction(instrNode, setCCInstr);
+}
+
+
+static inline MachineOpCode 
 ChooseMovFpccInstruction(const InstructionNode* instrNode)
 {
   MachineOpCode opCode = INVALID_OPCODE;
@@ -322,8 +268,8 @@ ChooseMovFpccInstruction(const InstructionNode* instrNode)
 // 
 static MachineOpCode
 ChooseMovpccAfterSub(const InstructionNode* instrNode,
-		     bool& mustClearReg,
-		     int& valueToMove)
+                     bool& mustClearReg,
+                     int& valueToMove)
 {
   MachineOpCode opCode = INVALID_OPCODE;
   mustClearReg = true;
@@ -346,7 +292,7 @@ ChooseMovpccAfterSub(const InstructionNode* instrNode,
 
 static inline MachineOpCode
 ChooseConvertToFloatInstr(const InstructionNode* instrNode,
-			  const Type* opType)
+                          const Type* opType)
 {
   MachineOpCode opCode = INVALID_OPCODE;
   
@@ -354,28 +300,28 @@ ChooseConvertToFloatInstr(const InstructionNode* instrNode,
     {
     case ToFloatTy: 
       if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy)
-	opCode = FITOS;
+        opCode = FITOS;
       else if (opType == Type::LongTy)
-	opCode = FXTOS;
+        opCode = FXTOS;
       else if (opType == Type::DoubleTy)
-	opCode = FDTOS;
+        opCode = FDTOS;
       else if (opType == Type::FloatTy)
-	;
+        ;
       else
-	assert(0 && "Cannot convert this type to FLOAT on SPARC");		
+        assert(0 && "Cannot convert this type to FLOAT on SPARC");
       break;
       
     case ToDoubleTy: 
       if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy)
-	opCode = FITOD;
+        opCode = FITOD;
       else if (opType == Type::LongTy)
-	opCode = FXTOD;
+        opCode = FXTOD;
       else if (opType == Type::FloatTy)
-	opCode = FSTOD;
+        opCode = FSTOD;
       else if (opType == Type::DoubleTy)
-	;
+        ;
       else
-	assert(0 && "Cannot convert this type to DOUBLE on SPARC");		
+        assert(0 && "Cannot convert this type to DOUBLE on SPARC");
       break;
       
     default:
@@ -387,7 +333,7 @@ ChooseConvertToFloatInstr(const InstructionNode* instrNode,
 
 static inline MachineOpCode 
 ChooseConvertToIntInstr(const InstructionNode* instrNode,
-			const Type* opType)
+                        const Type* opType)
 {
   MachineOpCode opCode = INVALID_OPCODE;;
   
@@ -396,24 +342,24 @@ ChooseConvertToIntInstr(const InstructionNode* instrNode,
   if (instrType == ToSByteTy || instrType == ToShortTy || instrType == ToIntTy)
     {
       switch (opType->getPrimitiveID())
-	{
+        {
         case Type::FloatTyID:   opCode = FSTOI; break;
         case Type::DoubleTyID:  opCode = FDTOI; break;
-	default:
-	  assert(0 && "Non-numeric non-bool type cannot be converted to Int");
-	  break;
-	}
+        default:
+          assert(0 && "Non-numeric non-bool type cannot be converted to Int");
+          break;
+        }
     }
   else if (instrType == ToLongTy)
     {
       switch (opType->getPrimitiveID())
-	{
+        {
         case Type::FloatTyID:   opCode = FSTOX; break;
         case Type::DoubleTyID:  opCode = FDTOX; break;
-	default:
-	  assert(0 && "Non-numeric non-bool type cannot be converted to Long");
-	  break;
-	}
+        default:
+          assert(0 && "Non-numeric non-bool type cannot be converted to Long");
+          break;
+        }
     }
   else
       assert(0 && "Should not get here, Mo!");
@@ -423,44 +369,47 @@ ChooseConvertToIntInstr(const InstructionNode* instrNode,
 
 
 static inline MachineOpCode 
-ChooseAddInstruction(const InstructionNode* instrNode)
+ChooseAddInstructionByType(const Type* resultType)
 {
   MachineOpCode opCode = INVALID_OPCODE;
   
-  const Type* resultType = instrNode->getInstruction()->getType();
-  
   if (resultType->isIntegral() ||
       resultType->isPointerType() ||
       resultType->isMethodType() ||
-      resultType->isLabelType())
+      resultType->isLabelType() ||
+      resultType == Type::BoolTy)
     {
       opCode = ADD;
     }
   else
-    {
-      Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue();
-      switch(operand->getType()->getPrimitiveID())
-	{
-	case Type::FloatTyID:  opCode = FADDS; break;
-	case Type::DoubleTyID: opCode = FADDD; break;
-	default: assert(0 && "Invalid type for ADD instruction"); break; 
-	}
-    }
+    switch(resultType->getPrimitiveID())
+      {
+      case Type::FloatTyID:  opCode = FADDS; break;
+      case Type::DoubleTyID: opCode = FADDD; break;
+      default: assert(0 && "Invalid type for ADD instruction"); break; 
+      }
   
   return opCode;
 }
 
 
+static inline MachineOpCode 
+ChooseAddInstruction(const InstructionNode* instrNode)
+{
+  return ChooseAddInstructionByType(instrNode->getInstruction()->getType());
+}
+
+
 static inline MachineInstr* 
 CreateMovFloatInstruction(const InstructionNode* instrNode,
-			  const Type* resultType)
+                          const Type* resultType)
 {
   MachineInstr* minstr = new MachineInstr((resultType == Type::FloatTy)
-					  ? FMOVS : FMOVD);
+                                          ? FMOVS : FMOVD);
   minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
-			    instrNode->leftChild()->getValue());
+                            instrNode->leftChild()->getValue());
   minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
-			    instrNode->getValue());
+                            instrNode->getValue());
   return minstr;
 }
 
@@ -478,11 +427,13 @@ CreateAddConstInstruction(const InstructionNode* instrNode)
   // 
   const Type* resultType = instrNode->getInstruction()->getType();
   
-  if (resultType == Type::FloatTy || resultType == Type::DoubleTy) {
-    double dval = ((ConstPoolFP*) constOp)->getValue();
-    if (dval == 0.0)
-      minstr = CreateMovFloatInstruction(instrNode, resultType);
-  }
+  if (resultType == Type::FloatTy ||
+      resultType == Type::DoubleTy)
+    {
+      double dval = ((ConstPoolFP*) constOp)->getValue();
+      if (dval == 0.0)
+        minstr = CreateMovFloatInstruction(instrNode, resultType);
+    }
   
   return minstr;
 }
@@ -501,15 +452,12 @@ ChooseSubInstruction(const InstructionNode* instrNode)
       opCode = SUB;
     }
   else
-    {
-      Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue();
-      switch(operand->getType()->getPrimitiveID())
-	{
-	case Type::FloatTyID:  opCode = FSUBS; break;
-	case Type::DoubleTyID: opCode = FSUBD; break;
-	default: assert(0 && "Invalid type for SUB instruction"); break; 
-	}
-    }
+    switch(resultType->getPrimitiveID())
+      {
+      case Type::FloatTyID:  opCode = FSUBS; break;
+      case Type::DoubleTyID: opCode = FSUBD; break;
+      default: assert(0 && "Invalid type for SUB instruction"); break; 
+      }
   
   return opCode;
 }
@@ -534,7 +482,7 @@ CreateSubConstInstruction(const InstructionNode* instrNode)
     {
       double dval = ((ConstPoolFP*) constOp)->getValue();
       if (dval == 0.0)
-	minstr = CreateMovFloatInstruction(instrNode, resultType);
+        minstr = CreateMovFloatInstruction(instrNode, resultType);
     }
   
   return minstr;
@@ -570,14 +518,14 @@ BothFloatToDouble(const InstructionNode* instrNode)
   
   // Check if both arguments are floats cast to double
   return (leftArg->getValue()->getType() == Type::DoubleTy &&
-	  leftArgArg->getValue()->getType() == Type::FloatTy &&
-	  rightArgArg->getValue()->getType() == Type::FloatTy);
+          leftArgArg->getValue()->getType() == Type::FloatTy &&
+          rightArgArg->getValue()->getType() == Type::FloatTy);
 }
 
 
 static inline MachineOpCode 
 ChooseMulInstruction(const InstructionNode* instrNode,
-		     bool checkCasts)
+                     bool checkCasts)
 {
   MachineOpCode opCode = INVALID_OPCODE;
   
@@ -594,24 +542,23 @@ ChooseMulInstruction(const InstructionNode* instrNode,
       opCode = MULX;
     }
   else
-    {
-      switch(instrNode->leftChild()->getValue()->getType()->getPrimitiveID())
-	{
-	case Type::FloatTyID:  opCode = FMULS; break;
-	case Type::DoubleTyID: opCode = FMULD; break;
-	default: assert(0 && "Invalid type for MUL instruction"); break; 
-	}
-    }
+    switch(resultType->getPrimitiveID())
+      {
+      case Type::FloatTyID:  opCode = FMULS; break;
+      case Type::DoubleTyID: opCode = FMULD; break;
+      default: assert(0 && "Invalid type for MUL instruction"); break; 
+      }
   
   return opCode;
 }
 
 
 static inline MachineInstr*
-CreateIntNegInstruction(Value* vreg)
+CreateIntNegInstruction(TargetMachine& target,
+                        Value* vreg)
 {
   MachineInstr* minstr = new MachineInstr(SUB);
-  minstr->SetMachineOperand(0, /*regNum %g0*/(unsigned int) 0);
+  minstr->SetMachineOperand(0, target.getRegInfo().getZeroRegNum());
   minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, vreg);
   minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, vreg);
   return minstr;
@@ -619,8 +566,9 @@ CreateIntNegInstruction(Value* vreg)
 
 
 static inline MachineInstr* 
-CreateMulConstInstruction(const InstructionNode* instrNode,
-			  MachineInstr*& getMinstr2)
+CreateMulConstInstruction(TargetMachine &target,
+                          const InstructionNode* instrNode,
+                          MachineInstr*& getMinstr2)
 {
   MachineInstr* minstr = NULL;
   getMinstr2 = NULL;
@@ -641,111 +589,111 @@ CreateMulConstInstruction(const InstructionNode* instrNode,
       bool isValidConst;
       int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
       if (isValidConst)
-	{
-	  bool needNeg = false;
-	  if (C < 0)
-	    {
-	      needNeg = true;
-	      C = -C;
-	    }
-	  
-	  if (C == 0 || C == 1)
-	    {
-	      minstr = new MachineInstr(ADD);
-	      
-	      if (C == 0)
-		minstr->SetMachineOperand(0, /*regNum %g0*/ (unsigned int) 0);
-	      else
-		minstr->SetMachineOperand(0,MachineOperand::MO_VirtualRegister,
-					  instrNode->leftChild()->getValue());
-	      minstr->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0);
-	    }
-	  else if (IsPowerOf2(C, pow))
-	    {
-	      minstr = new MachineInstr((resultType == Type::LongTy)
-					? SLLX : SLL);
-	      minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
-					   instrNode->leftChild()->getValue());
-	      minstr->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed,
-					   pow);
-	    }
-	  
-	  if (minstr && needNeg)
-	    { // insert <reg = SUB 0, reg> after the instr to flip the sign
-	      getMinstr2 = CreateIntNegInstruction(instrNode->getValue());
-	    }
-	}
+        {
+          bool needNeg = false;
+          if (C < 0)
+            {
+              needNeg = true;
+              C = -C;
+            }
+          
+          if (C == 0 || C == 1)
+            {
+              minstr = new MachineInstr(ADD);
+              
+              if (C == 0)
+                minstr->SetMachineOperand(0,
+                                          target.getRegInfo().getZeroRegNum());
+              else
+                minstr->SetMachineOperand(0,MachineOperand::MO_VirtualRegister,
+                                          instrNode->leftChild()->getValue());
+              minstr->SetMachineOperand(1,target.getRegInfo().getZeroRegNum());
+            }
+          else if (IsPowerOf2(C, pow))
+            {
+              minstr = new MachineInstr((resultType == Type::LongTy)
+                                        ? SLLX : SLL);
+              minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
+                                           instrNode->leftChild()->getValue());
+              minstr->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed,
+                                           pow);
+            }
+          
+          if (minstr && needNeg)
+            { // insert <reg = SUB 0, reg> after the instr to flip the sign
+              getMinstr2 = CreateIntNegInstruction(target,
+                                                   instrNode->getValue());
+            }
+        }
     }
   else
     {
       if (resultType == Type::FloatTy ||
-	  resultType == Type::DoubleTy)
-	{
-	  bool isValidConst;
-	  double dval = ((ConstPoolFP*) constOp)->getValue();
-	  
-	  if (isValidConst)
-	    {
-	      if (dval == 0)
-		{
-		  minstr = new MachineInstr((resultType == Type::FloatTy)
-					    ? FITOS : FITOD);
-		  minstr->SetMachineOperand(0, /*regNum %g0*/(unsigned int) 0);
-		}
-	      else if (fabs(dval) == 1)
-		{
-		  bool needNeg = (dval < 0);
-		  
-		  MachineOpCode opCode = needNeg
-		    ? (resultType == Type::FloatTy? FNEGS : FNEGD)
-		    : (resultType == Type::FloatTy? FMOVS : FMOVD);
-		  
-		  minstr = new MachineInstr(opCode);
-		  minstr->SetMachineOperand(0,
-					   MachineOperand::MO_VirtualRegister,
-					   instrNode->leftChild()->getValue());
-		} 
-	    }
-	}
+          resultType == Type::DoubleTy)
+        {
+          bool isValidConst;
+          double dval = ((ConstPoolFP*) constOp)->getValue();
+          
+          if (isValidConst)
+            {
+              if (dval == 0)
+                {
+                  minstr = new MachineInstr((resultType == Type::FloatTy)
+                                            ? FITOS : FITOD);
+                  minstr->SetMachineOperand(0,
+                                        target.getRegInfo().getZeroRegNum());
+                }
+              else if (fabs(dval) == 1)
+                {
+                  bool needNeg = (dval < 0);
+                  
+                  MachineOpCode opCode = needNeg
+                    ? (resultType == Type::FloatTy? FNEGS : FNEGD)
+                    : (resultType == Type::FloatTy? FMOVS : FMOVD);
+                  
+                  minstr = new MachineInstr(opCode);
+                  minstr->SetMachineOperand(0,
+                                           MachineOperand::MO_VirtualRegister,
+                                           instrNode->leftChild()->getValue());
+                } 
+            }
+        }
     }
   
   if (minstr != NULL)
     minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
-			      instrNode->getValue());   
+                              instrNode->getValue());   
   
   return minstr;
 }
 
 
 static inline MachineOpCode 
-ChooseDivInstruction(const InstructionNode* instrNode)
+ChooseDivInstruction(TargetMachine &target,
+                     const InstructionNode* instrNode)
 {
   MachineOpCode opCode = INVALID_OPCODE;
   
   const Type* resultType = instrNode->getInstruction()->getType();
   
   if (resultType->isIntegral())
-    {
-      opCode = resultType->isSigned()? SDIVX : UDIVX;
-    }
+    opCode = resultType->isSigned()? SDIVX : UDIVX;
   else
-    {
-      Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue();
-      switch(operand->getType()->getPrimitiveID())
-	{
-	case Type::FloatTyID:  opCode = FDIVS; break;
-	case Type::DoubleTyID: opCode = FDIVD; break;
-	default: assert(0 && "Invalid type for DIV instruction"); break; 
-	}
-    }
+    switch(resultType->getPrimitiveID())
+      {
+      case Type::FloatTyID:  opCode = FDIVS; break;
+      case Type::DoubleTyID: opCode = FDIVD; break;
+      default: assert(0 && "Invalid type for DIV instruction"); break; 
+      }
   
   return opCode;
 }
 
 
 static inline MachineInstr* 
-CreateDivConstInstruction(const InstructionNode* instrNode,
-			  MachineInstr*& getMinstr2)
+CreateDivConstInstruction(TargetMachine &target,
+                          const InstructionNode* instrNode,
+                          MachineInstr*& getMinstr2)
 {
   MachineInstr* minstr = NULL;
   getMinstr2 = NULL;
@@ -765,71 +713,74 @@ CreateDivConstInstruction(const InstructionNode* instrNode,
       bool isValidConst;
       int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
       if (isValidConst)
-	{
-	  bool needNeg = false;
-	  if (C < 0)
-	    {
-	      needNeg = true;
-	      C = -C;
-	    }
-	  
-	  if (C == 1)
-	    {
-	      minstr = new MachineInstr(ADD);
-	      minstr->SetMachineOperand(0,MachineOperand::MO_VirtualRegister,
-					  instrNode->leftChild()->getValue());
-	      minstr->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0);
-	    }
-	  else if (IsPowerOf2(C, pow))
-	    {
-	      MachineOpCode opCode= ((resultType->isSigned())
-				     ? (resultType==Type::LongTy)? SRAX : SRA
-				     : (resultType==Type::LongTy)? SRLX : SRL);
-	      minstr = new MachineInstr(opCode);
-	      minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
-					   instrNode->leftChild()->getValue());
-	      minstr->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed,
-					   pow);
-	    }
-	  
-	  if (minstr && needNeg)
-	    { // insert <reg = SUB 0, reg> after the instr to flip the sign
-	      getMinstr2 = CreateIntNegInstruction(instrNode->getValue());
-	    }
-	}
+        {
+          bool needNeg = false;
+          if (C < 0)
+            {
+              needNeg = true;
+              C = -C;
+            }
+          
+          if (C == 1)
+            {
+              minstr = new MachineInstr(ADD);
+              minstr->SetMachineOperand(0,MachineOperand::MO_VirtualRegister,
+                                          instrNode->leftChild()->getValue());
+              minstr->SetMachineOperand(1,target.getRegInfo().getZeroRegNum());
+            }
+          else if (IsPowerOf2(C, pow))
+            {
+              MachineOpCode opCode= ((resultType->isSigned())
+                                     ? (resultType==Type::LongTy)? SRAX : SRA
+                                     : (resultType==Type::LongTy)? SRLX : SRL);
+              minstr = new MachineInstr(opCode);
+              minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
+                                           instrNode->leftChild()->getValue());
+              minstr->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed,
+                                           pow);
+            }
+          
+          if (minstr && needNeg)
+            { // insert <reg = SUB 0, reg> after the instr to flip the sign
+              getMinstr2 = CreateIntNegInstruction(target,
+                                                   instrNode->getValue());
+            }
+        }
     }
   else
     {
       if (resultType == Type::FloatTy ||
-	  resultType == Type::DoubleTy)
-	{
-	  bool isValidConst;
-	  double dval = ((ConstPoolFP*) constOp)->getValue();
-	  
-	  if (isValidConst && fabs(dval) == 1)
-	    {
-	      bool needNeg = (dval < 0);
-	      
-	      MachineOpCode opCode = needNeg
-		? (resultType == Type::FloatTy? FNEGS : FNEGD)
-		: (resultType == Type::FloatTy? FMOVS : FMOVD);
-	      
-	      minstr = new MachineInstr(opCode);
-	      minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
-					   instrNode->leftChild()->getValue());
-	    } 
-	}
+          resultType == Type::DoubleTy)
+        {
+          bool isValidConst;
+          double dval = ((ConstPoolFP*) constOp)->getValue();
+          
+          if (isValidConst && fabs(dval) == 1)
+            {
+              bool needNeg = (dval < 0);
+              
+              MachineOpCode opCode = needNeg
+                ? (resultType == Type::FloatTy? FNEGS : FNEGD)
+                : (resultType == Type::FloatTy? FMOVS : FMOVD);
+              
+              minstr = new MachineInstr(opCode);
+              minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
+                                           instrNode->leftChild()->getValue());
+            } 
+        }
     }
   
   if (minstr != NULL)
     minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
-			      instrNode->getValue());   
+                              instrNode->getValue());   
   
   return minstr;
 }
 
 
-static inline MachineOpCode ChooseLoadInstruction(const Type *DestTy) {
+static inline MachineOpCode
+ChooseLoadInstruction(const Type *DestTy)
+{
   switch (DestTy->getPrimitiveID()) {
   case Type::BoolTyID:
   case Type::UByteTyID:   return LDUB;
@@ -850,7 +801,9 @@ static inline MachineOpCode ChooseLoadInstruction(const Type *DestTy) {
 }
 
 
-static inline MachineOpCode ChooseStoreInstruction(const Type *DestTy) {
+static inline MachineOpCode
+ChooseStoreInstruction(const Type *DestTy)
+{
   switch (DestTy->getPrimitiveID()) {
   case Type::BoolTyID:
   case Type::UByteTyID:
@@ -889,8 +842,8 @@ static inline MachineOpCode ChooseStoreInstruction(const Type *DestTy) {
 
 static void
 SetOperandsForMemInstr(MachineInstr* minstr,
-		       const InstructionNode* vmInstrNode,
-		       const TargetMachine& target)
+                       const InstructionNode* vmInstrNode,
+                       const TargetMachine& target)
 {
   MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction();
   
@@ -908,8 +861,8 @@ SetOperandsForMemInstr(MachineInstr* minstr,
   // and in the right child for Store instructions.
   // 
   InstrTreeNode* ptrChild = (vmInstrNode->getOpLabel() == Instruction::Store
-			     ? vmInstrNode->rightChild()
-			     : vmInstrNode->leftChild()); 
+                             ? vmInstrNode->rightChild()
+                             : vmInstrNode->leftChild()); 
   
   if (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
       ptrChild->getOpLabel() == GetElemPtrIdx)
@@ -927,7 +880,7 @@ SetOperandsForMemInstr(MachineInstr* minstr,
       idxVec = newIdxVec;
       
       assert(! ((PointerType*)ptrVal->getType())->getValueType()->isArrayType()
-	     && "GetElemPtr cannot be folded into array refs in selection");
+             && "GetElemPtr cannot be folded into array refs in selection");
     }
   else
     {
@@ -938,19 +891,19 @@ SetOperandsForMemInstr(MachineInstr* minstr,
       ptrVal = memInst->getPtrOperand();
 
       const Type* opType =
-	((const PointerType*) ptrVal->getType())->getValueType();
+        ((const PointerType*) ptrVal->getType())->getValueType();
       if (opType->isArrayType())
-	{
-	  assert((memInst->getNumOperands()
-		  == (unsigned) 1 + memInst->getFirstOffsetIdx())
-		 && "Array refs must be lowered before Instruction Selection");
-	  
-	  arrayOffsetVal = memInst->getOperand(memInst->getFirstOffsetIdx());
-	}
+        {
+          assert((memInst->getNumOperands()
+                  == (unsigned) 1 + memInst->getFirstOffsetIdx())
+                 && "Array refs must be lowered before Instruction Selection");
+          
+          arrayOffsetVal = memInst->getOperand(memInst->getFirstOffsetIdx());
+        }
     }
   
   SetMemOperands_Internal(minstr, vmInstrNode, ptrVal, arrayOffsetVal,
-			  *idxVec, target);
+                          *idxVec, target);
   
   if (newIdxVec != NULL)
     delete newIdxVec;
@@ -959,11 +912,11 @@ SetOperandsForMemInstr(MachineInstr* minstr,
 
 static void
 SetMemOperands_Internal(MachineInstr* minstr,
-			const InstructionNode* vmInstrNode,
-			Value* ptrVal,
-			Value* arrayOffsetVal,
-			const vector<ConstPoolVal*>& idxVec,
-			const TargetMachine& target)
+                        const InstructionNode* vmInstrNode,
+                        Value* ptrVal,
+                        Value* arrayOffsetVal,
+                        const vector<ConstPoolVal*>& idxVec,
+                        const TargetMachine& target)
 {
   MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction();
   
@@ -983,41 +936,41 @@ SetMemOperands_Internal(MachineInstr* minstr,
       const PointerType* ptrType = (PointerType*) ptrVal->getType();
       
       if (ptrType->getValueType()->isStructType())
-	{
-	  // the offset is always constant for structs
-	  isConstantOffset = true;
-	  
-	  // Compute the offset value using the index vector
-	  offset = target.DataLayout.getIndexedOffset(ptrType, idxVec);
-	}
+        {
+          // the offset is always constant for structs
+          isConstantOffset = true;
+          
+          // Compute the offset value using the index vector
+          offset = target.DataLayout.getIndexedOffset(ptrType, idxVec);
+        }
       else
-	{
-	  // It must be an array ref.  Check if the offset is a constant,
-	  // and that the indexing has been lowered to a single offset.
-	  // 
-	  assert(ptrType->getValueType()->isArrayType());
-	  assert(arrayOffsetVal != NULL
-		 && "Expect to be given Value* for array offsets");
-	  
-	  if (ConstPoolVal *CPV = arrayOffsetVal->castConstant())
-	    {
-	      isConstantOffset = true;	// always constant for structs
-	      assert(arrayOffsetVal->getType()->isIntegral());
-	      offset = (CPV->getType()->isSigned()
-			? ((ConstPoolSInt*)CPV)->getValue()
-			: (int64_t) ((ConstPoolUInt*)CPV)->getValue());
-	    }
-	  else
-	    {
-	      valueForRegOffset = arrayOffsetVal;
-	    }
-	}
+        {
+          // It must be an array ref.  Check if the offset is a constant,
+          // and that the indexing has been lowered to a single offset.
+          // 
+          assert(ptrType->getValueType()->isArrayType());
+          assert(arrayOffsetVal != NULL
+                 && "Expect to be given Value* for array offsets");
+          
+          if (ConstPoolVal *CPV = arrayOffsetVal->castConstant())
+            {
+              isConstantOffset = true;  // always constant for structs
+              assert(arrayOffsetVal->getType()->isIntegral());
+              offset = (CPV->getType()->isSigned()
+                        ? ((ConstPoolSInt*)CPV)->getValue()
+                        : (int64_t) ((ConstPoolUInt*)CPV)->getValue());
+            }
+          else
+            {
+              valueForRegOffset = arrayOffsetVal;
+            }
+        }
       
       if (isConstantOffset)
-	{
-	  // create a virtual register for the constant
-	  valueForRegOffset = ConstPoolSInt::get(Type::IntTy, offset);
-	}
+        {
+          // create a virtual register for the constant
+          valueForRegOffset = ConstPoolSInt::get(Type::IntTy, offset);
+        }
     }
   else
     {
@@ -1031,7 +984,7 @@ SetMemOperands_Internal(MachineInstr* minstr,
   minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, leftVal);
   
   // Operand 1 is ptr for STORE, offset for LOAD or GET_ELEMENT_PTR
-  // Operand 3 is offset for STORE, result reg for LOAD or GET_ELEMENT_PTR
+  // Operand 2 is offset for STORE, result reg for LOAD or GET_ELEMENT_PTR
   //
   unsigned offsetOpNum = (memInst->getOpcode() == Instruction::Store)? 2 : 1;
   if (offsetOpType == MachineOperand::MO_VirtualRegister)
@@ -1046,96 +999,12 @@ SetMemOperands_Internal(MachineInstr* minstr,
     minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, ptrVal);
   else
     minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
-			         vmInstrNode->getValue());
-}
-
-
-// Special handling for constant operands:
-// -- if the constant is 0, use the hardwired 0 register, if any;
-// -- if the constant is of float or double type but has an integer value,
-//    use int-to-float conversion instruction instead of generating a load;
-// -- if the constant fits in the IMMEDIATE field, use that field;
-// -- else insert instructions to put the constant into a register, either
-//    directly or by loading explicitly from the constant pool.
-// 
-static unsigned
-FixConstantOperands(const InstructionNode* vmInstrNode,
-		    MachineInstr** mvec,
-		    unsigned numInstr,
-		    TargetMachine& target)
-{
-  static MachineInstr* loadConstVec[MAX_INSTR_PER_VMINSTR];
-
-  unsigned numNew = 0;
-  Instruction* vmInstr = vmInstrNode->getInstruction();
-  
-  for (unsigned i=0; i < numInstr; i++)
-    {
-      MachineInstr* minstr = mvec[i];
-      const MachineInstrDescriptor& instrDesc =
-	target.getInstrInfo().getDescriptor(minstr->getOpCode());
-      
-      for (unsigned op=0; op < minstr->getNumOperands(); op++)
-	{
-	  const MachineOperand& mop = minstr->getOperand(op);
-	  
-	  // skip the result position (for efficiency below) and any other
-	  // positions already marked as not a virtual register
-	  if (instrDesc.resultPos == (int) op || 
-	      mop.getOperandType() != MachineOperand::MO_VirtualRegister ||
-	      mop.getVRegValue() == NULL)
-	    {
-	      break;
-	    }
-	  
-	  Value* opValue = mop.getVRegValue();
-	  
-	  if (opValue->isConstant())
-	    {
-	      unsigned int machineRegNum;
-	      int64_t immedValue;
-	      MachineOperand::MachineOperandType opType =
-		ChooseRegOrImmed(opValue, minstr->getOpCode(), target,
-				 /*canUseImmed*/ (op == 1),
-				 machineRegNum, immedValue);
-	      
-	      if (opType == MachineOperand::MO_MachineRegister)
-		minstr->SetMachineOperand(op, machineRegNum);
-	      else if (opType == MachineOperand::MO_VirtualRegister)
-		{
-		  // value is constant and must be loaded into a register
-		  TmpInstruction* tmpReg;
-		  MachineInstr* minstr2;
-		  loadConstVec[numNew++] = MakeLoadConstInstr(vmInstr, opValue,
-							      tmpReg, minstr2);
-		  minstr->SetMachineOperand(op, opType, tmpReg);
-		  if (minstr2 != NULL)
-		    loadConstVec[numNew++] = minstr2;
-		}
-	      else
-		minstr->SetMachineOperand(op, opType, immedValue);
-	    }
-	}
-    }
-  
-  if (numNew > 0)
-    {
-      // Insert the new instructions *before* the old ones by moving
-      // the old ones over `numNew' positions (last-to-first, of course!).
-      // We do check *after* returning that we did not exceed the vector mvec.
-      for (int i=numInstr-1; i >= 0; i--)
-	mvec[i+numNew] = mvec[i];
-      
-      for (unsigned i=0; i < numNew; i++)
-	mvec[i] = loadConstVec[i];
-    }
-  
-  return (numInstr + numNew);
+                                 vmInstrNode->getValue());
 }
 
 
 static inline MachineInstr*
-MakeIntSetInstruction(int64_t C, bool isSigned, Value* dest)
+CreateIntSetInstruction(int64_t C, bool isSigned, Value* dest)
 {
   MachineInstr* minstr;
   if (isSigned)
@@ -1155,22 +1024,25 @@ MakeIntSetInstruction(int64_t C, bool isSigned, Value* dest)
 }
 
 
+// Create an instruction sequence to load a constant into a register.
+// This always creates either one or two instructions.
+// If two instructions are created, the second one is returned in getMinstr2
+// The implicit virtual register used to hold the constant is returned in
+// tmpReg.
+// 
 static MachineInstr*
-MakeLoadConstInstr(Instruction* vmInstr,
-		   Value* val,
-		   TmpInstruction*& tmpReg,
-		   MachineInstr*& getMinstr2)
+CreateLoadConstInstr(const TargetMachine &target,
+                     Instruction* vmInstr,
+                     Value* val,
+                     Instruction* dest,
+                     MachineInstr*& getMinstr2)
 {
   assert(val->isConstant());
   
-  MachineInstr* minstr;
+  MachineInstr* minstr1 = NULL;
   
   getMinstr2 = NULL;
   
-  // Create a TmpInstruction to mark the hidden register used for the constant
-  tmpReg = new TmpInstruction(Instruction::UserOp1, val, NULL);
-  vmInstr->getMachineInstrVec().addTempValue(tmpReg);
-  
   // Use a "set" instruction for known constants that can go in an integer reg.
   // Use a "set" instruction followed by a int-to-float conversion for known
   // constants that must go in a floating point reg but have an integer value.
@@ -1179,84 +1051,199 @@ MakeLoadConstInstr(Instruction* vmInstr,
   // 
   const Type* valType = val->getType();
   
-  if (valType->isIntegral() ||
-      valType->isPointerType() ||
-      valType == Type::BoolTy)
+  if (valType->isIntegral() || valType == Type::BoolTy)
     {
       bool isValidConstant;
       int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
       assert(isValidConstant && "Unrecognized constant");
-      
-      minstr = MakeIntSetInstruction(C, valType->isSigned(), tmpReg);
+      minstr1 = CreateIntSetInstruction(C, valType->isSigned(), dest);
     }
   else
     {
+      
+#undef MOVE_INT_TO_FP_REG_AVAILABLE
+#ifdef MOVE_INT_TO_FP_REG_AVAILABLE
+      //
+      // This code was written to generate the following sequence:
+      //        SET[SU]W <int-const> <int-reg>
+      //        FITO[SD] <int-reg>   <fp-reg>
+      // (it really should have moved the int-reg to an fp-reg and then FITOS).
+      // But for now the only way to move a value from an int-reg to an fp-reg
+      // is via memory.  Leave this code here but unused.
+      // 
       assert(valType == Type::FloatTy || valType == Type::DoubleTy);
       double dval = ((ConstPoolFP*) val)->getValue();
       if (dval == (int64_t) dval)
-	{
-	  // The constant actually has an integer value, so use a
-	  // [set; int-to-float] sequence instead of a load instruction.
-	  // 
-	  TmpInstruction* tmpReg2 = NULL;
-	  if (dval != 0.0)
-	    { // First, create an integer constant of the same value as dval
-	      ConstPoolSInt* ival = ConstPoolSInt::get(Type::IntTy,
-						       (int64_t) dval);
-	      // Create another TmpInstruction for the hidden integer register
-	      TmpInstruction* tmpReg2 =
-		new TmpInstruction(Instruction::UserOp1, ival, NULL);
-	      vmInstr->getMachineInstrVec().addTempValue(tmpReg2);
-	  
-	      // Create the `SET' instruction
-	      minstr = MakeIntSetInstruction((int64_t)dval, true, tmpReg2);
-	    }
-	  
-	  // In which variable do we put the second instruction?
-	  MachineInstr*& instr2 = (minstr)? getMinstr2 : minstr;
-	  
-	  // Create the int-to-float instruction
-	  instr2 = new MachineInstr(valType == Type::FloatTy? FITOS : FITOD);
-	  
-	  if (dval == 0.0)
-	    instr2->SetMachineOperand(0, /*regNum %g0*/ (unsigned int) 0);
-	  else
-	    instr2->SetMachineOperand(0,MachineOperand::MO_VirtualRegister,
-					  tmpReg2);
-	  
-	  instr2->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
-					   tmpReg);
-	}
+        {
+          // The constant actually has an integer value, so use a
+          // [set; int-to-float] sequence instead of a load instruction.
+          // 
+          TmpInstruction* tmpReg2 = NULL;
+          if (dval != 0.0)
+            { // First, create an integer constant of the same value as dval
+              ConstPoolSInt* ival = ConstPoolSInt::get(Type::IntTy,
+                                                       (int64_t) dval);
+              // Create another TmpInstruction for the hidden integer register
+              tmpReg2 = new TmpInstruction(Instruction::UserOp1, ival, NULL);
+              vmInstr->getMachineInstrVec().addTempValue(tmpReg2);
+              
+              // Create the `SET' instruction
+              minstr1 = CreateIntSetInstruction((int64_t)dval, true, tmpReg2);
+              tmpReg2->addMachineInstruction(minstr1);
+            }
+          
+          // In which variable do we put the second instruction?
+          MachineInstr*& instr2 = (minstr1)? getMinstr2 : minstr1;
+          
+          // Create the int-to-float instruction
+          instr2 = new MachineInstr(valType == Type::FloatTy? FITOS : FITOD);
+          
+          if (dval == 0.0)
+            instr2->SetMachineOperand(0, target.getRegInfo().getZeroRegNum());
+          else
+            instr2->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
+                                         tmpReg2);
+          
+          instr2->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
+                                         dest);
+        }
       else
-	{
-	  // Make a Load instruction, and make `val' both the ptr value *and*
-	  // the result value, and set the offset field to 0.  Final code
-	  // generation will have to generate the base+offset for the constant.
-	  // 
-	  int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
-	  minstr = new MachineInstr(ChooseLoadInstruction(val->getType()));
-	  minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,val);
-	  minstr->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,
-				       zeroOffset);
-	  minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
-				       tmpReg);
-	}
+#endif MOVE_INT_TO_FP_REG_AVAILABLE
+        
+        {
+          // Make an instruction sequence to load the constant, viz:
+          //            SETSW <addr-of-constant>, tmpReg2
+          //            LOAD  /*addr*/ tmpReg2, /*offset*/ 0, dest
+          // set the offset field to 0.
+          // 
+          int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
+
+          // Create another TmpInstruction for the hidden integer register
+          TmpInstruction* tmpReg2 =
+            new TmpInstruction(Instruction::UserOp1, val, NULL);
+          vmInstr->getMachineInstrVec().addTempValue(tmpReg2);
+          
+          minstr1 = new MachineInstr(SETUW);
+          minstr1->SetMachineOperand(0, MachineOperand::MO_PCRelativeDisp,val);
+          minstr1->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
+                                        tmpReg2);
+          tmpReg2->addMachineInstruction(minstr1);
+          
+          getMinstr2 = new MachineInstr(ChooseLoadInstruction(val->getType()));
+          getMinstr2->SetMachineOperand(0,MachineOperand::MO_VirtualRegister,
+                                          tmpReg2);
+          getMinstr2->SetMachineOperand(1,MachineOperand::MO_SignExtendedImmed,
+                                          zeroOffset);
+          getMinstr2->SetMachineOperand(2,MachineOperand::MO_VirtualRegister,
+                                          dest);
+        }
     }
   
-  tmpReg->addMachineInstruction(minstr);
+  assert(minstr1);
+  return minstr1;
+}
+
+// Special handling for constant operands:
+// -- if the constant is 0, use the hardwired 0 register, if any;
+// -- if the constant is of float or double type but has an integer value,
+//    use int-to-float conversion instruction instead of generating a load;
+// -- if the constant fits in the IMMEDIATE field, use that field;
+// -- else insert instructions to put the constant into a register, either
+//    directly or by loading explicitly from the constant pool.
+// 
+static unsigned
+FixConstantOperands(const InstructionNode* vmInstrNode,
+                    MachineInstr** mvec,
+                    unsigned numInstr,
+                    TargetMachine& target)
+{
+  static MachineInstr* loadConstVec[MAX_INSTR_PER_VMINSTR];
+
+  unsigned numNew = 0;
+  Instruction* vmInstr = vmInstrNode->getInstruction();
+  
+  for (unsigned i=0; i < numInstr; i++)
+    {
+      MachineInstr* minstr = mvec[i];
+      const MachineInstrDescriptor& instrDesc =
+        target.getInstrInfo().getDescriptor(minstr->getOpCode());
+      
+      for (unsigned op=0; op < minstr->getNumOperands(); op++)
+        {
+          const MachineOperand& mop = minstr->getOperand(op);
+          
+          // skip the result position (for efficiency below) and any other
+          // positions already marked as not a virtual register
+          if (instrDesc.resultPos == (int) op || 
+              mop.getOperandType() != MachineOperand::MO_VirtualRegister ||
+              mop.getVRegValue() == NULL)
+            {
+              continue;
+            }
+          
+          Value* opValue = mop.getVRegValue();
+          
+          if (opValue->isConstant())
+            {
+              unsigned int machineRegNum;
+              int64_t immedValue;
+              MachineOperand::MachineOperandType opType =
+                ChooseRegOrImmed(opValue, minstr->getOpCode(), target,
+                                 /*canUseImmed*/ (op == 1),
+                                 machineRegNum, immedValue);
+              
+              if (opType == MachineOperand::MO_MachineRegister)
+                minstr->SetMachineOperand(op, machineRegNum);
+              else if (opType == MachineOperand::MO_VirtualRegister)
+                {
+                  // value is constant and must be loaded into a register.
+                  // First, create a tmp virtual register (TmpInstruction)
+                  // to hold the constant.
+                  // This will replace the constant operand in `minstr'.
+                  TmpInstruction* tmpReg =
+                    new TmpInstruction(Instruction::UserOp1, opValue, NULL);
+                  vmInstr->getMachineInstrVec().addTempValue(tmpReg);
+                  minstr->SetMachineOperand(op, opType, tmpReg);
+                  
+                  MachineInstr *minstr1, *minstr2;
+                  minstr1 = CreateLoadConstInstr(target, vmInstr,
+                                                 opValue, tmpReg, minstr2);
+                  tmpReg->addMachineInstruction(minstr1);
+                  
+                  loadConstVec[numNew++] = minstr1;
+                  if (minstr2 != NULL)
+                    loadConstVec[numNew++] = minstr2;
+                }
+              else
+                minstr->SetMachineOperand(op, opType, immedValue);
+            }
+        }
+    }
   
-  assert(minstr);
-  return minstr;
+  if (numNew > 0)
+    {
+      // Insert the new instructions *before* the old ones by moving
+      // the old ones over `numNew' positions (last-to-first, of course!).
+      // We do check *after* returning that we did not exceed the vector mvec.
+      for (int i=numInstr-1; i >= 0; i--)
+        mvec[i+numNew] = mvec[i];
+      
+      for (unsigned i=0; i < numNew; i++)
+        mvec[i] = loadConstVec[i];
+    }
+  
+  return (numInstr + numNew);
 }
 
+
 // 
 // Substitute operand `operandNum' of the instruction in node `treeNode'
 // in place the use(s) of that instruction in node `parent'.
 // 
 static void
 ForwardOperand(InstructionNode* treeNode,
-	       InstrTreeNode*   parent,
-	       int operandNum)
+               InstrTreeNode*   parent,
+               int operandNum)
 {
   assert(treeNode && parent && "Invalid invocation of ForwardOperand");
   
@@ -1277,19 +1264,73 @@ ForwardOperand(InstructionNode* treeNode,
     {
       MachineInstr* minstr = mvec[i];
       for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; i++)
-	{
-	  const MachineOperand& mop = minstr->getOperand(i);
-	  if (mop.getOperandType() == MachineOperand::MO_VirtualRegister &&
-	      mop.getVRegValue() == unusedOp)
-	    {
-	      minstr->SetMachineOperand(i, MachineOperand::MO_VirtualRegister,
-					   fwdOp);
-	    }
-	}
+        {
+          const MachineOperand& mop = minstr->getOperand(i);
+          if (mop.getOperandType() == MachineOperand::MO_VirtualRegister &&
+              mop.getVRegValue() == unusedOp)
+            {
+              minstr->SetMachineOperand(i, MachineOperand::MO_VirtualRegister,
+                                           fwdOp);
+            }
+        }
     }
 }
 
 
+MachineInstr*
+CreateCopyInstructionsByType(const TargetMachine& target,
+                             Value* src,
+                             Instruction* dest,
+                             MachineInstr*& getMinstr2)
+{
+  getMinstr2 = NULL;                    // initialize second return value
+  
+  MachineInstr* minstr1 = NULL;
+  
+  const Type* resultType = dest->getType();
+  
+  MachineOpCode opCode = ChooseAddInstructionByType(resultType);
+  if (opCode == INVALID_OPCODE)
+    {
+      assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
+      return NULL;
+    }
+  
+  // if `src' is a constant that doesn't fit in the immed field, generate
+  // a load instruction instead of an add
+  if (src->isConstant())
+    {
+      unsigned int machineRegNum;
+      int64_t immedValue;
+      MachineOperand::MachineOperandType opType =
+        ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
+                         machineRegNum, immedValue);
+      
+      if (opType == MachineOperand::MO_VirtualRegister)
+        { // value is constant and cannot fit in immed field for the ADD
+          minstr1 = CreateLoadConstInstr(target, dest, src, dest, getMinstr2);
+        }
+    }
+  
+  if (minstr1 == NULL)
+    { // Create the appropriate add instruction.
+      // Make `src' the second operand, in case it is a constant
+      // Use (unsigned long) 0 for a NULL pointer value.
+      // 
+      const Type* nullValueType =
+        (resultType->getPrimitiveID() == Type::PointerTyID)? Type::ULongTy
+                                                           : resultType;
+      minstr1 = new MachineInstr(opCode);
+      minstr1->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
+                                 ConstPoolVal::getNullConstant(nullValueType));
+      minstr1->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, src);
+      minstr1->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, dest);
+    }
+  
+  return minstr1;
+}
+
+
 // This function is currently unused and incomplete but will be 
 // used if we have a linear layout of basic blocks in LLVM code.
 // It decides which branch should fall-through, and whether an
@@ -1301,11 +1342,11 @@ ChooseBranchPattern(Instruction* vmInstr, BranchPattern& brPattern)
   BranchInst* brInstr = (BranchInst*) vmInstr;
   
   brPattern.flipCondition = false;
-  brPattern.targetBB	  = brInstr->getSuccessor(0);
+  brPattern.targetBB      = brInstr->getSuccessor(0);
   brPattern.extraBranch   = NULL;
   
   assert(brInstr->getNumSuccessors() > 1 &&
-	 "Unnecessary analysis for unconditional branch");
+         "Unnecessary analysis for unconditional branch");
   
   assert(0 && "Fold branches in peephole optimization");
 }
@@ -1324,10 +1365,10 @@ ChooseBranchPattern(Instruction* vmInstr, BranchPattern& brPattern)
 
 unsigned
 GetInstructionsByRule(InstructionNode* subtreeRoot,
-		      int ruleForNode,
-		      short* nts,
-		      TargetMachine &target,
-		      MachineInstr** mvec)
+                      int ruleForNode,
+                      short* nts,
+                      TargetMachine &target,
+                      MachineInstr** mvec)
 {
   int numInstr = 1;			// initialize for common case
   bool checkCast = false;		// initialize here to use fall-through
@@ -1340,678 +1381,715 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
   
   mvec[0] = mvec[1] = mvec[2] = mvec[3] = NULL;	// just for safety
   
-  switch(ruleForNode) {
-  case 1:	// stmt:   Ret
-  case 2:	// stmt:   RetValue(reg)
-		// NOTE: Prepass of register allocation is responsible
-		//	 for moving return value to appropriate register.
-		// Mark the return-address register as a hidden virtual reg.
-    {		
-    Instruction* returnReg = new TmpInstruction(Instruction::UserOp1,
-					subtreeRoot->getInstruction(), NULL);
-    subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(returnReg);
-    
-    mvec[0] = new MachineInstr(RETURN);
-    mvec[0]->SetMachineOperand(0,MachineOperand::MO_VirtualRegister,returnReg);
-    mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed, s0);
-    
-    returnReg->addMachineInstruction(mvec[0]);
-    
-    mvec[numInstr++] = new MachineInstr(NOP); // delay slot
-    break;
-    }  
-    
-  case 3:	// stmt:   Store(reg,reg)
-  case 4:	// stmt:   Store(reg,ptrreg)
-    mvec[0] = new MachineInstr(ChooseStoreInstruction(subtreeRoot->leftChild()->getValue()->getType()));
-    SetOperandsForMemInstr(mvec[0], subtreeRoot, target);
-    break;
-    
-  case 5:	// stmt:   BrUncond
-    mvec[0] = new MachineInstr(BA);
-    mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister, (Value*)NULL);
-    mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
-	      ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
-    
-    // delay slot
-    mvec[numInstr++] = new MachineInstr(NOP);
-    break;
-    
-  case 206:	// stmt:   BrCond(setCCconst)
-    // setCCconst => boolean was computed with `%b = setCC type reg1 constant'
-    // If the constant is ZERO, we can use the branch-on-integer-register
-    // instructions and avoid the SUBcc instruction entirely.
-    // Otherwise this is just the same as case 5, so just fall through.
+  // 
+  // Let's check for chain rules outside the switch so that we don't have
+  // to duplicate the list of chain rule production numbers here again
+  // 
+  if (ThisIsAChainRule(ruleForNode))
     {
-    InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild();
-    assert(constNode && constNode->getNodeType() ==InstrTreeNode::NTConstNode);
-    ConstPoolVal* constVal = (ConstPoolVal*) constNode->getValue();
-    bool isValidConst;
-    
-    if ((constVal->getType()->isIntegral()
-	 || constVal->getType()->isPointerType())
-	&& GetConstantValueAsSignedInt(constVal, isValidConst) == 0
-	&& isValidConst)
-      {
-	// That constant is a zero after all...
-	// Use the left child of the setCC instruction as the first argument!
-	mvec[0] = new MachineInstr(ChooseBprInstruction(subtreeRoot));
-	mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
-		      subtreeRoot->leftChild()->leftChild()->getValue());
-	mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
-	      ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
-
-	// delay slot
-	mvec[numInstr++] = new MachineInstr(NOP);
-	
-	// false branch
-	mvec[numInstr++] = new MachineInstr(BA);
-	mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
-						(Value*) NULL);
-	mvec[numInstr-1]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp, ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1));
-
-	// delay slot
-	mvec[numInstr++] = new MachineInstr(NOP);
-	
-	break;
-      }
-    // ELSE FALL THROUGH
+      // Chain rules have a single nonterminal on the RHS.
+      // Get the rule that matches the RHS non-terminal and use that instead.
+      // 
+      assert(nts[0] && ! nts[1]
+             && "A chain rule should have only one RHS non-terminal!");
+      nextRule = burm_rule(subtreeRoot->state, nts[0]);
+      nts = burm_nts[nextRule];
+      numInstr = GetInstructionsByRule(subtreeRoot, nextRule, nts,target,mvec);
     }
-    
-  case 6:	// stmt:   BrCond(bool)
-    // bool => boolean was computed with some boolean operator (setCC,Not,...)
-    // Need to check whether the type was a FP, signed int or unsigned int,
-    // and check the branching condition in order to choose the branch to use.
-    // 
+  else
     {
-    bool isFPBranch;
-    mvec[0] = new MachineInstr(ChooseBccInstruction(subtreeRoot, isFPBranch));
-    mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
-			          subtreeRoot->leftChild()->getValue());
-    mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
-	      ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
-    
-    // delay slot
-    mvec[numInstr++] = new MachineInstr(NOP);
-    
-    // false branch
-    mvec[numInstr++] = new MachineInstr(BA);
-    mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
-					   (Value*) NULL);
-    mvec[numInstr-1]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
-	      ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1));
-    
-    // delay slot
-    mvec[numInstr++] = new MachineInstr(NOP);
-    break;
-    }
-    
-  case   8:	// stmt:   BrCond(boolreg)
-  case 208:	// stmt:   BrCond(boolconst)
-    // boolreg   => boolean is stored in an existing register.
-    // boolconst => boolean is a constant; can be loaded into a register.
-    // Just use the branch-on-integer-register instruction!
-    // 
-    mvec[0] = new MachineInstr(BRNZ);
-    mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
-			          subtreeRoot->leftChild()->getValue());
-    mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
-	      ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
-    
-    // delay slot
-    mvec[numInstr++] = new MachineInstr(NOP); // delay slot
-    
-    // false branch
-    mvec[numInstr++] = new MachineInstr(BA);
-    mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
-					   (Value*) NULL);
-    mvec[numInstr-1]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
-	      ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1));
-    
-    // delay slot
-    mvec[numInstr++] = new MachineInstr(NOP);
-    break;
-    
-  case 9:	// stmt:   Switch(reg)
-    assert(0 && "*** SWITCH instruction is not implemented yet.");
-    numInstr = 0;
-    break;
-    
-  case 10:	// reg:   VRegList(reg, reg)
-    assert(0 && "VRegList should never be the topmost non-chain rule");
-    break;
-    
-  case 21:	// reg:   Not(reg):	Implemented as reg = reg XOR-NOT 0
-    mvec[0] = new MachineInstr(XNOR);
-    mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
-			          subtreeRoot->leftChild()->getValue());
-    mvec[0]->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0);
-    mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
-				 subtreeRoot->getValue());
-    break;
-    
-  case 322:	// reg:   ToBoolTy(bool):
-  case 22:	// reg:   ToBoolTy(reg):
-    opType = subtreeRoot->leftChild()->getValue()->getType();
-    assert(opType->isIntegral() || opType == Type::BoolTy);
-    numInstr = 0;
-    forwardOperandNum = 0;
-    break;
-    
-  case 23:	// reg:   ToUByteTy(reg)
-  case 25:	// reg:   ToUShortTy(reg)
-  case 27:	// reg:   ToUIntTy(reg)
-  case 29:	// reg:   ToULongTy(reg)
-    opType = subtreeRoot->leftChild()->getValue()->getType();
-    assert(opType->isIntegral() ||
-	   opType->isPointerType() ||
-	   opType == Type::BoolTy && "Ignoring cast: illegal for other types");
-    numInstr = 0;
-    forwardOperandNum = 0;
-    break;
-    
-  case 24:	// reg:   ToSByteTy(reg)
-  case 26:	// reg:   ToShortTy(reg)
-  case 28:	// reg:   ToIntTy(reg)
-  case 30:	// reg:   ToLongTy(reg)
-    opType = subtreeRoot->leftChild()->getValue()->getType();
-    if (opType->isIntegral() || opType == Type::BoolTy)
-      {
-	numInstr = 0;
-	forwardOperandNum = 0;
-      }
-    else
-      {
-	mvec[0] =new MachineInstr(ChooseConvertToIntInstr(subtreeRoot,opType));
-	Set2OperandsFromInstr(mvec[0], subtreeRoot, target);
-      }
-    break;
-    
-  case 31:	// reg:   ToFloatTy(reg):
-  case 32:	// reg:   ToDoubleTy(reg):
-    
-    // If this instruction has a parent (a user) in the tree 
-    // and the user is translated as an FsMULd instruction,
-    // then the cast is unnecessary.  So check that first.
-    // In the future, we'll want to do the same for the FdMULq instruction,
-    // so do the check here instead of only for ToFloatTy(reg).
-    // 
-    if (subtreeRoot->parent() != NULL &&
-	((InstructionNode*) subtreeRoot->parent())->getInstruction()->getMachineInstrVec()[0]->getOpCode() == FSMULD)
-      {
-	numInstr = 0;
-	forwardOperandNum = 0;
-      }
-    else
-      {
-	opType = subtreeRoot->leftChild()->getValue()->getType();
-	MachineOpCode opCode = ChooseConvertToFloatInstr(subtreeRoot, opType);
-	if (opCode == INVALID_OPCODE)	// no conversion needed
-	  {
-	    numInstr = 0;
-	    forwardOperandNum = 0;
-	  }
-	else
-	  {
-	    mvec[0] = new MachineInstr(opCode);
-	    Set2OperandsFromInstr(mvec[0], subtreeRoot, target);
-	  }
-      }
-    break;
-    
-  case 19:	// reg:   ToArrayTy(reg):
-  case 20:	// reg:   ToPointerTy(reg):
-    numInstr = 0;
-    forwardOperandNum = 0;
-    break;
-    
-  case 233:	// reg:   Add(reg, Constant)
-    mvec[0] = CreateAddConstInstruction(subtreeRoot);
-    if (mvec[0] != NULL)
-      break;
-    // ELSE FALL THROUGH
-    
-  case 33:	// reg:   Add(reg, reg)
-    mvec[0] = new MachineInstr(ChooseAddInstruction(subtreeRoot));
-    Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
-    break;
-    
-  case 234:	// reg:   Sub(reg, Constant)
-    mvec[0] = CreateSubConstInstruction(subtreeRoot);
-    if (mvec[0] != NULL)
-      break;
-    // ELSE FALL THROUGH
-    
-  case 34:	// reg:   Sub(reg, reg)
-    mvec[0] = new MachineInstr(ChooseSubInstruction(subtreeRoot));
-    Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
-    break;
-    
-  case 135:	// reg:   Mul(todouble, todouble)
-    checkCast = true;
-    // FALL THROUGH 
-    
-  case 35:	// reg:   Mul(reg, reg)
-    mvec[0] = new MachineInstr(ChooseMulInstruction(subtreeRoot, checkCast));
-    Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
-    break;
-
-  case 335:	// reg:   Mul(todouble, todoubleConst)
-    checkCast = true;
-    // FALL THROUGH 
-   
-  case 235:	// reg:   Mul(reg, Constant)
-    mvec[0] = CreateMulConstInstruction(subtreeRoot, mvec[1]);
-    if (mvec[0] == NULL)
-      {
-	mvec[0]=new MachineInstr(ChooseMulInstruction(subtreeRoot, checkCast));
-	Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
-      }
-    else
-      if (mvec[1] != NULL)
-	++numInstr;
-    break;
-    
-  case 236:	// reg:   Div(reg, Constant)
-    mvec[0] = CreateDivConstInstruction(subtreeRoot, mvec[1]);
-    if (mvec[0] != NULL)
-      {
-	if (mvec[1] != NULL)
-	  ++numInstr;
-      }
-    else
-    // ELSE FALL THROUGH
-    
-  case 36:	// reg:   Div(reg, reg)
-    mvec[0] = new MachineInstr(ChooseDivInstruction(subtreeRoot));
-    Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
-    break;
-    
-  case  37:	// reg:   Rem(reg, reg)
-  case 237:	// reg:   Rem(reg, Constant)
-    assert(0 && "REM instruction unimplemented for the SPARC.");
-    break;
-    
-  case  38:	// reg:   And(reg, reg)
-  case 238:	// reg:   And(reg, Constant)
-    mvec[0] = new MachineInstr(AND);
-    Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
-    break;
-    
-  case 138:	// reg:   And(reg, not)
-    mvec[0] = new MachineInstr(ANDN);
-    Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
-    break;
-    
-  case  39:	// reg:   Or(reg, reg)
-  case 239:	// reg:   Or(reg, Constant)
-    mvec[0] = new MachineInstr(ORN);
-    Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
-    break;
-    
-  case 139:	// reg:   Or(reg, not)
-    mvec[0] = new MachineInstr(ORN);
-    Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
-    break;
-    
-  case  40:	// reg:   Xor(reg, reg)
-  case 240:	// reg:   Xor(reg, Constant)
-    mvec[0] = new MachineInstr(XOR);
-    Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
-    break;
-    
-  case 140:	// reg:   Xor(reg, not)
-    mvec[0] = new MachineInstr(XNOR);
-    Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
-    break;
-    
-  case 41:	// boolconst:   SetCC(reg, Constant)
-    // Check if this is an integer comparison, and
-    // there is a parent, and the parent decided to use
-    // a branch-on-integer-register instead of branch-on-condition-code.
-    // If so, the SUBcc instruction is not required.
-    // (However, we must still check for constants to be loaded from
-    // the constant pool so that such a load can be associated with
-    // this instruction.)
-    // 
-    // Otherwise this is just the same as case 42, so just fall through.
-    // 
-    if (subtreeRoot->leftChild()->getValue()->getType()->isIntegral() &&
-	subtreeRoot->parent() != NULL)
-      {
-	InstructionNode* parentNode = (InstructionNode*) subtreeRoot->parent();
-	assert(parentNode->getNodeType() == InstrTreeNode::NTInstructionNode);
-	const vector<MachineInstr*>&
-	  minstrVec = parentNode->getInstruction()->getMachineInstrVec();
-	MachineOpCode parentOpCode;
-	if (parentNode->getInstruction()->getOpcode() == Instruction::Br &&
-	    (parentOpCode = minstrVec[0]->getOpCode()) >= BRZ &&
-	    parentOpCode <= BRGEZ)
-	  {
-	    numInstr = 0;		// don't forward the operand!
-	    break;
-	  }
-      }
-    // ELSE FALL THROUGH
-    
-  case 42:	// bool:   SetCC(reg, reg):
-  {
-    // If result of the SetCC is only used for a branch, we can
-    // discard the result. otherwise, it must go into an integer register.
-    // Note that the user may or may not be in the same tree, so we have
-    // to follow SSA def-use edges here, not BURG tree edges.
-    // 
-    Instruction* result = subtreeRoot->getInstruction();
-    Value* firstUse = result->use_empty() ? 0 : *result->use_begin();
-    bool discardResult =
-      (result->use_size() == 1
-       && firstUse->isInstruction()
-       && ((Instruction*) firstUse)->getOpcode() == Instruction::Br);
-    
-    bool mustClearReg;
-    int valueToMove;
-    MachineOpCode movOpCode;
-    
-    if (subtreeRoot->leftChild()->getValue()->getType()->isIntegral() ||
-	subtreeRoot->leftChild()->getValue()->getType()->isPointerType())
-      {
-	// Integer condition: destination should be %g0 or integer register.
-	// If result must be saved but condition is not SetEQ then we need
-	// a separate instruction to compute the bool result, so discard
-	// result of SUBcc instruction anyway.
-	// 
-	mvec[0] = new MachineInstr(SUBcc);
-	Set3OperandsFromInstr(mvec[0], subtreeRoot, target, discardResult);
-	
-	// mark the 4th operand as being a CC register, and a "result"
-	mvec[0]->SetMachineOperand(3, MachineOperand::MO_CCRegister,
-				      subtreeRoot->getValue(), /*def*/ true);
-	
-	if (!discardResult) 
-	  { // recompute bool if needed, using the integer condition codes
-	    if (result->getOpcode() == Instruction::SetNE)
-	      discardResult = true;
-	    else
-	      movOpCode =
-		ChooseMovpccAfterSub(subtreeRoot, mustClearReg, valueToMove);
-	  }
-      }
-    else
-      {
-	// FP condition: dest of FCMP should be some FCCn register
-	mvec[0] = new MachineInstr(ChooseFcmpInstruction(subtreeRoot));
-	mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
-				      subtreeRoot->getValue());
-	mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
-				      subtreeRoot->leftChild()->getValue());
-	mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
-				      subtreeRoot->rightChild()->getValue());
-	
-	if (!discardResult)
-	  {// recompute bool using the FP condition codes
-	    mustClearReg = true;
-	    valueToMove = 1;
-	    movOpCode = ChooseMovFpccInstruction(subtreeRoot);
-	  }
-      }
-    
-    if (!discardResult)
-      {
-	if (mustClearReg)
-	  {// Unconditionally set register to 0
-	   int n = numInstr++;
-	   mvec[n] = new MachineInstr(SETHI);
-	   mvec[n]->SetMachineOperand(0,MachineOperand::MO_UnextendedImmed,s0);
-	   mvec[n]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
-				         subtreeRoot->getValue());
-	  }
-	
-	// Now conditionally move `valueToMove' (0 or 1) into the register
-	int n = numInstr++;
-	mvec[n] = new MachineInstr(movOpCode);
-	mvec[n]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
-				      subtreeRoot->getValue());
-	mvec[n]->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed,
-				      valueToMove);
-	mvec[n]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
-				      subtreeRoot->getValue());
-      }
-    break;
-  }    
-  
-  case 43:	// boolreg: VReg
-  case 44:	// boolreg: Constant
-    numInstr = 0;
-    break;
-
-  case 51:	// reg:   Load(reg)
-  case 52:	// reg:   Load(ptrreg)
-  case 53:	// reg:   LoadIdx(reg,reg)
-  case 54:	// reg:   LoadIdx(ptrreg,reg)
-    mvec[0] = new MachineInstr(ChooseLoadInstruction(subtreeRoot->getValue()->getType()));
-    SetOperandsForMemInstr(mvec[0], subtreeRoot, target);
-    break;
-    
-  case 55:	// reg:   GetElemPtr(reg)
-  case 56:	// reg:   GetElemPtrIdx(reg,reg)
-    if (subtreeRoot->parent() != NULL)
+      switch(ruleForNode) {
+      case 1:	// stmt:   Ret
+      case 2:	// stmt:   RetValue(reg)
+                // NOTE: Prepass of register allocation is responsible
+                //	 for moving return value to appropriate register.
+                // Mark the return-address register as a hidden virtual reg.
+                // Mark the return value   register as an implicit use.
+        {		
+        ReturnInst* returnInstr = (ReturnInst*) subtreeRoot->getInstruction();
+        assert(returnInstr->getOpcode() == Instruction::Ret);
+        
+        Instruction* returnReg = new TmpInstruction(Instruction::UserOp1,
+                                                    returnInstr, NULL);
+        returnInstr->getMachineInstrVec().addTempValue(returnReg);
+
+        if (returnInstr->getReturnValue() != NULL)
+          returnInstr->getMachineInstrVec().addImplicitUse(
+                                             returnInstr->getReturnValue());
+        
+        mvec[0] = new MachineInstr(RETURN);
+        mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
+                                      returnReg);
+        mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,s0);
+        
+        returnReg->addMachineInstruction(mvec[0]);
+        
+        mvec[numInstr++] = new MachineInstr(NOP); // delay slot
+        break;
+        }  
+        
+      case 3:	// stmt:   Store(reg,reg)
+      case 4:	// stmt:   Store(reg,ptrreg)
+        mvec[0] = new MachineInstr(
+                       ChooseStoreInstruction(
+                            subtreeRoot->leftChild()->getValue()->getType()));
+        SetOperandsForMemInstr(mvec[0], subtreeRoot, target);
+        break;
+
+      case 5:	// stmt:   BrUncond
+        mvec[0] = new MachineInstr(BA);
+        mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
+                                      (Value*)NULL);
+        mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
+              ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
+        
+        // delay slot
+        mvec[numInstr++] = new MachineInstr(NOP);
+        break;
+
+      case 206:	// stmt:   BrCond(setCCconst)
+        // setCCconst => boolean was computed with `%b = setCC type reg1 const'
+        // If the constant is ZERO, we can use the branch-on-integer-register
+        // instructions and avoid the SUBcc instruction entirely.
+        // Otherwise this is just the same as case 5, so just fall through.
+        {
+        InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild();
+        assert(constNode &&
+               constNode->getNodeType() ==InstrTreeNode::NTConstNode);
+        ConstPoolVal* constVal = (ConstPoolVal*) constNode->getValue();
+        bool isValidConst;
+
+        if ((constVal->getType()->isIntegral()
+             || constVal->getType()->isPointerType())
+            && GetConstantValueAsSignedInt(constVal, isValidConst) == 0
+            && isValidConst)
+          {
+            // That constant is a zero after all...
+            // Use the left child of setCC as the first argument!
+            mvec[0] = new MachineInstr(ChooseBprInstruction(subtreeRoot));
+            mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
+                          subtreeRoot->leftChild()->leftChild()->getValue());
+            mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
+              ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
+
+            // delay slot
+            mvec[numInstr++] = new MachineInstr(NOP);
+
+            // false branch
+            int n = numInstr++; 
+            mvec[n] = new MachineInstr(BA);
+            mvec[n]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
+                                          (Value*) NULL);
+            mvec[n]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
+               ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1));
+            
+            // delay slot
+            mvec[numInstr++] = new MachineInstr(NOP);
+            
+            break;
+          }
+        // ELSE FALL THROUGH
+        }
+
+      case 6:	// stmt:   BrCond(bool)
+        // bool => boolean was computed with some boolean operator
+        // (SetCC, Not, ...).  We need to check whether the type was a FP,
+        // signed int or unsigned int, and check the branching condition in
+        // order to choose the branch to use.
+        // 
+        {
+        bool isFPBranch;
+        mvec[0] = new MachineInstr(ChooseBccInstruction(subtreeRoot,
+                                                        isFPBranch));
+        mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
+                                      subtreeRoot->leftChild()->getValue());
+        mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
+              ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
+
+        // delay slot
+        mvec[numInstr++] = new MachineInstr(NOP);
+
+        // false branch
+        int n = numInstr++;
+        mvec[n] = new MachineInstr(BA);
+        mvec[n]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
+                                      (Value*) NULL);
+        mvec[n]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
+              ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1));
+        
+        // delay slot
+        mvec[numInstr++] = new MachineInstr(NOP);
+        break;
+        }
+        
+      case 208:	// stmt:   BrCond(boolconst)
+        {
+        // boolconst => boolean is a constant; use BA to first or second label
+        ConstPoolVal* constVal =
+          subtreeRoot->leftChild()->getValue()->castConstantAsserting();
+        unsigned dest = ((ConstPoolBool*) constVal)->getValue()? 0 : 1;
+        
+        mvec[0] = new MachineInstr(BA);
+        mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
+                                      (Value*) NULL);
+        mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
+          ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(dest));
+        
+        // delay slot
+        mvec[numInstr++] = new MachineInstr(NOP);
+        break;
+        }
+        
+      case   8:	// stmt:   BrCond(boolreg)
+        // boolreg   => boolean is stored in an existing register.
+        // Just use the branch-on-integer-register instruction!
+        // 
+        {
+        mvec[0] = new MachineInstr(BRNZ);
+        mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
+                                      subtreeRoot->leftChild()->getValue());
+        mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
+              ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
+
+        // delay slot
+        mvec[numInstr++] = new MachineInstr(NOP); // delay slot
+
+        // false branch
+        int n = numInstr++;
+        mvec[n] = new MachineInstr(BA);
+        mvec[n]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
+                                      (Value*) NULL);
+        mvec[n]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
+              ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1));
+        
+        // delay slot
+        mvec[numInstr++] = new MachineInstr(NOP);
+        break;
+        }  
+      
+      case 9:	// stmt:   Switch(reg)
+        assert(0 && "*** SWITCH instruction is not implemented yet.");
+        numInstr = 0;
+        break;
+
+      case 10:	// reg:   VRegList(reg, reg)
+        assert(0 && "VRegList should never be the topmost non-chain rule");
+        break;
+
+      case 21:	// reg:   Not(reg):	Implemented as reg = reg XOR-NOT 0
+        mvec[0] = new MachineInstr(XNOR);
+        mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
+                                      subtreeRoot->leftChild()->getValue());
+        mvec[0]->SetMachineOperand(1, target.getRegInfo().getZeroRegNum());
+        mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
+                                     subtreeRoot->getValue());
+        break;
+
+      case 322:	// reg:   ToBoolTy(bool):
+      case 22:	// reg:   ToBoolTy(reg):
+        opType = subtreeRoot->leftChild()->getValue()->getType();
+        assert(opType->isIntegral() || opType == Type::BoolTy);
+        numInstr = 0;
+        forwardOperandNum = 0;
+        break;
+
+      case 23:	// reg:   ToUByteTy(reg)
+      case 25:	// reg:   ToUShortTy(reg)
+      case 27:	// reg:   ToUIntTy(reg)
+      case 29:	// reg:   ToULongTy(reg)
+        opType = subtreeRoot->leftChild()->getValue()->getType();
+        assert(opType->isIntegral() ||
+               opType->isPointerType() ||
+               opType == Type::BoolTy && "Cast is illegal for other types");
+        numInstr = 0;
+        forwardOperandNum = 0;
+        break;
+        
+      case 24:	// reg:   ToSByteTy(reg)
+      case 26:	// reg:   ToShortTy(reg)
+      case 28:	// reg:   ToIntTy(reg)
+      case 30:	// reg:   ToLongTy(reg)
+        opType = subtreeRoot->leftChild()->getValue()->getType();
+        if (opType->isIntegral() || opType == Type::BoolTy)
+          {
+            numInstr = 0;
+            forwardOperandNum = 0;
+          }
+        else
+          {
+            mvec[0] = new MachineInstr(ChooseConvertToIntInstr(subtreeRoot,
+                                                              opType));
+            Set2OperandsFromInstr(mvec[0], subtreeRoot, target);
+          }
+        break;
+        
+      case  31:	// reg:   ToFloatTy(reg):
+      case  32:	// reg:   ToDoubleTy(reg):
+      case 232:	// reg:   ToDoubleTy(Constant):
+        
+        // If this instruction has a parent (a user) in the tree 
+        // and the user is translated as an FsMULd instruction,
+        // then the cast is unnecessary.  So check that first.
+        // In the future, we'll want to do the same for the FdMULq instruction,
+        // so do the check here instead of only for ToFloatTy(reg).
+        // 
+        if (subtreeRoot->parent() != NULL &&
+            ((InstructionNode*) subtreeRoot->parent())->getInstruction()->getMachineInstrVec()[0]->getOpCode() == FSMULD)
+          {
+            numInstr = 0;
+            forwardOperandNum = 0;
+          }
+        else
+          {
+            opType = subtreeRoot->leftChild()->getValue()->getType();
+            MachineOpCode opCode=ChooseConvertToFloatInstr(subtreeRoot,opType);
+            if (opCode == INVALID_OPCODE)	// no conversion needed
+              {
+                numInstr = 0;
+                forwardOperandNum = 0;
+              }
+            else
+              {
+                mvec[0] = new MachineInstr(opCode);
+                Set2OperandsFromInstr(mvec[0], subtreeRoot, target);
+              }
+          }
+        break;
+
+      case 19:	// reg:   ToArrayTy(reg):
+      case 20:	// reg:   ToPointerTy(reg):
+        numInstr = 0;
+        forwardOperandNum = 0;
+        break;
+
+      case 233:	// reg:   Add(reg, Constant)
+        mvec[0] = CreateAddConstInstruction(subtreeRoot);
+        if (mvec[0] != NULL)
+          break;
+        // ELSE FALL THROUGH
+
+      case 33:	// reg:   Add(reg, reg)
+        mvec[0] = new MachineInstr(ChooseAddInstruction(subtreeRoot));
+        Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
+        break;
+
+      case 234:	// reg:   Sub(reg, Constant)
+        mvec[0] = CreateSubConstInstruction(subtreeRoot);
+        if (mvec[0] != NULL)
+          break;
+        // ELSE FALL THROUGH
+
+      case 34:	// reg:   Sub(reg, reg)
+        mvec[0] = new MachineInstr(ChooseSubInstruction(subtreeRoot));
+        Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
+        break;
+
+      case 135:	// reg:   Mul(todouble, todouble)
+        checkCast = true;
+        // FALL THROUGH 
+
+      case 35:	// reg:   Mul(reg, reg)
+        mvec[0] =new MachineInstr(ChooseMulInstruction(subtreeRoot,checkCast));
+        Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
+        break;
+
+      case 335:	// reg:   Mul(todouble, todoubleConst)
+        checkCast = true;
+        // FALL THROUGH 
+
+      case 235:	// reg:   Mul(reg, Constant)
+        mvec[0] = CreateMulConstInstruction(target, subtreeRoot, mvec[1]);
+        if (mvec[0] == NULL)
+          {
+            mvec[0] = new MachineInstr(ChooseMulInstruction(subtreeRoot,
+                                                            checkCast));
+            Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
+          }
+        else
+          if (mvec[1] != NULL)
+            ++numInstr;
+        break;
+
+      case 236:	// reg:   Div(reg, Constant)
+        mvec[0] = CreateDivConstInstruction(target, subtreeRoot, mvec[1]);
+        if (mvec[0] != NULL)
+          {
+            if (mvec[1] != NULL)
+              ++numInstr;
+          }
+        else
+        // ELSE FALL THROUGH
+
+      case 36:	// reg:   Div(reg, reg)
+        mvec[0] = new MachineInstr(ChooseDivInstruction(target, subtreeRoot));
+        Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
+        break;
+
+      case  37:	// reg:   Rem(reg, reg)
+      case 237:	// reg:   Rem(reg, Constant)
+        assert(0 && "REM instruction unimplemented for the SPARC.");
+        break;
+
+      case  38:	// reg:   And(reg, reg)
+      case 238:	// reg:   And(reg, Constant)
+        mvec[0] = new MachineInstr(AND);
+        Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
+        break;
+
+      case 138:	// reg:   And(reg, not)
+        mvec[0] = new MachineInstr(ANDN);
+        Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
+        break;
+
+      case  39:	// reg:   Or(reg, reg)
+      case 239:	// reg:   Or(reg, Constant)
+        mvec[0] = new MachineInstr(ORN);
+        Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
+        break;
+
+      case 139:	// reg:   Or(reg, not)
+        mvec[0] = new MachineInstr(ORN);
+        Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
+        break;
+
+      case  40:	// reg:   Xor(reg, reg)
+      case 240:	// reg:   Xor(reg, Constant)
+        mvec[0] = new MachineInstr(XOR);
+        Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
+        break;
+
+      case 140:	// reg:   Xor(reg, not)
+        mvec[0] = new MachineInstr(XNOR);
+        Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
+        break;
+
+      case 41:	// boolconst:   SetCC(reg, Constant)
+        // Check if this is an integer comparison, and
+        // there is a parent, and the parent decided to use
+        // a branch-on-integer-register instead of branch-on-condition-code.
+        // If so, the SUBcc instruction is not required.
+        // (However, we must still check for constants to be loaded from
+        // the constant pool so that such a load can be associated with
+        // this instruction.)
+        // 
+        // Otherwise this is just the same as case 42, so just fall through.
+        // 
+        if (subtreeRoot->leftChild()->getValue()->getType()->isIntegral() &&
+            subtreeRoot->parent() != NULL)
+          {
+            InstructionNode* parent = (InstructionNode*) subtreeRoot->parent();
+            assert(parent->getNodeType() == InstrTreeNode::NTInstructionNode);
+            const vector<MachineInstr*>&
+              minstrVec = parent->getInstruction()->getMachineInstrVec();
+            MachineOpCode parentOpCode;
+            if (parent->getInstruction()->getOpcode() == Instruction::Br &&
+                (parentOpCode = minstrVec[0]->getOpCode()) >= BRZ &&
+                parentOpCode <= BRGEZ)
+              {
+                numInstr = 0;		// don't forward the operand!
+                break;
+              }
+          }
+        // ELSE FALL THROUGH
+
+      case 42:	// bool:   SetCC(reg, reg):
       {
-	// Check if the parent was an array access.
-	// If so, we still need to generate this instruction.
-	MemAccessInst* memInst =(MemAccessInst*) subtreeRoot->getInstruction();
-	const PointerType* ptrType =
-	  (const PointerType*) memInst->getPtrOperand()->getType();
-	if (! ptrType->getValueType()->isArrayType())
-	  {// we don't need a separate instr
-	    numInstr = 0;		// don't forward operand!
-	    break;
-	  }
+        // If result of the SetCC is only used for a single branch, we can
+        // discard the result.  Otherwise, the boolean value must go into
+        // an integer register.
+        // 
+        bool keepBoolVal = (subtreeRoot->parent() == NULL ||
+                            ((InstructionNode*) subtreeRoot->parent())
+                            ->getInstruction()->getOpcode() !=Instruction::Br);
+        bool subValIsBoolVal =
+          subtreeRoot->getInstruction()->getOpcode() == Instruction::SetNE;
+        bool keepSubVal = keepBoolVal && subValIsBoolVal;
+        bool computeBoolVal = keepBoolVal && ! subValIsBoolVal;
+        
+        bool mustClearReg;
+        int valueToMove;
+        MachineOpCode movOpCode;
+        
+        if (subtreeRoot->leftChild()->getValue()->getType()->isIntegral() ||
+            subtreeRoot->leftChild()->getValue()->getType()->isPointerType())
+          {
+            // Integer condition: dest. should be %g0 or an integer register.
+            // If result must be saved but condition is not SetEQ then we need
+            // a separate instruction to compute the bool result, so discard
+            // result of SUBcc instruction anyway.
+            // 
+            mvec[0] = new MachineInstr(SUBcc);
+            Set3OperandsFromInstr(mvec[0], subtreeRoot, target, ! keepSubVal);
+            
+            // mark the 4th operand as being a CC register, and a "result"
+            mvec[0]->SetMachineOperand(3, MachineOperand::MO_CCRegister,
+                                          subtreeRoot->getValue(),/*def*/true);
+            
+            if (computeBoolVal)
+              { // recompute bool using the integer condition codes
+                movOpCode =
+                  ChooseMovpccAfterSub(subtreeRoot,mustClearReg,valueToMove);
+              }
+          }
+        else
+          {
+            // FP condition: dest of FCMP should be some FCCn register
+            mvec[0] = new MachineInstr(ChooseFcmpInstruction(subtreeRoot));
+            mvec[0]->SetMachineOperand(0,MachineOperand::MO_CCRegister,
+                                         subtreeRoot->getValue());
+            mvec[0]->SetMachineOperand(1,MachineOperand::MO_VirtualRegister,
+                                         subtreeRoot->leftChild()->getValue());
+            mvec[0]->SetMachineOperand(2,MachineOperand::MO_VirtualRegister,
+                                        subtreeRoot->rightChild()->getValue());
+            
+            if (computeBoolVal)
+              {// recompute bool using the FP condition codes
+                mustClearReg = true;
+                valueToMove = 1;
+                movOpCode = ChooseMovFpccInstruction(subtreeRoot);
+              }
+          }
+        
+        if (computeBoolVal)
+          {
+            if (mustClearReg)
+              {// Unconditionally set register to 0
+               int n = numInstr++;
+               mvec[n] = new MachineInstr(SETHI);
+               mvec[n]->SetMachineOperand(0,MachineOperand::MO_UnextendedImmed,
+                                            s0);
+               mvec[n]->SetMachineOperand(1,MachineOperand::MO_VirtualRegister,
+                                            subtreeRoot->getValue());
+              }
+            
+            // Now conditionally move `valueToMove' (0 or 1) into the register
+            int n = numInstr++;
+            mvec[n] = new MachineInstr(movOpCode);
+            mvec[n]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
+                                          subtreeRoot->getValue());
+            mvec[n]->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed,
+                                          valueToMove);
+            mvec[n]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
+                                          subtreeRoot->getValue());
+          }
+        break;
+      }    
+
+      case 43:	// boolreg: VReg
+      case 44:	// boolreg: Constant
+        numInstr = 0;
+        break;
+
+      case 51:	// reg:   Load(reg)
+      case 52:	// reg:   Load(ptrreg)
+      case 53:	// reg:   LoadIdx(reg,reg)
+      case 54:	// reg:   LoadIdx(ptrreg,reg)
+        mvec[0] = new MachineInstr(ChooseLoadInstruction(
+                                     subtreeRoot->getValue()->getType()));
+        SetOperandsForMemInstr(mvec[0], subtreeRoot, target);
+        break;
+
+      case 55:	// reg:   GetElemPtr(reg)
+      case 56:	// reg:   GetElemPtrIdx(reg,reg)
+        if (subtreeRoot->parent() != NULL)
+          {
+            // Check if the parent was an array access.
+            // If so, we still need to generate this instruction.
+            MemAccessInst* memInst = (MemAccessInst*)
+              subtreeRoot->getInstruction();
+            const PointerType* ptrType =
+              (const PointerType*) memInst->getPtrOperand()->getType();
+            if (! ptrType->getValueType()->isArrayType())
+              {// we don't need a separate instr
+                numInstr = 0;		// don't forward operand!
+                break;
+              }
+          }
+        // else in all other cases we need to a separate ADD instruction
+        mvec[0] = new MachineInstr(ADD);
+        SetOperandsForMemInstr(mvec[0], subtreeRoot, target);
+        break;
+
+      case 57:	// reg:   Alloca: Implement as 2 instructions:
+                    //	sub %sp, tmp -> %sp
+        {		//	add %sp, 0   -> result
+        Instruction* instr = subtreeRoot->getInstruction();
+        const PointerType* instrType = (const PointerType*) instr->getType();
+        assert(instrType->isPointerType());
+        int tsize = (int)
+          target.findOptimalStorageSize(instrType->getValueType());
+        assert(tsize != 0 && "Just to check when this can happen");
+        
+        // Create a temporary Value to hold the constant type-size
+        ConstPoolSInt* valueForTSize = ConstPoolSInt::get(Type::IntTy, tsize);
+
+        // Instruction 1: sub %sp, tsize -> %sp
+        // tsize is always constant, but it may have to be put into a
+        // register if it doesn't fit in the immediate field.
+        // 
+        mvec[0] = new MachineInstr(SUB);
+        mvec[0]->SetMachineOperand(0, /*regNum %sp=o6=r[14]*/(unsigned int)14);
+        mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
+                                      valueForTSize);
+        mvec[0]->SetMachineOperand(2, /*regNum %sp=o6=r[14]*/(unsigned int)14);
+
+        // Instruction 2: add %sp, 0 -> result
+        numInstr++;
+        mvec[1] = new MachineInstr(ADD);
+        mvec[1]->SetMachineOperand(0, /*regNum %sp=o6=r[14]*/(unsigned int)14);
+        mvec[1]->SetMachineOperand(1, target.getRegInfo().getZeroRegNum());
+        mvec[1]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
+                                      instr);
+        break;
+        }
+        
+      case 58:	// reg:   Alloca(reg): Implement as 3 instructions:
+                //	mul num, typeSz -> tmp
+                //	sub %sp, tmp    -> %sp
+        {	//	add %sp, 0      -> result
+        Instruction* instr = subtreeRoot->getInstruction();
+        const PointerType* instrType = (const PointerType*) instr->getType();
+        assert(instrType->isPointerType() &&
+               instrType->getValueType()->isArrayType());
+        const Type* eltType =
+          ((ArrayType*) instrType->getValueType())->getElementType();
+        int tsize = (int) target.findOptimalStorageSize(eltType);
+
+        assert(tsize != 0 && "Just to check when this can happen");
+        // if (tsize == 0)
+          // {
+            // numInstr = 0;
+            // break;
+          // }
+        //else go on to create the instructions needed...
+
+        // Create a temporary Value to hold the constant type-size
+        ConstPoolSInt* valueForTSize = ConstPoolSInt::get(Type::IntTy, tsize);
+
+        // Create a temporary value to hold `tmp'
+        Instruction* tmpInstr = new TmpInstruction(Instruction::UserOp1,
+                                          subtreeRoot->leftChild()->getValue(),
+                                          NULL /*could insert tsize here*/);
+        subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(tmpInstr);
+        
+        // Instruction 1: mul numElements, typeSize -> tmp
+        mvec[0] = new MachineInstr(MULX);
+        mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
+                                    subtreeRoot->leftChild()->getValue());
+        mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
+                                      valueForTSize);
+        mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
+                                      tmpInstr);
+
+        tmpInstr->addMachineInstruction(mvec[0]);
+
+        // Instruction 2: sub %sp, tmp -> %sp
+        numInstr++;
+        mvec[1] = new MachineInstr(SUB);
+        mvec[1]->SetMachineOperand(0, /*regNum %sp=o6=r[14]*/(unsigned int)14);
+        mvec[1]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
+                                      tmpInstr);
+        mvec[1]->SetMachineOperand(2, /*regNum %sp=o6=r[14]*/(unsigned int)14);
+        
+        // Instruction 3: add %sp, 0 -> result
+        numInstr++;
+        mvec[2] = new MachineInstr(ADD);
+        mvec[2]->SetMachineOperand(0, /*regNum %sp=o6=r[14]*/(unsigned int)14);
+        mvec[2]->SetMachineOperand(1, target.getRegInfo().getZeroRegNum());
+        mvec[2]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
+                                      instr);
+        break;
+        }
+
+      case 61:	// reg:   Call
+                // Generate a call-indirect (i.e., JMPL) for now to expose
+                // the potential need for registers.  If an absolute address
+                // is available, replace this with a CALL instruction.
+                // Mark both the indirection register and the return-address
+        	// register as hidden virtual registers.
+                // Also, mark the operands of the Call as implicit operands
+                // of the machine instruction.
+        {
+        CallInst* callInstr = (CallInst*) subtreeRoot->getInstruction();
+        Method* callee = callInstr->getCalledMethod();
+        assert(callInstr->getOpcode() == Instruction::Call); 
+        
+        Instruction* jmpAddrReg = new TmpInstruction(Instruction::UserOp1,
+                                                     callee, NULL);
+        Instruction* retAddrReg = new TmpInstruction(Instruction::UserOp1,
+                                                     callInstr, NULL);
+
+        // Note temporary values and implicit uses in mvec
+        callInstr->getMachineInstrVec().addTempValue(jmpAddrReg);
+        callInstr->getMachineInstrVec().addTempValue(retAddrReg);
+        for (unsigned i=0, N=callInstr->getNumOperands(); i < N; ++i)
+          if (callInstr->getOperand(i) != callee)
+            callInstr->getMachineInstrVec().addImplicitUse(
+                                                   callInstr->getOperand(i));
+        
+        // Generate the machine instruction and its operands
+        mvec[0] = new MachineInstr(JMPL);
+        mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
+                                      jmpAddrReg);
+        mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,
+                                      (int64_t) 0);
+        mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
+                                      retAddrReg);
+        
+        // NOTE: jmpAddrReg will be loaded by a different instruction generated
+        //   by the final code generator, so we just mark the CALL instruction
+        //   as computing that value.
+        //   The retAddrReg is actually computed by the CALL instruction.
+        //
+        jmpAddrReg->addMachineInstruction(mvec[0]);
+        retAddrReg->addMachineInstruction(mvec[0]);
+        
+        mvec[numInstr++] = new MachineInstr(NOP); // delay slot
+        break;
+        }
+
+      case 62:	// reg:   Shl(reg, reg)
+        opType = subtreeRoot->leftChild()->getValue()->getType();
+        assert(opType->isIntegral()
+               || opType == Type::BoolTy
+               || opType->isPointerType()&& "Shl unsupported for other types");
+        mvec[0] = new MachineInstr((opType == Type::LongTy)? SLLX : SLL);
+        Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
+        break;
+
+      case 63:	// reg:   Shr(reg, reg)
+        opType = subtreeRoot->leftChild()->getValue()->getType();
+        assert(opType->isIntegral()
+               || opType == Type::BoolTy
+               || opType->isPointerType() &&"Shr unsupported for other types");
+        mvec[0] = new MachineInstr((opType->isSigned()
+                                    ? ((opType == Type::LongTy)? SRAX : SRA)
+                                    : ((opType == Type::LongTy)? SRLX : SRL)));
+        Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
+        break;
+
+      case 64:	// reg:   Phi(reg,reg)
+      {		// This instruction has variable #operands, so resultPos is 0.
+        Instruction* phi = subtreeRoot->getInstruction();
+        mvec[0] = new MachineInstr(PHI, 1 + phi->getNumOperands());
+        mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
+                                      subtreeRoot->getValue());
+        for (unsigned i=0, N=phi->getNumOperands(); i < N; i++)
+          mvec[0]->SetMachineOperand(i+1, MachineOperand::MO_VirtualRegister,
+                                          phi->getOperand(i));
+        break;
+      }  
+      case 71:	// reg:     VReg
+      case 72:	// reg:     Constant
+        numInstr = 0;			// don't forward the value
+        break;
+
+      default:
+        assert(0 && "Unrecognized BURG rule");
+        numInstr = 0;
+        break;
       }
-    // else in all other cases we need to a separate ADD instruction
-    mvec[0] = new MachineInstr(ADD);
-    SetOperandsForMemInstr(mvec[0], subtreeRoot, target);
-    break;
-    
-  case 57:	// reg:   Alloca: Implement as 2 instructions:
-    		//	sub %sp, tmp -> %sp
-    {		//	add %sp, 0   -> result
-    Instruction* instr = subtreeRoot->getInstruction();
-    const PointerType* instrType = (const PointerType*) instr->getType();
-    assert(instrType->isPointerType());
-    int tsize = (int) target.findOptimalStorageSize(instrType->getValueType());
-    assert(tsize != 0 && "Just to check when this can happen");
-    // if (tsize == 0)
-    //   {
-	// numInstr = 0;
-	// break;
-    // }
-    //else go on to create the instructions needed...
-    
-    // Create a temporary Value to hold the constant type-size
-    ConstPoolSInt* valueForTSize = ConstPoolSInt::get(Type::IntTy, tsize);
-    
-    // Instruction 1: sub %sp, tsize -> %sp
-    // tsize is always constant, but it may have to be put into a
-    // register if it doesn't fit in the immediate field.
-    // 
-    mvec[0] = new MachineInstr(SUB);
-    mvec[0]->SetMachineOperand(0, /*regNum %sp = o6 = r[14]*/(unsigned int)14);
-    mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, valueForTSize);
-    mvec[0]->SetMachineOperand(2, /*regNum %sp = o6 = r[14]*/(unsigned int)14);
-    
-    // Instruction 2: add %sp, 0 -> result
-    numInstr++;
-    mvec[1] = new MachineInstr(ADD);
-    mvec[1]->SetMachineOperand(0, /*regNum %sp = o6 = r[14]*/(unsigned int)14);
-    mvec[1]->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0);
-    mvec[1]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, instr);
-    break;
-    }
-  
-  case 58:	// reg:   Alloca(reg): Implement as 3 instructions:
-    		//	mul num, typeSz -> tmp
-    		//	sub %sp, tmp    -> %sp
-    {		//	add %sp, 0      -> result
-    Instruction* instr = subtreeRoot->getInstruction();
-    const PointerType* instrType = (const PointerType*) instr->getType();
-    assert(instrType->isPointerType() &&
-	   instrType->getValueType()->isArrayType());
-    const Type* eltType =
-      ((ArrayType*) instrType->getValueType())->getElementType();
-    int tsize = (int) target.findOptimalStorageSize(eltType);
-    
-    assert(tsize != 0 && "Just to check when this can happen");
-    // if (tsize == 0)
-      // {
-	// numInstr = 0;
-	// break;
-      // }
-    //else go on to create the instructions needed...
-
-    // Create a temporary Value to hold the constant type-size
-    ConstPoolSInt* valueForTSize = ConstPoolSInt::get(Type::IntTy, tsize);
-    
-    // Create a temporary value to hold `tmp'
-    Instruction* tmpInstr = new TmpInstruction(Instruction::UserOp1,
-					  subtreeRoot->leftChild()->getValue(),
-					  NULL /*could insert tsize here*/);
-    subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(tmpInstr);
-
-    // Instruction 1: mul numElements, typeSize -> tmp
-    mvec[0] = new MachineInstr(MULX);
-    mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
-				subtreeRoot->leftChild()->getValue());
-    mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, valueForTSize);
-    mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,tmpInstr);
-
-    tmpInstr->addMachineInstruction(mvec[0]);
-    
-    // Instruction 2: sub %sp, tmp -> %sp
-    numInstr++;
-    mvec[1] = new MachineInstr(SUB);
-    mvec[1]->SetMachineOperand(0, /*regNum %sp = o6 = r[14]*/(unsigned int)14);
-    mvec[1]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,tmpInstr);
-    mvec[1]->SetMachineOperand(2, /*regNum %sp = o6 = r[14]*/(unsigned int)14);
-    
-    // Instruction 3: add %sp, 0 -> result
-    numInstr++;
-    mvec[2] = new MachineInstr(ADD);
-    mvec[2]->SetMachineOperand(0, /*regNum %sp = o6 = r[14]*/(unsigned int)14);
-    mvec[2]->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0);
-    mvec[2]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, instr);
-    break;
     }
-    
-  case 61:	// reg:   Call
-		// Generate a call-indirect (i.e., JMPL) for now to expose
-		// the potential need for registers.  If an absolute address
-		// is available, replace this with a CALL instruction.
-		// Mark both the indirection register and the return-address
-    {		// register as hidden virtual registers.
-      
-    Instruction* jmpAddrReg = new TmpInstruction(Instruction::UserOp1,
-	((CallInst*) subtreeRoot->getInstruction())->getCalledMethod(), NULL);
-    Instruction* retAddrReg = new TmpInstruction(Instruction::UserOp1,
-					     subtreeRoot->getValue(), NULL);
-    subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(jmpAddrReg);
-    subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(retAddrReg);
-    
-    mvec[0] = new MachineInstr(JMPL);
-    mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, jmpAddrReg);
-    mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,
-			          (int64_t) 0);
-    mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, retAddrReg);
-
-    // NOTE: jmpAddrReg will be loaded by a different instruction generated
-    //	     by the final code generator, so we just mark the CALL instruction
-    //	     as computing that value.
-    //	     The retAddrReg is actually computed by the CALL instruction.
-    //
-    jmpAddrReg->addMachineInstruction(mvec[0]);
-    retAddrReg->addMachineInstruction(mvec[0]);
-    
-    mvec[numInstr++] = new MachineInstr(NOP); // delay slot
-    break;
-    }
-    
-  case 62:	// reg:   Shl(reg, reg)
-    opType = subtreeRoot->leftChild()->getValue()->getType();
-    assert(opType->isIntegral()
-	   || opType == Type::BoolTy
-	   || opType->isPointerType() && "Shl unsupported for other types"); 
-    mvec[0] = new MachineInstr((opType == Type::LongTy)? SLLX : SLL);
-    Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
-    break;
-    
-  case 63:	// reg:   Shr(reg, reg)
-    opType = subtreeRoot->leftChild()->getValue()->getType();
-    assert(opType->isIntegral()
-	   || opType == Type::BoolTy
-	   || opType->isPointerType() && "Shr unsupported for other types"); 
-    mvec[0] = new MachineInstr((opType->isSigned()
-				? ((opType == Type::LongTy)? SRAX : SRA)
-				: ((opType == Type::LongTy)? SRLX : SRL)));
-    Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
-    break;
-    
-  case 64:	// reg:   Phi(reg,reg)
-  {		// This instruction has variable #operands, so resultPos is 0.
-    Instruction* phi = subtreeRoot->getInstruction();
-    mvec[0] = new MachineInstr(PHI, 1 + phi->getNumOperands());
-    mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
-			          subtreeRoot->getValue());
-    for (unsigned i=0, N=phi->getNumOperands(); i < N; i++)
-      mvec[0]->SetMachineOperand(i+1, MachineOperand::MO_VirtualRegister,
-				      phi->getOperand(i));
-    break;
-  }  
-  case 71:	// reg:     VReg
-  case 72:	// reg:     Constant
-    numInstr = 0;			// don't forward the value
-    break;
-
-  case 111:	// stmt:  reg
-  case 112:	// stmt:  boolconst
-  case 113:	// stmt:  bool
-  case 121:
-  case 122:
-  case 123:
-  case 124:
-  case 125:
-  case 126:
-  case 127:
-  case 128:
-  case 129:
-  case 130:
-  case 131:
-  case 132:
-  case 133:
-  case 153:
-  case 155:
-  case 221:
-  case 222:
-  case 232:
-  case 241:
-  case 242:
-  case 243:
-  case 244:
-    // 
-    // These are all chain rules, which have a single nonterminal on the RHS.
-    // Get the rule that matches the RHS non-terminal and use that instead.
-    // 
-    assert(ThisIsAChainRule(ruleForNode));
-    assert(nts[0] && ! nts[1]
-	   && "A chain rule should have only one RHS non-terminal!");
-    nextRule = burm_rule(subtreeRoot->state, nts[0]);
-    nts = burm_nts[nextRule];
-    numInstr = GetInstructionsByRule(subtreeRoot, nextRule, nts,target,mvec);
-    break;
-    
-  default:
-    assert(0 && "Unrecognized BURG rule");
-    numInstr = 0;
-    break;
-  }
   
   if (forwardOperandNum >= 0)
     { // We did not generate a machine instruction but need to use operand.
@@ -2019,17 +2097,18 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
       // If not, insert a copy instruction which should get coalesced away
       // by register allocation.
       if (subtreeRoot->parent() != NULL)
-	ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum);
+        ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum);
       else
-	{
-	  int n = numInstr++;
-	  mvec[n] = new MachineInstr(ADD);
-	  mvec[n]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
-		subtreeRoot->getInstruction()->getOperand(forwardOperandNum));
-	  mvec[n]->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0);
-	  mvec[n]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
-				        subtreeRoot->getInstruction());
-	}
+        {
+          MachineInstr *minstr1 = NULL, *minstr2 = NULL;
+          minstr1 = CreateCopyInstructionsByType(target,
+                subtreeRoot->getInstruction()->getOperand(forwardOperandNum),
+                subtreeRoot->getInstruction(), minstr2);
+          assert(minstr1);
+          mvec[numInstr++] = minstr1;
+          if (minstr2 != NULL)
+            mvec[numInstr++] = minstr2;
+        }
     }
   
   if (! ThisIsAChainRule(ruleForNode))