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authorJim Grosbach <grosbach@apple.com>2011-07-20 18:20:31 +0000
committerJim Grosbach <grosbach@apple.com>2011-07-20 18:20:31 +0000
commitab40f4b737b0a87c4048a9ad2f0c02be735e3770 (patch)
tree5acd32e18f438a76dcaf72589d2198d7f799ce18 /lib/Target
parent0381c21d2ddc182aebfef25c6500d781ddb428fe (diff)
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ARM assembly parsing of MUL instruction.
Correctly handle 's' bit and predication suffices. Add parsing and encoding tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/ARM/AsmParser/ARMAsmParser.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 0cf9a4a..89501dc 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -1977,7 +1977,8 @@ StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic,
// First, split out any predication code. Ignore mnemonics we know aren't
// predicated but do have a carry-set and so weren't caught above.
- if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs") {
+ if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
+ Mnemonic != "muls") {
unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
.Case("eq", ARMCC::EQ)
.Case("ne", ARMCC::NE)