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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-08 08:55:49 -0700 |
|---|---|---|
| committer | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-09 15:04:38 -0700 |
| commit | 4c5e43da7792f75567b693105cc53e3f1992ad98 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/AArch64 | |
| parent | c75239e6119d0f9a74c57099d91cbc9bde56bf33 (diff) | |
| download | external_llvm-4c5e43da7792f75567b693105cc53e3f1992ad98.zip external_llvm-4c5e43da7792f75567b693105cc53e3f1992ad98.tar.gz external_llvm-4c5e43da7792f75567b693105cc53e3f1992ad98.tar.bz2 | |
Update aosp/master llvm for rebase to r233350
Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
Diffstat (limited to 'test/CodeGen/AArch64')
268 files changed, 5770 insertions, 4991 deletions
diff --git a/test/CodeGen/AArch64/128bit_load_store.ll b/test/CodeGen/AArch64/128bit_load_store.ll index a6f0776..94fd386 100644 --- a/test/CodeGen/AArch64/128bit_load_store.ll +++ b/test/CodeGen/AArch64/128bit_load_store.ll @@ -12,7 +12,7 @@ define fp128 @test_load_f128(fp128* readonly %ptr) #2 { ; CHECK-LABEL: test_load_f128 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}] entry: - %0 = load fp128* %ptr, align 16 + %0 = load fp128, fp128* %ptr, align 16 ret fp128 %0 } @@ -33,7 +33,7 @@ define i128 @test_vldrq_p128(i128* readonly %ptr) #2 { entry: %0 = bitcast i128* %ptr to fp128* - %1 = load fp128* %0, align 16 + %1 = load fp128, fp128* %0, align 16 %2 = bitcast fp128 %1 to i128 ret i128 %2 } @@ -44,8 +44,8 @@ define void @test_ld_st_p128(i128* nocapture %ptr) #0 { ; CHECK-NEXT: str {{q[0-9]+}}, [{{x[0-9]+}}, #16] entry: %0 = bitcast i128* %ptr to fp128* - %1 = load fp128* %0, align 16 - %add.ptr = getelementptr inbounds i128* %ptr, i64 1 + %1 = load fp128, fp128* %0, align 16 + %add.ptr = getelementptr inbounds i128, i128* %ptr, i64 1 %2 = bitcast i128* %add.ptr to fp128* store fp128 %1, fp128* %2, align 16 ret void diff --git a/test/CodeGen/AArch64/PBQP-chain.ll b/test/CodeGen/AArch64/PBQP-chain.ll index c4ba026..3e5fa74 100644 --- a/test/CodeGen/AArch64/PBQP-chain.ll +++ b/test/CodeGen/AArch64/PBQP-chain.ll @@ -22,79 +22,79 @@ target triple = "aarch64" ; CHECK-ODD: fmadd {{d[0-9]*[13579]}}, {{d[0-9]*}}, {{d[0-9]*}}, {{d[0-9]*[13579]}} define void @fir(double* nocapture %rx, double* nocapture %ry, double* nocapture %c, double* nocapture %x, double* nocapture %y) { entry: - %0 = load double* %c, align 8 - %1 = load double* %x, align 8 + %0 = load double, double* %c, align 8 + %1 = load double, double* %x, align 8 %mul = fmul fast double %1, %0 - %2 = load double* %y, align 8 + %2 = load double, double* %y, align 8 %mul7 = fmul fast double %2, %0 - %arrayidx.1 = getelementptr inbounds double* %c, i64 1 - %3 = load double* %arrayidx.1, align 8 - %arrayidx2.1 = getelementptr inbounds double* %x, i64 1 - %4 = load double* %arrayidx2.1, align 8 + %arrayidx.1 = getelementptr inbounds double, double* %c, i64 1 + %3 = load double, double* %arrayidx.1, align 8 + %arrayidx2.1 = getelementptr inbounds double, double* %x, i64 1 + %4 = load double, double* %arrayidx2.1, align 8 %mul.1 = fmul fast double %4, %3 %add.1 = fadd fast double %mul.1, %mul - %arrayidx6.1 = getelementptr inbounds double* %y, i64 1 - %5 = load double* %arrayidx6.1, align 8 + %arrayidx6.1 = getelementptr inbounds double, double* %y, i64 1 + %5 = load double, double* %arrayidx6.1, align 8 %mul7.1 = fmul fast double %5, %3 %add8.1 = fadd fast double %mul7.1, %mul7 - %arrayidx.2 = getelementptr inbounds double* %c, i64 2 - %6 = load double* %arrayidx.2, align 8 - %arrayidx2.2 = getelementptr inbounds double* %x, i64 2 - %7 = load double* %arrayidx2.2, align 8 + %arrayidx.2 = getelementptr inbounds double, double* %c, i64 2 + %6 = load double, double* %arrayidx.2, align 8 + %arrayidx2.2 = getelementptr inbounds double, double* %x, i64 2 + %7 = load double, double* %arrayidx2.2, align 8 %mul.2 = fmul fast double %7, %6 %add.2 = fadd fast double %mul.2, %add.1 - %arrayidx6.2 = getelementptr inbounds double* %y, i64 2 - %8 = load double* %arrayidx6.2, align 8 + %arrayidx6.2 = getelementptr inbounds double, double* %y, i64 2 + %8 = load double, double* %arrayidx6.2, align 8 %mul7.2 = fmul fast double %8, %6 %add8.2 = fadd fast double %mul7.2, %add8.1 - %arrayidx.3 = getelementptr inbounds double* %c, i64 3 - %9 = load double* %arrayidx.3, align 8 - %arrayidx2.3 = getelementptr inbounds double* %x, i64 3 - %10 = load double* %arrayidx2.3, align 8 + %arrayidx.3 = getelementptr inbounds double, double* %c, i64 3 + %9 = load double, double* %arrayidx.3, align 8 + %arrayidx2.3 = getelementptr inbounds double, double* %x, i64 3 + %10 = load double, double* %arrayidx2.3, align 8 %mul.3 = fmul fast double %10, %9 %add.3 = fadd fast double %mul.3, %add.2 - %arrayidx6.3 = getelementptr inbounds double* %y, i64 3 - %11 = load double* %arrayidx6.3, align 8 + %arrayidx6.3 = getelementptr inbounds double, double* %y, i64 3 + %11 = load double, double* %arrayidx6.3, align 8 %mul7.3 = fmul fast double %11, %9 %add8.3 = fadd fast double %mul7.3, %add8.2 - %arrayidx.4 = getelementptr inbounds double* %c, i64 4 - %12 = load double* %arrayidx.4, align 8 - %arrayidx2.4 = getelementptr inbounds double* %x, i64 4 - %13 = load double* %arrayidx2.4, align 8 + %arrayidx.4 = getelementptr inbounds double, double* %c, i64 4 + %12 = load double, double* %arrayidx.4, align 8 + %arrayidx2.4 = getelementptr inbounds double, double* %x, i64 4 + %13 = load double, double* %arrayidx2.4, align 8 %mul.4 = fmul fast double %13, %12 %add.4 = fadd fast double %mul.4, %add.3 - %arrayidx6.4 = getelementptr inbounds double* %y, i64 4 - %14 = load double* %arrayidx6.4, align 8 + %arrayidx6.4 = getelementptr inbounds double, double* %y, i64 4 + %14 = load double, double* %arrayidx6.4, align 8 %mul7.4 = fmul fast double %14, %12 %add8.4 = fadd fast double %mul7.4, %add8.3 - %arrayidx.5 = getelementptr inbounds double* %c, i64 5 - %15 = load double* %arrayidx.5, align 8 - %arrayidx2.5 = getelementptr inbounds double* %x, i64 5 - %16 = load double* %arrayidx2.5, align 8 + %arrayidx.5 = getelementptr inbounds double, double* %c, i64 5 + %15 = load double, double* %arrayidx.5, align 8 + %arrayidx2.5 = getelementptr inbounds double, double* %x, i64 5 + %16 = load double, double* %arrayidx2.5, align 8 %mul.5 = fmul fast double %16, %15 %add.5 = fadd fast double %mul.5, %add.4 - %arrayidx6.5 = getelementptr inbounds double* %y, i64 5 - %17 = load double* %arrayidx6.5, align 8 + %arrayidx6.5 = getelementptr inbounds double, double* %y, i64 5 + %17 = load double, double* %arrayidx6.5, align 8 %mul7.5 = fmul fast double %17, %15 %add8.5 = fadd fast double %mul7.5, %add8.4 - %arrayidx.6 = getelementptr inbounds double* %c, i64 6 - %18 = load double* %arrayidx.6, align 8 - %arrayidx2.6 = getelementptr inbounds double* %x, i64 6 - %19 = load double* %arrayidx2.6, align 8 + %arrayidx.6 = getelementptr inbounds double, double* %c, i64 6 + %18 = load double, double* %arrayidx.6, align 8 + %arrayidx2.6 = getelementptr inbounds double, double* %x, i64 6 + %19 = load double, double* %arrayidx2.6, align 8 %mul.6 = fmul fast double %19, %18 %add.6 = fadd fast double %mul.6, %add.5 - %arrayidx6.6 = getelementptr inbounds double* %y, i64 6 - %20 = load double* %arrayidx6.6, align 8 + %arrayidx6.6 = getelementptr inbounds double, double* %y, i64 6 + %20 = load double, double* %arrayidx6.6, align 8 %mul7.6 = fmul fast double %20, %18 %add8.6 = fadd fast double %mul7.6, %add8.5 - %arrayidx.7 = getelementptr inbounds double* %c, i64 7 - %21 = load double* %arrayidx.7, align 8 - %arrayidx2.7 = getelementptr inbounds double* %x, i64 7 - %22 = load double* %arrayidx2.7, align 8 + %arrayidx.7 = getelementptr inbounds double, double* %c, i64 7 + %21 = load double, double* %arrayidx.7, align 8 + %arrayidx2.7 = getelementptr inbounds double, double* %x, i64 7 + %22 = load double, double* %arrayidx2.7, align 8 %mul.7 = fmul fast double %22, %21 %add.7 = fadd fast double %mul.7, %add.6 - %arrayidx6.7 = getelementptr inbounds double* %y, i64 7 - %23 = load double* %arrayidx6.7, align 8 + %arrayidx6.7 = getelementptr inbounds double, double* %y, i64 7 + %23 = load double, double* %arrayidx6.7, align 8 %mul7.7 = fmul fast double %23, %21 %add8.7 = fadd fast double %mul7.7, %add8.6 store double %add.7, double* %rx, align 8 diff --git a/test/CodeGen/AArch64/PBQP-coalesce-benefit.ll b/test/CodeGen/AArch64/PBQP-coalesce-benefit.ll index 45ac5e6..bd50b2d 100644 --- a/test/CodeGen/AArch64/PBQP-coalesce-benefit.ll +++ b/test/CodeGen/AArch64/PBQP-coalesce-benefit.ll @@ -3,11 +3,11 @@ ; CHECK-LABEL: test: define i32 @test(i32 %acc, i32* nocapture readonly %c) { entry: - %0 = load i32* %c, align 4 + %0 = load i32, i32* %c, align 4 ; CHECK-NOT: mov w{{[0-9]*}}, w0 %add = add nsw i32 %0, %acc - %arrayidx1 = getelementptr inbounds i32* %c, i64 1 - %1 = load i32* %arrayidx1, align 4 + %arrayidx1 = getelementptr inbounds i32, i32* %c, i64 1 + %1 = load i32, i32* %arrayidx1, align 4 %add2 = add nsw i32 %add, %1 ret i32 %add2 } diff --git a/test/CodeGen/AArch64/PBQP-csr.ll b/test/CodeGen/AArch64/PBQP-csr.ll index 64335ae..16d7f8c 100644 --- a/test/CodeGen/AArch64/PBQP-csr.ll +++ b/test/CodeGen/AArch64/PBQP-csr.ll @@ -11,27 +11,27 @@ define void @test_csr(%pl* nocapture readnone %this, %rs* nocapture %r) align 2 { ;CHECK-NOT: stp {{d[0-9]+}}, {{d[0-9]+}} entry: - %x.i = getelementptr inbounds %rs* %r, i64 0, i32 7, i32 0 - %y.i = getelementptr inbounds %rs* %r, i64 0, i32 7, i32 1 - %z.i = getelementptr inbounds %rs* %r, i64 0, i32 7, i32 2 - %x.i61 = getelementptr inbounds %rs* %r, i64 0, i32 8, i32 0 - %y.i62 = getelementptr inbounds %rs* %r, i64 0, i32 8, i32 1 - %z.i63 = getelementptr inbounds %rs* %r, i64 0, i32 8, i32 2 - %x.i58 = getelementptr inbounds %rs* %r, i64 0, i32 9, i32 0 - %y.i59 = getelementptr inbounds %rs* %r, i64 0, i32 9, i32 1 - %z.i60 = getelementptr inbounds %rs* %r, i64 0, i32 9, i32 2 - %na = getelementptr inbounds %rs* %r, i64 0, i32 0 + %x.i = getelementptr inbounds %rs, %rs* %r, i64 0, i32 7, i32 0 + %y.i = getelementptr inbounds %rs, %rs* %r, i64 0, i32 7, i32 1 + %z.i = getelementptr inbounds %rs, %rs* %r, i64 0, i32 7, i32 2 + %x.i61 = getelementptr inbounds %rs, %rs* %r, i64 0, i32 8, i32 0 + %y.i62 = getelementptr inbounds %rs, %rs* %r, i64 0, i32 8, i32 1 + %z.i63 = getelementptr inbounds %rs, %rs* %r, i64 0, i32 8, i32 2 + %x.i58 = getelementptr inbounds %rs, %rs* %r, i64 0, i32 9, i32 0 + %y.i59 = getelementptr inbounds %rs, %rs* %r, i64 0, i32 9, i32 1 + %z.i60 = getelementptr inbounds %rs, %rs* %r, i64 0, i32 9, i32 2 + %na = getelementptr inbounds %rs, %rs* %r, i64 0, i32 0 %0 = bitcast double* %x.i to i8* call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 72, i32 8, i1 false) - %1 = load i32* %na, align 4 + %1 = load i32, i32* %na, align 4 %cmp70 = icmp sgt i32 %1, 0 br i1 %cmp70, label %for.body.lr.ph, label %for.end for.body.lr.ph: ; preds = %entry - %fn = getelementptr inbounds %rs* %r, i64 0, i32 4 - %2 = load %v** %fn, align 8 - %fs = getelementptr inbounds %rs* %r, i64 0, i32 5 - %3 = load %v** %fs, align 8 + %fn = getelementptr inbounds %rs, %rs* %r, i64 0, i32 4 + %2 = load %v*, %v** %fn, align 8 + %fs = getelementptr inbounds %rs, %rs* %r, i64 0, i32 5 + %3 = load %v*, %v** %fs, align 8 %4 = sext i32 %1 to i64 br label %for.body @@ -42,31 +42,31 @@ for.body: ; preds = %for.body.lr.ph, %fo %7 = phi <2 x double> [ zeroinitializer, %for.body.lr.ph ], [ %22, %for.body ] %8 = phi <2 x double> [ zeroinitializer, %for.body.lr.ph ], [ %26, %for.body ] %9 = phi <2 x double> [ zeroinitializer, %for.body.lr.ph ], [ %28, %for.body ] - %x.i54 = getelementptr inbounds %v* %2, i64 %indvars.iv, i32 0 - %x1.i = getelementptr inbounds %v* %3, i64 %indvars.iv, i32 0 - %y.i56 = getelementptr inbounds %v* %2, i64 %indvars.iv, i32 1 + %x.i54 = getelementptr inbounds %v, %v* %2, i64 %indvars.iv, i32 0 + %x1.i = getelementptr inbounds %v, %v* %3, i64 %indvars.iv, i32 0 + %y.i56 = getelementptr inbounds %v, %v* %2, i64 %indvars.iv, i32 1 %10 = bitcast double* %x.i54 to <2 x double>* - %11 = load <2 x double>* %10, align 8 - %y2.i = getelementptr inbounds %v* %3, i64 %indvars.iv, i32 1 + %11 = load <2 x double>, <2 x double>* %10, align 8 + %y2.i = getelementptr inbounds %v, %v* %3, i64 %indvars.iv, i32 1 %12 = bitcast double* %x1.i to <2 x double>* - %13 = load <2 x double>* %12, align 8 + %13 = load <2 x double>, <2 x double>* %12, align 8 %14 = fadd fast <2 x double> %13, %11 - %z.i57 = getelementptr inbounds %v* %2, i64 %indvars.iv, i32 2 - %15 = load double* %z.i57, align 8 - %z4.i = getelementptr inbounds %v* %3, i64 %indvars.iv, i32 2 - %16 = load double* %z4.i, align 8 + %z.i57 = getelementptr inbounds %v, %v* %2, i64 %indvars.iv, i32 2 + %15 = load double, double* %z.i57, align 8 + %z4.i = getelementptr inbounds %v, %v* %3, i64 %indvars.iv, i32 2 + %16 = load double, double* %z4.i, align 8 %add5.i = fadd fast double %16, %15 %17 = fadd fast <2 x double> %6, %11 %18 = bitcast double* %x.i to <2 x double>* store <2 x double> %17, <2 x double>* %18, align 8 - %19 = load double* %x1.i, align 8 + %19 = load double, double* %x1.i, align 8 %20 = insertelement <2 x double> undef, double %15, i32 0 %21 = insertelement <2 x double> %20, double %19, i32 1 %22 = fadd fast <2 x double> %7, %21 %23 = bitcast double* %z.i to <2 x double>* store <2 x double> %22, <2 x double>* %23, align 8 %24 = bitcast double* %y2.i to <2 x double>* - %25 = load <2 x double>* %24, align 8 + %25 = load <2 x double>, <2 x double>* %24, align 8 %26 = fadd fast <2 x double> %8, %25 %27 = bitcast double* %y.i62 to <2 x double>* store <2 x double> %26, <2 x double>* %27, align 8 diff --git a/test/CodeGen/AArch64/Redundantstore.ll b/test/CodeGen/AArch64/Redundantstore.ll index 72f7f46..b207268 100644 --- a/test/CodeGen/AArch64/Redundantstore.ll +++ b/test/CodeGen/AArch64/Redundantstore.ll @@ -8,16 +8,16 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" ; CHECK-NOT: stur define i8* @test(i32 %size) { entry: - %0 = load i8** @end_of_array, align 8 + %0 = load i8*, i8** @end_of_array, align 8 %conv = sext i32 %size to i64 %and = and i64 %conv, -8 %conv2 = trunc i64 %and to i32 %add.ptr.sum = add nsw i64 %and, -4 - %add.ptr3 = getelementptr inbounds i8* %0, i64 %add.ptr.sum + %add.ptr3 = getelementptr inbounds i8, i8* %0, i64 %add.ptr.sum %size4 = bitcast i8* %add.ptr3 to i32* store i32 %conv2, i32* %size4, align 4 %add.ptr.sum9 = add nsw i64 %and, -4 - %add.ptr5 = getelementptr inbounds i8* %0, i64 %add.ptr.sum9 + %add.ptr5 = getelementptr inbounds i8, i8* %0, i64 %add.ptr.sum9 %size6 = bitcast i8* %add.ptr5 to i32* store i32 %conv2, i32* %size6, align 4 ret i8* %0 diff --git a/test/CodeGen/AArch64/a57-csel.ll b/test/CodeGen/AArch64/a57-csel.ll index 9d16d1a..f5496f7 100644 --- a/test/CodeGen/AArch64/a57-csel.ll +++ b/test/CodeGen/AArch64/a57-csel.ll @@ -3,7 +3,7 @@ ; Check that the select is expanded into a branch sequence. define i64 @f(i64 %a, i64 %b, i64* %c, i64 %d, i64 %e) { ; CHECK: cbz - %x0 = load i64* %c + %x0 = load i64, i64* %c %x1 = icmp eq i64 %x0, 0 %x2 = select i1 %x1, i64 %a, i64 %b %x3 = add i64 %x2, %d diff --git a/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll b/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll index 73ee522..8d60670 100644 --- a/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll +++ b/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll @@ -8,15 +8,15 @@ entry: br label %for.body, !dbg !39 for.body: ; preds = %for.body, %entry - %arrayidx5 = getelementptr inbounds i32* null, i64 1, !dbg !43 - %0 = load i32* null, align 4, !dbg !45, !tbaa !46 + %arrayidx5 = getelementptr inbounds i32, i32* null, i64 1, !dbg !43 + %0 = load i32, i32* null, align 4, !dbg !45, !tbaa !46 %s1 = sub nsw i32 0, %0, !dbg !50 %n1 = sext i32 %s1 to i64, !dbg !50 - %arrayidx21 = getelementptr inbounds i32* null, i64 3, !dbg !51 + %arrayidx21 = getelementptr inbounds i32, i32* null, i64 3, !dbg !51 %add53 = add nsw i64 %n1, 0, !dbg !52 %add55 = add nsw i64 %n1, 0, !dbg !53 %mul63 = mul nsw i64 %add53, -20995, !dbg !54 - tail call void @llvm.dbg.value(metadata i64 %mul63, i64 0, metadata !30, metadata !{!"0x102"}), !dbg !55 + tail call void @llvm.dbg.value(metadata i64 %mul63, i64 0, metadata !30, metadata !MDExpression()), !dbg !55 %mul65 = mul nsw i64 %add55, -3196, !dbg !56 %add67 = add nsw i64 0, %mul65, !dbg !57 %add80 = add i64 0, 1024, !dbg !58 @@ -44,51 +44,48 @@ attributes #1 = { nounwind readnone } !llvm.module.flags = !{!36, !37} !llvm.ident = !{!38} -!0 = !{!"0x11\0012\00clang version 3.6.0 \001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [] [] [] -!1 = !{!"test.c", !""} +!0 = !MDCompileUnit(language: DW_LANG_C99, producer: "clang version 3.6.0 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) +!1 = !MDFile(filename: "test.c", directory: "") !2 = !{} !3 = !{!4} -!4 = !{!"0x2e\00\00\00\00140\000\001\000\006\00256\001\00141", !1, !5, !6, null, void ()* @test, null, null, !12} ; [ DW_TAG_subprogram ] [] [] [def] [scope 141] [] -!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ] [] [] -!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [] [] [from ] +!4 = !MDSubprogram(name: "", line: 140, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 141, file: !1, scope: !1, type: !6, function: void ()* @test, variables: !12) +!6 = !MDSubroutineType(types: !7) !7 = !{null, !8} -!8 = !{!"0xf\00\000\0064\0064\000\000", null, null, !9} ; [ DW_TAG_pointer_type ] [] [] [] -!9 = !{!"0x16\00\0030\000\000\000\000", !10, null, !11} ; [ DW_TAG_typedef ] [] [] [] [from int] -!10 = !{!"", !""} -!11 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [] [int] [] +!8 = !MDDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !9) +!9 = !MDDerivedType(tag: DW_TAG_typedef, line: 30, file: !1, baseType: !11) +!11 = !MDBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !12 = !{!13, !14, !18, !19, !20, !21, !22, !23, !24, !25, !26, !27, !28, !29, !30, !31, !32, !33, !34, !35} -!13 = !{!"0x101\00\0016777356\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [] [data] [] -!14 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] [] -!15 = !{!"0x16\00\00183\000\000\000\000", !16, null, !17} ; [ DW_TAG_typedef ] [] [INT32] [] [from long int] -!16 = !{!"", !""} -!17 = !{!"0x24\00\000\0064\0064\000\000\005", null, null} ; [ DW_TAG_base_type ] [] [long int] [] -!18 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] [] -!19 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] [] -!20 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] [] -!21 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] [] -!22 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] [] -!23 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] [] -!24 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!25 = !{!"0x100\00\00143\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!26 = !{!"0x100\00\00143\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!27 = !{!"0x100\00\00143\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!28 = !{!"0x100\00\00143\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!29 = !{!"0x100\00\00144\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!30 = !{!"0x100\00\00144\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!31 = !{!"0x100\00\00144\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!32 = !{!"0x100\00\00144\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!33 = !{!"0x100\00\00144\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!34 = !{!"0x100\00\00145\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [ ] [] [] -!35 = !{!"0x100\00\00146\000", !4, !5, !11} ; [ DW_TAG_auto_variable ] [ ] [] [] +!13 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "", line: 140, arg: 1, scope: !4, file: !1, type: !8) +!14 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 142, scope: !4, file: !1, type: !15) +!15 = !MDDerivedType(tag: DW_TAG_typedef, line: 183, file: !1, baseType: !17) +!17 = !MDBasicType(tag: DW_TAG_base_type, size: 64, align: 64, encoding: DW_ATE_signed) +!18 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 142, scope: !4, file: !1, type: !15) +!19 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 142, scope: !4, file: !1, type: !15) +!20 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 142, scope: !4, file: !1, type: !15) +!21 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 142, scope: !4, file: !1, type: !15) +!22 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 142, scope: !4, file: !1, type: !15) +!23 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 142, scope: !4, file: !1, type: !15) +!24 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 142, scope: !4, file: !1, type: !15) +!25 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 143, scope: !4, file: !1, type: !15) +!26 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 143, scope: !4, file: !1, type: !15) +!27 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 143, scope: !4, file: !1, type: !15) +!28 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 143, scope: !4, file: !1, type: !15) +!29 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 144, scope: !4, file: !1, type: !15) +!30 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 144, scope: !4, file: !1, type: !15) +!31 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 144, scope: !4, file: !1, type: !15) +!32 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 144, scope: !4, file: !1, type: !15) +!33 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 144, scope: !4, file: !1, type: !15) +!34 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 145, scope: !4, file: !1, type: !8) +!35 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "", line: 146, scope: !4, file: !1, type: !11) !36 = !{i32 2, !"Dwarf Version", i32 4} -!37 = !{i32 2, !"Debug Info Version", i32 2} +!37 = !{i32 2, !"Debug Info Version", i32 3} !38 = !{!"clang version 3.6.0 "} !39 = !MDLocation(line: 154, column: 8, scope: !40) -!40 = !{!"0xb\00154\008\002", !1, !41} ; [ DW_TAG_lexical_block ] [ ] [] -!41 = !{!"0xb\00154\008\001", !1, !42} ; [ DW_TAG_lexical_block ] [ ] [] -!42 = !{!"0xb\00154\003\000", !1, !4} ; [ DW_TAG_lexical_block ] [ ] [] +!40 = distinct !MDLexicalBlock(line: 154, column: 8, file: !1, scope: !41) +!41 = distinct !MDLexicalBlock(line: 154, column: 8, file: !1, scope: !42) +!42 = distinct !MDLexicalBlock(line: 154, column: 3, file: !1, scope: !4) !43 = !MDLocation(line: 157, column: 5, scope: !44) -!44 = !{!"0xb\00154\0042\000", !1, !42} ; [ DW_TAG_lexical_block ] [ ] [] +!44 = distinct !MDLexicalBlock(line: 154, column: 42, file: !1, scope: !42) !45 = !MDLocation(line: 159, column: 5, scope: !44) !46 = !{!47, !47, i64 0} !47 = !{!"int", !48, i64 0} diff --git a/test/CodeGen/AArch64/aarch64-2014-12-02-combine-soften.ll b/test/CodeGen/AArch64/aarch64-2014-12-02-combine-soften.ll index 4553251..b2ee517 100644 --- a/test/CodeGen/AArch64/aarch64-2014-12-02-combine-soften.ll +++ b/test/CodeGen/AArch64/aarch64-2014-12-02-combine-soften.ll @@ -9,7 +9,7 @@ define void @foo() { entry: ;CHECK-LABEL: foo: ;CHECK: __floatsisf - %0 = load i32* @x, align 4 + %0 = load i32, i32* @x, align 4 %conv = sitofp i32 %0 to float store float %conv, float* bitcast (i32* @t to float*), align 4 ret void diff --git a/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll b/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll index 7108bc0..b0e9d4a 100644 --- a/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll +++ b/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll @@ -29,15 +29,15 @@ target triple = "aarch64" define void @f1(double* nocapture readonly %p, double* nocapture %q) #0 { entry: - %0 = load double* %p, align 8 - %arrayidx1 = getelementptr inbounds double* %p, i64 1 - %1 = load double* %arrayidx1, align 8 - %arrayidx2 = getelementptr inbounds double* %p, i64 2 - %2 = load double* %arrayidx2, align 8 - %arrayidx3 = getelementptr inbounds double* %p, i64 3 - %3 = load double* %arrayidx3, align 8 - %arrayidx4 = getelementptr inbounds double* %p, i64 4 - %4 = load double* %arrayidx4, align 8 + %0 = load double, double* %p, align 8 + %arrayidx1 = getelementptr inbounds double, double* %p, i64 1 + %1 = load double, double* %arrayidx1, align 8 + %arrayidx2 = getelementptr inbounds double, double* %p, i64 2 + %2 = load double, double* %arrayidx2, align 8 + %arrayidx3 = getelementptr inbounds double, double* %p, i64 3 + %3 = load double, double* %arrayidx3, align 8 + %arrayidx4 = getelementptr inbounds double, double* %p, i64 4 + %4 = load double, double* %arrayidx4, align 8 %mul = fmul fast double %0, %1 %add = fadd fast double %mul, %4 %mul5 = fmul fast double %1, %2 @@ -47,18 +47,18 @@ entry: %mul8 = fmul fast double %2, %3 %add9 = fadd fast double %mul8, %sub store double %add9, double* %q, align 8 - %arrayidx11 = getelementptr inbounds double* %p, i64 5 - %5 = load double* %arrayidx11, align 8 - %arrayidx12 = getelementptr inbounds double* %p, i64 6 - %6 = load double* %arrayidx12, align 8 - %arrayidx13 = getelementptr inbounds double* %p, i64 7 - %7 = load double* %arrayidx13, align 8 + %arrayidx11 = getelementptr inbounds double, double* %p, i64 5 + %5 = load double, double* %arrayidx11, align 8 + %arrayidx12 = getelementptr inbounds double, double* %p, i64 6 + %6 = load double, double* %arrayidx12, align 8 + %arrayidx13 = getelementptr inbounds double, double* %p, i64 7 + %7 = load double, double* %arrayidx13, align 8 %mul15 = fmul fast double %6, %7 %mul16 = fmul fast double %0, %5 %add17 = fadd fast double %mul16, %mul15 %mul18 = fmul fast double %5, %6 %add19 = fadd fast double %mul18, %add17 - %arrayidx20 = getelementptr inbounds double* %q, i64 1 + %arrayidx20 = getelementptr inbounds double, double* %q, i64 1 store double %add19, double* %arrayidx20, align 8 ret void } @@ -81,21 +81,21 @@ entry: define void @f2(double* nocapture readonly %p, double* nocapture %q) #0 { entry: - %0 = load double* %p, align 8 - %arrayidx1 = getelementptr inbounds double* %p, i64 1 - %1 = load double* %arrayidx1, align 8 - %arrayidx2 = getelementptr inbounds double* %p, i64 2 - %2 = load double* %arrayidx2, align 8 - %arrayidx3 = getelementptr inbounds double* %p, i64 3 - %3 = load double* %arrayidx3, align 8 - %arrayidx4 = getelementptr inbounds double* %p, i64 4 - %4 = load double* %arrayidx4, align 8 - %arrayidx5 = getelementptr inbounds double* %p, i64 5 - %5 = load double* %arrayidx5, align 8 - %arrayidx6 = getelementptr inbounds double* %p, i64 6 - %6 = load double* %arrayidx6, align 8 - %arrayidx7 = getelementptr inbounds double* %p, i64 7 - %7 = load double* %arrayidx7, align 8 + %0 = load double, double* %p, align 8 + %arrayidx1 = getelementptr inbounds double, double* %p, i64 1 + %1 = load double, double* %arrayidx1, align 8 + %arrayidx2 = getelementptr inbounds double, double* %p, i64 2 + %2 = load double, double* %arrayidx2, align 8 + %arrayidx3 = getelementptr inbounds double, double* %p, i64 3 + %3 = load double, double* %arrayidx3, align 8 + %arrayidx4 = getelementptr inbounds double, double* %p, i64 4 + %4 = load double, double* %arrayidx4, align 8 + %arrayidx5 = getelementptr inbounds double, double* %p, i64 5 + %5 = load double, double* %arrayidx5, align 8 + %arrayidx6 = getelementptr inbounds double, double* %p, i64 6 + %6 = load double, double* %arrayidx6, align 8 + %arrayidx7 = getelementptr inbounds double, double* %p, i64 7 + %7 = load double, double* %arrayidx7, align 8 %mul = fmul fast double %0, %1 %add = fadd fast double %mul, %7 %mul8 = fmul fast double %5, %6 @@ -110,7 +110,7 @@ entry: %mul16 = fmul fast double %2, %3 %add17 = fadd fast double %mul16, %sub store double %add17, double* %q, align 8 - %arrayidx19 = getelementptr inbounds double* %q, i64 1 + %arrayidx19 = getelementptr inbounds double, double* %q, i64 1 store double %add15, double* %arrayidx19, align 8 ret void } @@ -127,15 +127,15 @@ entry: define void @f3(double* nocapture readonly %p, double* nocapture %q) #0 { entry: - %0 = load double* %p, align 8 - %arrayidx1 = getelementptr inbounds double* %p, i64 1 - %1 = load double* %arrayidx1, align 8 - %arrayidx2 = getelementptr inbounds double* %p, i64 2 - %2 = load double* %arrayidx2, align 8 - %arrayidx3 = getelementptr inbounds double* %p, i64 3 - %3 = load double* %arrayidx3, align 8 - %arrayidx4 = getelementptr inbounds double* %p, i64 4 - %4 = load double* %arrayidx4, align 8 + %0 = load double, double* %p, align 8 + %arrayidx1 = getelementptr inbounds double, double* %p, i64 1 + %1 = load double, double* %arrayidx1, align 8 + %arrayidx2 = getelementptr inbounds double, double* %p, i64 2 + %2 = load double, double* %arrayidx2, align 8 + %arrayidx3 = getelementptr inbounds double, double* %p, i64 3 + %3 = load double, double* %arrayidx3, align 8 + %arrayidx4 = getelementptr inbounds double, double* %p, i64 4 + %4 = load double, double* %arrayidx4, align 8 %mul = fmul fast double %0, %1 %add = fadd fast double %mul, %4 %mul5 = fmul fast double %1, %2 @@ -176,21 +176,21 @@ declare void @g(...) #1 define void @f4(float* nocapture readonly %p, float* nocapture %q) #0 { entry: - %0 = load float* %p, align 4 - %arrayidx1 = getelementptr inbounds float* %p, i64 1 - %1 = load float* %arrayidx1, align 4 - %arrayidx2 = getelementptr inbounds float* %p, i64 2 - %2 = load float* %arrayidx2, align 4 - %arrayidx3 = getelementptr inbounds float* %p, i64 3 - %3 = load float* %arrayidx3, align 4 - %arrayidx4 = getelementptr inbounds float* %p, i64 4 - %4 = load float* %arrayidx4, align 4 - %arrayidx5 = getelementptr inbounds float* %p, i64 5 - %5 = load float* %arrayidx5, align 4 - %arrayidx6 = getelementptr inbounds float* %p, i64 6 - %6 = load float* %arrayidx6, align 4 - %arrayidx7 = getelementptr inbounds float* %p, i64 7 - %7 = load float* %arrayidx7, align 4 + %0 = load float, float* %p, align 4 + %arrayidx1 = getelementptr inbounds float, float* %p, i64 1 + %1 = load float, float* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds float, float* %p, i64 2 + %2 = load float, float* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds float, float* %p, i64 3 + %3 = load float, float* %arrayidx3, align 4 + %arrayidx4 = getelementptr inbounds float, float* %p, i64 4 + %4 = load float, float* %arrayidx4, align 4 + %arrayidx5 = getelementptr inbounds float, float* %p, i64 5 + %5 = load float, float* %arrayidx5, align 4 + %arrayidx6 = getelementptr inbounds float, float* %p, i64 6 + %6 = load float, float* %arrayidx6, align 4 + %arrayidx7 = getelementptr inbounds float, float* %p, i64 7 + %7 = load float, float* %arrayidx7, align 4 %mul = fmul fast float %0, %1 %add = fadd fast float %mul, %7 %mul8 = fmul fast float %5, %6 @@ -205,7 +205,7 @@ entry: %mul16 = fmul fast float %2, %3 %add17 = fadd fast float %mul16, %sub store float %add17, float* %q, align 4 - %arrayidx19 = getelementptr inbounds float* %q, i64 1 + %arrayidx19 = getelementptr inbounds float, float* %q, i64 1 store float %add15, float* %arrayidx19, align 4 ret void } @@ -222,15 +222,15 @@ entry: define void @f5(float* nocapture readonly %p, float* nocapture %q) #0 { entry: - %0 = load float* %p, align 4 - %arrayidx1 = getelementptr inbounds float* %p, i64 1 - %1 = load float* %arrayidx1, align 4 - %arrayidx2 = getelementptr inbounds float* %p, i64 2 - %2 = load float* %arrayidx2, align 4 - %arrayidx3 = getelementptr inbounds float* %p, i64 3 - %3 = load float* %arrayidx3, align 4 - %arrayidx4 = getelementptr inbounds float* %p, i64 4 - %4 = load float* %arrayidx4, align 4 + %0 = load float, float* %p, align 4 + %arrayidx1 = getelementptr inbounds float, float* %p, i64 1 + %1 = load float, float* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds float, float* %p, i64 2 + %2 = load float, float* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds float, float* %p, i64 3 + %3 = load float, float* %arrayidx3, align 4 + %arrayidx4 = getelementptr inbounds float, float* %p, i64 4 + %4 = load float, float* %arrayidx4, align 4 %mul = fmul fast float %0, %1 %add = fadd fast float %mul, %4 %mul5 = fmul fast float %1, %2 @@ -264,15 +264,15 @@ if.end: ; preds = %if.then, %entry define void @f6(double* nocapture readonly %p, double* nocapture %q) #0 { entry: - %0 = load double* %p, align 8 - %arrayidx1 = getelementptr inbounds double* %p, i64 1 - %1 = load double* %arrayidx1, align 8 - %arrayidx2 = getelementptr inbounds double* %p, i64 2 - %2 = load double* %arrayidx2, align 8 - %arrayidx3 = getelementptr inbounds double* %p, i64 3 - %3 = load double* %arrayidx3, align 8 - %arrayidx4 = getelementptr inbounds double* %p, i64 4 - %4 = load double* %arrayidx4, align 8 + %0 = load double, double* %p, align 8 + %arrayidx1 = getelementptr inbounds double, double* %p, i64 1 + %1 = load double, double* %arrayidx1, align 8 + %arrayidx2 = getelementptr inbounds double, double* %p, i64 2 + %2 = load double, double* %arrayidx2, align 8 + %arrayidx3 = getelementptr inbounds double, double* %p, i64 3 + %3 = load double, double* %arrayidx3, align 8 + %arrayidx4 = getelementptr inbounds double, double* %p, i64 4 + %4 = load double, double* %arrayidx4, align 8 %mul = fmul fast double %0, %1 %add = fadd fast double %mul, %4 %mul5 = fmul fast double %1, %2 @@ -299,15 +299,15 @@ declare double @hh(double) #1 define void @f7(double* nocapture readonly %p, double* nocapture %q) #0 { entry: - %0 = load double* %p, align 8 - %arrayidx1 = getelementptr inbounds double* %p, i64 1 - %1 = load double* %arrayidx1, align 8 - %arrayidx2 = getelementptr inbounds double* %p, i64 2 - %2 = load double* %arrayidx2, align 8 - %arrayidx3 = getelementptr inbounds double* %p, i64 3 - %3 = load double* %arrayidx3, align 8 - %arrayidx4 = getelementptr inbounds double* %p, i64 4 - %4 = load double* %arrayidx4, align 8 + %0 = load double, double* %p, align 8 + %arrayidx1 = getelementptr inbounds double, double* %p, i64 1 + %1 = load double, double* %arrayidx1, align 8 + %arrayidx2 = getelementptr inbounds double, double* %p, i64 2 + %2 = load double, double* %arrayidx2, align 8 + %arrayidx3 = getelementptr inbounds double, double* %p, i64 3 + %3 = load double, double* %arrayidx3, align 8 + %arrayidx4 = getelementptr inbounds double, double* %p, i64 4 + %4 = load double, double* %arrayidx4, align 8 %mul = fmul fast double %0, %1 %add = fadd fast double %mul, %4 %mul5 = fmul fast double %1, %2 diff --git a/test/CodeGen/AArch64/aarch64-address-type-promotion-assertion.ll b/test/CodeGen/AArch64/aarch64-address-type-promotion-assertion.ll index 2df9c37..0c6be21 100644 --- a/test/CodeGen/AArch64/aarch64-address-type-promotion-assertion.ll +++ b/test/CodeGen/AArch64/aarch64-address-type-promotion-assertion.ll @@ -11,14 +11,14 @@ invoke.cont145: br i1 %or.cond, label %if.then274, label %invoke.cont145 if.then274: - %0 = load i32* null, align 4 + %0 = load i32, i32* null, align 4 br i1 undef, label %invoke.cont291, label %if.else313 invoke.cont291: %idxprom.i.i.i605 = sext i32 %0 to i64 - %arrayidx.i.i.i607 = getelementptr inbounds double* undef, i64 %idxprom.i.i.i605 + %arrayidx.i.i.i607 = getelementptr inbounds double, double* undef, i64 %idxprom.i.i.i605 %idxprom.i.i.i596 = sext i32 %0 to i64 - %arrayidx.i.i.i598 = getelementptr inbounds double* undef, i64 %idxprom.i.i.i596 + %arrayidx.i.i.i598 = getelementptr inbounds double, double* undef, i64 %idxprom.i.i.i596 br label %if.end356 if.else313: @@ -30,7 +30,7 @@ invoke.cont317: invoke.cont326: %idxprom.i.i.i587 = sext i32 %0 to i64 - %arrayidx.i.i.i589 = getelementptr inbounds double* undef, i64 %idxprom.i.i.i587 + %arrayidx.i.i.i589 = getelementptr inbounds double, double* undef, i64 %idxprom.i.i.i587 %sub329 = fsub fast double undef, undef br label %invoke.cont334 @@ -40,12 +40,12 @@ invoke.cont334: invoke.cont342: %idxprom.i.i.i578 = sext i32 %0 to i64 - %arrayidx.i.i.i580 = getelementptr inbounds double* undef, i64 %idxprom.i.i.i578 + %arrayidx.i.i.i580 = getelementptr inbounds double, double* undef, i64 %idxprom.i.i.i578 br label %if.end356 invoke.cont353: %idxprom.i.i.i572 = sext i32 %0 to i64 - %arrayidx.i.i.i574 = getelementptr inbounds double* undef, i64 %idxprom.i.i.i572 + %arrayidx.i.i.i574 = getelementptr inbounds double, double* undef, i64 %idxprom.i.i.i572 br label %if.end356 if.end356: diff --git a/test/CodeGen/AArch64/aarch64-address-type-promotion.ll b/test/CodeGen/AArch64/aarch64-address-type-promotion.ll index ee90d19..07e0ba6 100644 --- a/test/CodeGen/AArch64/aarch64-address-type-promotion.ll +++ b/test/CodeGen/AArch64/aarch64-address-type-promotion.ll @@ -14,15 +14,15 @@ entry: ; CHECK-NEXT: ret %add = add nsw i32 %i, 1 %idxprom = sext i32 %add to i64 - %arrayidx = getelementptr inbounds i32* %a, i64 %idxprom - %0 = load i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, i32* %a, i64 %idxprom + %0 = load i32, i32* %arrayidx, align 4 %add1 = add nsw i32 %i, 2 %idxprom2 = sext i32 %add1 to i64 - %arrayidx3 = getelementptr inbounds i32* %a, i64 %idxprom2 - %1 = load i32* %arrayidx3, align 4 + %arrayidx3 = getelementptr inbounds i32, i32* %a, i64 %idxprom2 + %1 = load i32, i32* %arrayidx3, align 4 %add4 = add nsw i32 %1, %0 %idxprom5 = sext i32 %i to i64 - %arrayidx6 = getelementptr inbounds i32* %a, i64 %idxprom5 + %arrayidx6 = getelementptr inbounds i32, i32* %a, i64 %idxprom5 store i32 %add4, i32* %arrayidx6, align 4 ret void } diff --git a/test/CodeGen/AArch64/aarch64-be-bv.ll b/test/CodeGen/AArch64/aarch64-be-bv.ll index 01642a4..fb41156 100644 --- a/test/CodeGen/AArch64/aarch64-be-bv.ll +++ b/test/CodeGen/AArch64/aarch64-be-bv.ll @@ -8,7 +8,7 @@ define i16 @movi_modimm_t1() nounwind { ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -20,7 +20,7 @@ define i16 @movi_modimm_t2() nounwind { ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1, lsl #8 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -32,7 +32,7 @@ define i16 @movi_modimm_t3() nounwind { ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1, lsl #16 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -44,7 +44,7 @@ define i16 @movi_modimm_t4() nounwind { ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1, lsl #24 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -56,7 +56,7 @@ define i16 @movi_modimm_t5() nounwind { ; CHECK-NEXT: movi v[[REG2:[0-9]+]].8h, #0x1 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -68,7 +68,7 @@ define i16 @movi_modimm_t6() nounwind { ; CHECK-NEXT: movi v[[REG2:[0-9]+]].8h, #0x1, lsl #8 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -80,7 +80,7 @@ define i16 @movi_modimm_t7() nounwind { ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1, msl #8 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 511, i16 0, i16 511, i16 0, i16 511, i16 0, i16 511, i16 0> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -92,7 +92,7 @@ define i16 @movi_modimm_t8() nounwind { ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1, msl #16 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 1> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -104,7 +104,7 @@ define i16 @movi_modimm_t9() nounwind { ; CHECK-NEXT: movi v[[REG2:[0-9]+]].16b, #0x1 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -116,7 +116,7 @@ define i16 @movi_modimm_t10() nounwind { ; CHECK-NEXT: movi v[[REG2:[0-9]+]].2d, #0x00ffff0000ffff ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 -1, i16 0, i16 -1, i16 0, i16 -1, i16 0, i16 -1, i16 0> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -128,7 +128,7 @@ define i16 @fmov_modimm_t11() nounwind { ; CHECK-NEXT: fmov v[[REG2:[0-9]+]].4s, #3.00000000 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -140,7 +140,7 @@ define i16 @fmov_modimm_t12() nounwind { ; CHECK-NEXT: fmov v[[REG2:[0-9]+]].2d, #0.17968750 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 0, i16 0, i16 0, i16 16327, i16 0, i16 0, i16 0, i16 16327> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -152,7 +152,7 @@ define i16 @mvni_modimm_t1() nounwind { ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -164,7 +164,7 @@ define i16 @mvni_modimm_t2() nounwind { ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1, lsl #8 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -176,7 +176,7 @@ define i16 @mvni_modimm_t3() nounwind { ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1, lsl #16 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -188,7 +188,7 @@ define i16 @mvni_modimm_t4() nounwind { ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1, lsl #24 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -200,7 +200,7 @@ define i16 @mvni_modimm_t5() nounwind { ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].8h, #0x1 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -212,7 +212,7 @@ define i16 @mvni_modimm_t6() nounwind { ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].8h, #0x1, lsl #8 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -224,7 +224,7 @@ define i16 @mvni_modimm_t7() nounwind { ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1, msl #8 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 65024, i16 65535, i16 65024, i16 65535, i16 65024, i16 65535, i16 65024, i16 65535> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -236,7 +236,7 @@ define i16 @mvni_modimm_t8() nounwind { ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1, msl #16 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = add <8 x i16> %in, <i16 0, i16 65534, i16 0, i16 65534, i16 0, i16 65534, i16 0, i16 65534> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -247,7 +247,7 @@ define i16 @bic_modimm_t1() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #0x1 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = and <8 x i16> %in, <i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -258,7 +258,7 @@ define i16 @bic_modimm_t2() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #0x1, lsl #8 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = and <8 x i16> %in, <i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -269,7 +269,7 @@ define i16 @bic_modimm_t3() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #0x1, lsl #16 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = and <8 x i16> %in, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -280,7 +280,7 @@ define i16 @bic_modimm_t4() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #0x1, lsl #24 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = and <8 x i16> %in, <i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -291,7 +291,7 @@ define i16 @bic_modimm_t5() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] ; CHECK-NEXT: bic v[[REG2:[0-9]+]].8h, #0x1 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = and <8 x i16> %in, <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -302,7 +302,7 @@ define i16 @bic_modimm_t6() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] ; CHECK-NEXT: bic v[[REG2:[0-9]+]].8h, #0x1, lsl #8 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = and <8 x i16> %in, <i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -313,7 +313,7 @@ define i16 @orr_modimm_t1() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #0x1 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = or <8 x i16> %in, <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -324,7 +324,7 @@ define i16 @orr_modimm_t2() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #0x1, lsl #8 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = or <8 x i16> %in, <i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -335,7 +335,7 @@ define i16 @orr_modimm_t3() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #0x1, lsl #16 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = or <8 x i16> %in, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -346,7 +346,7 @@ define i16 @orr_modimm_t4() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #0x1, lsl #24 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = or <8 x i16> %in, <i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -357,7 +357,7 @@ define i16 @orr_modimm_t5() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] ; CHECK-NEXT: orr v[[REG2:[0-9]+]].8h, #0x1 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = or <8 x i16> %in, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el @@ -368,7 +368,7 @@ define i16 @orr_modimm_t6() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] ; CHECK-NEXT: orr v[[REG2:[0-9]+]].8h, #0x1, lsl #8 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] - %in = load <8 x i16>* @vec_v8i16 + %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = or <8 x i16> %in, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256> %el = extractelement <8 x i16> %rv, i32 0 ret i16 %el diff --git a/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll b/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll index 64d91ee..2170e4b 100644 --- a/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll +++ b/test/CodeGen/AArch64/aarch64-fix-cortex-a53-835769.ll @@ -22,7 +22,7 @@ target triple = "aarch64--linux-gnu" define i64 @f_load_madd_64(i64 %a, i64 %b, i64* nocapture readonly %c) #0 { entry: - %0 = load i64* %c, align 8 + %0 = load i64, i64* %c, align 8 %mul = mul nsw i64 %0, %b %add = add nsw i64 %mul, %a ret i64 %add @@ -41,7 +41,7 @@ entry: define i32 @f_load_madd_32(i32 %a, i32 %b, i32* nocapture readonly %c) #0 { entry: - %0 = load i32* %c, align 4 + %0 = load i32, i32* %c, align 4 %mul = mul nsw i32 %0, %b %add = add nsw i32 %mul, %a ret i32 %add @@ -56,7 +56,7 @@ entry: define i64 @f_load_msub_64(i64 %a, i64 %b, i64* nocapture readonly %c) #0 { entry: - %0 = load i64* %c, align 8 + %0 = load i64, i64* %c, align 8 %mul = mul nsw i64 %0, %b %sub = sub nsw i64 %a, %mul ret i64 %sub @@ -72,7 +72,7 @@ entry: define i32 @f_load_msub_32(i32 %a, i32 %b, i32* nocapture readonly %c) #0 { entry: - %0 = load i32* %c, align 4 + %0 = load i32, i32* %c, align 4 %mul = mul nsw i32 %0, %b %sub = sub nsw i32 %a, %mul ret i32 %sub @@ -87,7 +87,7 @@ entry: define i64 @f_load_mul_64(i64 %a, i64 %b, i64* nocapture readonly %c) #0 { entry: - %0 = load i64* %c, align 8 + %0 = load i64, i64* %c, align 8 %mul = mul nsw i64 %0, %b ret i64 %mul } @@ -101,7 +101,7 @@ entry: define i32 @f_load_mul_32(i32 %a, i32 %b, i32* nocapture readonly %c) #0 { entry: - %0 = load i32* %c, align 4 + %0 = load i32, i32* %c, align 4 %mul = mul nsw i32 %0, %b ret i32 %mul } @@ -115,7 +115,7 @@ entry: define i64 @f_load_mneg_64(i64 %a, i64 %b, i64* nocapture readonly %c) #0 { entry: - %0 = load i64* %c, align 8 + %0 = load i64, i64* %c, align 8 %mul = sub i64 0, %b %sub = mul i64 %0, %mul ret i64 %sub @@ -133,7 +133,7 @@ entry: define i32 @f_load_mneg_32(i32 %a, i32 %b, i32* nocapture readonly %c) #0 { entry: - %0 = load i32* %c, align 4 + %0 = load i32, i32* %c, align 4 %mul = sub i32 0, %b %sub = mul i32 %0, %mul ret i32 %sub @@ -154,7 +154,7 @@ entry: %conv1 = sext i32 %c to i64 %mul = mul nsw i64 %conv1, %conv %add = add nsw i64 %mul, %a - %0 = load i32* %d, align 4 + %0 = load i32, i32* %d, align 4 %conv2 = sext i32 %0 to i64 %add3 = add nsw i64 %add, %conv2 ret i64 %add3 @@ -174,7 +174,7 @@ entry: %conv1 = sext i32 %c to i64 %mul = mul nsw i64 %conv1, %conv %sub = sub i64 %a, %mul - %0 = load i32* %d, align 4 + %0 = load i32, i32* %d, align 4 %conv2 = sext i32 %0 to i64 %add = add nsw i64 %sub, %conv2 ret i64 %add @@ -193,7 +193,7 @@ entry: %conv = sext i32 %b to i64 %conv1 = sext i32 %c to i64 %mul = mul nsw i64 %conv1, %conv - %0 = load i32* %d, align 4 + %0 = load i32, i32* %d, align 4 %conv2 = sext i32 %0 to i64 %div = sdiv i64 %mul, %conv2 ret i64 %div @@ -212,7 +212,7 @@ entry: %conv1 = sext i32 %c to i64 %mul = sub nsw i64 0, %conv %sub = mul i64 %conv1, %mul - %0 = load i32* %d, align 4 + %0 = load i32, i32* %d, align 4 %conv2 = sext i32 %0 to i64 %div = sdiv i64 %sub, %conv2 ret i64 %div @@ -229,7 +229,7 @@ entry: %conv1 = zext i32 %c to i64 %mul = mul i64 %conv1, %conv %add = add i64 %mul, %a - %0 = load i32* %d, align 4 + %0 = load i32, i32* %d, align 4 %conv2 = zext i32 %0 to i64 %add3 = add i64 %add, %conv2 ret i64 %add3 @@ -249,7 +249,7 @@ entry: %conv1 = zext i32 %c to i64 %mul = mul i64 %conv1, %conv %sub = sub i64 %a, %mul - %0 = load i32* %d, align 4 + %0 = load i32, i32* %d, align 4 %conv2 = zext i32 %0 to i64 %add = add i64 %sub, %conv2 ret i64 %add @@ -268,7 +268,7 @@ entry: %conv = zext i32 %b to i64 %conv1 = zext i32 %c to i64 %mul = mul i64 %conv1, %conv - %0 = load i32* %d, align 4 + %0 = load i32, i32* %d, align 4 %conv2 = zext i32 %0 to i64 %div = udiv i64 %mul, %conv2 ret i64 %div @@ -287,7 +287,7 @@ entry: %conv1 = zext i32 %c to i64 %mul = sub nsw i64 0, %conv %sub = mul i64 %conv1, %mul - %0 = load i32* %d, align 4 + %0 = load i32, i32* %d, align 4 %conv2 = zext i32 %0 to i64 %div = udiv i64 %sub, %conv2 ret i64 %div @@ -300,7 +300,7 @@ entry: define i64 @f_store_madd_64(i64 %a, i64 %b, i64* nocapture readonly %cp, i64* nocapture %e) #1 { entry: - %0 = load i64* %cp, align 8 + %0 = load i64, i64* %cp, align 8 store i64 %a, i64* %e, align 8 %mul = mul nsw i64 %0, %b %add = add nsw i64 %mul, %a @@ -317,7 +317,7 @@ entry: define i32 @f_store_madd_32(i32 %a, i32 %b, i32* nocapture readonly %cp, i32* nocapture %e) #1 { entry: - %0 = load i32* %cp, align 4 + %0 = load i32, i32* %cp, align 4 store i32 %a, i32* %e, align 4 %mul = mul nsw i32 %0, %b %add = add nsw i32 %mul, %a @@ -333,7 +333,7 @@ entry: define i64 @f_store_msub_64(i64 %a, i64 %b, i64* nocapture readonly %cp, i64* nocapture %e) #1 { entry: - %0 = load i64* %cp, align 8 + %0 = load i64, i64* %cp, align 8 store i64 %a, i64* %e, align 8 %mul = mul nsw i64 %0, %b %sub = sub nsw i64 %a, %mul @@ -350,7 +350,7 @@ entry: define i32 @f_store_msub_32(i32 %a, i32 %b, i32* nocapture readonly %cp, i32* nocapture %e) #1 { entry: - %0 = load i32* %cp, align 4 + %0 = load i32, i32* %cp, align 4 store i32 %a, i32* %e, align 4 %mul = mul nsw i32 %0, %b %sub = sub nsw i32 %a, %mul @@ -366,7 +366,7 @@ entry: define i64 @f_store_mul_64(i64 %a, i64 %b, i64* nocapture readonly %cp, i64* nocapture %e) #1 { entry: - %0 = load i64* %cp, align 8 + %0 = load i64, i64* %cp, align 8 store i64 %a, i64* %e, align 8 %mul = mul nsw i64 %0, %b ret i64 %mul @@ -381,7 +381,7 @@ entry: define i32 @f_store_mul_32(i32 %a, i32 %b, i32* nocapture readonly %cp, i32* nocapture %e) #1 { entry: - %0 = load i32* %cp, align 4 + %0 = load i32, i32* %cp, align 4 store i32 %a, i32* %e, align 4 %mul = mul nsw i32 %0, %b ret i32 %mul @@ -396,7 +396,7 @@ entry: define i64 @f_prefetch_madd_64(i64 %a, i64 %b, i64* nocapture readonly %cp, i64* nocapture %e) #1 { entry: - %0 = load i64* %cp, align 8 + %0 = load i64, i64* %cp, align 8 %1 = bitcast i64* %e to i8* tail call void @llvm.prefetch(i8* %1, i32 0, i32 0, i32 1) %mul = mul nsw i64 %0, %b @@ -415,7 +415,7 @@ declare void @llvm.prefetch(i8* nocapture, i32, i32, i32) #2 define i32 @f_prefetch_madd_32(i32 %a, i32 %b, i32* nocapture readonly %cp, i32* nocapture %e) #1 { entry: - %0 = load i32* %cp, align 4 + %0 = load i32, i32* %cp, align 4 %1 = bitcast i32* %e to i8* tail call void @llvm.prefetch(i8* %1, i32 1, i32 0, i32 1) %mul = mul nsw i32 %0, %b @@ -431,7 +431,7 @@ entry: define i64 @f_prefetch_msub_64(i64 %a, i64 %b, i64* nocapture readonly %cp, i64* nocapture %e) #1 { entry: - %0 = load i64* %cp, align 8 + %0 = load i64, i64* %cp, align 8 %1 = bitcast i64* %e to i8* tail call void @llvm.prefetch(i8* %1, i32 0, i32 1, i32 1) %mul = mul nsw i64 %0, %b @@ -448,7 +448,7 @@ entry: define i32 @f_prefetch_msub_32(i32 %a, i32 %b, i32* nocapture readonly %cp, i32* nocapture %e) #1 { entry: - %0 = load i32* %cp, align 4 + %0 = load i32, i32* %cp, align 4 %1 = bitcast i32* %e to i8* tail call void @llvm.prefetch(i8* %1, i32 1, i32 1, i32 1) %mul = mul nsw i32 %0, %b @@ -464,7 +464,7 @@ entry: define i64 @f_prefetch_mul_64(i64 %a, i64 %b, i64* nocapture readonly %cp, i64* nocapture %e) #1 { entry: - %0 = load i64* %cp, align 8 + %0 = load i64, i64* %cp, align 8 %1 = bitcast i64* %e to i8* tail call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1) %mul = mul nsw i64 %0, %b @@ -479,7 +479,7 @@ entry: define i32 @f_prefetch_mul_32(i32 %a, i32 %b, i32* nocapture readonly %cp, i32* nocapture %e) #1 { entry: - %0 = load i32* %cp, align 4 + %0 = load i32, i32* %cp, align 4 %1 = bitcast i32* %e to i8* tail call void @llvm.prefetch(i8* %1, i32 1, i32 3, i32 1) %mul = mul nsw i32 %0, %b @@ -494,7 +494,7 @@ entry: define i64 @fall_through(i64 %a, i64 %b, i64* nocapture readonly %c) #0 { entry: - %0 = load i64* %c, align 8 + %0 = load i64, i64* %c, align 8 br label %block1 block1: diff --git a/test/CodeGen/AArch64/aarch64-gep-opt.ll b/test/CodeGen/AArch64/aarch64-gep-opt.ll index 811eed9..ce6c8a0 100644 --- a/test/CodeGen/AArch64/aarch64-gep-opt.ll +++ b/test/CodeGen/AArch64/aarch64-gep-opt.ll @@ -14,14 +14,14 @@ target triple = "aarch64-linux-gnueabi" ; Check that when two complex GEPs are used in two basic blocks, LLVM can ; elimilate the common subexpression for the second use. define void @test_GEP_CSE([240 x %struct]* %string, i32* %adj, i32 %lib, i64 %idxprom) { - %liberties = getelementptr [240 x %struct]* %string, i64 1, i64 %idxprom, i32 3 - %1 = load i32* %liberties, align 4 + %liberties = getelementptr [240 x %struct], [240 x %struct]* %string, i64 1, i64 %idxprom, i32 3 + %1 = load i32, i32* %liberties, align 4 %cmp = icmp eq i32 %1, %lib br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry - %origin = getelementptr [240 x %struct]* %string, i64 1, i64 %idxprom, i32 2 - %2 = load i32* %origin, align 4 + %origin = getelementptr [240 x %struct], [240 x %struct]* %string, i64 1, i64 %idxprom, i32 2 + %2 = load i32, i32* %origin, align 4 store i32 %2, i32* %adj, align 4 br label %if.end @@ -50,11 +50,11 @@ if.end: ; preds = %if.then, %entry ; CHECK-UseAA-LABEL: @test_GEP_CSE( ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = bitcast [240 x %struct]* %string to i8* ; CHECK-UseAA: [[IDX:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96 -; CHECK-UseAA: [[PTR1:%[a-zA-Z0-9]+]] = getelementptr i8* [[PTR0]], i64 [[IDX]] -; CHECK-UseAA: getelementptr i8* [[PTR1]], i64 23052 +; CHECK-UseAA: [[PTR1:%[a-zA-Z0-9]+]] = getelementptr i8, i8* [[PTR0]], i64 [[IDX]] +; CHECK-UseAA: getelementptr i8, i8* [[PTR1]], i64 23052 ; CHECK-UseAA: bitcast ; CHECK-UseAA: if.then: -; CHECK-UseAA: getelementptr i8* [[PTR1]], i64 23048 +; CHECK-UseAA: getelementptr i8, i8* [[PTR1]], i64 23048 ; CHECK-UseAA: bitcast %class.my = type { i32, [128 x i32], i32, [256 x %struct.pt]} @@ -65,10 +65,10 @@ if.end: ; preds = %if.then, %entry ; calculation and code gen can generate a better addressing mode for the second ; use. define void @test_GEP_across_BB(%class.my* %this, i64 %idx) { - %1 = getelementptr %class.my* %this, i64 0, i32 3, i64 %idx, i32 1 - %2 = load i32* %1, align 4 - %3 = getelementptr %class.my* %this, i64 0, i32 3, i64 %idx, i32 2 - %4 = load i32* %3, align 4 + %1 = getelementptr %class.my, %class.my* %this, i64 0, i32 3, i64 %idx, i32 1 + %2 = load i32, i32* %1, align 4 + %3 = getelementptr %class.my, %class.my* %this, i64 0, i32 3, i64 %idx, i32 2 + %4 = load i32, i32* %3, align 4 %5 = icmp eq i32 %2, %4 br i1 %5, label %if.true, label %exit @@ -99,12 +99,12 @@ exit: ; CHECK-UseAA-LABEL: test_GEP_across_BB( ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = getelementptr -; CHECK-UseAA: getelementptr i8* [[PTR0]], i64 528 -; CHECK-UseAA: getelementptr i8* [[PTR0]], i64 532 +; CHECK-UseAA: getelementptr i8, i8* [[PTR0]], i64 528 +; CHECK-UseAA: getelementptr i8, i8* [[PTR0]], i64 532 ; CHECK-UseAA: if.true: -; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8* [[PTR0]], i64 532 +; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, i8* [[PTR0]], i64 532 ; CHECK-UseAA: exit: -; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8* [[PTR0]], i64 528 +; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, i8* [[PTR0]], i64 528 %struct.S = type { float, double } @struct_array = global [1024 x %struct.S] zeroinitializer, align 16 @@ -118,7 +118,7 @@ define double* @test-struct_1(i32 %i) { entry: %add = add nsw i32 %i, 5 %idxprom = sext i32 %add to i64 - %p = getelementptr [1024 x %struct.S]* @struct_array, i64 0, i64 %idxprom, i32 1 + %p = getelementptr [1024 x %struct.S], [1024 x %struct.S]* @struct_array, i64 0, i64 %idxprom, i32 1 ret double* %p } ; CHECK-NoAA-LABEL: @test-struct_1( @@ -126,7 +126,7 @@ entry: ; CHECK-NoAA: add i64 %{{[a-zA-Z0-9]+}}, 88 ; CHECK-UseAA-LABEL: @test-struct_1( -; CHECK-UseAA: getelementptr i8* %{{[a-zA-Z0-9]+}}, i64 88 +; CHECK-UseAA: getelementptr i8, i8* %{{[a-zA-Z0-9]+}}, i64 88 %struct3 = type { i64, i32 } %struct2 = type { %struct3, i32 } @@ -140,7 +140,7 @@ entry: define %struct2* @test-struct_2(%struct0* %ptr, i64 %idx) { entry: %arrayidx = add nsw i64 %idx, -2 - %ptr2 = getelementptr %struct0* %ptr, i64 0, i32 3, i64 %arrayidx, i32 1 + %ptr2 = getelementptr %struct0, %struct0* %ptr, i64 0, i32 3, i64 %arrayidx, i32 1 ret %struct2* %ptr2 } ; CHECK-NoAA-LABEL: @test-struct_2( @@ -148,14 +148,14 @@ entry: ; CHECK-NoAA: add i64 %{{[a-zA-Z0-9]+}}, -40 ; CHECK-UseAA-LABEL: @test-struct_2( -; CHECK-UseAA: getelementptr i8* %{{[a-zA-Z0-9]+}}, i64 -40 +; CHECK-UseAA: getelementptr i8, i8* %{{[a-zA-Z0-9]+}}, i64 -40 ; Test that when a index is added from two constant, SeparateConstOffsetFromGEP ; pass does not generate incorrect result. define void @test_const_add([3 x i32]* %in) { %inc = add nsw i32 2, 1 %idxprom = sext i32 %inc to i64 - %arrayidx = getelementptr [3 x i32]* %in, i64 %idxprom, i64 2 + %arrayidx = getelementptr [3 x i32], [3 x i32]* %in, i64 %idxprom, i64 2 store i32 0, i32* %arrayidx, align 4 ret void } diff --git a/test/CodeGen/AArch64/aarch64-smull.ll b/test/CodeGen/AArch64/aarch64-smull.ll index 92582d7..ec0e2de 100644 --- a/test/CodeGen/AArch64/aarch64-smull.ll +++ b/test/CodeGen/AArch64/aarch64-smull.ll @@ -3,8 +3,8 @@ define <8 x i16> @smull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: smull_v8i8_v8i16: ; CHECK: smull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = sext <8 x i8> %tmp1 to <8 x i16> %tmp4 = sext <8 x i8> %tmp2 to <8 x i16> %tmp5 = mul <8 x i16> %tmp3, %tmp4 @@ -14,8 +14,8 @@ define <8 x i16> @smull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @smull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: smull_v4i16_v4i32: ; CHECK: smull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = sext <4 x i16> %tmp1 to <4 x i32> %tmp4 = sext <4 x i16> %tmp2 to <4 x i32> %tmp5 = mul <4 x i32> %tmp3, %tmp4 @@ -25,8 +25,8 @@ define <4 x i32> @smull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @smull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind { ; CHECK-LABEL: smull_v2i32_v2i64: ; CHECK: smull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = sext <2 x i32> %tmp1 to <2 x i64> %tmp4 = sext <2 x i32> %tmp2 to <2 x i64> %tmp5 = mul <2 x i64> %tmp3, %tmp4 @@ -36,8 +36,8 @@ define <2 x i64> @smull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @umull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind { ; CHECK-LABEL: umull_v8i8_v8i16: ; CHECK: umull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = zext <8 x i8> %tmp1 to <8 x i16> %tmp4 = zext <8 x i8> %tmp2 to <8 x i16> %tmp5 = mul <8 x i16> %tmp3, %tmp4 @@ -47,8 +47,8 @@ define <8 x i16> @umull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @umull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; CHECK-LABEL: umull_v4i16_v4i32: ; CHECK: umull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = zext <4 x i16> %tmp1 to <4 x i32> %tmp4 = zext <4 x i16> %tmp2 to <4 x i32> %tmp5 = mul <4 x i32> %tmp3, %tmp4 @@ -58,8 +58,8 @@ define <4 x i32> @umull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @umull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind { ; CHECK-LABEL: umull_v2i32_v2i64: ; CHECK: umull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = zext <2 x i32> %tmp1 to <2 x i64> %tmp4 = zext <2 x i32> %tmp2 to <2 x i64> %tmp5 = mul <2 x i64> %tmp3, %tmp4 @@ -69,9 +69,9 @@ define <2 x i64> @umull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @smlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ; CHECK-LABEL: smlal_v8i8_v8i16: ; CHECK: smlal {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i8>, <8 x i8>* %C %tmp4 = sext <8 x i8> %tmp2 to <8 x i16> %tmp5 = sext <8 x i8> %tmp3 to <8 x i16> %tmp6 = mul <8 x i16> %tmp4, %tmp5 @@ -82,9 +82,9 @@ define <8 x i16> @smlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) no define <4 x i32> @smlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ; CHECK-LABEL: smlal_v4i16_v4i32: ; CHECK: smlal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = sext <4 x i16> %tmp2 to <4 x i32> %tmp5 = sext <4 x i16> %tmp3 to <4 x i32> %tmp6 = mul <4 x i32> %tmp4, %tmp5 @@ -95,9 +95,9 @@ define <4 x i32> @smlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) define <2 x i64> @smlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ; CHECK-LABEL: smlal_v2i32_v2i64: ; CHECK: smlal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = sext <2 x i32> %tmp2 to <2 x i64> %tmp5 = sext <2 x i32> %tmp3 to <2 x i64> %tmp6 = mul <2 x i64> %tmp4, %tmp5 @@ -108,9 +108,9 @@ define <2 x i64> @smlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) define <8 x i16> @umlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ; CHECK-LABEL: umlal_v8i8_v8i16: ; CHECK: umlal {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i8>, <8 x i8>* %C %tmp4 = zext <8 x i8> %tmp2 to <8 x i16> %tmp5 = zext <8 x i8> %tmp3 to <8 x i16> %tmp6 = mul <8 x i16> %tmp4, %tmp5 @@ -121,9 +121,9 @@ define <8 x i16> @umlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) no define <4 x i32> @umlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ; CHECK-LABEL: umlal_v4i16_v4i32: ; CHECK: umlal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = zext <4 x i16> %tmp2 to <4 x i32> %tmp5 = zext <4 x i16> %tmp3 to <4 x i32> %tmp6 = mul <4 x i32> %tmp4, %tmp5 @@ -134,9 +134,9 @@ define <4 x i32> @umlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) define <2 x i64> @umlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ; CHECK-LABEL: umlal_v2i32_v2i64: ; CHECK: umlal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = zext <2 x i32> %tmp2 to <2 x i64> %tmp5 = zext <2 x i32> %tmp3 to <2 x i64> %tmp6 = mul <2 x i64> %tmp4, %tmp5 @@ -147,9 +147,9 @@ define <2 x i64> @umlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) define <8 x i16> @smlsl_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ; CHECK-LABEL: smlsl_v8i8_v8i16: ; CHECK: smlsl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i8>, <8 x i8>* %C %tmp4 = sext <8 x i8> %tmp2 to <8 x i16> %tmp5 = sext <8 x i8> %tmp3 to <8 x i16> %tmp6 = mul <8 x i16> %tmp4, %tmp5 @@ -160,9 +160,9 @@ define <8 x i16> @smlsl_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) no define <4 x i32> @smlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ; CHECK-LABEL: smlsl_v4i16_v4i32: ; CHECK: smlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = sext <4 x i16> %tmp2 to <4 x i32> %tmp5 = sext <4 x i16> %tmp3 to <4 x i32> %tmp6 = mul <4 x i32> %tmp4, %tmp5 @@ -173,9 +173,9 @@ define <4 x i32> @smlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) define <2 x i64> @smlsl_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ; CHECK-LABEL: smlsl_v2i32_v2i64: ; CHECK: smlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = sext <2 x i32> %tmp2 to <2 x i64> %tmp5 = sext <2 x i32> %tmp3 to <2 x i64> %tmp6 = mul <2 x i64> %tmp4, %tmp5 @@ -186,9 +186,9 @@ define <2 x i64> @smlsl_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) define <8 x i16> @umlsl_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ; CHECK-LABEL: umlsl_v8i8_v8i16: ; CHECK: umlsl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i8>* %C + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i8>, <8 x i8>* %C %tmp4 = zext <8 x i8> %tmp2 to <8 x i16> %tmp5 = zext <8 x i8> %tmp3 to <8 x i16> %tmp6 = mul <8 x i16> %tmp4, %tmp5 @@ -199,9 +199,9 @@ define <8 x i16> @umlsl_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) no define <4 x i32> @umlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ; CHECK-LABEL: umlsl_v4i16_v4i32: ; CHECK: umlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i16>, <4 x i16>* %C %tmp4 = zext <4 x i16> %tmp2 to <4 x i32> %tmp5 = zext <4 x i16> %tmp3 to <4 x i32> %tmp6 = mul <4 x i32> %tmp4, %tmp5 @@ -212,9 +212,9 @@ define <4 x i32> @umlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) define <2 x i64> @umlsl_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ; CHECK-LABEL: umlsl_v2i32_v2i64: ; CHECK: umlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i32>, <2 x i32>* %C %tmp4 = zext <2 x i32> %tmp2 to <2 x i64> %tmp5 = zext <2 x i32> %tmp3 to <2 x i64> %tmp6 = mul <2 x i64> %tmp4, %tmp5 diff --git a/test/CodeGen/AArch64/addsub-shifted.ll b/test/CodeGen/AArch64/addsub-shifted.ll index 1d963f4..7c7d654 100644 --- a/test/CodeGen/AArch64/addsub-shifted.ll +++ b/test/CodeGen/AArch64/addsub-shifted.ll @@ -6,63 +6,63 @@ define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) { ; CHECK-LABEL: test_lsl_arith: - %rhs1 = load volatile i32* @var32 + %rhs1 = load volatile i32, i32* @var32 %shift1 = shl i32 %rhs1, 18 %val1 = add i32 %lhs32, %shift1 store volatile i32 %val1, i32* @var32 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #18 - %rhs2 = load volatile i32* @var32 + %rhs2 = load volatile i32, i32* @var32 %shift2 = shl i32 %rhs2, 31 %val2 = add i32 %shift2, %lhs32 store volatile i32 %val2, i32* @var32 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31 - %rhs3 = load volatile i32* @var32 + %rhs3 = load volatile i32, i32* @var32 %shift3 = shl i32 %rhs3, 5 %val3 = sub i32 %lhs32, %shift3 store volatile i32 %val3, i32* @var32 ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #5 ; Subtraction is not commutative! - %rhs4 = load volatile i32* @var32 + %rhs4 = load volatile i32, i32* @var32 %shift4 = shl i32 %rhs4, 19 %val4 = sub i32 %shift4, %lhs32 store volatile i32 %val4, i32* @var32 ; CHECK-NOT: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #19 - %lhs4a = load volatile i32* @var32 + %lhs4a = load volatile i32, i32* @var32 %shift4a = shl i32 %lhs4a, 15 %val4a = sub i32 0, %shift4a store volatile i32 %val4a, i32* @var32 ; CHECK: neg {{w[0-9]+}}, {{w[0-9]+}}, lsl #15 - %rhs5 = load volatile i64* @var64 + %rhs5 = load volatile i64, i64* @var64 %shift5 = shl i64 %rhs5, 18 %val5 = add i64 %lhs64, %shift5 store volatile i64 %val5, i64* @var64 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #18 - %rhs6 = load volatile i64* @var64 + %rhs6 = load volatile i64, i64* @var64 %shift6 = shl i64 %rhs6, 31 %val6 = add i64 %shift6, %lhs64 store volatile i64 %val6, i64* @var64 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #31 - %rhs7 = load volatile i64* @var64 + %rhs7 = load volatile i64, i64* @var64 %shift7 = shl i64 %rhs7, 5 %val7 = sub i64 %lhs64, %shift7 store volatile i64 %val7, i64* @var64 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #5 ; Subtraction is not commutative! - %rhs8 = load volatile i64* @var64 + %rhs8 = load volatile i64, i64* @var64 %shift8 = shl i64 %rhs8, 19 %val8 = sub i64 %shift8, %lhs64 store volatile i64 %val8, i64* @var64 ; CHECK-NOT: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #19 - %lhs8a = load volatile i64* @var64 + %lhs8a = load volatile i64, i64* @var64 %shift8a = shl i64 %lhs8a, 60 %val8a = sub i64 0, %shift8a store volatile i64 %val8a, i64* @var64 diff --git a/test/CodeGen/AArch64/addsub.ll b/test/CodeGen/AArch64/addsub.ll index b85fdbb..09b9f62 100644 --- a/test/CodeGen/AArch64/addsub.ll +++ b/test/CodeGen/AArch64/addsub.ll @@ -12,12 +12,12 @@ define void @add_small() { ; CHECK-LABEL: add_small: ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #4095 - %val32 = load i32* @var_i32 + %val32 = load i32, i32* @var_i32 %newval32 = add i32 %val32, 4095 store i32 %newval32, i32* @var_i32 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, #52 - %val64 = load i64* @var_i64 + %val64 = load i64, i64* @var_i64 %newval64 = add i64 %val64, 52 store i64 %newval64, i64* @var_i64 @@ -29,12 +29,12 @@ define void @add_med() { ; CHECK-LABEL: add_med: ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{#3567, lsl #12|#14610432}} - %val32 = load i32* @var_i32 + %val32 = load i32, i32* @var_i32 %newval32 = add i32 %val32, 14610432 ; =0xdef000 store i32 %newval32, i32* @var_i32 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{#4095, lsl #12|#16773120}} - %val64 = load i64* @var_i64 + %val64 = load i64, i64* @var_i64 %newval64 = add i64 %val64, 16773120 ; =0xfff000 store i64 %newval64, i64* @var_i64 @@ -46,12 +46,12 @@ define void @sub_small() { ; CHECK-LABEL: sub_small: ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4095 - %val32 = load i32* @var_i32 + %val32 = load i32, i32* @var_i32 %newval32 = sub i32 %val32, 4095 store i32 %newval32, i32* @var_i32 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, #52 - %val64 = load i64* @var_i64 + %val64 = load i64, i64* @var_i64 %newval64 = sub i64 %val64, 52 store i64 %newval64, i64* @var_i64 @@ -63,12 +63,12 @@ define void @sub_med() { ; CHECK-LABEL: sub_med: ; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{#3567, lsl #12|#14610432}} - %val32 = load i32* @var_i32 + %val32 = load i32, i32* @var_i32 %newval32 = sub i32 %val32, 14610432 ; =0xdef000 store i32 %newval32, i32* @var_i32 ; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{#4095, lsl #12|#16773120}} - %val64 = load i64* @var_i64 + %val64 = load i64, i64* @var_i64 %newval64 = sub i64 %val64, 16773120 ; =0xfff000 store i64 %newval64, i64* @var_i64 @@ -77,7 +77,7 @@ define void @sub_med() { define void @testing() { ; CHECK-LABEL: testing: - %val = load i32* @var_i32 + %val = load i32, i32* @var_i32 ; CHECK: cmp {{w[0-9]+}}, #4095 ; CHECK: b.ne [[RET:.?LBB[0-9]+_[0-9]+]] diff --git a/test/CodeGen/AArch64/addsub_ext.ll b/test/CodeGen/AArch64/addsub_ext.ll index ceea8a0..f0c7572 100644 --- a/test/CodeGen/AArch64/addsub_ext.ll +++ b/test/CodeGen/AArch64/addsub_ext.ll @@ -7,9 +7,9 @@ define void @addsub_i8rhs() minsize { ; CHECK-LABEL: addsub_i8rhs: - %val8_tmp = load i8* @var8 - %lhs32 = load i32* @var32 - %lhs64 = load i64* @var64 + %val8_tmp = load i8, i8* @var8 + %lhs32 = load i32, i32* @var32 + %lhs64 = load i64, i64* @var64 ; Need this to prevent extension upon load and give a vanilla i8 operand. %val8 = add i8 %val8_tmp, 123 @@ -82,9 +82,9 @@ end: define void @addsub_i16rhs() minsize { ; CHECK-LABEL: addsub_i16rhs: - %val16_tmp = load i16* @var16 - %lhs32 = load i32* @var32 - %lhs64 = load i64* @var64 + %val16_tmp = load i16, i16* @var16 + %lhs32 = load i32, i32* @var32 + %lhs64 = load i64, i64* @var64 ; Need this to prevent extension upon load and give a vanilla i16 operand. %val16 = add i16 %val16_tmp, 123 @@ -160,8 +160,8 @@ end: ; in the face of "add/sub (shifted register)" so I don't intend to. define void @addsub_i32rhs() minsize { ; CHECK-LABEL: addsub_i32rhs: - %val32_tmp = load i32* @var32 - %lhs64 = load i64* @var64 + %val32_tmp = load i32, i32* @var32 + %lhs64 = load i64, i64* @var64 %val32 = add i32 %val32_tmp, 123 diff --git a/test/CodeGen/AArch64/alloca.ll b/test/CodeGen/AArch64/alloca.ll index f93efbc..5b2278c 100644 --- a/test/CodeGen/AArch64/alloca.ll +++ b/test/CodeGen/AArch64/alloca.ll @@ -51,7 +51,7 @@ define i64 @test_alloca_with_local(i64 %n) { call void @use_addr_loc(i8* %buf, i64* %loc) ; CHECK: bl use_addr - %val = load i64* %loc + %val = load i64, i64* %loc ; CHECK: ldur x0, [x29, #-[[LOC_FROM_FP]]] diff --git a/test/CodeGen/AArch64/and-mask-removal.ll b/test/CodeGen/AArch64/and-mask-removal.ll index f803b85..8291516 100644 --- a/test/CodeGen/AArch64/and-mask-removal.ll +++ b/test/CodeGen/AArch64/and-mask-removal.ll @@ -8,15 +8,15 @@ define void @new_position(i32 %pos) { entry: %idxprom = sext i32 %pos to i64 - %arrayidx = getelementptr inbounds [400 x i8]* @board, i64 0, i64 %idxprom - %tmp = load i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds [400 x i8], [400 x i8]* @board, i64 0, i64 %idxprom + %tmp = load i8, i8* %arrayidx, align 1 %.off = add i8 %tmp, -1 %switch = icmp ult i8 %.off, 2 br i1 %switch, label %if.then, label %if.end if.then: ; preds = %entry - %tmp1 = load i32* @next_string, align 4 - %arrayidx8 = getelementptr inbounds [400 x i32]* @string_number, i64 0, i64 %idxprom + %tmp1 = load i32, i32* @next_string, align 4 + %arrayidx8 = getelementptr inbounds [400 x i32], [400 x i32]* @string_number, i64 0, i64 %idxprom store i32 %tmp1, i32* %arrayidx8, align 4 br label %if.end diff --git a/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll b/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll index 8b88c0b..330fccc 100644 --- a/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll +++ b/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll @@ -11,7 +11,7 @@ if.then24: ; preds = %entry unreachable if.else295: ; preds = %entry - call void @llvm.dbg.declare(metadata i32* %do_tab_convert, metadata !16, metadata !{!"0x102"}), !dbg !18 + call void @llvm.dbg.declare(metadata i32* %do_tab_convert, metadata !16, metadata !MDExpression()), !dbg !18 store i32 0, i32* %do_tab_convert, align 4, !dbg !19 unreachable } @@ -21,25 +21,25 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone !llvm.dbg.gv = !{!0} !llvm.dbg.sp = !{!1, !7, !10, !11, !12} -!0 = !{!"0x34\00vsplive\00vsplive\00\00617\001\001", !1, !2, !6, null, null} ; [ DW_TAG_variable ] -!1 = !{!"0x2e\00drt_vsprintf\00drt_vsprintf\00\00616\000\001\000\006\00256\000\000", !20, !2, !4, null, null, null, null, null} ; [ DW_TAG_subprogram ] -!2 = !{!"0x29", !20} ; [ DW_TAG_file_type ] -!3 = !{!"0x11\0012\00clang version 3.0 (http://llvm.org/git/clang.git git:/git/puzzlebox/clang.git/ c4d1aea01c4444eb81bdbf391f1be309127c3cf1)\001\00\000\00\000", !20, !21, !21, null, null, null} ; [ DW_TAG_compile_unit ] -!4 = !{!"0x15\00\000\000\000\000\000\000", !20, !2, null, !5, i32 0} ; [ DW_TAG_subroutine_type ] +!0 = !MDGlobalVariable(name: "vsplive", line: 617, isLocal: true, isDefinition: true, scope: !1, file: !2, type: !6) +!1 = !MDSubprogram(name: "drt_vsprintf", line: 616, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !20, scope: !2, type: !4) +!2 = !MDFile(filename: "print.i", directory: "/Volumes/Ebi/echeng/radars/r9146594") +!3 = !MDCompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (http://llvm.org/git/clang.git git:/git/puzzlebox/clang.git/ c4d1aea01c4444eb81bdbf391f1be309127c3cf1)", isOptimized: true, emissionKind: 0, file: !20, enums: !21, retainedTypes: !21) +!4 = !MDSubroutineType(types: !5) !5 = !{!6} -!6 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !3} ; [ DW_TAG_base_type ] -!7 = !{!"0x2e\00putc_mem\00putc_mem\00\0030\001\001\000\006\00256\000\000", !20, !2, !8, null, null, null, null, null} ; [ DW_TAG_subprogram ] -!8 = !{!"0x15\00\000\000\000\000\000\000", !20, !2, null, !9, i32 0} ; [ DW_TAG_subroutine_type ] +!6 = !MDBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!7 = !MDSubprogram(name: "putc_mem", line: 30, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !20, scope: !2, type: !8) +!8 = !MDSubroutineType(types: !9) !9 = !{null} -!10 = !{!"0x2e\00print_double\00print_double\00\00203\001\001\000\006\00256\000\000", !20, !2, !4, null, null, null, null, null} ; [ DW_TAG_subprogram ] -!11 = !{!"0x2e\00print_number\00print_number\00\0075\001\001\000\006\00256\000\000", !20, !2, !4, i32 0, null, null, null, null} ; [ DW_TAG_subprogram ] -!12 = !{!"0x2e\00get_flags\00get_flags\00\00508\001\001\000\006\00256\000\000", !20, !2, !8, null, null, null, null, null} ; [ DW_TAG_subprogram ] +!10 = !MDSubprogram(name: "print_double", line: 203, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !20, scope: !2, type: !4) +!11 = !MDSubprogram(name: "print_number", line: 75, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !20, scope: !2, type: !4) +!12 = !MDSubprogram(name: "get_flags", line: 508, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !20, scope: !2, type: !8) !13 = !MDLocation(line: 653, column: 5, scope: !14) -!14 = !{!"0xb\00652\0035\002", !20, !15} ; [ DW_TAG_lexical_block ] -!15 = !{!"0xb\00616\001\000", !20, !1} ; [ DW_TAG_lexical_block ] -!16 = !{!"0x100\00do_tab_convert\00853\000", !17, !2, !6} ; [ DW_TAG_auto_variable ] -!17 = !{!"0xb\00850\0012\0033", !20, !14} ; [ DW_TAG_lexical_block ] +!14 = distinct !MDLexicalBlock(line: 652, column: 35, file: !20, scope: !15) +!15 = distinct !MDLexicalBlock(line: 616, column: 1, file: !20, scope: !1) +!16 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "do_tab_convert", line: 853, scope: !17, file: !2, type: !6) +!17 = distinct !MDLexicalBlock(line: 850, column: 12, file: !20, scope: !14) !18 = !MDLocation(line: 853, column: 11, scope: !17) !19 = !MDLocation(line: 853, column: 29, scope: !17) -!20 = !{!"print.i", !"/Volumes/Ebi/echeng/radars/r9146594"} +!20 = !MDFile(filename: "print.i", directory: "/Volumes/Ebi/echeng/radars/r9146594") !21 = !{i32 0} diff --git a/test/CodeGen/AArch64/arm64-2011-03-21-Unaligned-Frame-Index.ll b/test/CodeGen/AArch64/arm64-2011-03-21-Unaligned-Frame-Index.ll index 6f0ec34..491433c 100644 --- a/test/CodeGen/AArch64/arm64-2011-03-21-Unaligned-Frame-Index.ll +++ b/test/CodeGen/AArch64/arm64-2011-03-21-Unaligned-Frame-Index.ll @@ -5,7 +5,7 @@ define void @foo(i64 %val) { ; instruction that can handle that. ; CHECK: stur x0, [sp, #20] %a = alloca [49 x i32], align 4 - %p32 = getelementptr inbounds [49 x i32]* %a, i64 0, i64 2 + %p32 = getelementptr inbounds [49 x i32], [49 x i32]* %a, i64 0, i64 2 %p = bitcast i32* %p32 to i64* store i64 %val, i64* %p, align 8 ret void diff --git a/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll b/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll index 88232fc..e2c39e0 100644 --- a/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll +++ b/test/CodeGen/AArch64/arm64-2011-04-21-CPSRBug.ll @@ -8,7 +8,7 @@ entry: %cmp = icmp eq i32* null, undef %frombool = zext i1 %cmp to i8 store i8 %frombool, i8* undef, align 1 - %tmp4 = load i8* undef, align 1 + %tmp4 = load i8, i8* undef, align 1 %tobool = trunc i8 %tmp4 to i1 br i1 %tobool, label %land.lhs.true, label %if.end diff --git a/test/CodeGen/AArch64/arm64-2011-10-18-LdStOptBug.ll b/test/CodeGen/AArch64/arm64-2011-10-18-LdStOptBug.ll index a83f164..b69cd24 100644 --- a/test/CodeGen/AArch64/arm64-2011-10-18-LdStOptBug.ll +++ b/test/CodeGen/AArch64/arm64-2011-10-18-LdStOptBug.ll @@ -19,7 +19,7 @@ for.body: %0 = shl nsw i64 %indvars.iv, 12 %add = add nsw i64 %0, 34628173824 %1 = inttoptr i64 %add to i32* - %2 = load volatile i32* %1, align 4096 + %2 = load volatile i32, i32* %1, align 4096 store volatile i32 %2, i32* @test_data, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 diff --git a/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll b/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll index d47dbb2..8d0b1b6 100644 --- a/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll +++ b/test/CodeGen/AArch64/arm64-2012-01-11-ComparisonDAGCrash.ll @@ -13,7 +13,7 @@ lor.lhs.false: br i1 undef, label %return, label %if.end if.end: - %tmp.i = load i64* undef, align 8 + %tmp.i = load i64, i64* undef, align 8 %and.i.i.i = and i64 %tmp.i, -16 br i1 %IsArrow, label %if.else_crit_edge, label %if.end32 diff --git a/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll b/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll index b5b1b70..ef8d6f3 100644 --- a/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll +++ b/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll @@ -15,23 +15,23 @@ define hidden %struct.CGRect @t(%0* nocapture %self, i8* nocapture %_cmd) nounwi entry: ; CHECK-LABEL: t: ; CHECK: ldp d{{[0-9]+}}, d{{[0-9]+}} - %ivar = load i64* @"OBJC_IVAR_$_UIScreen._bounds", align 8, !invariant.load !4 + %ivar = load i64, i64* @"OBJC_IVAR_$_UIScreen._bounds", align 8, !invariant.load !4 %0 = bitcast %0* %self to i8* - %add.ptr = getelementptr inbounds i8* %0, i64 %ivar + %add.ptr = getelementptr inbounds i8, i8* %0, i64 %ivar %add.ptr10.0 = bitcast i8* %add.ptr to double* - %tmp11 = load double* %add.ptr10.0, align 8 + %tmp11 = load double, double* %add.ptr10.0, align 8 %add.ptr.sum = add i64 %ivar, 8 - %add.ptr10.1 = getelementptr inbounds i8* %0, i64 %add.ptr.sum + %add.ptr10.1 = getelementptr inbounds i8, i8* %0, i64 %add.ptr.sum %1 = bitcast i8* %add.ptr10.1 to double* - %tmp12 = load double* %1, align 8 + %tmp12 = load double, double* %1, align 8 %add.ptr.sum17 = add i64 %ivar, 16 - %add.ptr4.1 = getelementptr inbounds i8* %0, i64 %add.ptr.sum17 + %add.ptr4.1 = getelementptr inbounds i8, i8* %0, i64 %add.ptr.sum17 %add.ptr4.1.0 = bitcast i8* %add.ptr4.1 to double* - %tmp = load double* %add.ptr4.1.0, align 8 + %tmp = load double, double* %add.ptr4.1.0, align 8 %add.ptr4.1.sum = add i64 %ivar, 24 - %add.ptr4.1.1 = getelementptr inbounds i8* %0, i64 %add.ptr4.1.sum + %add.ptr4.1.1 = getelementptr inbounds i8, i8* %0, i64 %add.ptr4.1.sum %2 = bitcast i8* %add.ptr4.1.1 to double* - %tmp5 = load double* %2, align 8 + %tmp5 = load double, double* %2, align 8 %insert14 = insertvalue %struct.CGPoint undef, double %tmp11, 0 %insert16 = insertvalue %struct.CGPoint %insert14, double %tmp12, 1 %insert = insertvalue %struct.CGRect undef, %struct.CGPoint %insert16, 0 diff --git a/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll b/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll index 4db1f59..41e22e9 100644 --- a/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll +++ b/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll @@ -13,14 +13,14 @@ define void @testDouble(double %d) ssp { entry: %d.addr = alloca double, align 8 store double %d, double* %d.addr, align 8 - %0 = load double* %d.addr, align 8 - %1 = load double* %d.addr, align 8 + %0 = load double, double* %d.addr, align 8 + %1 = load double, double* %d.addr, align 8 %conv = fptoui double %1 to i64 - %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), double %0, i64 %conv) - %2 = load double* %d.addr, align 8 - %3 = load double* %d.addr, align 8 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), double %0, i64 %conv) + %2 = load double, double* %d.addr, align 8 + %3 = load double, double* %d.addr, align 8 %conv1 = fptoui double %3 to i32 - %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str1, i32 0, i32 0), double %2, i32 %conv1) + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str1, i32 0, i32 0), double %2, i32 %conv1) ret void } @@ -33,16 +33,16 @@ define void @testFloat(float %f) ssp { entry: %f.addr = alloca float, align 4 store float %f, float* %f.addr, align 4 - %0 = load float* %f.addr, align 4 + %0 = load float, float* %f.addr, align 4 %conv = fpext float %0 to double - %1 = load float* %f.addr, align 4 + %1 = load float, float* %f.addr, align 4 %conv1 = fptoui float %1 to i64 - %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str2, i32 0, i32 0), double %conv, i64 %conv1) - %2 = load float* %f.addr, align 4 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str2, i32 0, i32 0), double %conv, i64 %conv1) + %2 = load float, float* %f.addr, align 4 %conv2 = fpext float %2 to double - %3 = load float* %f.addr, align 4 + %3 = load float, float* %f.addr, align 4 %conv3 = fptoui float %3 to i32 - %call4 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8]* @.str3, i32 0, i32 0), double %conv2, i32 %conv3) + %call4 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str3, i32 0, i32 0), double %conv2, i32 %conv3) ret void } diff --git a/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll b/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll index 55ecfb5..997431b 100644 --- a/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll +++ b/test/CodeGen/AArch64/arm64-2012-07-11-InstrEmitterBug.ll @@ -44,7 +44,7 @@ cond.true43: ; preds = %for.body14 unreachable cond.false45: ; preds = %for.body14 - %add.ptr = getelementptr inbounds i8* %path, i64 %conv30 + %add.ptr = getelementptr inbounds i8, i8* %path, i64 %conv30 unreachable if.end56: ; preds = %for.cond10, %entry diff --git a/test/CodeGen/AArch64/arm64-abi-varargs.ll b/test/CodeGen/AArch64/arm64-abi-varargs.ll index 92db392..f95fec6 100644 --- a/test/CodeGen/AArch64/arm64-abi-varargs.ll +++ b/test/CodeGen/AArch64/arm64-abi-varargs.ll @@ -82,18 +82,18 @@ define i32 @main() nounwind ssp { store i32 10, i32* %a10, align 4 store i32 11, i32* %a11, align 4 store i32 12, i32* %a12, align 4 - %1 = load i32* %a1, align 4 - %2 = load i32* %a2, align 4 - %3 = load i32* %a3, align 4 - %4 = load i32* %a4, align 4 - %5 = load i32* %a5, align 4 - %6 = load i32* %a6, align 4 - %7 = load i32* %a7, align 4 - %8 = load i32* %a8, align 4 - %9 = load i32* %a9, align 4 - %10 = load i32* %a10, align 4 - %11 = load i32* %a11, align 4 - %12 = load i32* %a12, align 4 + %1 = load i32, i32* %a1, align 4 + %2 = load i32, i32* %a2, align 4 + %3 = load i32, i32* %a3, align 4 + %4 = load i32, i32* %a4, align 4 + %5 = load i32, i32* %a5, align 4 + %6 = load i32, i32* %a6, align 4 + %7 = load i32, i32* %a7, align 4 + %8 = load i32, i32* %a8, align 4 + %9 = load i32, i32* %a9, align 4 + %10 = load i32, i32* %a10, align 4 + %11 = load i32, i32* %a11, align 4 + %12 = load i32, i32* %a12, align 4 call void (i32, i32, i32, i32, i32, i32, i32, i32, i32, ...)* @fn9(i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12) ret i32 0 } @@ -131,9 +131,9 @@ entry: %y.addr = alloca <4 x i32>, align 16 store i32 %x, i32* %x.addr, align 4 store <4 x i32> %y, <4 x i32>* %y.addr, align 16 - %0 = load i32* %x.addr, align 4 - %1 = load <4 x i32>* %y.addr, align 16 - call void (i8*, ...)* @foo(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 %0, <4 x i32> %1) + %0 = load i32, i32* %x.addr, align 4 + %1 = load <4 x i32>, <4 x i32>* %y.addr, align 16 + call void (i8*, ...)* @foo(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %0, <4 x i32> %1) ret void } @@ -158,12 +158,12 @@ entry: call void @llvm.va_start(i8* %args1) %0 = va_arg i8** %args, i32 store i32 %0, i32* %vc, align 4 - %ap.cur = load i8** %args - %1 = getelementptr i8* %ap.cur, i32 15 + %ap.cur = load i8*, i8** %args + %1 = getelementptr i8, i8* %ap.cur, i32 15 %2 = ptrtoint i8* %1 to i64 %3 = and i64 %2, -16 %ap.align = inttoptr i64 %3 to i8* - %ap.next = getelementptr i8* %ap.align, i32 16 + %ap.next = getelementptr i8, i8* %ap.align, i32 16 store i8* %ap.next, i8** %args %4 = bitcast i8* %ap.align to %struct.s41* %5 = bitcast %struct.s41* %vs to i8* @@ -183,9 +183,9 @@ entry: store i32 %x, i32* %x.addr, align 4 %0 = bitcast %struct.s41* %s41 to i128* store i128 %s41.coerce, i128* %0, align 1 - %1 = load i32* %x.addr, align 4 + %1 = load i32, i32* %x.addr, align 4 %2 = bitcast %struct.s41* %s41 to i128* - %3 = load i128* %2, align 1 - call void (i8*, ...)* @foo2(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i32 %1, i128 %3) + %3 = load i128, i128* %2, align 1 + call void (i8*, ...)* @foo2(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %1, i128 %3) ret void } diff --git a/test/CodeGen/AArch64/arm64-abi.ll b/test/CodeGen/AArch64/arm64-abi.ll index 8a6b64d..36a6822 100644 --- a/test/CodeGen/AArch64/arm64-abi.ll +++ b/test/CodeGen/AArch64/arm64-abi.ll @@ -79,7 +79,7 @@ entry: ; FAST: sub sp, sp ; FAST: mov x[[ADDR:[0-9]+]], sp ; FAST: str [[REG_1:q[0-9]+]], [x[[ADDR]], #16] - %0 = load <4 x i32>* %in, align 16 + %0 = load <4 x i32>, <4 x i32>* %in, align 16 %call = tail call double @args_vec_4i(double 3.000000e+00, <4 x i32> %0, <4 x i32> %0, <4 x i32> %0, <4 x i32> %0, <4 x i32> %0, <4 x i32> %0, <4 x i32> %0, double 3.000000e+00, <4 x i32> %0, i8 signext 3) ret double %call } @@ -133,7 +133,7 @@ entry: ; FAST: sub sp, sp, #32 ; FAST: mov x[[ADDR:[0-9]+]], sp ; FAST: str [[REG_1:d[0-9]+]], [x[[ADDR]], #8] - %0 = load <2 x i32>* %in, align 8 + %0 = load <2 x i32>, <2 x i32>* %in, align 8 %call = tail call double @args_vec_2i(double 3.000000e+00, <2 x i32> %0, <2 x i32> %0, <2 x i32> %0, <2 x i32> %0, <2 x i32> %0, <2 x i32> %0, <2 x i32> %0, float 3.000000e+00, <2 x i32> %0, i8 signext 3) @@ -148,7 +148,7 @@ entry: ; CHECK: str [[REG_1:d[0-9]+]], [sp, #8] ; CHECK: str [[REG_2:w[0-9]+]], [sp] ; CHECK: orr w0, wzr, #0x3 - %0 = load double* %in, align 8 + %0 = load double, double* %in, align 8 %call = tail call double @args_f64(double 3.000000e+00, double %0, double %0, double %0, double %0, double %0, double %0, double %0, float 3.000000e+00, double %0, i8 signext 3) @@ -163,7 +163,7 @@ entry: ; CHECK: strb [[REG_3:w[0-9]+]], [sp, #16] ; CHECK: str [[REG_1:x[0-9]+]], [sp, #8] ; CHECK: str [[REG_2:w[0-9]+]], [sp] - %0 = load i64* %in, align 8 + %0 = load i64, i64* %in, align 8 %call = tail call i64 @args_i64(i64 3, i64 %0, i64 %0, i64 %0, i64 %0, i64 %0, i64 %0, i64 %0, i32 3, i64 %0, i8 signext 3) ret i64 %call @@ -177,7 +177,7 @@ entry: ; CHECK: strb [[REG_2:w[0-9]+]], [sp, #8] ; CHECK: str [[REG_1:s[0-9]+]], [sp, #4] ; CHECK: strh [[REG_3:w[0-9]+]], [sp] - %0 = load float* %in, align 4 + %0 = load float, float* %in, align 4 %call = tail call i32 @args_f32(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, i16 signext 3, float %0, @@ -194,7 +194,7 @@ entry: ; CHECK: strb [[REG_2:w[0-9]+]], [sp, #8] ; CHECK: str [[REG_1:w[0-9]+]], [sp, #4] ; CHECK: strh [[REG_3:w[0-9]+]], [sp] - %0 = load i32* %in, align 4 + %0 = load i32, i32* %in, align 4 %call = tail call i32 @args_i32(i32 3, i32 %0, i32 %0, i32 %0, i32 %0, i32 %0, i32 %0, i32 %0, i16 signext 3, i32 %0, i8 signext 4) ret i32 %call diff --git a/test/CodeGen/AArch64/arm64-abi_align.ll b/test/CodeGen/AArch64/arm64-abi_align.ll index e03d7fa..1c1b58b 100644 --- a/test/CodeGen/AArch64/arm64-abi_align.ll +++ b/test/CodeGen/AArch64/arm64-abi_align.ll @@ -59,8 +59,8 @@ entry: ; CHECK-LABEL: caller38 ; CHECK: ldr x1, ; CHECK: ldr x2, - %0 = load i64* bitcast (%struct.s38* @g38 to i64*), align 4 - %1 = load i64* bitcast (%struct.s38* @g38_2 to i64*), align 4 + %0 = load i64, i64* bitcast (%struct.s38* @g38 to i64*), align 4 + %1 = load i64, i64* bitcast (%struct.s38* @g38_2 to i64*), align 4 %call = tail call i32 @f38(i32 3, i64 %0, i64 %1) #5 ret i32 %call } @@ -76,8 +76,8 @@ entry: ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8] ; CHECK: movz w[[C:[0-9]+]], #0x9 ; CHECK: str w[[C]], [sp] - %0 = load i64* bitcast (%struct.s38* @g38 to i64*), align 4 - %1 = load i64* bitcast (%struct.s38* @g38_2 to i64*), align 4 + %0 = load i64, i64* bitcast (%struct.s38* @g38 to i64*), align 4 + %1 = load i64, i64* bitcast (%struct.s38* @g38_2 to i64*), align 4 %call = tail call i32 @f38_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i64 %0, i64 %1) #5 ret i32 %call @@ -112,8 +112,8 @@ entry: ; CHECK-LABEL: caller39 ; CHECK: ldp x1, x2, ; CHECK: ldp x3, x4, - %0 = load i128* bitcast (%struct.s39* @g39 to i128*), align 16 - %1 = load i128* bitcast (%struct.s39* @g39_2 to i128*), align 16 + %0 = load i128, i128* bitcast (%struct.s39* @g39 to i128*), align 16 + %1 = load i128, i128* bitcast (%struct.s39* @g39_2 to i128*), align 16 %call = tail call i32 @f39(i32 3, i128 %0, i128 %1) #5 ret i32 %call } @@ -130,8 +130,8 @@ entry: ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16] ; CHECK: movz w[[C:[0-9]+]], #0x9 ; CHECK: str w[[C]], [sp] - %0 = load i128* bitcast (%struct.s39* @g39 to i128*), align 16 - %1 = load i128* bitcast (%struct.s39* @g39_2 to i128*), align 16 + %0 = load i128, i128* bitcast (%struct.s39* @g39 to i128*), align 16 + %1 = load i128, i128* bitcast (%struct.s39* @g39_2 to i128*), align 16 %call = tail call i32 @f39_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i128 %0, i128 %1) #5 ret i32 %call @@ -168,8 +168,8 @@ entry: ; CHECK-LABEL: caller40 ; CHECK: ldp x1, x2, ; CHECK: ldp x3, x4, - %0 = load [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 4 - %1 = load [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 4 + %0 = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 4 + %1 = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 4 %call = tail call i32 @f40(i32 3, [2 x i64] %0, [2 x i64] %1) #5 ret i32 %call } @@ -186,8 +186,8 @@ entry: ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8] ; CHECK: movz w[[C:[0-9]+]], #0x9 ; CHECK: str w[[C]], [sp] - %0 = load [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 4 - %1 = load [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 4 + %0 = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 4 + %1 = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 4 %call = tail call i32 @f40_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, [2 x i64] %0, [2 x i64] %1) #5 ret i32 %call @@ -222,8 +222,8 @@ entry: ; CHECK-LABEL: caller41 ; CHECK: ldp x1, x2, ; CHECK: ldp x3, x4, - %0 = load i128* bitcast (%struct.s41* @g41 to i128*), align 16 - %1 = load i128* bitcast (%struct.s41* @g41_2 to i128*), align 16 + %0 = load i128, i128* bitcast (%struct.s41* @g41 to i128*), align 16 + %1 = load i128, i128* bitcast (%struct.s41* @g41_2 to i128*), align 16 %call = tail call i32 @f41(i32 3, i128 %0, i128 %1) #5 ret i32 %call } @@ -240,8 +240,8 @@ entry: ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16] ; CHECK: movz w[[C:[0-9]+]], #0x9 ; CHECK: str w[[C]], [sp] - %0 = load i128* bitcast (%struct.s41* @g41 to i128*), align 16 - %1 = load i128* bitcast (%struct.s41* @g41_2 to i128*), align 16 + %0 = load i128, i128* bitcast (%struct.s41* @g41 to i128*), align 16 + %1 = load i128, i128* bitcast (%struct.s41* @g41_2 to i128*), align 16 %call = tail call i32 @f41_stack(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i128 %0, i128 %1) #5 ret i32 %call @@ -260,15 +260,15 @@ entry: ; FAST: ldr w[[B:[0-9]+]], [x2] ; FAST: add w[[C:[0-9]+]], w[[A]], w0 ; FAST: add {{w[0-9]+}}, w[[C]], w[[B]] - %i1 = getelementptr inbounds %struct.s42* %s1, i64 0, i32 0 - %0 = load i32* %i1, align 4, !tbaa !0 - %i2 = getelementptr inbounds %struct.s42* %s2, i64 0, i32 0 - %1 = load i32* %i2, align 4, !tbaa !0 - %s = getelementptr inbounds %struct.s42* %s1, i64 0, i32 1 - %2 = load i16* %s, align 2, !tbaa !3 + %i1 = getelementptr inbounds %struct.s42, %struct.s42* %s1, i64 0, i32 0 + %0 = load i32, i32* %i1, align 4, !tbaa !0 + %i2 = getelementptr inbounds %struct.s42, %struct.s42* %s2, i64 0, i32 0 + %1 = load i32, i32* %i2, align 4, !tbaa !0 + %s = getelementptr inbounds %struct.s42, %struct.s42* %s1, i64 0, i32 1 + %2 = load i16, i16* %s, align 2, !tbaa !3 %conv = sext i16 %2 to i32 - %s5 = getelementptr inbounds %struct.s42* %s2, i64 0, i32 1 - %3 = load i16* %s5, align 2, !tbaa !3 + %s5 = getelementptr inbounds %struct.s42, %struct.s42* %s2, i64 0, i32 1 + %3 = load i16, i16* %s5, align 2, !tbaa !3 %conv6 = sext i16 %3 to i32 %add = add i32 %0, %i %add3 = add i32 %add, %1 @@ -369,15 +369,15 @@ entry: ; FAST: ldr w[[B:[0-9]+]], [x2] ; FAST: add w[[C:[0-9]+]], w[[A]], w0 ; FAST: add {{w[0-9]+}}, w[[C]], w[[B]] - %i1 = getelementptr inbounds %struct.s43* %s1, i64 0, i32 0 - %0 = load i32* %i1, align 4, !tbaa !0 - %i2 = getelementptr inbounds %struct.s43* %s2, i64 0, i32 0 - %1 = load i32* %i2, align 4, !tbaa !0 - %s = getelementptr inbounds %struct.s43* %s1, i64 0, i32 1 - %2 = load i16* %s, align 2, !tbaa !3 + %i1 = getelementptr inbounds %struct.s43, %struct.s43* %s1, i64 0, i32 0 + %0 = load i32, i32* %i1, align 4, !tbaa !0 + %i2 = getelementptr inbounds %struct.s43, %struct.s43* %s2, i64 0, i32 0 + %1 = load i32, i32* %i2, align 4, !tbaa !0 + %s = getelementptr inbounds %struct.s43, %struct.s43* %s1, i64 0, i32 1 + %2 = load i16, i16* %s, align 2, !tbaa !3 %conv = sext i16 %2 to i32 - %s5 = getelementptr inbounds %struct.s43* %s2, i64 0, i32 1 - %3 = load i16* %s5, align 2, !tbaa !3 + %s5 = getelementptr inbounds %struct.s43, %struct.s43* %s2, i64 0, i32 1 + %3 = load i16, i16* %s5, align 2, !tbaa !3 %conv6 = sext i16 %3 to i32 %add = add i32 %0, %i %add3 = add i32 %add, %1 @@ -493,7 +493,7 @@ entry: ; Load/Store opt is disabled with -O0, so the i128 is split. ; FAST: str {{x[0-9]+}}, [x[[ADDR]], #8] ; FAST: str {{x[0-9]+}}, [x[[ADDR]]] - %0 = load i128* bitcast (%struct.s41* @g41 to i128*), align 16 + %0 = load i128, i128* bitcast (%struct.s41* @g41 to i128*), align 16 %call = tail call i32 @callee_i128_split(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i128 %0, i32 8) #5 ret i32 %call @@ -514,7 +514,7 @@ entry: ; FAST: mov x[[R0:[0-9]+]], sp ; FAST: orr w[[R1:[0-9]+]], wzr, #0x8 ; FAST: str w[[R1]], {{\[}}x[[R0]]{{\]}} - %0 = load i64* bitcast (%struct.s41* @g41 to i64*), align 16 + %0 = load i64, i64* bitcast (%struct.s41* @g41 to i64*), align 16 %call = tail call i32 @callee_i64(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i64 %0, i32 8) #5 ret i32 %call diff --git a/test/CodeGen/AArch64/arm64-addr-mode-folding.ll b/test/CodeGen/AArch64/arm64-addr-mode-folding.ll index 74bb398..3197f5b 100644 --- a/test/CodeGen/AArch64/arm64-addr-mode-folding.ll +++ b/test/CodeGen/AArch64/arm64-addr-mode-folding.ll @@ -11,12 +11,12 @@ define i32 @fct(i32 %i1, i32 %i2) { ; _CHECK-NOT_: , sxtw] entry: %idxprom = sext i32 %i1 to i64 - %0 = load i8** @block, align 8 - %arrayidx = getelementptr inbounds i8* %0, i64 %idxprom - %1 = load i8* %arrayidx, align 1 + %0 = load i8*, i8** @block, align 8 + %arrayidx = getelementptr inbounds i8, i8* %0, i64 %idxprom + %1 = load i8, i8* %arrayidx, align 1 %idxprom1 = sext i32 %i2 to i64 - %arrayidx2 = getelementptr inbounds i8* %0, i64 %idxprom1 - %2 = load i8* %arrayidx2, align 1 + %arrayidx2 = getelementptr inbounds i8, i8* %0, i64 %idxprom1 + %2 = load i8, i8* %arrayidx2, align 1 %cmp = icmp eq i8 %1, %2 br i1 %cmp, label %if.end, label %if.then @@ -29,11 +29,11 @@ if.end: ; preds = %entry %inc = add nsw i32 %i1, 1 %inc9 = add nsw i32 %i2, 1 %idxprom10 = sext i32 %inc to i64 - %arrayidx11 = getelementptr inbounds i8* %0, i64 %idxprom10 - %3 = load i8* %arrayidx11, align 1 + %arrayidx11 = getelementptr inbounds i8, i8* %0, i64 %idxprom10 + %3 = load i8, i8* %arrayidx11, align 1 %idxprom12 = sext i32 %inc9 to i64 - %arrayidx13 = getelementptr inbounds i8* %0, i64 %idxprom12 - %4 = load i8* %arrayidx13, align 1 + %arrayidx13 = getelementptr inbounds i8, i8* %0, i64 %idxprom12 + %4 = load i8, i8* %arrayidx13, align 1 %cmp16 = icmp eq i8 %3, %4 br i1 %cmp16, label %if.end23, label %if.then18 @@ -46,11 +46,11 @@ if.end23: ; preds = %if.end %inc24 = add nsw i32 %i1, 2 %inc25 = add nsw i32 %i2, 2 %idxprom26 = sext i32 %inc24 to i64 - %arrayidx27 = getelementptr inbounds i8* %0, i64 %idxprom26 - %5 = load i8* %arrayidx27, align 1 + %arrayidx27 = getelementptr inbounds i8, i8* %0, i64 %idxprom26 + %5 = load i8, i8* %arrayidx27, align 1 %idxprom28 = sext i32 %inc25 to i64 - %arrayidx29 = getelementptr inbounds i8* %0, i64 %idxprom28 - %6 = load i8* %arrayidx29, align 1 + %arrayidx29 = getelementptr inbounds i8, i8* %0, i64 %idxprom28 + %6 = load i8, i8* %arrayidx29, align 1 %cmp32 = icmp eq i8 %5, %6 br i1 %cmp32, label %return, label %if.then34 @@ -71,12 +71,12 @@ define i32 @fct1(i32 %i1, i32 %i2) optsize { ; CHECK: , sxtw] entry: %idxprom = sext i32 %i1 to i64 - %0 = load i8** @block, align 8 - %arrayidx = getelementptr inbounds i8* %0, i64 %idxprom - %1 = load i8* %arrayidx, align 1 + %0 = load i8*, i8** @block, align 8 + %arrayidx = getelementptr inbounds i8, i8* %0, i64 %idxprom + %1 = load i8, i8* %arrayidx, align 1 %idxprom1 = sext i32 %i2 to i64 - %arrayidx2 = getelementptr inbounds i8* %0, i64 %idxprom1 - %2 = load i8* %arrayidx2, align 1 + %arrayidx2 = getelementptr inbounds i8, i8* %0, i64 %idxprom1 + %2 = load i8, i8* %arrayidx2, align 1 %cmp = icmp eq i8 %1, %2 br i1 %cmp, label %if.end, label %if.then @@ -89,11 +89,11 @@ if.end: ; preds = %entry %inc = add nsw i32 %i1, 1 %inc9 = add nsw i32 %i2, 1 %idxprom10 = sext i32 %inc to i64 - %arrayidx11 = getelementptr inbounds i8* %0, i64 %idxprom10 - %3 = load i8* %arrayidx11, align 1 + %arrayidx11 = getelementptr inbounds i8, i8* %0, i64 %idxprom10 + %3 = load i8, i8* %arrayidx11, align 1 %idxprom12 = sext i32 %inc9 to i64 - %arrayidx13 = getelementptr inbounds i8* %0, i64 %idxprom12 - %4 = load i8* %arrayidx13, align 1 + %arrayidx13 = getelementptr inbounds i8, i8* %0, i64 %idxprom12 + %4 = load i8, i8* %arrayidx13, align 1 %cmp16 = icmp eq i8 %3, %4 br i1 %cmp16, label %if.end23, label %if.then18 @@ -106,11 +106,11 @@ if.end23: ; preds = %if.end %inc24 = add nsw i32 %i1, 2 %inc25 = add nsw i32 %i2, 2 %idxprom26 = sext i32 %inc24 to i64 - %arrayidx27 = getelementptr inbounds i8* %0, i64 %idxprom26 - %5 = load i8* %arrayidx27, align 1 + %arrayidx27 = getelementptr inbounds i8, i8* %0, i64 %idxprom26 + %5 = load i8, i8* %arrayidx27, align 1 %idxprom28 = sext i32 %inc25 to i64 - %arrayidx29 = getelementptr inbounds i8* %0, i64 %idxprom28 - %6 = load i8* %arrayidx29, align 1 + %arrayidx29 = getelementptr inbounds i8, i8* %0, i64 %idxprom28 + %6 = load i8, i8* %arrayidx29, align 1 %cmp32 = icmp eq i8 %5, %6 br i1 %cmp32, label %return, label %if.then34 @@ -135,9 +135,9 @@ entry: if.then: ; preds = %entry %idxprom = zext i8 %c to i64 - %arrayidx = getelementptr inbounds i32* %array, i64 %idxprom - %0 = load volatile i32* %arrayidx, align 4 - %1 = load volatile i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, i32* %array, i64 %idxprom + %0 = load volatile i32, i32* %arrayidx, align 4 + %1 = load volatile i32, i32* %arrayidx, align 4 %add3 = add nsw i32 %1, %0 br label %if.end @@ -159,9 +159,9 @@ entry: if.then: ; preds = %entry %idxprom = zext i8 %c to i64 - %arrayidx = getelementptr inbounds i32* %array, i64 %idxprom - %0 = load volatile i32* %arrayidx, align 4 - %1 = load volatile i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, i32* %array, i64 %idxprom + %0 = load volatile i32, i32* %arrayidx, align 4 + %1 = load volatile i32, i32* %arrayidx, align 4 %add3 = add nsw i32 %1, %0 br label %if.end diff --git a/test/CodeGen/AArch64/arm64-addr-type-promotion.ll b/test/CodeGen/AArch64/arm64-addr-type-promotion.ll index 1a3ca8b..4703d25 100644 --- a/test/CodeGen/AArch64/arm64-addr-type-promotion.ll +++ b/test/CodeGen/AArch64/arm64-addr-type-promotion.ll @@ -28,12 +28,12 @@ define zeroext i8 @fullGtU(i32 %i1, i32 %i2) { ; CHECK-NEXT: cmp [[LOADEDVAL3]], [[LOADEDVAL4]] entry: %idxprom = sext i32 %i1 to i64 - %tmp = load i8** @block, align 8 - %arrayidx = getelementptr inbounds i8* %tmp, i64 %idxprom - %tmp1 = load i8* %arrayidx, align 1 + %tmp = load i8*, i8** @block, align 8 + %arrayidx = getelementptr inbounds i8, i8* %tmp, i64 %idxprom + %tmp1 = load i8, i8* %arrayidx, align 1 %idxprom1 = sext i32 %i2 to i64 - %arrayidx2 = getelementptr inbounds i8* %tmp, i64 %idxprom1 - %tmp2 = load i8* %arrayidx2, align 1 + %arrayidx2 = getelementptr inbounds i8, i8* %tmp, i64 %idxprom1 + %tmp2 = load i8, i8* %arrayidx2, align 1 %cmp = icmp eq i8 %tmp1, %tmp2 br i1 %cmp, label %if.end, label %if.then @@ -46,11 +46,11 @@ if.end: ; preds = %entry %inc = add nsw i32 %i1, 1 %inc10 = add nsw i32 %i2, 1 %idxprom11 = sext i32 %inc to i64 - %arrayidx12 = getelementptr inbounds i8* %tmp, i64 %idxprom11 - %tmp3 = load i8* %arrayidx12, align 1 + %arrayidx12 = getelementptr inbounds i8, i8* %tmp, i64 %idxprom11 + %tmp3 = load i8, i8* %arrayidx12, align 1 %idxprom13 = sext i32 %inc10 to i64 - %arrayidx14 = getelementptr inbounds i8* %tmp, i64 %idxprom13 - %tmp4 = load i8* %arrayidx14, align 1 + %arrayidx14 = getelementptr inbounds i8, i8* %tmp, i64 %idxprom13 + %tmp4 = load i8, i8* %arrayidx14, align 1 %cmp17 = icmp eq i8 %tmp3, %tmp4 br i1 %cmp17, label %if.end25, label %if.then19 @@ -63,11 +63,11 @@ if.end25: ; preds = %if.end %inc26 = add nsw i32 %i1, 2 %inc27 = add nsw i32 %i2, 2 %idxprom28 = sext i32 %inc26 to i64 - %arrayidx29 = getelementptr inbounds i8* %tmp, i64 %idxprom28 - %tmp5 = load i8* %arrayidx29, align 1 + %arrayidx29 = getelementptr inbounds i8, i8* %tmp, i64 %idxprom28 + %tmp5 = load i8, i8* %arrayidx29, align 1 %idxprom30 = sext i32 %inc27 to i64 - %arrayidx31 = getelementptr inbounds i8* %tmp, i64 %idxprom30 - %tmp6 = load i8* %arrayidx31, align 1 + %arrayidx31 = getelementptr inbounds i8, i8* %tmp, i64 %idxprom30 + %tmp6 = load i8, i8* %arrayidx31, align 1 %cmp34 = icmp eq i8 %tmp5, %tmp6 br i1 %cmp34, label %return, label %if.then36 diff --git a/test/CodeGen/AArch64/arm64-addrmode.ll b/test/CodeGen/AArch64/arm64-addrmode.ll index 5433a8c..c22d031 100644 --- a/test/CodeGen/AArch64/arm64-addrmode.ll +++ b/test/CodeGen/AArch64/arm64-addrmode.ll @@ -8,8 +8,8 @@ ; CHECK: ldr xzr, [x{{[0-9]+}}, #8] ; CHECK: ret define void @t1() { - %incdec.ptr = getelementptr inbounds i64* @object, i64 1 - %tmp = load volatile i64* %incdec.ptr, align 8 + %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 1 + %tmp = load volatile i64, i64* %incdec.ptr, align 8 ret void } @@ -20,8 +20,8 @@ define void @t1() { ; CHECK: [[ADDREG]]] ; CHECK: ret define void @t2() { - %incdec.ptr = getelementptr inbounds i64* @object, i64 -33 - %tmp = load volatile i64* %incdec.ptr, align 8 + %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 -33 + %tmp = load volatile i64, i64* %incdec.ptr, align 8 ret void } @@ -30,8 +30,8 @@ define void @t2() { ; CHECK: ldr xzr, [x{{[0-9]+}}, #32760] ; CHECK: ret define void @t3() { - %incdec.ptr = getelementptr inbounds i64* @object, i64 4095 - %tmp = load volatile i64* %incdec.ptr, align 8 + %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 4095 + %tmp = load volatile i64, i64* %incdec.ptr, align 8 ret void } @@ -41,8 +41,8 @@ define void @t3() { ; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]] ; CHECK: ret define void @t4() { - %incdec.ptr = getelementptr inbounds i64* @object, i64 4096 - %tmp = load volatile i64* %incdec.ptr, align 8 + %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 4096 + %tmp = load volatile i64, i64* %incdec.ptr, align 8 ret void } @@ -51,8 +51,8 @@ define void @t4() { ; CHECK: ldr xzr, [x{{[0-9]+}}, x{{[0-9]+}}, lsl #3] ; CHECK: ret define void @t5(i64 %a) { - %incdec.ptr = getelementptr inbounds i64* @object, i64 %a - %tmp = load volatile i64* %incdec.ptr, align 8 + %incdec.ptr = getelementptr inbounds i64, i64* @object, i64 %a + %tmp = load volatile i64, i64* %incdec.ptr, align 8 ret void } @@ -63,9 +63,9 @@ define void @t5(i64 %a) { ; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]] ; CHECK: ret define void @t6(i64 %a) { - %tmp1 = getelementptr inbounds i64* @object, i64 %a - %incdec.ptr = getelementptr inbounds i64* %tmp1, i64 4096 - %tmp = load volatile i64* %incdec.ptr, align 8 + %tmp1 = getelementptr inbounds i64, i64* @object, i64 %a + %incdec.ptr = getelementptr inbounds i64, i64* %tmp1, i64 4096 + %tmp = load volatile i64, i64* %incdec.ptr, align 8 ret void } @@ -76,7 +76,7 @@ define void @t7(i64 %a) { ; CHECK-NEXT: ldr xzr, [x0, x[[NUM]]] %1 = add i64 %a, 65535 ;0xffff %2 = inttoptr i64 %1 to i64* - %3 = load volatile i64* %2, align 8 + %3 = load volatile i64, i64* %2, align 8 ret void } @@ -86,7 +86,7 @@ define void @t8(i64 %a) { ; CHECK-NEXT: ldr xzr, [x0, [[REG]]] %1 = sub i64 %a, 4662 ;-4662 is 0xffffffffffffedca %2 = inttoptr i64 %1 to i64* - %3 = load volatile i64* %2, align 8 + %3 = load volatile i64, i64* %2, align 8 ret void } @@ -96,7 +96,7 @@ define void @t9(i64 %a) { ; CHECK-NEXT: ldr xzr, [x0, [[REG]]] %1 = add i64 -305463297, %a ;-305463297 is 0xffffffffedcaffff %2 = inttoptr i64 %1 to i64* - %3 = load volatile i64* %2, align 8 + %3 = load volatile i64, i64* %2, align 8 ret void } @@ -106,7 +106,7 @@ define void @t10(i64 %a) { ; CHECK-NEXT: ldr xzr, [x0, [[REG]]] %1 = add i64 %a, 81909218222800896 ;0x123000000000000 %2 = inttoptr i64 %1 to i64* - %3 = load volatile i64* %2, align 8 + %3 = load volatile i64, i64* %2, align 8 ret void } @@ -117,7 +117,7 @@ define void @t11(i64 %a) { ; CHECK-NEXT: ldr xzr, [x0, x[[NUM]]] %1 = add i64 %a, 19088743 ;0x1234567 %2 = inttoptr i64 %1 to i64* - %3 = load volatile i64* %2, align 8 + %3 = load volatile i64, i64* %2, align 8 ret void } @@ -128,7 +128,7 @@ define void @t12(i64 %a) { ; CHECK-NEXT: ldr xzr, {{\[}}[[REG]]] %1 = add i64 %a, 4095 ;0xfff %2 = inttoptr i64 %1 to i64* - %3 = load volatile i64* %2, align 8 + %3 = load volatile i64, i64* %2, align 8 ret void } @@ -138,7 +138,7 @@ define void @t13(i64 %a) { ; CHECK-NEXT: ldr xzr, {{\[}}[[REG]]] %1 = add i64 %a, -4095 ;-0xfff %2 = inttoptr i64 %1 to i64* - %3 = load volatile i64* %2, align 8 + %3 = load volatile i64, i64* %2, align 8 ret void } @@ -148,7 +148,7 @@ define void @t14(i64 %a) { ; CHECK-NEXT: ldr xzr, {{\[}}[[REG]]] %1 = add i64 %a, 1191936 ;0x123000 %2 = inttoptr i64 %1 to i64* - %3 = load volatile i64* %2, align 8 + %3 = load volatile i64, i64* %2, align 8 ret void } @@ -158,7 +158,7 @@ define void @t15(i64 %a) { ; CHECK-NEXT: ldr xzr, {{\[}}[[REG]]] %1 = add i64 %a, -1191936 ;0xFFFFFFFFFFEDD000 %2 = inttoptr i64 %1 to i64* - %3 = load volatile i64* %2, align 8 + %3 = load volatile i64, i64* %2, align 8 ret void } @@ -167,7 +167,7 @@ define void @t16(i64 %a) { ; CHECK: ldr xzr, [x0, #28672] %1 = add i64 %a, 28672 ;0x7000 %2 = inttoptr i64 %1 to i64* - %3 = load volatile i64* %2, align 8 + %3 = load volatile i64, i64* %2, align 8 ret void } @@ -176,6 +176,6 @@ define void @t17(i64 %a) { ; CHECK: ldur xzr, [x0, #-256] %1 = add i64 %a, -256 ;-0x100 %2 = inttoptr i64 %1 to i64* - %3 = load volatile i64* %2, align 8 + %3 = load volatile i64, i64* %2, align 8 ret void } diff --git a/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll b/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll index f396bc9..bf2d2cf 100644 --- a/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll +++ b/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll @@ -13,9 +13,9 @@ entry: ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], {{\[}}[[BASE:x[0-9]+]], #32] ; CHECK: stp [[Q1:q[0-9]+]], [[Q2:q[0-9]+]], {{\[}}[[BASE]]] %retval = alloca <16 x float>, align 16 - %0 = load <16 x float>* @T3_retval, align 16 + %0 = load <16 x float>, <16 x float>* @T3_retval, align 16 store <16 x float> %0, <16 x float>* %retval - %1 = load <16 x float>* %retval + %1 = load <16 x float>, <16 x float>* %retval store <16 x float> %1, <16 x float>* %agg.result, align 16 ret void } diff --git a/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll b/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll index 3750f31..eb0cd35 100644 --- a/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll +++ b/test/CodeGen/AArch64/arm64-alloca-frame-pointer-offset.ll @@ -13,17 +13,17 @@ define i32 @foo(i32 %a) nounwind { %arr2 = alloca [32 x i32], align 4 %j = alloca i32, align 4 store i32 %a, i32* %a.addr, align 4 - %tmp = load i32* %a.addr, align 4 + %tmp = load i32, i32* %a.addr, align 4 %tmp1 = zext i32 %tmp to i64 %v = mul i64 4, %tmp1 %vla = alloca i8, i64 %v, align 4 %tmp2 = bitcast i8* %vla to i32* - %tmp3 = load i32* %a.addr, align 4 + %tmp3 = load i32, i32* %a.addr, align 4 store i32 %tmp3, i32* %i, align 4 - %tmp4 = load i32* %a.addr, align 4 + %tmp4 = load i32, i32* %a.addr, align 4 store i32 %tmp4, i32* %j, align 4 - %tmp5 = load i32* %j, align 4 + %tmp5 = load i32, i32* %j, align 4 store i32 %tmp5, i32* %retval - %x = load i32* %retval + %x = load i32, i32* %retval ret i32 %x } diff --git a/test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll b/test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll index 4194977..71e6480 100644 --- a/test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll +++ b/test/CodeGen/AArch64/arm64-andCmpBrToTBZ.ll @@ -29,7 +29,7 @@ _ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit: ; preds = %lor.rhs.i.i br i1 %cmp.i.i.i.i, label %if.then3, label %if.end5 if.then3: ; preds = %_ZNK7WebCore4Node10hasTagNameERKNS_13QualifiedNameE.exit, %land.rhs.i - %tmp11 = load i8* %str14, align 8 + %tmp11 = load i8, i8* %str14, align 8 %tmp12 = and i8 %tmp11, 2 %tmp13 = icmp ne i8 %tmp12, 0 br label %return @@ -55,7 +55,7 @@ if.then7: ; preds = %_ZNK7WebCore4Node10 br i1 %isTextField, label %if.then9, label %if.end12 if.then9: ; preds = %if.then7 - %tmp23 = load i8* %str5, align 8 + %tmp23 = load i8, i8* %str5, align 8 %tmp24 = and i8 %tmp23, 2 %tmp25 = icmp ne i8 %tmp24, 0 br label %return diff --git a/test/CodeGen/AArch64/arm64-atomic-128.ll b/test/CodeGen/AArch64/arm64-atomic-128.ll index 642d72a..a76cf74 100644 --- a/test/CodeGen/AArch64/arm64-atomic-128.ll +++ b/test/CodeGen/AArch64/arm64-atomic-128.ll @@ -169,7 +169,7 @@ define i128 @atomic_load_seq_cst(i128* %p) { ; CHECK-NOT: dmb ; CHECK-LABEL: ldaxp ; CHECK-NOT: dmb - %r = load atomic i128* %p seq_cst, align 16 + %r = load atomic i128, i128* %p seq_cst, align 16 ret i128 %r } @@ -178,7 +178,7 @@ define i128 @atomic_load_relaxed(i128* %p) { ; CHECK-NOT: dmb ; CHECK: ldxp [[LO:x[0-9]+]], [[HI:x[0-9]+]], [x0] ; CHECK-NOT: dmb - %r = load atomic i128* %p monotonic, align 16 + %r = load atomic i128, i128* %p monotonic, align 16 ret i128 %r } diff --git a/test/CodeGen/AArch64/arm64-atomic.ll b/test/CodeGen/AArch64/arm64-atomic.ll index b56f91d..451e7e0 100644 --- a/test/CodeGen/AArch64/arm64-atomic.ll +++ b/test/CodeGen/AArch64/arm64-atomic.ll @@ -107,7 +107,7 @@ define void @seq_cst_fence() { } define i32 @atomic_load(i32* %p) { - %r = load atomic i32* %p seq_cst, align 4 + %r = load atomic i32, i32* %p seq_cst, align 4 ret i32 %r ; CHECK-LABEL: atomic_load: ; CHECK: ldar @@ -115,22 +115,22 @@ define i32 @atomic_load(i32* %p) { define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) { ; CHECK-LABEL: atomic_load_relaxed_8: - %ptr_unsigned = getelementptr i8* %p, i32 4095 - %val_unsigned = load atomic i8* %ptr_unsigned monotonic, align 1 + %ptr_unsigned = getelementptr i8, i8* %p, i32 4095 + %val_unsigned = load atomic i8, i8* %ptr_unsigned monotonic, align 1 ; CHECK: ldrb {{w[0-9]+}}, [x0, #4095] - %ptr_regoff = getelementptr i8* %p, i32 %off32 - %val_regoff = load atomic i8* %ptr_regoff unordered, align 1 + %ptr_regoff = getelementptr i8, i8* %p, i32 %off32 + %val_regoff = load atomic i8, i8* %ptr_regoff unordered, align 1 %tot1 = add i8 %val_unsigned, %val_regoff ; CHECK: ldrb {{w[0-9]+}}, [x0, w1, sxtw] - %ptr_unscaled = getelementptr i8* %p, i32 -256 - %val_unscaled = load atomic i8* %ptr_unscaled monotonic, align 1 + %ptr_unscaled = getelementptr i8, i8* %p, i32 -256 + %val_unscaled = load atomic i8, i8* %ptr_unscaled monotonic, align 1 %tot2 = add i8 %tot1, %val_unscaled ; CHECK: ldurb {{w[0-9]+}}, [x0, #-256] - %ptr_random = getelementptr i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm) - %val_random = load atomic i8* %ptr_random unordered, align 1 + %ptr_random = getelementptr i8, i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm) + %val_random = load atomic i8, i8* %ptr_random unordered, align 1 %tot3 = add i8 %tot2, %val_random ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12 ; CHECK: ldrb {{w[0-9]+}}, [x[[ADDR]]] @@ -140,22 +140,22 @@ define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) { define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) { ; CHECK-LABEL: atomic_load_relaxed_16: - %ptr_unsigned = getelementptr i16* %p, i32 4095 - %val_unsigned = load atomic i16* %ptr_unsigned monotonic, align 2 + %ptr_unsigned = getelementptr i16, i16* %p, i32 4095 + %val_unsigned = load atomic i16, i16* %ptr_unsigned monotonic, align 2 ; CHECK: ldrh {{w[0-9]+}}, [x0, #8190] - %ptr_regoff = getelementptr i16* %p, i32 %off32 - %val_regoff = load atomic i16* %ptr_regoff unordered, align 2 + %ptr_regoff = getelementptr i16, i16* %p, i32 %off32 + %val_regoff = load atomic i16, i16* %ptr_regoff unordered, align 2 %tot1 = add i16 %val_unsigned, %val_regoff ; CHECK: ldrh {{w[0-9]+}}, [x0, w1, sxtw #1] - %ptr_unscaled = getelementptr i16* %p, i32 -128 - %val_unscaled = load atomic i16* %ptr_unscaled monotonic, align 2 + %ptr_unscaled = getelementptr i16, i16* %p, i32 -128 + %val_unscaled = load atomic i16, i16* %ptr_unscaled monotonic, align 2 %tot2 = add i16 %tot1, %val_unscaled ; CHECK: ldurh {{w[0-9]+}}, [x0, #-256] - %ptr_random = getelementptr i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm) - %val_random = load atomic i16* %ptr_random unordered, align 2 + %ptr_random = getelementptr i16, i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm) + %val_random = load atomic i16, i16* %ptr_random unordered, align 2 %tot3 = add i16 %tot2, %val_random ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12 ; CHECK: ldrh {{w[0-9]+}}, [x[[ADDR]]] @@ -165,22 +165,22 @@ define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) { define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) { ; CHECK-LABEL: atomic_load_relaxed_32: - %ptr_unsigned = getelementptr i32* %p, i32 4095 - %val_unsigned = load atomic i32* %ptr_unsigned monotonic, align 4 + %ptr_unsigned = getelementptr i32, i32* %p, i32 4095 + %val_unsigned = load atomic i32, i32* %ptr_unsigned monotonic, align 4 ; CHECK: ldr {{w[0-9]+}}, [x0, #16380] - %ptr_regoff = getelementptr i32* %p, i32 %off32 - %val_regoff = load atomic i32* %ptr_regoff unordered, align 4 + %ptr_regoff = getelementptr i32, i32* %p, i32 %off32 + %val_regoff = load atomic i32, i32* %ptr_regoff unordered, align 4 %tot1 = add i32 %val_unsigned, %val_regoff ; CHECK: ldr {{w[0-9]+}}, [x0, w1, sxtw #2] - %ptr_unscaled = getelementptr i32* %p, i32 -64 - %val_unscaled = load atomic i32* %ptr_unscaled monotonic, align 4 + %ptr_unscaled = getelementptr i32, i32* %p, i32 -64 + %val_unscaled = load atomic i32, i32* %ptr_unscaled monotonic, align 4 %tot2 = add i32 %tot1, %val_unscaled ; CHECK: ldur {{w[0-9]+}}, [x0, #-256] - %ptr_random = getelementptr i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm) - %val_random = load atomic i32* %ptr_random unordered, align 4 + %ptr_random = getelementptr i32, i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm) + %val_random = load atomic i32, i32* %ptr_random unordered, align 4 %tot3 = add i32 %tot2, %val_random ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12 ; CHECK: ldr {{w[0-9]+}}, [x[[ADDR]]] @@ -190,22 +190,22 @@ define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) { define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) { ; CHECK-LABEL: atomic_load_relaxed_64: - %ptr_unsigned = getelementptr i64* %p, i32 4095 - %val_unsigned = load atomic i64* %ptr_unsigned monotonic, align 8 + %ptr_unsigned = getelementptr i64, i64* %p, i32 4095 + %val_unsigned = load atomic i64, i64* %ptr_unsigned monotonic, align 8 ; CHECK: ldr {{x[0-9]+}}, [x0, #32760] - %ptr_regoff = getelementptr i64* %p, i32 %off32 - %val_regoff = load atomic i64* %ptr_regoff unordered, align 8 + %ptr_regoff = getelementptr i64, i64* %p, i32 %off32 + %val_regoff = load atomic i64, i64* %ptr_regoff unordered, align 8 %tot1 = add i64 %val_unsigned, %val_regoff ; CHECK: ldr {{x[0-9]+}}, [x0, w1, sxtw #3] - %ptr_unscaled = getelementptr i64* %p, i32 -32 - %val_unscaled = load atomic i64* %ptr_unscaled monotonic, align 8 + %ptr_unscaled = getelementptr i64, i64* %p, i32 -32 + %val_unscaled = load atomic i64, i64* %ptr_unscaled monotonic, align 8 %tot2 = add i64 %tot1, %val_unscaled ; CHECK: ldur {{x[0-9]+}}, [x0, #-256] - %ptr_random = getelementptr i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm) - %val_random = load atomic i64* %ptr_random unordered, align 8 + %ptr_random = getelementptr i64, i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm) + %val_random = load atomic i64, i64* %ptr_random unordered, align 8 %tot3 = add i64 %tot2, %val_random ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12 ; CHECK: ldr {{x[0-9]+}}, [x[[ADDR]]] @@ -223,19 +223,19 @@ define void @atomc_store(i32* %p) { define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) { ; CHECK-LABEL: atomic_store_relaxed_8: - %ptr_unsigned = getelementptr i8* %p, i32 4095 + %ptr_unsigned = getelementptr i8, i8* %p, i32 4095 store atomic i8 %val, i8* %ptr_unsigned monotonic, align 1 ; CHECK: strb {{w[0-9]+}}, [x0, #4095] - %ptr_regoff = getelementptr i8* %p, i32 %off32 + %ptr_regoff = getelementptr i8, i8* %p, i32 %off32 store atomic i8 %val, i8* %ptr_regoff unordered, align 1 ; CHECK: strb {{w[0-9]+}}, [x0, w1, sxtw] - %ptr_unscaled = getelementptr i8* %p, i32 -256 + %ptr_unscaled = getelementptr i8, i8* %p, i32 -256 store atomic i8 %val, i8* %ptr_unscaled monotonic, align 1 ; CHECK: sturb {{w[0-9]+}}, [x0, #-256] - %ptr_random = getelementptr i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm) + %ptr_random = getelementptr i8, i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm) store atomic i8 %val, i8* %ptr_random unordered, align 1 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12 ; CHECK: strb {{w[0-9]+}}, [x[[ADDR]]] @@ -245,19 +245,19 @@ define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) { define void @atomic_store_relaxed_16(i16* %p, i32 %off32, i16 %val) { ; CHECK-LABEL: atomic_store_relaxed_16: - %ptr_unsigned = getelementptr i16* %p, i32 4095 + %ptr_unsigned = getelementptr i16, i16* %p, i32 4095 store atomic i16 %val, i16* %ptr_unsigned monotonic, align 2 ; CHECK: strh {{w[0-9]+}}, [x0, #8190] - %ptr_regoff = getelementptr i16* %p, i32 %off32 + %ptr_regoff = getelementptr i16, i16* %p, i32 %off32 store atomic i16 %val, i16* %ptr_regoff unordered, align 2 ; CHECK: strh {{w[0-9]+}}, [x0, w1, sxtw #1] - %ptr_unscaled = getelementptr i16* %p, i32 -128 + %ptr_unscaled = getelementptr i16, i16* %p, i32 -128 store atomic i16 %val, i16* %ptr_unscaled monotonic, align 2 ; CHECK: sturh {{w[0-9]+}}, [x0, #-256] - %ptr_random = getelementptr i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm) + %ptr_random = getelementptr i16, i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm) store atomic i16 %val, i16* %ptr_random unordered, align 2 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12 ; CHECK: strh {{w[0-9]+}}, [x[[ADDR]]] @@ -267,19 +267,19 @@ define void @atomic_store_relaxed_16(i16* %p, i32 %off32, i16 %val) { define void @atomic_store_relaxed_32(i32* %p, i32 %off32, i32 %val) { ; CHECK-LABEL: atomic_store_relaxed_32: - %ptr_unsigned = getelementptr i32* %p, i32 4095 + %ptr_unsigned = getelementptr i32, i32* %p, i32 4095 store atomic i32 %val, i32* %ptr_unsigned monotonic, align 4 ; CHECK: str {{w[0-9]+}}, [x0, #16380] - %ptr_regoff = getelementptr i32* %p, i32 %off32 + %ptr_regoff = getelementptr i32, i32* %p, i32 %off32 store atomic i32 %val, i32* %ptr_regoff unordered, align 4 ; CHECK: str {{w[0-9]+}}, [x0, w1, sxtw #2] - %ptr_unscaled = getelementptr i32* %p, i32 -64 + %ptr_unscaled = getelementptr i32, i32* %p, i32 -64 store atomic i32 %val, i32* %ptr_unscaled monotonic, align 4 ; CHECK: stur {{w[0-9]+}}, [x0, #-256] - %ptr_random = getelementptr i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm) + %ptr_random = getelementptr i32, i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm) store atomic i32 %val, i32* %ptr_random unordered, align 4 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12 ; CHECK: str {{w[0-9]+}}, [x[[ADDR]]] @@ -289,19 +289,19 @@ define void @atomic_store_relaxed_32(i32* %p, i32 %off32, i32 %val) { define void @atomic_store_relaxed_64(i64* %p, i32 %off32, i64 %val) { ; CHECK-LABEL: atomic_store_relaxed_64: - %ptr_unsigned = getelementptr i64* %p, i32 4095 + %ptr_unsigned = getelementptr i64, i64* %p, i32 4095 store atomic i64 %val, i64* %ptr_unsigned monotonic, align 8 ; CHECK: str {{x[0-9]+}}, [x0, #32760] - %ptr_regoff = getelementptr i64* %p, i32 %off32 + %ptr_regoff = getelementptr i64, i64* %p, i32 %off32 store atomic i64 %val, i64* %ptr_regoff unordered, align 8 ; CHECK: str {{x[0-9]+}}, [x0, w1, sxtw #3] - %ptr_unscaled = getelementptr i64* %p, i32 -32 + %ptr_unscaled = getelementptr i64, i64* %p, i32 -32 store atomic i64 %val, i64* %ptr_unscaled monotonic, align 8 ; CHECK: stur {{x[0-9]+}}, [x0, #-256] - %ptr_random = getelementptr i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm) + %ptr_random = getelementptr i64, i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm) store atomic i64 %val, i64* %ptr_random unordered, align 8 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12 ; CHECK: str {{x[0-9]+}}, [x[[ADDR]]] @@ -319,13 +319,13 @@ define void @atomic_store_relaxed_64(i64* %p, i32 %off32, i64 %val) { define i32 @next_id() nounwind optsize ssp align 2 { entry: - %0 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst + %0 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic", %"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst %add.i = add i32 %0, 1 %tobool = icmp eq i32 %add.i, 0 br i1 %tobool, label %if.else, label %return if.else: ; preds = %entry - %1 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst + %1 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic", %"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst %add.i2 = add i32 %1, 1 br label %return diff --git a/test/CodeGen/AArch64/arm64-basic-pic.ll b/test/CodeGen/AArch64/arm64-basic-pic.ll index 9fdb1e9..e11274e 100644 --- a/test/CodeGen/AArch64/arm64-basic-pic.ll +++ b/test/CodeGen/AArch64/arm64-basic-pic.ll @@ -5,7 +5,7 @@ define i32 @get_globalvar() { ; CHECK-LABEL: get_globalvar: - %val = load i32* @var + %val = load i32, i32* @var ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var ; CHECK: ldr x[[GOTLOC:[0-9]+]], [x[[GOTHI]], :got_lo12:var] ; CHECK: ldr w0, [x[[GOTLOC]]] @@ -16,7 +16,7 @@ define i32 @get_globalvar() { define i32* @get_globalvaraddr() { ; CHECK-LABEL: get_globalvaraddr: - %val = load i32* @var + %val = load i32, i32* @var ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var ; CHECK: ldr x0, [x[[GOTHI]], :got_lo12:var] @@ -28,7 +28,7 @@ define i32* @get_globalvaraddr() { define i32 @get_hiddenvar() { ; CHECK-LABEL: get_hiddenvar: - %val = load i32* @hiddenvar + %val = load i32, i32* @hiddenvar ; CHECK: adrp x[[HI:[0-9]+]], hiddenvar ; CHECK: ldr w0, [x[[HI]], :lo12:hiddenvar] @@ -38,7 +38,7 @@ define i32 @get_hiddenvar() { define i32* @get_hiddenvaraddr() { ; CHECK-LABEL: get_hiddenvaraddr: - %val = load i32* @hiddenvar + %val = load i32, i32* @hiddenvar ; CHECK: adrp [[HI:x[0-9]+]], hiddenvar ; CHECK: add x0, [[HI]], :lo12:hiddenvar diff --git a/test/CodeGen/AArch64/arm64-bcc.ll b/test/CodeGen/AArch64/arm64-bcc.ll index 138ae90..66d2f52 100644 --- a/test/CodeGen/AArch64/arm64-bcc.ll +++ b/test/CodeGen/AArch64/arm64-bcc.ll @@ -27,10 +27,10 @@ entry: define { i64, i1 } @foo(i64* , %Sstruct* , i1, i64) { entry: %.sroa.0 = alloca i72, align 16 - %.count.value = getelementptr inbounds %Sstruct* %1, i64 0, i32 0, i32 0 - %4 = load i64* %.count.value, align 8 - %.repeatedValue.value = getelementptr inbounds %Sstruct* %1, i64 0, i32 1, i32 0 - %5 = load i32* %.repeatedValue.value, align 8 + %.count.value = getelementptr inbounds %Sstruct, %Sstruct* %1, i64 0, i32 0, i32 0 + %4 = load i64, i64* %.count.value, align 8 + %.repeatedValue.value = getelementptr inbounds %Sstruct, %Sstruct* %1, i64 0, i32 1, i32 0 + %5 = load i32, i32* %.repeatedValue.value, align 8 %6 = icmp eq i64 %4, 0 br label %7 diff --git a/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll b/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll index d2985f4..876a691 100644 --- a/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll +++ b/test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll @@ -5,7 +5,7 @@ define void @test_i64_f64(double* %p, i64* %q) { ; CHECK: ldr ; CHECK: str - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = bitcast double %2 to i64 %4 = add i64 %3, %3 @@ -17,7 +17,7 @@ define void @test_i64_f64(double* %p, i64* %q) { define void @test_i64_v1i64(<1 x i64>* %p, i64* %q) { ; CHECK: ldr ; CHECK: str - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = bitcast <1 x i64> %2 to i64 %4 = add i64 %3, %3 @@ -30,7 +30,7 @@ define void @test_i64_v2f32(<2 x float>* %p, i64* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2s } ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: str - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = bitcast <2 x float> %2 to i64 %4 = add i64 %3, %3 @@ -43,7 +43,7 @@ define void @test_i64_v2i32(<2 x i32>* %p, i64* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2s } ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: str - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = bitcast <2 x i32> %2 to i64 %4 = add i64 %3, %3 @@ -56,7 +56,7 @@ define void @test_i64_v4i16(<4 x i16>* %p, i64* %q) { ; CHECK: ld1 { v{{[0-9]+}}.4h } ; CHECK: rev64 v{{[0-9]+}}.4h ; CHECK: str - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = bitcast <4 x i16> %2 to i64 %4 = add i64 %3, %3 @@ -69,7 +69,7 @@ define void @test_i64_v8i8(<8 x i8>* %p, i64* %q) { ; CHECK: ld1 { v{{[0-9]+}}.8b } ; CHECK: rev64 v{{[0-9]+}}.8b ; CHECK: str - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = bitcast <8 x i8> %2 to i64 %4 = add i64 %3, %3 @@ -81,7 +81,7 @@ define void @test_i64_v8i8(<8 x i8>* %p, i64* %q) { define void @test_f64_i64(i64* %p, double* %q) { ; CHECK: ldr ; CHECK: str - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = bitcast i64 %2 to double %4 = fadd double %3, %3 @@ -93,7 +93,7 @@ define void @test_f64_i64(i64* %p, double* %q) { define void @test_f64_v1i64(<1 x i64>* %p, double* %q) { ; CHECK: ldr ; CHECK: str - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = bitcast <1 x i64> %2 to double %4 = fadd double %3, %3 @@ -106,7 +106,7 @@ define void @test_f64_v2f32(<2 x float>* %p, double* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2s } ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: str - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = bitcast <2 x float> %2 to double %4 = fadd double %3, %3 @@ -119,7 +119,7 @@ define void @test_f64_v2i32(<2 x i32>* %p, double* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2s } ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: str - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = bitcast <2 x i32> %2 to double %4 = fadd double %3, %3 @@ -132,7 +132,7 @@ define void @test_f64_v4i16(<4 x i16>* %p, double* %q) { ; CHECK: ld1 { v{{[0-9]+}}.4h } ; CHECK: rev64 v{{[0-9]+}}.4h ; CHECK: str - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = bitcast <4 x i16> %2 to double %4 = fadd double %3, %3 @@ -145,7 +145,7 @@ define void @test_f64_v8i8(<8 x i8>* %p, double* %q) { ; CHECK: ld1 { v{{[0-9]+}}.8b } ; CHECK: rev64 v{{[0-9]+}}.8b ; CHECK: str - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = bitcast <8 x i8> %2 to double %4 = fadd double %3, %3 @@ -157,7 +157,7 @@ define void @test_f64_v8i8(<8 x i8>* %p, double* %q) { define void @test_v1i64_i64(i64* %p, <1 x i64>* %q) { ; CHECK: ldr ; CHECK: str - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = bitcast i64 %2 to <1 x i64> %4 = add <1 x i64> %3, %3 @@ -169,7 +169,7 @@ define void @test_v1i64_i64(i64* %p, <1 x i64>* %q) { define void @test_v1i64_f64(double* %p, <1 x i64>* %q) { ; CHECK: ldr ; CHECK: str - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = bitcast double %2 to <1 x i64> %4 = add <1 x i64> %3, %3 @@ -182,7 +182,7 @@ define void @test_v1i64_v2f32(<2 x float>* %p, <1 x i64>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2s } ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: str - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = bitcast <2 x float> %2 to <1 x i64> %4 = add <1 x i64> %3, %3 @@ -195,7 +195,7 @@ define void @test_v1i64_v2i32(<2 x i32>* %p, <1 x i64>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2s } ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: str - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = bitcast <2 x i32> %2 to <1 x i64> %4 = add <1 x i64> %3, %3 @@ -208,7 +208,7 @@ define void @test_v1i64_v4i16(<4 x i16>* %p, <1 x i64>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.4h } ; CHECK: rev64 v{{[0-9]+}}.4h ; CHECK: str - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = bitcast <4 x i16> %2 to <1 x i64> %4 = add <1 x i64> %3, %3 @@ -221,7 +221,7 @@ define void @test_v1i64_v8i8(<8 x i8>* %p, <1 x i64>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.8b } ; CHECK: rev64 v{{[0-9]+}}.8b ; CHECK: str - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = bitcast <8 x i8> %2 to <1 x i64> %4 = add <1 x i64> %3, %3 @@ -234,7 +234,7 @@ define void @test_v2f32_i64(i64* %p, <2 x float>* %q) { ; CHECK: ldr ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: st1 { v{{[0-9]+}}.2s } - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = bitcast i64 %2 to <2 x float> %4 = fadd <2 x float> %3, %3 @@ -247,7 +247,7 @@ define void @test_v2f32_f64(double* %p, <2 x float>* %q) { ; CHECK: ldr ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: st1 { v{{[0-9]+}}.2s } - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = bitcast double %2 to <2 x float> %4 = fadd <2 x float> %3, %3 @@ -260,7 +260,7 @@ define void @test_v2f32_v1i64(<1 x i64>* %p, <2 x float>* %q) { ; CHECK: ldr ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: st1 { v{{[0-9]+}}.2s } - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = bitcast <1 x i64> %2 to <2 x float> %4 = fadd <2 x float> %3, %3 @@ -272,7 +272,7 @@ define void @test_v2f32_v1i64(<1 x i64>* %p, <2 x float>* %q) { define void @test_v2f32_v2i32(<2 x i32>* %p, <2 x float>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2s } ; CHECK: st1 { v{{[0-9]+}}.2s } - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = bitcast <2 x i32> %2 to <2 x float> %4 = fadd <2 x float> %3, %3 @@ -285,7 +285,7 @@ define void @test_v2f32_v4i16(<4 x i16>* %p, <2 x float>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.4h } ; CHECK: rev32 v{{[0-9]+}}.4h ; CHECK: st1 { v{{[0-9]+}}.2s } - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = bitcast <4 x i16> %2 to <2 x float> %4 = fadd <2 x float> %3, %3 @@ -298,7 +298,7 @@ define void @test_v2f32_v8i8(<8 x i8>* %p, <2 x float>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.8b } ; CHECK: rev32 v{{[0-9]+}}.8b ; CHECK: st1 { v{{[0-9]+}}.2s } - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = bitcast <8 x i8> %2 to <2 x float> %4 = fadd <2 x float> %3, %3 @@ -311,7 +311,7 @@ define void @test_v2i32_i64(i64* %p, <2 x i32>* %q) { ; CHECK: ldr ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: st1 { v{{[0-9]+}}.2s } - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = bitcast i64 %2 to <2 x i32> %4 = add <2 x i32> %3, %3 @@ -324,7 +324,7 @@ define void @test_v2i32_f64(double* %p, <2 x i32>* %q) { ; CHECK: ldr ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: st1 { v{{[0-9]+}}.2s } - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = bitcast double %2 to <2 x i32> %4 = add <2 x i32> %3, %3 @@ -337,7 +337,7 @@ define void @test_v2i32_v1i64(<1 x i64>* %p, <2 x i32>* %q) { ; CHECK: ldr ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: st1 { v{{[0-9]+}}.2s } - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = bitcast <1 x i64> %2 to <2 x i32> %4 = add <2 x i32> %3, %3 @@ -349,7 +349,7 @@ define void @test_v2i32_v1i64(<1 x i64>* %p, <2 x i32>* %q) { define void @test_v2i32_v2f32(<2 x float>* %p, <2 x i32>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2s } ; CHECK: st1 { v{{[0-9]+}}.2s } - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = bitcast <2 x float> %2 to <2 x i32> %4 = add <2 x i32> %3, %3 @@ -362,7 +362,7 @@ define void @test_v2i32_v4i16(<4 x i16>* %p, <2 x i32>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.4h } ; CHECK: rev32 v{{[0-9]+}}.4h ; CHECK: st1 { v{{[0-9]+}}.2s } - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = bitcast <4 x i16> %2 to <2 x i32> %4 = add <2 x i32> %3, %3 @@ -375,7 +375,7 @@ define void @test_v2i32_v8i8(<8 x i8>* %p, <2 x i32>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.8b } ; CHECK: rev32 v{{[0-9]+}}.8b ; CHECK: st1 { v{{[0-9]+}}.2s } - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = bitcast <8 x i8> %2 to <2 x i32> %4 = add <2 x i32> %3, %3 @@ -388,7 +388,7 @@ define void @test_v4i16_i64(i64* %p, <4 x i16>* %q) { ; CHECK: ldr ; CHECK: rev64 v{{[0-9]+}}.4h ; CHECK: st1 { v{{[0-9]+}}.4h } - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = bitcast i64 %2 to <4 x i16> %4 = add <4 x i16> %3, %3 @@ -401,7 +401,7 @@ define void @test_v4i16_f64(double* %p, <4 x i16>* %q) { ; CHECK: ldr ; CHECK: rev64 v{{[0-9]+}}.4h ; CHECK: st1 { v{{[0-9]+}}.4h } - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = bitcast double %2 to <4 x i16> %4 = add <4 x i16> %3, %3 @@ -414,7 +414,7 @@ define void @test_v4i16_v1i64(<1 x i64>* %p, <4 x i16>* %q) { ; CHECK: ldr ; CHECK: rev64 v{{[0-9]+}}.4h ; CHECK: st1 { v{{[0-9]+}}.4h } - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = bitcast <1 x i64> %2 to <4 x i16> %4 = add <4 x i16> %3, %3 @@ -427,7 +427,7 @@ define void @test_v4i16_v2f32(<2 x float>* %p, <4 x i16>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2s } ; CHECK: rev32 v{{[0-9]+}}.4h ; CHECK: st1 { v{{[0-9]+}}.4h } - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = bitcast <2 x float> %2 to <4 x i16> %4 = add <4 x i16> %3, %3 @@ -440,7 +440,7 @@ define void @test_v4i16_v2i32(<2 x i32>* %p, <4 x i16>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2s } ; CHECK: rev32 v{{[0-9]+}}.4h ; CHECK: st1 { v{{[0-9]+}}.4h } - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = bitcast <2 x i32> %2 to <4 x i16> %4 = add <4 x i16> %3, %3 @@ -453,7 +453,7 @@ define void @test_v4i16_v8i8(<8 x i8>* %p, <4 x i16>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.8b } ; CHECK: rev16 v{{[0-9]+}}.8b ; CHECK: st1 { v{{[0-9]+}}.4h } - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = bitcast <8 x i8> %2 to <4 x i16> %4 = add <4 x i16> %3, %3 @@ -466,7 +466,7 @@ define void @test_v8i8_i64(i64* %p, <8 x i8>* %q) { ; CHECK: ldr ; CHECK: rev64 v{{[0-9]+}}.8b ; CHECK: st1 { v{{[0-9]+}}.8b } - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = bitcast i64 %2 to <8 x i8> %4 = add <8 x i8> %3, %3 @@ -479,7 +479,7 @@ define void @test_v8i8_f64(double* %p, <8 x i8>* %q) { ; CHECK: ldr ; CHECK: rev64 v{{[0-9]+}}.8b ; CHECK: st1 { v{{[0-9]+}}.8b } - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = bitcast double %2 to <8 x i8> %4 = add <8 x i8> %3, %3 @@ -492,7 +492,7 @@ define void @test_v8i8_v1i64(<1 x i64>* %p, <8 x i8>* %q) { ; CHECK: ldr ; CHECK: rev64 v{{[0-9]+}}.8b ; CHECK: st1 { v{{[0-9]+}}.8b } - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = bitcast <1 x i64> %2 to <8 x i8> %4 = add <8 x i8> %3, %3 @@ -505,7 +505,7 @@ define void @test_v8i8_v2f32(<2 x float>* %p, <8 x i8>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2s } ; CHECK: rev32 v{{[0-9]+}}.8b ; CHECK: st1 { v{{[0-9]+}}.8b } - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = bitcast <2 x float> %2 to <8 x i8> %4 = add <8 x i8> %3, %3 @@ -518,7 +518,7 @@ define void @test_v8i8_v2i32(<2 x i32>* %p, <8 x i8>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2s } ; CHECK: rev32 v{{[0-9]+}}.8b ; CHECK: st1 { v{{[0-9]+}}.8b } - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = bitcast <2 x i32> %2 to <8 x i8> %4 = add <8 x i8> %3, %3 @@ -531,7 +531,7 @@ define void @test_v8i8_v4i16(<4 x i16>* %p, <8 x i8>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.4h } ; CHECK: rev16 v{{[0-9]+}}.8b ; CHECK: st1 { v{{[0-9]+}}.8b } - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = bitcast <4 x i16> %2 to <8 x i8> %4 = add <8 x i8> %3, %3 @@ -544,7 +544,7 @@ define void @test_f128_v2f64(<2 x double>* %p, fp128* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2d } ; CHECK: ext ; CHECK: str - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = bitcast <2 x double> %2 to fp128 %4 = fadd fp128 %3, %3 @@ -557,7 +557,7 @@ define void @test_f128_v2i64(<2 x i64>* %p, fp128* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2d } ; CHECK: ext ; CHECK: str - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = bitcast <2 x i64> %2 to fp128 %4 = fadd fp128 %3, %3 @@ -572,7 +572,7 @@ define void @test_f128_v4f32(<4 x float>* %p, fp128* %q) { ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext ; CHECK: str q - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = bitcast <4 x float> %2 to fp128 %4 = fadd fp128 %3, %3 @@ -586,7 +586,7 @@ define void @test_f128_v4i32(<4 x i32>* %p, fp128* %q) { ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext ; CHECK: str - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = bitcast <4 x i32> %2 to fp128 %4 = fadd fp128 %3, %3 @@ -600,7 +600,7 @@ define void @test_f128_v8i16(<8 x i16>* %p, fp128* %q) { ; CHECK: rev64 v{{[0-9]+}}.8h ; CHECK: ext ; CHECK: str - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = bitcast <8 x i16> %2 to fp128 %4 = fadd fp128 %3, %3 @@ -613,7 +613,7 @@ define void @test_f128_v16i8(<16 x i8>* %p, fp128* %q) { ; CHECK: ld1 { v{{[0-9]+}}.16b } ; CHECK: ext ; CHECK: str q - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = bitcast <16 x i8> %2 to fp128 %4 = fadd fp128 %3, %3 @@ -626,7 +626,7 @@ define void @test_v2f64_f128(fp128* %p, <2 x double>* %q) { ; CHECK: ldr ; CHECK: ext ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = bitcast fp128 %2 to <2 x double> %4 = fadd <2 x double> %3, %3 @@ -638,7 +638,7 @@ define void @test_v2f64_f128(fp128* %p, <2 x double>* %q) { define void @test_v2f64_v2i64(<2 x i64>* %p, <2 x double>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2d } ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = bitcast <2 x i64> %2 to <2 x double> %4 = fadd <2 x double> %3, %3 @@ -652,7 +652,7 @@ define void @test_v2f64_v4f32(<4 x float>* %p, <2 x double>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = bitcast <4 x float> %2 to <2 x double> %4 = fadd <2 x double> %3, %3 @@ -665,7 +665,7 @@ define void @test_v2f64_v4i32(<4 x i32>* %p, <2 x double>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.4s } ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = bitcast <4 x i32> %2 to <2 x double> %4 = fadd <2 x double> %3, %3 @@ -678,7 +678,7 @@ define void @test_v2f64_v8i16(<8 x i16>* %p, <2 x double>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.8h } ; CHECK: rev64 v{{[0-9]+}}.8h ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = bitcast <8 x i16> %2 to <2 x double> %4 = fadd <2 x double> %3, %3 @@ -691,7 +691,7 @@ define void @test_v2f64_v16i8(<16 x i8>* %p, <2 x double>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.16b } ; CHECK: rev64 v{{[0-9]+}}.16b ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = bitcast <16 x i8> %2 to <2 x double> %4 = fadd <2 x double> %3, %3 @@ -704,7 +704,7 @@ define void @test_v2i64_f128(fp128* %p, <2 x i64>* %q) { ; CHECK: ldr ; CHECK: ext ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = bitcast fp128 %2 to <2 x i64> %4 = add <2 x i64> %3, %3 @@ -716,7 +716,7 @@ define void @test_v2i64_f128(fp128* %p, <2 x i64>* %q) { define void @test_v2i64_v2f64(<2 x double>* %p, <2 x i64>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2d } ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = bitcast <2 x double> %2 to <2 x i64> %4 = add <2 x i64> %3, %3 @@ -730,7 +730,7 @@ define void @test_v2i64_v4f32(<4 x float>* %p, <2 x i64>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = bitcast <4 x float> %2 to <2 x i64> %4 = add <2 x i64> %3, %3 @@ -743,7 +743,7 @@ define void @test_v2i64_v4i32(<4 x i32>* %p, <2 x i64>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.4s } ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = bitcast <4 x i32> %2 to <2 x i64> %4 = add <2 x i64> %3, %3 @@ -756,7 +756,7 @@ define void @test_v2i64_v8i16(<8 x i16>* %p, <2 x i64>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.8h } ; CHECK: rev64 v{{[0-9]+}}.8h ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = bitcast <8 x i16> %2 to <2 x i64> %4 = add <2 x i64> %3, %3 @@ -769,7 +769,7 @@ define void @test_v2i64_v16i8(<16 x i8>* %p, <2 x i64>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.16b } ; CHECK: rev64 v{{[0-9]+}}.16b ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = bitcast <16 x i8> %2 to <2 x i64> %4 = add <2 x i64> %3, %3 @@ -784,7 +784,7 @@ define void @test_v4f32_f128(fp128* %p, <4 x float>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = bitcast fp128 %2 to <4 x float> %4 = fadd <4 x float> %3, %3 @@ -798,7 +798,7 @@ define void @test_v4f32_v2f64(<2 x double>* %p, <4 x float>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = bitcast <2 x double> %2 to <4 x float> %4 = fadd <4 x float> %3, %3 @@ -812,7 +812,7 @@ define void @test_v4f32_v2i64(<2 x i64>* %p, <4 x float>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = bitcast <2 x i64> %2 to <4 x float> %4 = fadd <4 x float> %3, %3 @@ -825,7 +825,7 @@ define void @test_v4f32_v4i32(<4 x i32>* %p, <4 x float>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.4s } ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = bitcast <4 x i32> %2 to <4 x float> %4 = fadd <4 x float> %3, %3 @@ -839,7 +839,7 @@ define void @test_v4f32_v8i16(<8 x i16>* %p, <4 x float>* %q) { ; CHECK: rev32 v{{[0-9]+}}.8h ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = bitcast <8 x i16> %2 to <4 x float> %4 = fadd <4 x float> %3, %3 @@ -853,7 +853,7 @@ define void @test_v4f32_v16i8(<16 x i8>* %p, <4 x float>* %q) { ; CHECK: rev32 v{{[0-9]+}}.16b ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: st1 { v{{[0-9]+}}.2d } - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = bitcast <16 x i8> %2 to <4 x float> %4 = fadd <4 x float> %3, %3 @@ -867,7 +867,7 @@ define void @test_v4i32_f128(fp128* %p, <4 x i32>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext ; CHECK: st1 { v{{[0-9]+}}.4s } - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = bitcast fp128 %2 to <4 x i32> %4 = add <4 x i32> %3, %3 @@ -880,7 +880,7 @@ define void @test_v4i32_v2f64(<2 x double>* %p, <4 x i32>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2d } ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: st1 { v{{[0-9]+}}.4s } - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = bitcast <2 x double> %2 to <4 x i32> %4 = add <4 x i32> %3, %3 @@ -893,7 +893,7 @@ define void @test_v4i32_v2i64(<2 x i64>* %p, <4 x i32>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2d } ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: st1 { v{{[0-9]+}}.4s } - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = bitcast <2 x i64> %2 to <4 x i32> %4 = add <4 x i32> %3, %3 @@ -906,7 +906,7 @@ define void @test_v4i32_v4f32(<4 x float>* %p, <4 x i32>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2d } ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: st1 { v{{[0-9]+}}.4s } - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = bitcast <4 x float> %2 to <4 x i32> %4 = add <4 x i32> %3, %3 @@ -919,7 +919,7 @@ define void @test_v4i32_v8i16(<8 x i16>* %p, <4 x i32>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.8h } ; CHECK: rev32 v{{[0-9]+}}.8h ; CHECK: st1 { v{{[0-9]+}}.4s } - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = bitcast <8 x i16> %2 to <4 x i32> %4 = add <4 x i32> %3, %3 @@ -932,7 +932,7 @@ define void @test_v4i32_v16i8(<16 x i8>* %p, <4 x i32>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.16b } ; CHECK: rev32 v{{[0-9]+}}.16b ; CHECK: st1 { v{{[0-9]+}}.4s } - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = bitcast <16 x i8> %2 to <4 x i32> %4 = add <4 x i32> %3, %3 @@ -946,7 +946,7 @@ define void @test_v8i16_f128(fp128* %p, <8 x i16>* %q) { ; CHECK: rev64 v{{[0-9]+}}.8h ; CHECK: ext ; CHECK: st1 { v{{[0-9]+}}.8h } - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = bitcast fp128 %2 to <8 x i16> %4 = add <8 x i16> %3, %3 @@ -959,7 +959,7 @@ define void @test_v8i16_v2f64(<2 x double>* %p, <8 x i16>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2d } ; CHECK: rev64 v{{[0-9]+}}.8h ; CHECK: st1 { v{{[0-9]+}}.8h } - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = bitcast <2 x double> %2 to <8 x i16> %4 = add <8 x i16> %3, %3 @@ -972,7 +972,7 @@ define void @test_v8i16_v2i64(<2 x i64>* %p, <8 x i16>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2d } ; CHECK: rev64 v{{[0-9]+}}.8h ; CHECK: st1 { v{{[0-9]+}}.8h } - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = bitcast <2 x i64> %2 to <8 x i16> %4 = add <8 x i16> %3, %3 @@ -986,7 +986,7 @@ define void @test_v8i16_v4f32(<4 x float>* %p, <8 x i16>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: rev32 v{{[0-9]+}}.8h ; CHECK: st1 { v{{[0-9]+}}.8h } - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = bitcast <4 x float> %2 to <8 x i16> %4 = add <8 x i16> %3, %3 @@ -999,7 +999,7 @@ define void @test_v8i16_v4i32(<4 x i32>* %p, <8 x i16>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.4s } ; CHECK: rev32 v{{[0-9]+}}.8h ; CHECK: st1 { v{{[0-9]+}}.8h } - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = bitcast <4 x i32> %2 to <8 x i16> %4 = add <8 x i16> %3, %3 @@ -1012,7 +1012,7 @@ define void @test_v8i16_v16i8(<16 x i8>* %p, <8 x i16>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.16b } ; CHECK: rev16 v{{[0-9]+}}.16b ; CHECK: st1 { v{{[0-9]+}}.8h } - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = bitcast <16 x i8> %2 to <8 x i16> %4 = add <8 x i16> %3, %3 @@ -1026,7 +1026,7 @@ define void @test_v16i8_f128(fp128* %p, <16 x i8>* %q) { ; CHECK: rev64 v{{[0-9]+}}.16b ; CHECK: ext ; CHECK: st1 { v{{[0-9]+}}.16b } - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = bitcast fp128 %2 to <16 x i8> %4 = add <16 x i8> %3, %3 @@ -1039,7 +1039,7 @@ define void @test_v16i8_v2f64(<2 x double>* %p, <16 x i8>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2d } ; CHECK: rev64 v{{[0-9]+}}.16b ; CHECK: st1 { v{{[0-9]+}}.16b } - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = bitcast <2 x double> %2 to <16 x i8> %4 = add <16 x i8> %3, %3 @@ -1052,7 +1052,7 @@ define void @test_v16i8_v2i64(<2 x i64>* %p, <16 x i8>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.2d } ; CHECK: rev64 v{{[0-9]+}}.16b ; CHECK: st1 { v{{[0-9]+}}.16b } - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = bitcast <2 x i64> %2 to <16 x i8> %4 = add <16 x i8> %3, %3 @@ -1066,7 +1066,7 @@ define void @test_v16i8_v4f32(<4 x float>* %p, <16 x i8>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: rev32 v{{[0-9]+}}.16b ; CHECK: st1 { v{{[0-9]+}}.16b } - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = bitcast <4 x float> %2 to <16 x i8> %4 = add <16 x i8> %3, %3 @@ -1079,7 +1079,7 @@ define void @test_v16i8_v4i32(<4 x i32>* %p, <16 x i8>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.4s } ; CHECK: rev32 v{{[0-9]+}}.16b ; CHECK: st1 { v{{[0-9]+}}.16b } - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = bitcast <4 x i32> %2 to <16 x i8> %4 = add <16 x i8> %3, %3 @@ -1092,7 +1092,7 @@ define void @test_v16i8_v8i16(<8 x i16>* %p, <16 x i8>* %q) { ; CHECK: ld1 { v{{[0-9]+}}.8h } ; CHECK: rev16 v{{[0-9]+}}.16b ; CHECK: st1 { v{{[0-9]+}}.16b } - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = bitcast <8 x i16> %2 to <16 x i8> %4 = add <16 x i8> %3, %3 diff --git a/test/CodeGen/AArch64/arm64-big-endian-varargs.ll b/test/CodeGen/AArch64/arm64-big-endian-varargs.ll index db1f48c..e5e1684 100644 --- a/test/CodeGen/AArch64/arm64-big-endian-varargs.ll +++ b/test/CodeGen/AArch64/arm64-big-endian-varargs.ll @@ -21,8 +21,8 @@ entry: %vl = alloca %struct.__va_list, align 8 %vl1 = bitcast %struct.__va_list* %vl to i8* call void @llvm.va_start(i8* %vl1) - %vr_offs_p = getelementptr inbounds %struct.__va_list* %vl, i64 0, i32 4 - %vr_offs = load i32* %vr_offs_p, align 4 + %vr_offs_p = getelementptr inbounds %struct.__va_list, %struct.__va_list* %vl, i64 0, i32 4 + %vr_offs = load i32, i32* %vr_offs_p, align 4 %0 = icmp sgt i32 %vr_offs, -1 br i1 %0, label %vaarg.on_stack, label %vaarg.maybe_reg @@ -33,26 +33,26 @@ vaarg.maybe_reg: ; preds = %entry br i1 %inreg, label %vaarg.in_reg, label %vaarg.on_stack vaarg.in_reg: ; preds = %vaarg.maybe_reg - %reg_top_p = getelementptr inbounds %struct.__va_list* %vl, i64 0, i32 2 - %reg_top = load i8** %reg_top_p, align 8 + %reg_top_p = getelementptr inbounds %struct.__va_list, %struct.__va_list* %vl, i64 0, i32 2 + %reg_top = load i8*, i8** %reg_top_p, align 8 %1 = sext i32 %vr_offs to i64 - %2 = getelementptr i8* %reg_top, i64 %1 + %2 = getelementptr i8, i8* %reg_top, i64 %1 %3 = ptrtoint i8* %2 to i64 %align_be = add i64 %3, 8 %4 = inttoptr i64 %align_be to i8* br label %vaarg.end vaarg.on_stack: ; preds = %vaarg.maybe_reg, %entry - %stack_p = getelementptr inbounds %struct.__va_list* %vl, i64 0, i32 0 - %stack = load i8** %stack_p, align 8 - %new_stack = getelementptr i8* %stack, i64 8 + %stack_p = getelementptr inbounds %struct.__va_list, %struct.__va_list* %vl, i64 0, i32 0 + %stack = load i8*, i8** %stack_p, align 8 + %new_stack = getelementptr i8, i8* %stack, i64 8 store i8* %new_stack, i8** %stack_p, align 8 br label %vaarg.end vaarg.end: ; preds = %vaarg.on_stack, %vaarg.in_reg %.sink = phi i8* [ %4, %vaarg.in_reg ], [ %stack, %vaarg.on_stack ] %5 = bitcast i8* %.sink to double* - %6 = load double* %5, align 8 + %6 = load double, double* %5, align 8 call void @llvm.va_end(i8* %vl1) ret double %6 } diff --git a/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll b/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll index d72d0a5..c280bef 100644 --- a/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll +++ b/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll @@ -5,7 +5,7 @@ declare i64 @test_i64_f64_helper(double %p) define void @test_i64_f64(double* %p, i64* %q) { ; CHECK-NOT: rev - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call i64 @test_i64_f64_helper(double %2) %4 = add i64 %3, %3 @@ -17,7 +17,7 @@ define void @test_i64_f64(double* %p, i64* %q) { declare i64 @test_i64_v1i64_helper(<1 x i64> %p) define void @test_i64_v1i64(<1 x i64>* %p, i64* %q) { ; CHECK-NOT: rev - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call i64 @test_i64_v1i64_helper(<1 x i64> %2) %4 = add i64 %3, %3 @@ -29,7 +29,7 @@ define void @test_i64_v1i64(<1 x i64>* %p, i64* %q) { declare i64 @test_i64_v2f32_helper(<2 x float> %p) define void @test_i64_v2f32(<2 x float>* %p, i64* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call i64 @test_i64_v2f32_helper(<2 x float> %2) %4 = add i64 %3, %3 @@ -41,7 +41,7 @@ define void @test_i64_v2f32(<2 x float>* %p, i64* %q) { declare i64 @test_i64_v2i32_helper(<2 x i32> %p) define void @test_i64_v2i32(<2 x i32>* %p, i64* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call i64 @test_i64_v2i32_helper(<2 x i32> %2) %4 = add i64 %3, %3 @@ -53,7 +53,7 @@ define void @test_i64_v2i32(<2 x i32>* %p, i64* %q) { declare i64 @test_i64_v4i16_helper(<4 x i16> %p) define void @test_i64_v4i16(<4 x i16>* %p, i64* %q) { ; CHECK: rev64 v{{[0-9]+}}.4h - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call i64 @test_i64_v4i16_helper(<4 x i16> %2) %4 = add i64 %3, %3 @@ -65,7 +65,7 @@ define void @test_i64_v4i16(<4 x i16>* %p, i64* %q) { declare i64 @test_i64_v8i8_helper(<8 x i8> %p) define void @test_i64_v8i8(<8 x i8>* %p, i64* %q) { ; CHECK: rev64 v{{[0-9]+}}.8b - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call i64 @test_i64_v8i8_helper(<8 x i8> %2) %4 = add i64 %3, %3 @@ -77,7 +77,7 @@ define void @test_i64_v8i8(<8 x i8>* %p, i64* %q) { declare double @test_f64_i64_helper(i64 %p) define void @test_f64_i64(i64* %p, double* %q) { ; CHECK-NOT: rev - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call double @test_f64_i64_helper(i64 %2) %4 = fadd double %3, %3 @@ -89,7 +89,7 @@ define void @test_f64_i64(i64* %p, double* %q) { declare double @test_f64_v1i64_helper(<1 x i64> %p) define void @test_f64_v1i64(<1 x i64>* %p, double* %q) { ; CHECK-NOT: rev - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call double @test_f64_v1i64_helper(<1 x i64> %2) %4 = fadd double %3, %3 @@ -101,7 +101,7 @@ define void @test_f64_v1i64(<1 x i64>* %p, double* %q) { declare double @test_f64_v2f32_helper(<2 x float> %p) define void @test_f64_v2f32(<2 x float>* %p, double* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call double @test_f64_v2f32_helper(<2 x float> %2) %4 = fadd double %3, %3 @@ -113,7 +113,7 @@ define void @test_f64_v2f32(<2 x float>* %p, double* %q) { declare double @test_f64_v2i32_helper(<2 x i32> %p) define void @test_f64_v2i32(<2 x i32>* %p, double* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call double @test_f64_v2i32_helper(<2 x i32> %2) %4 = fadd double %3, %3 @@ -125,7 +125,7 @@ define void @test_f64_v2i32(<2 x i32>* %p, double* %q) { declare double @test_f64_v4i16_helper(<4 x i16> %p) define void @test_f64_v4i16(<4 x i16>* %p, double* %q) { ; CHECK: rev64 v{{[0-9]+}}.4h - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call double @test_f64_v4i16_helper(<4 x i16> %2) %4 = fadd double %3, %3 @@ -137,7 +137,7 @@ define void @test_f64_v4i16(<4 x i16>* %p, double* %q) { declare double @test_f64_v8i8_helper(<8 x i8> %p) define void @test_f64_v8i8(<8 x i8>* %p, double* %q) { ; CHECK: rev64 v{{[0-9]+}}.8b - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call double @test_f64_v8i8_helper(<8 x i8> %2) %4 = fadd double %3, %3 @@ -149,7 +149,7 @@ define void @test_f64_v8i8(<8 x i8>* %p, double* %q) { declare <1 x i64> @test_v1i64_i64_helper(i64 %p) define void @test_v1i64_i64(i64* %p, <1 x i64>* %q) { ; CHECK-NOT: rev - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <1 x i64> @test_v1i64_i64_helper(i64 %2) %4 = add <1 x i64> %3, %3 @@ -161,7 +161,7 @@ define void @test_v1i64_i64(i64* %p, <1 x i64>* %q) { declare <1 x i64> @test_v1i64_f64_helper(double %p) define void @test_v1i64_f64(double* %p, <1 x i64>* %q) { ; CHECK-NOT: rev - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <1 x i64> @test_v1i64_f64_helper(double %2) %4 = add <1 x i64> %3, %3 @@ -173,7 +173,7 @@ define void @test_v1i64_f64(double* %p, <1 x i64>* %q) { declare <1 x i64> @test_v1i64_v2f32_helper(<2 x float> %p) define void @test_v1i64_v2f32(<2 x float>* %p, <1 x i64>* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call <1 x i64> @test_v1i64_v2f32_helper(<2 x float> %2) %4 = add <1 x i64> %3, %3 @@ -185,7 +185,7 @@ define void @test_v1i64_v2f32(<2 x float>* %p, <1 x i64>* %q) { declare <1 x i64> @test_v1i64_v2i32_helper(<2 x i32> %p) define void @test_v1i64_v2i32(<2 x i32>* %p, <1 x i64>* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call <1 x i64> @test_v1i64_v2i32_helper(<2 x i32> %2) %4 = add <1 x i64> %3, %3 @@ -197,7 +197,7 @@ define void @test_v1i64_v2i32(<2 x i32>* %p, <1 x i64>* %q) { declare <1 x i64> @test_v1i64_v4i16_helper(<4 x i16> %p) define void @test_v1i64_v4i16(<4 x i16>* %p, <1 x i64>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4h - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call <1 x i64> @test_v1i64_v4i16_helper(<4 x i16> %2) %4 = add <1 x i64> %3, %3 @@ -209,7 +209,7 @@ define void @test_v1i64_v4i16(<4 x i16>* %p, <1 x i64>* %q) { declare <1 x i64> @test_v1i64_v8i8_helper(<8 x i8> %p) define void @test_v1i64_v8i8(<8 x i8>* %p, <1 x i64>* %q) { ; CHECK: rev64 v{{[0-9]+}}.8b - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call <1 x i64> @test_v1i64_v8i8_helper(<8 x i8> %2) %4 = add <1 x i64> %3, %3 @@ -221,7 +221,7 @@ define void @test_v1i64_v8i8(<8 x i8>* %p, <1 x i64>* %q) { declare <2 x float> @test_v2f32_i64_helper(i64 %p) define void @test_v2f32_i64(i64* %p, <2 x float>* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <2 x float> @test_v2f32_i64_helper(i64 %2) %4 = fadd <2 x float> %3, %3 @@ -233,7 +233,7 @@ define void @test_v2f32_i64(i64* %p, <2 x float>* %q) { declare <2 x float> @test_v2f32_f64_helper(double %p) define void @test_v2f32_f64(double* %p, <2 x float>* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <2 x float> @test_v2f32_f64_helper(double %2) %4 = fadd <2 x float> %3, %3 @@ -245,7 +245,7 @@ define void @test_v2f32_f64(double* %p, <2 x float>* %q) { declare <2 x float> @test_v2f32_v1i64_helper(<1 x i64> %p) define void @test_v2f32_v1i64(<1 x i64>* %p, <2 x float>* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call <2 x float> @test_v2f32_v1i64_helper(<1 x i64> %2) %4 = fadd <2 x float> %3, %3 @@ -258,7 +258,7 @@ declare <2 x float> @test_v2f32_v2i32_helper(<2 x i32> %p) define void @test_v2f32_v2i32(<2 x i32>* %p, <2 x float>* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call <2 x float> @test_v2f32_v2i32_helper(<2 x i32> %2) %4 = fadd <2 x float> %3, %3 @@ -271,7 +271,7 @@ declare <2 x float> @test_v2f32_v4i16_helper(<4 x i16> %p) define void @test_v2f32_v4i16(<4 x i16>* %p, <2 x float>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4h ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call <2 x float> @test_v2f32_v4i16_helper(<4 x i16> %2) %4 = fadd <2 x float> %3, %3 @@ -284,7 +284,7 @@ declare <2 x float> @test_v2f32_v8i8_helper(<8 x i8> %p) define void @test_v2f32_v8i8(<8 x i8>* %p, <2 x float>* %q) { ; CHECK: rev64 v{{[0-9]+}}.8b ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call <2 x float> @test_v2f32_v8i8_helper(<8 x i8> %2) %4 = fadd <2 x float> %3, %3 @@ -296,7 +296,7 @@ define void @test_v2f32_v8i8(<8 x i8>* %p, <2 x float>* %q) { declare <2 x i32> @test_v2i32_i64_helper(i64 %p) define void @test_v2i32_i64(i64* %p, <2 x i32>* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <2 x i32> @test_v2i32_i64_helper(i64 %2) %4 = add <2 x i32> %3, %3 @@ -308,7 +308,7 @@ define void @test_v2i32_i64(i64* %p, <2 x i32>* %q) { declare <2 x i32> @test_v2i32_f64_helper(double %p) define void @test_v2i32_f64(double* %p, <2 x i32>* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <2 x i32> @test_v2i32_f64_helper(double %2) %4 = add <2 x i32> %3, %3 @@ -320,7 +320,7 @@ define void @test_v2i32_f64(double* %p, <2 x i32>* %q) { declare <2 x i32> @test_v2i32_v1i64_helper(<1 x i64> %p) define void @test_v2i32_v1i64(<1 x i64>* %p, <2 x i32>* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call <2 x i32> @test_v2i32_v1i64_helper(<1 x i64> %2) %4 = add <2 x i32> %3, %3 @@ -333,7 +333,7 @@ declare <2 x i32> @test_v2i32_v2f32_helper(<2 x float> %p) define void @test_v2i32_v2f32(<2 x float>* %p, <2 x i32>* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call <2 x i32> @test_v2i32_v2f32_helper(<2 x float> %2) %4 = add <2 x i32> %3, %3 @@ -346,7 +346,7 @@ declare <2 x i32> @test_v2i32_v4i16_helper(<4 x i16> %p) define void @test_v2i32_v4i16(<4 x i16>* %p, <2 x i32>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4h ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call <2 x i32> @test_v2i32_v4i16_helper(<4 x i16> %2) %4 = add <2 x i32> %3, %3 @@ -359,7 +359,7 @@ declare <2 x i32> @test_v2i32_v8i8_helper(<8 x i8> %p) define void @test_v2i32_v8i8(<8 x i8>* %p, <2 x i32>* %q) { ; CHECK: rev64 v{{[0-9]+}}.8b ; CHECK: rev64 v{{[0-9]+}}.2s - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call <2 x i32> @test_v2i32_v8i8_helper(<8 x i8> %2) %4 = add <2 x i32> %3, %3 @@ -371,7 +371,7 @@ define void @test_v2i32_v8i8(<8 x i8>* %p, <2 x i32>* %q) { declare <4 x i16> @test_v4i16_i64_helper(i64 %p) define void @test_v4i16_i64(i64* %p, <4 x i16>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4h - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <4 x i16> @test_v4i16_i64_helper(i64 %2) %4 = add <4 x i16> %3, %3 @@ -383,7 +383,7 @@ define void @test_v4i16_i64(i64* %p, <4 x i16>* %q) { declare <4 x i16> @test_v4i16_f64_helper(double %p) define void @test_v4i16_f64(double* %p, <4 x i16>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4h - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <4 x i16> @test_v4i16_f64_helper(double %2) %4 = add <4 x i16> %3, %3 @@ -395,7 +395,7 @@ define void @test_v4i16_f64(double* %p, <4 x i16>* %q) { declare <4 x i16> @test_v4i16_v1i64_helper(<1 x i64> %p) define void @test_v4i16_v1i64(<1 x i64>* %p, <4 x i16>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4h - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call <4 x i16> @test_v4i16_v1i64_helper(<1 x i64> %2) %4 = add <4 x i16> %3, %3 @@ -408,7 +408,7 @@ declare <4 x i16> @test_v4i16_v2f32_helper(<2 x float> %p) define void @test_v4i16_v2f32(<2 x float>* %p, <4 x i16>* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: rev64 v{{[0-9]+}}.4h - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call <4 x i16> @test_v4i16_v2f32_helper(<2 x float> %2) %4 = add <4 x i16> %3, %3 @@ -421,7 +421,7 @@ declare <4 x i16> @test_v4i16_v2i32_helper(<2 x i32> %p) define void @test_v4i16_v2i32(<2 x i32>* %p, <4 x i16>* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: rev64 v{{[0-9]+}}.4h - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call <4 x i16> @test_v4i16_v2i32_helper(<2 x i32> %2) %4 = add <4 x i16> %3, %3 @@ -434,7 +434,7 @@ declare <4 x i16> @test_v4i16_v8i8_helper(<8 x i8> %p) define void @test_v4i16_v8i8(<8 x i8>* %p, <4 x i16>* %q) { ; CHECK: rev64 v{{[0-9]+}}.8b ; CHECK: rev64 v{{[0-9]+}}.4h - %1 = load <8 x i8>* %p + %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call <4 x i16> @test_v4i16_v8i8_helper(<8 x i8> %2) %4 = add <4 x i16> %3, %3 @@ -446,7 +446,7 @@ define void @test_v4i16_v8i8(<8 x i8>* %p, <4 x i16>* %q) { declare <8 x i8> @test_v8i8_i64_helper(i64 %p) define void @test_v8i8_i64(i64* %p, <8 x i8>* %q) { ; CHECK: rev64 v{{[0-9]+}}.8b - %1 = load i64* %p + %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <8 x i8> @test_v8i8_i64_helper(i64 %2) %4 = add <8 x i8> %3, %3 @@ -458,7 +458,7 @@ define void @test_v8i8_i64(i64* %p, <8 x i8>* %q) { declare <8 x i8> @test_v8i8_f64_helper(double %p) define void @test_v8i8_f64(double* %p, <8 x i8>* %q) { ; CHECK: rev64 v{{[0-9]+}}.8b - %1 = load double* %p + %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <8 x i8> @test_v8i8_f64_helper(double %2) %4 = add <8 x i8> %3, %3 @@ -470,7 +470,7 @@ define void @test_v8i8_f64(double* %p, <8 x i8>* %q) { declare <8 x i8> @test_v8i8_v1i64_helper(<1 x i64> %p) define void @test_v8i8_v1i64(<1 x i64>* %p, <8 x i8>* %q) { ; CHECK: rev64 v{{[0-9]+}}.8b - %1 = load <1 x i64>* %p + %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call <8 x i8> @test_v8i8_v1i64_helper(<1 x i64> %2) %4 = add <8 x i8> %3, %3 @@ -483,7 +483,7 @@ declare <8 x i8> @test_v8i8_v2f32_helper(<2 x float> %p) define void @test_v8i8_v2f32(<2 x float>* %p, <8 x i8>* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: rev64 v{{[0-9]+}}.8b - %1 = load <2 x float>* %p + %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call <8 x i8> @test_v8i8_v2f32_helper(<2 x float> %2) %4 = add <8 x i8> %3, %3 @@ -496,7 +496,7 @@ declare <8 x i8> @test_v8i8_v2i32_helper(<2 x i32> %p) define void @test_v8i8_v2i32(<2 x i32>* %p, <8 x i8>* %q) { ; CHECK: rev64 v{{[0-9]+}}.2s ; CHECK: rev64 v{{[0-9]+}}.8b - %1 = load <2 x i32>* %p + %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call <8 x i8> @test_v8i8_v2i32_helper(<2 x i32> %2) %4 = add <8 x i8> %3, %3 @@ -509,7 +509,7 @@ declare <8 x i8> @test_v8i8_v4i16_helper(<4 x i16> %p) define void @test_v8i8_v4i16(<4 x i16>* %p, <8 x i8>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4h ; CHECK: rev64 v{{[0-9]+}}.8b - %1 = load <4 x i16>* %p + %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call <8 x i8> @test_v8i8_v4i16_helper(<4 x i16> %2) %4 = add <8 x i8> %3, %3 @@ -521,7 +521,7 @@ define void @test_v8i8_v4i16(<4 x i16>* %p, <8 x i8>* %q) { declare fp128 @test_f128_v2f64_helper(<2 x double> %p) define void @test_f128_v2f64(<2 x double>* %p, fp128* %q) { ; CHECK: ext - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call fp128 @test_f128_v2f64_helper(<2 x double> %2) %4 = fadd fp128 %3, %3 @@ -533,7 +533,7 @@ define void @test_f128_v2f64(<2 x double>* %p, fp128* %q) { declare fp128 @test_f128_v2i64_helper(<2 x i64> %p) define void @test_f128_v2i64(<2 x i64>* %p, fp128* %q) { ; CHECK: ext - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call fp128 @test_f128_v2i64_helper(<2 x i64> %2) %4 = fadd fp128 %3, %3 @@ -546,7 +546,7 @@ declare fp128 @test_f128_v4f32_helper(<4 x float> %p) define void @test_f128_v4f32(<4 x float>* %p, fp128* %q) { ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call fp128 @test_f128_v4f32_helper(<4 x float> %2) %4 = fadd fp128 %3, %3 @@ -559,7 +559,7 @@ declare fp128 @test_f128_v4i32_helper(<4 x i32> %p) define void @test_f128_v4i32(<4 x i32>* %p, fp128* %q) { ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call fp128 @test_f128_v4i32_helper(<4 x i32> %2) %4 = fadd fp128 %3, %3 @@ -572,7 +572,7 @@ declare fp128 @test_f128_v8i16_helper(<8 x i16> %p) define void @test_f128_v8i16(<8 x i16>* %p, fp128* %q) { ; CHECK: rev64 v{{[0-9]+}}.8h ; CHECK: ext - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call fp128 @test_f128_v8i16_helper(<8 x i16> %2) %4 = fadd fp128 %3, %3 @@ -585,7 +585,7 @@ declare fp128 @test_f128_v16i8_helper(<16 x i8> %p) define void @test_f128_v16i8(<16 x i8>* %p, fp128* %q) { ; CHECK: rev64 v{{[0-9]+}}.16b ; CHECK: ext - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call fp128 @test_f128_v16i8_helper(<16 x i8> %2) %4 = fadd fp128 %3, %3 @@ -597,7 +597,7 @@ define void @test_f128_v16i8(<16 x i8>* %p, fp128* %q) { declare <2 x double> @test_v2f64_f128_helper(fp128 %p) define void @test_v2f64_f128(fp128* %p, <2 x double>* %q) { ; CHECK: ext - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <2 x double> @test_v2f64_f128_helper(fp128 %2) %4 = fadd <2 x double> %3, %3 @@ -610,7 +610,7 @@ declare <2 x double> @test_v2f64_v2i64_helper(<2 x i64> %p) define void @test_v2f64_v2i64(<2 x i64>* %p, <2 x double>* %q) { ; CHECK: ext ; CHECK: ext - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <2 x double> @test_v2f64_v2i64_helper(<2 x i64> %2) %4 = fadd <2 x double> %3, %3 @@ -624,7 +624,7 @@ define void @test_v2f64_v4f32(<4 x float>* %p, <2 x double>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext ; CHECK: ext - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <2 x double> @test_v2f64_v4f32_helper(<4 x float> %2) %4 = fadd <2 x double> %3, %3 @@ -638,7 +638,7 @@ define void @test_v2f64_v4i32(<4 x i32>* %p, <2 x double>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext ; CHECK: ext - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <2 x double> @test_v2f64_v4i32_helper(<4 x i32> %2) %4 = fadd <2 x double> %3, %3 @@ -652,7 +652,7 @@ define void @test_v2f64_v8i16(<8 x i16>* %p, <2 x double>* %q) { ; CHECK: rev64 v{{[0-9]+}}.8h ; CHECK: ext ; CHECK: ext - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <2 x double> @test_v2f64_v8i16_helper(<8 x i16> %2) %4 = fadd <2 x double> %3, %3 @@ -666,7 +666,7 @@ define void @test_v2f64_v16i8(<16 x i8>* %p, <2 x double>* %q) { ; CHECK: rev64 v{{[0-9]+}}.16b ; CHECK: ext ; CHECK: ext - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <2 x double> @test_v2f64_v16i8_helper(<16 x i8> %2) %4 = fadd <2 x double> %3, %3 @@ -678,7 +678,7 @@ define void @test_v2f64_v16i8(<16 x i8>* %p, <2 x double>* %q) { declare <2 x i64> @test_v2i64_f128_helper(fp128 %p) define void @test_v2i64_f128(fp128* %p, <2 x i64>* %q) { ; CHECK: ext - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <2 x i64> @test_v2i64_f128_helper(fp128 %2) %4 = add <2 x i64> %3, %3 @@ -691,7 +691,7 @@ declare <2 x i64> @test_v2i64_v2f64_helper(<2 x double> %p) define void @test_v2i64_v2f64(<2 x double>* %p, <2 x i64>* %q) { ; CHECK: ext ; CHECK: ext - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <2 x i64> @test_v2i64_v2f64_helper(<2 x double> %2) %4 = add <2 x i64> %3, %3 @@ -705,7 +705,7 @@ define void @test_v2i64_v4f32(<4 x float>* %p, <2 x i64>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext ; CHECK: ext - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <2 x i64> @test_v2i64_v4f32_helper(<4 x float> %2) %4 = add <2 x i64> %3, %3 @@ -719,7 +719,7 @@ define void @test_v2i64_v4i32(<4 x i32>* %p, <2 x i64>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext ; CHECK: ext - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <2 x i64> @test_v2i64_v4i32_helper(<4 x i32> %2) %4 = add <2 x i64> %3, %3 @@ -733,7 +733,7 @@ define void @test_v2i64_v8i16(<8 x i16>* %p, <2 x i64>* %q) { ; CHECK: rev64 v{{[0-9]+}}.8h ; CHECK: ext ; CHECK: ext - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <2 x i64> @test_v2i64_v8i16_helper(<8 x i16> %2) %4 = add <2 x i64> %3, %3 @@ -747,7 +747,7 @@ define void @test_v2i64_v16i8(<16 x i8>* %p, <2 x i64>* %q) { ; CHECK: rev64 v{{[0-9]+}}.16b ; CHECK: ext ; CHECK: ext - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <2 x i64> @test_v2i64_v16i8_helper(<16 x i8> %2) %4 = add <2 x i64> %3, %3 @@ -760,7 +760,7 @@ declare <4 x float> @test_v4f32_f128_helper(fp128 %p) define void @test_v4f32_f128(fp128* %p, <4 x float>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <4 x float> @test_v4f32_f128_helper(fp128 %2) %4 = fadd <4 x float> %3, %3 @@ -774,7 +774,7 @@ define void @test_v4f32_v2f64(<2 x double>* %p, <4 x float>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <4 x float> @test_v4f32_v2f64_helper(<2 x double> %2) %4 = fadd <4 x float> %3, %3 @@ -788,7 +788,7 @@ define void @test_v4f32_v2i64(<2 x i64>* %p, <4 x float>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <4 x float> @test_v4f32_v2i64_helper(<2 x i64> %2) %4 = fadd <4 x float> %3, %3 @@ -803,7 +803,7 @@ define void @test_v4f32_v4i32(<4 x i32>* %p, <4 x float>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <4 x float> @test_v4f32_v4i32_helper(<4 x i32> %2) %4 = fadd <4 x float> %3, %3 @@ -818,7 +818,7 @@ define void @test_v4f32_v8i16(<8 x i16>* %p, <4 x float>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <4 x float> @test_v4f32_v8i16_helper(<8 x i16> %2) %4 = fadd <4 x float> %3, %3 @@ -833,7 +833,7 @@ define void @test_v4f32_v16i8(<16 x i8>* %p, <4 x float>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <4 x float> @test_v4f32_v16i8_helper(<16 x i8> %2) %4 = fadd <4 x float> %3, %3 @@ -846,7 +846,7 @@ declare <4 x i32> @test_v4i32_f128_helper(fp128 %p) define void @test_v4i32_f128(fp128* %p, <4 x i32>* %q) { ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <4 x i32> @test_v4i32_f128_helper(fp128 %2) %4 = add <4 x i32> %3, %3 @@ -860,7 +860,7 @@ define void @test_v4i32_v2f64(<2 x double>* %p, <4 x i32>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <4 x i32> @test_v4i32_v2f64_helper(<2 x double> %2) %4 = add <4 x i32> %3, %3 @@ -874,7 +874,7 @@ define void @test_v4i32_v2i64(<2 x i64>* %p, <4 x i32>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <4 x i32> @test_v4i32_v2i64_helper(<2 x i64> %2) %4 = add <4 x i32> %3, %3 @@ -889,7 +889,7 @@ define void @test_v4i32_v4f32(<4 x float>* %p, <4 x i32>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <4 x i32> @test_v4i32_v4f32_helper(<4 x float> %2) %4 = add <4 x i32> %3, %3 @@ -904,7 +904,7 @@ define void @test_v4i32_v8i16(<8 x i16>* %p, <4 x i32>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <4 x i32> @test_v4i32_v8i16_helper(<8 x i16> %2) %4 = add <4 x i32> %3, %3 @@ -919,7 +919,7 @@ define void @test_v4i32_v16i8(<16 x i8>* %p, <4 x i32>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.4s ; CHECK: ext - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <4 x i32> @test_v4i32_v16i8_helper(<16 x i8> %2) %4 = add <4 x i32> %3, %3 @@ -932,7 +932,7 @@ declare <8 x i16> @test_v8i16_f128_helper(fp128 %p) define void @test_v8i16_f128(fp128* %p, <8 x i16>* %q) { ; CHECK: rev64 v{{[0-9]+}}.8h ; CHECK: ext - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <8 x i16> @test_v8i16_f128_helper(fp128 %2) %4 = add <8 x i16> %3, %3 @@ -946,7 +946,7 @@ define void @test_v8i16_v2f64(<2 x double>* %p, <8 x i16>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.8h ; CHECK: ext - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <8 x i16> @test_v8i16_v2f64_helper(<2 x double> %2) %4 = add <8 x i16> %3, %3 @@ -960,7 +960,7 @@ define void @test_v8i16_v2i64(<2 x i64>* %p, <8 x i16>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.8h ; CHECK: ext - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <8 x i16> @test_v8i16_v2i64_helper(<2 x i64> %2) %4 = add <8 x i16> %3, %3 @@ -975,7 +975,7 @@ define void @test_v8i16_v4f32(<4 x float>* %p, <8 x i16>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.8h ; CHECK: ext - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <8 x i16> @test_v8i16_v4f32_helper(<4 x float> %2) %4 = add <8 x i16> %3, %3 @@ -990,7 +990,7 @@ define void @test_v8i16_v4i32(<4 x i32>* %p, <8 x i16>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.8h ; CHECK: ext - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <8 x i16> @test_v8i16_v4i32_helper(<4 x i32> %2) %4 = add <8 x i16> %3, %3 @@ -1005,7 +1005,7 @@ define void @test_v8i16_v16i8(<16 x i8>* %p, <8 x i16>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.8h ; CHECK: ext - %1 = load <16 x i8>* %p + %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <8 x i16> @test_v8i16_v16i8_helper(<16 x i8> %2) %4 = add <8 x i16> %3, %3 @@ -1018,7 +1018,7 @@ declare <16 x i8> @test_v16i8_f128_helper(fp128 %p) define void @test_v16i8_f128(fp128* %p, <16 x i8>* %q) { ; CHECK: rev64 v{{[0-9]+}}.16b ; CHECK: ext - %1 = load fp128* %p + %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <16 x i8> @test_v16i8_f128_helper(fp128 %2) %4 = add <16 x i8> %3, %3 @@ -1032,7 +1032,7 @@ define void @test_v16i8_v2f64(<2 x double>* %p, <16 x i8>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.16b ; CHECK: ext - %1 = load <2 x double>* %p + %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <16 x i8> @test_v16i8_v2f64_helper(<2 x double> %2) %4 = add <16 x i8> %3, %3 @@ -1046,7 +1046,7 @@ define void @test_v16i8_v2i64(<2 x i64>* %p, <16 x i8>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.16b ; CHECK: ext - %1 = load <2 x i64>* %p + %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <16 x i8> @test_v16i8_v2i64_helper(<2 x i64> %2) %4 = add <16 x i8> %3, %3 @@ -1061,7 +1061,7 @@ define void @test_v16i8_v4f32(<4 x float>* %p, <16 x i8>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.16b ; CHECK: ext - %1 = load <4 x float>* %p + %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <16 x i8> @test_v16i8_v4f32_helper(<4 x float> %2) %4 = add <16 x i8> %3, %3 @@ -1076,7 +1076,7 @@ define void @test_v16i8_v4i32(<4 x i32>* %p, <16 x i8>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.16b ; CHECK: ext - %1 = load <4 x i32>* %p + %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <16 x i8> @test_v16i8_v4i32_helper(<4 x i32> %2) %4 = add <16 x i8> %3, %3 @@ -1091,7 +1091,7 @@ define void @test_v16i8_v8i16(<8 x i16>* %p, <16 x i8>* %q) { ; CHECK: ext ; CHECK: rev64 v{{[0-9]+}}.16b ; CHECK: ext - %1 = load <8 x i16>* %p + %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <16 x i8> @test_v16i8_v8i16_helper(<8 x i16> %2) %4 = add <16 x i8> %3, %3 diff --git a/test/CodeGen/AArch64/arm64-big-stack.ll b/test/CodeGen/AArch64/arm64-big-stack.ll index 3f91bb3c2..c9acbc5 100644 --- a/test/CodeGen/AArch64/arm64-big-stack.ll +++ b/test/CodeGen/AArch64/arm64-big-stack.ll @@ -13,7 +13,7 @@ target triple = "arm64-apple-macosx10" define void @foo() nounwind ssp { entry: %buffer = alloca [33554432 x i8], align 1 - %arraydecay = getelementptr inbounds [33554432 x i8]* %buffer, i64 0, i64 0 + %arraydecay = getelementptr inbounds [33554432 x i8], [33554432 x i8]* %buffer, i64 0, i64 0 call void @doit(i8* %arraydecay) nounwind ret void } diff --git a/test/CodeGen/AArch64/arm64-bitfield-extract.ll b/test/CodeGen/AArch64/arm64-bitfield-extract.ll index 112efdd..5dca929 100644 --- a/test/CodeGen/AArch64/arm64-bitfield-extract.ll +++ b/test/CodeGen/AArch64/arm64-bitfield-extract.ll @@ -12,8 +12,8 @@ define void @foo(%struct.X* nocapture %x, %struct.Y* nocapture %y) nounwind opts ; CHECK: ret %tmp = bitcast %struct.X* %x to i32* - %tmp1 = load i32* %tmp, align 4 - %b = getelementptr inbounds %struct.Y* %y, i64 0, i32 1 + %tmp1 = load i32, i32* %tmp, align 4 + %b = getelementptr inbounds %struct.Y, %struct.Y* %y, i64 0, i32 1 %bf.clear = lshr i32 %tmp1, 3 %bf.clear.lobit = and i32 %bf.clear, 1 %frombool = trunc i32 %bf.clear.lobit to i8 @@ -46,8 +46,8 @@ define void @fct1(%struct.Z* nocapture %x, %struct.A* nocapture %y) nounwind opt ; CHECK: ret %tmp = bitcast %struct.Z* %x to i64* - %tmp1 = load i64* %tmp, align 4 - %b = getelementptr inbounds %struct.A* %y, i64 0, i32 0 + %tmp1 = load i64, i64* %tmp, align 4 + %b = getelementptr inbounds %struct.A, %struct.A* %y, i64 0, i32 0 %bf.clear = lshr i64 %tmp1, 3 %bf.clear.lobit = and i64 %bf.clear, 1 store i64 %bf.clear.lobit, i64* %b, align 8 @@ -77,7 +77,7 @@ entry: ; CHECK-NEXT: bfxil [[REG1]], x1, #16, #24 ; CHECK-NEXT: str [[REG1]], ; CHECK-NEXT: ret - %0 = load i64* %y, align 8 + %0 = load i64, i64* %y, align 8 %and = and i64 %0, -16777216 %shr = lshr i64 %x, 16 %and1 = and i64 %shr, 16777215 @@ -93,7 +93,7 @@ entry: ; CHECK-NEXT: bfxil [[REG1]], w1, #16, #3 ; CHECK-NEXT: str [[REG1]], ; CHECK-NEXT: ret - %0 = load i32* %y, align 8 + %0 = load i32, i32* %y, align 8 %and = and i32 %0, -8 %shr = lshr i32 %x, 16 %and1 = and i32 %shr, 7 @@ -112,7 +112,7 @@ entry: ; CHECK-NEXT: lsr [[REG2:w[0-9]+]], [[REG1]], #2 ; CHECK-NEXT: str [[REG2]], ; CHECK-NEXT: ret - %0 = load i32* %y, align 8 + %0 = load i32, i32* %y, align 8 %and = and i32 %0, -8 %shr = lshr i32 %x, 16 %and1 = and i32 %shr, 7 @@ -133,7 +133,7 @@ entry: ; CHECK-NEXT: lsl [[REG2:w[0-9]+]], [[REG1]], #2 ; CHECK-NEXT: str [[REG2]], ; CHECK-NEXT: ret - %0 = load i32* %y, align 8 + %0 = load i32, i32* %y, align 8 %and = and i32 %0, -8 %shr = lshr i32 %x, 16 %and1 = and i32 %shr, 7 @@ -155,7 +155,7 @@ entry: ; CHECK-NEXT: lsr [[REG2:x[0-9]+]], [[REG1]], #2 ; CHECK-NEXT: str [[REG2]], ; CHECK-NEXT: ret - %0 = load i64* %y, align 8 + %0 = load i64, i64* %y, align 8 %and = and i64 %0, -8 %shr = lshr i64 %x, 16 %and1 = and i64 %shr, 7 @@ -177,7 +177,7 @@ entry: ; CHECK-NEXT: lsl [[REG2:x[0-9]+]], [[REG1]], #2 ; CHECK-NEXT: str [[REG2]], ; CHECK-NEXT: ret - %0 = load i64* %y, align 8 + %0 = load i64, i64* %y, align 8 %and = and i64 %0, -8 %shr = lshr i64 %x, 16 %and1 = and i64 %shr, 7 @@ -198,7 +198,7 @@ entry: ; CHECK-NEXT: lsl [[REG2:w[0-9]+]], [[REG1]], #2 ; CHECK-NEXT: str [[REG2]], ; CHECK-NEXT: ret - %0 = load i32* %y, align 8 + %0 = load i32, i32* %y, align 8 %and = and i32 %0, -8 %and1 = and i32 %x, 7 %or = or i32 %and, %and1 @@ -218,7 +218,7 @@ entry: ; CHECK-NEXT: lsl [[REG2:x[0-9]+]], [[REG1]], #2 ; CHECK-NEXT: str [[REG2]], ; CHECK-NEXT: ret - %0 = load i64* %y, align 8 + %0 = load i64, i64* %y, align 8 %and = and i64 %0, -8 %and1 = and i64 %x, 7 %or = or i64 %and, %and1 @@ -247,7 +247,7 @@ entry: ; CHECK-NEXT: ubfx [[REG2:w[0-9]+]], [[REG1]], #2, #28 ; CHECK-NEXT: str [[REG2]], ; CHECK-NEXT: ret - %0 = load i32* %y, align 8 + %0 = load i32, i32* %y, align 8 %and = and i32 %0, -8 %shr = lshr i32 %x, 16 %and1 = and i32 %shr, 7 @@ -270,7 +270,7 @@ entry: ; CHECK-NEXT: ubfx [[REG2:x[0-9]+]], [[REG1]], #2, #60 ; CHECK-NEXT: str [[REG2]], ; CHECK-NEXT: ret - %0 = load i64* %y, align 8 + %0 = load i64, i64* %y, align 8 %and = and i64 %0, -8 %shr = lshr i64 %x, 16 %and1 = and i64 %shr, 7 @@ -296,7 +296,7 @@ entry: ; CHECK-NEXT: lsl [[REG3:w[0-9]+]], [[REG2]], #2 ; CHECK-NEXT: str [[REG3]], ; CHECK-NEXT: ret - %0 = load i32* %y, align 8 + %0 = load i32, i32* %y, align 8 %and = and i32 %0, -256 %shr = lshr i32 %x, 16 %and1 = and i32 %shr, 255 @@ -326,7 +326,7 @@ entry: ; CHECK-NEXT: lsl [[REG3:x[0-9]+]], [[REG2]], #2 ; CHECK-NEXT: str [[REG3]], ; CHECK-NEXT: ret - %0 = load i64* %y, align 8 + %0 = load i64, i64* %y, align 8 %and = and i64 %0, -256 %shr = lshr i64 %x, 16 %and1 = and i64 %shr, 255 @@ -357,7 +357,7 @@ entry: ; CHECK-NEXT: ubfx [[REG3:w[0-9]+]], [[REG2]], #2, #28 ; CHECK-NEXT: str [[REG3]], ; CHECK-NEXT: ret - %0 = load i32* %y, align 8 + %0 = load i32, i32* %y, align 8 %and = and i32 %0, 1737056 %shr = lshr i32 %x, 16 %and1 = and i32 %shr, 7 @@ -386,7 +386,7 @@ entry: ; CHECK-NEXT: ubfx [[REG3:x[0-9]+]], [[REG2]], #2, #60 ; CHECK-NEXT: str [[REG3]], ; CHECK-NEXT: ret - %0 = load i64* %y, align 8 + %0 = load i64, i64* %y, align 8 %and = and i64 %0, 1737056 %shr = lshr i64 %x, 16 %and1 = and i64 %shr, 7 @@ -421,8 +421,8 @@ entry: br i1 %tobool, label %if.end, label %if.then if.then: ; preds = %entry - %arrayidx3 = getelementptr inbounds [65536 x i8]* @first_ones, i64 0, i64 %x.sroa.5.0.extract.shift - %0 = load i8* %arrayidx3, align 1 + %arrayidx3 = getelementptr inbounds [65536 x i8], [65536 x i8]* @first_ones, i64 0, i64 %x.sroa.5.0.extract.shift + %0 = load i8, i8* %arrayidx3, align 1 %conv = zext i8 %0 to i32 br label %return @@ -443,8 +443,8 @@ if.then7: ; preds = %if.end ; CHECK-NOT: and ; CHECK-NOT: ubfm %idxprom10 = and i64 %x.sroa.3.0.extract.shift, 65535 - %arrayidx11 = getelementptr inbounds [65536 x i8]* @first_ones, i64 0, i64 %idxprom10 - %1 = load i8* %arrayidx11, align 1 + %arrayidx11 = getelementptr inbounds [65536 x i8], [65536 x i8]* @first_ones, i64 0, i64 %idxprom10 + %1 = load i8, i8* %arrayidx11, align 1 %conv12 = zext i8 %1 to i32 %add = add nsw i32 %conv12, 16 br label %return @@ -466,8 +466,8 @@ if.then17: ; preds = %if.end13 ; CHECK-NOT: and ; CHECK-NOT: ubfm %idxprom20 = and i64 %x.sroa.1.0.extract.shift, 65535 - %arrayidx21 = getelementptr inbounds [65536 x i8]* @first_ones, i64 0, i64 %idxprom20 - %2 = load i8* %arrayidx21, align 1 + %arrayidx21 = getelementptr inbounds [65536 x i8], [65536 x i8]* @first_ones, i64 0, i64 %idxprom20 + %2 = load i8, i8* %arrayidx21, align 1 %conv22 = zext i8 %2 to i32 %add23 = add nsw i32 %conv22, 32 br label %return @@ -509,8 +509,8 @@ define i64 @fct21(i64 %x) { entry: %shr = lshr i64 %x, 4 %and = and i64 %shr, 15 - %arrayidx = getelementptr inbounds [8 x [64 x i64]]* @arr, i64 0, i64 0, i64 %and - %0 = load i64* %arrayidx, align 8 + %arrayidx = getelementptr inbounds [8 x [64 x i64]], [8 x [64 x i64]]* @arr, i64 0, i64 0, i64 %and + %0 = load i64, i64* %arrayidx, align 8 ret i64 %0 } diff --git a/test/CodeGen/AArch64/arm64-blockaddress.ll b/test/CodeGen/AArch64/arm64-blockaddress.ll index ac4f19e..5df8402 100644 --- a/test/CodeGen/AArch64/arm64-blockaddress.ll +++ b/test/CodeGen/AArch64/arm64-blockaddress.ll @@ -25,6 +25,6 @@ entry: br label %mylabel mylabel: - %tmp = load volatile i64* %recover, align 8 + %tmp = load volatile i64, i64* %recover, align 8 ret i64 %tmp } diff --git a/test/CodeGen/AArch64/arm64-call-tailcalls.ll b/test/CodeGen/AArch64/arm64-call-tailcalls.ll index 487c1d9..71d9327 100644 --- a/test/CodeGen/AArch64/arm64-call-tailcalls.ll +++ b/test/CodeGen/AArch64/arm64-call-tailcalls.ll @@ -9,7 +9,7 @@ define void @t2() { ; CHECK: ldr x[[ADDR:[0-9]+]], [x[[GOTADDR]], _t@GOTPAGEOFF] ; CHECK: ldr x[[DEST:[0-9]+]], [x[[ADDR]]] ; CHECK: br x[[DEST]] - %tmp = load i32 ()** @t + %tmp = load i32 ()*, i32 ()** @t %tmp.upgrd.2 = tail call i32 %tmp() ret void } diff --git a/test/CodeGen/AArch64/arm64-cast-opt.ll b/test/CodeGen/AArch64/arm64-cast-opt.ll index 65a871d..463add5 100644 --- a/test/CodeGen/AArch64/arm64-cast-opt.ll +++ b/test/CodeGen/AArch64/arm64-cast-opt.ll @@ -11,12 +11,12 @@ define zeroext i8 @foo(i32 %i1, i32 %i2) { ; CHECK-NOT: and entry: %idxprom = sext i32 %i1 to i64 - %0 = load i8** @block, align 8 - %arrayidx = getelementptr inbounds i8* %0, i64 %idxprom - %1 = load i8* %arrayidx, align 1 + %0 = load i8*, i8** @block, align 8 + %arrayidx = getelementptr inbounds i8, i8* %0, i64 %idxprom + %1 = load i8, i8* %arrayidx, align 1 %idxprom1 = sext i32 %i2 to i64 - %arrayidx2 = getelementptr inbounds i8* %0, i64 %idxprom1 - %2 = load i8* %arrayidx2, align 1 + %arrayidx2 = getelementptr inbounds i8, i8* %0, i64 %idxprom1 + %2 = load i8, i8* %arrayidx2, align 1 %cmp = icmp eq i8 %1, %2 br i1 %cmp, label %return, label %if.then diff --git a/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll b/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll index b032d9c..4e47ab6 100644 --- a/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll +++ b/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll @@ -21,7 +21,7 @@ target triple = "arm64-apple-ios7.0.0" ; CHECK-NEXT b.cc define i32 @Maze1() nounwind ssp { entry: - %0 = load i64* @channelColumns, align 8, !tbaa !0 + %0 = load i64, i64* @channelColumns, align 8, !tbaa !0 %cmp90 = icmp eq i64 %0, 0 br i1 %cmp90, label %for.end, label %for.body @@ -29,51 +29,51 @@ for.body: ; preds = %for.inc, %entry %1 = phi i64 [ %0, %entry ], [ %37, %for.inc ] %i.092 = phi i64 [ 1, %entry ], [ %inc53, %for.inc ] %numLeft.091 = phi i32 [ 0, %entry ], [ %numLeft.1, %for.inc ] - %2 = load i8** @mazeRoute, align 8, !tbaa !3 - %arrayidx = getelementptr inbounds i8* %2, i64 %i.092 - %3 = load i8* %arrayidx, align 1, !tbaa !1 + %2 = load i8*, i8** @mazeRoute, align 8, !tbaa !3 + %arrayidx = getelementptr inbounds i8, i8* %2, i64 %i.092 + %3 = load i8, i8* %arrayidx, align 1, !tbaa !1 %tobool = icmp eq i8 %3, 0 br i1 %tobool, label %for.inc, label %if.then if.then: ; preds = %for.body - %4 = load i64** @TOP, align 8, !tbaa !3 - %arrayidx1 = getelementptr inbounds i64* %4, i64 %i.092 - %5 = load i64* %arrayidx1, align 8, !tbaa !0 - %6 = load i64** @netsAssign, align 8, !tbaa !3 - %arrayidx2 = getelementptr inbounds i64* %6, i64 %5 - %7 = load i64* %arrayidx2, align 8, !tbaa !0 - %8 = load i64** @BOT, align 8, !tbaa !3 - %arrayidx3 = getelementptr inbounds i64* %8, i64 %i.092 - %9 = load i64* %arrayidx3, align 8, !tbaa !0 - %arrayidx4 = getelementptr inbounds i64* %6, i64 %9 - %10 = load i64* %arrayidx4, align 8, !tbaa !0 + %4 = load i64*, i64** @TOP, align 8, !tbaa !3 + %arrayidx1 = getelementptr inbounds i64, i64* %4, i64 %i.092 + %5 = load i64, i64* %arrayidx1, align 8, !tbaa !0 + %6 = load i64*, i64** @netsAssign, align 8, !tbaa !3 + %arrayidx2 = getelementptr inbounds i64, i64* %6, i64 %5 + %7 = load i64, i64* %arrayidx2, align 8, !tbaa !0 + %8 = load i64*, i64** @BOT, align 8, !tbaa !3 + %arrayidx3 = getelementptr inbounds i64, i64* %8, i64 %i.092 + %9 = load i64, i64* %arrayidx3, align 8, !tbaa !0 + %arrayidx4 = getelementptr inbounds i64, i64* %6, i64 %9 + %10 = load i64, i64* %arrayidx4, align 8, !tbaa !0 %cmp5 = icmp ugt i64 %i.092, 1 %cmp6 = icmp ugt i64 %10, 1 %or.cond = and i1 %cmp5, %cmp6 br i1 %or.cond, label %land.lhs.true7, label %if.else land.lhs.true7: ; preds = %if.then - %11 = load i64* @channelTracks, align 8, !tbaa !0 + %11 = load i64, i64* @channelTracks, align 8, !tbaa !0 %add = add i64 %11, 1 %call = tail call fastcc i32 @Maze1Mech(i64 %i.092, i64 %add, i64 %10, i64 0, i64 %7, i32 -1, i32 -1) %tobool8 = icmp eq i32 %call, 0 br i1 %tobool8, label %land.lhs.true7.if.else_crit_edge, label %if.then9 land.lhs.true7.if.else_crit_edge: ; preds = %land.lhs.true7 - %.pre = load i64* @channelColumns, align 8, !tbaa !0 + %.pre = load i64, i64* @channelColumns, align 8, !tbaa !0 br label %if.else if.then9: ; preds = %land.lhs.true7 - %12 = load i8** @mazeRoute, align 8, !tbaa !3 - %arrayidx10 = getelementptr inbounds i8* %12, i64 %i.092 + %12 = load i8*, i8** @mazeRoute, align 8, !tbaa !3 + %arrayidx10 = getelementptr inbounds i8, i8* %12, i64 %i.092 store i8 0, i8* %arrayidx10, align 1, !tbaa !1 - %13 = load i64** @TOP, align 8, !tbaa !3 - %arrayidx11 = getelementptr inbounds i64* %13, i64 %i.092 - %14 = load i64* %arrayidx11, align 8, !tbaa !0 + %13 = load i64*, i64** @TOP, align 8, !tbaa !3 + %arrayidx11 = getelementptr inbounds i64, i64* %13, i64 %i.092 + %14 = load i64, i64* %arrayidx11, align 8, !tbaa !0 tail call fastcc void @CleanNet(i64 %14) - %15 = load i64** @BOT, align 8, !tbaa !3 - %arrayidx12 = getelementptr inbounds i64* %15, i64 %i.092 - %16 = load i64* %arrayidx12, align 8, !tbaa !0 + %15 = load i64*, i64** @BOT, align 8, !tbaa !3 + %arrayidx12 = getelementptr inbounds i64, i64* %15, i64 %i.092 + %16 = load i64, i64* %arrayidx12, align 8, !tbaa !0 tail call fastcc void @CleanNet(i64 %16) br label %for.inc @@ -84,23 +84,23 @@ if.else: ; preds = %land.lhs.true7.if.e br i1 %or.cond89, label %land.lhs.true16, label %if.else24 land.lhs.true16: ; preds = %if.else - %18 = load i64* @channelTracks, align 8, !tbaa !0 + %18 = load i64, i64* @channelTracks, align 8, !tbaa !0 %add17 = add i64 %18, 1 %call18 = tail call fastcc i32 @Maze1Mech(i64 %i.092, i64 %add17, i64 %10, i64 0, i64 %7, i32 1, i32 -1) %tobool19 = icmp eq i32 %call18, 0 br i1 %tobool19, label %if.else24, label %if.then20 if.then20: ; preds = %land.lhs.true16 - %19 = load i8** @mazeRoute, align 8, !tbaa !3 - %arrayidx21 = getelementptr inbounds i8* %19, i64 %i.092 + %19 = load i8*, i8** @mazeRoute, align 8, !tbaa !3 + %arrayidx21 = getelementptr inbounds i8, i8* %19, i64 %i.092 store i8 0, i8* %arrayidx21, align 1, !tbaa !1 - %20 = load i64** @TOP, align 8, !tbaa !3 - %arrayidx22 = getelementptr inbounds i64* %20, i64 %i.092 - %21 = load i64* %arrayidx22, align 8, !tbaa !0 + %20 = load i64*, i64** @TOP, align 8, !tbaa !3 + %arrayidx22 = getelementptr inbounds i64, i64* %20, i64 %i.092 + %21 = load i64, i64* %arrayidx22, align 8, !tbaa !0 tail call fastcc void @CleanNet(i64 %21) - %22 = load i64** @BOT, align 8, !tbaa !3 - %arrayidx23 = getelementptr inbounds i64* %22, i64 %i.092 - %23 = load i64* %arrayidx23, align 8, !tbaa !0 + %22 = load i64*, i64** @BOT, align 8, !tbaa !3 + %arrayidx23 = getelementptr inbounds i64, i64* %22, i64 %i.092 + %23 = load i64, i64* %arrayidx23, align 8, !tbaa !0 tail call fastcc void @CleanNet(i64 %23) br label %for.inc @@ -108,7 +108,7 @@ if.else24: ; preds = %land.lhs.true16, %i br i1 %cmp5, label %land.lhs.true26, label %if.else36 land.lhs.true26: ; preds = %if.else24 - %24 = load i64* @channelTracks, align 8, !tbaa !0 + %24 = load i64, i64* @channelTracks, align 8, !tbaa !0 %cmp27 = icmp ult i64 %7, %24 br i1 %cmp27, label %land.lhs.true28, label %if.else36 @@ -119,26 +119,26 @@ land.lhs.true28: ; preds = %land.lhs.true26 br i1 %tobool31, label %if.else36, label %if.then32 if.then32: ; preds = %land.lhs.true28 - %25 = load i8** @mazeRoute, align 8, !tbaa !3 - %arrayidx33 = getelementptr inbounds i8* %25, i64 %i.092 + %25 = load i8*, i8** @mazeRoute, align 8, !tbaa !3 + %arrayidx33 = getelementptr inbounds i8, i8* %25, i64 %i.092 store i8 0, i8* %arrayidx33, align 1, !tbaa !1 - %26 = load i64** @TOP, align 8, !tbaa !3 - %arrayidx34 = getelementptr inbounds i64* %26, i64 %i.092 - %27 = load i64* %arrayidx34, align 8, !tbaa !0 + %26 = load i64*, i64** @TOP, align 8, !tbaa !3 + %arrayidx34 = getelementptr inbounds i64, i64* %26, i64 %i.092 + %27 = load i64, i64* %arrayidx34, align 8, !tbaa !0 tail call fastcc void @CleanNet(i64 %27) - %28 = load i64** @BOT, align 8, !tbaa !3 - %arrayidx35 = getelementptr inbounds i64* %28, i64 %i.092 - %29 = load i64* %arrayidx35, align 8, !tbaa !0 + %28 = load i64*, i64** @BOT, align 8, !tbaa !3 + %arrayidx35 = getelementptr inbounds i64, i64* %28, i64 %i.092 + %29 = load i64, i64* %arrayidx35, align 8, !tbaa !0 tail call fastcc void @CleanNet(i64 %29) br label %for.inc if.else36: ; preds = %land.lhs.true28, %land.lhs.true26, %if.else24 - %30 = load i64* @channelColumns, align 8, !tbaa !0 + %30 = load i64, i64* @channelColumns, align 8, !tbaa !0 %cmp37 = icmp ult i64 %i.092, %30 br i1 %cmp37, label %land.lhs.true38, label %if.else48 land.lhs.true38: ; preds = %if.else36 - %31 = load i64* @channelTracks, align 8, !tbaa !0 + %31 = load i64, i64* @channelTracks, align 8, !tbaa !0 %cmp39 = icmp ult i64 %7, %31 br i1 %cmp39, label %land.lhs.true40, label %if.else48 @@ -149,16 +149,16 @@ land.lhs.true40: ; preds = %land.lhs.true38 br i1 %tobool43, label %if.else48, label %if.then44 if.then44: ; preds = %land.lhs.true40 - %32 = load i8** @mazeRoute, align 8, !tbaa !3 - %arrayidx45 = getelementptr inbounds i8* %32, i64 %i.092 + %32 = load i8*, i8** @mazeRoute, align 8, !tbaa !3 + %arrayidx45 = getelementptr inbounds i8, i8* %32, i64 %i.092 store i8 0, i8* %arrayidx45, align 1, !tbaa !1 - %33 = load i64** @TOP, align 8, !tbaa !3 - %arrayidx46 = getelementptr inbounds i64* %33, i64 %i.092 - %34 = load i64* %arrayidx46, align 8, !tbaa !0 + %33 = load i64*, i64** @TOP, align 8, !tbaa !3 + %arrayidx46 = getelementptr inbounds i64, i64* %33, i64 %i.092 + %34 = load i64, i64* %arrayidx46, align 8, !tbaa !0 tail call fastcc void @CleanNet(i64 %34) - %35 = load i64** @BOT, align 8, !tbaa !3 - %arrayidx47 = getelementptr inbounds i64* %35, i64 %i.092 - %36 = load i64* %arrayidx47, align 8, !tbaa !0 + %35 = load i64*, i64** @BOT, align 8, !tbaa !3 + %arrayidx47 = getelementptr inbounds i64, i64* %35, i64 %i.092 + %36 = load i64, i64* %arrayidx47, align 8, !tbaa !0 tail call fastcc void @CleanNet(i64 %36) br label %for.inc @@ -169,7 +169,7 @@ if.else48: ; preds = %land.lhs.true40, %l for.inc: ; preds = %if.else48, %if.then44, %if.then32, %if.then20, %if.then9, %for.body %numLeft.1 = phi i32 [ %numLeft.091, %if.then9 ], [ %numLeft.091, %if.then20 ], [ %numLeft.091, %if.then32 ], [ %numLeft.091, %if.then44 ], [ %inc, %if.else48 ], [ %numLeft.091, %for.body ] %inc53 = add i64 %i.092, 1 - %37 = load i64* @channelColumns, align 8, !tbaa !0 + %37 = load i64, i64* @channelColumns, align 8, !tbaa !0 %cmp = icmp ugt i64 %inc53, %37 br i1 %cmp, label %for.end, label %for.body diff --git a/test/CodeGen/AArch64/arm64-ccmp.ll b/test/CodeGen/AArch64/arm64-ccmp.ll index 63965f9..ff18f73 100644 --- a/test/CodeGen/AArch64/arm64-ccmp.ll +++ b/test/CodeGen/AArch64/arm64-ccmp.ll @@ -281,9 +281,9 @@ if.end85: sw.bb.i.i: %ref.tr.i.i = phi %str1* [ %0, %sw.bb.i.i ], [ undef, %entry ] - %operands.i.i = getelementptr inbounds %str1* %ref.tr.i.i, i64 0, i32 0, i32 2 + %operands.i.i = getelementptr inbounds %str1, %str1* %ref.tr.i.i, i64 0, i32 0, i32 2 %arrayidx.i.i = bitcast i32* %operands.i.i to %str1** - %0 = load %str1** %arrayidx.i.i, align 8 - %code1.i.i.phi.trans.insert = getelementptr inbounds %str1* %0, i64 0, i32 0, i32 0, i64 16 + %0 = load %str1*, %str1** %arrayidx.i.i, align 8 + %code1.i.i.phi.trans.insert = getelementptr inbounds %str1, %str1* %0, i64 0, i32 0, i32 0, i64 16 br label %sw.bb.i.i } diff --git a/test/CodeGen/AArch64/arm64-code-model-large-abs.ll b/test/CodeGen/AArch64/arm64-code-model-large-abs.ll index 264da2d..9f50fea 100644 --- a/test/CodeGen/AArch64/arm64-code-model-large-abs.ll +++ b/test/CodeGen/AArch64/arm64-code-model-large-abs.ll @@ -18,7 +18,7 @@ define i8* @global_addr() { define i8 @global_i8() { ; CHECK-LABEL: global_i8: - %val = load i8* @var8 + %val = load i8, i8* @var8 ret i8 %val ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8 @@ -29,7 +29,7 @@ define i8 @global_i8() { define i16 @global_i16() { ; CHECK-LABEL: global_i16: - %val = load i16* @var16 + %val = load i16, i16* @var16 ret i16 %val ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16 @@ -40,7 +40,7 @@ define i16 @global_i16() { define i32 @global_i32() { ; CHECK-LABEL: global_i32: - %val = load i32* @var32 + %val = load i32, i32* @var32 ret i32 %val ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32 @@ -51,7 +51,7 @@ define i32 @global_i32() { define i64 @global_i64() { ; CHECK-LABEL: global_i64: - %val = load i64* @var64 + %val = load i64, i64* @var64 ret i64 %val ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64 diff --git a/test/CodeGen/AArch64/arm64-collect-loh-garbage-crash.ll b/test/CodeGen/AArch64/arm64-collect-loh-garbage-crash.ll index 81cee38..e34ef39 100644 --- a/test/CodeGen/AArch64/arm64-collect-loh-garbage-crash.ll +++ b/test/CodeGen/AArch64/arm64-collect-loh-garbage-crash.ll @@ -22,13 +22,13 @@ define void @foo() { entry: br label %if.then83 if.then83: ; preds = %if.end81 - %tmp = load %"class.H4ISP::H4ISPDevice"** @pH4ISPDevice, align 8 + %tmp = load %"class.H4ISP::H4ISPDevice"*, %"class.H4ISP::H4ISPDevice"** @pH4ISPDevice, align 8 %call84 = call i32 @_ZN5H4ISP11H4ISPDevice32ISP_SelectBestMIPIFrequencyIndexEjPj(%"class.H4ISP::H4ISPDevice"* %tmp) #19 tail call void asm sideeffect "", "~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27}"() - %tmp2 = load %"class.H4ISP::H4ISPDevice"** @pH4ISPDevice, align 8 + %tmp2 = load %"class.H4ISP::H4ISPDevice"*, %"class.H4ISP::H4ISPDevice"** @pH4ISPDevice, align 8 tail call void asm sideeffect "", "~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x28}"() - %pCameraManager.i268 = getelementptr inbounds %"class.H4ISP::H4ISPDevice"* %tmp2, i64 0, i32 3 - %tmp3 = load %"class.H4ISP::H4ISPCameraManager"** %pCameraManager.i268, align 8 + %pCameraManager.i268 = getelementptr inbounds %"class.H4ISP::H4ISPDevice", %"class.H4ISP::H4ISPDevice"* %tmp2, i64 0, i32 3 + %tmp3 = load %"class.H4ISP::H4ISPCameraManager"*, %"class.H4ISP::H4ISPCameraManager"** %pCameraManager.i268, align 8 %tobool.i269 = icmp eq %"class.H4ISP::H4ISPCameraManager"* %tmp3, null br i1 %tobool.i269, label %if.then83, label %end end: diff --git a/test/CodeGen/AArch64/arm64-collect-loh-str.ll b/test/CodeGen/AArch64/arm64-collect-loh-str.ll index d7bc00e..8889cb4 100644 --- a/test/CodeGen/AArch64/arm64-collect-loh-str.ll +++ b/test/CodeGen/AArch64/arm64-collect-loh-str.ll @@ -15,8 +15,8 @@ ; CHECK-NOT: AdrpAddStr define i32 @pptp_wan_init() { entry: - store i32* null, i32** getelementptr inbounds (%struct.anon* @pptp_wan_head, i64 0, i32 0), align 8 - store i32** getelementptr inbounds (%struct.anon* @pptp_wan_head, i64 0, i32 0), i32*** getelementptr inbounds (%struct.anon* @pptp_wan_head, i64 0, i32 1), align 8 + store i32* null, i32** getelementptr inbounds (%struct.anon, %struct.anon* @pptp_wan_head, i64 0, i32 0), align 8 + store i32** getelementptr inbounds (%struct.anon, %struct.anon* @pptp_wan_head, i64 0, i32 0), i32*** getelementptr inbounds (%struct.anon, %struct.anon* @pptp_wan_head, i64 0, i32 1), align 8 ret i32 0 } diff --git a/test/CodeGen/AArch64/arm64-collect-loh.ll b/test/CodeGen/AArch64/arm64-collect-loh.ll index 6d73daa..c0aa63c 100644 --- a/test/CodeGen/AArch64/arm64-collect-loh.ll +++ b/test/CodeGen/AArch64/arm64-collect-loh.ll @@ -12,7 +12,7 @@ ; Function Attrs: noinline nounwind ssp define void @foo(i32 %t) { entry: - %tmp = load i32* @a, align 4 + %tmp = load i32, i32* @a, align 4 %add = add nsw i32 %tmp, %t store i32 %add, i32* @a, align 4 ret void @@ -32,22 +32,22 @@ entry: br i1 %cmp, label %if.then, label %if.end4 if.then: ; preds = %entry - %tmp = load i32* @a, align 4 + %tmp = load i32, i32* @a, align 4 %add = add nsw i32 %tmp, %t %cmp1 = icmp sgt i32 %add, 12 br i1 %cmp1, label %if.then2, label %if.end4 if.then2: ; preds = %if.then tail call void @foo(i32 %add) - %tmp1 = load i32* @a, align 4 + %tmp1 = load i32, i32* @a, align 4 br label %if.end4 if.end4: ; preds = %if.then2, %if.then, %entry %t.addr.0 = phi i32 [ %tmp1, %if.then2 ], [ %t, %if.then ], [ %t, %entry ] - %tmp2 = load i32* @b, align 4 + %tmp2 = load i32, i32* @b, align 4 %add5 = add nsw i32 %tmp2, %t.addr.0 tail call void @foo(i32 %add5) - %tmp3 = load i32* @b, align 4 + %tmp3 = load i32, i32* @b, align 4 %add6 = add nsw i32 %tmp3, %t.addr.0 ret i32 %add6 } diff --git a/test/CodeGen/AArch64/arm64-complex-copy-noneon.ll b/test/CodeGen/AArch64/arm64-complex-copy-noneon.ll index f65b116..938bc62 100644 --- a/test/CodeGen/AArch64/arm64-complex-copy-noneon.ll +++ b/test/CodeGen/AArch64/arm64-complex-copy-noneon.ll @@ -8,13 +8,13 @@ define void @store_combine() nounwind { %src = alloca { double, double }, align 8 %dst = alloca { double, double }, align 8 - %src.realp = getelementptr inbounds { double, double }* %src, i32 0, i32 0 - %src.real = load double* %src.realp - %src.imagp = getelementptr inbounds { double, double }* %src, i32 0, i32 1 - %src.imag = load double* %src.imagp + %src.realp = getelementptr inbounds { double, double }, { double, double }* %src, i32 0, i32 0 + %src.real = load double, double* %src.realp + %src.imagp = getelementptr inbounds { double, double }, { double, double }* %src, i32 0, i32 1 + %src.imag = load double, double* %src.imagp - %dst.realp = getelementptr inbounds { double, double }* %dst, i32 0, i32 0 - %dst.imagp = getelementptr inbounds { double, double }* %dst, i32 0, i32 1 + %dst.realp = getelementptr inbounds { double, double }, { double, double }* %dst, i32 0, i32 0 + %dst.imagp = getelementptr inbounds { double, double }, { double, double }* %dst, i32 0, i32 1 store double %src.real, double* %dst.realp store double %src.imag, double* %dst.imagp ret void diff --git a/test/CodeGen/AArch64/arm64-const-addr.ll b/test/CodeGen/AArch64/arm64-const-addr.ll index c55a922..ffc1533 100644 --- a/test/CodeGen/AArch64/arm64-const-addr.ll +++ b/test/CodeGen/AArch64/arm64-const-addr.ll @@ -10,13 +10,13 @@ define i32 @test1() nounwind { ; CHECK-NEXT: ldp w9, w10, [x8, #4] ; CHECK: ldr w8, [x8, #12] %at = inttoptr i64 68141056 to %T* - %o1 = getelementptr %T* %at, i32 0, i32 1 - %t1 = load i32* %o1 - %o2 = getelementptr %T* %at, i32 0, i32 2 - %t2 = load i32* %o2 + %o1 = getelementptr %T, %T* %at, i32 0, i32 1 + %t1 = load i32, i32* %o1 + %o2 = getelementptr %T, %T* %at, i32 0, i32 2 + %t2 = load i32, i32* %o2 %a1 = add i32 %t1, %t2 - %o3 = getelementptr %T* %at, i32 0, i32 3 - %t3 = load i32* %o3 + %o3 = getelementptr %T, %T* %at, i32 0, i32 3 + %t3 = load i32, i32* %o3 %a2 = add i32 %a1, %t3 ret i32 %a2 } diff --git a/test/CodeGen/AArch64/arm64-convert-v4f64.ll b/test/CodeGen/AArch64/arm64-convert-v4f64.ll index 7123e5e..c6b7d83 100644 --- a/test/CodeGen/AArch64/arm64-convert-v4f64.ll +++ b/test/CodeGen/AArch64/arm64-convert-v4f64.ll @@ -8,7 +8,7 @@ define <4 x i16> @fptosi_v4f64_to_v4i16(<4 x double>* %ptr) { ; CHECK-DAG: xtn v[[LHS_NA:[0-9]+]].2s, v[[LHS]].2d ; CHECK-DAG: xtn v[[RHS_NA:[0-9]+]].2s, v[[RHS]].2d ; CHECK: uzp1 v0.4h, v[[RHS_NA]].4h, v[[LHS_NA]].4h - %tmp1 = load <4 x double>* %ptr + %tmp1 = load <4 x double>, <4 x double>* %ptr %tmp2 = fptosi <4 x double> %tmp1 to <4 x i16> ret <4 x i16> %tmp2 } @@ -26,7 +26,7 @@ define <8 x i8> @fptosi_v4f64_to_v4i8(<8 x double>* %ptr) { ; CHECK-DAG: uzp1 v[[TMP1:[0-9]+]].4h, v[[CONV2]].4h, v[[CONV3]].4h ; CHECK-DAG: uzp1 v[[TMP2:[0-9]+]].4h, v[[CONV0]].4h, v[[CONV1]].4h ; CHECK: uzp1 v0.8b, v[[TMP2]].8b, v[[TMP1]].8b - %tmp1 = load <8 x double>* %ptr + %tmp1 = load <8 x double>, <8 x double>* %ptr %tmp2 = fptosi <8 x double> %tmp1 to <8 x i8> ret <8 x i8> %tmp2 } diff --git a/test/CodeGen/AArch64/arm64-cse.ll b/test/CodeGen/AArch64/arm64-cse.ll index 508df7c..8d4bf5d 100644 --- a/test/CodeGen/AArch64/arm64-cse.ll +++ b/test/CodeGen/AArch64/arm64-cse.ll @@ -15,7 +15,7 @@ entry: ; CHECK: sub ; CHECK-NOT: sub ; CHECK: ret - %0 = load i32* %offset, align 4 + %0 = load i32, i32* %offset, align 4 %cmp = icmp slt i32 %0, %size %s = sub nsw i32 %0, %size br i1 %cmp, label %return, label %if.end @@ -25,7 +25,7 @@ if.end: %s2 = sub nsw i32 %s, %size %s3 = sub nsw i32 %sub, %s2 store i32 %s3, i32* %offset, align 4 - %add.ptr = getelementptr inbounds i8* %base, i32 %sub + %add.ptr = getelementptr inbounds i8, i8* %base, i32 %sub br label %return return: @@ -43,14 +43,14 @@ entry: ; CHECK: b.lt ; CHECK-NOT: sub ; CHECK: ret - %0 = load i32* %offset, align 4 + %0 = load i32, i32* %offset, align 4 %cmp = icmp slt i32 %0, 1 br i1 %cmp, label %return, label %if.end if.end: %sub = sub nsw i32 %0, 1 store i32 %sub, i32* %offset, align 4 - %add.ptr = getelementptr inbounds i8* %base, i32 %sub + %add.ptr = getelementptr inbounds i8, i8* %base, i32 %sub br label %return return: diff --git a/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll b/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll index 2eb6307..37f3504 100644 --- a/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll +++ b/test/CodeGen/AArch64/arm64-dagcombiner-dead-indexed-load.ll @@ -17,9 +17,9 @@ target triple = "arm64-apple-ios" ; CHECK-NOT: str define void @test(%"struct.SU"* nocapture %su) { entry: - %r1 = getelementptr inbounds %"struct.SU"* %su, i64 1, i32 5 + %r1 = getelementptr inbounds %"struct.SU", %"struct.SU"* %su, i64 1, i32 5 %r2 = bitcast %"struct.BO"* %r1 to i48* - %r3 = load i48* %r2, align 8 + %r3 = load i48, i48* %r2, align 8 %r4 = and i48 %r3, -4294967296 %r5 = or i48 0, %r4 store i48 %r5, i48* %r2, align 8 diff --git a/test/CodeGen/AArch64/arm64-dagcombiner-load-slicing.ll b/test/CodeGen/AArch64/arm64-dagcombiner-load-slicing.ll index 0679014..09483ea 100644 --- a/test/CodeGen/AArch64/arm64-dagcombiner-load-slicing.ll +++ b/test/CodeGen/AArch64/arm64-dagcombiner-load-slicing.ll @@ -14,22 +14,22 @@ ; CHECK: ret define void @test(%class.Complex* nocapture %out, i64 %out_start) { entry: - %arrayidx = getelementptr inbounds %class.Complex* %out, i64 %out_start + %arrayidx = getelementptr inbounds %class.Complex, %class.Complex* %out, i64 %out_start %0 = bitcast %class.Complex* %arrayidx to i64* - %1 = load i64* %0, align 4 + %1 = load i64, i64* %0, align 4 %t0.sroa.0.0.extract.trunc = trunc i64 %1 to i32 %2 = bitcast i32 %t0.sroa.0.0.extract.trunc to float %t0.sroa.2.0.extract.shift = lshr i64 %1, 32 %t0.sroa.2.0.extract.trunc = trunc i64 %t0.sroa.2.0.extract.shift to i32 %3 = bitcast i32 %t0.sroa.2.0.extract.trunc to float %add = add i64 %out_start, 8 - %arrayidx2 = getelementptr inbounds %class.Complex* %out, i64 %add - %i.i = getelementptr inbounds %class.Complex* %arrayidx2, i64 0, i32 0 - %4 = load float* %i.i, align 4 + %arrayidx2 = getelementptr inbounds %class.Complex, %class.Complex* %out, i64 %add + %i.i = getelementptr inbounds %class.Complex, %class.Complex* %arrayidx2, i64 0, i32 0 + %4 = load float, float* %i.i, align 4 %add.i = fadd float %4, %2 %retval.sroa.0.0.vec.insert.i = insertelement <2 x float> undef, float %add.i, i32 0 - %r.i = getelementptr inbounds %class.Complex* %arrayidx2, i64 0, i32 1 - %5 = load float* %r.i, align 4 + %r.i = getelementptr inbounds %class.Complex, %class.Complex* %arrayidx2, i64 0, i32 1 + %5 = load float, float* %r.i, align 4 %add5.i = fadd float %5, %3 %retval.sroa.0.4.vec.insert.i = insertelement <2 x float> %retval.sroa.0.0.vec.insert.i, float %add5.i, i32 1 %ref.tmp.sroa.0.0.cast = bitcast %class.Complex* %arrayidx to <2 x float>* @@ -46,22 +46,22 @@ entry: ; CHECK: ret define void @test_int(%class.Complex_int* nocapture %out, i64 %out_start) { entry: - %arrayidx = getelementptr inbounds %class.Complex_int* %out, i64 %out_start + %arrayidx = getelementptr inbounds %class.Complex_int, %class.Complex_int* %out, i64 %out_start %0 = bitcast %class.Complex_int* %arrayidx to i64* - %1 = load i64* %0, align 4 + %1 = load i64, i64* %0, align 4 %t0.sroa.0.0.extract.trunc = trunc i64 %1 to i32 %2 = bitcast i32 %t0.sroa.0.0.extract.trunc to i32 %t0.sroa.2.0.extract.shift = lshr i64 %1, 32 %t0.sroa.2.0.extract.trunc = trunc i64 %t0.sroa.2.0.extract.shift to i32 %3 = bitcast i32 %t0.sroa.2.0.extract.trunc to i32 %add = add i64 %out_start, 8 - %arrayidx2 = getelementptr inbounds %class.Complex_int* %out, i64 %add - %i.i = getelementptr inbounds %class.Complex_int* %arrayidx2, i64 0, i32 0 - %4 = load i32* %i.i, align 4 + %arrayidx2 = getelementptr inbounds %class.Complex_int, %class.Complex_int* %out, i64 %add + %i.i = getelementptr inbounds %class.Complex_int, %class.Complex_int* %arrayidx2, i64 0, i32 0 + %4 = load i32, i32* %i.i, align 4 %add.i = add i32 %4, %2 %retval.sroa.0.0.vec.insert.i = insertelement <2 x i32> undef, i32 %add.i, i32 0 - %r.i = getelementptr inbounds %class.Complex_int* %arrayidx2, i64 0, i32 1 - %5 = load i32* %r.i, align 4 + %r.i = getelementptr inbounds %class.Complex_int, %class.Complex_int* %arrayidx2, i64 0, i32 1 + %5 = load i32, i32* %r.i, align 4 %add5.i = add i32 %5, %3 %retval.sroa.0.4.vec.insert.i = insertelement <2 x i32> %retval.sroa.0.0.vec.insert.i, i32 %add5.i, i32 1 %ref.tmp.sroa.0.0.cast = bitcast %class.Complex_int* %arrayidx to <2 x i32>* @@ -78,22 +78,22 @@ entry: ; CHECK: ret define void @test_long(%class.Complex_long* nocapture %out, i64 %out_start) { entry: - %arrayidx = getelementptr inbounds %class.Complex_long* %out, i64 %out_start + %arrayidx = getelementptr inbounds %class.Complex_long, %class.Complex_long* %out, i64 %out_start %0 = bitcast %class.Complex_long* %arrayidx to i128* - %1 = load i128* %0, align 4 + %1 = load i128, i128* %0, align 4 %t0.sroa.0.0.extract.trunc = trunc i128 %1 to i64 %2 = bitcast i64 %t0.sroa.0.0.extract.trunc to i64 %t0.sroa.2.0.extract.shift = lshr i128 %1, 64 %t0.sroa.2.0.extract.trunc = trunc i128 %t0.sroa.2.0.extract.shift to i64 %3 = bitcast i64 %t0.sroa.2.0.extract.trunc to i64 %add = add i64 %out_start, 8 - %arrayidx2 = getelementptr inbounds %class.Complex_long* %out, i64 %add - %i.i = getelementptr inbounds %class.Complex_long* %arrayidx2, i32 0, i32 0 - %4 = load i64* %i.i, align 4 + %arrayidx2 = getelementptr inbounds %class.Complex_long, %class.Complex_long* %out, i64 %add + %i.i = getelementptr inbounds %class.Complex_long, %class.Complex_long* %arrayidx2, i32 0, i32 0 + %4 = load i64, i64* %i.i, align 4 %add.i = add i64 %4, %2 %retval.sroa.0.0.vec.insert.i = insertelement <2 x i64> undef, i64 %add.i, i32 0 - %r.i = getelementptr inbounds %class.Complex_long* %arrayidx2, i32 0, i32 1 - %5 = load i64* %r.i, align 4 + %r.i = getelementptr inbounds %class.Complex_long, %class.Complex_long* %arrayidx2, i32 0, i32 1 + %5 = load i64, i64* %r.i, align 4 %add5.i = add i64 %5, %3 %retval.sroa.0.4.vec.insert.i = insertelement <2 x i64> %retval.sroa.0.0.vec.insert.i, i64 %add5.i, i32 1 %ref.tmp.sroa.0.0.cast = bitcast %class.Complex_long* %arrayidx to <2 x i64>* diff --git a/test/CodeGen/AArch64/arm64-dup.ll b/test/CodeGen/AArch64/arm64-dup.ll index 0c56b46..849e227 100644 --- a/test/CodeGen/AArch64/arm64-dup.ll +++ b/test/CodeGen/AArch64/arm64-dup.ll @@ -165,7 +165,7 @@ define <4 x float> @v_shuffledupQfloat(float %A) nounwind { define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vduplane8: ;CHECK: dup.8b - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 > ret <8 x i8> %tmp2 } @@ -173,7 +173,7 @@ define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind { define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vduplane16: ;CHECK: dup.4h - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ret <4 x i16> %tmp2 } @@ -181,7 +181,7 @@ define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind { define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vduplane32: ;CHECK: dup.2s - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 > ret <2 x i32> %tmp2 } @@ -189,7 +189,7 @@ define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind { define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind { ;CHECK-LABEL: vduplanefloat: ;CHECK: dup.2s - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 > ret <2 x float> %tmp2 } @@ -197,7 +197,7 @@ define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind { define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vduplaneQ8: ;CHECK: dup.16b - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 > ret <16 x i8> %tmp2 } @@ -205,7 +205,7 @@ define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind { define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vduplaneQ16: ;CHECK: dup.8h - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 > ret <8 x i16> %tmp2 } @@ -213,7 +213,7 @@ define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind { define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vduplaneQ32: ;CHECK: dup.4s - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ret <4 x i32> %tmp2 } @@ -221,7 +221,7 @@ define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind { define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind { ;CHECK-LABEL: vduplaneQfloat: ;CHECK: dup.4s - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > ret <4 x float> %tmp2 } diff --git a/test/CodeGen/AArch64/arm64-early-ifcvt.ll b/test/CodeGen/AArch64/arm64-early-ifcvt.ll index 44150c2..8164f46 100644 --- a/test/CodeGen/AArch64/arm64-early-ifcvt.ll +++ b/test/CodeGen/AArch64/arm64-early-ifcvt.ll @@ -14,8 +14,8 @@ do.body: %min.0 = phi i32 [ 0, %entry ], [ %min.1, %do.cond ] %n.addr.0 = phi i32 [ %n, %entry ], [ %dec, %do.cond ] %p.addr.0 = phi i32* [ %p, %entry ], [ %incdec.ptr, %do.cond ] - %incdec.ptr = getelementptr inbounds i32* %p.addr.0, i64 1 - %0 = load i32* %p.addr.0, align 4 + %incdec.ptr = getelementptr inbounds i32, i32* %p.addr.0, i64 1 + %0 = load i32, i32* %p.addr.0, align 4 %cmp = icmp sgt i32 %0, %max.0 br i1 %cmp, label %do.cond, label %if.else @@ -400,7 +400,7 @@ entry: br label %for.body for.body: - %x0 = load i32* undef, align 4 + %x0 = load i32, i32* undef, align 4 br i1 undef, label %if.then.i146, label %is_sbox.exit155 if.then.i146: @@ -412,8 +412,8 @@ if.then.i146: is_sbox.exit155: ; preds = %if.then.i146, %for.body %seg_offset.0.i151 = phi i32 [ %add9.i145, %if.then.i146 ], [ undef, %for.body ] %idxprom15.i152 = sext i32 %seg_offset.0.i151 to i64 - %arrayidx18.i154 = getelementptr inbounds i32* null, i64 %idxprom15.i152 - %x1 = load i32* %arrayidx18.i154, align 4 + %arrayidx18.i154 = getelementptr inbounds i32, i32* null, i64 %idxprom15.i152 + %x1 = load i32, i32* %arrayidx18.i154, align 4 br i1 undef, label %for.body51, label %for.body for.body51: ; preds = %is_sbox.exit155 diff --git a/test/CodeGen/AArch64/arm64-elf-globals.ll b/test/CodeGen/AArch64/arm64-elf-globals.ll index 4ed44e7..b1d5524 100644 --- a/test/CodeGen/AArch64/arm64-elf-globals.ll +++ b/test/CodeGen/AArch64/arm64-elf-globals.ll @@ -9,7 +9,7 @@ @var64 = external global i64, align 8 define i8 @test_i8(i8 %new) { - %val = load i8* @var8, align 1 + %val = load i8, i8* @var8, align 1 store i8 %new, i8* @var8 ret i8 %val ; CHECK-LABEL: test_i8: @@ -31,7 +31,7 @@ define i8 @test_i8(i8 %new) { } define i16 @test_i16(i16 %new) { - %val = load i16* @var16, align 2 + %val = load i16, i16* @var16, align 2 store i16 %new, i16* @var16 ret i16 %val ; CHECK-LABEL: test_i16: @@ -44,7 +44,7 @@ define i16 @test_i16(i16 %new) { } define i32 @test_i32(i32 %new) { - %val = load i32* @var32, align 4 + %val = load i32, i32* @var32, align 4 store i32 %new, i32* @var32 ret i32 %val ; CHECK-LABEL: test_i32: @@ -57,7 +57,7 @@ define i32 @test_i32(i32 %new) { } define i64 @test_i64(i64 %new) { - %val = load i64* @var64, align 8 + %val = load i64, i64* @var64, align 8 store i64 %new, i64* @var64 ret i64 %val ; CHECK-LABEL: test_i64: @@ -83,8 +83,8 @@ define i64* @test_addr() { @protectedvar = protected global i32 0, align 4 define i32 @test_vis() { - %lhs = load i32* @hiddenvar, align 4 - %rhs = load i32* @protectedvar, align 4 + %lhs = load i32, i32* @hiddenvar, align 4 + %rhs = load i32, i32* @protectedvar, align 4 %ret = add i32 %lhs, %rhs ret i32 %ret ; CHECK-PIC: adrp {{x[0-9]+}}, hiddenvar @@ -96,8 +96,8 @@ define i32 @test_vis() { @var_default = external global [2 x i32] define i32 @test_default_align() { - %addr = getelementptr [2 x i32]* @var_default, i32 0, i32 0 - %val = load i32* %addr + %addr = getelementptr [2 x i32], [2 x i32]* @var_default, i32 0, i32 0 + %val = load i32, i32* %addr ret i32 %val ; CHECK-LABEL: test_default_align: ; CHECK: adrp x[[HIREG:[0-9]+]], var_default @@ -106,7 +106,7 @@ define i32 @test_default_align() { define i64 @test_default_unaligned() { %addr = bitcast [2 x i32]* @var_default to i64* - %val = load i64* %addr + %val = load i64, i64* %addr ret i64 %val ; CHECK-LABEL: test_default_unaligned: ; CHECK: adrp [[HIREG:x[0-9]+]], var_default diff --git a/test/CodeGen/AArch64/arm64-ext.ll b/test/CodeGen/AArch64/arm64-ext.ll index 67860de..8315ffc 100644 --- a/test/CodeGen/AArch64/arm64-ext.ll +++ b/test/CodeGen/AArch64/arm64-ext.ll @@ -3,8 +3,8 @@ define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: test_vextd: ;CHECK: {{ext.8b.*#3}} - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10> ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: test_vextRd: ;CHECK: {{ext.8b.*#5}} - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4> ret <8 x i8> %tmp3 } @@ -21,8 +21,8 @@ define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: test_vextq: ;CHECK: {{ext.16b.*3}} - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18> ret <16 x i8> %tmp3 } @@ -30,8 +30,8 @@ define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: test_vextRq: ;CHECK: {{ext.16b.*7}} - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6> ret <16 x i8> %tmp3 } @@ -39,8 +39,8 @@ define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: test_vextd16: ;CHECK: {{ext.8b.*#6}} - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> ret <4 x i16> %tmp3 } @@ -48,8 +48,8 @@ define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: test_vextq32: ;CHECK: {{ext.16b.*12}} - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6> ret <4 x i32> %tmp3 } @@ -59,8 +59,8 @@ define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: test_vextd_undef: ;CHECK: {{ext.8b.*}} - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10> ret <8 x i8> %tmp3 } @@ -68,8 +68,8 @@ define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @test_vextd_undef2(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: test_vextd_undef2: ;CHECK: {{ext.8b.*#6}} - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 5> ret <8 x i8> %tmp3 } @@ -77,8 +77,8 @@ define <8 x i8> @test_vextd_undef2(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: test_vextRq_undef: ;CHECK: {{ext.16b.*#7}} - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 undef, i32 undef, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 undef, i32 6> ret <16 x i8> %tmp3 } @@ -86,7 +86,7 @@ define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @test_vextRq_undef2(<8 x i16>* %A) nounwind { ;CHECK-LABEL: test_vextRq_undef2: ;CHECK: {{ext.16b.*#10}} - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %vext = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2, i32 3, i32 4> ret <8 x i16> %vext; } @@ -101,8 +101,8 @@ define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: test_interleaved: ;CHECK: ext.8b ;CHECK: zip1.4h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 3, i32 8, i32 5, i32 9> ret <4 x i16> %tmp3 } @@ -111,8 +111,8 @@ define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: test_undef: ;CHECK: zip1.4h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 undef, i32 8, i32 5, i32 9> ret <4 x i16> %tmp3 } diff --git a/test/CodeGen/AArch64/arm64-extend.ll b/test/CodeGen/AArch64/arm64-extend.ll index afcaca2..0ef68f8 100644 --- a/test/CodeGen/AArch64/arm64-extend.ll +++ b/test/CodeGen/AArch64/arm64-extend.ll @@ -8,8 +8,8 @@ define i64 @foo(i32 %i) { ; CHECK: ldrsw x0, [x[[REG1]], w0, sxtw #2] ; CHECK: ret %idxprom = sext i32 %i to i64 - %arrayidx = getelementptr inbounds [0 x i32]* @array, i64 0, i64 %idxprom - %tmp1 = load i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds [0 x i32], [0 x i32]* @array, i64 0, i64 %idxprom + %tmp1 = load i32, i32* %arrayidx, align 4 %conv = sext i32 %tmp1 to i64 ret i64 %conv } diff --git a/test/CodeGen/AArch64/arm64-extern-weak.ll b/test/CodeGen/AArch64/arm64-extern-weak.ll index 06bd927..020c07c 100644 --- a/test/CodeGen/AArch64/arm64-extern-weak.ll +++ b/test/CodeGen/AArch64/arm64-extern-weak.ll @@ -30,7 +30,7 @@ define i32()* @foo() { @arr_var = extern_weak global [10 x i32] define i32* @bar() { - %addr = getelementptr [10 x i32]* @arr_var, i32 0, i32 5 + %addr = getelementptr [10 x i32], [10 x i32]* @arr_var, i32 0, i32 5 ; CHECK: adrp x[[ARR_VAR_HI:[0-9]+]], :got:arr_var ; CHECK: ldr [[ARR_VAR:x[0-9]+]], [x[[ARR_VAR_HI]], :got_lo12:arr_var] ; CHECK: add x0, [[ARR_VAR]], #20 diff --git a/test/CodeGen/AArch64/arm64-extload-knownzero.ll b/test/CodeGen/AArch64/arm64-extload-knownzero.ll index 14e5fd3..642af87 100644 --- a/test/CodeGen/AArch64/arm64-extload-knownzero.ll +++ b/test/CodeGen/AArch64/arm64-extload-knownzero.ll @@ -9,7 +9,7 @@ entry: bb1: ; CHECK: %bb1 ; CHECK: ldrh [[REG:w[0-9]+]] - %tmp2 = load i16* %ptr, align 2 + %tmp2 = load i16, i16* %ptr, align 2 br label %bb2 bb2: ; CHECK: %bb2 diff --git a/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll b/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll index d81bc7c..e4dc948 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s +; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s @sortlist = common global [5001 x i32] zeroinitializer, align 16 @sortlist2 = common global [5001 x i64] zeroinitializer, align 16 @@ -13,7 +13,7 @@ entry: ; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]] ; CHECK: ldr w0, [x[[REG3]]] ; CHECK: ret - %0 = load i32* getelementptr inbounds ([5001 x i32]* @sortlist, i32 0, i64 5000), align 4 + %0 = load i32, i32* getelementptr inbounds ([5001 x i32], [5001 x i32]* @sortlist, i32 0, i64 5000), align 4 ret i32 %0 } @@ -26,7 +26,7 @@ entry: ; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]] ; CHECK: ldr x0, [x[[REG3]]] ; CHECK: ret - %0 = load i64* getelementptr inbounds ([5001 x i64]* @sortlist2, i32 0, i64 5000), align 4 + %0 = load i64, i64* getelementptr inbounds ([5001 x i64], [5001 x i64]* @sortlist2, i32 0, i64 5000), align 4 ret i64 %0 } @@ -40,8 +40,8 @@ entry: ; CHECK: movz x[[REG:[0-9]+]], #0xb3a, lsl #32 ; CHECK: movk x[[REG]], #0x73ce, lsl #16 ; CHECK: movk x[[REG]], #0x2ff2 - %0 = load i8** @pd2, align 8 - %arrayidx = getelementptr inbounds i8* %0, i64 12345678901234 - %1 = load i8* %arrayidx, align 1 + %0 = load i8*, i8** @pd2, align 8 + %arrayidx = getelementptr inbounds i8, i8* %0, i64 12345678901234 + %1 = load i8, i8* %arrayidx, align 1 ret i8 %1 } diff --git a/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll b/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll index a841702..a506607 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll @@ -1,5 +1,5 @@ ; This test should cause the TargetMaterializeAlloca to be invoked -; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s +; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s %struct.S1Ty = type { i64 } %struct.S2Ty = type { %struct.S1Ty, %struct.S1Ty } @@ -18,7 +18,7 @@ entry: ; CHECK: mov [[REG:x[0-9]+]], sp ; CHECK-NEXT: add x0, [[REG]], #8 %E = alloca %struct.S2Ty, align 4 - %B = getelementptr inbounds %struct.S2Ty* %E, i32 0, i32 1 + %B = getelementptr inbounds %struct.S2Ty, %struct.S2Ty* %E, i32 0, i32 1 call void @takeS1(%struct.S1Ty* %B) ret void } diff --git a/test/CodeGen/AArch64/arm64-fast-isel-br.ll b/test/CodeGen/AArch64/arm64-fast-isel-br.ll index f896d85..0ef7b14 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-br.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-br.ll @@ -1,9 +1,9 @@ -; RUN: llc -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -mcpu=cyclone -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -O0 -fast-isel-abort=1 -mtriple=arm64-apple-darwin -mcpu=cyclone -verify-machineinstrs < %s | FileCheck %s define void @branch1() nounwind uwtable ssp { %x = alloca i32, align 4 store i32 0, i32* %x, align 4 - %1 = load i32* %x, align 4 + %1 = load i32, i32* %x, align 4 %2 = icmp ne i32 %1, 0 br i1 %2, label %3, label %4 @@ -23,7 +23,7 @@ define void @branch2() nounwind uwtable ssp { store i32 1, i32* %y, align 4 store i32 1, i32* %x, align 4 store i32 0, i32* %z, align 4 - %2 = load i32* %x, align 4 + %2 = load i32, i32* %x, align 4 %3 = icmp ne i32 %2, 0 br i1 %3, label %4, label %5 @@ -32,12 +32,12 @@ define void @branch2() nounwind uwtable ssp { br label %14 ; <label>:5 ; preds = %0 - %6 = load i32* %y, align 4 + %6 = load i32, i32* %y, align 4 %7 = icmp ne i32 %6, 0 br i1 %7, label %8, label %13 ; <label>:8 ; preds = %5 - %9 = load i32* %z, align 4 + %9 = load i32, i32* %z, align 4 %10 = icmp ne i32 %9, 0 br i1 %10, label %11, label %12 @@ -53,7 +53,7 @@ define void @branch2() nounwind uwtable ssp { br label %14 ; <label>:14 ; preds = %4, %11, %12, %13 - %15 = load i32* %1 + %15 = load i32, i32* %1 ret void } @@ -93,7 +93,7 @@ entry: store i16 %b, i16* %b.addr, align 2 store i32 %c, i32* %c.addr, align 4 store i64 %d, i64* %d.addr, align 8 - %0 = load i16* %b.addr, align 2 + %0 = load i16, i16* %b.addr, align 2 ; CHECK: and w0, w0, #0x1 ; CHECK: cmp w0, #0 ; CHECK: b.eq LBB4_2 @@ -105,7 +105,7 @@ if.then: ; preds = %entry br label %if.end if.end: ; preds = %if.then, %entry - %1 = load i32* %c.addr, align 4 + %1 = load i32, i32* %c.addr, align 4 ; CHECK: and w[[REG:[0-9]+]], w{{[0-9]+}}, #0x1 ; CHECK: cmp w[[REG]], #0 ; CHECK: b.eq LBB4_4 @@ -117,7 +117,7 @@ if.then3: ; preds = %if.end br label %if.end4 if.end4: ; preds = %if.then3, %if.end - %2 = load i64* %d.addr, align 8 + %2 = load i64, i64* %d.addr, align 8 ; CHECK: cmp w{{[0-9]+}}, #0 ; CHECK: b.eq LBB4_6 %conv5 = trunc i64 %2 to i1 @@ -128,7 +128,7 @@ if.then7: ; preds = %if.end4 br label %if.end8 if.end8: ; preds = %if.then7, %if.end4 - %3 = load i8* %a.addr, align 1 + %3 = load i8, i8* %a.addr, align 1 ret i8 %3 } diff --git a/test/CodeGen/AArch64/arm64-fast-isel-call.ll b/test/CodeGen/AArch64/arm64-fast-isel-call.ll index f1e2c40..d6957f9 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-call.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-call.ll @@ -1,6 +1,6 @@ -; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=small -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s -; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=large -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s --check-prefix=LARGE -; RUN: llc -O0 -fast-isel-abort -fast-isel-abort-args -code-model=small -verify-machineinstrs -mtriple=aarch64_be-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-BE +; RUN: llc -O0 -fast-isel-abort=2 -code-model=small -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s +; RUN: llc -O0 -fast-isel-abort=2 -code-model=large -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s --check-prefix=LARGE +; RUN: llc -O0 -fast-isel-abort=2 -code-model=small -verify-machineinstrs -mtriple=aarch64_be-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-BE define void @call0() nounwind { entry: @@ -23,7 +23,7 @@ define i32 @call1(i32 %a) nounwind { entry: %a.addr = alloca i32, align 4 store i32 %a, i32* %a.addr, align 4 - %tmp = load i32* %a.addr, align 4 + %tmp = load i32, i32* %a.addr, align 4 ret i32 %tmp } @@ -35,7 +35,7 @@ entry: ; CHECK-NEXT: bl _call1 %a.addr = alloca i32, align 4 store i32 %a, i32* %a.addr, align 4 - %tmp = load i32* %a.addr, align 4 + %tmp = load i32, i32* %a.addr, align 4 %call = call i32 @call1(i32 %tmp) ret i32 %call } diff --git a/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll b/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll index e515184..1b68865 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin -mcpu=cyclone < %s | FileCheck %s +; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin -mcpu=cyclone < %s | FileCheck %s ;; Test various conversions. define zeroext i32 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp { @@ -27,16 +27,16 @@ entry: store i16 %b, i16* %b.addr, align 2 store i32 %c, i32* %c.addr, align 4 store i64 %d, i64* %d.addr, align 8 - %tmp = load i64* %d.addr, align 8 + %tmp = load i64, i64* %d.addr, align 8 %conv = trunc i64 %tmp to i32 store i32 %conv, i32* %c.addr, align 4 - %tmp1 = load i32* %c.addr, align 4 + %tmp1 = load i32, i32* %c.addr, align 4 %conv2 = trunc i32 %tmp1 to i16 store i16 %conv2, i16* %b.addr, align 2 - %tmp3 = load i16* %b.addr, align 2 + %tmp3 = load i16, i16* %b.addr, align 2 %conv4 = trunc i16 %tmp3 to i8 store i8 %conv4, i8* %a.addr, align 1 - %tmp5 = load i8* %a.addr, align 1 + %tmp5 = load i8, i8* %a.addr, align 1 %conv6 = zext i8 %tmp5 to i32 ret i32 %conv6 } @@ -66,16 +66,16 @@ entry: store i16 %b, i16* %b.addr, align 2 store i32 %c, i32* %c.addr, align 4 store i64 %d, i64* %d.addr, align 8 - %tmp = load i8* %a.addr, align 1 + %tmp = load i8, i8* %a.addr, align 1 %conv = zext i8 %tmp to i16 store i16 %conv, i16* %b.addr, align 2 - %tmp1 = load i16* %b.addr, align 2 + %tmp1 = load i16, i16* %b.addr, align 2 %conv2 = zext i16 %tmp1 to i32 store i32 %conv2, i32* %c.addr, align 4 - %tmp3 = load i32* %c.addr, align 4 + %tmp3 = load i32, i32* %c.addr, align 4 %conv4 = zext i32 %tmp3 to i64 store i64 %conv4, i64* %d.addr, align 8 - %tmp5 = load i64* %d.addr, align 8 + %tmp5 = load i64, i64* %d.addr, align 8 ret i64 %tmp5 } @@ -121,16 +121,16 @@ entry: store i16 %b, i16* %b.addr, align 2 store i32 %c, i32* %c.addr, align 4 store i64 %d, i64* %d.addr, align 8 - %tmp = load i8* %a.addr, align 1 + %tmp = load i8, i8* %a.addr, align 1 %conv = sext i8 %tmp to i16 store i16 %conv, i16* %b.addr, align 2 - %tmp1 = load i16* %b.addr, align 2 + %tmp1 = load i16, i16* %b.addr, align 2 %conv2 = sext i16 %tmp1 to i32 store i32 %conv2, i32* %c.addr, align 4 - %tmp3 = load i32* %c.addr, align 4 + %tmp3 = load i32, i32* %c.addr, align 4 %conv4 = sext i32 %tmp3 to i64 store i64 %conv4, i64* %d.addr, align 8 - %tmp5 = load i64* %d.addr, align 8 + %tmp5 = load i64, i64* %d.addr, align 8 ret i64 %tmp5 } @@ -409,7 +409,7 @@ define void @stack_trunc() nounwind { ; CHECK: add sp, sp, #16 %a = alloca i8, align 1 %b = alloca i64, align 8 - %c = load i64* %b, align 8 + %c = load i64, i64* %b, align 8 %d = trunc i64 %c to i8 store i8 %d, i8* %a, align 1 ret void diff --git a/test/CodeGen/AArch64/arm64-fast-isel-fcmp.ll b/test/CodeGen/AArch64/arm64-fast-isel-fcmp.ll index 111b6bd..c77949f 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-fcmp.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-fcmp.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s +; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s define zeroext i1 @fcmp_float1(float %a) { ; CHECK-LABEL: fcmp_float1 diff --git a/test/CodeGen/AArch64/arm64-fast-isel-gv.ll b/test/CodeGen/AArch64/arm64-fast-isel-gv.ll index 1a4e8ea..ab29824 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-gv.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-gv.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s +; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ; Test load/store of global value from global offset table. @seed = common global i64 0, align 8 @@ -26,12 +26,12 @@ entry: ; CHECK: and [[REG8:x[0-9]+]], [[REG7]], #0xffff ; CHECK: str [[REG8]], {{\[}}[[REG1]]{{\]}} ; CHECK: ldr {{x[0-9]+}}, {{\[}}[[REG1]]{{\]}} - %0 = load i64* @seed, align 8 + %0 = load i64, i64* @seed, align 8 %mul = mul nsw i64 %0, 1309 %add = add nsw i64 %mul, 13849 %and = and i64 %add, 65535 store i64 %and, i64* @seed, align 8 - %1 = load i64* @seed, align 8 + %1 = load i64, i64* @seed, align 8 %conv = trunc i64 %1 to i32 ret i32 %conv } diff --git a/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll b/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll index 245c70e..4bc02eb 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s +; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s define i32 @icmp_eq_imm(i32 %a) nounwind ssp { entry: diff --git a/test/CodeGen/AArch64/arm64-fast-isel-indirectbr.ll b/test/CodeGen/AArch64/arm64-fast-isel-indirectbr.ll index a5f4524..cb54e45 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-indirectbr.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-indirectbr.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s +; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s @fn.table = internal global [2 x i8*] [i8* blockaddress(@fn, %ZERO), i8* blockaddress(@fn, %ONE)], align 8 @@ -8,10 +8,10 @@ entry: %retval = alloca i32, align 4 %target.addr = alloca i32, align 4 store i32 %target, i32* %target.addr, align 4 - %0 = load i32* %target.addr, align 4 + %0 = load i32, i32* %target.addr, align 4 %idxprom = zext i32 %0 to i64 - %arrayidx = getelementptr inbounds [2 x i8*]* @fn.table, i32 0, i64 %idxprom - %1 = load i8** %arrayidx, align 8 + %arrayidx = getelementptr inbounds [2 x i8*], [2 x i8*]* @fn.table, i32 0, i64 %idxprom + %1 = load i8*, i8** %arrayidx, align 8 br label %indirectgoto ZERO: ; preds = %indirectgoto @@ -25,7 +25,7 @@ ONE: ; preds = %indirectgoto br label %return return: ; preds = %ONE, %ZERO - %2 = load i32* %retval + %2 = load i32, i32* %retval ret i32 %2 indirectgoto: ; preds = %entry diff --git a/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll b/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll index 9ac3e44..bb2889e 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=arm64-apple-ios < %s | FileCheck %s --check-prefix=ARM64 +; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=arm64-apple-ios < %s | FileCheck %s --check-prefix=ARM64 @message = global [80 x i8] c"The LLVM Compiler Infrastructure\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 16 @temp = common global [80 x i8] zeroinitializer, align 16 @@ -11,7 +11,7 @@ define void @t1() { ; ARM64: movz x2, #0x50 ; ARM64: uxtb w1, w9 ; ARM64: bl _memset - call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i8 0, i64 80, i32 16, i1 false) + call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i8 0, i64 80, i32 16, i1 false) ret void } @@ -25,7 +25,7 @@ define void @t2() { ; ARM64: add x1, x8, _message@PAGEOFF ; ARM64: movz x2, #0x50 ; ARM64: bl _memcpy - call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 80, i32 16, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 80, i32 16, i1 false) ret void } @@ -39,7 +39,7 @@ define void @t3() { ; ARM64: add x1, x8, _message@PAGEOFF ; ARM64: movz x2, #0x14 ; ARM64: bl _memmove - call void @llvm.memmove.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 20, i32 16, i1 false) + call void @llvm.memmove.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 20, i32 16, i1 false) ret void } @@ -58,7 +58,7 @@ define void @t4() { ; ARM64: ldrb w11, [x9, #16] ; ARM64: strb w11, [x8, #16] ; ARM64: ret - call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 17, i32 16, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 17, i32 16, i1 false) ret void } @@ -75,7 +75,7 @@ define void @t5() { ; ARM64: ldrb w11, [x9, #16] ; ARM64: strb w11, [x8, #16] ; ARM64: ret - call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 17, i32 8, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 17, i32 8, i1 false) ret void } @@ -92,7 +92,7 @@ define void @t6() { ; ARM64: ldrb w10, [x9, #8] ; ARM64: strb w10, [x8, #8] ; ARM64: ret - call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 9, i32 4, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 9, i32 4, i1 false) ret void } @@ -111,7 +111,7 @@ define void @t7() { ; ARM64: ldrb w10, [x9, #6] ; ARM64: strb w10, [x8, #6] ; ARM64: ret - call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 7, i32 2, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 7, i32 2, i1 false) ret void } @@ -130,7 +130,7 @@ define void @t8() { ; ARM64: ldrb w10, [x9, #3] ; ARM64: strb w10, [x8, #3] ; ARM64: ret - call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8]* @message, i32 0, i32 0), i64 4, i32 1, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 4, i32 1, i1 false) ret void } @@ -142,7 +142,7 @@ define void @test_distant_memcpy(i8* %dst) { ; ARM64: ldrb [[BYTE:w[0-9]+]], [x[[ADDR]]] ; ARM64: strb [[BYTE]], [x0] %array = alloca i8, i32 8192 - %elem = getelementptr i8* %array, i32 8000 + %elem = getelementptr i8, i8* %array, i32 8000 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %elem, i64 1, i32 1, i1 false) ret void } diff --git a/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll b/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll index 1dea5d9..b5a08c1 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-materialize.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s +; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ; Materialize using fmov define float @fmov_float1() { diff --git a/test/CodeGen/AArch64/arm64-fast-isel-rem.ll b/test/CodeGen/AArch64/arm64-fast-isel-rem.ll index 26f9afa..05aa969 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-rem.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-rem.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s -; RUN: llc %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t +; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s +; RUN: llc %s -O0 -fast-isel-abort=1 -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t ; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA ; CHECK-SSA-LABEL: Machine code for function t1 diff --git a/test/CodeGen/AArch64/arm64-fast-isel-ret.ll b/test/CodeGen/AArch64/arm64-fast-isel-ret.ll index f84c755..1f6a60e 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-ret.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-ret.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s +; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s ;; Test returns. define void @t0() nounwind ssp { @@ -16,7 +16,7 @@ entry: ; CHECK: ret %a.addr = alloca i32, align 4 store i32 %a, i32* %a.addr, align 4 - %tmp = load i32* %a.addr, align 4 + %tmp = load i32, i32* %a.addr, align 4 ret i32 %tmp } @@ -28,7 +28,7 @@ entry: ; CHECK: ret %a.addr = alloca i64, align 8 store i64 %a, i64* %a.addr, align 8 - %tmp = load i64* %a.addr, align 8 + %tmp = load i64, i64* %a.addr, align 8 ret i64 %tmp } @@ -38,7 +38,7 @@ entry: ; CHECK: sxth w0, w0 %a.addr = alloca i16, align 1 store i16 %a, i16* %a.addr, align 1 - %0 = load i16* %a.addr, align 1 + %0 = load i16, i16* %a.addr, align 1 ret i16 %0 } @@ -48,7 +48,7 @@ entry: ; CHECK: sxtb w0, w0 %a.addr = alloca i8, align 1 store i8 %a, i8* %a.addr, align 1 - %0 = load i8* %a.addr, align 1 + %0 = load i8, i8* %a.addr, align 1 ret i8 %0 } @@ -58,6 +58,6 @@ entry: ; CHECK: and w0, w0, #0x1 %a.addr = alloca i1, align 1 store i1 %a, i1* %a.addr, align 1 - %0 = load i1* %a.addr, align 1 + %0 = load i1, i1* %a.addr, align 1 ret i1 %0 } diff --git a/test/CodeGen/AArch64/arm64-fast-isel-store.ll b/test/CodeGen/AArch64/arm64-fast-isel-store.ll index 9494d55..47d4cdb 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-store.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-store.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=aarch64-unknown-unknown -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-unknown-unknown -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s define void @store_i8(i8* %a) { ; CHECK-LABEL: store_i8 diff --git a/test/CodeGen/AArch64/arm64-fast-isel.ll b/test/CodeGen/AArch64/arm64-fast-isel.ll index 4349946..a4d08f9 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s +; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s define void @t0(i32 %a) nounwind { entry: @@ -9,7 +9,7 @@ entry: ; CHECK: ret %a.addr = alloca i32, align 4 store i32 %a, i32* %a.addr - %tmp = load i32* %a.addr + %tmp = load i32, i32* %a.addr store i32 %tmp, i32* %a.addr ret void } @@ -22,7 +22,7 @@ define void @t1(i64 %a) nounwind { ; CHECK: ret %a.addr = alloca i64, align 4 store i64 %a, i64* %a.addr - %tmp = load i64* %a.addr + %tmp = load i64, i64* %a.addr store i64 %tmp, i64* %a.addr ret void } @@ -39,7 +39,7 @@ entry: ; CHECK: ret %a.addr = alloca i1, align 1 store i1 %a, i1* %a.addr, align 1 - %0 = load i1* %a.addr, align 1 + %0 = load i1, i1* %a.addr, align 1 ret i1 %0 } @@ -48,8 +48,8 @@ entry: ; CHECK-LABEL: t2: ; CHECK: ldur w0, [x0, #-4] ; CHECK: ret - %0 = getelementptr i32 *%ptr, i32 -1 - %1 = load i32* %0, align 4 + %0 = getelementptr i32, i32 *%ptr, i32 -1 + %1 = load i32, i32* %0, align 4 ret i32 %1 } @@ -58,8 +58,8 @@ entry: ; CHECK-LABEL: t3: ; CHECK: ldur w0, [x0, #-256] ; CHECK: ret - %0 = getelementptr i32 *%ptr, i32 -64 - %1 = load i32* %0, align 4 + %0 = getelementptr i32, i32 *%ptr, i32 -64 + %1 = load i32, i32* %0, align 4 ret i32 %1 } @@ -68,7 +68,7 @@ entry: ; CHECK-LABEL: t4: ; CHECK: stur wzr, [x0, #-4] ; CHECK: ret - %0 = getelementptr i32 *%ptr, i32 -1 + %0 = getelementptr i32, i32 *%ptr, i32 -1 store i32 0, i32* %0, align 4 ret void } @@ -78,7 +78,7 @@ entry: ; CHECK-LABEL: t5: ; CHECK: stur wzr, [x0, #-256] ; CHECK: ret - %0 = getelementptr i32 *%ptr, i32 -64 + %0 = getelementptr i32, i32 *%ptr, i32 -64 store i32 0, i32* %0, align 4 ret void } diff --git a/test/CodeGen/AArch64/arm64-fastisel-gep-promote-before-add.ll b/test/CodeGen/AArch64/arm64-fastisel-gep-promote-before-add.ll index af9fe05..8268bcf 100644 --- a/test/CodeGen/AArch64/arm64-fastisel-gep-promote-before-add.ll +++ b/test/CodeGen/AArch64/arm64-fastisel-gep-promote-before-add.ll @@ -6,13 +6,13 @@ define zeroext i8 @gep_promotion(i8* %ptr) nounwind uwtable ssp { entry: %ptr.addr = alloca i8*, align 8 %add = add i8 64, 64 ; 0x40 + 0x40 - %0 = load i8** %ptr.addr, align 8 + %0 = load i8*, i8** %ptr.addr, align 8 ; CHECK-LABEL: _gep_promotion: ; CHECK: ldrb {{[a-z][0-9]+}}, {{\[[a-z][0-9]+\]}} - %arrayidx = getelementptr inbounds i8* %0, i8 %add + %arrayidx = getelementptr inbounds i8, i8* %0, i8 %add - %1 = load i8* %arrayidx, align 1 + %1 = load i8, i8* %arrayidx, align 1 ret i8 %1 } diff --git a/test/CodeGen/AArch64/arm64-fmuladd.ll b/test/CodeGen/AArch64/arm64-fmuladd.ll index 6c5eeca..cfc8b5f 100644 --- a/test/CodeGen/AArch64/arm64-fmuladd.ll +++ b/test/CodeGen/AArch64/arm64-fmuladd.ll @@ -4,9 +4,9 @@ define float @test_f32(float* %A, float* %B, float* %C) nounwind { ;CHECK-LABEL: test_f32: ;CHECK: fmadd ;CHECK-NOT: fmadd - %tmp1 = load float* %A - %tmp2 = load float* %B - %tmp3 = load float* %C + %tmp1 = load float, float* %A + %tmp2 = load float, float* %B + %tmp3 = load float, float* %C %tmp4 = call float @llvm.fmuladd.f32(float %tmp1, float %tmp2, float %tmp3) ret float %tmp4 } @@ -15,9 +15,9 @@ define <2 x float> @test_v2f32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C ;CHECK-LABEL: test_v2f32: ;CHECK: fmla.2s ;CHECK-NOT: fmla.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B - %tmp3 = load <2 x float>* %C + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B + %tmp3 = load <2 x float>, <2 x float>* %C %tmp4 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2, <2 x float> %tmp3) ret <2 x float> %tmp4 } @@ -26,9 +26,9 @@ define <4 x float> @test_v4f32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C ;CHECK-LABEL: test_v4f32: ;CHECK: fmla.4s ;CHECK-NOT: fmla.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B - %tmp3 = load <4 x float>* %C + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B + %tmp3 = load <4 x float>, <4 x float>* %C %tmp4 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> %tmp1, <4 x float> %tmp2, <4 x float> %tmp3) ret <4 x float> %tmp4 } @@ -38,9 +38,9 @@ define <8 x float> @test_v8f32(<8 x float>* %A, <8 x float>* %B, <8 x float>* %C ;CHECK: fmla.4s ;CHECK: fmla.4s ;CHECK-NOT: fmla.4s - %tmp1 = load <8 x float>* %A - %tmp2 = load <8 x float>* %B - %tmp3 = load <8 x float>* %C + %tmp1 = load <8 x float>, <8 x float>* %A + %tmp2 = load <8 x float>, <8 x float>* %B + %tmp3 = load <8 x float>, <8 x float>* %C %tmp4 = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> %tmp1, <8 x float> %tmp2, <8 x float> %tmp3) ret <8 x float> %tmp4 } @@ -49,9 +49,9 @@ define double @test_f64(double* %A, double* %B, double* %C) nounwind { ;CHECK-LABEL: test_f64: ;CHECK: fmadd ;CHECK-NOT: fmadd - %tmp1 = load double* %A - %tmp2 = load double* %B - %tmp3 = load double* %C + %tmp1 = load double, double* %A + %tmp2 = load double, double* %B + %tmp3 = load double, double* %C %tmp4 = call double @llvm.fmuladd.f64(double %tmp1, double %tmp2, double %tmp3) ret double %tmp4 } @@ -60,9 +60,9 @@ define <2 x double> @test_v2f64(<2 x double>* %A, <2 x double>* %B, <2 x double> ;CHECK-LABEL: test_v2f64: ;CHECK: fmla.2d ;CHECK-NOT: fmla.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B - %tmp3 = load <2 x double>* %C + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B + %tmp3 = load <2 x double>, <2 x double>* %C %tmp4 = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> %tmp1, <2 x double> %tmp2, <2 x double> %tmp3) ret <2 x double> %tmp4 } @@ -72,9 +72,9 @@ define <4 x double> @test_v4f64(<4 x double>* %A, <4 x double>* %B, <4 x double> ;CHECK: fmla.2d ;CHECK: fmla.2d ;CHECK-NOT: fmla.2d - %tmp1 = load <4 x double>* %A - %tmp2 = load <4 x double>* %B - %tmp3 = load <4 x double>* %C + %tmp1 = load <4 x double>, <4 x double>* %A + %tmp2 = load <4 x double>, <4 x double>* %B + %tmp3 = load <4 x double>, <4 x double>* %C %tmp4 = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> %tmp1, <4 x double> %tmp2, <4 x double> %tmp3) ret <4 x double> %tmp4 } diff --git a/test/CodeGen/AArch64/arm64-fold-address.ll b/test/CodeGen/AArch64/arm64-fold-address.ll index 1f0b918..6d2ea17 100644 --- a/test/CodeGen/AArch64/arm64-fold-address.ll +++ b/test/CodeGen/AArch64/arm64-fold-address.ll @@ -14,23 +14,23 @@ entry: ; CHECK: ldp d0, d1, [x[[REG]]] ; CHECK: ldp d2, d3, [x[[REG]], #16] ; CHECK: ret - %ivar = load i64* @"OBJC_IVAR_$_UIScreen._bounds", align 8, !invariant.load !4 + %ivar = load i64, i64* @"OBJC_IVAR_$_UIScreen._bounds", align 8, !invariant.load !4 %0 = bitcast %0* %self to i8* - %add.ptr = getelementptr inbounds i8* %0, i64 %ivar + %add.ptr = getelementptr inbounds i8, i8* %0, i64 %ivar %add.ptr10.0 = bitcast i8* %add.ptr to double* - %tmp11 = load double* %add.ptr10.0, align 8 + %tmp11 = load double, double* %add.ptr10.0, align 8 %add.ptr.sum = add i64 %ivar, 8 - %add.ptr10.1 = getelementptr inbounds i8* %0, i64 %add.ptr.sum + %add.ptr10.1 = getelementptr inbounds i8, i8* %0, i64 %add.ptr.sum %1 = bitcast i8* %add.ptr10.1 to double* - %tmp12 = load double* %1, align 8 + %tmp12 = load double, double* %1, align 8 %add.ptr.sum17 = add i64 %ivar, 16 - %add.ptr4.1 = getelementptr inbounds i8* %0, i64 %add.ptr.sum17 + %add.ptr4.1 = getelementptr inbounds i8, i8* %0, i64 %add.ptr.sum17 %add.ptr4.1.0 = bitcast i8* %add.ptr4.1 to double* - %tmp = load double* %add.ptr4.1.0, align 8 + %tmp = load double, double* %add.ptr4.1.0, align 8 %add.ptr4.1.sum = add i64 %ivar, 24 - %add.ptr4.1.1 = getelementptr inbounds i8* %0, i64 %add.ptr4.1.sum + %add.ptr4.1.1 = getelementptr inbounds i8, i8* %0, i64 %add.ptr4.1.sum %2 = bitcast i8* %add.ptr4.1.1 to double* - %tmp5 = load double* %2, align 8 + %tmp5 = load double, double* %2, align 8 %insert14 = insertvalue %struct.CGPoint undef, double %tmp11, 0 %insert16 = insertvalue %struct.CGPoint %insert14, double %tmp12, 1 %insert = insertvalue %struct.CGRect undef, %struct.CGPoint %insert16, 0 @@ -46,20 +46,20 @@ entry: ; CHECK: ldr d0, [x0, x{{[0-9]+}}] ; CHECK-NOT: add x0, x0, x1 ; CHECK: ret - %ivar = load i64* @"OBJC_IVAR_$_UIScreen._bounds", align 8, !invariant.load !4 + %ivar = load i64, i64* @"OBJC_IVAR_$_UIScreen._bounds", align 8, !invariant.load !4 %0 = bitcast %0* %self to i8* - %add.ptr = getelementptr inbounds i8* %0, i64 %ivar + %add.ptr = getelementptr inbounds i8, i8* %0, i64 %ivar %add.ptr10.0 = bitcast i8* %add.ptr to double* - %tmp11 = load double* %add.ptr10.0, align 8 - %add.ptr10.1 = getelementptr inbounds i8* %0, i64 %ivar + %tmp11 = load double, double* %add.ptr10.0, align 8 + %add.ptr10.1 = getelementptr inbounds i8, i8* %0, i64 %ivar %1 = bitcast i8* %add.ptr10.1 to double* - %tmp12 = load double* %1, align 8 - %add.ptr4.1 = getelementptr inbounds i8* %0, i64 %ivar + %tmp12 = load double, double* %1, align 8 + %add.ptr4.1 = getelementptr inbounds i8, i8* %0, i64 %ivar %add.ptr4.1.0 = bitcast i8* %add.ptr4.1 to double* - %tmp = load double* %add.ptr4.1.0, align 8 - %add.ptr4.1.1 = getelementptr inbounds i8* %0, i64 %ivar + %tmp = load double, double* %add.ptr4.1.0, align 8 + %add.ptr4.1.1 = getelementptr inbounds i8, i8* %0, i64 %ivar %2 = bitcast i8* %add.ptr4.1.1 to double* - %tmp5 = load double* %2, align 8 + %tmp5 = load double, double* %2, align 8 %insert14 = insertvalue %struct.CGPoint undef, double %tmp11, 0 %insert16 = insertvalue %struct.CGPoint %insert14, double %tmp12, 1 %insert = insertvalue %struct.CGRect undef, %struct.CGPoint %insert16, 0 diff --git a/test/CodeGen/AArch64/arm64-fold-lsl.ll b/test/CodeGen/AArch64/arm64-fold-lsl.ll index ec65e46..e1acd6f 100644 --- a/test/CodeGen/AArch64/arm64-fold-lsl.ll +++ b/test/CodeGen/AArch64/arm64-fold-lsl.ll @@ -13,8 +13,8 @@ define i16 @load_halfword(%struct.a* %ctx, i32 %xor72) nounwind { %shr81 = lshr i32 %xor72, 9 %conv82 = zext i32 %shr81 to i64 %idxprom83 = and i64 %conv82, 255 - %arrayidx86 = getelementptr inbounds %struct.a* %ctx, i64 0, i64 %idxprom83 - %result = load i16* %arrayidx86, align 2 + %arrayidx86 = getelementptr inbounds %struct.a, %struct.a* %ctx, i64 0, i64 %idxprom83 + %result = load i16, i16* %arrayidx86, align 2 ret i16 %result } @@ -25,8 +25,8 @@ define i32 @load_word(%struct.b* %ctx, i32 %xor72) nounwind { %shr81 = lshr i32 %xor72, 9 %conv82 = zext i32 %shr81 to i64 %idxprom83 = and i64 %conv82, 255 - %arrayidx86 = getelementptr inbounds %struct.b* %ctx, i64 0, i64 %idxprom83 - %result = load i32* %arrayidx86, align 4 + %arrayidx86 = getelementptr inbounds %struct.b, %struct.b* %ctx, i64 0, i64 %idxprom83 + %result = load i32, i32* %arrayidx86, align 4 ret i32 %result } @@ -37,8 +37,8 @@ define i64 @load_doubleword(%struct.c* %ctx, i32 %xor72) nounwind { %shr81 = lshr i32 %xor72, 9 %conv82 = zext i32 %shr81 to i64 %idxprom83 = and i64 %conv82, 255 - %arrayidx86 = getelementptr inbounds %struct.c* %ctx, i64 0, i64 %idxprom83 - %result = load i64* %arrayidx86, align 8 + %arrayidx86 = getelementptr inbounds %struct.c, %struct.c* %ctx, i64 0, i64 %idxprom83 + %result = load i64, i64* %arrayidx86, align 8 ret i64 %result } @@ -49,7 +49,7 @@ define void @store_halfword(%struct.a* %ctx, i32 %xor72, i16 %val) nounwind { %shr81 = lshr i32 %xor72, 9 %conv82 = zext i32 %shr81 to i64 %idxprom83 = and i64 %conv82, 255 - %arrayidx86 = getelementptr inbounds %struct.a* %ctx, i64 0, i64 %idxprom83 + %arrayidx86 = getelementptr inbounds %struct.a, %struct.a* %ctx, i64 0, i64 %idxprom83 store i16 %val, i16* %arrayidx86, align 8 ret void } @@ -61,7 +61,7 @@ define void @store_word(%struct.b* %ctx, i32 %xor72, i32 %val) nounwind { %shr81 = lshr i32 %xor72, 9 %conv82 = zext i32 %shr81 to i64 %idxprom83 = and i64 %conv82, 255 - %arrayidx86 = getelementptr inbounds %struct.b* %ctx, i64 0, i64 %idxprom83 + %arrayidx86 = getelementptr inbounds %struct.b, %struct.b* %ctx, i64 0, i64 %idxprom83 store i32 %val, i32* %arrayidx86, align 8 ret void } @@ -73,7 +73,7 @@ define void @store_doubleword(%struct.c* %ctx, i32 %xor72, i64 %val) nounwind { %shr81 = lshr i32 %xor72, 9 %conv82 = zext i32 %shr81 to i64 %idxprom83 = and i64 %conv82, 255 - %arrayidx86 = getelementptr inbounds %struct.c* %ctx, i64 0, i64 %idxprom83 + %arrayidx86 = getelementptr inbounds %struct.c, %struct.c* %ctx, i64 0, i64 %idxprom83 store i64 %val, i64* %arrayidx86, align 8 ret void } diff --git a/test/CodeGen/AArch64/arm64-fp128-folding.ll b/test/CodeGen/AArch64/arm64-fp128-folding.ll index 6a7d203..4024dc9 100644 --- a/test/CodeGen/AArch64/arm64-fp128-folding.ll +++ b/test/CodeGen/AArch64/arm64-fp128-folding.ll @@ -8,7 +8,7 @@ define fp128 @test_folding() { ; CHECK-LABEL: test_folding: %l = alloca i32 store i32 42, i32* %l - %val = load i32* %l + %val = load i32, i32* %l %fpval = sitofp i32 %val to fp128 ; If the value is loaded from a constant pool into an fp128, it's been folded ; successfully. diff --git a/test/CodeGen/AArch64/arm64-fp128.ll b/test/CodeGen/AArch64/arm64-fp128.ll index b1d5010..aaef39f 100644 --- a/test/CodeGen/AArch64/arm64-fp128.ll +++ b/test/CodeGen/AArch64/arm64-fp128.ll @@ -6,8 +6,8 @@ define fp128 @test_add() { ; CHECK-LABEL: test_add: - %lhs = load fp128* @lhs, align 16 - %rhs = load fp128* @rhs, align 16 + %lhs = load fp128, fp128* @lhs, align 16 + %rhs = load fp128, fp128* @rhs, align 16 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs] ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs] @@ -19,8 +19,8 @@ define fp128 @test_add() { define fp128 @test_sub() { ; CHECK-LABEL: test_sub: - %lhs = load fp128* @lhs, align 16 - %rhs = load fp128* @rhs, align 16 + %lhs = load fp128, fp128* @lhs, align 16 + %rhs = load fp128, fp128* @rhs, align 16 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs] ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs] @@ -32,8 +32,8 @@ define fp128 @test_sub() { define fp128 @test_mul() { ; CHECK-LABEL: test_mul: - %lhs = load fp128* @lhs, align 16 - %rhs = load fp128* @rhs, align 16 + %lhs = load fp128, fp128* @lhs, align 16 + %rhs = load fp128, fp128* @rhs, align 16 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs] ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs] @@ -45,8 +45,8 @@ define fp128 @test_mul() { define fp128 @test_div() { ; CHECK-LABEL: test_div: - %lhs = load fp128* @lhs, align 16 - %rhs = load fp128* @rhs, align 16 + %lhs = load fp128, fp128* @lhs, align 16 + %rhs = load fp128, fp128* @rhs, align 16 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs] ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs] @@ -60,7 +60,7 @@ define fp128 @test_div() { define void @test_fptosi() { ; CHECK-LABEL: test_fptosi: - %val = load fp128* @lhs, align 16 + %val = load fp128, fp128* @lhs, align 16 %val32 = fptosi fp128 %val to i32 store i32 %val32, i32* @var32 @@ -75,7 +75,7 @@ define void @test_fptosi() { define void @test_fptoui() { ; CHECK-LABEL: test_fptoui: - %val = load fp128* @lhs, align 16 + %val = load fp128, fp128* @lhs, align 16 %val32 = fptoui fp128 %val to i32 store i32 %val32, i32* @var32 @@ -91,12 +91,12 @@ define void @test_fptoui() { define void @test_sitofp() { ; CHECK-LABEL: test_sitofp: - %src32 = load i32* @var32 + %src32 = load i32, i32* @var32 %val32 = sitofp i32 %src32 to fp128 store volatile fp128 %val32, fp128* @lhs ; CHECK: bl __floatsitf - %src64 = load i64* @var64 + %src64 = load i64, i64* @var64 %val64 = sitofp i64 %src64 to fp128 store volatile fp128 %val64, fp128* @lhs ; CHECK: bl __floatditf @@ -107,12 +107,12 @@ define void @test_sitofp() { define void @test_uitofp() { ; CHECK-LABEL: test_uitofp: - %src32 = load i32* @var32 + %src32 = load i32, i32* @var32 %val32 = uitofp i32 %src32 to fp128 store volatile fp128 %val32, fp128* @lhs ; CHECK: bl __floatunsitf - %src64 = load i64* @var64 + %src64 = load i64, i64* @var64 %val64 = uitofp i64 %src64 to fp128 store volatile fp128 %val64, fp128* @lhs ; CHECK: bl __floatunditf @@ -123,8 +123,8 @@ define void @test_uitofp() { define i1 @test_setcc1() { ; CHECK-LABEL: test_setcc1: - %lhs = load fp128* @lhs, align 16 - %rhs = load fp128* @rhs, align 16 + %lhs = load fp128, fp128* @lhs, align 16 + %rhs = load fp128, fp128* @rhs, align 16 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs] ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs] @@ -142,8 +142,8 @@ define i1 @test_setcc1() { define i1 @test_setcc2() { ; CHECK-LABEL: test_setcc2: - %lhs = load fp128* @lhs, align 16 - %rhs = load fp128* @rhs, align 16 + %lhs = load fp128, fp128* @lhs, align 16 + %rhs = load fp128, fp128* @rhs, align 16 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs] ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs] @@ -164,8 +164,8 @@ define i1 @test_setcc2() { define i32 @test_br_cc() { ; CHECK-LABEL: test_br_cc: - %lhs = load fp128* @lhs, align 16 - %rhs = load fp128* @rhs, align 16 + %lhs = load fp128, fp128* @lhs, align 16 + %rhs = load fp128, fp128* @rhs, align 16 ; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs] ; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs] @@ -218,7 +218,7 @@ define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) { define void @test_round() { ; CHECK-LABEL: test_round: - %val = load fp128* @lhs, align 16 + %val = load fp128, fp128* @lhs, align 16 %float = fptrunc fp128 %val to float store float %float, float* @varfloat, align 4 @@ -236,15 +236,15 @@ define void @test_round() { define void @test_extend() { ; CHECK-LABEL: test_extend: - %val = load fp128* @lhs, align 16 + %val = load fp128, fp128* @lhs, align 16 - %float = load float* @varfloat + %float = load float, float* @varfloat %fromfloat = fpext float %float to fp128 store volatile fp128 %fromfloat, fp128* @lhs, align 16 ; CHECK: bl __extendsftf2 ; CHECK: str q0, [{{x[0-9]+}}, :lo12:lhs] - %double = load double* @vardouble + %double = load double, double* @vardouble %fromdouble = fpext double %double to fp128 store volatile fp128 %fromdouble, fp128* @lhs, align 16 ; CHECK: bl __extenddftf2 diff --git a/test/CodeGen/AArch64/arm64-hello.ll b/test/CodeGen/AArch64/arm64-hello.ll index a6346fb..f1c4e9b 100644 --- a/test/CodeGen/AArch64/arm64-hello.ll +++ b/test/CodeGen/AArch64/arm64-hello.ll @@ -31,7 +31,7 @@ define i32 @main() nounwind ssp { entry: %retval = alloca i32, align 4 store i32 0, i32* %retval - %call = call i32 @puts(i8* getelementptr inbounds ([7 x i8]* @.str, i32 0, i32 0)) + %call = call i32 @puts(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0)) ret i32 %call } diff --git a/test/CodeGen/AArch64/arm64-i16-subreg-extract.ll b/test/CodeGen/AArch64/arm64-i16-subreg-extract.ll index ba759e3..8d74ce7 100644 --- a/test/CodeGen/AArch64/arm64-i16-subreg-extract.ll +++ b/test/CodeGen/AArch64/arm64-i16-subreg-extract.ll @@ -3,7 +3,7 @@ define i32 @foo(<4 x i16>* %__a) nounwind { ; CHECK-LABEL: foo: ; CHECK: umov.h w{{[0-9]+}}, v{{[0-9]+}}[0] - %tmp18 = load <4 x i16>* %__a, align 8 + %tmp18 = load <4 x i16>, <4 x i16>* %__a, align 8 %vget_lane = extractelement <4 x i16> %tmp18, i32 0 %conv = zext i16 %vget_lane to i32 %mul = mul nsw i32 3, %conv diff --git a/test/CodeGen/AArch64/arm64-indexed-memory.ll b/test/CodeGen/AArch64/arm64-indexed-memory.ll index a8620f4..b52cddf 100644 --- a/test/CodeGen/AArch64/arm64-indexed-memory.ll +++ b/test/CodeGen/AArch64/arm64-indexed-memory.ll @@ -4,8 +4,8 @@ define void @store64(i64** nocapture %out, i64 %index, i64 %spacing) nounwind no ; CHECK-LABEL: store64: ; CHECK: str x{{[0-9+]}}, [x{{[0-9+]}}], #8 ; CHECK: ret - %tmp = load i64** %out, align 8 - %incdec.ptr = getelementptr inbounds i64* %tmp, i64 1 + %tmp = load i64*, i64** %out, align 8 + %incdec.ptr = getelementptr inbounds i64, i64* %tmp, i64 1 store i64 %spacing, i64* %tmp, align 4 store i64* %incdec.ptr, i64** %out, align 8 ret void @@ -15,8 +15,8 @@ define void @store32(i32** nocapture %out, i32 %index, i32 %spacing) nounwind no ; CHECK-LABEL: store32: ; CHECK: str w{{[0-9+]}}, [x{{[0-9+]}}], #4 ; CHECK: ret - %tmp = load i32** %out, align 8 - %incdec.ptr = getelementptr inbounds i32* %tmp, i64 1 + %tmp = load i32*, i32** %out, align 8 + %incdec.ptr = getelementptr inbounds i32, i32* %tmp, i64 1 store i32 %spacing, i32* %tmp, align 4 store i32* %incdec.ptr, i32** %out, align 8 ret void @@ -26,8 +26,8 @@ define void @store16(i16** nocapture %out, i16 %index, i16 %spacing) nounwind no ; CHECK-LABEL: store16: ; CHECK: strh w{{[0-9+]}}, [x{{[0-9+]}}], #2 ; CHECK: ret - %tmp = load i16** %out, align 8 - %incdec.ptr = getelementptr inbounds i16* %tmp, i64 1 + %tmp = load i16*, i16** %out, align 8 + %incdec.ptr = getelementptr inbounds i16, i16* %tmp, i64 1 store i16 %spacing, i16* %tmp, align 4 store i16* %incdec.ptr, i16** %out, align 8 ret void @@ -37,8 +37,8 @@ define void @store8(i8** nocapture %out, i8 %index, i8 %spacing) nounwind noinli ; CHECK-LABEL: store8: ; CHECK: strb w{{[0-9+]}}, [x{{[0-9+]}}], #1 ; CHECK: ret - %tmp = load i8** %out, align 8 - %incdec.ptr = getelementptr inbounds i8* %tmp, i64 1 + %tmp = load i8*, i8** %out, align 8 + %incdec.ptr = getelementptr inbounds i8, i8* %tmp, i64 1 store i8 %spacing, i8* %tmp, align 4 store i8* %incdec.ptr, i8** %out, align 8 ret void @@ -48,8 +48,8 @@ define void @truncst64to32(i32** nocapture %out, i32 %index, i64 %spacing) nounw ; CHECK-LABEL: truncst64to32: ; CHECK: str w{{[0-9+]}}, [x{{[0-9+]}}], #4 ; CHECK: ret - %tmp = load i32** %out, align 8 - %incdec.ptr = getelementptr inbounds i32* %tmp, i64 1 + %tmp = load i32*, i32** %out, align 8 + %incdec.ptr = getelementptr inbounds i32, i32* %tmp, i64 1 %trunc = trunc i64 %spacing to i32 store i32 %trunc, i32* %tmp, align 4 store i32* %incdec.ptr, i32** %out, align 8 @@ -60,8 +60,8 @@ define void @truncst64to16(i16** nocapture %out, i16 %index, i64 %spacing) nounw ; CHECK-LABEL: truncst64to16: ; CHECK: strh w{{[0-9+]}}, [x{{[0-9+]}}], #2 ; CHECK: ret - %tmp = load i16** %out, align 8 - %incdec.ptr = getelementptr inbounds i16* %tmp, i64 1 + %tmp = load i16*, i16** %out, align 8 + %incdec.ptr = getelementptr inbounds i16, i16* %tmp, i64 1 %trunc = trunc i64 %spacing to i16 store i16 %trunc, i16* %tmp, align 4 store i16* %incdec.ptr, i16** %out, align 8 @@ -72,8 +72,8 @@ define void @truncst64to8(i8** nocapture %out, i8 %index, i64 %spacing) nounwind ; CHECK-LABEL: truncst64to8: ; CHECK: strb w{{[0-9+]}}, [x{{[0-9+]}}], #1 ; CHECK: ret - %tmp = load i8** %out, align 8 - %incdec.ptr = getelementptr inbounds i8* %tmp, i64 1 + %tmp = load i8*, i8** %out, align 8 + %incdec.ptr = getelementptr inbounds i8, i8* %tmp, i64 1 %trunc = trunc i64 %spacing to i8 store i8 %trunc, i8* %tmp, align 4 store i8* %incdec.ptr, i8** %out, align 8 @@ -85,8 +85,8 @@ define void @storef32(float** nocapture %out, float %index, float %spacing) noun ; CHECK-LABEL: storef32: ; CHECK: str s{{[0-9+]}}, [x{{[0-9+]}}], #4 ; CHECK: ret - %tmp = load float** %out, align 8 - %incdec.ptr = getelementptr inbounds float* %tmp, i64 1 + %tmp = load float*, float** %out, align 8 + %incdec.ptr = getelementptr inbounds float, float* %tmp, i64 1 store float %spacing, float* %tmp, align 4 store float* %incdec.ptr, float** %out, align 8 ret void @@ -96,8 +96,8 @@ define void @storef64(double** nocapture %out, double %index, double %spacing) n ; CHECK-LABEL: storef64: ; CHECK: str d{{[0-9+]}}, [x{{[0-9+]}}], #8 ; CHECK: ret - %tmp = load double** %out, align 8 - %incdec.ptr = getelementptr inbounds double* %tmp, i64 1 + %tmp = load double*, double** %out, align 8 + %incdec.ptr = getelementptr inbounds double, double* %tmp, i64 1 store double %spacing, double* %tmp, align 4 store double* %incdec.ptr, double** %out, align 8 ret void @@ -108,8 +108,8 @@ define double * @pref64(double** nocapture %out, double %spacing) nounwind noinl ; CHECK: ldr x0, [x0] ; CHECK-NEXT: str d0, [x0, #32]! ; CHECK-NEXT: ret - %tmp = load double** %out, align 8 - %ptr = getelementptr inbounds double* %tmp, i64 4 + %tmp = load double*, double** %out, align 8 + %ptr = getelementptr inbounds double, double* %tmp, i64 4 store double %spacing, double* %ptr, align 4 ret double *%ptr } @@ -119,8 +119,8 @@ define float * @pref32(float** nocapture %out, float %spacing) nounwind noinline ; CHECK: ldr x0, [x0] ; CHECK-NEXT: str s0, [x0, #12]! ; CHECK-NEXT: ret - %tmp = load float** %out, align 8 - %ptr = getelementptr inbounds float* %tmp, i64 3 + %tmp = load float*, float** %out, align 8 + %ptr = getelementptr inbounds float, float* %tmp, i64 3 store float %spacing, float* %ptr, align 4 ret float *%ptr } @@ -130,8 +130,8 @@ define i64 * @pre64(i64** nocapture %out, i64 %spacing) nounwind noinline ssp { ; CHECK: ldr x0, [x0] ; CHECK-NEXT: str x1, [x0, #16]! ; CHECK-NEXT: ret - %tmp = load i64** %out, align 8 - %ptr = getelementptr inbounds i64* %tmp, i64 2 + %tmp = load i64*, i64** %out, align 8 + %ptr = getelementptr inbounds i64, i64* %tmp, i64 2 store i64 %spacing, i64* %ptr, align 4 ret i64 *%ptr } @@ -141,8 +141,8 @@ define i32 * @pre32(i32** nocapture %out, i32 %spacing) nounwind noinline ssp { ; CHECK: ldr x0, [x0] ; CHECK-NEXT: str w1, [x0, #8]! ; CHECK-NEXT: ret - %tmp = load i32** %out, align 8 - %ptr = getelementptr inbounds i32* %tmp, i64 2 + %tmp = load i32*, i32** %out, align 8 + %ptr = getelementptr inbounds i32, i32* %tmp, i64 2 store i32 %spacing, i32* %ptr, align 4 ret i32 *%ptr } @@ -152,8 +152,8 @@ define i16 * @pre16(i16** nocapture %out, i16 %spacing) nounwind noinline ssp { ; CHECK: ldr x0, [x0] ; CHECK-NEXT: strh w1, [x0, #4]! ; CHECK-NEXT: ret - %tmp = load i16** %out, align 8 - %ptr = getelementptr inbounds i16* %tmp, i64 2 + %tmp = load i16*, i16** %out, align 8 + %ptr = getelementptr inbounds i16, i16* %tmp, i64 2 store i16 %spacing, i16* %ptr, align 4 ret i16 *%ptr } @@ -163,8 +163,8 @@ define i8 * @pre8(i8** nocapture %out, i8 %spacing) nounwind noinline ssp { ; CHECK: ldr x0, [x0] ; CHECK-NEXT: strb w1, [x0, #2]! ; CHECK-NEXT: ret - %tmp = load i8** %out, align 8 - %ptr = getelementptr inbounds i8* %tmp, i64 2 + %tmp = load i8*, i8** %out, align 8 + %ptr = getelementptr inbounds i8, i8* %tmp, i64 2 store i8 %spacing, i8* %ptr, align 4 ret i8 *%ptr } @@ -174,8 +174,8 @@ define i32 * @pretrunc64to32(i32** nocapture %out, i64 %spacing) nounwind noinli ; CHECK: ldr x0, [x0] ; CHECK-NEXT: str w1, [x0, #8]! ; CHECK-NEXT: ret - %tmp = load i32** %out, align 8 - %ptr = getelementptr inbounds i32* %tmp, i64 2 + %tmp = load i32*, i32** %out, align 8 + %ptr = getelementptr inbounds i32, i32* %tmp, i64 2 %trunc = trunc i64 %spacing to i32 store i32 %trunc, i32* %ptr, align 4 ret i32 *%ptr @@ -186,8 +186,8 @@ define i16 * @pretrunc64to16(i16** nocapture %out, i64 %spacing) nounwind noinli ; CHECK: ldr x0, [x0] ; CHECK-NEXT: strh w1, [x0, #4]! ; CHECK-NEXT: ret - %tmp = load i16** %out, align 8 - %ptr = getelementptr inbounds i16* %tmp, i64 2 + %tmp = load i16*, i16** %out, align 8 + %ptr = getelementptr inbounds i16, i16* %tmp, i64 2 %trunc = trunc i64 %spacing to i16 store i16 %trunc, i16* %ptr, align 4 ret i16 *%ptr @@ -198,8 +198,8 @@ define i8 * @pretrunc64to8(i8** nocapture %out, i64 %spacing) nounwind noinline ; CHECK: ldr x0, [x0] ; CHECK-NEXT: strb w1, [x0, #2]! ; CHECK-NEXT: ret - %tmp = load i8** %out, align 8 - %ptr = getelementptr inbounds i8* %tmp, i64 2 + %tmp = load i8*, i8** %out, align 8 + %ptr = getelementptr inbounds i8, i8* %tmp, i64 2 %trunc = trunc i64 %spacing to i8 store i8 %trunc, i8* %ptr, align 4 ret i8 *%ptr @@ -213,8 +213,8 @@ define double* @preidxf64(double* %src, double* %out) { ; CHECK: ldr d0, [x0, #8]! ; CHECK: str d0, [x1] ; CHECK: ret - %ptr = getelementptr inbounds double* %src, i64 1 - %tmp = load double* %ptr, align 4 + %ptr = getelementptr inbounds double, double* %src, i64 1 + %tmp = load double, double* %ptr, align 4 store double %tmp, double* %out, align 4 ret double* %ptr } @@ -224,8 +224,8 @@ define float* @preidxf32(float* %src, float* %out) { ; CHECK: ldr s0, [x0, #4]! ; CHECK: str s0, [x1] ; CHECK: ret - %ptr = getelementptr inbounds float* %src, i64 1 - %tmp = load float* %ptr, align 4 + %ptr = getelementptr inbounds float, float* %src, i64 1 + %tmp = load float, float* %ptr, align 4 store float %tmp, float* %out, align 4 ret float* %ptr } @@ -235,8 +235,8 @@ define i64* @preidx64(i64* %src, i64* %out) { ; CHECK: ldr x[[REG:[0-9]+]], [x0, #8]! ; CHECK: str x[[REG]], [x1] ; CHECK: ret - %ptr = getelementptr inbounds i64* %src, i64 1 - %tmp = load i64* %ptr, align 4 + %ptr = getelementptr inbounds i64, i64* %src, i64 1 + %tmp = load i64, i64* %ptr, align 4 store i64 %tmp, i64* %out, align 4 ret i64* %ptr } @@ -245,8 +245,8 @@ define i32* @preidx32(i32* %src, i32* %out) { ; CHECK: ldr w[[REG:[0-9]+]], [x0, #4]! ; CHECK: str w[[REG]], [x1] ; CHECK: ret - %ptr = getelementptr inbounds i32* %src, i64 1 - %tmp = load i32* %ptr, align 4 + %ptr = getelementptr inbounds i32, i32* %src, i64 1 + %tmp = load i32, i32* %ptr, align 4 store i32 %tmp, i32* %out, align 4 ret i32* %ptr } @@ -255,8 +255,8 @@ define i16* @preidx16zext32(i16* %src, i32* %out) { ; CHECK: ldrh w[[REG:[0-9]+]], [x0, #2]! ; CHECK: str w[[REG]], [x1] ; CHECK: ret - %ptr = getelementptr inbounds i16* %src, i64 1 - %tmp = load i16* %ptr, align 4 + %ptr = getelementptr inbounds i16, i16* %src, i64 1 + %tmp = load i16, i16* %ptr, align 4 %ext = zext i16 %tmp to i32 store i32 %ext, i32* %out, align 4 ret i16* %ptr @@ -266,8 +266,8 @@ define i16* @preidx16zext64(i16* %src, i64* %out) { ; CHECK: ldrh w[[REG:[0-9]+]], [x0, #2]! ; CHECK: str x[[REG]], [x1] ; CHECK: ret - %ptr = getelementptr inbounds i16* %src, i64 1 - %tmp = load i16* %ptr, align 4 + %ptr = getelementptr inbounds i16, i16* %src, i64 1 + %tmp = load i16, i16* %ptr, align 4 %ext = zext i16 %tmp to i64 store i64 %ext, i64* %out, align 4 ret i16* %ptr @@ -277,8 +277,8 @@ define i8* @preidx8zext32(i8* %src, i32* %out) { ; CHECK: ldrb w[[REG:[0-9]+]], [x0, #1]! ; CHECK: str w[[REG]], [x1] ; CHECK: ret - %ptr = getelementptr inbounds i8* %src, i64 1 - %tmp = load i8* %ptr, align 4 + %ptr = getelementptr inbounds i8, i8* %src, i64 1 + %tmp = load i8, i8* %ptr, align 4 %ext = zext i8 %tmp to i32 store i32 %ext, i32* %out, align 4 ret i8* %ptr @@ -288,8 +288,8 @@ define i8* @preidx8zext64(i8* %src, i64* %out) { ; CHECK: ldrb w[[REG:[0-9]+]], [x0, #1]! ; CHECK: str x[[REG]], [x1] ; CHECK: ret - %ptr = getelementptr inbounds i8* %src, i64 1 - %tmp = load i8* %ptr, align 4 + %ptr = getelementptr inbounds i8, i8* %src, i64 1 + %tmp = load i8, i8* %ptr, align 4 %ext = zext i8 %tmp to i64 store i64 %ext, i64* %out, align 4 ret i8* %ptr @@ -299,8 +299,8 @@ define i32* @preidx32sext64(i32* %src, i64* %out) { ; CHECK: ldrsw x[[REG:[0-9]+]], [x0, #4]! ; CHECK: str x[[REG]], [x1] ; CHECK: ret - %ptr = getelementptr inbounds i32* %src, i64 1 - %tmp = load i32* %ptr, align 4 + %ptr = getelementptr inbounds i32, i32* %src, i64 1 + %tmp = load i32, i32* %ptr, align 4 %ext = sext i32 %tmp to i64 store i64 %ext, i64* %out, align 8 ret i32* %ptr @@ -310,8 +310,8 @@ define i16* @preidx16sext32(i16* %src, i32* %out) { ; CHECK: ldrsh w[[REG:[0-9]+]], [x0, #2]! ; CHECK: str w[[REG]], [x1] ; CHECK: ret - %ptr = getelementptr inbounds i16* %src, i64 1 - %tmp = load i16* %ptr, align 4 + %ptr = getelementptr inbounds i16, i16* %src, i64 1 + %tmp = load i16, i16* %ptr, align 4 %ext = sext i16 %tmp to i32 store i32 %ext, i32* %out, align 4 ret i16* %ptr @@ -321,8 +321,8 @@ define i16* @preidx16sext64(i16* %src, i64* %out) { ; CHECK: ldrsh x[[REG:[0-9]+]], [x0, #2]! ; CHECK: str x[[REG]], [x1] ; CHECK: ret - %ptr = getelementptr inbounds i16* %src, i64 1 - %tmp = load i16* %ptr, align 4 + %ptr = getelementptr inbounds i16, i16* %src, i64 1 + %tmp = load i16, i16* %ptr, align 4 %ext = sext i16 %tmp to i64 store i64 %ext, i64* %out, align 4 ret i16* %ptr @@ -332,8 +332,8 @@ define i8* @preidx8sext32(i8* %src, i32* %out) { ; CHECK: ldrsb w[[REG:[0-9]+]], [x0, #1]! ; CHECK: str w[[REG]], [x1] ; CHECK: ret - %ptr = getelementptr inbounds i8* %src, i64 1 - %tmp = load i8* %ptr, align 4 + %ptr = getelementptr inbounds i8, i8* %src, i64 1 + %tmp = load i8, i8* %ptr, align 4 %ext = sext i8 %tmp to i32 store i32 %ext, i32* %out, align 4 ret i8* %ptr @@ -343,8 +343,8 @@ define i8* @preidx8sext64(i8* %src, i64* %out) { ; CHECK: ldrsb x[[REG:[0-9]+]], [x0, #1]! ; CHECK: str x[[REG]], [x1] ; CHECK: ret - %ptr = getelementptr inbounds i8* %src, i64 1 - %tmp = load i8* %ptr, align 4 + %ptr = getelementptr inbounds i8, i8* %src, i64 1 + %tmp = load i8, i8* %ptr, align 4 %ext = sext i8 %tmp to i64 store i64 %ext, i64* %out, align 4 ret i8* %ptr @@ -358,6 +358,6 @@ define i64* @postidx_clobber(i64* %addr) nounwind noinline ssp { ; ret %paddr = bitcast i64* %addr to i64** store i64* %addr, i64** %paddr - %newaddr = getelementptr i64* %addr, i32 1 + %newaddr = getelementptr i64, i64* %addr, i32 1 ret i64* %newaddr } diff --git a/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll b/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll index 917911a..14beb1a 100644 --- a/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll +++ b/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll @@ -9,9 +9,9 @@ target triple = "arm64-apple-ios7.0.0" ; Function Attrs: nounwind ssp define void @f(double* %P1) #0 { entry: - %arrayidx4 = getelementptr inbounds double* %P1, i64 1 - %0 = load double* %arrayidx4, align 8, !tbaa !1 - %1 = load double* %P1, align 8, !tbaa !1 + %arrayidx4 = getelementptr inbounds double, double* %P1, i64 1 + %0 = load double, double* %arrayidx4, align 8, !tbaa !1 + %1 = load double, double* %P1, align 8, !tbaa !1 %2 = insertelement <2 x double> undef, double %0, i32 0 %3 = insertelement <2 x double> %2, double %1, i32 1 %4 = fsub <2 x double> zeroinitializer, %3 diff --git a/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll b/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll index 9ee4063..706871e 100644 --- a/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll +++ b/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll @@ -5,8 +5,8 @@ define <8 x i8> @test_v8i8_pre_load(<8 x i8>* %addr) { ; CHECK-LABEL: test_v8i8_pre_load: ; CHECK: ldr d0, [x0, #40]! - %newaddr = getelementptr <8 x i8>* %addr, i32 5 - %val = load <8 x i8>* %newaddr, align 8 + %newaddr = getelementptr <8 x i8>, <8 x i8>* %addr, i32 5 + %val = load <8 x i8>, <8 x i8>* %newaddr, align 8 store <8 x i8>* %newaddr, <8 x i8>** bitcast(i8** @ptr to <8 x i8>**) ret <8 x i8> %val } @@ -14,8 +14,8 @@ define <8 x i8> @test_v8i8_pre_load(<8 x i8>* %addr) { define <8 x i8> @test_v8i8_post_load(<8 x i8>* %addr) { ; CHECK-LABEL: test_v8i8_post_load: ; CHECK: ldr d0, [x0], #40 - %newaddr = getelementptr <8 x i8>* %addr, i32 5 - %val = load <8 x i8>* %addr, align 8 + %newaddr = getelementptr <8 x i8>, <8 x i8>* %addr, i32 5 + %val = load <8 x i8>, <8 x i8>* %addr, align 8 store <8 x i8>* %newaddr, <8 x i8>** bitcast(i8** @ptr to <8 x i8>**) ret <8 x i8> %val } @@ -23,7 +23,7 @@ define <8 x i8> @test_v8i8_post_load(<8 x i8>* %addr) { define void @test_v8i8_pre_store(<8 x i8> %in, <8 x i8>* %addr) { ; CHECK-LABEL: test_v8i8_pre_store: ; CHECK: str d0, [x0, #40]! - %newaddr = getelementptr <8 x i8>* %addr, i32 5 + %newaddr = getelementptr <8 x i8>, <8 x i8>* %addr, i32 5 store <8 x i8> %in, <8 x i8>* %newaddr, align 8 store <8 x i8>* %newaddr, <8 x i8>** bitcast(i8** @ptr to <8 x i8>**) ret void @@ -32,7 +32,7 @@ define void @test_v8i8_pre_store(<8 x i8> %in, <8 x i8>* %addr) { define void @test_v8i8_post_store(<8 x i8> %in, <8 x i8>* %addr) { ; CHECK-LABEL: test_v8i8_post_store: ; CHECK: str d0, [x0], #40 - %newaddr = getelementptr <8 x i8>* %addr, i32 5 + %newaddr = getelementptr <8 x i8>, <8 x i8>* %addr, i32 5 store <8 x i8> %in, <8 x i8>* %addr, align 8 store <8 x i8>* %newaddr, <8 x i8>** bitcast(i8** @ptr to <8 x i8>**) ret void @@ -41,8 +41,8 @@ define void @test_v8i8_post_store(<8 x i8> %in, <8 x i8>* %addr) { define <4 x i16> @test_v4i16_pre_load(<4 x i16>* %addr) { ; CHECK-LABEL: test_v4i16_pre_load: ; CHECK: ldr d0, [x0, #40]! - %newaddr = getelementptr <4 x i16>* %addr, i32 5 - %val = load <4 x i16>* %newaddr, align 8 + %newaddr = getelementptr <4 x i16>, <4 x i16>* %addr, i32 5 + %val = load <4 x i16>, <4 x i16>* %newaddr, align 8 store <4 x i16>* %newaddr, <4 x i16>** bitcast(i8** @ptr to <4 x i16>**) ret <4 x i16> %val } @@ -50,8 +50,8 @@ define <4 x i16> @test_v4i16_pre_load(<4 x i16>* %addr) { define <4 x i16> @test_v4i16_post_load(<4 x i16>* %addr) { ; CHECK-LABEL: test_v4i16_post_load: ; CHECK: ldr d0, [x0], #40 - %newaddr = getelementptr <4 x i16>* %addr, i32 5 - %val = load <4 x i16>* %addr, align 8 + %newaddr = getelementptr <4 x i16>, <4 x i16>* %addr, i32 5 + %val = load <4 x i16>, <4 x i16>* %addr, align 8 store <4 x i16>* %newaddr, <4 x i16>** bitcast(i8** @ptr to <4 x i16>**) ret <4 x i16> %val } @@ -59,7 +59,7 @@ define <4 x i16> @test_v4i16_post_load(<4 x i16>* %addr) { define void @test_v4i16_pre_store(<4 x i16> %in, <4 x i16>* %addr) { ; CHECK-LABEL: test_v4i16_pre_store: ; CHECK: str d0, [x0, #40]! - %newaddr = getelementptr <4 x i16>* %addr, i32 5 + %newaddr = getelementptr <4 x i16>, <4 x i16>* %addr, i32 5 store <4 x i16> %in, <4 x i16>* %newaddr, align 8 store <4 x i16>* %newaddr, <4 x i16>** bitcast(i8** @ptr to <4 x i16>**) ret void @@ -68,7 +68,7 @@ define void @test_v4i16_pre_store(<4 x i16> %in, <4 x i16>* %addr) { define void @test_v4i16_post_store(<4 x i16> %in, <4 x i16>* %addr) { ; CHECK-LABEL: test_v4i16_post_store: ; CHECK: str d0, [x0], #40 - %newaddr = getelementptr <4 x i16>* %addr, i32 5 + %newaddr = getelementptr <4 x i16>, <4 x i16>* %addr, i32 5 store <4 x i16> %in, <4 x i16>* %addr, align 8 store <4 x i16>* %newaddr, <4 x i16>** bitcast(i8** @ptr to <4 x i16>**) ret void @@ -77,8 +77,8 @@ define void @test_v4i16_post_store(<4 x i16> %in, <4 x i16>* %addr) { define <2 x i32> @test_v2i32_pre_load(<2 x i32>* %addr) { ; CHECK-LABEL: test_v2i32_pre_load: ; CHECK: ldr d0, [x0, #40]! - %newaddr = getelementptr <2 x i32>* %addr, i32 5 - %val = load <2 x i32>* %newaddr, align 8 + %newaddr = getelementptr <2 x i32>, <2 x i32>* %addr, i32 5 + %val = load <2 x i32>, <2 x i32>* %newaddr, align 8 store <2 x i32>* %newaddr, <2 x i32>** bitcast(i8** @ptr to <2 x i32>**) ret <2 x i32> %val } @@ -86,8 +86,8 @@ define <2 x i32> @test_v2i32_pre_load(<2 x i32>* %addr) { define <2 x i32> @test_v2i32_post_load(<2 x i32>* %addr) { ; CHECK-LABEL: test_v2i32_post_load: ; CHECK: ldr d0, [x0], #40 - %newaddr = getelementptr <2 x i32>* %addr, i32 5 - %val = load <2 x i32>* %addr, align 8 + %newaddr = getelementptr <2 x i32>, <2 x i32>* %addr, i32 5 + %val = load <2 x i32>, <2 x i32>* %addr, align 8 store <2 x i32>* %newaddr, <2 x i32>** bitcast(i8** @ptr to <2 x i32>**) ret <2 x i32> %val } @@ -95,7 +95,7 @@ define <2 x i32> @test_v2i32_post_load(<2 x i32>* %addr) { define void @test_v2i32_pre_store(<2 x i32> %in, <2 x i32>* %addr) { ; CHECK-LABEL: test_v2i32_pre_store: ; CHECK: str d0, [x0, #40]! - %newaddr = getelementptr <2 x i32>* %addr, i32 5 + %newaddr = getelementptr <2 x i32>, <2 x i32>* %addr, i32 5 store <2 x i32> %in, <2 x i32>* %newaddr, align 8 store <2 x i32>* %newaddr, <2 x i32>** bitcast(i8** @ptr to <2 x i32>**) ret void @@ -104,7 +104,7 @@ define void @test_v2i32_pre_store(<2 x i32> %in, <2 x i32>* %addr) { define void @test_v2i32_post_store(<2 x i32> %in, <2 x i32>* %addr) { ; CHECK-LABEL: test_v2i32_post_store: ; CHECK: str d0, [x0], #40 - %newaddr = getelementptr <2 x i32>* %addr, i32 5 + %newaddr = getelementptr <2 x i32>, <2 x i32>* %addr, i32 5 store <2 x i32> %in, <2 x i32>* %addr, align 8 store <2 x i32>* %newaddr, <2 x i32>** bitcast(i8** @ptr to <2 x i32>**) ret void @@ -113,8 +113,8 @@ define void @test_v2i32_post_store(<2 x i32> %in, <2 x i32>* %addr) { define <2 x float> @test_v2f32_pre_load(<2 x float>* %addr) { ; CHECK-LABEL: test_v2f32_pre_load: ; CHECK: ldr d0, [x0, #40]! - %newaddr = getelementptr <2 x float>* %addr, i32 5 - %val = load <2 x float>* %newaddr, align 8 + %newaddr = getelementptr <2 x float>, <2 x float>* %addr, i32 5 + %val = load <2 x float>, <2 x float>* %newaddr, align 8 store <2 x float>* %newaddr, <2 x float>** bitcast(i8** @ptr to <2 x float>**) ret <2 x float> %val } @@ -122,8 +122,8 @@ define <2 x float> @test_v2f32_pre_load(<2 x float>* %addr) { define <2 x float> @test_v2f32_post_load(<2 x float>* %addr) { ; CHECK-LABEL: test_v2f32_post_load: ; CHECK: ldr d0, [x0], #40 - %newaddr = getelementptr <2 x float>* %addr, i32 5 - %val = load <2 x float>* %addr, align 8 + %newaddr = getelementptr <2 x float>, <2 x float>* %addr, i32 5 + %val = load <2 x float>, <2 x float>* %addr, align 8 store <2 x float>* %newaddr, <2 x float>** bitcast(i8** @ptr to <2 x float>**) ret <2 x float> %val } @@ -131,7 +131,7 @@ define <2 x float> @test_v2f32_post_load(<2 x float>* %addr) { define void @test_v2f32_pre_store(<2 x float> %in, <2 x float>* %addr) { ; CHECK-LABEL: test_v2f32_pre_store: ; CHECK: str d0, [x0, #40]! - %newaddr = getelementptr <2 x float>* %addr, i32 5 + %newaddr = getelementptr <2 x float>, <2 x float>* %addr, i32 5 store <2 x float> %in, <2 x float>* %newaddr, align 8 store <2 x float>* %newaddr, <2 x float>** bitcast(i8** @ptr to <2 x float>**) ret void @@ -140,7 +140,7 @@ define void @test_v2f32_pre_store(<2 x float> %in, <2 x float>* %addr) { define void @test_v2f32_post_store(<2 x float> %in, <2 x float>* %addr) { ; CHECK-LABEL: test_v2f32_post_store: ; CHECK: str d0, [x0], #40 - %newaddr = getelementptr <2 x float>* %addr, i32 5 + %newaddr = getelementptr <2 x float>, <2 x float>* %addr, i32 5 store <2 x float> %in, <2 x float>* %addr, align 8 store <2 x float>* %newaddr, <2 x float>** bitcast(i8** @ptr to <2 x float>**) ret void @@ -149,8 +149,8 @@ define void @test_v2f32_post_store(<2 x float> %in, <2 x float>* %addr) { define <1 x i64> @test_v1i64_pre_load(<1 x i64>* %addr) { ; CHECK-LABEL: test_v1i64_pre_load: ; CHECK: ldr d0, [x0, #40]! - %newaddr = getelementptr <1 x i64>* %addr, i32 5 - %val = load <1 x i64>* %newaddr, align 8 + %newaddr = getelementptr <1 x i64>, <1 x i64>* %addr, i32 5 + %val = load <1 x i64>, <1 x i64>* %newaddr, align 8 store <1 x i64>* %newaddr, <1 x i64>** bitcast(i8** @ptr to <1 x i64>**) ret <1 x i64> %val } @@ -158,8 +158,8 @@ define <1 x i64> @test_v1i64_pre_load(<1 x i64>* %addr) { define <1 x i64> @test_v1i64_post_load(<1 x i64>* %addr) { ; CHECK-LABEL: test_v1i64_post_load: ; CHECK: ldr d0, [x0], #40 - %newaddr = getelementptr <1 x i64>* %addr, i32 5 - %val = load <1 x i64>* %addr, align 8 + %newaddr = getelementptr <1 x i64>, <1 x i64>* %addr, i32 5 + %val = load <1 x i64>, <1 x i64>* %addr, align 8 store <1 x i64>* %newaddr, <1 x i64>** bitcast(i8** @ptr to <1 x i64>**) ret <1 x i64> %val } @@ -167,7 +167,7 @@ define <1 x i64> @test_v1i64_post_load(<1 x i64>* %addr) { define void @test_v1i64_pre_store(<1 x i64> %in, <1 x i64>* %addr) { ; CHECK-LABEL: test_v1i64_pre_store: ; CHECK: str d0, [x0, #40]! - %newaddr = getelementptr <1 x i64>* %addr, i32 5 + %newaddr = getelementptr <1 x i64>, <1 x i64>* %addr, i32 5 store <1 x i64> %in, <1 x i64>* %newaddr, align 8 store <1 x i64>* %newaddr, <1 x i64>** bitcast(i8** @ptr to <1 x i64>**) ret void @@ -176,7 +176,7 @@ define void @test_v1i64_pre_store(<1 x i64> %in, <1 x i64>* %addr) { define void @test_v1i64_post_store(<1 x i64> %in, <1 x i64>* %addr) { ; CHECK-LABEL: test_v1i64_post_store: ; CHECK: str d0, [x0], #40 - %newaddr = getelementptr <1 x i64>* %addr, i32 5 + %newaddr = getelementptr <1 x i64>, <1 x i64>* %addr, i32 5 store <1 x i64> %in, <1 x i64>* %addr, align 8 store <1 x i64>* %newaddr, <1 x i64>** bitcast(i8** @ptr to <1 x i64>**) ret void @@ -185,8 +185,8 @@ define void @test_v1i64_post_store(<1 x i64> %in, <1 x i64>* %addr) { define <16 x i8> @test_v16i8_pre_load(<16 x i8>* %addr) { ; CHECK-LABEL: test_v16i8_pre_load: ; CHECK: ldr q0, [x0, #80]! - %newaddr = getelementptr <16 x i8>* %addr, i32 5 - %val = load <16 x i8>* %newaddr, align 8 + %newaddr = getelementptr <16 x i8>, <16 x i8>* %addr, i32 5 + %val = load <16 x i8>, <16 x i8>* %newaddr, align 8 store <16 x i8>* %newaddr, <16 x i8>** bitcast(i8** @ptr to <16 x i8>**) ret <16 x i8> %val } @@ -194,8 +194,8 @@ define <16 x i8> @test_v16i8_pre_load(<16 x i8>* %addr) { define <16 x i8> @test_v16i8_post_load(<16 x i8>* %addr) { ; CHECK-LABEL: test_v16i8_post_load: ; CHECK: ldr q0, [x0], #80 - %newaddr = getelementptr <16 x i8>* %addr, i32 5 - %val = load <16 x i8>* %addr, align 8 + %newaddr = getelementptr <16 x i8>, <16 x i8>* %addr, i32 5 + %val = load <16 x i8>, <16 x i8>* %addr, align 8 store <16 x i8>* %newaddr, <16 x i8>** bitcast(i8** @ptr to <16 x i8>**) ret <16 x i8> %val } @@ -203,7 +203,7 @@ define <16 x i8> @test_v16i8_post_load(<16 x i8>* %addr) { define void @test_v16i8_pre_store(<16 x i8> %in, <16 x i8>* %addr) { ; CHECK-LABEL: test_v16i8_pre_store: ; CHECK: str q0, [x0, #80]! - %newaddr = getelementptr <16 x i8>* %addr, i32 5 + %newaddr = getelementptr <16 x i8>, <16 x i8>* %addr, i32 5 store <16 x i8> %in, <16 x i8>* %newaddr, align 8 store <16 x i8>* %newaddr, <16 x i8>** bitcast(i8** @ptr to <16 x i8>**) ret void @@ -212,7 +212,7 @@ define void @test_v16i8_pre_store(<16 x i8> %in, <16 x i8>* %addr) { define void @test_v16i8_post_store(<16 x i8> %in, <16 x i8>* %addr) { ; CHECK-LABEL: test_v16i8_post_store: ; CHECK: str q0, [x0], #80 - %newaddr = getelementptr <16 x i8>* %addr, i32 5 + %newaddr = getelementptr <16 x i8>, <16 x i8>* %addr, i32 5 store <16 x i8> %in, <16 x i8>* %addr, align 8 store <16 x i8>* %newaddr, <16 x i8>** bitcast(i8** @ptr to <16 x i8>**) ret void @@ -221,8 +221,8 @@ define void @test_v16i8_post_store(<16 x i8> %in, <16 x i8>* %addr) { define <8 x i16> @test_v8i16_pre_load(<8 x i16>* %addr) { ; CHECK-LABEL: test_v8i16_pre_load: ; CHECK: ldr q0, [x0, #80]! - %newaddr = getelementptr <8 x i16>* %addr, i32 5 - %val = load <8 x i16>* %newaddr, align 8 + %newaddr = getelementptr <8 x i16>, <8 x i16>* %addr, i32 5 + %val = load <8 x i16>, <8 x i16>* %newaddr, align 8 store <8 x i16>* %newaddr, <8 x i16>** bitcast(i8** @ptr to <8 x i16>**) ret <8 x i16> %val } @@ -230,8 +230,8 @@ define <8 x i16> @test_v8i16_pre_load(<8 x i16>* %addr) { define <8 x i16> @test_v8i16_post_load(<8 x i16>* %addr) { ; CHECK-LABEL: test_v8i16_post_load: ; CHECK: ldr q0, [x0], #80 - %newaddr = getelementptr <8 x i16>* %addr, i32 5 - %val = load <8 x i16>* %addr, align 8 + %newaddr = getelementptr <8 x i16>, <8 x i16>* %addr, i32 5 + %val = load <8 x i16>, <8 x i16>* %addr, align 8 store <8 x i16>* %newaddr, <8 x i16>** bitcast(i8** @ptr to <8 x i16>**) ret <8 x i16> %val } @@ -239,7 +239,7 @@ define <8 x i16> @test_v8i16_post_load(<8 x i16>* %addr) { define void @test_v8i16_pre_store(<8 x i16> %in, <8 x i16>* %addr) { ; CHECK-LABEL: test_v8i16_pre_store: ; CHECK: str q0, [x0, #80]! - %newaddr = getelementptr <8 x i16>* %addr, i32 5 + %newaddr = getelementptr <8 x i16>, <8 x i16>* %addr, i32 5 store <8 x i16> %in, <8 x i16>* %newaddr, align 8 store <8 x i16>* %newaddr, <8 x i16>** bitcast(i8** @ptr to <8 x i16>**) ret void @@ -248,7 +248,7 @@ define void @test_v8i16_pre_store(<8 x i16> %in, <8 x i16>* %addr) { define void @test_v8i16_post_store(<8 x i16> %in, <8 x i16>* %addr) { ; CHECK-LABEL: test_v8i16_post_store: ; CHECK: str q0, [x0], #80 - %newaddr = getelementptr <8 x i16>* %addr, i32 5 + %newaddr = getelementptr <8 x i16>, <8 x i16>* %addr, i32 5 store <8 x i16> %in, <8 x i16>* %addr, align 8 store <8 x i16>* %newaddr, <8 x i16>** bitcast(i8** @ptr to <8 x i16>**) ret void @@ -257,8 +257,8 @@ define void @test_v8i16_post_store(<8 x i16> %in, <8 x i16>* %addr) { define <4 x i32> @test_v4i32_pre_load(<4 x i32>* %addr) { ; CHECK-LABEL: test_v4i32_pre_load: ; CHECK: ldr q0, [x0, #80]! - %newaddr = getelementptr <4 x i32>* %addr, i32 5 - %val = load <4 x i32>* %newaddr, align 8 + %newaddr = getelementptr <4 x i32>, <4 x i32>* %addr, i32 5 + %val = load <4 x i32>, <4 x i32>* %newaddr, align 8 store <4 x i32>* %newaddr, <4 x i32>** bitcast(i8** @ptr to <4 x i32>**) ret <4 x i32> %val } @@ -266,8 +266,8 @@ define <4 x i32> @test_v4i32_pre_load(<4 x i32>* %addr) { define <4 x i32> @test_v4i32_post_load(<4 x i32>* %addr) { ; CHECK-LABEL: test_v4i32_post_load: ; CHECK: ldr q0, [x0], #80 - %newaddr = getelementptr <4 x i32>* %addr, i32 5 - %val = load <4 x i32>* %addr, align 8 + %newaddr = getelementptr <4 x i32>, <4 x i32>* %addr, i32 5 + %val = load <4 x i32>, <4 x i32>* %addr, align 8 store <4 x i32>* %newaddr, <4 x i32>** bitcast(i8** @ptr to <4 x i32>**) ret <4 x i32> %val } @@ -275,7 +275,7 @@ define <4 x i32> @test_v4i32_post_load(<4 x i32>* %addr) { define void @test_v4i32_pre_store(<4 x i32> %in, <4 x i32>* %addr) { ; CHECK-LABEL: test_v4i32_pre_store: ; CHECK: str q0, [x0, #80]! - %newaddr = getelementptr <4 x i32>* %addr, i32 5 + %newaddr = getelementptr <4 x i32>, <4 x i32>* %addr, i32 5 store <4 x i32> %in, <4 x i32>* %newaddr, align 8 store <4 x i32>* %newaddr, <4 x i32>** bitcast(i8** @ptr to <4 x i32>**) ret void @@ -284,7 +284,7 @@ define void @test_v4i32_pre_store(<4 x i32> %in, <4 x i32>* %addr) { define void @test_v4i32_post_store(<4 x i32> %in, <4 x i32>* %addr) { ; CHECK-LABEL: test_v4i32_post_store: ; CHECK: str q0, [x0], #80 - %newaddr = getelementptr <4 x i32>* %addr, i32 5 + %newaddr = getelementptr <4 x i32>, <4 x i32>* %addr, i32 5 store <4 x i32> %in, <4 x i32>* %addr, align 8 store <4 x i32>* %newaddr, <4 x i32>** bitcast(i8** @ptr to <4 x i32>**) ret void @@ -294,8 +294,8 @@ define void @test_v4i32_post_store(<4 x i32> %in, <4 x i32>* %addr) { define <4 x float> @test_v4f32_pre_load(<4 x float>* %addr) { ; CHECK-LABEL: test_v4f32_pre_load: ; CHECK: ldr q0, [x0, #80]! - %newaddr = getelementptr <4 x float>* %addr, i32 5 - %val = load <4 x float>* %newaddr, align 8 + %newaddr = getelementptr <4 x float>, <4 x float>* %addr, i32 5 + %val = load <4 x float>, <4 x float>* %newaddr, align 8 store <4 x float>* %newaddr, <4 x float>** bitcast(i8** @ptr to <4 x float>**) ret <4 x float> %val } @@ -303,8 +303,8 @@ define <4 x float> @test_v4f32_pre_load(<4 x float>* %addr) { define <4 x float> @test_v4f32_post_load(<4 x float>* %addr) { ; CHECK-LABEL: test_v4f32_post_load: ; CHECK: ldr q0, [x0], #80 - %newaddr = getelementptr <4 x float>* %addr, i32 5 - %val = load <4 x float>* %addr, align 8 + %newaddr = getelementptr <4 x float>, <4 x float>* %addr, i32 5 + %val = load <4 x float>, <4 x float>* %addr, align 8 store <4 x float>* %newaddr, <4 x float>** bitcast(i8** @ptr to <4 x float>**) ret <4 x float> %val } @@ -312,7 +312,7 @@ define <4 x float> @test_v4f32_post_load(<4 x float>* %addr) { define void @test_v4f32_pre_store(<4 x float> %in, <4 x float>* %addr) { ; CHECK-LABEL: test_v4f32_pre_store: ; CHECK: str q0, [x0, #80]! - %newaddr = getelementptr <4 x float>* %addr, i32 5 + %newaddr = getelementptr <4 x float>, <4 x float>* %addr, i32 5 store <4 x float> %in, <4 x float>* %newaddr, align 8 store <4 x float>* %newaddr, <4 x float>** bitcast(i8** @ptr to <4 x float>**) ret void @@ -321,7 +321,7 @@ define void @test_v4f32_pre_store(<4 x float> %in, <4 x float>* %addr) { define void @test_v4f32_post_store(<4 x float> %in, <4 x float>* %addr) { ; CHECK-LABEL: test_v4f32_post_store: ; CHECK: str q0, [x0], #80 - %newaddr = getelementptr <4 x float>* %addr, i32 5 + %newaddr = getelementptr <4 x float>, <4 x float>* %addr, i32 5 store <4 x float> %in, <4 x float>* %addr, align 8 store <4 x float>* %newaddr, <4 x float>** bitcast(i8** @ptr to <4 x float>**) ret void @@ -331,8 +331,8 @@ define void @test_v4f32_post_store(<4 x float> %in, <4 x float>* %addr) { define <2 x i64> @test_v2i64_pre_load(<2 x i64>* %addr) { ; CHECK-LABEL: test_v2i64_pre_load: ; CHECK: ldr q0, [x0, #80]! - %newaddr = getelementptr <2 x i64>* %addr, i32 5 - %val = load <2 x i64>* %newaddr, align 8 + %newaddr = getelementptr <2 x i64>, <2 x i64>* %addr, i32 5 + %val = load <2 x i64>, <2 x i64>* %newaddr, align 8 store <2 x i64>* %newaddr, <2 x i64>** bitcast(i8** @ptr to <2 x i64>**) ret <2 x i64> %val } @@ -340,8 +340,8 @@ define <2 x i64> @test_v2i64_pre_load(<2 x i64>* %addr) { define <2 x i64> @test_v2i64_post_load(<2 x i64>* %addr) { ; CHECK-LABEL: test_v2i64_post_load: ; CHECK: ldr q0, [x0], #80 - %newaddr = getelementptr <2 x i64>* %addr, i32 5 - %val = load <2 x i64>* %addr, align 8 + %newaddr = getelementptr <2 x i64>, <2 x i64>* %addr, i32 5 + %val = load <2 x i64>, <2 x i64>* %addr, align 8 store <2 x i64>* %newaddr, <2 x i64>** bitcast(i8** @ptr to <2 x i64>**) ret <2 x i64> %val } @@ -349,7 +349,7 @@ define <2 x i64> @test_v2i64_post_load(<2 x i64>* %addr) { define void @test_v2i64_pre_store(<2 x i64> %in, <2 x i64>* %addr) { ; CHECK-LABEL: test_v2i64_pre_store: ; CHECK: str q0, [x0, #80]! - %newaddr = getelementptr <2 x i64>* %addr, i32 5 + %newaddr = getelementptr <2 x i64>, <2 x i64>* %addr, i32 5 store <2 x i64> %in, <2 x i64>* %newaddr, align 8 store <2 x i64>* %newaddr, <2 x i64>** bitcast(i8** @ptr to <2 x i64>**) ret void @@ -358,7 +358,7 @@ define void @test_v2i64_pre_store(<2 x i64> %in, <2 x i64>* %addr) { define void @test_v2i64_post_store(<2 x i64> %in, <2 x i64>* %addr) { ; CHECK-LABEL: test_v2i64_post_store: ; CHECK: str q0, [x0], #80 - %newaddr = getelementptr <2 x i64>* %addr, i32 5 + %newaddr = getelementptr <2 x i64>, <2 x i64>* %addr, i32 5 store <2 x i64> %in, <2 x i64>* %addr, align 8 store <2 x i64>* %newaddr, <2 x i64>** bitcast(i8** @ptr to <2 x i64>**) ret void @@ -368,8 +368,8 @@ define void @test_v2i64_post_store(<2 x i64> %in, <2 x i64>* %addr) { define <2 x double> @test_v2f64_pre_load(<2 x double>* %addr) { ; CHECK-LABEL: test_v2f64_pre_load: ; CHECK: ldr q0, [x0, #80]! - %newaddr = getelementptr <2 x double>* %addr, i32 5 - %val = load <2 x double>* %newaddr, align 8 + %newaddr = getelementptr <2 x double>, <2 x double>* %addr, i32 5 + %val = load <2 x double>, <2 x double>* %newaddr, align 8 store <2 x double>* %newaddr, <2 x double>** bitcast(i8** @ptr to <2 x double>**) ret <2 x double> %val } @@ -377,8 +377,8 @@ define <2 x double> @test_v2f64_pre_load(<2 x double>* %addr) { define <2 x double> @test_v2f64_post_load(<2 x double>* %addr) { ; CHECK-LABEL: test_v2f64_post_load: ; CHECK: ldr q0, [x0], #80 - %newaddr = getelementptr <2 x double>* %addr, i32 5 - %val = load <2 x double>* %addr, align 8 + %newaddr = getelementptr <2 x double>, <2 x double>* %addr, i32 5 + %val = load <2 x double>, <2 x double>* %addr, align 8 store <2 x double>* %newaddr, <2 x double>** bitcast(i8** @ptr to <2 x double>**) ret <2 x double> %val } @@ -386,7 +386,7 @@ define <2 x double> @test_v2f64_post_load(<2 x double>* %addr) { define void @test_v2f64_pre_store(<2 x double> %in, <2 x double>* %addr) { ; CHECK-LABEL: test_v2f64_pre_store: ; CHECK: str q0, [x0, #80]! - %newaddr = getelementptr <2 x double>* %addr, i32 5 + %newaddr = getelementptr <2 x double>, <2 x double>* %addr, i32 5 store <2 x double> %in, <2 x double>* %newaddr, align 8 store <2 x double>* %newaddr, <2 x double>** bitcast(i8** @ptr to <2 x double>**) ret void @@ -395,7 +395,7 @@ define void @test_v2f64_pre_store(<2 x double> %in, <2 x double>* %addr) { define void @test_v2f64_post_store(<2 x double> %in, <2 x double>* %addr) { ; CHECK-LABEL: test_v2f64_post_store: ; CHECK: str q0, [x0], #80 - %newaddr = getelementptr <2 x double>* %addr, i32 5 + %newaddr = getelementptr <2 x double>, <2 x double>* %addr, i32 5 store <2 x double> %in, <2 x double>* %addr, align 8 store <2 x double>* %newaddr, <2 x double>** bitcast(i8** @ptr to <2 x double>**) ret void @@ -407,7 +407,7 @@ define i8* @test_v16i8_post_imm_st1_lane(<16 x i8> %in, i8* %addr) { %elt = extractelement <16 x i8> %in, i32 3 store i8 %elt, i8* %addr - %newaddr = getelementptr i8* %addr, i32 1 + %newaddr = getelementptr i8, i8* %addr, i32 1 ret i8* %newaddr } @@ -418,7 +418,7 @@ define i8* @test_v16i8_post_reg_st1_lane(<16 x i8> %in, i8* %addr) { %elt = extractelement <16 x i8> %in, i32 3 store i8 %elt, i8* %addr - %newaddr = getelementptr i8* %addr, i32 2 + %newaddr = getelementptr i8, i8* %addr, i32 2 ret i8* %newaddr } @@ -429,7 +429,7 @@ define i16* @test_v8i16_post_imm_st1_lane(<8 x i16> %in, i16* %addr) { %elt = extractelement <8 x i16> %in, i32 3 store i16 %elt, i16* %addr - %newaddr = getelementptr i16* %addr, i32 1 + %newaddr = getelementptr i16, i16* %addr, i32 1 ret i16* %newaddr } @@ -440,7 +440,7 @@ define i16* @test_v8i16_post_reg_st1_lane(<8 x i16> %in, i16* %addr) { %elt = extractelement <8 x i16> %in, i32 3 store i16 %elt, i16* %addr - %newaddr = getelementptr i16* %addr, i32 2 + %newaddr = getelementptr i16, i16* %addr, i32 2 ret i16* %newaddr } @@ -450,7 +450,7 @@ define i32* @test_v4i32_post_imm_st1_lane(<4 x i32> %in, i32* %addr) { %elt = extractelement <4 x i32> %in, i32 3 store i32 %elt, i32* %addr - %newaddr = getelementptr i32* %addr, i32 1 + %newaddr = getelementptr i32, i32* %addr, i32 1 ret i32* %newaddr } @@ -461,7 +461,7 @@ define i32* @test_v4i32_post_reg_st1_lane(<4 x i32> %in, i32* %addr) { %elt = extractelement <4 x i32> %in, i32 3 store i32 %elt, i32* %addr - %newaddr = getelementptr i32* %addr, i32 2 + %newaddr = getelementptr i32, i32* %addr, i32 2 ret i32* %newaddr } @@ -471,7 +471,7 @@ define float* @test_v4f32_post_imm_st1_lane(<4 x float> %in, float* %addr) { %elt = extractelement <4 x float> %in, i32 3 store float %elt, float* %addr - %newaddr = getelementptr float* %addr, i32 1 + %newaddr = getelementptr float, float* %addr, i32 1 ret float* %newaddr } @@ -482,7 +482,7 @@ define float* @test_v4f32_post_reg_st1_lane(<4 x float> %in, float* %addr) { %elt = extractelement <4 x float> %in, i32 3 store float %elt, float* %addr - %newaddr = getelementptr float* %addr, i32 2 + %newaddr = getelementptr float, float* %addr, i32 2 ret float* %newaddr } @@ -492,7 +492,7 @@ define i64* @test_v2i64_post_imm_st1_lane(<2 x i64> %in, i64* %addr) { %elt = extractelement <2 x i64> %in, i64 1 store i64 %elt, i64* %addr - %newaddr = getelementptr i64* %addr, i64 1 + %newaddr = getelementptr i64, i64* %addr, i64 1 ret i64* %newaddr } @@ -503,7 +503,7 @@ define i64* @test_v2i64_post_reg_st1_lane(<2 x i64> %in, i64* %addr) { %elt = extractelement <2 x i64> %in, i64 1 store i64 %elt, i64* %addr - %newaddr = getelementptr i64* %addr, i64 2 + %newaddr = getelementptr i64, i64* %addr, i64 2 ret i64* %newaddr } @@ -513,7 +513,7 @@ define double* @test_v2f64_post_imm_st1_lane(<2 x double> %in, double* %addr) { %elt = extractelement <2 x double> %in, i32 1 store double %elt, double* %addr - %newaddr = getelementptr double* %addr, i32 1 + %newaddr = getelementptr double, double* %addr, i32 1 ret double* %newaddr } @@ -524,7 +524,7 @@ define double* @test_v2f64_post_reg_st1_lane(<2 x double> %in, double* %addr) { %elt = extractelement <2 x double> %in, i32 1 store double %elt, double* %addr - %newaddr = getelementptr double* %addr, i32 2 + %newaddr = getelementptr double, double* %addr, i32 2 ret double* %newaddr } @@ -534,7 +534,7 @@ define i8* @test_v8i8_post_imm_st1_lane(<8 x i8> %in, i8* %addr) { %elt = extractelement <8 x i8> %in, i32 3 store i8 %elt, i8* %addr - %newaddr = getelementptr i8* %addr, i32 1 + %newaddr = getelementptr i8, i8* %addr, i32 1 ret i8* %newaddr } @@ -545,7 +545,7 @@ define i8* @test_v8i8_post_reg_st1_lane(<8 x i8> %in, i8* %addr) { %elt = extractelement <8 x i8> %in, i32 3 store i8 %elt, i8* %addr - %newaddr = getelementptr i8* %addr, i32 2 + %newaddr = getelementptr i8, i8* %addr, i32 2 ret i8* %newaddr } @@ -555,7 +555,7 @@ define i16* @test_v4i16_post_imm_st1_lane(<4 x i16> %in, i16* %addr) { %elt = extractelement <4 x i16> %in, i32 3 store i16 %elt, i16* %addr - %newaddr = getelementptr i16* %addr, i32 1 + %newaddr = getelementptr i16, i16* %addr, i32 1 ret i16* %newaddr } @@ -566,7 +566,7 @@ define i16* @test_v4i16_post_reg_st1_lane(<4 x i16> %in, i16* %addr) { %elt = extractelement <4 x i16> %in, i32 3 store i16 %elt, i16* %addr - %newaddr = getelementptr i16* %addr, i32 2 + %newaddr = getelementptr i16, i16* %addr, i32 2 ret i16* %newaddr } @@ -576,7 +576,7 @@ define i32* @test_v2i32_post_imm_st1_lane(<2 x i32> %in, i32* %addr) { %elt = extractelement <2 x i32> %in, i32 1 store i32 %elt, i32* %addr - %newaddr = getelementptr i32* %addr, i32 1 + %newaddr = getelementptr i32, i32* %addr, i32 1 ret i32* %newaddr } @@ -587,7 +587,7 @@ define i32* @test_v2i32_post_reg_st1_lane(<2 x i32> %in, i32* %addr) { %elt = extractelement <2 x i32> %in, i32 1 store i32 %elt, i32* %addr - %newaddr = getelementptr i32* %addr, i32 2 + %newaddr = getelementptr i32, i32* %addr, i32 2 ret i32* %newaddr } @@ -597,7 +597,7 @@ define float* @test_v2f32_post_imm_st1_lane(<2 x float> %in, float* %addr) { %elt = extractelement <2 x float> %in, i32 1 store float %elt, float* %addr - %newaddr = getelementptr float* %addr, i32 1 + %newaddr = getelementptr float, float* %addr, i32 1 ret float* %newaddr } @@ -608,7 +608,7 @@ define float* @test_v2f32_post_reg_st1_lane(<2 x float> %in, float* %addr) { %elt = extractelement <2 x float> %in, i32 1 store float %elt, float* %addr - %newaddr = getelementptr float* %addr, i32 2 + %newaddr = getelementptr float, float* %addr, i32 2 ret float* %newaddr } @@ -616,7 +616,7 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(i8* %A, i8** %ptr) { ;CHECK-LABEL: test_v16i8_post_imm_ld2: ;CHECK: ld2.16b { v0, v1 }, [x0], #32 %ld2 = tail call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 32 + %tmp = getelementptr i8, i8* %A, i32 32 store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8> } %ld2 } @@ -625,7 +625,7 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld2(i8* %A, i8** %ptr, i64 ;CHECK-LABEL: test_v16i8_post_reg_ld2: ;CHECK: ld2.16b { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = tail call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8> } %ld2 } @@ -637,7 +637,7 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld2(i8* %A, i8** %ptr) { ;CHECK-LABEL: test_v8i8_post_imm_ld2: ;CHECK: ld2.8b { v0, v1 }, [x0], #16 %ld2 = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 16 + %tmp = getelementptr i8, i8* %A, i32 16 store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8> } %ld2 } @@ -646,7 +646,7 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld2(i8* %A, i8** %ptr, i64 %in ;CHECK-LABEL: test_v8i8_post_reg_ld2: ;CHECK: ld2.8b { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8> } %ld2 } @@ -658,7 +658,7 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld2(i16* %A, i16** %ptr) { ;CHECK-LABEL: test_v8i16_post_imm_ld2: ;CHECK: ld2.8h { v0, v1 }, [x0], #32 %ld2 = tail call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 16 + %tmp = getelementptr i16, i16* %A, i32 16 store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16> } %ld2 } @@ -667,7 +667,7 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld2(i16* %A, i16** %ptr, i6 ;CHECK-LABEL: test_v8i16_post_reg_ld2: ;CHECK: ld2.8h { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = tail call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16> } %ld2 } @@ -679,7 +679,7 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld2(i16* %A, i16** %ptr) { ;CHECK-LABEL: test_v4i16_post_imm_ld2: ;CHECK: ld2.4h { v0, v1 }, [x0], #16 %ld2 = tail call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 8 + %tmp = getelementptr i16, i16* %A, i32 8 store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16> } %ld2 } @@ -688,7 +688,7 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld2(i16* %A, i16** %ptr, i6 ;CHECK-LABEL: test_v4i16_post_reg_ld2: ;CHECK: ld2.4h { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = tail call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16> } %ld2 } @@ -700,7 +700,7 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld2(i32* %A, i32** %ptr) { ;CHECK-LABEL: test_v4i32_post_imm_ld2: ;CHECK: ld2.4s { v0, v1 }, [x0], #32 %ld2 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 8 + %tmp = getelementptr i32, i32* %A, i32 8 store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32> } %ld2 } @@ -709,7 +709,7 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld2(i32* %A, i32** %ptr, i6 ;CHECK-LABEL: test_v4i32_post_reg_ld2: ;CHECK: ld2.4s { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32> } %ld2 } @@ -721,7 +721,7 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld2(i32* %A, i32** %ptr) { ;CHECK-LABEL: test_v2i32_post_imm_ld2: ;CHECK: ld2.2s { v0, v1 }, [x0], #16 %ld2 = tail call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 4 + %tmp = getelementptr i32, i32* %A, i32 4 store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32> } %ld2 } @@ -730,7 +730,7 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld2(i32* %A, i32** %ptr, i6 ;CHECK-LABEL: test_v2i32_post_reg_ld2: ;CHECK: ld2.2s { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = tail call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32> } %ld2 } @@ -742,7 +742,7 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld2(i64* %A, i64** %ptr) { ;CHECK-LABEL: test_v2i64_post_imm_ld2: ;CHECK: ld2.2d { v0, v1 }, [x0], #32 %ld2 = tail call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 4 + %tmp = getelementptr i64, i64* %A, i32 4 store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64> } %ld2 } @@ -751,7 +751,7 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld2(i64* %A, i64** %ptr, i6 ;CHECK-LABEL: test_v2i64_post_reg_ld2: ;CHECK: ld2.2d { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = tail call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64> } %ld2 } @@ -763,7 +763,7 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld2(i64* %A, i64** %ptr) { ;CHECK-LABEL: test_v1i64_post_imm_ld2: ;CHECK: ld1.1d { v0, v1 }, [x0], #16 %ld2 = tail call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 2 + %tmp = getelementptr i64, i64* %A, i32 2 store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64> } %ld2 } @@ -772,7 +772,7 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld2(i64* %A, i64** %ptr, i6 ;CHECK-LABEL: test_v1i64_post_reg_ld2: ;CHECK: ld1.1d { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = tail call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64> } %ld2 } @@ -784,7 +784,7 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld2(float* %A, float** ;CHECK-LABEL: test_v4f32_post_imm_ld2: ;CHECK: ld2.4s { v0, v1 }, [x0], #32 %ld2 = tail call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 8 + %tmp = getelementptr float, float* %A, i32 8 store float* %tmp, float** %ptr ret { <4 x float>, <4 x float> } %ld2 } @@ -793,7 +793,7 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_reg_ld2(float* %A, float** ;CHECK-LABEL: test_v4f32_post_reg_ld2: ;CHECK: ld2.4s { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = tail call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <4 x float>, <4 x float> } %ld2 } @@ -805,7 +805,7 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld2(float* %A, float** ;CHECK-LABEL: test_v2f32_post_imm_ld2: ;CHECK: ld2.2s { v0, v1 }, [x0], #16 %ld2 = tail call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 4 + %tmp = getelementptr float, float* %A, i32 4 store float* %tmp, float** %ptr ret { <2 x float>, <2 x float> } %ld2 } @@ -814,7 +814,7 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_reg_ld2(float* %A, float** ;CHECK-LABEL: test_v2f32_post_reg_ld2: ;CHECK: ld2.2s { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = tail call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <2 x float>, <2 x float> } %ld2 } @@ -826,7 +826,7 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld2(double* %A, doubl ;CHECK-LABEL: test_v2f64_post_imm_ld2: ;CHECK: ld2.2d { v0, v1 }, [x0], #32 %ld2 = tail call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 4 + %tmp = getelementptr double, double* %A, i32 4 store double* %tmp, double** %ptr ret { <2 x double>, <2 x double> } %ld2 } @@ -835,7 +835,7 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_reg_ld2(double* %A, doubl ;CHECK-LABEL: test_v2f64_post_reg_ld2: ;CHECK: ld2.2d { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = tail call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <2 x double>, <2 x double> } %ld2 } @@ -847,7 +847,7 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld2(double* %A, doubl ;CHECK-LABEL: test_v1f64_post_imm_ld2: ;CHECK: ld1.1d { v0, v1 }, [x0], #16 %ld2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 2 + %tmp = getelementptr double, double* %A, i32 2 store double* %tmp, double** %ptr ret { <1 x double>, <1 x double> } %ld2 } @@ -856,7 +856,7 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_reg_ld2(double* %A, doubl ;CHECK-LABEL: test_v1f64_post_reg_ld2: ;CHECK: ld1.1d { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <1 x double>, <1 x double> } %ld2 } @@ -868,7 +868,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld3(i8* %A, i8** ;CHECK-LABEL: test_v16i8_post_imm_ld3: ;CHECK: ld3.16b { v0, v1, v2 }, [x0], #48 %ld3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 48 + %tmp = getelementptr i8, i8* %A, i32 48 store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3 } @@ -877,7 +877,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld3(i8* %A, i8** ;CHECK-LABEL: test_v16i8_post_reg_ld3: ;CHECK: ld3.16b { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3 } @@ -889,7 +889,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld3(i8* %A, i8** %pt ;CHECK-LABEL: test_v8i8_post_imm_ld3: ;CHECK: ld3.8b { v0, v1, v2 }, [x0], #24 %ld3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 24 + %tmp = getelementptr i8, i8* %A, i32 24 store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3 } @@ -898,7 +898,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld3(i8* %A, i8** %pt ;CHECK-LABEL: test_v8i8_post_reg_ld3: ;CHECK: ld3.8b { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3 } @@ -910,7 +910,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld3(i16* %A, i16 ;CHECK-LABEL: test_v8i16_post_imm_ld3: ;CHECK: ld3.8h { v0, v1, v2 }, [x0], #48 %ld3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 24 + %tmp = getelementptr i16, i16* %A, i32 24 store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3 } @@ -919,7 +919,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld3(i16* %A, i16 ;CHECK-LABEL: test_v8i16_post_reg_ld3: ;CHECK: ld3.8h { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3 } @@ -931,7 +931,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld3(i16* %A, i16 ;CHECK-LABEL: test_v4i16_post_imm_ld3: ;CHECK: ld3.4h { v0, v1, v2 }, [x0], #24 %ld3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 12 + %tmp = getelementptr i16, i16* %A, i32 12 store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3 } @@ -940,7 +940,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld3(i16* %A, i16 ;CHECK-LABEL: test_v4i16_post_reg_ld3: ;CHECK: ld3.4h { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3 } @@ -952,7 +952,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld3(i32* %A, i32 ;CHECK-LABEL: test_v4i32_post_imm_ld3: ;CHECK: ld3.4s { v0, v1, v2 }, [x0], #48 %ld3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 12 + %tmp = getelementptr i32, i32* %A, i32 12 store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3 } @@ -961,7 +961,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld3(i32* %A, i32 ;CHECK-LABEL: test_v4i32_post_reg_ld3: ;CHECK: ld3.4s { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3 } @@ -973,7 +973,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld3(i32* %A, i32 ;CHECK-LABEL: test_v2i32_post_imm_ld3: ;CHECK: ld3.2s { v0, v1, v2 }, [x0], #24 %ld3 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 6 + %tmp = getelementptr i32, i32* %A, i32 6 store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3 } @@ -982,7 +982,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld3(i32* %A, i32 ;CHECK-LABEL: test_v2i32_post_reg_ld3: ;CHECK: ld3.2s { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3 } @@ -994,7 +994,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld3(i64* %A, i64 ;CHECK-LABEL: test_v2i64_post_imm_ld3: ;CHECK: ld3.2d { v0, v1, v2 }, [x0], #48 %ld3 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 6 + %tmp = getelementptr i64, i64* %A, i32 6 store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3 } @@ -1003,7 +1003,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld3(i64* %A, i64 ;CHECK-LABEL: test_v2i64_post_reg_ld3: ;CHECK: ld3.2d { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3 } @@ -1015,7 +1015,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld3(i64* %A, i64 ;CHECK-LABEL: test_v1i64_post_imm_ld3: ;CHECK: ld1.1d { v0, v1, v2 }, [x0], #24 %ld3 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 3 + %tmp = getelementptr i64, i64* %A, i32 3 store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3 } @@ -1024,7 +1024,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld3(i64* %A, i64 ;CHECK-LABEL: test_v1i64_post_reg_ld3: ;CHECK: ld1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3 } @@ -1036,7 +1036,7 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld3(float* ;CHECK-LABEL: test_v4f32_post_imm_ld3: ;CHECK: ld3.4s { v0, v1, v2 }, [x0], #48 %ld3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 12 + %tmp = getelementptr float, float* %A, i32 12 store float* %tmp, float** %ptr ret { <4 x float>, <4 x float>, <4 x float> } %ld3 } @@ -1045,7 +1045,7 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld3(float* ;CHECK-LABEL: test_v4f32_post_reg_ld3: ;CHECK: ld3.4s { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <4 x float>, <4 x float>, <4 x float> } %ld3 } @@ -1057,7 +1057,7 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld3(float* ;CHECK-LABEL: test_v2f32_post_imm_ld3: ;CHECK: ld3.2s { v0, v1, v2 }, [x0], #24 %ld3 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 6 + %tmp = getelementptr float, float* %A, i32 6 store float* %tmp, float** %ptr ret { <2 x float>, <2 x float>, <2 x float> } %ld3 } @@ -1066,7 +1066,7 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld3(float* ;CHECK-LABEL: test_v2f32_post_reg_ld3: ;CHECK: ld3.2s { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <2 x float>, <2 x float>, <2 x float> } %ld3 } @@ -1078,7 +1078,7 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld3(dou ;CHECK-LABEL: test_v2f64_post_imm_ld3: ;CHECK: ld3.2d { v0, v1, v2 }, [x0], #48 %ld3 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 6 + %tmp = getelementptr double, double* %A, i32 6 store double* %tmp, double** %ptr ret { <2 x double>, <2 x double>, <2 x double> } %ld3 } @@ -1087,7 +1087,7 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld3(dou ;CHECK-LABEL: test_v2f64_post_reg_ld3: ;CHECK: ld3.2d { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <2 x double>, <2 x double>, <2 x double> } %ld3 } @@ -1099,7 +1099,7 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld3(dou ;CHECK-LABEL: test_v1f64_post_imm_ld3: ;CHECK: ld1.1d { v0, v1, v2 }, [x0], #24 %ld3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 3 + %tmp = getelementptr double, double* %A, i32 3 store double* %tmp, double** %ptr ret { <1 x double>, <1 x double>, <1 x double> } %ld3 } @@ -1108,7 +1108,7 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld3(dou ;CHECK-LABEL: test_v1f64_post_reg_ld3: ;CHECK: ld1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <1 x double>, <1 x double>, <1 x double> } %ld3 } @@ -1120,7 +1120,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld4(i ;CHECK-LABEL: test_v16i8_post_imm_ld4: ;CHECK: ld4.16b { v0, v1, v2, v3 }, [x0], #64 %ld4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 64 + %tmp = getelementptr i8, i8* %A, i32 64 store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4 } @@ -1129,7 +1129,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld4(i ;CHECK-LABEL: test_v16i8_post_reg_ld4: ;CHECK: ld4.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4 } @@ -1141,7 +1141,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld4(i8* %A ;CHECK-LABEL: test_v8i8_post_imm_ld4: ;CHECK: ld4.8b { v0, v1, v2, v3 }, [x0], #32 %ld4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 32 + %tmp = getelementptr i8, i8* %A, i32 32 store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4 } @@ -1150,7 +1150,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld4(i8* %A ;CHECK-LABEL: test_v8i8_post_reg_ld4: ;CHECK: ld4.8b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4 } @@ -1162,7 +1162,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld4(i ;CHECK-LABEL: test_v8i16_post_imm_ld4: ;CHECK: ld4.8h { v0, v1, v2, v3 }, [x0], #64 %ld4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 32 + %tmp = getelementptr i16, i16* %A, i32 32 store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4 } @@ -1171,7 +1171,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld4(i ;CHECK-LABEL: test_v8i16_post_reg_ld4: ;CHECK: ld4.8h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4 } @@ -1183,7 +1183,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld4(i ;CHECK-LABEL: test_v4i16_post_imm_ld4: ;CHECK: ld4.4h { v0, v1, v2, v3 }, [x0], #32 %ld4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 16 + %tmp = getelementptr i16, i16* %A, i32 16 store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4 } @@ -1192,7 +1192,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld4(i ;CHECK-LABEL: test_v4i16_post_reg_ld4: ;CHECK: ld4.4h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4 } @@ -1204,7 +1204,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld4(i ;CHECK-LABEL: test_v4i32_post_imm_ld4: ;CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], #64 %ld4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 16 + %tmp = getelementptr i32, i32* %A, i32 16 store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4 } @@ -1213,7 +1213,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld4(i ;CHECK-LABEL: test_v4i32_post_reg_ld4: ;CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4 } @@ -1225,7 +1225,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld4(i ;CHECK-LABEL: test_v2i32_post_imm_ld4: ;CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], #32 %ld4 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 8 + %tmp = getelementptr i32, i32* %A, i32 8 store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4 } @@ -1234,7 +1234,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld4(i ;CHECK-LABEL: test_v2i32_post_reg_ld4: ;CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4 } @@ -1246,7 +1246,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld4(i ;CHECK-LABEL: test_v2i64_post_imm_ld4: ;CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], #64 %ld4 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 8 + %tmp = getelementptr i64, i64* %A, i32 8 store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4 } @@ -1255,7 +1255,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld4(i ;CHECK-LABEL: test_v2i64_post_reg_ld4: ;CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4 } @@ -1267,7 +1267,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld4(i ;CHECK-LABEL: test_v1i64_post_imm_ld4: ;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], #32 %ld4 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 4 + %tmp = getelementptr i64, i64* %A, i32 4 store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4 } @@ -1276,7 +1276,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld4(i ;CHECK-LABEL: test_v1i64_post_reg_ld4: ;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4 } @@ -1288,7 +1288,7 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_i ;CHECK-LABEL: test_v4f32_post_imm_ld4: ;CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], #64 %ld4 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 16 + %tmp = getelementptr float, float* %A, i32 16 store float* %tmp, float** %ptr ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4 } @@ -1297,7 +1297,7 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_r ;CHECK-LABEL: test_v4f32_post_reg_ld4: ;CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4 } @@ -1309,7 +1309,7 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_i ;CHECK-LABEL: test_v2f32_post_imm_ld4: ;CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], #32 %ld4 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 8 + %tmp = getelementptr float, float* %A, i32 8 store float* %tmp, float** %ptr ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4 } @@ -1318,7 +1318,7 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_r ;CHECK-LABEL: test_v2f32_post_reg_ld4: ;CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4 } @@ -1330,7 +1330,7 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po ;CHECK-LABEL: test_v2f64_post_imm_ld4: ;CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], #64 %ld4 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 8 + %tmp = getelementptr double, double* %A, i32 8 store double* %tmp, double** %ptr ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4 } @@ -1339,7 +1339,7 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po ;CHECK-LABEL: test_v2f64_post_reg_ld4: ;CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4 } @@ -1351,7 +1351,7 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po ;CHECK-LABEL: test_v1f64_post_imm_ld4: ;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], #32 %ld4 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 4 + %tmp = getelementptr double, double* %A, i32 4 store double* %tmp, double** %ptr ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4 } @@ -1360,7 +1360,7 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po ;CHECK-LABEL: test_v1f64_post_reg_ld4: ;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4 } @@ -1371,7 +1371,7 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld1x2(i8* %A, i8** %ptr) { ;CHECK-LABEL: test_v16i8_post_imm_ld1x2: ;CHECK: ld1.16b { v0, v1 }, [x0], #32 %ld1x2 = tail call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x2.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 32 + %tmp = getelementptr i8, i8* %A, i32 32 store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8> } %ld1x2 } @@ -1380,7 +1380,7 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld1x2(i8* %A, i8** %ptr, i6 ;CHECK-LABEL: test_v16i8_post_reg_ld1x2: ;CHECK: ld1.16b { v0, v1 }, [x0], x{{[0-9]+}} %ld1x2 = tail call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x2.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8> } %ld1x2 } @@ -1392,7 +1392,7 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld1x2(i8* %A, i8** %ptr) { ;CHECK-LABEL: test_v8i8_post_imm_ld1x2: ;CHECK: ld1.8b { v0, v1 }, [x0], #16 %ld1x2 = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x2.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 16 + %tmp = getelementptr i8, i8* %A, i32 16 store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8> } %ld1x2 } @@ -1401,7 +1401,7 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld1x2(i8* %A, i8** %ptr, i64 % ;CHECK-LABEL: test_v8i8_post_reg_ld1x2: ;CHECK: ld1.8b { v0, v1 }, [x0], x{{[0-9]+}} %ld1x2 = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x2.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8> } %ld1x2 } @@ -1413,7 +1413,7 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld1x2(i16* %A, i16** %ptr) ;CHECK-LABEL: test_v8i16_post_imm_ld1x2: ;CHECK: ld1.8h { v0, v1 }, [x0], #32 %ld1x2 = tail call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x2.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 16 + %tmp = getelementptr i16, i16* %A, i32 16 store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16> } %ld1x2 } @@ -1422,7 +1422,7 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld1x2(i16* %A, i16** %ptr, ;CHECK-LABEL: test_v8i16_post_reg_ld1x2: ;CHECK: ld1.8h { v0, v1 }, [x0], x{{[0-9]+}} %ld1x2 = tail call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x2.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16> } %ld1x2 } @@ -1434,7 +1434,7 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld1x2(i16* %A, i16** %ptr) ;CHECK-LABEL: test_v4i16_post_imm_ld1x2: ;CHECK: ld1.4h { v0, v1 }, [x0], #16 %ld1x2 = tail call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 8 + %tmp = getelementptr i16, i16* %A, i32 8 store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16> } %ld1x2 } @@ -1443,7 +1443,7 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld1x2(i16* %A, i16** %ptr, ;CHECK-LABEL: test_v4i16_post_reg_ld1x2: ;CHECK: ld1.4h { v0, v1 }, [x0], x{{[0-9]+}} %ld1x2 = tail call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16> } %ld1x2 } @@ -1455,7 +1455,7 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld1x2(i32* %A, i32** %ptr) ;CHECK-LABEL: test_v4i32_post_imm_ld1x2: ;CHECK: ld1.4s { v0, v1 }, [x0], #32 %ld1x2 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x2.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 8 + %tmp = getelementptr i32, i32* %A, i32 8 store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32> } %ld1x2 } @@ -1464,7 +1464,7 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld1x2(i32* %A, i32** %ptr, ;CHECK-LABEL: test_v4i32_post_reg_ld1x2: ;CHECK: ld1.4s { v0, v1 }, [x0], x{{[0-9]+}} %ld1x2 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x2.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32> } %ld1x2 } @@ -1476,7 +1476,7 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld1x2(i32* %A, i32** %ptr) ;CHECK-LABEL: test_v2i32_post_imm_ld1x2: ;CHECK: ld1.2s { v0, v1 }, [x0], #16 %ld1x2 = tail call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x2.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 4 + %tmp = getelementptr i32, i32* %A, i32 4 store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32> } %ld1x2 } @@ -1485,7 +1485,7 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld1x2(i32* %A, i32** %ptr, ;CHECK-LABEL: test_v2i32_post_reg_ld1x2: ;CHECK: ld1.2s { v0, v1 }, [x0], x{{[0-9]+}} %ld1x2 = tail call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x2.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32> } %ld1x2 } @@ -1497,7 +1497,7 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld1x2(i64* %A, i64** %ptr) ;CHECK-LABEL: test_v2i64_post_imm_ld1x2: ;CHECK: ld1.2d { v0, v1 }, [x0], #32 %ld1x2 = tail call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x2.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 4 + %tmp = getelementptr i64, i64* %A, i32 4 store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64> } %ld1x2 } @@ -1506,7 +1506,7 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld1x2(i64* %A, i64** %ptr, ;CHECK-LABEL: test_v2i64_post_reg_ld1x2: ;CHECK: ld1.2d { v0, v1 }, [x0], x{{[0-9]+}} %ld1x2 = tail call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x2.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64> } %ld1x2 } @@ -1518,7 +1518,7 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld1x2(i64* %A, i64** %ptr) ;CHECK-LABEL: test_v1i64_post_imm_ld1x2: ;CHECK: ld1.1d { v0, v1 }, [x0], #16 %ld1x2 = tail call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x2.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 2 + %tmp = getelementptr i64, i64* %A, i32 2 store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64> } %ld1x2 } @@ -1527,7 +1527,7 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld1x2(i64* %A, i64** %ptr, ;CHECK-LABEL: test_v1i64_post_reg_ld1x2: ;CHECK: ld1.1d { v0, v1 }, [x0], x{{[0-9]+}} %ld1x2 = tail call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x2.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64> } %ld1x2 } @@ -1539,7 +1539,7 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld1x2(float* %A, float* ;CHECK-LABEL: test_v4f32_post_imm_ld1x2: ;CHECK: ld1.4s { v0, v1 }, [x0], #32 %ld1x2 = tail call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x2.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 8 + %tmp = getelementptr float, float* %A, i32 8 store float* %tmp, float** %ptr ret { <4 x float>, <4 x float> } %ld1x2 } @@ -1548,7 +1548,7 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_reg_ld1x2(float* %A, float* ;CHECK-LABEL: test_v4f32_post_reg_ld1x2: ;CHECK: ld1.4s { v0, v1 }, [x0], x{{[0-9]+}} %ld1x2 = tail call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x2.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <4 x float>, <4 x float> } %ld1x2 } @@ -1560,7 +1560,7 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld1x2(float* %A, float* ;CHECK-LABEL: test_v2f32_post_imm_ld1x2: ;CHECK: ld1.2s { v0, v1 }, [x0], #16 %ld1x2 = tail call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 4 + %tmp = getelementptr float, float* %A, i32 4 store float* %tmp, float** %ptr ret { <2 x float>, <2 x float> } %ld1x2 } @@ -1569,7 +1569,7 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_reg_ld1x2(float* %A, float* ;CHECK-LABEL: test_v2f32_post_reg_ld1x2: ;CHECK: ld1.2s { v0, v1 }, [x0], x{{[0-9]+}} %ld1x2 = tail call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <2 x float>, <2 x float> } %ld1x2 } @@ -1581,7 +1581,7 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld1x2(double* %A, dou ;CHECK-LABEL: test_v2f64_post_imm_ld1x2: ;CHECK: ld1.2d { v0, v1 }, [x0], #32 %ld1x2 = tail call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x2.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 4 + %tmp = getelementptr double, double* %A, i32 4 store double* %tmp, double** %ptr ret { <2 x double>, <2 x double> } %ld1x2 } @@ -1590,7 +1590,7 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_reg_ld1x2(double* %A, dou ;CHECK-LABEL: test_v2f64_post_reg_ld1x2: ;CHECK: ld1.2d { v0, v1 }, [x0], x{{[0-9]+}} %ld1x2 = tail call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x2.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <2 x double>, <2 x double> } %ld1x2 } @@ -1602,7 +1602,7 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld1x2(double* %A, dou ;CHECK-LABEL: test_v1f64_post_imm_ld1x2: ;CHECK: ld1.1d { v0, v1 }, [x0], #16 %ld1x2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x2.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 2 + %tmp = getelementptr double, double* %A, i32 2 store double* %tmp, double** %ptr ret { <1 x double>, <1 x double> } %ld1x2 } @@ -1611,7 +1611,7 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_reg_ld1x2(double* %A, dou ;CHECK-LABEL: test_v1f64_post_reg_ld1x2: ;CHECK: ld1.1d { v0, v1 }, [x0], x{{[0-9]+}} %ld1x2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x2.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <1 x double>, <1 x double> } %ld1x2 } @@ -1623,7 +1623,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld1x3(i8* %A, i8 ;CHECK-LABEL: test_v16i8_post_imm_ld1x3: ;CHECK: ld1.16b { v0, v1, v2 }, [x0], #48 %ld1x3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x3.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 48 + %tmp = getelementptr i8, i8* %A, i32 48 store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld1x3 } @@ -1632,7 +1632,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld1x3(i8* %A, i8 ;CHECK-LABEL: test_v16i8_post_reg_ld1x3: ;CHECK: ld1.16b { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld1x3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x3.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld1x3 } @@ -1644,7 +1644,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld1x3(i8* %A, i8** % ;CHECK-LABEL: test_v8i8_post_imm_ld1x3: ;CHECK: ld1.8b { v0, v1, v2 }, [x0], #24 %ld1x3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x3.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 24 + %tmp = getelementptr i8, i8* %A, i32 24 store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld1x3 } @@ -1653,7 +1653,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld1x3(i8* %A, i8** % ;CHECK-LABEL: test_v8i8_post_reg_ld1x3: ;CHECK: ld1.8b { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld1x3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x3.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld1x3 } @@ -1665,7 +1665,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld1x3(i16* %A, i ;CHECK-LABEL: test_v8i16_post_imm_ld1x3: ;CHECK: ld1.8h { v0, v1, v2 }, [x0], #48 %ld1x3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x3.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 24 + %tmp = getelementptr i16, i16* %A, i32 24 store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld1x3 } @@ -1674,7 +1674,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld1x3(i16* %A, i ;CHECK-LABEL: test_v8i16_post_reg_ld1x3: ;CHECK: ld1.8h { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld1x3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x3.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld1x3 } @@ -1686,7 +1686,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld1x3(i16* %A, i ;CHECK-LABEL: test_v4i16_post_imm_ld1x3: ;CHECK: ld1.4h { v0, v1, v2 }, [x0], #24 %ld1x3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x3.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 12 + %tmp = getelementptr i16, i16* %A, i32 12 store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld1x3 } @@ -1695,7 +1695,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld1x3(i16* %A, i ;CHECK-LABEL: test_v4i16_post_reg_ld1x3: ;CHECK: ld1.4h { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld1x3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x3.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld1x3 } @@ -1707,7 +1707,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld1x3(i32* %A, i ;CHECK-LABEL: test_v4i32_post_imm_ld1x3: ;CHECK: ld1.4s { v0, v1, v2 }, [x0], #48 %ld1x3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x3.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 12 + %tmp = getelementptr i32, i32* %A, i32 12 store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld1x3 } @@ -1716,7 +1716,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld1x3(i32* %A, i ;CHECK-LABEL: test_v4i32_post_reg_ld1x3: ;CHECK: ld1.4s { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld1x3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x3.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld1x3 } @@ -1728,7 +1728,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld1x3(i32* %A, i ;CHECK-LABEL: test_v2i32_post_imm_ld1x3: ;CHECK: ld1.2s { v0, v1, v2 }, [x0], #24 %ld1x3 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x3.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 6 + %tmp = getelementptr i32, i32* %A, i32 6 store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld1x3 } @@ -1737,7 +1737,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld1x3(i32* %A, i ;CHECK-LABEL: test_v2i32_post_reg_ld1x3: ;CHECK: ld1.2s { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld1x3 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x3.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld1x3 } @@ -1749,7 +1749,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld1x3(i64* %A, i ;CHECK-LABEL: test_v2i64_post_imm_ld1x3: ;CHECK: ld1.2d { v0, v1, v2 }, [x0], #48 %ld1x3 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x3.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 6 + %tmp = getelementptr i64, i64* %A, i32 6 store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld1x3 } @@ -1758,7 +1758,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld1x3(i64* %A, i ;CHECK-LABEL: test_v2i64_post_reg_ld1x3: ;CHECK: ld1.2d { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld1x3 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x3.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld1x3 } @@ -1770,7 +1770,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld1x3(i64* %A, i ;CHECK-LABEL: test_v1i64_post_imm_ld1x3: ;CHECK: ld1.1d { v0, v1, v2 }, [x0], #24 %ld1x3 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x3.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 3 + %tmp = getelementptr i64, i64* %A, i32 3 store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld1x3 } @@ -1779,7 +1779,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld1x3(i64* %A, i ;CHECK-LABEL: test_v1i64_post_reg_ld1x3: ;CHECK: ld1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld1x3 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x3.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld1x3 } @@ -1791,7 +1791,7 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld1x3(floa ;CHECK-LABEL: test_v4f32_post_imm_ld1x3: ;CHECK: ld1.4s { v0, v1, v2 }, [x0], #48 %ld1x3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x3.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 12 + %tmp = getelementptr float, float* %A, i32 12 store float* %tmp, float** %ptr ret { <4 x float>, <4 x float>, <4 x float> } %ld1x3 } @@ -1800,7 +1800,7 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld1x3(floa ;CHECK-LABEL: test_v4f32_post_reg_ld1x3: ;CHECK: ld1.4s { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld1x3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x3.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <4 x float>, <4 x float>, <4 x float> } %ld1x3 } @@ -1812,7 +1812,7 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld1x3(floa ;CHECK-LABEL: test_v2f32_post_imm_ld1x3: ;CHECK: ld1.2s { v0, v1, v2 }, [x0], #24 %ld1x3 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 6 + %tmp = getelementptr float, float* %A, i32 6 store float* %tmp, float** %ptr ret { <2 x float>, <2 x float>, <2 x float> } %ld1x3 } @@ -1821,7 +1821,7 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld1x3(floa ;CHECK-LABEL: test_v2f32_post_reg_ld1x3: ;CHECK: ld1.2s { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld1x3 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <2 x float>, <2 x float>, <2 x float> } %ld1x3 } @@ -1833,7 +1833,7 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld1x3(d ;CHECK-LABEL: test_v2f64_post_imm_ld1x3: ;CHECK: ld1.2d { v0, v1, v2 }, [x0], #48 %ld1x3 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x3.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 6 + %tmp = getelementptr double, double* %A, i32 6 store double* %tmp, double** %ptr ret { <2 x double>, <2 x double>, <2 x double> } %ld1x3 } @@ -1842,7 +1842,7 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld1x3(d ;CHECK-LABEL: test_v2f64_post_reg_ld1x3: ;CHECK: ld1.2d { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld1x3 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x3.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <2 x double>, <2 x double>, <2 x double> } %ld1x3 } @@ -1854,7 +1854,7 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld1x3(d ;CHECK-LABEL: test_v1f64_post_imm_ld1x3: ;CHECK: ld1.1d { v0, v1, v2 }, [x0], #24 %ld1x3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x3.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 3 + %tmp = getelementptr double, double* %A, i32 3 store double* %tmp, double** %ptr ret { <1 x double>, <1 x double>, <1 x double> } %ld1x3 } @@ -1863,7 +1863,7 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld1x3(d ;CHECK-LABEL: test_v1f64_post_reg_ld1x3: ;CHECK: ld1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld1x3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x3.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <1 x double>, <1 x double>, <1 x double> } %ld1x3 } @@ -1875,7 +1875,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld1x4 ;CHECK-LABEL: test_v16i8_post_imm_ld1x4: ;CHECK: ld1.16b { v0, v1, v2, v3 }, [x0], #64 %ld1x4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x4.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 64 + %tmp = getelementptr i8, i8* %A, i32 64 store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld1x4 } @@ -1884,7 +1884,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld1x4 ;CHECK-LABEL: test_v16i8_post_reg_ld1x4: ;CHECK: ld1.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld1x4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x4.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld1x4 } @@ -1896,7 +1896,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld1x4(i8* ;CHECK-LABEL: test_v8i8_post_imm_ld1x4: ;CHECK: ld1.8b { v0, v1, v2, v3 }, [x0], #32 %ld1x4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x4.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 32 + %tmp = getelementptr i8, i8* %A, i32 32 store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld1x4 } @@ -1905,7 +1905,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld1x4(i8* ;CHECK-LABEL: test_v8i8_post_reg_ld1x4: ;CHECK: ld1.8b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld1x4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x4.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld1x4 } @@ -1917,7 +1917,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld1x4 ;CHECK-LABEL: test_v8i16_post_imm_ld1x4: ;CHECK: ld1.8h { v0, v1, v2, v3 }, [x0], #64 %ld1x4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x4.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 32 + %tmp = getelementptr i16, i16* %A, i32 32 store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld1x4 } @@ -1926,7 +1926,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld1x4 ;CHECK-LABEL: test_v8i16_post_reg_ld1x4: ;CHECK: ld1.8h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld1x4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x4.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld1x4 } @@ -1938,7 +1938,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld1x4 ;CHECK-LABEL: test_v4i16_post_imm_ld1x4: ;CHECK: ld1.4h { v0, v1, v2, v3 }, [x0], #32 %ld1x4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x4.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 16 + %tmp = getelementptr i16, i16* %A, i32 16 store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld1x4 } @@ -1947,7 +1947,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld1x4 ;CHECK-LABEL: test_v4i16_post_reg_ld1x4: ;CHECK: ld1.4h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld1x4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x4.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld1x4 } @@ -1959,7 +1959,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld1x4 ;CHECK-LABEL: test_v4i32_post_imm_ld1x4: ;CHECK: ld1.4s { v0, v1, v2, v3 }, [x0], #64 %ld1x4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x4.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 16 + %tmp = getelementptr i32, i32* %A, i32 16 store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld1x4 } @@ -1968,7 +1968,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld1x4 ;CHECK-LABEL: test_v4i32_post_reg_ld1x4: ;CHECK: ld1.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld1x4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x4.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld1x4 } @@ -1980,7 +1980,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld1x4 ;CHECK-LABEL: test_v2i32_post_imm_ld1x4: ;CHECK: ld1.2s { v0, v1, v2, v3 }, [x0], #32 %ld1x4 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x4.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 8 + %tmp = getelementptr i32, i32* %A, i32 8 store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld1x4 } @@ -1989,7 +1989,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld1x4 ;CHECK-LABEL: test_v2i32_post_reg_ld1x4: ;CHECK: ld1.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld1x4 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x4.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld1x4 } @@ -2001,7 +2001,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld1x4 ;CHECK-LABEL: test_v2i64_post_imm_ld1x4: ;CHECK: ld1.2d { v0, v1, v2, v3 }, [x0], #64 %ld1x4 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x4.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 8 + %tmp = getelementptr i64, i64* %A, i32 8 store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld1x4 } @@ -2010,7 +2010,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld1x4 ;CHECK-LABEL: test_v2i64_post_reg_ld1x4: ;CHECK: ld1.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld1x4 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x4.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld1x4 } @@ -2022,7 +2022,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld1x4 ;CHECK-LABEL: test_v1i64_post_imm_ld1x4: ;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], #32 %ld1x4 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x4.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 4 + %tmp = getelementptr i64, i64* %A, i32 4 store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld1x4 } @@ -2031,7 +2031,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld1x4 ;CHECK-LABEL: test_v1i64_post_reg_ld1x4: ;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld1x4 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x4.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld1x4 } @@ -2043,7 +2043,7 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_i ;CHECK-LABEL: test_v4f32_post_imm_ld1x4: ;CHECK: ld1.4s { v0, v1, v2, v3 }, [x0], #64 %ld1x4 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x4.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 16 + %tmp = getelementptr float, float* %A, i32 16 store float* %tmp, float** %ptr ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld1x4 } @@ -2052,7 +2052,7 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_r ;CHECK-LABEL: test_v4f32_post_reg_ld1x4: ;CHECK: ld1.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld1x4 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x4.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld1x4 } @@ -2064,7 +2064,7 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_i ;CHECK-LABEL: test_v2f32_post_imm_ld1x4: ;CHECK: ld1.2s { v0, v1, v2, v3 }, [x0], #32 %ld1x4 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 8 + %tmp = getelementptr float, float* %A, i32 8 store float* %tmp, float** %ptr ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld1x4 } @@ -2073,7 +2073,7 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_r ;CHECK-LABEL: test_v2f32_post_reg_ld1x4: ;CHECK: ld1.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld1x4 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld1x4 } @@ -2085,7 +2085,7 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po ;CHECK-LABEL: test_v2f64_post_imm_ld1x4: ;CHECK: ld1.2d { v0, v1, v2, v3 }, [x0], #64 %ld1x4 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x4.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 8 + %tmp = getelementptr double, double* %A, i32 8 store double* %tmp, double** %ptr ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld1x4 } @@ -2094,7 +2094,7 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po ;CHECK-LABEL: test_v2f64_post_reg_ld1x4: ;CHECK: ld1.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld1x4 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x4.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld1x4 } @@ -2106,7 +2106,7 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po ;CHECK-LABEL: test_v1f64_post_imm_ld1x4: ;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], #32 %ld1x4 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x4.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 4 + %tmp = getelementptr double, double* %A, i32 4 store double* %tmp, double** %ptr ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld1x4 } @@ -2115,7 +2115,7 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po ;CHECK-LABEL: test_v1f64_post_reg_ld1x4: ;CHECK: ld1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld1x4 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x4.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld1x4 } @@ -2127,7 +2127,7 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2r(i8* %A, i8** %ptr) nou ;CHECK-LABEL: test_v16i8_post_imm_ld2r: ;CHECK: ld2r.16b { v0, v1 }, [x0], #2 %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 2 + %tmp = getelementptr i8, i8* %A, i32 2 store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8> } %ld2 } @@ -2136,7 +2136,7 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld2r(i8* %A, i8** %ptr, i64 ;CHECK-LABEL: test_v16i8_post_reg_ld2r: ;CHECK: ld2r.16b { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8> } %ld2 } @@ -2148,7 +2148,7 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld2r(i8* %A, i8** %ptr) nounwi ;CHECK-LABEL: test_v8i8_post_imm_ld2r: ;CHECK: ld2r.8b { v0, v1 }, [x0], #2 %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 2 + %tmp = getelementptr i8, i8* %A, i32 2 store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8> } %ld2 } @@ -2157,7 +2157,7 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld2r(i8* %A, i8** %ptr, i64 %i ;CHECK-LABEL: test_v8i8_post_reg_ld2r: ;CHECK: ld2r.8b { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8> } %ld2 } @@ -2169,7 +2169,7 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld2r(i16* %A, i16** %ptr) n ;CHECK-LABEL: test_v8i16_post_imm_ld2r: ;CHECK: ld2r.8h { v0, v1 }, [x0], #4 %ld2 = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2r.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 2 + %tmp = getelementptr i16, i16* %A, i32 2 store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16> } %ld2 } @@ -2178,7 +2178,7 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld2r(i16* %A, i16** %ptr, i ;CHECK-LABEL: test_v8i16_post_reg_ld2r: ;CHECK: ld2r.8h { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2r.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16> } %ld2 } @@ -2190,7 +2190,7 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld2r(i16* %A, i16** %ptr) n ;CHECK-LABEL: test_v4i16_post_imm_ld2r: ;CHECK: ld2r.4h { v0, v1 }, [x0], #4 %ld2 = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2r.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 2 + %tmp = getelementptr i16, i16* %A, i32 2 store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16> } %ld2 } @@ -2199,7 +2199,7 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld2r(i16* %A, i16** %ptr, i ;CHECK-LABEL: test_v4i16_post_reg_ld2r: ;CHECK: ld2r.4h { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2r.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16> } %ld2 } @@ -2211,7 +2211,7 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld2r(i32* %A, i32** %ptr) n ;CHECK-LABEL: test_v4i32_post_imm_ld2r: ;CHECK: ld2r.4s { v0, v1 }, [x0], #8 %ld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2r.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 2 + %tmp = getelementptr i32, i32* %A, i32 2 store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32> } %ld2 } @@ -2220,7 +2220,7 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld2r(i32* %A, i32** %ptr, i ;CHECK-LABEL: test_v4i32_post_reg_ld2r: ;CHECK: ld2r.4s { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2r.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32> } %ld2 } @@ -2231,7 +2231,7 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld2r(i32* %A, i32** %ptr) n ;CHECK-LABEL: test_v2i32_post_imm_ld2r: ;CHECK: ld2r.2s { v0, v1 }, [x0], #8 %ld2 = call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2r.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 2 + %tmp = getelementptr i32, i32* %A, i32 2 store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32> } %ld2 } @@ -2240,7 +2240,7 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld2r(i32* %A, i32** %ptr, i ;CHECK-LABEL: test_v2i32_post_reg_ld2r: ;CHECK: ld2r.2s { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2r.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32> } %ld2 } @@ -2252,7 +2252,7 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld2r(i64* %A, i64** %ptr) n ;CHECK-LABEL: test_v2i64_post_imm_ld2r: ;CHECK: ld2r.2d { v0, v1 }, [x0], #16 %ld2 = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2r.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 2 + %tmp = getelementptr i64, i64* %A, i32 2 store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64> } %ld2 } @@ -2261,7 +2261,7 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld2r(i64* %A, i64** %ptr, i ;CHECK-LABEL: test_v2i64_post_reg_ld2r: ;CHECK: ld2r.2d { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2r.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64> } %ld2 } @@ -2272,7 +2272,7 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld2r(i64* %A, i64** %ptr) n ;CHECK-LABEL: test_v1i64_post_imm_ld2r: ;CHECK: ld2r.1d { v0, v1 }, [x0], #16 %ld2 = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2r.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 2 + %tmp = getelementptr i64, i64* %A, i32 2 store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64> } %ld2 } @@ -2281,7 +2281,7 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld2r(i64* %A, i64** %ptr, i ;CHECK-LABEL: test_v1i64_post_reg_ld2r: ;CHECK: ld2r.1d { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2r.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64> } %ld2 } @@ -2293,7 +2293,7 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld2r(float* %A, float** ;CHECK-LABEL: test_v4f32_post_imm_ld2r: ;CHECK: ld2r.4s { v0, v1 }, [x0], #8 %ld2 = call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2r.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 2 + %tmp = getelementptr float, float* %A, i32 2 store float* %tmp, float** %ptr ret { <4 x float>, <4 x float> } %ld2 } @@ -2302,7 +2302,7 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_reg_ld2r(float* %A, float** ;CHECK-LABEL: test_v4f32_post_reg_ld2r: ;CHECK: ld2r.4s { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2r.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <4 x float>, <4 x float> } %ld2 } @@ -2313,7 +2313,7 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld2r(float* %A, float** ;CHECK-LABEL: test_v2f32_post_imm_ld2r: ;CHECK: ld2r.2s { v0, v1 }, [x0], #8 %ld2 = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2r.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 2 + %tmp = getelementptr float, float* %A, i32 2 store float* %tmp, float** %ptr ret { <2 x float>, <2 x float> } %ld2 } @@ -2322,7 +2322,7 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_reg_ld2r(float* %A, float** ;CHECK-LABEL: test_v2f32_post_reg_ld2r: ;CHECK: ld2r.2s { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2r.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <2 x float>, <2 x float> } %ld2 } @@ -2334,7 +2334,7 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld2r(double* %A, doub ;CHECK-LABEL: test_v2f64_post_imm_ld2r: ;CHECK: ld2r.2d { v0, v1 }, [x0], #16 %ld2 = call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2r.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 2 + %tmp = getelementptr double, double* %A, i32 2 store double* %tmp, double** %ptr ret { <2 x double>, <2 x double> } %ld2 } @@ -2343,7 +2343,7 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_reg_ld2r(double* %A, doub ;CHECK-LABEL: test_v2f64_post_reg_ld2r: ;CHECK: ld2r.2d { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2r.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <2 x double>, <2 x double> } %ld2 } @@ -2354,7 +2354,7 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld2r(double* %A, doub ;CHECK-LABEL: test_v1f64_post_imm_ld2r: ;CHECK: ld2r.1d { v0, v1 }, [x0], #16 %ld2 = call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2r.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 2 + %tmp = getelementptr double, double* %A, i32 2 store double* %tmp, double** %ptr ret { <1 x double>, <1 x double> } %ld2 } @@ -2363,7 +2363,7 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_reg_ld2r(double* %A, doub ;CHECK-LABEL: test_v1f64_post_reg_ld2r: ;CHECK: ld2r.1d { v0, v1 }, [x0], x{{[0-9]+}} %ld2 = call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2r.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <1 x double>, <1 x double> } %ld2 } @@ -2375,7 +2375,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld3r(i8* %A, i8* ;CHECK-LABEL: test_v16i8_post_imm_ld3r: ;CHECK: ld3r.16b { v0, v1, v2 }, [x0], #3 %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 3 + %tmp = getelementptr i8, i8* %A, i32 3 store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3 } @@ -2384,7 +2384,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld3r(i8* %A, i8* ;CHECK-LABEL: test_v16i8_post_reg_ld3r: ;CHECK: ld3r.16b { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3 } @@ -2396,7 +2396,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld3r(i8* %A, i8** %p ;CHECK-LABEL: test_v8i8_post_imm_ld3r: ;CHECK: ld3r.8b { v0, v1, v2 }, [x0], #3 %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 3 + %tmp = getelementptr i8, i8* %A, i32 3 store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3 } @@ -2405,7 +2405,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld3r(i8* %A, i8** %p ;CHECK-LABEL: test_v8i8_post_reg_ld3r: ;CHECK: ld3r.8b { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3 } @@ -2417,7 +2417,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld3r(i16* %A, i1 ;CHECK-LABEL: test_v8i16_post_imm_ld3r: ;CHECK: ld3r.8h { v0, v1, v2 }, [x0], #6 %ld3 = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3r.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 3 + %tmp = getelementptr i16, i16* %A, i32 3 store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3 } @@ -2426,7 +2426,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld3r(i16* %A, i1 ;CHECK-LABEL: test_v8i16_post_reg_ld3r: ;CHECK: ld3r.8h { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3r.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3 } @@ -2438,7 +2438,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld3r(i16* %A, i1 ;CHECK-LABEL: test_v4i16_post_imm_ld3r: ;CHECK: ld3r.4h { v0, v1, v2 }, [x0], #6 %ld3 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3r.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 3 + %tmp = getelementptr i16, i16* %A, i32 3 store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3 } @@ -2447,7 +2447,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld3r(i16* %A, i1 ;CHECK-LABEL: test_v4i16_post_reg_ld3r: ;CHECK: ld3r.4h { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3r.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3 } @@ -2459,7 +2459,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld3r(i32* %A, i3 ;CHECK-LABEL: test_v4i32_post_imm_ld3r: ;CHECK: ld3r.4s { v0, v1, v2 }, [x0], #12 %ld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3r.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 3 + %tmp = getelementptr i32, i32* %A, i32 3 store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3 } @@ -2468,7 +2468,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld3r(i32* %A, i3 ;CHECK-LABEL: test_v4i32_post_reg_ld3r: ;CHECK: ld3r.4s { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3r.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3 } @@ -2479,7 +2479,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld3r(i32* %A, i3 ;CHECK-LABEL: test_v2i32_post_imm_ld3r: ;CHECK: ld3r.2s { v0, v1, v2 }, [x0], #12 %ld3 = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3r.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 3 + %tmp = getelementptr i32, i32* %A, i32 3 store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3 } @@ -2488,7 +2488,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld3r(i32* %A, i3 ;CHECK-LABEL: test_v2i32_post_reg_ld3r: ;CHECK: ld3r.2s { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3r.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3 } @@ -2500,7 +2500,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld3r(i64* %A, i6 ;CHECK-LABEL: test_v2i64_post_imm_ld3r: ;CHECK: ld3r.2d { v0, v1, v2 }, [x0], #24 %ld3 = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3r.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 3 + %tmp = getelementptr i64, i64* %A, i32 3 store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3 } @@ -2509,7 +2509,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld3r(i64* %A, i6 ;CHECK-LABEL: test_v2i64_post_reg_ld3r: ;CHECK: ld3r.2d { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3r.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3 } @@ -2520,7 +2520,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld3r(i64* %A, i6 ;CHECK-LABEL: test_v1i64_post_imm_ld3r: ;CHECK: ld3r.1d { v0, v1, v2 }, [x0], #24 %ld3 = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3r.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 3 + %tmp = getelementptr i64, i64* %A, i32 3 store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3 } @@ -2529,7 +2529,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld3r(i64* %A, i6 ;CHECK-LABEL: test_v1i64_post_reg_ld3r: ;CHECK: ld3r.1d { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3r.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3 } @@ -2541,7 +2541,7 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld3r(float ;CHECK-LABEL: test_v4f32_post_imm_ld3r: ;CHECK: ld3r.4s { v0, v1, v2 }, [x0], #12 %ld3 = call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3r.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 3 + %tmp = getelementptr float, float* %A, i32 3 store float* %tmp, float** %ptr ret { <4 x float>, <4 x float>, <4 x float> } %ld3 } @@ -2550,7 +2550,7 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld3r(float ;CHECK-LABEL: test_v4f32_post_reg_ld3r: ;CHECK: ld3r.4s { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3r.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <4 x float>, <4 x float>, <4 x float> } %ld3 } @@ -2561,7 +2561,7 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld3r(float ;CHECK-LABEL: test_v2f32_post_imm_ld3r: ;CHECK: ld3r.2s { v0, v1, v2 }, [x0], #12 %ld3 = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3r.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 3 + %tmp = getelementptr float, float* %A, i32 3 store float* %tmp, float** %ptr ret { <2 x float>, <2 x float>, <2 x float> } %ld3 } @@ -2570,7 +2570,7 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld3r(float ;CHECK-LABEL: test_v2f32_post_reg_ld3r: ;CHECK: ld3r.2s { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3r.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <2 x float>, <2 x float>, <2 x float> } %ld3 } @@ -2582,7 +2582,7 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld3r(do ;CHECK-LABEL: test_v2f64_post_imm_ld3r: ;CHECK: ld3r.2d { v0, v1, v2 }, [x0], #24 %ld3 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3r.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 3 + %tmp = getelementptr double, double* %A, i32 3 store double* %tmp, double** %ptr ret { <2 x double>, <2 x double>, <2 x double> } %ld3 } @@ -2591,7 +2591,7 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld3r(do ;CHECK-LABEL: test_v2f64_post_reg_ld3r: ;CHECK: ld3r.2d { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3r.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <2 x double>, <2 x double>, <2 x double> } %ld3 } @@ -2602,7 +2602,7 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld3r(do ;CHECK-LABEL: test_v1f64_post_imm_ld3r: ;CHECK: ld3r.1d { v0, v1, v2 }, [x0], #24 %ld3 = call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3r.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 3 + %tmp = getelementptr double, double* %A, i32 3 store double* %tmp, double** %ptr ret { <1 x double>, <1 x double>, <1 x double> } %ld3 } @@ -2611,7 +2611,7 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld3r(do ;CHECK-LABEL: test_v1f64_post_reg_ld3r: ;CHECK: ld3r.1d { v0, v1, v2 }, [x0], x{{[0-9]+}} %ld3 = call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3r.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <1 x double>, <1 x double>, <1 x double> } %ld3 } @@ -2623,7 +2623,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld4r( ;CHECK-LABEL: test_v16i8_post_imm_ld4r: ;CHECK: ld4r.16b { v0, v1, v2, v3 }, [x0], #4 %ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4r.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 4 + %tmp = getelementptr i8, i8* %A, i32 4 store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4 } @@ -2632,7 +2632,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld4r( ;CHECK-LABEL: test_v16i8_post_reg_ld4r: ;CHECK: ld4r.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4r.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4 } @@ -2644,7 +2644,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld4r(i8* % ;CHECK-LABEL: test_v8i8_post_imm_ld4r: ;CHECK: ld4r.8b { v0, v1, v2, v3 }, [x0], #4 %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4r.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 4 + %tmp = getelementptr i8, i8* %A, i32 4 store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4 } @@ -2653,7 +2653,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld4r(i8* % ;CHECK-LABEL: test_v8i8_post_reg_ld4r: ;CHECK: ld4r.8b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4r.v8i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4 } @@ -2665,7 +2665,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld4r( ;CHECK-LABEL: test_v8i16_post_imm_ld4r: ;CHECK: ld4r.8h { v0, v1, v2, v3 }, [x0], #8 %ld4 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4r.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 4 + %tmp = getelementptr i16, i16* %A, i32 4 store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4 } @@ -2674,7 +2674,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld4r( ;CHECK-LABEL: test_v8i16_post_reg_ld4r: ;CHECK: ld4r.8h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4r.v8i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4 } @@ -2686,7 +2686,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld4r( ;CHECK-LABEL: test_v4i16_post_imm_ld4r: ;CHECK: ld4r.4h { v0, v1, v2, v3 }, [x0], #8 %ld4 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4r.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i32 4 + %tmp = getelementptr i16, i16* %A, i32 4 store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4 } @@ -2695,7 +2695,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld4r( ;CHECK-LABEL: test_v4i16_post_reg_ld4r: ;CHECK: ld4r.4h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4r.v4i16.p0i16(i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4 } @@ -2707,7 +2707,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld4r( ;CHECK-LABEL: test_v4i32_post_imm_ld4r: ;CHECK: ld4r.4s { v0, v1, v2, v3 }, [x0], #16 %ld4 = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4r.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 4 + %tmp = getelementptr i32, i32* %A, i32 4 store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4 } @@ -2716,7 +2716,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld4r( ;CHECK-LABEL: test_v4i32_post_reg_ld4r: ;CHECK: ld4r.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4r.v4i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4 } @@ -2727,7 +2727,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld4r( ;CHECK-LABEL: test_v2i32_post_imm_ld4r: ;CHECK: ld4r.2s { v0, v1, v2, v3 }, [x0], #16 %ld4 = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4r.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i32 4 + %tmp = getelementptr i32, i32* %A, i32 4 store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4 } @@ -2736,7 +2736,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld4r( ;CHECK-LABEL: test_v2i32_post_reg_ld4r: ;CHECK: ld4r.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4r.v2i32.p0i32(i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4 } @@ -2748,7 +2748,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld4r( ;CHECK-LABEL: test_v2i64_post_imm_ld4r: ;CHECK: ld4r.2d { v0, v1, v2, v3 }, [x0], #32 %ld4 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4r.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 4 + %tmp = getelementptr i64, i64* %A, i32 4 store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4 } @@ -2757,7 +2757,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld4r( ;CHECK-LABEL: test_v2i64_post_reg_ld4r: ;CHECK: ld4r.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4r.v2i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4 } @@ -2768,7 +2768,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld4r( ;CHECK-LABEL: test_v1i64_post_imm_ld4r: ;CHECK: ld4r.1d { v0, v1, v2, v3 }, [x0], #32 %ld4 = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4r.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i32 4 + %tmp = getelementptr i64, i64* %A, i32 4 store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4 } @@ -2777,7 +2777,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld4r( ;CHECK-LABEL: test_v1i64_post_reg_ld4r: ;CHECK: ld4r.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4r.v1i64.p0i64(i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4 } @@ -2789,7 +2789,7 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_i ;CHECK-LABEL: test_v4f32_post_imm_ld4r: ;CHECK: ld4r.4s { v0, v1, v2, v3 }, [x0], #16 %ld4 = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4r.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 4 + %tmp = getelementptr float, float* %A, i32 4 store float* %tmp, float** %ptr ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4 } @@ -2798,7 +2798,7 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_r ;CHECK-LABEL: test_v4f32_post_reg_ld4r: ;CHECK: ld4r.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4r.v4f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4 } @@ -2809,7 +2809,7 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_i ;CHECK-LABEL: test_v2f32_post_imm_ld4r: ;CHECK: ld4r.2s { v0, v1, v2, v3 }, [x0], #16 %ld4 = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4r.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i32 4 + %tmp = getelementptr float, float* %A, i32 4 store float* %tmp, float** %ptr ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4 } @@ -2818,7 +2818,7 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_r ;CHECK-LABEL: test_v2f32_post_reg_ld4r: ;CHECK: ld4r.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4r.v2f32.p0f32(float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4 } @@ -2830,7 +2830,7 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po ;CHECK-LABEL: test_v2f64_post_imm_ld4r: ;CHECK: ld4r.2d { v0, v1, v2, v3 }, [x0], #32 %ld4 = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4r.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 4 + %tmp = getelementptr double, double* %A, i32 4 store double* %tmp, double** %ptr ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4 } @@ -2839,7 +2839,7 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po ;CHECK-LABEL: test_v2f64_post_reg_ld4r: ;CHECK: ld4r.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4r.v2f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4 } @@ -2850,7 +2850,7 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po ;CHECK-LABEL: test_v1f64_post_imm_ld4r: ;CHECK: ld4r.1d { v0, v1, v2, v3 }, [x0], #32 %ld4 = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4r.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i32 4 + %tmp = getelementptr double, double* %A, i32 4 store double* %tmp, double** %ptr ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4 } @@ -2859,7 +2859,7 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po ;CHECK-LABEL: test_v1f64_post_reg_ld4r: ;CHECK: ld4r.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} %ld4 = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4r.v1f64.p0f64(double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4 } @@ -2871,7 +2871,7 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2lane(i8* %A, i8** %ptr, ;CHECK-LABEL: test_v16i8_post_imm_ld2lane: ;CHECK: ld2.b { v0, v1 }[0], [x0], #2 %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i32 2 + %tmp = getelementptr i8, i8* %A, i32 2 store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8> } %ld2 } @@ -2880,7 +2880,7 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld2lane(i8* %A, i8** %ptr, ;CHECK-LABEL: test_v16i8_post_reg_ld2lane: ;CHECK: ld2.b { v0, v1 }[0], [x0], x{{[0-9]+}} %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8> } %ld2 } @@ -2892,7 +2892,7 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld2lane(i8* %A, i8** %ptr, <8 ;CHECK-LABEL: test_v8i8_post_imm_ld2lane: ;CHECK: ld2.b { v0, v1 }[0], [x0], #2 %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i32 2 + %tmp = getelementptr i8, i8* %A, i32 2 store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8> } %ld2 } @@ -2901,7 +2901,7 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld2lane(i8* %A, i8** %ptr, i64 ;CHECK-LABEL: test_v8i8_post_reg_ld2lane: ;CHECK: ld2.b { v0, v1 }[0], [x0], x{{[0-9]+}} %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8> } %ld2 } @@ -2913,7 +2913,7 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld2lane(i16* %A, i16** %ptr ;CHECK-LABEL: test_v8i16_post_imm_ld2lane: ;CHECK: ld2.h { v0, v1 }[0], [x0], #4 %ld2 = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i32 2 + %tmp = getelementptr i16, i16* %A, i32 2 store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16> } %ld2 } @@ -2922,7 +2922,7 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld2lane(i16* %A, i16** %ptr ;CHECK-LABEL: test_v8i16_post_reg_ld2lane: ;CHECK: ld2.h { v0, v1 }[0], [x0], x{{[0-9]+}} %ld2 = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16> } %ld2 } @@ -2934,7 +2934,7 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld2lane(i16* %A, i16** %ptr ;CHECK-LABEL: test_v4i16_post_imm_ld2lane: ;CHECK: ld2.h { v0, v1 }[0], [x0], #4 %ld2 = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i32 2 + %tmp = getelementptr i16, i16* %A, i32 2 store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16> } %ld2 } @@ -2943,7 +2943,7 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld2lane(i16* %A, i16** %ptr ;CHECK-LABEL: test_v4i16_post_reg_ld2lane: ;CHECK: ld2.h { v0, v1 }[0], [x0], x{{[0-9]+}} %ld2 = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16> } %ld2 } @@ -2955,7 +2955,7 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld2lane(i32* %A, i32** %ptr ;CHECK-LABEL: test_v4i32_post_imm_ld2lane: ;CHECK: ld2.s { v0, v1 }[0], [x0], #8 %ld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i32 2 + %tmp = getelementptr i32, i32* %A, i32 2 store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32> } %ld2 } @@ -2964,7 +2964,7 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld2lane(i32* %A, i32** %ptr ;CHECK-LABEL: test_v4i32_post_reg_ld2lane: ;CHECK: ld2.s { v0, v1 }[0], [x0], x{{[0-9]+}} %ld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32> } %ld2 } @@ -2976,7 +2976,7 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld2lane(i32* %A, i32** %ptr ;CHECK-LABEL: test_v2i32_post_imm_ld2lane: ;CHECK: ld2.s { v0, v1 }[0], [x0], #8 %ld2 = call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i32 2 + %tmp = getelementptr i32, i32* %A, i32 2 store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32> } %ld2 } @@ -2985,7 +2985,7 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld2lane(i32* %A, i32** %ptr ;CHECK-LABEL: test_v2i32_post_reg_ld2lane: ;CHECK: ld2.s { v0, v1 }[0], [x0], x{{[0-9]+}} %ld2 = call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32> } %ld2 } @@ -2997,7 +2997,7 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld2lane(i64* %A, i64** %ptr ;CHECK-LABEL: test_v2i64_post_imm_ld2lane: ;CHECK: ld2.d { v0, v1 }[0], [x0], #16 %ld2 = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i32 2 + %tmp = getelementptr i64, i64* %A, i32 2 store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64> } %ld2 } @@ -3006,7 +3006,7 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld2lane(i64* %A, i64** %ptr ;CHECK-LABEL: test_v2i64_post_reg_ld2lane: ;CHECK: ld2.d { v0, v1 }[0], [x0], x{{[0-9]+}} %ld2 = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64> } %ld2 } @@ -3018,7 +3018,7 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld2lane(i64* %A, i64** %ptr ;CHECK-LABEL: test_v1i64_post_imm_ld2lane: ;CHECK: ld2.d { v0, v1 }[0], [x0], #16 %ld2 = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i32 2 + %tmp = getelementptr i64, i64* %A, i32 2 store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64> } %ld2 } @@ -3027,7 +3027,7 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld2lane(i64* %A, i64** %ptr ;CHECK-LABEL: test_v1i64_post_reg_ld2lane: ;CHECK: ld2.d { v0, v1 }[0], [x0], x{{[0-9]+}} %ld2 = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64> } %ld2 } @@ -3039,7 +3039,7 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld2lane(float* %A, floa ;CHECK-LABEL: test_v4f32_post_imm_ld2lane: ;CHECK: ld2.s { v0, v1 }[0], [x0], #8 %ld2 = call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, i64 0, float* %A) - %tmp = getelementptr float* %A, i32 2 + %tmp = getelementptr float, float* %A, i32 2 store float* %tmp, float** %ptr ret { <4 x float>, <4 x float> } %ld2 } @@ -3048,7 +3048,7 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_reg_ld2lane(float* %A, floa ;CHECK-LABEL: test_v4f32_post_reg_ld2lane: ;CHECK: ld2.s { v0, v1 }[0], [x0], x{{[0-9]+}} %ld2 = call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, i64 0, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <4 x float>, <4 x float> } %ld2 } @@ -3060,7 +3060,7 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld2lane(float* %A, floa ;CHECK-LABEL: test_v2f32_post_imm_ld2lane: ;CHECK: ld2.s { v0, v1 }[0], [x0], #8 %ld2 = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, i64 0, float* %A) - %tmp = getelementptr float* %A, i32 2 + %tmp = getelementptr float, float* %A, i32 2 store float* %tmp, float** %ptr ret { <2 x float>, <2 x float> } %ld2 } @@ -3069,7 +3069,7 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_reg_ld2lane(float* %A, floa ;CHECK-LABEL: test_v2f32_post_reg_ld2lane: ;CHECK: ld2.s { v0, v1 }[0], [x0], x{{[0-9]+}} %ld2 = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, i64 0, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <2 x float>, <2 x float> } %ld2 } @@ -3081,7 +3081,7 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld2lane(double* %A, d ;CHECK-LABEL: test_v2f64_post_imm_ld2lane: ;CHECK: ld2.d { v0, v1 }[0], [x0], #16 %ld2 = call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, i64 0, double* %A) - %tmp = getelementptr double* %A, i32 2 + %tmp = getelementptr double, double* %A, i32 2 store double* %tmp, double** %ptr ret { <2 x double>, <2 x double> } %ld2 } @@ -3090,7 +3090,7 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_reg_ld2lane(double* %A, d ;CHECK-LABEL: test_v2f64_post_reg_ld2lane: ;CHECK: ld2.d { v0, v1 }[0], [x0], x{{[0-9]+}} %ld2 = call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <2 x double>, <2 x double> } %ld2 } @@ -3102,7 +3102,7 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld2lane(double* %A, d ;CHECK-LABEL: test_v1f64_post_imm_ld2lane: ;CHECK: ld2.d { v0, v1 }[0], [x0], #16 %ld2 = call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, i64 0, double* %A) - %tmp = getelementptr double* %A, i32 2 + %tmp = getelementptr double, double* %A, i32 2 store double* %tmp, double** %ptr ret { <1 x double>, <1 x double> } %ld2 } @@ -3111,7 +3111,7 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_reg_ld2lane(double* %A, d ;CHECK-LABEL: test_v1f64_post_reg_ld2lane: ;CHECK: ld2.d { v0, v1 }[0], [x0], x{{[0-9]+}} %ld2 = call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <1 x double>, <1 x double> } %ld2 } @@ -3123,7 +3123,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld3lane(i8* %A, ;CHECK-LABEL: test_v16i8_post_imm_ld3lane: ;CHECK: ld3.b { v0, v1, v2 }[0], [x0], #3 %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i32 3 + %tmp = getelementptr i8, i8* %A, i32 3 store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3 } @@ -3132,7 +3132,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld3lane(i8* %A, ;CHECK-LABEL: test_v16i8_post_reg_ld3lane: ;CHECK: ld3.b { v0, v1, v2 }[0], [x0], x{{[0-9]+}} %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8>, <16 x i8> } %ld3 } @@ -3144,7 +3144,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld3lane(i8* %A, i8** ;CHECK-LABEL: test_v8i8_post_imm_ld3lane: ;CHECK: ld3.b { v0, v1, v2 }[0], [x0], #3 %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i32 3 + %tmp = getelementptr i8, i8* %A, i32 3 store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3 } @@ -3153,7 +3153,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld3lane(i8* %A, i8** ;CHECK-LABEL: test_v8i8_post_reg_ld3lane: ;CHECK: ld3.b { v0, v1, v2 }[0], [x0], x{{[0-9]+}} %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8>, <8 x i8> } %ld3 } @@ -3165,7 +3165,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld3lane(i16* %A, ;CHECK-LABEL: test_v8i16_post_imm_ld3lane: ;CHECK: ld3.h { v0, v1, v2 }[0], [x0], #6 %ld3 = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i32 3 + %tmp = getelementptr i16, i16* %A, i32 3 store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3 } @@ -3174,7 +3174,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld3lane(i16* %A, ;CHECK-LABEL: test_v8i16_post_reg_ld3lane: ;CHECK: ld3.h { v0, v1, v2 }[0], [x0], x{{[0-9]+}} %ld3 = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16>, <8 x i16> } %ld3 } @@ -3186,7 +3186,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld3lane(i16* %A, ;CHECK-LABEL: test_v4i16_post_imm_ld3lane: ;CHECK: ld3.h { v0, v1, v2 }[0], [x0], #6 %ld3 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i32 3 + %tmp = getelementptr i16, i16* %A, i32 3 store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3 } @@ -3195,7 +3195,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld3lane(i16* %A, ;CHECK-LABEL: test_v4i16_post_reg_ld3lane: ;CHECK: ld3.h { v0, v1, v2 }[0], [x0], x{{[0-9]+}} %ld3 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16>, <4 x i16> } %ld3 } @@ -3207,7 +3207,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld3lane(i32* %A, ;CHECK-LABEL: test_v4i32_post_imm_ld3lane: ;CHECK: ld3.s { v0, v1, v2 }[0], [x0], #12 %ld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i32 3 + %tmp = getelementptr i32, i32* %A, i32 3 store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3 } @@ -3216,7 +3216,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld3lane(i32* %A, ;CHECK-LABEL: test_v4i32_post_reg_ld3lane: ;CHECK: ld3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}} %ld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32>, <4 x i32> } %ld3 } @@ -3228,7 +3228,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld3lane(i32* %A, ;CHECK-LABEL: test_v2i32_post_imm_ld3lane: ;CHECK: ld3.s { v0, v1, v2 }[0], [x0], #12 %ld3 = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i32 3 + %tmp = getelementptr i32, i32* %A, i32 3 store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3 } @@ -3237,7 +3237,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld3lane(i32* %A, ;CHECK-LABEL: test_v2i32_post_reg_ld3lane: ;CHECK: ld3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}} %ld3 = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32>, <2 x i32> } %ld3 } @@ -3249,7 +3249,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld3lane(i64* %A, ;CHECK-LABEL: test_v2i64_post_imm_ld3lane: ;CHECK: ld3.d { v0, v1, v2 }[0], [x0], #24 %ld3 = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i32 3 + %tmp = getelementptr i64, i64* %A, i32 3 store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3 } @@ -3258,7 +3258,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld3lane(i64* %A, ;CHECK-LABEL: test_v2i64_post_reg_ld3lane: ;CHECK: ld3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}} %ld3 = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64>, <2 x i64> } %ld3 } @@ -3270,7 +3270,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld3lane(i64* %A, ;CHECK-LABEL: test_v1i64_post_imm_ld3lane: ;CHECK: ld3.d { v0, v1, v2 }[0], [x0], #24 %ld3 = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i32 3 + %tmp = getelementptr i64, i64* %A, i32 3 store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3 } @@ -3279,7 +3279,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld3lane(i64* %A, ;CHECK-LABEL: test_v1i64_post_reg_ld3lane: ;CHECK: ld3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}} %ld3 = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64>, <1 x i64> } %ld3 } @@ -3291,7 +3291,7 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld3lane(fl ;CHECK-LABEL: test_v4f32_post_imm_ld3lane: ;CHECK: ld3.s { v0, v1, v2 }[0], [x0], #12 %ld3 = call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, i64 0, float* %A) - %tmp = getelementptr float* %A, i32 3 + %tmp = getelementptr float, float* %A, i32 3 store float* %tmp, float** %ptr ret { <4 x float>, <4 x float>, <4 x float> } %ld3 } @@ -3300,7 +3300,7 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld3lane(fl ;CHECK-LABEL: test_v4f32_post_reg_ld3lane: ;CHECK: ld3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}} %ld3 = call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, i64 0, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <4 x float>, <4 x float>, <4 x float> } %ld3 } @@ -3312,7 +3312,7 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld3lane(fl ;CHECK-LABEL: test_v2f32_post_imm_ld3lane: ;CHECK: ld3.s { v0, v1, v2 }[0], [x0], #12 %ld3 = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, i64 0, float* %A) - %tmp = getelementptr float* %A, i32 3 + %tmp = getelementptr float, float* %A, i32 3 store float* %tmp, float** %ptr ret { <2 x float>, <2 x float>, <2 x float> } %ld3 } @@ -3321,7 +3321,7 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld3lane(fl ;CHECK-LABEL: test_v2f32_post_reg_ld3lane: ;CHECK: ld3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}} %ld3 = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, i64 0, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <2 x float>, <2 x float>, <2 x float> } %ld3 } @@ -3333,7 +3333,7 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld3lane ;CHECK-LABEL: test_v2f64_post_imm_ld3lane: ;CHECK: ld3.d { v0, v1, v2 }[0], [x0], #24 %ld3 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, i64 0, double* %A) - %tmp = getelementptr double* %A, i32 3 + %tmp = getelementptr double, double* %A, i32 3 store double* %tmp, double** %ptr ret { <2 x double>, <2 x double>, <2 x double> } %ld3 } @@ -3342,7 +3342,7 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld3lane ;CHECK-LABEL: test_v2f64_post_reg_ld3lane: ;CHECK: ld3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}} %ld3 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <2 x double>, <2 x double>, <2 x double> } %ld3 } @@ -3354,7 +3354,7 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld3lane ;CHECK-LABEL: test_v1f64_post_imm_ld3lane: ;CHECK: ld3.d { v0, v1, v2 }[0], [x0], #24 %ld3 = call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, i64 0, double* %A) - %tmp = getelementptr double* %A, i32 3 + %tmp = getelementptr double, double* %A, i32 3 store double* %tmp, double** %ptr ret { <1 x double>, <1 x double>, <1 x double> } %ld3 } @@ -3363,7 +3363,7 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld3lane ;CHECK-LABEL: test_v1f64_post_reg_ld3lane: ;CHECK: ld3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}} %ld3 = call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <1 x double>, <1 x double>, <1 x double> } %ld3 } @@ -3375,7 +3375,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld4la ;CHECK-LABEL: test_v16i8_post_imm_ld4lane: ;CHECK: ld4.b { v0, v1, v2, v3 }[0], [x0], #4 %ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i32 4 + %tmp = getelementptr i8, i8* %A, i32 4 store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4 } @@ -3384,7 +3384,7 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld4la ;CHECK-LABEL: test_v16i8_post_reg_ld4lane: ;CHECK: ld4.b { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} %ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %ld4 } @@ -3396,7 +3396,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld4lane(i8 ;CHECK-LABEL: test_v8i8_post_imm_ld4lane: ;CHECK: ld4.b { v0, v1, v2, v3 }[0], [x0], #4 %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i32 4 + %tmp = getelementptr i8, i8* %A, i32 4 store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4 } @@ -3405,7 +3405,7 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld4lane(i8 ;CHECK-LABEL: test_v8i8_post_reg_ld4lane: ;CHECK: ld4.b { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc store i8* %tmp, i8** %ptr ret { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %ld4 } @@ -3417,7 +3417,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld4la ;CHECK-LABEL: test_v8i16_post_imm_ld4lane: ;CHECK: ld4.h { v0, v1, v2, v3 }[0], [x0], #8 %ld4 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i32 4 + %tmp = getelementptr i16, i16* %A, i32 4 store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4 } @@ -3426,7 +3426,7 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld4la ;CHECK-LABEL: test_v8i16_post_reg_ld4lane: ;CHECK: ld4.h { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} %ld4 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } %ld4 } @@ -3438,7 +3438,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld4la ;CHECK-LABEL: test_v4i16_post_imm_ld4lane: ;CHECK: ld4.h { v0, v1, v2, v3 }[0], [x0], #8 %ld4 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i32 4 + %tmp = getelementptr i16, i16* %A, i32 4 store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4 } @@ -3447,7 +3447,7 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld4la ;CHECK-LABEL: test_v4i16_post_reg_ld4lane: ;CHECK: ld4.h { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} %ld4 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc store i16* %tmp, i16** %ptr ret { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } %ld4 } @@ -3459,7 +3459,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld4la ;CHECK-LABEL: test_v4i32_post_imm_ld4lane: ;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], #16 %ld4 = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i32 4 + %tmp = getelementptr i32, i32* %A, i32 4 store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4 } @@ -3468,7 +3468,7 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld4la ;CHECK-LABEL: test_v4i32_post_reg_ld4lane: ;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} %ld4 = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %ld4 } @@ -3480,7 +3480,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld4la ;CHECK-LABEL: test_v2i32_post_imm_ld4lane: ;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], #16 %ld4 = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i32 4 + %tmp = getelementptr i32, i32* %A, i32 4 store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4 } @@ -3489,7 +3489,7 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld4la ;CHECK-LABEL: test_v2i32_post_reg_ld4lane: ;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} %ld4 = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc store i32* %tmp, i32** %ptr ret { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } %ld4 } @@ -3501,7 +3501,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld4la ;CHECK-LABEL: test_v2i64_post_imm_ld4lane: ;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], #32 %ld4 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i32 4 + %tmp = getelementptr i64, i64* %A, i32 4 store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4 } @@ -3510,7 +3510,7 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld4la ;CHECK-LABEL: test_v2i64_post_reg_ld4lane: ;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} %ld4 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } %ld4 } @@ -3522,7 +3522,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld4la ;CHECK-LABEL: test_v1i64_post_imm_ld4lane: ;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], #32 %ld4 = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i32 4 + %tmp = getelementptr i64, i64* %A, i32 4 store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4 } @@ -3531,7 +3531,7 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld4la ;CHECK-LABEL: test_v1i64_post_reg_ld4lane: ;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} %ld4 = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc store i64* %tmp, i64** %ptr ret { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } %ld4 } @@ -3543,7 +3543,7 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_i ;CHECK-LABEL: test_v4f32_post_imm_ld4lane: ;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], #16 %ld4 = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 0, float* %A) - %tmp = getelementptr float* %A, i32 4 + %tmp = getelementptr float, float* %A, i32 4 store float* %tmp, float** %ptr ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4 } @@ -3552,7 +3552,7 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_r ;CHECK-LABEL: test_v4f32_post_reg_ld4lane: ;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} %ld4 = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 0, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <4 x float>, <4 x float>, <4 x float>, <4 x float> } %ld4 } @@ -3564,7 +3564,7 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_i ;CHECK-LABEL: test_v2f32_post_imm_ld4lane: ;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], #16 %ld4 = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 0, float* %A) - %tmp = getelementptr float* %A, i32 4 + %tmp = getelementptr float, float* %A, i32 4 store float* %tmp, float** %ptr ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4 } @@ -3573,7 +3573,7 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_r ;CHECK-LABEL: test_v2f32_post_reg_ld4lane: ;CHECK: ld4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} %ld4 = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 0, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc store float* %tmp, float** %ptr ret { <2 x float>, <2 x float>, <2 x float>, <2 x float> } %ld4 } @@ -3585,7 +3585,7 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po ;CHECK-LABEL: test_v2f64_post_imm_ld4lane: ;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], #32 %ld4 = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 0, double* %A) - %tmp = getelementptr double* %A, i32 4 + %tmp = getelementptr double, double* %A, i32 4 store double* %tmp, double** %ptr ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4 } @@ -3594,7 +3594,7 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po ;CHECK-LABEL: test_v2f64_post_reg_ld4lane: ;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} %ld4 = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <2 x double>, <2 x double>, <2 x double>, <2 x double> } %ld4 } @@ -3606,7 +3606,7 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po ;CHECK-LABEL: test_v1f64_post_imm_ld4lane: ;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], #32 %ld4 = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 0, double* %A) - %tmp = getelementptr double* %A, i32 4 + %tmp = getelementptr double, double* %A, i32 4 store double* %tmp, double** %ptr ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4 } @@ -3615,7 +3615,7 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po ;CHECK-LABEL: test_v1f64_post_reg_ld4lane: ;CHECK: ld4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} %ld4 = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc store double* %tmp, double** %ptr ret { <1 x double>, <1 x double>, <1 x double>, <1 x double> } %ld4 } @@ -3627,7 +3627,7 @@ define i8* @test_v16i8_post_imm_st2(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> % ;CHECK-LABEL: test_v16i8_post_imm_st2: ;CHECK: st2.16b { v0, v1 }, [x0], #32 call void @llvm.aarch64.neon.st2.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i8* %A) - %tmp = getelementptr i8* %A, i32 32 + %tmp = getelementptr i8, i8* %A, i32 32 ret i8* %tmp } @@ -3635,7 +3635,7 @@ define i8* @test_v16i8_post_reg_st2(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> % ;CHECK-LABEL: test_v16i8_post_reg_st2: ;CHECK: st2.16b { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -3646,7 +3646,7 @@ define i8* @test_v8i8_post_imm_st2(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C) ;CHECK-LABEL: test_v8i8_post_imm_st2: ;CHECK: st2.8b { v0, v1 }, [x0], #16 call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i8* %A) - %tmp = getelementptr i8* %A, i32 16 + %tmp = getelementptr i8, i8* %A, i32 16 ret i8* %tmp } @@ -3654,7 +3654,7 @@ define i8* @test_v8i8_post_reg_st2(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, ;CHECK-LABEL: test_v8i8_post_reg_st2: ;CHECK: st2.8b { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -3665,7 +3665,7 @@ define i16* @test_v8i16_post_imm_st2(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16 ;CHECK-LABEL: test_v8i16_post_imm_st2: ;CHECK: st2.8h { v0, v1 }, [x0], #32 call void @llvm.aarch64.neon.st2.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i16* %A) - %tmp = getelementptr i16* %A, i32 16 + %tmp = getelementptr i16, i16* %A, i32 16 ret i16* %tmp } @@ -3673,7 +3673,7 @@ define i16* @test_v8i16_post_reg_st2(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16 ;CHECK-LABEL: test_v8i16_post_reg_st2: ;CHECK: st2.8h { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -3684,7 +3684,7 @@ define i16* @test_v4i16_post_imm_st2(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16 ;CHECK-LABEL: test_v4i16_post_imm_st2: ;CHECK: st2.4h { v0, v1 }, [x0], #16 call void @llvm.aarch64.neon.st2.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i16* %A) - %tmp = getelementptr i16* %A, i32 8 + %tmp = getelementptr i16, i16* %A, i32 8 ret i16* %tmp } @@ -3692,7 +3692,7 @@ define i16* @test_v4i16_post_reg_st2(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16 ;CHECK-LABEL: test_v4i16_post_reg_st2: ;CHECK: st2.4h { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -3703,7 +3703,7 @@ define i32* @test_v4i32_post_imm_st2(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32 ;CHECK-LABEL: test_v4i32_post_imm_st2: ;CHECK: st2.4s { v0, v1 }, [x0], #32 call void @llvm.aarch64.neon.st2.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i32* %A) - %tmp = getelementptr i32* %A, i32 8 + %tmp = getelementptr i32, i32* %A, i32 8 ret i32* %tmp } @@ -3711,7 +3711,7 @@ define i32* @test_v4i32_post_reg_st2(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32 ;CHECK-LABEL: test_v4i32_post_reg_st2: ;CHECK: st2.4s { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -3722,7 +3722,7 @@ define i32* @test_v2i32_post_imm_st2(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32 ;CHECK-LABEL: test_v2i32_post_imm_st2: ;CHECK: st2.2s { v0, v1 }, [x0], #16 call void @llvm.aarch64.neon.st2.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i32* %A) - %tmp = getelementptr i32* %A, i32 4 + %tmp = getelementptr i32, i32* %A, i32 4 ret i32* %tmp } @@ -3730,7 +3730,7 @@ define i32* @test_v2i32_post_reg_st2(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32 ;CHECK-LABEL: test_v2i32_post_reg_st2: ;CHECK: st2.2s { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -3741,7 +3741,7 @@ define i64* @test_v2i64_post_imm_st2(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64 ;CHECK-LABEL: test_v2i64_post_imm_st2: ;CHECK: st2.2d { v0, v1 }, [x0], #32 call void @llvm.aarch64.neon.st2.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64* %A) - %tmp = getelementptr i64* %A, i64 4 + %tmp = getelementptr i64, i64* %A, i64 4 ret i64* %tmp } @@ -3749,7 +3749,7 @@ define i64* @test_v2i64_post_reg_st2(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64 ;CHECK-LABEL: test_v2i64_post_reg_st2: ;CHECK: st2.2d { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -3760,7 +3760,7 @@ define i64* @test_v1i64_post_imm_st2(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64 ;CHECK-LABEL: test_v1i64_post_imm_st2: ;CHECK: st1.1d { v0, v1 }, [x0], #16 call void @llvm.aarch64.neon.st2.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64* %A) - %tmp = getelementptr i64* %A, i64 2 + %tmp = getelementptr i64, i64* %A, i64 2 ret i64* %tmp } @@ -3768,7 +3768,7 @@ define i64* @test_v1i64_post_reg_st2(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64 ;CHECK-LABEL: test_v1i64_post_reg_st2: ;CHECK: st1.1d { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -3779,7 +3779,7 @@ define float* @test_v4f32_post_imm_st2(float* %A, float** %ptr, <4 x float> %B, ;CHECK-LABEL: test_v4f32_post_imm_st2: ;CHECK: st2.4s { v0, v1 }, [x0], #32 call void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float> %B, <4 x float> %C, float* %A) - %tmp = getelementptr float* %A, i32 8 + %tmp = getelementptr float, float* %A, i32 8 ret float* %tmp } @@ -3787,7 +3787,7 @@ define float* @test_v4f32_post_reg_st2(float* %A, float** %ptr, <4 x float> %B, ;CHECK-LABEL: test_v4f32_post_reg_st2: ;CHECK: st2.4s { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float> %B, <4 x float> %C, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -3798,7 +3798,7 @@ define float* @test_v2f32_post_imm_st2(float* %A, float** %ptr, <2 x float> %B, ;CHECK-LABEL: test_v2f32_post_imm_st2: ;CHECK: st2.2s { v0, v1 }, [x0], #16 call void @llvm.aarch64.neon.st2.v2f32.p0f32(<2 x float> %B, <2 x float> %C, float* %A) - %tmp = getelementptr float* %A, i32 4 + %tmp = getelementptr float, float* %A, i32 4 ret float* %tmp } @@ -3806,7 +3806,7 @@ define float* @test_v2f32_post_reg_st2(float* %A, float** %ptr, <2 x float> %B, ;CHECK-LABEL: test_v2f32_post_reg_st2: ;CHECK: st2.2s { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2.v2f32.p0f32(<2 x float> %B, <2 x float> %C, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -3817,7 +3817,7 @@ define double* @test_v2f64_post_imm_st2(double* %A, double** %ptr, <2 x double> ;CHECK-LABEL: test_v2f64_post_imm_st2: ;CHECK: st2.2d { v0, v1 }, [x0], #32 call void @llvm.aarch64.neon.st2.v2f64.p0f64(<2 x double> %B, <2 x double> %C, double* %A) - %tmp = getelementptr double* %A, i64 4 + %tmp = getelementptr double, double* %A, i64 4 ret double* %tmp } @@ -3825,7 +3825,7 @@ define double* @test_v2f64_post_reg_st2(double* %A, double** %ptr, <2 x double> ;CHECK-LABEL: test_v2f64_post_reg_st2: ;CHECK: st2.2d { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2.v2f64.p0f64(<2 x double> %B, <2 x double> %C, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -3836,7 +3836,7 @@ define double* @test_v1f64_post_imm_st2(double* %A, double** %ptr, <1 x double> ;CHECK-LABEL: test_v1f64_post_imm_st2: ;CHECK: st1.1d { v0, v1 }, [x0], #16 call void @llvm.aarch64.neon.st2.v1f64.p0f64(<1 x double> %B, <1 x double> %C, double* %A) - %tmp = getelementptr double* %A, i64 2 + %tmp = getelementptr double, double* %A, i64 2 ret double* %tmp } @@ -3844,7 +3844,7 @@ define double* @test_v1f64_post_reg_st2(double* %A, double** %ptr, <1 x double> ;CHECK-LABEL: test_v1f64_post_reg_st2: ;CHECK: st1.1d { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2.v1f64.p0f64(<1 x double> %B, <1 x double> %C, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -3855,7 +3855,7 @@ define i8* @test_v16i8_post_imm_st3(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> % ;CHECK-LABEL: test_v16i8_post_imm_st3: ;CHECK: st3.16b { v0, v1, v2 }, [x0], #48 call void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %A) - %tmp = getelementptr i8* %A, i32 48 + %tmp = getelementptr i8, i8* %A, i32 48 ret i8* %tmp } @@ -3863,7 +3863,7 @@ define i8* @test_v16i8_post_reg_st3(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> % ;CHECK-LABEL: test_v16i8_post_reg_st3: ;CHECK: st3.16b { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -3874,7 +3874,7 @@ define i8* @test_v8i8_post_imm_st3(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, ;CHECK-LABEL: test_v8i8_post_imm_st3: ;CHECK: st3.8b { v0, v1, v2 }, [x0], #24 call void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %A) - %tmp = getelementptr i8* %A, i32 24 + %tmp = getelementptr i8, i8* %A, i32 24 ret i8* %tmp } @@ -3882,7 +3882,7 @@ define i8* @test_v8i8_post_reg_st3(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, ;CHECK-LABEL: test_v8i8_post_reg_st3: ;CHECK: st3.8b { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -3893,7 +3893,7 @@ define i16* @test_v8i16_post_imm_st3(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16 ;CHECK-LABEL: test_v8i16_post_imm_st3: ;CHECK: st3.8h { v0, v1, v2 }, [x0], #48 call void @llvm.aarch64.neon.st3.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %A) - %tmp = getelementptr i16* %A, i32 24 + %tmp = getelementptr i16, i16* %A, i32 24 ret i16* %tmp } @@ -3901,7 +3901,7 @@ define i16* @test_v8i16_post_reg_st3(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16 ;CHECK-LABEL: test_v8i16_post_reg_st3: ;CHECK: st3.8h { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -3912,7 +3912,7 @@ define i16* @test_v4i16_post_imm_st3(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16 ;CHECK-LABEL: test_v4i16_post_imm_st3: ;CHECK: st3.4h { v0, v1, v2 }, [x0], #24 call void @llvm.aarch64.neon.st3.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %A) - %tmp = getelementptr i16* %A, i32 12 + %tmp = getelementptr i16, i16* %A, i32 12 ret i16* %tmp } @@ -3920,7 +3920,7 @@ define i16* @test_v4i16_post_reg_st3(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16 ;CHECK-LABEL: test_v4i16_post_reg_st3: ;CHECK: st3.4h { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -3931,7 +3931,7 @@ define i32* @test_v4i32_post_imm_st3(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32 ;CHECK-LABEL: test_v4i32_post_imm_st3: ;CHECK: st3.4s { v0, v1, v2 }, [x0], #48 call void @llvm.aarch64.neon.st3.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %A) - %tmp = getelementptr i32* %A, i32 12 + %tmp = getelementptr i32, i32* %A, i32 12 ret i32* %tmp } @@ -3939,7 +3939,7 @@ define i32* @test_v4i32_post_reg_st3(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32 ;CHECK-LABEL: test_v4i32_post_reg_st3: ;CHECK: st3.4s { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -3950,7 +3950,7 @@ define i32* @test_v2i32_post_imm_st3(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32 ;CHECK-LABEL: test_v2i32_post_imm_st3: ;CHECK: st3.2s { v0, v1, v2 }, [x0], #24 call void @llvm.aarch64.neon.st3.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %A) - %tmp = getelementptr i32* %A, i32 6 + %tmp = getelementptr i32, i32* %A, i32 6 ret i32* %tmp } @@ -3958,7 +3958,7 @@ define i32* @test_v2i32_post_reg_st3(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32 ;CHECK-LABEL: test_v2i32_post_reg_st3: ;CHECK: st3.2s { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -3969,7 +3969,7 @@ define i64* @test_v2i64_post_imm_st3(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64 ;CHECK-LABEL: test_v2i64_post_imm_st3: ;CHECK: st3.2d { v0, v1, v2 }, [x0], #48 call void @llvm.aarch64.neon.st3.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %A) - %tmp = getelementptr i64* %A, i64 6 + %tmp = getelementptr i64, i64* %A, i64 6 ret i64* %tmp } @@ -3977,7 +3977,7 @@ define i64* @test_v2i64_post_reg_st3(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64 ;CHECK-LABEL: test_v2i64_post_reg_st3: ;CHECK: st3.2d { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -3988,7 +3988,7 @@ define i64* @test_v1i64_post_imm_st3(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64 ;CHECK-LABEL: test_v1i64_post_imm_st3: ;CHECK: st1.1d { v0, v1, v2 }, [x0], #24 call void @llvm.aarch64.neon.st3.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %A) - %tmp = getelementptr i64* %A, i64 3 + %tmp = getelementptr i64, i64* %A, i64 3 ret i64* %tmp } @@ -3996,7 +3996,7 @@ define i64* @test_v1i64_post_reg_st3(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64 ;CHECK-LABEL: test_v1i64_post_reg_st3: ;CHECK: st1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -4007,7 +4007,7 @@ define float* @test_v4f32_post_imm_st3(float* %A, float** %ptr, <4 x float> %B, ;CHECK-LABEL: test_v4f32_post_imm_st3: ;CHECK: st3.4s { v0, v1, v2 }, [x0], #48 call void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, float* %A) - %tmp = getelementptr float* %A, i32 12 + %tmp = getelementptr float, float* %A, i32 12 ret float* %tmp } @@ -4015,7 +4015,7 @@ define float* @test_v4f32_post_reg_st3(float* %A, float** %ptr, <4 x float> %B, ;CHECK-LABEL: test_v4f32_post_reg_st3: ;CHECK: st3.4s { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -4026,7 +4026,7 @@ define float* @test_v2f32_post_imm_st3(float* %A, float** %ptr, <2 x float> %B, ;CHECK-LABEL: test_v2f32_post_imm_st3: ;CHECK: st3.2s { v0, v1, v2 }, [x0], #24 call void @llvm.aarch64.neon.st3.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, float* %A) - %tmp = getelementptr float* %A, i32 6 + %tmp = getelementptr float, float* %A, i32 6 ret float* %tmp } @@ -4034,7 +4034,7 @@ define float* @test_v2f32_post_reg_st3(float* %A, float** %ptr, <2 x float> %B, ;CHECK-LABEL: test_v2f32_post_reg_st3: ;CHECK: st3.2s { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -4045,7 +4045,7 @@ define double* @test_v2f64_post_imm_st3(double* %A, double** %ptr, <2 x double> ;CHECK-LABEL: test_v2f64_post_imm_st3: ;CHECK: st3.2d { v0, v1, v2 }, [x0], #48 call void @llvm.aarch64.neon.st3.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, double* %A) - %tmp = getelementptr double* %A, i64 6 + %tmp = getelementptr double, double* %A, i64 6 ret double* %tmp } @@ -4053,7 +4053,7 @@ define double* @test_v2f64_post_reg_st3(double* %A, double** %ptr, <2 x double> ;CHECK-LABEL: test_v2f64_post_reg_st3: ;CHECK: st3.2d { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -4064,7 +4064,7 @@ define double* @test_v1f64_post_imm_st3(double* %A, double** %ptr, <1 x double> ;CHECK-LABEL: test_v1f64_post_imm_st3: ;CHECK: st1.1d { v0, v1, v2 }, [x0], #24 call void @llvm.aarch64.neon.st3.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, double* %A) - %tmp = getelementptr double* %A, i64 3 + %tmp = getelementptr double, double* %A, i64 3 ret double* %tmp } @@ -4072,7 +4072,7 @@ define double* @test_v1f64_post_reg_st3(double* %A, double** %ptr, <1 x double> ;CHECK-LABEL: test_v1f64_post_reg_st3: ;CHECK: st1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -4083,7 +4083,7 @@ define i8* @test_v16i8_post_imm_st4(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> % ;CHECK-LABEL: test_v16i8_post_imm_st4: ;CHECK: st4.16b { v0, v1, v2, v3 }, [x0], #64 call void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i8* %A) - %tmp = getelementptr i8* %A, i32 64 + %tmp = getelementptr i8, i8* %A, i32 64 ret i8* %tmp } @@ -4091,7 +4091,7 @@ define i8* @test_v16i8_post_reg_st4(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> % ;CHECK-LABEL: test_v16i8_post_reg_st4: ;CHECK: st4.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -4102,7 +4102,7 @@ define i8* @test_v8i8_post_imm_st4(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, ;CHECK-LABEL: test_v8i8_post_imm_st4: ;CHECK: st4.8b { v0, v1, v2, v3 }, [x0], #32 call void @llvm.aarch64.neon.st4.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i8* %A) - %tmp = getelementptr i8* %A, i32 32 + %tmp = getelementptr i8, i8* %A, i32 32 ret i8* %tmp } @@ -4110,7 +4110,7 @@ define i8* @test_v8i8_post_reg_st4(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C, ;CHECK-LABEL: test_v8i8_post_reg_st4: ;CHECK: st4.8b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -4121,7 +4121,7 @@ define i16* @test_v8i16_post_imm_st4(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16 ;CHECK-LABEL: test_v8i16_post_imm_st4: ;CHECK: st4.8h { v0, v1, v2, v3 }, [x0], #64 call void @llvm.aarch64.neon.st4.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i16* %A) - %tmp = getelementptr i16* %A, i32 32 + %tmp = getelementptr i16, i16* %A, i32 32 ret i16* %tmp } @@ -4129,7 +4129,7 @@ define i16* @test_v8i16_post_reg_st4(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i16 ;CHECK-LABEL: test_v8i16_post_reg_st4: ;CHECK: st4.8h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -4140,7 +4140,7 @@ define i16* @test_v4i16_post_imm_st4(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16 ;CHECK-LABEL: test_v4i16_post_imm_st4: ;CHECK: st4.4h { v0, v1, v2, v3 }, [x0], #32 call void @llvm.aarch64.neon.st4.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i16* %A) - %tmp = getelementptr i16* %A, i32 16 + %tmp = getelementptr i16, i16* %A, i32 16 ret i16* %tmp } @@ -4148,7 +4148,7 @@ define i16* @test_v4i16_post_reg_st4(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i16 ;CHECK-LABEL: test_v4i16_post_reg_st4: ;CHECK: st4.4h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -4159,7 +4159,7 @@ define i32* @test_v4i32_post_imm_st4(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32 ;CHECK-LABEL: test_v4i32_post_imm_st4: ;CHECK: st4.4s { v0, v1, v2, v3 }, [x0], #64 call void @llvm.aarch64.neon.st4.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i32* %A) - %tmp = getelementptr i32* %A, i32 16 + %tmp = getelementptr i32, i32* %A, i32 16 ret i32* %tmp } @@ -4167,7 +4167,7 @@ define i32* @test_v4i32_post_reg_st4(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i32 ;CHECK-LABEL: test_v4i32_post_reg_st4: ;CHECK: st4.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -4178,7 +4178,7 @@ define i32* @test_v2i32_post_imm_st4(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32 ;CHECK-LABEL: test_v2i32_post_imm_st4: ;CHECK: st4.2s { v0, v1, v2, v3 }, [x0], #32 call void @llvm.aarch64.neon.st4.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i32* %A) - %tmp = getelementptr i32* %A, i32 8 + %tmp = getelementptr i32, i32* %A, i32 8 ret i32* %tmp } @@ -4186,7 +4186,7 @@ define i32* @test_v2i32_post_reg_st4(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i32 ;CHECK-LABEL: test_v2i32_post_reg_st4: ;CHECK: st4.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -4197,7 +4197,7 @@ define i64* @test_v2i64_post_imm_st4(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64 ;CHECK-LABEL: test_v2i64_post_imm_st4: ;CHECK: st4.2d { v0, v1, v2, v3 }, [x0], #64 call void @llvm.aarch64.neon.st4.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64* %A) - %tmp = getelementptr i64* %A, i64 8 + %tmp = getelementptr i64, i64* %A, i64 8 ret i64* %tmp } @@ -4205,7 +4205,7 @@ define i64* @test_v2i64_post_reg_st4(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i64 ;CHECK-LABEL: test_v2i64_post_reg_st4: ;CHECK: st4.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -4216,7 +4216,7 @@ define i64* @test_v1i64_post_imm_st4(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64 ;CHECK-LABEL: test_v1i64_post_imm_st4: ;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], #32 call void @llvm.aarch64.neon.st4.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64* %A) - %tmp = getelementptr i64* %A, i64 4 + %tmp = getelementptr i64, i64* %A, i64 4 ret i64* %tmp } @@ -4224,7 +4224,7 @@ define i64* @test_v1i64_post_reg_st4(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i64 ;CHECK-LABEL: test_v1i64_post_reg_st4: ;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -4235,7 +4235,7 @@ define float* @test_v4f32_post_imm_st4(float* %A, float** %ptr, <4 x float> %B, ;CHECK-LABEL: test_v4f32_post_imm_st4: ;CHECK: st4.4s { v0, v1, v2, v3 }, [x0], #64 call void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, float* %A) - %tmp = getelementptr float* %A, i32 16 + %tmp = getelementptr float, float* %A, i32 16 ret float* %tmp } @@ -4243,7 +4243,7 @@ define float* @test_v4f32_post_reg_st4(float* %A, float** %ptr, <4 x float> %B, ;CHECK-LABEL: test_v4f32_post_reg_st4: ;CHECK: st4.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -4254,7 +4254,7 @@ define float* @test_v2f32_post_imm_st4(float* %A, float** %ptr, <2 x float> %B, ;CHECK-LABEL: test_v2f32_post_imm_st4: ;CHECK: st4.2s { v0, v1, v2, v3 }, [x0], #32 call void @llvm.aarch64.neon.st4.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, float* %A) - %tmp = getelementptr float* %A, i32 8 + %tmp = getelementptr float, float* %A, i32 8 ret float* %tmp } @@ -4262,7 +4262,7 @@ define float* @test_v2f32_post_reg_st4(float* %A, float** %ptr, <2 x float> %B, ;CHECK-LABEL: test_v2f32_post_reg_st4: ;CHECK: st4.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -4273,7 +4273,7 @@ define double* @test_v2f64_post_imm_st4(double* %A, double** %ptr, <2 x double> ;CHECK-LABEL: test_v2f64_post_imm_st4: ;CHECK: st4.2d { v0, v1, v2, v3 }, [x0], #64 call void @llvm.aarch64.neon.st4.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, double* %A) - %tmp = getelementptr double* %A, i64 8 + %tmp = getelementptr double, double* %A, i64 8 ret double* %tmp } @@ -4281,7 +4281,7 @@ define double* @test_v2f64_post_reg_st4(double* %A, double** %ptr, <2 x double> ;CHECK-LABEL: test_v2f64_post_reg_st4: ;CHECK: st4.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -4292,7 +4292,7 @@ define double* @test_v1f64_post_imm_st4(double* %A, double** %ptr, <1 x double> ;CHECK-LABEL: test_v1f64_post_imm_st4: ;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], #32 call void @llvm.aarch64.neon.st4.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, double* %A) - %tmp = getelementptr double* %A, i64 4 + %tmp = getelementptr double, double* %A, i64 4 ret double* %tmp } @@ -4300,7 +4300,7 @@ define double* @test_v1f64_post_reg_st4(double* %A, double** %ptr, <1 x double> ;CHECK-LABEL: test_v1f64_post_reg_st4: ;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -4311,7 +4311,7 @@ define i8* @test_v16i8_post_imm_st1x2(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> ;CHECK-LABEL: test_v16i8_post_imm_st1x2: ;CHECK: st1.16b { v0, v1 }, [x0], #32 call void @llvm.aarch64.neon.st1x2.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i8* %A) - %tmp = getelementptr i8* %A, i32 32 + %tmp = getelementptr i8, i8* %A, i32 32 ret i8* %tmp } @@ -4319,7 +4319,7 @@ define i8* @test_v16i8_post_reg_st1x2(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> ;CHECK-LABEL: test_v16i8_post_reg_st1x2: ;CHECK: st1.16b { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x2.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -4330,7 +4330,7 @@ define i8* @test_v8i8_post_imm_st1x2(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C ;CHECK-LABEL: test_v8i8_post_imm_st1x2: ;CHECK: st1.8b { v0, v1 }, [x0], #16 call void @llvm.aarch64.neon.st1x2.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i8* %A) - %tmp = getelementptr i8* %A, i32 16 + %tmp = getelementptr i8, i8* %A, i32 16 ret i8* %tmp } @@ -4338,7 +4338,7 @@ define i8* @test_v8i8_post_reg_st1x2(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C ;CHECK-LABEL: test_v8i8_post_reg_st1x2: ;CHECK: st1.8b { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x2.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -4349,7 +4349,7 @@ define i16* @test_v8i16_post_imm_st1x2(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i ;CHECK-LABEL: test_v8i16_post_imm_st1x2: ;CHECK: st1.8h { v0, v1 }, [x0], #32 call void @llvm.aarch64.neon.st1x2.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i16* %A) - %tmp = getelementptr i16* %A, i32 16 + %tmp = getelementptr i16, i16* %A, i32 16 ret i16* %tmp } @@ -4357,7 +4357,7 @@ define i16* @test_v8i16_post_reg_st1x2(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i ;CHECK-LABEL: test_v8i16_post_reg_st1x2: ;CHECK: st1.8h { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x2.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -4368,7 +4368,7 @@ define i16* @test_v4i16_post_imm_st1x2(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i ;CHECK-LABEL: test_v4i16_post_imm_st1x2: ;CHECK: st1.4h { v0, v1 }, [x0], #16 call void @llvm.aarch64.neon.st1x2.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i16* %A) - %tmp = getelementptr i16* %A, i32 8 + %tmp = getelementptr i16, i16* %A, i32 8 ret i16* %tmp } @@ -4376,7 +4376,7 @@ define i16* @test_v4i16_post_reg_st1x2(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i ;CHECK-LABEL: test_v4i16_post_reg_st1x2: ;CHECK: st1.4h { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x2.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -4387,7 +4387,7 @@ define i32* @test_v4i32_post_imm_st1x2(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i ;CHECK-LABEL: test_v4i32_post_imm_st1x2: ;CHECK: st1.4s { v0, v1 }, [x0], #32 call void @llvm.aarch64.neon.st1x2.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i32* %A) - %tmp = getelementptr i32* %A, i32 8 + %tmp = getelementptr i32, i32* %A, i32 8 ret i32* %tmp } @@ -4395,7 +4395,7 @@ define i32* @test_v4i32_post_reg_st1x2(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i ;CHECK-LABEL: test_v4i32_post_reg_st1x2: ;CHECK: st1.4s { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x2.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -4406,7 +4406,7 @@ define i32* @test_v2i32_post_imm_st1x2(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i ;CHECK-LABEL: test_v2i32_post_imm_st1x2: ;CHECK: st1.2s { v0, v1 }, [x0], #16 call void @llvm.aarch64.neon.st1x2.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i32* %A) - %tmp = getelementptr i32* %A, i32 4 + %tmp = getelementptr i32, i32* %A, i32 4 ret i32* %tmp } @@ -4414,7 +4414,7 @@ define i32* @test_v2i32_post_reg_st1x2(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i ;CHECK-LABEL: test_v2i32_post_reg_st1x2: ;CHECK: st1.2s { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x2.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -4425,7 +4425,7 @@ define i64* @test_v2i64_post_imm_st1x2(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i ;CHECK-LABEL: test_v2i64_post_imm_st1x2: ;CHECK: st1.2d { v0, v1 }, [x0], #32 call void @llvm.aarch64.neon.st1x2.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64* %A) - %tmp = getelementptr i64* %A, i64 4 + %tmp = getelementptr i64, i64* %A, i64 4 ret i64* %tmp } @@ -4433,7 +4433,7 @@ define i64* @test_v2i64_post_reg_st1x2(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i ;CHECK-LABEL: test_v2i64_post_reg_st1x2: ;CHECK: st1.2d { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x2.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -4444,7 +4444,7 @@ define i64* @test_v1i64_post_imm_st1x2(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i ;CHECK-LABEL: test_v1i64_post_imm_st1x2: ;CHECK: st1.1d { v0, v1 }, [x0], #16 call void @llvm.aarch64.neon.st1x2.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64* %A) - %tmp = getelementptr i64* %A, i64 2 + %tmp = getelementptr i64, i64* %A, i64 2 ret i64* %tmp } @@ -4452,7 +4452,7 @@ define i64* @test_v1i64_post_reg_st1x2(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i ;CHECK-LABEL: test_v1i64_post_reg_st1x2: ;CHECK: st1.1d { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x2.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -4463,7 +4463,7 @@ define float* @test_v4f32_post_imm_st1x2(float* %A, float** %ptr, <4 x float> %B ;CHECK-LABEL: test_v4f32_post_imm_st1x2: ;CHECK: st1.4s { v0, v1 }, [x0], #32 call void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float> %B, <4 x float> %C, float* %A) - %tmp = getelementptr float* %A, i32 8 + %tmp = getelementptr float, float* %A, i32 8 ret float* %tmp } @@ -4471,7 +4471,7 @@ define float* @test_v4f32_post_reg_st1x2(float* %A, float** %ptr, <4 x float> %B ;CHECK-LABEL: test_v4f32_post_reg_st1x2: ;CHECK: st1.4s { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float> %B, <4 x float> %C, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -4482,7 +4482,7 @@ define float* @test_v2f32_post_imm_st1x2(float* %A, float** %ptr, <2 x float> %B ;CHECK-LABEL: test_v2f32_post_imm_st1x2: ;CHECK: st1.2s { v0, v1 }, [x0], #16 call void @llvm.aarch64.neon.st1x2.v2f32.p0f32(<2 x float> %B, <2 x float> %C, float* %A) - %tmp = getelementptr float* %A, i32 4 + %tmp = getelementptr float, float* %A, i32 4 ret float* %tmp } @@ -4490,7 +4490,7 @@ define float* @test_v2f32_post_reg_st1x2(float* %A, float** %ptr, <2 x float> %B ;CHECK-LABEL: test_v2f32_post_reg_st1x2: ;CHECK: st1.2s { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x2.v2f32.p0f32(<2 x float> %B, <2 x float> %C, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -4501,7 +4501,7 @@ define double* @test_v2f64_post_imm_st1x2(double* %A, double** %ptr, <2 x double ;CHECK-LABEL: test_v2f64_post_imm_st1x2: ;CHECK: st1.2d { v0, v1 }, [x0], #32 call void @llvm.aarch64.neon.st1x2.v2f64.p0f64(<2 x double> %B, <2 x double> %C, double* %A) - %tmp = getelementptr double* %A, i64 4 + %tmp = getelementptr double, double* %A, i64 4 ret double* %tmp } @@ -4509,7 +4509,7 @@ define double* @test_v2f64_post_reg_st1x2(double* %A, double** %ptr, <2 x double ;CHECK-LABEL: test_v2f64_post_reg_st1x2: ;CHECK: st1.2d { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x2.v2f64.p0f64(<2 x double> %B, <2 x double> %C, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -4520,7 +4520,7 @@ define double* @test_v1f64_post_imm_st1x2(double* %A, double** %ptr, <1 x double ;CHECK-LABEL: test_v1f64_post_imm_st1x2: ;CHECK: st1.1d { v0, v1 }, [x0], #16 call void @llvm.aarch64.neon.st1x2.v1f64.p0f64(<1 x double> %B, <1 x double> %C, double* %A) - %tmp = getelementptr double* %A, i64 2 + %tmp = getelementptr double, double* %A, i64 2 ret double* %tmp } @@ -4528,7 +4528,7 @@ define double* @test_v1f64_post_reg_st1x2(double* %A, double** %ptr, <1 x double ;CHECK-LABEL: test_v1f64_post_reg_st1x2: ;CHECK: st1.1d { v0, v1 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x2.v1f64.p0f64(<1 x double> %B, <1 x double> %C, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -4539,7 +4539,7 @@ define i8* @test_v16i8_post_imm_st1x3(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> ;CHECK-LABEL: test_v16i8_post_imm_st1x3: ;CHECK: st1.16b { v0, v1, v2 }, [x0], #48 call void @llvm.aarch64.neon.st1x3.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %A) - %tmp = getelementptr i8* %A, i32 48 + %tmp = getelementptr i8, i8* %A, i32 48 ret i8* %tmp } @@ -4547,7 +4547,7 @@ define i8* @test_v16i8_post_reg_st1x3(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> ;CHECK-LABEL: test_v16i8_post_reg_st1x3: ;CHECK: st1.16b { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x3.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -4558,7 +4558,7 @@ define i8* @test_v8i8_post_imm_st1x3(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C ;CHECK-LABEL: test_v8i8_post_imm_st1x3: ;CHECK: st1.8b { v0, v1, v2 }, [x0], #24 call void @llvm.aarch64.neon.st1x3.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %A) - %tmp = getelementptr i8* %A, i32 24 + %tmp = getelementptr i8, i8* %A, i32 24 ret i8* %tmp } @@ -4566,7 +4566,7 @@ define i8* @test_v8i8_post_reg_st1x3(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C ;CHECK-LABEL: test_v8i8_post_reg_st1x3: ;CHECK: st1.8b { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x3.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -4577,7 +4577,7 @@ define i16* @test_v8i16_post_imm_st1x3(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i ;CHECK-LABEL: test_v8i16_post_imm_st1x3: ;CHECK: st1.8h { v0, v1, v2 }, [x0], #48 call void @llvm.aarch64.neon.st1x3.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %A) - %tmp = getelementptr i16* %A, i32 24 + %tmp = getelementptr i16, i16* %A, i32 24 ret i16* %tmp } @@ -4585,7 +4585,7 @@ define i16* @test_v8i16_post_reg_st1x3(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i ;CHECK-LABEL: test_v8i16_post_reg_st1x3: ;CHECK: st1.8h { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x3.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -4596,7 +4596,7 @@ define i16* @test_v4i16_post_imm_st1x3(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i ;CHECK-LABEL: test_v4i16_post_imm_st1x3: ;CHECK: st1.4h { v0, v1, v2 }, [x0], #24 call void @llvm.aarch64.neon.st1x3.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %A) - %tmp = getelementptr i16* %A, i32 12 + %tmp = getelementptr i16, i16* %A, i32 12 ret i16* %tmp } @@ -4604,7 +4604,7 @@ define i16* @test_v4i16_post_reg_st1x3(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i ;CHECK-LABEL: test_v4i16_post_reg_st1x3: ;CHECK: st1.4h { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x3.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -4615,7 +4615,7 @@ define i32* @test_v4i32_post_imm_st1x3(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i ;CHECK-LABEL: test_v4i32_post_imm_st1x3: ;CHECK: st1.4s { v0, v1, v2 }, [x0], #48 call void @llvm.aarch64.neon.st1x3.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %A) - %tmp = getelementptr i32* %A, i32 12 + %tmp = getelementptr i32, i32* %A, i32 12 ret i32* %tmp } @@ -4623,7 +4623,7 @@ define i32* @test_v4i32_post_reg_st1x3(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i ;CHECK-LABEL: test_v4i32_post_reg_st1x3: ;CHECK: st1.4s { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x3.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -4634,7 +4634,7 @@ define i32* @test_v2i32_post_imm_st1x3(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i ;CHECK-LABEL: test_v2i32_post_imm_st1x3: ;CHECK: st1.2s { v0, v1, v2 }, [x0], #24 call void @llvm.aarch64.neon.st1x3.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %A) - %tmp = getelementptr i32* %A, i32 6 + %tmp = getelementptr i32, i32* %A, i32 6 ret i32* %tmp } @@ -4642,7 +4642,7 @@ define i32* @test_v2i32_post_reg_st1x3(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i ;CHECK-LABEL: test_v2i32_post_reg_st1x3: ;CHECK: st1.2s { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x3.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -4653,7 +4653,7 @@ define i64* @test_v2i64_post_imm_st1x3(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i ;CHECK-LABEL: test_v2i64_post_imm_st1x3: ;CHECK: st1.2d { v0, v1, v2 }, [x0], #48 call void @llvm.aarch64.neon.st1x3.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %A) - %tmp = getelementptr i64* %A, i64 6 + %tmp = getelementptr i64, i64* %A, i64 6 ret i64* %tmp } @@ -4661,7 +4661,7 @@ define i64* @test_v2i64_post_reg_st1x3(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i ;CHECK-LABEL: test_v2i64_post_reg_st1x3: ;CHECK: st1.2d { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x3.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -4672,7 +4672,7 @@ define i64* @test_v1i64_post_imm_st1x3(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i ;CHECK-LABEL: test_v1i64_post_imm_st1x3: ;CHECK: st1.1d { v0, v1, v2 }, [x0], #24 call void @llvm.aarch64.neon.st1x3.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %A) - %tmp = getelementptr i64* %A, i64 3 + %tmp = getelementptr i64, i64* %A, i64 3 ret i64* %tmp } @@ -4680,7 +4680,7 @@ define i64* @test_v1i64_post_reg_st1x3(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i ;CHECK-LABEL: test_v1i64_post_reg_st1x3: ;CHECK: st1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x3.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -4691,7 +4691,7 @@ define float* @test_v4f32_post_imm_st1x3(float* %A, float** %ptr, <4 x float> %B ;CHECK-LABEL: test_v4f32_post_imm_st1x3: ;CHECK: st1.4s { v0, v1, v2 }, [x0], #48 call void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, float* %A) - %tmp = getelementptr float* %A, i32 12 + %tmp = getelementptr float, float* %A, i32 12 ret float* %tmp } @@ -4699,7 +4699,7 @@ define float* @test_v4f32_post_reg_st1x3(float* %A, float** %ptr, <4 x float> %B ;CHECK-LABEL: test_v4f32_post_reg_st1x3: ;CHECK: st1.4s { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -4710,7 +4710,7 @@ define float* @test_v2f32_post_imm_st1x3(float* %A, float** %ptr, <2 x float> %B ;CHECK-LABEL: test_v2f32_post_imm_st1x3: ;CHECK: st1.2s { v0, v1, v2 }, [x0], #24 call void @llvm.aarch64.neon.st1x3.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, float* %A) - %tmp = getelementptr float* %A, i32 6 + %tmp = getelementptr float, float* %A, i32 6 ret float* %tmp } @@ -4718,7 +4718,7 @@ define float* @test_v2f32_post_reg_st1x3(float* %A, float** %ptr, <2 x float> %B ;CHECK-LABEL: test_v2f32_post_reg_st1x3: ;CHECK: st1.2s { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x3.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -4729,7 +4729,7 @@ define double* @test_v2f64_post_imm_st1x3(double* %A, double** %ptr, <2 x double ;CHECK-LABEL: test_v2f64_post_imm_st1x3: ;CHECK: st1.2d { v0, v1, v2 }, [x0], #48 call void @llvm.aarch64.neon.st1x3.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, double* %A) - %tmp = getelementptr double* %A, i64 6 + %tmp = getelementptr double, double* %A, i64 6 ret double* %tmp } @@ -4737,7 +4737,7 @@ define double* @test_v2f64_post_reg_st1x3(double* %A, double** %ptr, <2 x double ;CHECK-LABEL: test_v2f64_post_reg_st1x3: ;CHECK: st1.2d { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x3.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -4748,7 +4748,7 @@ define double* @test_v1f64_post_imm_st1x3(double* %A, double** %ptr, <1 x double ;CHECK-LABEL: test_v1f64_post_imm_st1x3: ;CHECK: st1.1d { v0, v1, v2 }, [x0], #24 call void @llvm.aarch64.neon.st1x3.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, double* %A) - %tmp = getelementptr double* %A, i64 3 + %tmp = getelementptr double, double* %A, i64 3 ret double* %tmp } @@ -4756,7 +4756,7 @@ define double* @test_v1f64_post_reg_st1x3(double* %A, double** %ptr, <1 x double ;CHECK-LABEL: test_v1f64_post_reg_st1x3: ;CHECK: st1.1d { v0, v1, v2 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x3.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -4767,7 +4767,7 @@ define i8* @test_v16i8_post_imm_st1x4(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> ;CHECK-LABEL: test_v16i8_post_imm_st1x4: ;CHECK: st1.16b { v0, v1, v2, v3 }, [x0], #64 call void @llvm.aarch64.neon.st1x4.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i8* %A) - %tmp = getelementptr i8* %A, i32 64 + %tmp = getelementptr i8, i8* %A, i32 64 ret i8* %tmp } @@ -4775,7 +4775,7 @@ define i8* @test_v16i8_post_reg_st1x4(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> ;CHECK-LABEL: test_v16i8_post_reg_st1x4: ;CHECK: st1.16b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x4.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -4786,7 +4786,7 @@ define i8* @test_v8i8_post_imm_st1x4(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C ;CHECK-LABEL: test_v8i8_post_imm_st1x4: ;CHECK: st1.8b { v0, v1, v2, v3 }, [x0], #32 call void @llvm.aarch64.neon.st1x4.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i8* %A) - %tmp = getelementptr i8* %A, i32 32 + %tmp = getelementptr i8, i8* %A, i32 32 ret i8* %tmp } @@ -4794,7 +4794,7 @@ define i8* @test_v8i8_post_reg_st1x4(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> %C ;CHECK-LABEL: test_v8i8_post_reg_st1x4: ;CHECK: st1.8b { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x4.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -4805,7 +4805,7 @@ define i16* @test_v8i16_post_imm_st1x4(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i ;CHECK-LABEL: test_v8i16_post_imm_st1x4: ;CHECK: st1.8h { v0, v1, v2, v3 }, [x0], #64 call void @llvm.aarch64.neon.st1x4.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i16* %A) - %tmp = getelementptr i16* %A, i32 32 + %tmp = getelementptr i16, i16* %A, i32 32 ret i16* %tmp } @@ -4813,7 +4813,7 @@ define i16* @test_v8i16_post_reg_st1x4(i16* %A, i16** %ptr, <8 x i16> %B, <8 x i ;CHECK-LABEL: test_v8i16_post_reg_st1x4: ;CHECK: st1.8h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x4.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -4824,7 +4824,7 @@ define i16* @test_v4i16_post_imm_st1x4(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i ;CHECK-LABEL: test_v4i16_post_imm_st1x4: ;CHECK: st1.4h { v0, v1, v2, v3 }, [x0], #32 call void @llvm.aarch64.neon.st1x4.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i16* %A) - %tmp = getelementptr i16* %A, i32 16 + %tmp = getelementptr i16, i16* %A, i32 16 ret i16* %tmp } @@ -4832,7 +4832,7 @@ define i16* @test_v4i16_post_reg_st1x4(i16* %A, i16** %ptr, <4 x i16> %B, <4 x i ;CHECK-LABEL: test_v4i16_post_reg_st1x4: ;CHECK: st1.4h { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x4.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -4843,7 +4843,7 @@ define i32* @test_v4i32_post_imm_st1x4(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i ;CHECK-LABEL: test_v4i32_post_imm_st1x4: ;CHECK: st1.4s { v0, v1, v2, v3 }, [x0], #64 call void @llvm.aarch64.neon.st1x4.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i32* %A) - %tmp = getelementptr i32* %A, i32 16 + %tmp = getelementptr i32, i32* %A, i32 16 ret i32* %tmp } @@ -4851,7 +4851,7 @@ define i32* @test_v4i32_post_reg_st1x4(i32* %A, i32** %ptr, <4 x i32> %B, <4 x i ;CHECK-LABEL: test_v4i32_post_reg_st1x4: ;CHECK: st1.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x4.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -4862,7 +4862,7 @@ define i32* @test_v2i32_post_imm_st1x4(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i ;CHECK-LABEL: test_v2i32_post_imm_st1x4: ;CHECK: st1.2s { v0, v1, v2, v3 }, [x0], #32 call void @llvm.aarch64.neon.st1x4.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i32* %A) - %tmp = getelementptr i32* %A, i32 8 + %tmp = getelementptr i32, i32* %A, i32 8 ret i32* %tmp } @@ -4870,7 +4870,7 @@ define i32* @test_v2i32_post_reg_st1x4(i32* %A, i32** %ptr, <2 x i32> %B, <2 x i ;CHECK-LABEL: test_v2i32_post_reg_st1x4: ;CHECK: st1.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x4.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -4881,7 +4881,7 @@ define i64* @test_v2i64_post_imm_st1x4(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i ;CHECK-LABEL: test_v2i64_post_imm_st1x4: ;CHECK: st1.2d { v0, v1, v2, v3 }, [x0], #64 call void @llvm.aarch64.neon.st1x4.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64* %A) - %tmp = getelementptr i64* %A, i64 8 + %tmp = getelementptr i64, i64* %A, i64 8 ret i64* %tmp } @@ -4889,7 +4889,7 @@ define i64* @test_v2i64_post_reg_st1x4(i64* %A, i64** %ptr, <2 x i64> %B, <2 x i ;CHECK-LABEL: test_v2i64_post_reg_st1x4: ;CHECK: st1.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x4.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -4900,7 +4900,7 @@ define i64* @test_v1i64_post_imm_st1x4(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i ;CHECK-LABEL: test_v1i64_post_imm_st1x4: ;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], #32 call void @llvm.aarch64.neon.st1x4.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64* %A) - %tmp = getelementptr i64* %A, i64 4 + %tmp = getelementptr i64, i64* %A, i64 4 ret i64* %tmp } @@ -4908,7 +4908,7 @@ define i64* @test_v1i64_post_reg_st1x4(i64* %A, i64** %ptr, <1 x i64> %B, <1 x i ;CHECK-LABEL: test_v1i64_post_reg_st1x4: ;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x4.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -4919,7 +4919,7 @@ define float* @test_v4f32_post_imm_st1x4(float* %A, float** %ptr, <4 x float> %B ;CHECK-LABEL: test_v4f32_post_imm_st1x4: ;CHECK: st1.4s { v0, v1, v2, v3 }, [x0], #64 call void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, float* %A) - %tmp = getelementptr float* %A, i32 16 + %tmp = getelementptr float, float* %A, i32 16 ret float* %tmp } @@ -4927,7 +4927,7 @@ define float* @test_v4f32_post_reg_st1x4(float* %A, float** %ptr, <4 x float> %B ;CHECK-LABEL: test_v4f32_post_reg_st1x4: ;CHECK: st1.4s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -4938,7 +4938,7 @@ define float* @test_v2f32_post_imm_st1x4(float* %A, float** %ptr, <2 x float> %B ;CHECK-LABEL: test_v2f32_post_imm_st1x4: ;CHECK: st1.2s { v0, v1, v2, v3 }, [x0], #32 call void @llvm.aarch64.neon.st1x4.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, float* %A) - %tmp = getelementptr float* %A, i32 8 + %tmp = getelementptr float, float* %A, i32 8 ret float* %tmp } @@ -4946,7 +4946,7 @@ define float* @test_v2f32_post_reg_st1x4(float* %A, float** %ptr, <2 x float> %B ;CHECK-LABEL: test_v2f32_post_reg_st1x4: ;CHECK: st1.2s { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x4.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -4957,7 +4957,7 @@ define double* @test_v2f64_post_imm_st1x4(double* %A, double** %ptr, <2 x double ;CHECK-LABEL: test_v2f64_post_imm_st1x4: ;CHECK: st1.2d { v0, v1, v2, v3 }, [x0], #64 call void @llvm.aarch64.neon.st1x4.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, double* %A) - %tmp = getelementptr double* %A, i64 8 + %tmp = getelementptr double, double* %A, i64 8 ret double* %tmp } @@ -4965,7 +4965,7 @@ define double* @test_v2f64_post_reg_st1x4(double* %A, double** %ptr, <2 x double ;CHECK-LABEL: test_v2f64_post_reg_st1x4: ;CHECK: st1.2d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x4.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -4976,7 +4976,7 @@ define double* @test_v1f64_post_imm_st1x4(double* %A, double** %ptr, <1 x double ;CHECK-LABEL: test_v1f64_post_imm_st1x4: ;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], #32 call void @llvm.aarch64.neon.st1x4.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, double* %A) - %tmp = getelementptr double* %A, i64 4 + %tmp = getelementptr double, double* %A, i64 4 ret double* %tmp } @@ -4984,7 +4984,7 @@ define double* @test_v1f64_post_reg_st1x4(double* %A, double** %ptr, <1 x double ;CHECK-LABEL: test_v1f64_post_reg_st1x4: ;CHECK: st1.1d { v0, v1, v2, v3 }, [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st1x4.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -4993,13 +4993,13 @@ declare void @llvm.aarch64.neon.st1x4.v1f64.p0f64(<1 x double>, <1 x double>, <1 define i8* @test_v16i8_post_imm_st2lanelane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C) { call void @llvm.aarch64.neon.st2lanelane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i64 1, i8* %A) - %tmp = getelementptr i8* %A, i32 2 + %tmp = getelementptr i8, i8* %A, i32 2 ret i8* %tmp } define i8* @test_v16i8_post_reg_st2lanelane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i8> %C, i64 %inc) { call void @llvm.aarch64.neon.st2lanelane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i64 1, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -5010,7 +5010,7 @@ define i8* @test_v16i8_post_imm_st2lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i ;CHECK-LABEL: test_v16i8_post_imm_st2lane: ;CHECK: st2.b { v0, v1 }[0], [x0], #2 call void @llvm.aarch64.neon.st2lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i32 2 + %tmp = getelementptr i8, i8* %A, i32 2 ret i8* %tmp } @@ -5018,7 +5018,7 @@ define i8* @test_v16i8_post_reg_st2lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i ;CHECK-LABEL: test_v16i8_post_reg_st2lane: ;CHECK: st2.b { v0, v1 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -5029,7 +5029,7 @@ define i8* @test_v8i8_post_imm_st2lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> ;CHECK-LABEL: test_v8i8_post_imm_st2lane: ;CHECK: st2.b { v0, v1 }[0], [x0], #2 call void @llvm.aarch64.neon.st2lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i32 2 + %tmp = getelementptr i8, i8* %A, i32 2 ret i8* %tmp } @@ -5037,7 +5037,7 @@ define i8* @test_v8i8_post_reg_st2lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> ;CHECK-LABEL: test_v8i8_post_reg_st2lane: ;CHECK: st2.b { v0, v1 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -5048,7 +5048,7 @@ define i16* @test_v8i16_post_imm_st2lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x ;CHECK-LABEL: test_v8i16_post_imm_st2lane: ;CHECK: st2.h { v0, v1 }[0], [x0], #4 call void @llvm.aarch64.neon.st2lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i32 2 + %tmp = getelementptr i16, i16* %A, i32 2 ret i16* %tmp } @@ -5056,7 +5056,7 @@ define i16* @test_v8i16_post_reg_st2lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x ;CHECK-LABEL: test_v8i16_post_reg_st2lane: ;CHECK: st2.h { v0, v1 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -5067,7 +5067,7 @@ define i16* @test_v4i16_post_imm_st2lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x ;CHECK-LABEL: test_v4i16_post_imm_st2lane: ;CHECK: st2.h { v0, v1 }[0], [x0], #4 call void @llvm.aarch64.neon.st2lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i32 2 + %tmp = getelementptr i16, i16* %A, i32 2 ret i16* %tmp } @@ -5075,7 +5075,7 @@ define i16* @test_v4i16_post_reg_st2lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x ;CHECK-LABEL: test_v4i16_post_reg_st2lane: ;CHECK: st2.h { v0, v1 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -5086,7 +5086,7 @@ define i32* @test_v4i32_post_imm_st2lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x ;CHECK-LABEL: test_v4i32_post_imm_st2lane: ;CHECK: st2.s { v0, v1 }[0], [x0], #8 call void @llvm.aarch64.neon.st2lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i32 2 + %tmp = getelementptr i32, i32* %A, i32 2 ret i32* %tmp } @@ -5094,7 +5094,7 @@ define i32* @test_v4i32_post_reg_st2lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x ;CHECK-LABEL: test_v4i32_post_reg_st2lane: ;CHECK: st2.s { v0, v1 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -5105,7 +5105,7 @@ define i32* @test_v2i32_post_imm_st2lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x ;CHECK-LABEL: test_v2i32_post_imm_st2lane: ;CHECK: st2.s { v0, v1 }[0], [x0], #8 call void @llvm.aarch64.neon.st2lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i32 2 + %tmp = getelementptr i32, i32* %A, i32 2 ret i32* %tmp } @@ -5113,7 +5113,7 @@ define i32* @test_v2i32_post_reg_st2lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x ;CHECK-LABEL: test_v2i32_post_reg_st2lane: ;CHECK: st2.s { v0, v1 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -5124,7 +5124,7 @@ define i64* @test_v2i64_post_imm_st2lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x ;CHECK-LABEL: test_v2i64_post_imm_st2lane: ;CHECK: st2.d { v0, v1 }[0], [x0], #16 call void @llvm.aarch64.neon.st2lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 2 + %tmp = getelementptr i64, i64* %A, i64 2 ret i64* %tmp } @@ -5132,7 +5132,7 @@ define i64* @test_v2i64_post_reg_st2lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x ;CHECK-LABEL: test_v2i64_post_reg_st2lane: ;CHECK: st2.d { v0, v1 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -5143,7 +5143,7 @@ define i64* @test_v1i64_post_imm_st2lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x ;CHECK-LABEL: test_v1i64_post_imm_st2lane: ;CHECK: st2.d { v0, v1 }[0], [x0], #16 call void @llvm.aarch64.neon.st2lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 2 + %tmp = getelementptr i64, i64* %A, i64 2 ret i64* %tmp } @@ -5151,7 +5151,7 @@ define i64* @test_v1i64_post_reg_st2lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x ;CHECK-LABEL: test_v1i64_post_reg_st2lane: ;CHECK: st2.d { v0, v1 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -5162,7 +5162,7 @@ define float* @test_v4f32_post_imm_st2lane(float* %A, float** %ptr, <4 x float> ;CHECK-LABEL: test_v4f32_post_imm_st2lane: ;CHECK: st2.s { v0, v1 }[0], [x0], #8 call void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, i64 0, float* %A) - %tmp = getelementptr float* %A, i32 2 + %tmp = getelementptr float, float* %A, i32 2 ret float* %tmp } @@ -5170,7 +5170,7 @@ define float* @test_v4f32_post_reg_st2lane(float* %A, float** %ptr, <4 x float> ;CHECK-LABEL: test_v4f32_post_reg_st2lane: ;CHECK: st2.s { v0, v1 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, i64 0, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -5181,7 +5181,7 @@ define float* @test_v2f32_post_imm_st2lane(float* %A, float** %ptr, <2 x float> ;CHECK-LABEL: test_v2f32_post_imm_st2lane: ;CHECK: st2.s { v0, v1 }[0], [x0], #8 call void @llvm.aarch64.neon.st2lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, i64 0, float* %A) - %tmp = getelementptr float* %A, i32 2 + %tmp = getelementptr float, float* %A, i32 2 ret float* %tmp } @@ -5189,7 +5189,7 @@ define float* @test_v2f32_post_reg_st2lane(float* %A, float** %ptr, <2 x float> ;CHECK-LABEL: test_v2f32_post_reg_st2lane: ;CHECK: st2.s { v0, v1 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, i64 0, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -5200,7 +5200,7 @@ define double* @test_v2f64_post_imm_st2lane(double* %A, double** %ptr, <2 x doub ;CHECK-LABEL: test_v2f64_post_imm_st2lane: ;CHECK: st2.d { v0, v1 }[0], [x0], #16 call void @llvm.aarch64.neon.st2lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 2 + %tmp = getelementptr double, double* %A, i64 2 ret double* %tmp } @@ -5208,7 +5208,7 @@ define double* @test_v2f64_post_reg_st2lane(double* %A, double** %ptr, <2 x doub ;CHECK-LABEL: test_v2f64_post_reg_st2lane: ;CHECK: st2.d { v0, v1 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -5219,7 +5219,7 @@ define double* @test_v1f64_post_imm_st2lane(double* %A, double** %ptr, <1 x doub ;CHECK-LABEL: test_v1f64_post_imm_st2lane: ;CHECK: st2.d { v0, v1 }[0], [x0], #16 call void @llvm.aarch64.neon.st2lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 2 + %tmp = getelementptr double, double* %A, i64 2 ret double* %tmp } @@ -5227,7 +5227,7 @@ define double* @test_v1f64_post_reg_st2lane(double* %A, double** %ptr, <1 x doub ;CHECK-LABEL: test_v1f64_post_reg_st2lane: ;CHECK: st2.d { v0, v1 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st2lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -5238,7 +5238,7 @@ define i8* @test_v16i8_post_imm_st3lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i ;CHECK-LABEL: test_v16i8_post_imm_st3lane: ;CHECK: st3.b { v0, v1, v2 }[0], [x0], #3 call void @llvm.aarch64.neon.st3lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i32 3 + %tmp = getelementptr i8, i8* %A, i32 3 ret i8* %tmp } @@ -5246,7 +5246,7 @@ define i8* @test_v16i8_post_reg_st3lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i ;CHECK-LABEL: test_v16i8_post_reg_st3lane: ;CHECK: st3.b { v0, v1, v2 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -5257,7 +5257,7 @@ define i8* @test_v8i8_post_imm_st3lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> ;CHECK-LABEL: test_v8i8_post_imm_st3lane: ;CHECK: st3.b { v0, v1, v2 }[0], [x0], #3 call void @llvm.aarch64.neon.st3lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i32 3 + %tmp = getelementptr i8, i8* %A, i32 3 ret i8* %tmp } @@ -5265,7 +5265,7 @@ define i8* @test_v8i8_post_reg_st3lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> ;CHECK-LABEL: test_v8i8_post_reg_st3lane: ;CHECK: st3.b { v0, v1, v2 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -5276,7 +5276,7 @@ define i16* @test_v8i16_post_imm_st3lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x ;CHECK-LABEL: test_v8i16_post_imm_st3lane: ;CHECK: st3.h { v0, v1, v2 }[0], [x0], #6 call void @llvm.aarch64.neon.st3lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i32 3 + %tmp = getelementptr i16, i16* %A, i32 3 ret i16* %tmp } @@ -5284,7 +5284,7 @@ define i16* @test_v8i16_post_reg_st3lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x ;CHECK-LABEL: test_v8i16_post_reg_st3lane: ;CHECK: st3.h { v0, v1, v2 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -5295,7 +5295,7 @@ define i16* @test_v4i16_post_imm_st3lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x ;CHECK-LABEL: test_v4i16_post_imm_st3lane: ;CHECK: st3.h { v0, v1, v2 }[0], [x0], #6 call void @llvm.aarch64.neon.st3lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i32 3 + %tmp = getelementptr i16, i16* %A, i32 3 ret i16* %tmp } @@ -5303,7 +5303,7 @@ define i16* @test_v4i16_post_reg_st3lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x ;CHECK-LABEL: test_v4i16_post_reg_st3lane: ;CHECK: st3.h { v0, v1, v2 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -5314,7 +5314,7 @@ define i32* @test_v4i32_post_imm_st3lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x ;CHECK-LABEL: test_v4i32_post_imm_st3lane: ;CHECK: st3.s { v0, v1, v2 }[0], [x0], #12 call void @llvm.aarch64.neon.st3lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i32 3 + %tmp = getelementptr i32, i32* %A, i32 3 ret i32* %tmp } @@ -5322,7 +5322,7 @@ define i32* @test_v4i32_post_reg_st3lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x ;CHECK-LABEL: test_v4i32_post_reg_st3lane: ;CHECK: st3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -5333,7 +5333,7 @@ define i32* @test_v2i32_post_imm_st3lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x ;CHECK-LABEL: test_v2i32_post_imm_st3lane: ;CHECK: st3.s { v0, v1, v2 }[0], [x0], #12 call void @llvm.aarch64.neon.st3lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i32 3 + %tmp = getelementptr i32, i32* %A, i32 3 ret i32* %tmp } @@ -5341,7 +5341,7 @@ define i32* @test_v2i32_post_reg_st3lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x ;CHECK-LABEL: test_v2i32_post_reg_st3lane: ;CHECK: st3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -5352,7 +5352,7 @@ define i64* @test_v2i64_post_imm_st3lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x ;CHECK-LABEL: test_v2i64_post_imm_st3lane: ;CHECK: st3.d { v0, v1, v2 }[0], [x0], #24 call void @llvm.aarch64.neon.st3lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 3 + %tmp = getelementptr i64, i64* %A, i64 3 ret i64* %tmp } @@ -5360,7 +5360,7 @@ define i64* @test_v2i64_post_reg_st3lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x ;CHECK-LABEL: test_v2i64_post_reg_st3lane: ;CHECK: st3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -5371,7 +5371,7 @@ define i64* @test_v1i64_post_imm_st3lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x ;CHECK-LABEL: test_v1i64_post_imm_st3lane: ;CHECK: st3.d { v0, v1, v2 }[0], [x0], #24 call void @llvm.aarch64.neon.st3lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 3 + %tmp = getelementptr i64, i64* %A, i64 3 ret i64* %tmp } @@ -5379,7 +5379,7 @@ define i64* @test_v1i64_post_reg_st3lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x ;CHECK-LABEL: test_v1i64_post_reg_st3lane: ;CHECK: st3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -5390,7 +5390,7 @@ define float* @test_v4f32_post_imm_st3lane(float* %A, float** %ptr, <4 x float> ;CHECK-LABEL: test_v4f32_post_imm_st3lane: ;CHECK: st3.s { v0, v1, v2 }[0], [x0], #12 call void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, i64 0, float* %A) - %tmp = getelementptr float* %A, i32 3 + %tmp = getelementptr float, float* %A, i32 3 ret float* %tmp } @@ -5398,7 +5398,7 @@ define float* @test_v4f32_post_reg_st3lane(float* %A, float** %ptr, <4 x float> ;CHECK-LABEL: test_v4f32_post_reg_st3lane: ;CHECK: st3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, i64 0, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -5409,7 +5409,7 @@ define float* @test_v2f32_post_imm_st3lane(float* %A, float** %ptr, <2 x float> ;CHECK-LABEL: test_v2f32_post_imm_st3lane: ;CHECK: st3.s { v0, v1, v2 }[0], [x0], #12 call void @llvm.aarch64.neon.st3lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, i64 0, float* %A) - %tmp = getelementptr float* %A, i32 3 + %tmp = getelementptr float, float* %A, i32 3 ret float* %tmp } @@ -5417,7 +5417,7 @@ define float* @test_v2f32_post_reg_st3lane(float* %A, float** %ptr, <2 x float> ;CHECK-LABEL: test_v2f32_post_reg_st3lane: ;CHECK: st3.s { v0, v1, v2 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, i64 0, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -5428,7 +5428,7 @@ define double* @test_v2f64_post_imm_st3lane(double* %A, double** %ptr, <2 x doub ;CHECK-LABEL: test_v2f64_post_imm_st3lane: ;CHECK: st3.d { v0, v1, v2 }[0], [x0], #24 call void @llvm.aarch64.neon.st3lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 3 + %tmp = getelementptr double, double* %A, i64 3 ret double* %tmp } @@ -5436,7 +5436,7 @@ define double* @test_v2f64_post_reg_st3lane(double* %A, double** %ptr, <2 x doub ;CHECK-LABEL: test_v2f64_post_reg_st3lane: ;CHECK: st3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -5447,7 +5447,7 @@ define double* @test_v1f64_post_imm_st3lane(double* %A, double** %ptr, <1 x doub ;CHECK-LABEL: test_v1f64_post_imm_st3lane: ;CHECK: st3.d { v0, v1, v2 }[0], [x0], #24 call void @llvm.aarch64.neon.st3lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 3 + %tmp = getelementptr double, double* %A, i64 3 ret double* %tmp } @@ -5455,7 +5455,7 @@ define double* @test_v1f64_post_reg_st3lane(double* %A, double** %ptr, <1 x doub ;CHECK-LABEL: test_v1f64_post_reg_st3lane: ;CHECK: st3.d { v0, v1, v2 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st3lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -5466,7 +5466,7 @@ define i8* @test_v16i8_post_imm_st4lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i ;CHECK-LABEL: test_v16i8_post_imm_st4lane: ;CHECK: st4.b { v0, v1, v2, v3 }[0], [x0], #4 call void @llvm.aarch64.neon.st4lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i32 4 + %tmp = getelementptr i8, i8* %A, i32 4 ret i8* %tmp } @@ -5474,7 +5474,7 @@ define i8* @test_v16i8_post_reg_st4lane(i8* %A, i8** %ptr, <16 x i8> %B, <16 x i ;CHECK-LABEL: test_v16i8_post_reg_st4lane: ;CHECK: st4.b { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4lane.v16i8.p0i8(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -5485,7 +5485,7 @@ define i8* @test_v8i8_post_imm_st4lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> ;CHECK-LABEL: test_v8i8_post_imm_st4lane: ;CHECK: st4.b { v0, v1, v2, v3 }[0], [x0], #4 call void @llvm.aarch64.neon.st4lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i32 4 + %tmp = getelementptr i8, i8* %A, i32 4 ret i8* %tmp } @@ -5493,7 +5493,7 @@ define i8* @test_v8i8_post_reg_st4lane(i8* %A, i8** %ptr, <8 x i8> %B, <8 x i8> ;CHECK-LABEL: test_v8i8_post_reg_st4lane: ;CHECK: st4.b { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4lane.v8i8.p0i8(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 0, i8* %A) - %tmp = getelementptr i8* %A, i64 %inc + %tmp = getelementptr i8, i8* %A, i64 %inc ret i8* %tmp } @@ -5504,7 +5504,7 @@ define i16* @test_v8i16_post_imm_st4lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x ;CHECK-LABEL: test_v8i16_post_imm_st4lane: ;CHECK: st4.h { v0, v1, v2, v3 }[0], [x0], #8 call void @llvm.aarch64.neon.st4lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i32 4 + %tmp = getelementptr i16, i16* %A, i32 4 ret i16* %tmp } @@ -5512,7 +5512,7 @@ define i16* @test_v8i16_post_reg_st4lane(i16* %A, i16** %ptr, <8 x i16> %B, <8 x ;CHECK-LABEL: test_v8i16_post_reg_st4lane: ;CHECK: st4.h { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4lane.v8i16.p0i16(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -5523,7 +5523,7 @@ define i16* @test_v4i16_post_imm_st4lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x ;CHECK-LABEL: test_v4i16_post_imm_st4lane: ;CHECK: st4.h { v0, v1, v2, v3 }[0], [x0], #8 call void @llvm.aarch64.neon.st4lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i32 4 + %tmp = getelementptr i16, i16* %A, i32 4 ret i16* %tmp } @@ -5531,7 +5531,7 @@ define i16* @test_v4i16_post_reg_st4lane(i16* %A, i16** %ptr, <4 x i16> %B, <4 x ;CHECK-LABEL: test_v4i16_post_reg_st4lane: ;CHECK: st4.h { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4lane.v4i16.p0i16(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 0, i16* %A) - %tmp = getelementptr i16* %A, i64 %inc + %tmp = getelementptr i16, i16* %A, i64 %inc ret i16* %tmp } @@ -5542,7 +5542,7 @@ define i32* @test_v4i32_post_imm_st4lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x ;CHECK-LABEL: test_v4i32_post_imm_st4lane: ;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], #16 call void @llvm.aarch64.neon.st4lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i32 4 + %tmp = getelementptr i32, i32* %A, i32 4 ret i32* %tmp } @@ -5550,7 +5550,7 @@ define i32* @test_v4i32_post_reg_st4lane(i32* %A, i32** %ptr, <4 x i32> %B, <4 x ;CHECK-LABEL: test_v4i32_post_reg_st4lane: ;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4lane.v4i32.p0i32(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -5561,7 +5561,7 @@ define i32* @test_v2i32_post_imm_st4lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x ;CHECK-LABEL: test_v2i32_post_imm_st4lane: ;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], #16 call void @llvm.aarch64.neon.st4lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i32 4 + %tmp = getelementptr i32, i32* %A, i32 4 ret i32* %tmp } @@ -5569,7 +5569,7 @@ define i32* @test_v2i32_post_reg_st4lane(i32* %A, i32** %ptr, <2 x i32> %B, <2 x ;CHECK-LABEL: test_v2i32_post_reg_st4lane: ;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4lane.v2i32.p0i32(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 0, i32* %A) - %tmp = getelementptr i32* %A, i64 %inc + %tmp = getelementptr i32, i32* %A, i64 %inc ret i32* %tmp } @@ -5580,7 +5580,7 @@ define i64* @test_v2i64_post_imm_st4lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x ;CHECK-LABEL: test_v2i64_post_imm_st4lane: ;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], #32 call void @llvm.aarch64.neon.st4lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 4 + %tmp = getelementptr i64, i64* %A, i64 4 ret i64* %tmp } @@ -5588,7 +5588,7 @@ define i64* @test_v2i64_post_reg_st4lane(i64* %A, i64** %ptr, <2 x i64> %B, <2 x ;CHECK-LABEL: test_v2i64_post_reg_st4lane: ;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4lane.v2i64.p0i64(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -5599,7 +5599,7 @@ define i64* @test_v1i64_post_imm_st4lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x ;CHECK-LABEL: test_v1i64_post_imm_st4lane: ;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], #32 call void @llvm.aarch64.neon.st4lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 4 + %tmp = getelementptr i64, i64* %A, i64 4 ret i64* %tmp } @@ -5607,7 +5607,7 @@ define i64* @test_v1i64_post_reg_st4lane(i64* %A, i64** %ptr, <1 x i64> %B, <1 x ;CHECK-LABEL: test_v1i64_post_reg_st4lane: ;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4lane.v1i64.p0i64(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 0, i64* %A) - %tmp = getelementptr i64* %A, i64 %inc + %tmp = getelementptr i64, i64* %A, i64 %inc ret i64* %tmp } @@ -5618,7 +5618,7 @@ define float* @test_v4f32_post_imm_st4lane(float* %A, float** %ptr, <4 x float> ;CHECK-LABEL: test_v4f32_post_imm_st4lane: ;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], #16 call void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 0, float* %A) - %tmp = getelementptr float* %A, i32 4 + %tmp = getelementptr float, float* %A, i32 4 ret float* %tmp } @@ -5626,7 +5626,7 @@ define float* @test_v4f32_post_reg_st4lane(float* %A, float** %ptr, <4 x float> ;CHECK-LABEL: test_v4f32_post_reg_st4lane: ;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 0, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -5637,7 +5637,7 @@ define float* @test_v2f32_post_imm_st4lane(float* %A, float** %ptr, <2 x float> ;CHECK-LABEL: test_v2f32_post_imm_st4lane: ;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], #16 call void @llvm.aarch64.neon.st4lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 0, float* %A) - %tmp = getelementptr float* %A, i32 4 + %tmp = getelementptr float, float* %A, i32 4 ret float* %tmp } @@ -5645,7 +5645,7 @@ define float* @test_v2f32_post_reg_st4lane(float* %A, float** %ptr, <2 x float> ;CHECK-LABEL: test_v2f32_post_reg_st4lane: ;CHECK: st4.s { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4lane.v2f32.p0f32(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 0, float* %A) - %tmp = getelementptr float* %A, i64 %inc + %tmp = getelementptr float, float* %A, i64 %inc ret float* %tmp } @@ -5656,7 +5656,7 @@ define double* @test_v2f64_post_imm_st4lane(double* %A, double** %ptr, <2 x doub ;CHECK-LABEL: test_v2f64_post_imm_st4lane: ;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], #32 call void @llvm.aarch64.neon.st4lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 4 + %tmp = getelementptr double, double* %A, i64 4 ret double* %tmp } @@ -5664,7 +5664,7 @@ define double* @test_v2f64_post_reg_st4lane(double* %A, double** %ptr, <2 x doub ;CHECK-LABEL: test_v2f64_post_reg_st4lane: ;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4lane.v2f64.p0f64(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -5675,7 +5675,7 @@ define double* @test_v1f64_post_imm_st4lane(double* %A, double** %ptr, <1 x doub ;CHECK-LABEL: test_v1f64_post_imm_st4lane: ;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], #32 call void @llvm.aarch64.neon.st4lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 4 + %tmp = getelementptr double, double* %A, i64 4 ret double* %tmp } @@ -5683,7 +5683,7 @@ define double* @test_v1f64_post_reg_st4lane(double* %A, double** %ptr, <1 x doub ;CHECK-LABEL: test_v1f64_post_reg_st4lane: ;CHECK: st4.d { v0, v1, v2, v3 }[0], [x0], x{{[0-9]+}} call void @llvm.aarch64.neon.st4lane.v1f64.p0f64(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 0, double* %A) - %tmp = getelementptr double* %A, i64 %inc + %tmp = getelementptr double, double* %A, i64 %inc ret double* %tmp } @@ -5692,7 +5692,7 @@ declare void @llvm.aarch64.neon.st4lane.v1f64.p0f64(<1 x double>, <1 x double>, define <16 x i8> @test_v16i8_post_imm_ld1r(i8* %bar, i8** %ptr) { ; CHECK-LABEL: test_v16i8_post_imm_ld1r: ; CHECK: ld1r.16b { v0 }, [x0], #1 - %tmp1 = load i8* %bar + %tmp1 = load i8, i8* %bar %tmp2 = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0 %tmp3 = insertelement <16 x i8> %tmp2, i8 %tmp1, i32 1 %tmp4 = insertelement <16 x i8> %tmp3, i8 %tmp1, i32 2 @@ -5709,7 +5709,7 @@ define <16 x i8> @test_v16i8_post_imm_ld1r(i8* %bar, i8** %ptr) { %tmp15 = insertelement <16 x i8> %tmp14, i8 %tmp1, i32 13 %tmp16 = insertelement <16 x i8> %tmp15, i8 %tmp1, i32 14 %tmp17 = insertelement <16 x i8> %tmp16, i8 %tmp1, i32 15 - %tmp18 = getelementptr i8* %bar, i64 1 + %tmp18 = getelementptr i8, i8* %bar, i64 1 store i8* %tmp18, i8** %ptr ret <16 x i8> %tmp17 } @@ -5717,7 +5717,7 @@ define <16 x i8> @test_v16i8_post_imm_ld1r(i8* %bar, i8** %ptr) { define <16 x i8> @test_v16i8_post_reg_ld1r(i8* %bar, i8** %ptr, i64 %inc) { ; CHECK-LABEL: test_v16i8_post_reg_ld1r: ; CHECK: ld1r.16b { v0 }, [x0], x{{[0-9]+}} - %tmp1 = load i8* %bar + %tmp1 = load i8, i8* %bar %tmp2 = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0 %tmp3 = insertelement <16 x i8> %tmp2, i8 %tmp1, i32 1 %tmp4 = insertelement <16 x i8> %tmp3, i8 %tmp1, i32 2 @@ -5734,7 +5734,7 @@ define <16 x i8> @test_v16i8_post_reg_ld1r(i8* %bar, i8** %ptr, i64 %inc) { %tmp15 = insertelement <16 x i8> %tmp14, i8 %tmp1, i32 13 %tmp16 = insertelement <16 x i8> %tmp15, i8 %tmp1, i32 14 %tmp17 = insertelement <16 x i8> %tmp16, i8 %tmp1, i32 15 - %tmp18 = getelementptr i8* %bar, i64 %inc + %tmp18 = getelementptr i8, i8* %bar, i64 %inc store i8* %tmp18, i8** %ptr ret <16 x i8> %tmp17 } @@ -5742,7 +5742,7 @@ define <16 x i8> @test_v16i8_post_reg_ld1r(i8* %bar, i8** %ptr, i64 %inc) { define <8 x i8> @test_v8i8_post_imm_ld1r(i8* %bar, i8** %ptr) { ; CHECK-LABEL: test_v8i8_post_imm_ld1r: ; CHECK: ld1r.8b { v0 }, [x0], #1 - %tmp1 = load i8* %bar + %tmp1 = load i8, i8* %bar %tmp2 = insertelement <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0 %tmp3 = insertelement <8 x i8> %tmp2, i8 %tmp1, i32 1 %tmp4 = insertelement <8 x i8> %tmp3, i8 %tmp1, i32 2 @@ -5751,7 +5751,7 @@ define <8 x i8> @test_v8i8_post_imm_ld1r(i8* %bar, i8** %ptr) { %tmp7 = insertelement <8 x i8> %tmp6, i8 %tmp1, i32 5 %tmp8 = insertelement <8 x i8> %tmp7, i8 %tmp1, i32 6 %tmp9 = insertelement <8 x i8> %tmp8, i8 %tmp1, i32 7 - %tmp10 = getelementptr i8* %bar, i64 1 + %tmp10 = getelementptr i8, i8* %bar, i64 1 store i8* %tmp10, i8** %ptr ret <8 x i8> %tmp9 } @@ -5759,7 +5759,7 @@ define <8 x i8> @test_v8i8_post_imm_ld1r(i8* %bar, i8** %ptr) { define <8 x i8> @test_v8i8_post_reg_ld1r(i8* %bar, i8** %ptr, i64 %inc) { ; CHECK-LABEL: test_v8i8_post_reg_ld1r: ; CHECK: ld1r.8b { v0 }, [x0], x{{[0-9]+}} - %tmp1 = load i8* %bar + %tmp1 = load i8, i8* %bar %tmp2 = insertelement <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0 %tmp3 = insertelement <8 x i8> %tmp2, i8 %tmp1, i32 1 %tmp4 = insertelement <8 x i8> %tmp3, i8 %tmp1, i32 2 @@ -5768,7 +5768,7 @@ define <8 x i8> @test_v8i8_post_reg_ld1r(i8* %bar, i8** %ptr, i64 %inc) { %tmp7 = insertelement <8 x i8> %tmp6, i8 %tmp1, i32 5 %tmp8 = insertelement <8 x i8> %tmp7, i8 %tmp1, i32 6 %tmp9 = insertelement <8 x i8> %tmp8, i8 %tmp1, i32 7 - %tmp10 = getelementptr i8* %bar, i64 %inc + %tmp10 = getelementptr i8, i8* %bar, i64 %inc store i8* %tmp10, i8** %ptr ret <8 x i8> %tmp9 } @@ -5776,7 +5776,7 @@ define <8 x i8> @test_v8i8_post_reg_ld1r(i8* %bar, i8** %ptr, i64 %inc) { define <8 x i16> @test_v8i16_post_imm_ld1r(i16* %bar, i16** %ptr) { ; CHECK-LABEL: test_v8i16_post_imm_ld1r: ; CHECK: ld1r.8h { v0 }, [x0], #2 - %tmp1 = load i16* %bar + %tmp1 = load i16, i16* %bar %tmp2 = insertelement <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0 %tmp3 = insertelement <8 x i16> %tmp2, i16 %tmp1, i32 1 %tmp4 = insertelement <8 x i16> %tmp3, i16 %tmp1, i32 2 @@ -5785,7 +5785,7 @@ define <8 x i16> @test_v8i16_post_imm_ld1r(i16* %bar, i16** %ptr) { %tmp7 = insertelement <8 x i16> %tmp6, i16 %tmp1, i32 5 %tmp8 = insertelement <8 x i16> %tmp7, i16 %tmp1, i32 6 %tmp9 = insertelement <8 x i16> %tmp8, i16 %tmp1, i32 7 - %tmp10 = getelementptr i16* %bar, i64 1 + %tmp10 = getelementptr i16, i16* %bar, i64 1 store i16* %tmp10, i16** %ptr ret <8 x i16> %tmp9 } @@ -5793,7 +5793,7 @@ define <8 x i16> @test_v8i16_post_imm_ld1r(i16* %bar, i16** %ptr) { define <8 x i16> @test_v8i16_post_reg_ld1r(i16* %bar, i16** %ptr, i64 %inc) { ; CHECK-LABEL: test_v8i16_post_reg_ld1r: ; CHECK: ld1r.8h { v0 }, [x0], x{{[0-9]+}} - %tmp1 = load i16* %bar + %tmp1 = load i16, i16* %bar %tmp2 = insertelement <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0 %tmp3 = insertelement <8 x i16> %tmp2, i16 %tmp1, i32 1 %tmp4 = insertelement <8 x i16> %tmp3, i16 %tmp1, i32 2 @@ -5802,7 +5802,7 @@ define <8 x i16> @test_v8i16_post_reg_ld1r(i16* %bar, i16** %ptr, i64 %inc) { %tmp7 = insertelement <8 x i16> %tmp6, i16 %tmp1, i32 5 %tmp8 = insertelement <8 x i16> %tmp7, i16 %tmp1, i32 6 %tmp9 = insertelement <8 x i16> %tmp8, i16 %tmp1, i32 7 - %tmp10 = getelementptr i16* %bar, i64 %inc + %tmp10 = getelementptr i16, i16* %bar, i64 %inc store i16* %tmp10, i16** %ptr ret <8 x i16> %tmp9 } @@ -5810,12 +5810,12 @@ define <8 x i16> @test_v8i16_post_reg_ld1r(i16* %bar, i16** %ptr, i64 %inc) { define <4 x i16> @test_v4i16_post_imm_ld1r(i16* %bar, i16** %ptr) { ; CHECK-LABEL: test_v4i16_post_imm_ld1r: ; CHECK: ld1r.4h { v0 }, [x0], #2 - %tmp1 = load i16* %bar + %tmp1 = load i16, i16* %bar %tmp2 = insertelement <4 x i16> <i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0 %tmp3 = insertelement <4 x i16> %tmp2, i16 %tmp1, i32 1 %tmp4 = insertelement <4 x i16> %tmp3, i16 %tmp1, i32 2 %tmp5 = insertelement <4 x i16> %tmp4, i16 %tmp1, i32 3 - %tmp6 = getelementptr i16* %bar, i64 1 + %tmp6 = getelementptr i16, i16* %bar, i64 1 store i16* %tmp6, i16** %ptr ret <4 x i16> %tmp5 } @@ -5823,12 +5823,12 @@ define <4 x i16> @test_v4i16_post_imm_ld1r(i16* %bar, i16** %ptr) { define <4 x i16> @test_v4i16_post_reg_ld1r(i16* %bar, i16** %ptr, i64 %inc) { ; CHECK-LABEL: test_v4i16_post_reg_ld1r: ; CHECK: ld1r.4h { v0 }, [x0], x{{[0-9]+}} - %tmp1 = load i16* %bar + %tmp1 = load i16, i16* %bar %tmp2 = insertelement <4 x i16> <i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0 %tmp3 = insertelement <4 x i16> %tmp2, i16 %tmp1, i32 1 %tmp4 = insertelement <4 x i16> %tmp3, i16 %tmp1, i32 2 %tmp5 = insertelement <4 x i16> %tmp4, i16 %tmp1, i32 3 - %tmp6 = getelementptr i16* %bar, i64 %inc + %tmp6 = getelementptr i16, i16* %bar, i64 %inc store i16* %tmp6, i16** %ptr ret <4 x i16> %tmp5 } @@ -5836,12 +5836,12 @@ define <4 x i16> @test_v4i16_post_reg_ld1r(i16* %bar, i16** %ptr, i64 %inc) { define <4 x i32> @test_v4i32_post_imm_ld1r(i32* %bar, i32** %ptr) { ; CHECK-LABEL: test_v4i32_post_imm_ld1r: ; CHECK: ld1r.4s { v0 }, [x0], #4 - %tmp1 = load i32* %bar + %tmp1 = load i32, i32* %bar %tmp2 = insertelement <4 x i32> <i32 undef, i32 undef, i32 undef, i32 undef>, i32 %tmp1, i32 0 %tmp3 = insertelement <4 x i32> %tmp2, i32 %tmp1, i32 1 %tmp4 = insertelement <4 x i32> %tmp3, i32 %tmp1, i32 2 %tmp5 = insertelement <4 x i32> %tmp4, i32 %tmp1, i32 3 - %tmp6 = getelementptr i32* %bar, i64 1 + %tmp6 = getelementptr i32, i32* %bar, i64 1 store i32* %tmp6, i32** %ptr ret <4 x i32> %tmp5 } @@ -5849,12 +5849,12 @@ define <4 x i32> @test_v4i32_post_imm_ld1r(i32* %bar, i32** %ptr) { define <4 x i32> @test_v4i32_post_reg_ld1r(i32* %bar, i32** %ptr, i64 %inc) { ; CHECK-LABEL: test_v4i32_post_reg_ld1r: ; CHECK: ld1r.4s { v0 }, [x0], x{{[0-9]+}} - %tmp1 = load i32* %bar + %tmp1 = load i32, i32* %bar %tmp2 = insertelement <4 x i32> <i32 undef, i32 undef, i32 undef, i32 undef>, i32 %tmp1, i32 0 %tmp3 = insertelement <4 x i32> %tmp2, i32 %tmp1, i32 1 %tmp4 = insertelement <4 x i32> %tmp3, i32 %tmp1, i32 2 %tmp5 = insertelement <4 x i32> %tmp4, i32 %tmp1, i32 3 - %tmp6 = getelementptr i32* %bar, i64 %inc + %tmp6 = getelementptr i32, i32* %bar, i64 %inc store i32* %tmp6, i32** %ptr ret <4 x i32> %tmp5 } @@ -5862,10 +5862,10 @@ define <4 x i32> @test_v4i32_post_reg_ld1r(i32* %bar, i32** %ptr, i64 %inc) { define <2 x i32> @test_v2i32_post_imm_ld1r(i32* %bar, i32** %ptr) { ; CHECK-LABEL: test_v2i32_post_imm_ld1r: ; CHECK: ld1r.2s { v0 }, [x0], #4 - %tmp1 = load i32* %bar + %tmp1 = load i32, i32* %bar %tmp2 = insertelement <2 x i32> <i32 undef, i32 undef>, i32 %tmp1, i32 0 %tmp3 = insertelement <2 x i32> %tmp2, i32 %tmp1, i32 1 - %tmp4 = getelementptr i32* %bar, i64 1 + %tmp4 = getelementptr i32, i32* %bar, i64 1 store i32* %tmp4, i32** %ptr ret <2 x i32> %tmp3 } @@ -5873,10 +5873,10 @@ define <2 x i32> @test_v2i32_post_imm_ld1r(i32* %bar, i32** %ptr) { define <2 x i32> @test_v2i32_post_reg_ld1r(i32* %bar, i32** %ptr, i64 %inc) { ; CHECK-LABEL: test_v2i32_post_reg_ld1r: ; CHECK: ld1r.2s { v0 }, [x0], x{{[0-9]+}} - %tmp1 = load i32* %bar + %tmp1 = load i32, i32* %bar %tmp2 = insertelement <2 x i32> <i32 undef, i32 undef>, i32 %tmp1, i32 0 %tmp3 = insertelement <2 x i32> %tmp2, i32 %tmp1, i32 1 - %tmp4 = getelementptr i32* %bar, i64 %inc + %tmp4 = getelementptr i32, i32* %bar, i64 %inc store i32* %tmp4, i32** %ptr ret <2 x i32> %tmp3 } @@ -5884,10 +5884,10 @@ define <2 x i32> @test_v2i32_post_reg_ld1r(i32* %bar, i32** %ptr, i64 %inc) { define <2 x i64> @test_v2i64_post_imm_ld1r(i64* %bar, i64** %ptr) { ; CHECK-LABEL: test_v2i64_post_imm_ld1r: ; CHECK: ld1r.2d { v0 }, [x0], #8 - %tmp1 = load i64* %bar + %tmp1 = load i64, i64* %bar %tmp2 = insertelement <2 x i64> <i64 undef, i64 undef>, i64 %tmp1, i32 0 %tmp3 = insertelement <2 x i64> %tmp2, i64 %tmp1, i32 1 - %tmp4 = getelementptr i64* %bar, i64 1 + %tmp4 = getelementptr i64, i64* %bar, i64 1 store i64* %tmp4, i64** %ptr ret <2 x i64> %tmp3 } @@ -5895,10 +5895,10 @@ define <2 x i64> @test_v2i64_post_imm_ld1r(i64* %bar, i64** %ptr) { define <2 x i64> @test_v2i64_post_reg_ld1r(i64* %bar, i64** %ptr, i64 %inc) { ; CHECK-LABEL: test_v2i64_post_reg_ld1r: ; CHECK: ld1r.2d { v0 }, [x0], x{{[0-9]+}} - %tmp1 = load i64* %bar + %tmp1 = load i64, i64* %bar %tmp2 = insertelement <2 x i64> <i64 undef, i64 undef>, i64 %tmp1, i32 0 %tmp3 = insertelement <2 x i64> %tmp2, i64 %tmp1, i32 1 - %tmp4 = getelementptr i64* %bar, i64 %inc + %tmp4 = getelementptr i64, i64* %bar, i64 %inc store i64* %tmp4, i64** %ptr ret <2 x i64> %tmp3 } @@ -5906,12 +5906,12 @@ define <2 x i64> @test_v2i64_post_reg_ld1r(i64* %bar, i64** %ptr, i64 %inc) { define <4 x float> @test_v4f32_post_imm_ld1r(float* %bar, float** %ptr) { ; CHECK-LABEL: test_v4f32_post_imm_ld1r: ; CHECK: ld1r.4s { v0 }, [x0], #4 - %tmp1 = load float* %bar + %tmp1 = load float, float* %bar %tmp2 = insertelement <4 x float> <float undef, float undef, float undef, float undef>, float %tmp1, i32 0 %tmp3 = insertelement <4 x float> %tmp2, float %tmp1, i32 1 %tmp4 = insertelement <4 x float> %tmp3, float %tmp1, i32 2 %tmp5 = insertelement <4 x float> %tmp4, float %tmp1, i32 3 - %tmp6 = getelementptr float* %bar, i64 1 + %tmp6 = getelementptr float, float* %bar, i64 1 store float* %tmp6, float** %ptr ret <4 x float> %tmp5 } @@ -5919,12 +5919,12 @@ define <4 x float> @test_v4f32_post_imm_ld1r(float* %bar, float** %ptr) { define <4 x float> @test_v4f32_post_reg_ld1r(float* %bar, float** %ptr, i64 %inc) { ; CHECK-LABEL: test_v4f32_post_reg_ld1r: ; CHECK: ld1r.4s { v0 }, [x0], x{{[0-9]+}} - %tmp1 = load float* %bar + %tmp1 = load float, float* %bar %tmp2 = insertelement <4 x float> <float undef, float undef, float undef, float undef>, float %tmp1, i32 0 %tmp3 = insertelement <4 x float> %tmp2, float %tmp1, i32 1 %tmp4 = insertelement <4 x float> %tmp3, float %tmp1, i32 2 %tmp5 = insertelement <4 x float> %tmp4, float %tmp1, i32 3 - %tmp6 = getelementptr float* %bar, i64 %inc + %tmp6 = getelementptr float, float* %bar, i64 %inc store float* %tmp6, float** %ptr ret <4 x float> %tmp5 } @@ -5932,10 +5932,10 @@ define <4 x float> @test_v4f32_post_reg_ld1r(float* %bar, float** %ptr, i64 %inc define <2 x float> @test_v2f32_post_imm_ld1r(float* %bar, float** %ptr) { ; CHECK-LABEL: test_v2f32_post_imm_ld1r: ; CHECK: ld1r.2s { v0 }, [x0], #4 - %tmp1 = load float* %bar + %tmp1 = load float, float* %bar %tmp2 = insertelement <2 x float> <float undef, float undef>, float %tmp1, i32 0 %tmp3 = insertelement <2 x float> %tmp2, float %tmp1, i32 1 - %tmp4 = getelementptr float* %bar, i64 1 + %tmp4 = getelementptr float, float* %bar, i64 1 store float* %tmp4, float** %ptr ret <2 x float> %tmp3 } @@ -5943,10 +5943,10 @@ define <2 x float> @test_v2f32_post_imm_ld1r(float* %bar, float** %ptr) { define <2 x float> @test_v2f32_post_reg_ld1r(float* %bar, float** %ptr, i64 %inc) { ; CHECK-LABEL: test_v2f32_post_reg_ld1r: ; CHECK: ld1r.2s { v0 }, [x0], x{{[0-9]+}} - %tmp1 = load float* %bar + %tmp1 = load float, float* %bar %tmp2 = insertelement <2 x float> <float undef, float undef>, float %tmp1, i32 0 %tmp3 = insertelement <2 x float> %tmp2, float %tmp1, i32 1 - %tmp4 = getelementptr float* %bar, i64 %inc + %tmp4 = getelementptr float, float* %bar, i64 %inc store float* %tmp4, float** %ptr ret <2 x float> %tmp3 } @@ -5954,10 +5954,10 @@ define <2 x float> @test_v2f32_post_reg_ld1r(float* %bar, float** %ptr, i64 %inc define <2 x double> @test_v2f64_post_imm_ld1r(double* %bar, double** %ptr) { ; CHECK-LABEL: test_v2f64_post_imm_ld1r: ; CHECK: ld1r.2d { v0 }, [x0], #8 - %tmp1 = load double* %bar + %tmp1 = load double, double* %bar %tmp2 = insertelement <2 x double> <double undef, double undef>, double %tmp1, i32 0 %tmp3 = insertelement <2 x double> %tmp2, double %tmp1, i32 1 - %tmp4 = getelementptr double* %bar, i64 1 + %tmp4 = getelementptr double, double* %bar, i64 1 store double* %tmp4, double** %ptr ret <2 x double> %tmp3 } @@ -5965,10 +5965,10 @@ define <2 x double> @test_v2f64_post_imm_ld1r(double* %bar, double** %ptr) { define <2 x double> @test_v2f64_post_reg_ld1r(double* %bar, double** %ptr, i64 %inc) { ; CHECK-LABEL: test_v2f64_post_reg_ld1r: ; CHECK: ld1r.2d { v0 }, [x0], x{{[0-9]+}} - %tmp1 = load double* %bar + %tmp1 = load double, double* %bar %tmp2 = insertelement <2 x double> <double undef, double undef>, double %tmp1, i32 0 %tmp3 = insertelement <2 x double> %tmp2, double %tmp1, i32 1 - %tmp4 = getelementptr double* %bar, i64 %inc + %tmp4 = getelementptr double, double* %bar, i64 %inc store double* %tmp4, double** %ptr ret <2 x double> %tmp3 } @@ -5976,9 +5976,9 @@ define <2 x double> @test_v2f64_post_reg_ld1r(double* %bar, double** %ptr, i64 % define <16 x i8> @test_v16i8_post_imm_ld1lane(i8* %bar, i8** %ptr, <16 x i8> %A) { ; CHECK-LABEL: test_v16i8_post_imm_ld1lane: ; CHECK: ld1.b { v0 }[1], [x0], #1 - %tmp1 = load i8* %bar + %tmp1 = load i8, i8* %bar %tmp2 = insertelement <16 x i8> %A, i8 %tmp1, i32 1 - %tmp3 = getelementptr i8* %bar, i64 1 + %tmp3 = getelementptr i8, i8* %bar, i64 1 store i8* %tmp3, i8** %ptr ret <16 x i8> %tmp2 } @@ -5986,9 +5986,9 @@ define <16 x i8> @test_v16i8_post_imm_ld1lane(i8* %bar, i8** %ptr, <16 x i8> %A) define <16 x i8> @test_v16i8_post_reg_ld1lane(i8* %bar, i8** %ptr, i64 %inc, <16 x i8> %A) { ; CHECK-LABEL: test_v16i8_post_reg_ld1lane: ; CHECK: ld1.b { v0 }[1], [x0], x{{[0-9]+}} - %tmp1 = load i8* %bar + %tmp1 = load i8, i8* %bar %tmp2 = insertelement <16 x i8> %A, i8 %tmp1, i32 1 - %tmp3 = getelementptr i8* %bar, i64 %inc + %tmp3 = getelementptr i8, i8* %bar, i64 %inc store i8* %tmp3, i8** %ptr ret <16 x i8> %tmp2 } @@ -5996,9 +5996,9 @@ define <16 x i8> @test_v16i8_post_reg_ld1lane(i8* %bar, i8** %ptr, i64 %inc, <16 define <8 x i8> @test_v8i8_post_imm_ld1lane(i8* %bar, i8** %ptr, <8 x i8> %A) { ; CHECK-LABEL: test_v8i8_post_imm_ld1lane: ; CHECK: ld1.b { v0 }[1], [x0], #1 - %tmp1 = load i8* %bar + %tmp1 = load i8, i8* %bar %tmp2 = insertelement <8 x i8> %A, i8 %tmp1, i32 1 - %tmp3 = getelementptr i8* %bar, i64 1 + %tmp3 = getelementptr i8, i8* %bar, i64 1 store i8* %tmp3, i8** %ptr ret <8 x i8> %tmp2 } @@ -6006,9 +6006,9 @@ define <8 x i8> @test_v8i8_post_imm_ld1lane(i8* %bar, i8** %ptr, <8 x i8> %A) { define <8 x i8> @test_v8i8_post_reg_ld1lane(i8* %bar, i8** %ptr, i64 %inc, <8 x i8> %A) { ; CHECK-LABEL: test_v8i8_post_reg_ld1lane: ; CHECK: ld1.b { v0 }[1], [x0], x{{[0-9]+}} - %tmp1 = load i8* %bar + %tmp1 = load i8, i8* %bar %tmp2 = insertelement <8 x i8> %A, i8 %tmp1, i32 1 - %tmp3 = getelementptr i8* %bar, i64 %inc + %tmp3 = getelementptr i8, i8* %bar, i64 %inc store i8* %tmp3, i8** %ptr ret <8 x i8> %tmp2 } @@ -6016,9 +6016,9 @@ define <8 x i8> @test_v8i8_post_reg_ld1lane(i8* %bar, i8** %ptr, i64 %inc, <8 x define <8 x i16> @test_v8i16_post_imm_ld1lane(i16* %bar, i16** %ptr, <8 x i16> %A) { ; CHECK-LABEL: test_v8i16_post_imm_ld1lane: ; CHECK: ld1.h { v0 }[1], [x0], #2 - %tmp1 = load i16* %bar + %tmp1 = load i16, i16* %bar %tmp2 = insertelement <8 x i16> %A, i16 %tmp1, i32 1 - %tmp3 = getelementptr i16* %bar, i64 1 + %tmp3 = getelementptr i16, i16* %bar, i64 1 store i16* %tmp3, i16** %ptr ret <8 x i16> %tmp2 } @@ -6026,9 +6026,9 @@ define <8 x i16> @test_v8i16_post_imm_ld1lane(i16* %bar, i16** %ptr, <8 x i16> % define <8 x i16> @test_v8i16_post_reg_ld1lane(i16* %bar, i16** %ptr, i64 %inc, <8 x i16> %A) { ; CHECK-LABEL: test_v8i16_post_reg_ld1lane: ; CHECK: ld1.h { v0 }[1], [x0], x{{[0-9]+}} - %tmp1 = load i16* %bar + %tmp1 = load i16, i16* %bar %tmp2 = insertelement <8 x i16> %A, i16 %tmp1, i32 1 - %tmp3 = getelementptr i16* %bar, i64 %inc + %tmp3 = getelementptr i16, i16* %bar, i64 %inc store i16* %tmp3, i16** %ptr ret <8 x i16> %tmp2 } @@ -6036,9 +6036,9 @@ define <8 x i16> @test_v8i16_post_reg_ld1lane(i16* %bar, i16** %ptr, i64 %inc, < define <4 x i16> @test_v4i16_post_imm_ld1lane(i16* %bar, i16** %ptr, <4 x i16> %A) { ; CHECK-LABEL: test_v4i16_post_imm_ld1lane: ; CHECK: ld1.h { v0 }[1], [x0], #2 - %tmp1 = load i16* %bar + %tmp1 = load i16, i16* %bar %tmp2 = insertelement <4 x i16> %A, i16 %tmp1, i32 1 - %tmp3 = getelementptr i16* %bar, i64 1 + %tmp3 = getelementptr i16, i16* %bar, i64 1 store i16* %tmp3, i16** %ptr ret <4 x i16> %tmp2 } @@ -6046,9 +6046,9 @@ define <4 x i16> @test_v4i16_post_imm_ld1lane(i16* %bar, i16** %ptr, <4 x i16> % define <4 x i16> @test_v4i16_post_reg_ld1lane(i16* %bar, i16** %ptr, i64 %inc, <4 x i16> %A) { ; CHECK-LABEL: test_v4i16_post_reg_ld1lane: ; CHECK: ld1.h { v0 }[1], [x0], x{{[0-9]+}} - %tmp1 = load i16* %bar + %tmp1 = load i16, i16* %bar %tmp2 = insertelement <4 x i16> %A, i16 %tmp1, i32 1 - %tmp3 = getelementptr i16* %bar, i64 %inc + %tmp3 = getelementptr i16, i16* %bar, i64 %inc store i16* %tmp3, i16** %ptr ret <4 x i16> %tmp2 } @@ -6056,9 +6056,9 @@ define <4 x i16> @test_v4i16_post_reg_ld1lane(i16* %bar, i16** %ptr, i64 %inc, < define <4 x i32> @test_v4i32_post_imm_ld1lane(i32* %bar, i32** %ptr, <4 x i32> %A) { ; CHECK-LABEL: test_v4i32_post_imm_ld1lane: ; CHECK: ld1.s { v0 }[1], [x0], #4 - %tmp1 = load i32* %bar + %tmp1 = load i32, i32* %bar %tmp2 = insertelement <4 x i32> %A, i32 %tmp1, i32 1 - %tmp3 = getelementptr i32* %bar, i64 1 + %tmp3 = getelementptr i32, i32* %bar, i64 1 store i32* %tmp3, i32** %ptr ret <4 x i32> %tmp2 } @@ -6066,9 +6066,9 @@ define <4 x i32> @test_v4i32_post_imm_ld1lane(i32* %bar, i32** %ptr, <4 x i32> % define <4 x i32> @test_v4i32_post_reg_ld1lane(i32* %bar, i32** %ptr, i64 %inc, <4 x i32> %A) { ; CHECK-LABEL: test_v4i32_post_reg_ld1lane: ; CHECK: ld1.s { v0 }[1], [x0], x{{[0-9]+}} - %tmp1 = load i32* %bar + %tmp1 = load i32, i32* %bar %tmp2 = insertelement <4 x i32> %A, i32 %tmp1, i32 1 - %tmp3 = getelementptr i32* %bar, i64 %inc + %tmp3 = getelementptr i32, i32* %bar, i64 %inc store i32* %tmp3, i32** %ptr ret <4 x i32> %tmp2 } @@ -6076,9 +6076,9 @@ define <4 x i32> @test_v4i32_post_reg_ld1lane(i32* %bar, i32** %ptr, i64 %inc, < define <2 x i32> @test_v2i32_post_imm_ld1lane(i32* %bar, i32** %ptr, <2 x i32> %A) { ; CHECK-LABEL: test_v2i32_post_imm_ld1lane: ; CHECK: ld1.s { v0 }[1], [x0], #4 - %tmp1 = load i32* %bar + %tmp1 = load i32, i32* %bar %tmp2 = insertelement <2 x i32> %A, i32 %tmp1, i32 1 - %tmp3 = getelementptr i32* %bar, i64 1 + %tmp3 = getelementptr i32, i32* %bar, i64 1 store i32* %tmp3, i32** %ptr ret <2 x i32> %tmp2 } @@ -6086,9 +6086,9 @@ define <2 x i32> @test_v2i32_post_imm_ld1lane(i32* %bar, i32** %ptr, <2 x i32> % define <2 x i32> @test_v2i32_post_reg_ld1lane(i32* %bar, i32** %ptr, i64 %inc, <2 x i32> %A) { ; CHECK-LABEL: test_v2i32_post_reg_ld1lane: ; CHECK: ld1.s { v0 }[1], [x0], x{{[0-9]+}} - %tmp1 = load i32* %bar + %tmp1 = load i32, i32* %bar %tmp2 = insertelement <2 x i32> %A, i32 %tmp1, i32 1 - %tmp3 = getelementptr i32* %bar, i64 %inc + %tmp3 = getelementptr i32, i32* %bar, i64 %inc store i32* %tmp3, i32** %ptr ret <2 x i32> %tmp2 } @@ -6096,9 +6096,9 @@ define <2 x i32> @test_v2i32_post_reg_ld1lane(i32* %bar, i32** %ptr, i64 %inc, < define <2 x i64> @test_v2i64_post_imm_ld1lane(i64* %bar, i64** %ptr, <2 x i64> %A) { ; CHECK-LABEL: test_v2i64_post_imm_ld1lane: ; CHECK: ld1.d { v0 }[1], [x0], #8 - %tmp1 = load i64* %bar + %tmp1 = load i64, i64* %bar %tmp2 = insertelement <2 x i64> %A, i64 %tmp1, i32 1 - %tmp3 = getelementptr i64* %bar, i64 1 + %tmp3 = getelementptr i64, i64* %bar, i64 1 store i64* %tmp3, i64** %ptr ret <2 x i64> %tmp2 } @@ -6106,9 +6106,9 @@ define <2 x i64> @test_v2i64_post_imm_ld1lane(i64* %bar, i64** %ptr, <2 x i64> % define <2 x i64> @test_v2i64_post_reg_ld1lane(i64* %bar, i64** %ptr, i64 %inc, <2 x i64> %A) { ; CHECK-LABEL: test_v2i64_post_reg_ld1lane: ; CHECK: ld1.d { v0 }[1], [x0], x{{[0-9]+}} - %tmp1 = load i64* %bar + %tmp1 = load i64, i64* %bar %tmp2 = insertelement <2 x i64> %A, i64 %tmp1, i32 1 - %tmp3 = getelementptr i64* %bar, i64 %inc + %tmp3 = getelementptr i64, i64* %bar, i64 %inc store i64* %tmp3, i64** %ptr ret <2 x i64> %tmp2 } @@ -6116,9 +6116,9 @@ define <2 x i64> @test_v2i64_post_reg_ld1lane(i64* %bar, i64** %ptr, i64 %inc, < define <4 x float> @test_v4f32_post_imm_ld1lane(float* %bar, float** %ptr, <4 x float> %A) { ; CHECK-LABEL: test_v4f32_post_imm_ld1lane: ; CHECK: ld1.s { v0 }[1], [x0], #4 - %tmp1 = load float* %bar + %tmp1 = load float, float* %bar %tmp2 = insertelement <4 x float> %A, float %tmp1, i32 1 - %tmp3 = getelementptr float* %bar, i64 1 + %tmp3 = getelementptr float, float* %bar, i64 1 store float* %tmp3, float** %ptr ret <4 x float> %tmp2 } @@ -6126,9 +6126,9 @@ define <4 x float> @test_v4f32_post_imm_ld1lane(float* %bar, float** %ptr, <4 x define <4 x float> @test_v4f32_post_reg_ld1lane(float* %bar, float** %ptr, i64 %inc, <4 x float> %A) { ; CHECK-LABEL: test_v4f32_post_reg_ld1lane: ; CHECK: ld1.s { v0 }[1], [x0], x{{[0-9]+}} - %tmp1 = load float* %bar + %tmp1 = load float, float* %bar %tmp2 = insertelement <4 x float> %A, float %tmp1, i32 1 - %tmp3 = getelementptr float* %bar, i64 %inc + %tmp3 = getelementptr float, float* %bar, i64 %inc store float* %tmp3, float** %ptr ret <4 x float> %tmp2 } @@ -6136,9 +6136,9 @@ define <4 x float> @test_v4f32_post_reg_ld1lane(float* %bar, float** %ptr, i64 % define <2 x float> @test_v2f32_post_imm_ld1lane(float* %bar, float** %ptr, <2 x float> %A) { ; CHECK-LABEL: test_v2f32_post_imm_ld1lane: ; CHECK: ld1.s { v0 }[1], [x0], #4 - %tmp1 = load float* %bar + %tmp1 = load float, float* %bar %tmp2 = insertelement <2 x float> %A, float %tmp1, i32 1 - %tmp3 = getelementptr float* %bar, i64 1 + %tmp3 = getelementptr float, float* %bar, i64 1 store float* %tmp3, float** %ptr ret <2 x float> %tmp2 } @@ -6146,9 +6146,9 @@ define <2 x float> @test_v2f32_post_imm_ld1lane(float* %bar, float** %ptr, <2 x define <2 x float> @test_v2f32_post_reg_ld1lane(float* %bar, float** %ptr, i64 %inc, <2 x float> %A) { ; CHECK-LABEL: test_v2f32_post_reg_ld1lane: ; CHECK: ld1.s { v0 }[1], [x0], x{{[0-9]+}} - %tmp1 = load float* %bar + %tmp1 = load float, float* %bar %tmp2 = insertelement <2 x float> %A, float %tmp1, i32 1 - %tmp3 = getelementptr float* %bar, i64 %inc + %tmp3 = getelementptr float, float* %bar, i64 %inc store float* %tmp3, float** %ptr ret <2 x float> %tmp2 } @@ -6156,9 +6156,9 @@ define <2 x float> @test_v2f32_post_reg_ld1lane(float* %bar, float** %ptr, i64 % define <2 x double> @test_v2f64_post_imm_ld1lane(double* %bar, double** %ptr, <2 x double> %A) { ; CHECK-LABEL: test_v2f64_post_imm_ld1lane: ; CHECK: ld1.d { v0 }[1], [x0], #8 - %tmp1 = load double* %bar + %tmp1 = load double, double* %bar %tmp2 = insertelement <2 x double> %A, double %tmp1, i32 1 - %tmp3 = getelementptr double* %bar, i64 1 + %tmp3 = getelementptr double, double* %bar, i64 1 store double* %tmp3, double** %ptr ret <2 x double> %tmp2 } @@ -6166,9 +6166,9 @@ define <2 x double> @test_v2f64_post_imm_ld1lane(double* %bar, double** %ptr, <2 define <2 x double> @test_v2f64_post_reg_ld1lane(double* %bar, double** %ptr, i64 %inc, <2 x double> %A) { ; CHECK-LABEL: test_v2f64_post_reg_ld1lane: ; CHECK: ld1.d { v0 }[1], [x0], x{{[0-9]+}} - %tmp1 = load double* %bar + %tmp1 = load double, double* %bar %tmp2 = insertelement <2 x double> %A, double %tmp1, i32 1 - %tmp3 = getelementptr double* %bar, i64 %inc + %tmp3 = getelementptr double, double* %bar, i64 %inc store double* %tmp3, double** %ptr ret <2 x double> %tmp2 }
\ No newline at end of file diff --git a/test/CodeGen/AArch64/arm64-inline-asm.ll b/test/CodeGen/AArch64/arm64-inline-asm.ll index 9c8bcaa..802d958 100644 --- a/test/CodeGen/AArch64/arm64-inline-asm.ll +++ b/test/CodeGen/AArch64/arm64-inline-asm.ll @@ -125,7 +125,7 @@ define void @t9() nounwind { entry: ; CHECK-LABEL: t9: %data = alloca <2 x double>, align 16 - %0 = load <2 x double>* %data, align 16 + %0 = load <2 x double>, <2 x double>* %data, align 16 call void asm sideeffect "mov.2d v4, $0\0A", "w,~{v4}"(<2 x double> %0) nounwind ; CHECK: mov.2d v4, {{v[0-9]+}} ret void @@ -136,8 +136,8 @@ entry: ; CHECK-LABEL: t10: %data = alloca <2 x float>, align 8 %a = alloca [2 x float], align 4 - %arraydecay = getelementptr inbounds [2 x float]* %a, i32 0, i32 0 - %0 = load <2 x float>* %data, align 8 + %arraydecay = getelementptr inbounds [2 x float], [2 x float]* %a, i32 0, i32 0 + %0 = load <2 x float>, <2 x float>* %data, align 8 call void asm sideeffect "ldr ${1:q}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}] call void asm sideeffect "ldr ${1:d}, [$0]\0A", "r,w"(float* %arraydecay, <2 x float> %0) nounwind @@ -155,10 +155,10 @@ define void @t11() nounwind { entry: ; CHECK-LABEL: t11: %a = alloca i32, align 4 - %0 = load i32* %a, align 4 + %0 = load i32, i32* %a, align 4 call void asm sideeffect "mov ${1:x}, ${0:x}\0A", "r,i"(i32 %0, i32 0) nounwind ; CHECK: mov xzr, {{x[0-9]+}} - %1 = load i32* %a, align 4 + %1 = load i32, i32* %a, align 4 call void asm sideeffect "mov ${1:w}, ${0:w}\0A", "r,i"(i32 %1, i32 0) nounwind ; CHECK: mov wzr, {{w[0-9]+}} ret void @@ -168,9 +168,9 @@ define void @t12() nounwind { entry: ; CHECK-LABEL: t12: %data = alloca <4 x float>, align 16 - %0 = load <4 x float>* %data, align 16 + %0 = load <4 x float>, <4 x float>* %data, align 16 call void asm sideeffect "mov.2d v4, $0\0A", "x,~{v4}"(<4 x float> %0) nounwind - ; CHECK mov.2d v4, {{v([0-9])|(1[0-5])}} + ; CHECK: mov.2d v4, {{v([0-9])|(1[0-5])}} ret void } diff --git a/test/CodeGen/AArch64/arm64-large-frame.ll b/test/CodeGen/AArch64/arm64-large-frame.ll index 5a53da6..c4cce36 100644 --- a/test/CodeGen/AArch64/arm64-large-frame.ll +++ b/test/CodeGen/AArch64/arm64-large-frame.ll @@ -23,7 +23,7 @@ define void @test_bigframe() { ; CHECK: add {{x[0-9]+}}, [[TMP1]], #3344 store volatile i8* %var1, i8** @addr - %var1plus2 = getelementptr i8* %var1, i32 2 + %var1plus2 = getelementptr i8, i8* %var1, i32 2 store volatile i8* %var1plus2, i8** @addr ; CHECK: add [[TMP:x[0-9]+]], sp, #4095, lsl #12 @@ -31,12 +31,12 @@ define void @test_bigframe() { ; CHECK: add {{x[0-9]+}}, [[TMP1]], #3328 store volatile i8* %var2, i8** @addr - %var2plus2 = getelementptr i8* %var2, i32 2 + %var2plus2 = getelementptr i8, i8* %var2, i32 2 store volatile i8* %var2plus2, i8** @addr store volatile i8* %var3, i8** @addr - %var3plus2 = getelementptr i8* %var3, i32 2 + %var3plus2 = getelementptr i8, i8* %var3, i32 2 store volatile i8* %var3plus2, i8** @addr ; CHECK: add sp, sp, #4095, lsl #12 diff --git a/test/CodeGen/AArch64/arm64-ld1.ll b/test/CodeGen/AArch64/arm64-ld1.ll index 72d808c..a83a270 100644 --- a/test/CodeGen/AArch64/arm64-ld1.ll +++ b/test/CodeGen/AArch64/arm64-ld1.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -verify-machineinstrs -asm-verbose=false | FileCheck %s %struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> } %struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> } @@ -8,8 +8,8 @@ define %struct.__neon_int8x8x2_t @ld2_8b(i8* %A) nounwind { ; CHECK-LABEL: ld2_8b ; Make sure we are loading into the results defined by the ABI (i.e., v0, v1) ; and from the argument of the function also defined by ABI (i.e., x0) -; CHECK ld2.8b { v0, v1 }, [x0] -; CHECK-NEXT ret +; CHECK: ld2.8b { v0, v1 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int8x8x2_t @llvm.aarch64.neon.ld2.v8i8.p0i8(i8* %A) ret %struct.__neon_int8x8x2_t %tmp2 } @@ -17,8 +17,8 @@ define %struct.__neon_int8x8x2_t @ld2_8b(i8* %A) nounwind { define %struct.__neon_int8x8x3_t @ld3_8b(i8* %A) nounwind { ; CHECK-LABEL: ld3_8b ; Make sure we are using the operands defined by the ABI -; CHECK ld3.8b { v0, v1, v2 }, [x0] -; CHECK-NEXT ret +; CHECK: ld3.8b { v0, v1, v2 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int8x8x3_t @llvm.aarch64.neon.ld3.v8i8.p0i8(i8* %A) ret %struct.__neon_int8x8x3_t %tmp2 } @@ -26,8 +26,8 @@ define %struct.__neon_int8x8x3_t @ld3_8b(i8* %A) nounwind { define %struct.__neon_int8x8x4_t @ld4_8b(i8* %A) nounwind { ; CHECK-LABEL: ld4_8b ; Make sure we are using the operands defined by the ABI -; CHECK ld4.8b { v0, v1, v2, v3 }, [x0] -; CHECK-NEXT ret +; CHECK: ld4.8b { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int8x8x4_t @llvm.aarch64.neon.ld4.v8i8.p0i8(i8* %A) ret %struct.__neon_int8x8x4_t %tmp2 } @@ -43,8 +43,8 @@ declare %struct.__neon_int8x8x4_t @llvm.aarch64.neon.ld4.v8i8.p0i8(i8*) nounwind define %struct.__neon_int8x16x2_t @ld2_16b(i8* %A) nounwind { ; CHECK-LABEL: ld2_16b ; Make sure we are using the operands defined by the ABI -; CHECK ld2.16b { v0, v1 }, [x0] -; CHECK-NEXT ret +; CHECK: ld2.16b { v0, v1 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int8x16x2_t @llvm.aarch64.neon.ld2.v16i8.p0i8(i8* %A) ret %struct.__neon_int8x16x2_t %tmp2 } @@ -52,8 +52,8 @@ define %struct.__neon_int8x16x2_t @ld2_16b(i8* %A) nounwind { define %struct.__neon_int8x16x3_t @ld3_16b(i8* %A) nounwind { ; CHECK-LABEL: ld3_16b ; Make sure we are using the operands defined by the ABI -; CHECK ld3.16b { v0, v1, v2 }, [x0] -; CHECK-NEXT ret +; CHECK: ld3.16b { v0, v1, v2 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int8x16x3_t @llvm.aarch64.neon.ld3.v16i8.p0i8(i8* %A) ret %struct.__neon_int8x16x3_t %tmp2 } @@ -61,8 +61,8 @@ define %struct.__neon_int8x16x3_t @ld3_16b(i8* %A) nounwind { define %struct.__neon_int8x16x4_t @ld4_16b(i8* %A) nounwind { ; CHECK-LABEL: ld4_16b ; Make sure we are using the operands defined by the ABI -; CHECK ld4.16b { v0, v1, v2, v3 }, [x0] -; CHECK-NEXT ret +; CHECK: ld4.16b { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4.v16i8.p0i8(i8* %A) ret %struct.__neon_int8x16x4_t %tmp2 } @@ -78,8 +78,8 @@ declare %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4.v16i8.p0i8(i8*) nounwi define %struct.__neon_int16x4x2_t @ld2_4h(i16* %A) nounwind { ; CHECK-LABEL: ld2_4h ; Make sure we are using the operands defined by the ABI -; CHECK ld2.4h { v0, v1 }, [x0] -; CHECK-NEXT ret +; CHECK: ld2.4h { v0, v1 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int16x4x2_t @llvm.aarch64.neon.ld2.v4i16.p0i16(i16* %A) ret %struct.__neon_int16x4x2_t %tmp2 } @@ -87,8 +87,8 @@ define %struct.__neon_int16x4x2_t @ld2_4h(i16* %A) nounwind { define %struct.__neon_int16x4x3_t @ld3_4h(i16* %A) nounwind { ; CHECK-LABEL: ld3_4h ; Make sure we are using the operands defined by the ABI -; CHECK ld3.4h { v0, v1, v2 }, [x0] -; CHECK-NEXT ret +; CHECK: ld3.4h { v0, v1, v2 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int16x4x3_t @llvm.aarch64.neon.ld3.v4i16.p0i16(i16* %A) ret %struct.__neon_int16x4x3_t %tmp2 } @@ -96,8 +96,8 @@ define %struct.__neon_int16x4x3_t @ld3_4h(i16* %A) nounwind { define %struct.__neon_int16x4x4_t @ld4_4h(i16* %A) nounwind { ; CHECK-LABEL: ld4_4h ; Make sure we are using the operands defined by the ABI -; CHECK ld4.4h { v0, v1, v2, v3 }, [x0] -; CHECK-NEXT ret +; CHECK: ld4.4h { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int16x4x4_t @llvm.aarch64.neon.ld4.v4i16.p0i16(i16* %A) ret %struct.__neon_int16x4x4_t %tmp2 } @@ -113,8 +113,8 @@ declare %struct.__neon_int16x4x4_t @llvm.aarch64.neon.ld4.v4i16.p0i16(i16*) noun define %struct.__neon_int16x8x2_t @ld2_8h(i16* %A) nounwind { ; CHECK-LABEL: ld2_8h ; Make sure we are using the operands defined by the ABI -; CHECK ld2.8h { v0, v1 }, [x0] -; CHECK-NEXT ret +; CHECK: ld2.8h { v0, v1 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int16x8x2_t @llvm.aarch64.neon.ld2.v8i16.p0i16(i16* %A) ret %struct.__neon_int16x8x2_t %tmp2 } @@ -122,8 +122,8 @@ define %struct.__neon_int16x8x2_t @ld2_8h(i16* %A) nounwind { define %struct.__neon_int16x8x3_t @ld3_8h(i16* %A) nounwind { ; CHECK-LABEL: ld3_8h ; Make sure we are using the operands defined by the ABI -; CHECK ld3.8h { v0, v1, v2 }, [x0] -; CHECK-NEXT ret +; CHECK: ld3.8h { v0, v1, v2 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int16x8x3_t @llvm.aarch64.neon.ld3.v8i16.p0i16(i16* %A) ret %struct.__neon_int16x8x3_t %tmp2 } @@ -131,8 +131,8 @@ define %struct.__neon_int16x8x3_t @ld3_8h(i16* %A) nounwind { define %struct.__neon_int16x8x4_t @ld4_8h(i16* %A) nounwind { ; CHECK-LABEL: ld4_8h ; Make sure we are using the operands defined by the ABI -; CHECK ld4.8h { v0, v1, v2, v3 }, [x0] -; CHECK-NEXT ret +; CHECK: ld4.8h { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int16x8x4_t @llvm.aarch64.neon.ld4.v8i16.p0i16(i16* %A) ret %struct.__neon_int16x8x4_t %tmp2 } @@ -148,8 +148,8 @@ declare %struct.__neon_int16x8x4_t @llvm.aarch64.neon.ld4.v8i16.p0i16(i16*) noun define %struct.__neon_int32x2x2_t @ld2_2s(i32* %A) nounwind { ; CHECK-LABEL: ld2_2s ; Make sure we are using the operands defined by the ABI -; CHECK ld2.2s { v0, v1 }, [x0] -; CHECK-NEXT ret +; CHECK: ld2.2s { v0, v1 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int32x2x2_t @llvm.aarch64.neon.ld2.v2i32.p0i32(i32* %A) ret %struct.__neon_int32x2x2_t %tmp2 } @@ -157,8 +157,8 @@ define %struct.__neon_int32x2x2_t @ld2_2s(i32* %A) nounwind { define %struct.__neon_int32x2x3_t @ld3_2s(i32* %A) nounwind { ; CHECK-LABEL: ld3_2s ; Make sure we are using the operands defined by the ABI -; CHECK ld3.2s { v0, v1, v2 }, [x0] -; CHECK-NEXT ret +; CHECK: ld3.2s { v0, v1, v2 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int32x2x3_t @llvm.aarch64.neon.ld3.v2i32.p0i32(i32* %A) ret %struct.__neon_int32x2x3_t %tmp2 } @@ -166,8 +166,8 @@ define %struct.__neon_int32x2x3_t @ld3_2s(i32* %A) nounwind { define %struct.__neon_int32x2x4_t @ld4_2s(i32* %A) nounwind { ; CHECK-LABEL: ld4_2s ; Make sure we are using the operands defined by the ABI -; CHECK ld4.2s { v0, v1, v2, v3 }, [x0] -; CHECK-NEXT ret +; CHECK: ld4.2s { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int32x2x4_t @llvm.aarch64.neon.ld4.v2i32.p0i32(i32* %A) ret %struct.__neon_int32x2x4_t %tmp2 } @@ -183,8 +183,8 @@ declare %struct.__neon_int32x2x4_t @llvm.aarch64.neon.ld4.v2i32.p0i32(i32*) noun define %struct.__neon_int32x4x2_t @ld2_4s(i32* %A) nounwind { ; CHECK-LABEL: ld2_4s ; Make sure we are using the operands defined by the ABI -; CHECK ld2.4s { v0, v1 }, [x0] -; CHECK-NEXT ret +; CHECK: ld2.4s { v0, v1 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int32x4x2_t @llvm.aarch64.neon.ld2.v4i32.p0i32(i32* %A) ret %struct.__neon_int32x4x2_t %tmp2 } @@ -192,8 +192,8 @@ define %struct.__neon_int32x4x2_t @ld2_4s(i32* %A) nounwind { define %struct.__neon_int32x4x3_t @ld3_4s(i32* %A) nounwind { ; CHECK-LABEL: ld3_4s ; Make sure we are using the operands defined by the ABI -; CHECK ld3.4s { v0, v1, v2 }, [x0] -; CHECK-NEXT ret +; CHECK: ld3.4s { v0, v1, v2 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int32x4x3_t @llvm.aarch64.neon.ld3.v4i32.p0i32(i32* %A) ret %struct.__neon_int32x4x3_t %tmp2 } @@ -201,8 +201,8 @@ define %struct.__neon_int32x4x3_t @ld3_4s(i32* %A) nounwind { define %struct.__neon_int32x4x4_t @ld4_4s(i32* %A) nounwind { ; CHECK-LABEL: ld4_4s ; Make sure we are using the operands defined by the ABI -; CHECK ld4.4s { v0, v1, v2, v3 }, [x0] -; CHECK-NEXT ret +; CHECK: ld4.4s { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int32x4x4_t @llvm.aarch64.neon.ld4.v4i32.p0i32(i32* %A) ret %struct.__neon_int32x4x4_t %tmp2 } @@ -218,8 +218,8 @@ declare %struct.__neon_int32x4x4_t @llvm.aarch64.neon.ld4.v4i32.p0i32(i32*) noun define %struct.__neon_int64x2x2_t @ld2_2d(i64* %A) nounwind { ; CHECK-LABEL: ld2_2d ; Make sure we are using the operands defined by the ABI -; CHECK ld2.2d { v0, v1 }, [x0] -; CHECK-NEXT ret +; CHECK: ld2.2d { v0, v1 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int64x2x2_t @llvm.aarch64.neon.ld2.v2i64.p0i64(i64* %A) ret %struct.__neon_int64x2x2_t %tmp2 } @@ -227,8 +227,8 @@ define %struct.__neon_int64x2x2_t @ld2_2d(i64* %A) nounwind { define %struct.__neon_int64x2x3_t @ld3_2d(i64* %A) nounwind { ; CHECK-LABEL: ld3_2d ; Make sure we are using the operands defined by the ABI -; CHECK ld3.2d { v0, v1, v2 }, [x0] -; CHECK-NEXT ret +; CHECK: ld3.2d { v0, v1, v2 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int64x2x3_t @llvm.aarch64.neon.ld3.v2i64.p0i64(i64* %A) ret %struct.__neon_int64x2x3_t %tmp2 } @@ -236,8 +236,8 @@ define %struct.__neon_int64x2x3_t @ld3_2d(i64* %A) nounwind { define %struct.__neon_int64x2x4_t @ld4_2d(i64* %A) nounwind { ; CHECK-LABEL: ld4_2d ; Make sure we are using the operands defined by the ABI -; CHECK ld4.2d { v0, v1, v2, v3 }, [x0] -; CHECK-NEXT ret +; CHECK: ld4.2d { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int64x2x4_t @llvm.aarch64.neon.ld4.v2i64.p0i64(i64* %A) ret %struct.__neon_int64x2x4_t %tmp2 } @@ -254,8 +254,8 @@ declare %struct.__neon_int64x2x4_t @llvm.aarch64.neon.ld4.v2i64.p0i64(i64*) noun define %struct.__neon_int64x1x2_t @ld2_1di64(i64* %A) nounwind { ; CHECK-LABEL: ld2_1di64 ; Make sure we are using the operands defined by the ABI -; CHECK ld1.1d { v0, v1 }, [x0] -; CHECK-NEXT ret +; CHECK: ld1.1d { v0, v1 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int64x1x2_t @llvm.aarch64.neon.ld2.v1i64.p0i64(i64* %A) ret %struct.__neon_int64x1x2_t %tmp2 } @@ -263,8 +263,8 @@ define %struct.__neon_int64x1x2_t @ld2_1di64(i64* %A) nounwind { define %struct.__neon_int64x1x3_t @ld3_1di64(i64* %A) nounwind { ; CHECK-LABEL: ld3_1di64 ; Make sure we are using the operands defined by the ABI -; CHECK ld1.1d { v0, v1, v2 }, [x0] -; CHECK-NEXT ret +; CHECK: ld1.1d { v0, v1, v2 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int64x1x3_t @llvm.aarch64.neon.ld3.v1i64.p0i64(i64* %A) ret %struct.__neon_int64x1x3_t %tmp2 } @@ -272,8 +272,8 @@ define %struct.__neon_int64x1x3_t @ld3_1di64(i64* %A) nounwind { define %struct.__neon_int64x1x4_t @ld4_1di64(i64* %A) nounwind { ; CHECK-LABEL: ld4_1di64 ; Make sure we are using the operands defined by the ABI -; CHECK ld1.1d { v0, v1, v2, v3 }, [x0] -; CHECK-NEXT ret +; CHECK: ld1.1d { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int64x1x4_t @llvm.aarch64.neon.ld4.v1i64.p0i64(i64* %A) ret %struct.__neon_int64x1x4_t %tmp2 } @@ -291,8 +291,8 @@ declare %struct.__neon_int64x1x4_t @llvm.aarch64.neon.ld4.v1i64.p0i64(i64*) noun define %struct.__neon_float64x1x2_t @ld2_1df64(double* %A) nounwind { ; CHECK-LABEL: ld2_1df64 ; Make sure we are using the operands defined by the ABI -; CHECK ld1.1d { v0, v1 }, [x0] -; CHECK-NEXT ret +; CHECK: ld1.1d { v0, v1 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_float64x1x2_t @llvm.aarch64.neon.ld2.v1f64.p0f64(double* %A) ret %struct.__neon_float64x1x2_t %tmp2 } @@ -300,8 +300,8 @@ define %struct.__neon_float64x1x2_t @ld2_1df64(double* %A) nounwind { define %struct.__neon_float64x1x3_t @ld3_1df64(double* %A) nounwind { ; CHECK-LABEL: ld3_1df64 ; Make sure we are using the operands defined by the ABI -; CHECK ld1.1d { v0, v1, v2 }, [x0] -; CHECK-NEXT ret +; CHECK: ld1.1d { v0, v1, v2 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_float64x1x3_t @llvm.aarch64.neon.ld3.v1f64.p0f64(double* %A) ret %struct.__neon_float64x1x3_t %tmp2 } @@ -309,8 +309,8 @@ define %struct.__neon_float64x1x3_t @ld3_1df64(double* %A) nounwind { define %struct.__neon_float64x1x4_t @ld4_1df64(double* %A) nounwind { ; CHECK-LABEL: ld4_1df64 ; Make sure we are using the operands defined by the ABI -; CHECK ld1.1d { v0, v1, v2, v3 }, [x0] -; CHECK-NEXT ret +; CHECK: ld1.1d { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_float64x1x4_t @llvm.aarch64.neon.ld4.v1f64.p0f64(double* %A) ret %struct.__neon_float64x1x4_t %tmp2 } @@ -323,8 +323,8 @@ declare %struct.__neon_float64x1x4_t @llvm.aarch64.neon.ld4.v1f64.p0f64(double*) define %struct.__neon_int8x16x2_t @ld2lane_16b(<16 x i8> %L1, <16 x i8> %L2, i8* %A) nounwind { ; Make sure we are using the operands defined by the ABI ; CHECK: ld2lane_16b -; CHECK ld2.b { v0, v1 }[1], [x0] -; CHECK-NEXT ret +; CHECK: ld2.b { v0, v1 }[1], [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int8x16x2_t @llvm.aarch64.neon.ld2lane.v16i8.p0i8(<16 x i8> %L1, <16 x i8> %L2, i64 1, i8* %A) ret %struct.__neon_int8x16x2_t %tmp2 } @@ -332,8 +332,8 @@ define %struct.__neon_int8x16x2_t @ld2lane_16b(<16 x i8> %L1, <16 x i8> %L2, i8* define %struct.__neon_int8x16x3_t @ld3lane_16b(<16 x i8> %L1, <16 x i8> %L2, <16 x i8> %L3, i8* %A) nounwind { ; Make sure we are using the operands defined by the ABI ; CHECK: ld3lane_16b -; CHECK ld3.b { v0, v1, v2 }[1], [x0] -; CHECK-NEXT ret +; CHECK: ld3.b { v0, v1, v2 }[1], [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int8x16x3_t @llvm.aarch64.neon.ld3lane.v16i8.p0i8(<16 x i8> %L1, <16 x i8> %L2, <16 x i8> %L3, i64 1, i8* %A) ret %struct.__neon_int8x16x3_t %tmp2 } @@ -341,8 +341,8 @@ define %struct.__neon_int8x16x3_t @ld3lane_16b(<16 x i8> %L1, <16 x i8> %L2, <16 define %struct.__neon_int8x16x4_t @ld4lane_16b(<16 x i8> %L1, <16 x i8> %L2, <16 x i8> %L3, <16 x i8> %L4, i8* %A) nounwind { ; Make sure we are using the operands defined by the ABI ; CHECK: ld4lane_16b -; CHECK ld4.b { v0, v1, v2, v3 }[1], [x0] -; CHECK-NEXT ret +; CHECK: ld4.b { v0, v1, v2, v3 }[1], [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4lane.v16i8.p0i8(<16 x i8> %L1, <16 x i8> %L2, <16 x i8> %L3, <16 x i8> %L4, i64 1, i8* %A) ret %struct.__neon_int8x16x4_t %tmp2 } @@ -354,8 +354,8 @@ declare %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4lane.v16i8.p0i8(<16 x i define %struct.__neon_int16x8x2_t @ld2lane_8h(<8 x i16> %L1, <8 x i16> %L2, i16* %A) nounwind { ; Make sure we are using the operands defined by the ABI ; CHECK: ld2lane_8h -; CHECK ld2.h { v0, v1 }[1], [x0] -; CHECK-NEXT ret +; CHECK: ld2.h { v0, v1 }[1], [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int16x8x2_t @llvm.aarch64.neon.ld2lane.v8i16.p0i16(<8 x i16> %L1, <8 x i16> %L2, i64 1, i16* %A) ret %struct.__neon_int16x8x2_t %tmp2 } @@ -363,8 +363,8 @@ define %struct.__neon_int16x8x2_t @ld2lane_8h(<8 x i16> %L1, <8 x i16> %L2, i16* define %struct.__neon_int16x8x3_t @ld3lane_8h(<8 x i16> %L1, <8 x i16> %L2, <8 x i16> %L3, i16* %A) nounwind { ; Make sure we are using the operands defined by the ABI ; CHECK: ld3lane_8h -; CHECK ld3.h { v0, v1, v3 }[1], [x0] -; CHECK-NEXT ret +; CHECK: ld3.h { v0, v1, v2 }[1], [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int16x8x3_t @llvm.aarch64.neon.ld3lane.v8i16.p0i16(<8 x i16> %L1, <8 x i16> %L2, <8 x i16> %L3, i64 1, i16* %A) ret %struct.__neon_int16x8x3_t %tmp2 } @@ -372,8 +372,8 @@ define %struct.__neon_int16x8x3_t @ld3lane_8h(<8 x i16> %L1, <8 x i16> %L2, <8 x define %struct.__neon_int16x8x4_t @ld4lane_8h(<8 x i16> %L1, <8 x i16> %L2, <8 x i16> %L3, <8 x i16> %L4, i16* %A) nounwind { ; Make sure we are using the operands defined by the ABI ; CHECK: ld4lane_8h -; CHECK ld4.h { v0, v1, v2, v3 }[1], [x0] -; CHECK-NEXT ret +; CHECK: ld4.h { v0, v1, v2, v3 }[1], [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int16x8x4_t @llvm.aarch64.neon.ld4lane.v8i16.p0i16(<8 x i16> %L1, <8 x i16> %L2, <8 x i16> %L3, <8 x i16> %L4, i64 1, i16* %A) ret %struct.__neon_int16x8x4_t %tmp2 } @@ -385,8 +385,8 @@ declare %struct.__neon_int16x8x4_t @llvm.aarch64.neon.ld4lane.v8i16.p0i16(<8 x i define %struct.__neon_int32x4x2_t @ld2lane_4s(<4 x i32> %L1, <4 x i32> %L2, i32* %A) nounwind { ; Make sure we are using the operands defined by the ABI ; CHECK: ld2lane_4s -; CHECK ld2.s { v0, v1 }[1], [x0] -; CHECK-NEXT ret +; CHECK: ld2.s { v0, v1 }[1], [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int32x4x2_t @llvm.aarch64.neon.ld2lane.v4i32.p0i32(<4 x i32> %L1, <4 x i32> %L2, i64 1, i32* %A) ret %struct.__neon_int32x4x2_t %tmp2 } @@ -394,8 +394,8 @@ define %struct.__neon_int32x4x2_t @ld2lane_4s(<4 x i32> %L1, <4 x i32> %L2, i32* define %struct.__neon_int32x4x3_t @ld3lane_4s(<4 x i32> %L1, <4 x i32> %L2, <4 x i32> %L3, i32* %A) nounwind { ; Make sure we are using the operands defined by the ABI ; CHECK: ld3lane_4s -; CHECK ld3.s { v0, v1, v2 }[1], [x0] -; CHECK-NEXT ret +; CHECK: ld3.s { v0, v1, v2 }[1], [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int32x4x3_t @llvm.aarch64.neon.ld3lane.v4i32.p0i32(<4 x i32> %L1, <4 x i32> %L2, <4 x i32> %L3, i64 1, i32* %A) ret %struct.__neon_int32x4x3_t %tmp2 } @@ -403,8 +403,8 @@ define %struct.__neon_int32x4x3_t @ld3lane_4s(<4 x i32> %L1, <4 x i32> %L2, <4 x define %struct.__neon_int32x4x4_t @ld4lane_4s(<4 x i32> %L1, <4 x i32> %L2, <4 x i32> %L3, <4 x i32> %L4, i32* %A) nounwind { ; Make sure we are using the operands defined by the ABI ; CHECK: ld4lane_4s -; CHECK ld4.s { v0, v1, v2, v3 }[1], [x0] -; CHECK-NEXT ret +; CHECK: ld4.s { v0, v1, v2, v3 }[1], [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int32x4x4_t @llvm.aarch64.neon.ld4lane.v4i32.p0i32(<4 x i32> %L1, <4 x i32> %L2, <4 x i32> %L3, <4 x i32> %L4, i64 1, i32* %A) ret %struct.__neon_int32x4x4_t %tmp2 } @@ -416,8 +416,8 @@ declare %struct.__neon_int32x4x4_t @llvm.aarch64.neon.ld4lane.v4i32.p0i32(<4 x i define %struct.__neon_int64x2x2_t @ld2lane_2d(<2 x i64> %L1, <2 x i64> %L2, i64* %A) nounwind { ; Make sure we are using the operands defined by the ABI ; CHECK: ld2lane_2d -; CHECK ld2.d { v0, v1 }[1], [x0] -; CHECK-NEXT ret +; CHECK: ld2.d { v0, v1 }[1], [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int64x2x2_t @llvm.aarch64.neon.ld2lane.v2i64.p0i64(<2 x i64> %L1, <2 x i64> %L2, i64 1, i64* %A) ret %struct.__neon_int64x2x2_t %tmp2 } @@ -425,8 +425,8 @@ define %struct.__neon_int64x2x2_t @ld2lane_2d(<2 x i64> %L1, <2 x i64> %L2, i64* define %struct.__neon_int64x2x3_t @ld3lane_2d(<2 x i64> %L1, <2 x i64> %L2, <2 x i64> %L3, i64* %A) nounwind { ; Make sure we are using the operands defined by the ABI ; CHECK: ld3lane_2d -; CHECK ld3.d { v0, v1, v3 }[1], [x0] -; CHECK-NEXT ret +; CHECK: ld3.d { v0, v1, v2 }[1], [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int64x2x3_t @llvm.aarch64.neon.ld3lane.v2i64.p0i64(<2 x i64> %L1, <2 x i64> %L2, <2 x i64> %L3, i64 1, i64* %A) ret %struct.__neon_int64x2x3_t %tmp2 } @@ -434,8 +434,8 @@ define %struct.__neon_int64x2x3_t @ld3lane_2d(<2 x i64> %L1, <2 x i64> %L2, <2 x define %struct.__neon_int64x2x4_t @ld4lane_2d(<2 x i64> %L1, <2 x i64> %L2, <2 x i64> %L3, <2 x i64> %L4, i64* %A) nounwind { ; Make sure we are using the operands defined by the ABI ; CHECK: ld4lane_2d -; CHECK ld4.d { v0, v1, v2, v3 }[1], [x0] -; CHECK-NEXT ret +; CHECK: ld4.d { v0, v1, v2, v3 }[1], [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int64x2x4_t @llvm.aarch64.neon.ld4lane.v2i64.p0i64(<2 x i64> %L1, <2 x i64> %L2, <2 x i64> %L3, <2 x i64> %L4, i64 1, i64* %A) ret %struct.__neon_int64x2x4_t %tmp2 } @@ -448,8 +448,8 @@ define <8 x i8> @ld1r_8b(i8* %bar) { ; CHECK: ld1r_8b ; Make sure we are using the operands defined by the ABI ; CHECK: ld1r.8b { v0 }, [x0] -; CHECK-NEXT ret - %tmp1 = load i8* %bar +; CHECK-NEXT: ret + %tmp1 = load i8, i8* %bar %tmp2 = insertelement <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0 %tmp3 = insertelement <8 x i8> %tmp2, i8 %tmp1, i32 1 %tmp4 = insertelement <8 x i8> %tmp3, i8 %tmp1, i32 2 @@ -465,8 +465,8 @@ define <16 x i8> @ld1r_16b(i8* %bar) { ; CHECK: ld1r_16b ; Make sure we are using the operands defined by the ABI ; CHECK: ld1r.16b { v0 }, [x0] -; CHECK-NEXT ret - %tmp1 = load i8* %bar +; CHECK-NEXT: ret + %tmp1 = load i8, i8* %bar %tmp2 = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0 %tmp3 = insertelement <16 x i8> %tmp2, i8 %tmp1, i32 1 %tmp4 = insertelement <16 x i8> %tmp3, i8 %tmp1, i32 2 @@ -490,8 +490,8 @@ define <4 x i16> @ld1r_4h(i16* %bar) { ; CHECK: ld1r_4h ; Make sure we are using the operands defined by the ABI ; CHECK: ld1r.4h { v0 }, [x0] -; CHECK-NEXT ret - %tmp1 = load i16* %bar +; CHECK-NEXT: ret + %tmp1 = load i16, i16* %bar %tmp2 = insertelement <4 x i16> <i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0 %tmp3 = insertelement <4 x i16> %tmp2, i16 %tmp1, i32 1 %tmp4 = insertelement <4 x i16> %tmp3, i16 %tmp1, i32 2 @@ -503,8 +503,8 @@ define <8 x i16> @ld1r_8h(i16* %bar) { ; CHECK: ld1r_8h ; Make sure we are using the operands defined by the ABI ; CHECK: ld1r.8h { v0 }, [x0] -; CHECK-NEXT ret - %tmp1 = load i16* %bar +; CHECK-NEXT: ret + %tmp1 = load i16, i16* %bar %tmp2 = insertelement <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, i16 %tmp1, i32 0 %tmp3 = insertelement <8 x i16> %tmp2, i16 %tmp1, i32 1 %tmp4 = insertelement <8 x i16> %tmp3, i16 %tmp1, i32 2 @@ -520,8 +520,8 @@ define <2 x i32> @ld1r_2s(i32* %bar) { ; CHECK: ld1r_2s ; Make sure we are using the operands defined by the ABI ; CHECK: ld1r.2s { v0 }, [x0] -; CHECK-NEXT ret - %tmp1 = load i32* %bar +; CHECK-NEXT: ret + %tmp1 = load i32, i32* %bar %tmp2 = insertelement <2 x i32> <i32 undef, i32 undef>, i32 %tmp1, i32 0 %tmp3 = insertelement <2 x i32> %tmp2, i32 %tmp1, i32 1 ret <2 x i32> %tmp3 @@ -531,8 +531,8 @@ define <4 x i32> @ld1r_4s(i32* %bar) { ; CHECK: ld1r_4s ; Make sure we are using the operands defined by the ABI ; CHECK: ld1r.4s { v0 }, [x0] -; CHECK-NEXT ret - %tmp1 = load i32* %bar +; CHECK-NEXT: ret + %tmp1 = load i32, i32* %bar %tmp2 = insertelement <4 x i32> <i32 undef, i32 undef, i32 undef, i32 undef>, i32 %tmp1, i32 0 %tmp3 = insertelement <4 x i32> %tmp2, i32 %tmp1, i32 1 %tmp4 = insertelement <4 x i32> %tmp3, i32 %tmp1, i32 2 @@ -544,8 +544,8 @@ define <2 x i64> @ld1r_2d(i64* %bar) { ; CHECK: ld1r_2d ; Make sure we are using the operands defined by the ABI ; CHECK: ld1r.2d { v0 }, [x0] -; CHECK-NEXT ret - %tmp1 = load i64* %bar +; CHECK-NEXT: ret + %tmp1 = load i64, i64* %bar %tmp2 = insertelement <2 x i64> <i64 undef, i64 undef>, i64 %tmp1, i32 0 %tmp3 = insertelement <2 x i64> %tmp2, i64 %tmp1, i32 1 ret <2 x i64> %tmp3 @@ -554,8 +554,8 @@ define <2 x i64> @ld1r_2d(i64* %bar) { define %struct.__neon_int8x8x2_t @ld2r_8b(i8* %A) nounwind { ; CHECK: ld2r_8b ; Make sure we are using the operands defined by the ABI -; CHECK ld2r.8b { v0, v1 }, [x0] -; CHECK-NEXT ret +; CHECK: ld2r.8b { v0, v1 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int8x8x2_t @llvm.aarch64.neon.ld2r.v8i8.p0i8(i8* %A) ret %struct.__neon_int8x8x2_t %tmp2 } @@ -563,8 +563,8 @@ define %struct.__neon_int8x8x2_t @ld2r_8b(i8* %A) nounwind { define %struct.__neon_int8x8x3_t @ld3r_8b(i8* %A) nounwind { ; CHECK: ld3r_8b ; Make sure we are using the operands defined by the ABI -; CHECK ld3r.8b { v0, v1, v2 }, [x0] -; CHECK-NEXT ret +; CHECK: ld3r.8b { v0, v1, v2 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int8x8x3_t @llvm.aarch64.neon.ld3r.v8i8.p0i8(i8* %A) ret %struct.__neon_int8x8x3_t %tmp2 } @@ -572,8 +572,8 @@ define %struct.__neon_int8x8x3_t @ld3r_8b(i8* %A) nounwind { define %struct.__neon_int8x8x4_t @ld4r_8b(i8* %A) nounwind { ; CHECK: ld4r_8b ; Make sure we are using the operands defined by the ABI -; CHECK ld4r.8b { v0, v1, v2, v3 }, [x0] -; CHECK-NEXT ret +; CHECK: ld4r.8b { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int8x8x4_t @llvm.aarch64.neon.ld4r.v8i8.p0i8(i8* %A) ret %struct.__neon_int8x8x4_t %tmp2 } @@ -585,8 +585,8 @@ declare %struct.__neon_int8x8x4_t @llvm.aarch64.neon.ld4r.v8i8.p0i8(i8*) nounwin define %struct.__neon_int8x16x2_t @ld2r_16b(i8* %A) nounwind { ; CHECK: ld2r_16b ; Make sure we are using the operands defined by the ABI -; CHECK ld2r.16b { v0, v1 }, [x0] -; CHECK-NEXT ret +; CHECK: ld2r.16b { v0, v1 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int8x16x2_t @llvm.aarch64.neon.ld2r.v16i8.p0i8(i8* %A) ret %struct.__neon_int8x16x2_t %tmp2 } @@ -594,8 +594,8 @@ define %struct.__neon_int8x16x2_t @ld2r_16b(i8* %A) nounwind { define %struct.__neon_int8x16x3_t @ld3r_16b(i8* %A) nounwind { ; CHECK: ld3r_16b ; Make sure we are using the operands defined by the ABI -; CHECK ld3r.16b { v0, v1, v2 }, [x0] -; CHECK-NEXT ret +; CHECK: ld3r.16b { v0, v1, v2 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int8x16x3_t @llvm.aarch64.neon.ld3r.v16i8.p0i8(i8* %A) ret %struct.__neon_int8x16x3_t %tmp2 } @@ -603,8 +603,8 @@ define %struct.__neon_int8x16x3_t @ld3r_16b(i8* %A) nounwind { define %struct.__neon_int8x16x4_t @ld4r_16b(i8* %A) nounwind { ; CHECK: ld4r_16b ; Make sure we are using the operands defined by the ABI -; CHECK ld4r.16b { v0, v1, v2, v3 }, [x0] -; CHECK-NEXT ret +; CHECK: ld4r.16b { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4r.v16i8.p0i8(i8* %A) ret %struct.__neon_int8x16x4_t %tmp2 } @@ -616,8 +616,8 @@ declare %struct.__neon_int8x16x4_t @llvm.aarch64.neon.ld4r.v16i8.p0i8(i8*) nounw define %struct.__neon_int16x4x2_t @ld2r_4h(i16* %A) nounwind { ; CHECK: ld2r_4h ; Make sure we are using the operands defined by the ABI -; CHECK ld2r.4h { v0, v1 }, [x0] -; CHECK-NEXT ret +; CHECK: ld2r.4h { v0, v1 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int16x4x2_t @llvm.aarch64.neon.ld2r.v4i16.p0i16(i16* %A) ret %struct.__neon_int16x4x2_t %tmp2 } @@ -625,8 +625,8 @@ define %struct.__neon_int16x4x2_t @ld2r_4h(i16* %A) nounwind { define %struct.__neon_int16x4x3_t @ld3r_4h(i16* %A) nounwind { ; CHECK: ld3r_4h ; Make sure we are using the operands defined by the ABI -; CHECK ld3r.4h { v0, v1, v2 }, [x0] -; CHECK-NEXT ret +; CHECK: ld3r.4h { v0, v1, v2 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int16x4x3_t @llvm.aarch64.neon.ld3r.v4i16.p0i16(i16* %A) ret %struct.__neon_int16x4x3_t %tmp2 } @@ -634,8 +634,8 @@ define %struct.__neon_int16x4x3_t @ld3r_4h(i16* %A) nounwind { define %struct.__neon_int16x4x4_t @ld4r_4h(i16* %A) nounwind { ; CHECK: ld4r_4h ; Make sure we are using the operands defined by the ABI -; CHECK ld4r.4h { v0, v1, v2, v3 }, [x0] -; CHECK-NEXT ret +; CHECK: ld4r.4h { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int16x4x4_t @llvm.aarch64.neon.ld4r.v4i16.p0i16(i16* %A) ret %struct.__neon_int16x4x4_t %tmp2 } @@ -647,8 +647,8 @@ declare %struct.__neon_int16x4x4_t @llvm.aarch64.neon.ld4r.v4i16.p0i16(i16*) nou define %struct.__neon_int16x8x2_t @ld2r_8h(i16* %A) nounwind { ; CHECK: ld2r_8h ; Make sure we are using the operands defined by the ABI -; CHECK ld2r.8h { v0, v1 }, [x0] -; CHECK-NEXT ret +; CHECK: ld2r.8h { v0, v1 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int16x8x2_t @llvm.aarch64.neon.ld2r.v8i16.p0i16(i16* %A) ret %struct.__neon_int16x8x2_t %tmp2 } @@ -656,8 +656,8 @@ define %struct.__neon_int16x8x2_t @ld2r_8h(i16* %A) nounwind { define %struct.__neon_int16x8x3_t @ld3r_8h(i16* %A) nounwind { ; CHECK: ld3r_8h ; Make sure we are using the operands defined by the ABI -; CHECK ld3r.8h { v0, v1, v2 }, [x0] -; CHECK-NEXT ret +; CHECK: ld3r.8h { v0, v1, v2 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int16x8x3_t @llvm.aarch64.neon.ld3r.v8i16.p0i16(i16* %A) ret %struct.__neon_int16x8x3_t %tmp2 } @@ -665,8 +665,8 @@ define %struct.__neon_int16x8x3_t @ld3r_8h(i16* %A) nounwind { define %struct.__neon_int16x8x4_t @ld4r_8h(i16* %A) nounwind { ; CHECK: ld4r_8h ; Make sure we are using the operands defined by the ABI -; CHECK ld4r.8h { v0, v1, v2, v3 }, [x0] -; CHECK-NEXT ret +; CHECK: ld4r.8h { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int16x8x4_t @llvm.aarch64.neon.ld4r.v8i16.p0i16(i16* %A) ret %struct.__neon_int16x8x4_t %tmp2 } @@ -678,8 +678,8 @@ declare %struct.__neon_int16x8x4_t @llvm.aarch64.neon.ld4r.v8i16.p0i16(i16*) nou define %struct.__neon_int32x2x2_t @ld2r_2s(i32* %A) nounwind { ; CHECK: ld2r_2s ; Make sure we are using the operands defined by the ABI -; CHECK ld2r.2s { v0, v1 }, [x0] -; CHECK-NEXT ret +; CHECK: ld2r.2s { v0, v1 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int32x2x2_t @llvm.aarch64.neon.ld2r.v2i32.p0i32(i32* %A) ret %struct.__neon_int32x2x2_t %tmp2 } @@ -687,8 +687,8 @@ define %struct.__neon_int32x2x2_t @ld2r_2s(i32* %A) nounwind { define %struct.__neon_int32x2x3_t @ld3r_2s(i32* %A) nounwind { ; CHECK: ld3r_2s ; Make sure we are using the operands defined by the ABI -; CHECK ld3r.2s { v0, v1, v2 }, [x0] -; CHECK-NEXT ret +; CHECK: ld3r.2s { v0, v1, v2 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int32x2x3_t @llvm.aarch64.neon.ld3r.v2i32.p0i32(i32* %A) ret %struct.__neon_int32x2x3_t %tmp2 } @@ -696,8 +696,8 @@ define %struct.__neon_int32x2x3_t @ld3r_2s(i32* %A) nounwind { define %struct.__neon_int32x2x4_t @ld4r_2s(i32* %A) nounwind { ; CHECK: ld4r_2s ; Make sure we are using the operands defined by the ABI -; CHECK ld4r.2s { v0, v1, v2, v3 }, [x0] -; CHECK-NEXT ret +; CHECK: ld4r.2s { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int32x2x4_t @llvm.aarch64.neon.ld4r.v2i32.p0i32(i32* %A) ret %struct.__neon_int32x2x4_t %tmp2 } @@ -709,8 +709,8 @@ declare %struct.__neon_int32x2x4_t @llvm.aarch64.neon.ld4r.v2i32.p0i32(i32*) nou define %struct.__neon_int32x4x2_t @ld2r_4s(i32* %A) nounwind { ; CHECK: ld2r_4s ; Make sure we are using the operands defined by the ABI -; CHECK ld2r.4s { v0, v1 }, [x0] -; CHECK-NEXT ret +; CHECK: ld2r.4s { v0, v1 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int32x4x2_t @llvm.aarch64.neon.ld2r.v4i32.p0i32(i32* %A) ret %struct.__neon_int32x4x2_t %tmp2 } @@ -718,8 +718,8 @@ define %struct.__neon_int32x4x2_t @ld2r_4s(i32* %A) nounwind { define %struct.__neon_int32x4x3_t @ld3r_4s(i32* %A) nounwind { ; CHECK: ld3r_4s ; Make sure we are using the operands defined by the ABI -; CHECK ld3r.4s { v0, v1, v2 }, [x0] -; CHECK-NEXT ret +; CHECK: ld3r.4s { v0, v1, v2 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int32x4x3_t @llvm.aarch64.neon.ld3r.v4i32.p0i32(i32* %A) ret %struct.__neon_int32x4x3_t %tmp2 } @@ -727,8 +727,8 @@ define %struct.__neon_int32x4x3_t @ld3r_4s(i32* %A) nounwind { define %struct.__neon_int32x4x4_t @ld4r_4s(i32* %A) nounwind { ; CHECK: ld4r_4s ; Make sure we are using the operands defined by the ABI -; CHECK ld4r.4s { v0, v1, v2, v3 }, [x0] -; CHECK-NEXT ret +; CHECK: ld4r.4s { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int32x4x4_t @llvm.aarch64.neon.ld4r.v4i32.p0i32(i32* %A) ret %struct.__neon_int32x4x4_t %tmp2 } @@ -740,8 +740,8 @@ declare %struct.__neon_int32x4x4_t @llvm.aarch64.neon.ld4r.v4i32.p0i32(i32*) nou define %struct.__neon_int64x1x2_t @ld2r_1d(i64* %A) nounwind { ; CHECK: ld2r_1d ; Make sure we are using the operands defined by the ABI -; CHECK ld2r.1d { v0, v1 }, [x0] -; CHECK-NEXT ret +; CHECK: ld2r.1d { v0, v1 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int64x1x2_t @llvm.aarch64.neon.ld2r.v1i64.p0i64(i64* %A) ret %struct.__neon_int64x1x2_t %tmp2 } @@ -749,8 +749,8 @@ define %struct.__neon_int64x1x2_t @ld2r_1d(i64* %A) nounwind { define %struct.__neon_int64x1x3_t @ld3r_1d(i64* %A) nounwind { ; CHECK: ld3r_1d ; Make sure we are using the operands defined by the ABI -; CHECK ld3r.1d { v0, v1, v2 }, [x0] -; CHECK-NEXT ret +; CHECK: ld3r.1d { v0, v1, v2 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int64x1x3_t @llvm.aarch64.neon.ld3r.v1i64.p0i64(i64* %A) ret %struct.__neon_int64x1x3_t %tmp2 } @@ -758,8 +758,8 @@ define %struct.__neon_int64x1x3_t @ld3r_1d(i64* %A) nounwind { define %struct.__neon_int64x1x4_t @ld4r_1d(i64* %A) nounwind { ; CHECK: ld4r_1d ; Make sure we are using the operands defined by the ABI -; CHECK ld4r.1d { v0, v1, v2, v3 }, [x0] -; CHECK-NEXT ret +; CHECK: ld4r.1d { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int64x1x4_t @llvm.aarch64.neon.ld4r.v1i64.p0i64(i64* %A) ret %struct.__neon_int64x1x4_t %tmp2 } @@ -771,8 +771,8 @@ declare %struct.__neon_int64x1x4_t @llvm.aarch64.neon.ld4r.v1i64.p0i64(i64*) nou define %struct.__neon_int64x2x2_t @ld2r_2d(i64* %A) nounwind { ; CHECK: ld2r_2d ; Make sure we are using the operands defined by the ABI -; CHECK ld2r.2d { v0, v1 }, [x0] -; CHECK-NEXT ret +; CHECK: ld2r.2d { v0, v1 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int64x2x2_t @llvm.aarch64.neon.ld2r.v2i64.p0i64(i64* %A) ret %struct.__neon_int64x2x2_t %tmp2 } @@ -780,8 +780,8 @@ define %struct.__neon_int64x2x2_t @ld2r_2d(i64* %A) nounwind { define %struct.__neon_int64x2x3_t @ld3r_2d(i64* %A) nounwind { ; CHECK: ld3r_2d ; Make sure we are using the operands defined by the ABI -; CHECK ld3r.2d { v0, v1, v2 }, [x0] -; CHECK-NEXT ret +; CHECK: ld3r.2d { v0, v1, v2 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int64x2x3_t @llvm.aarch64.neon.ld3r.v2i64.p0i64(i64* %A) ret %struct.__neon_int64x2x3_t %tmp2 } @@ -789,8 +789,8 @@ define %struct.__neon_int64x2x3_t @ld3r_2d(i64* %A) nounwind { define %struct.__neon_int64x2x4_t @ld4r_2d(i64* %A) nounwind { ; CHECK: ld4r_2d ; Make sure we are using the operands defined by the ABI -; CHECK ld4r.2d { v0, v1, v2, v3 }, [x0] -; CHECK-NEXT ret +; CHECK: ld4r.2d { v0, v1, v2, v3 }, [x0] +; CHECK-NEXT: ret %tmp2 = call %struct.__neon_int64x2x4_t @llvm.aarch64.neon.ld4r.v2i64.p0i64(i64* %A) ret %struct.__neon_int64x2x4_t %tmp2 } @@ -803,8 +803,8 @@ define <16 x i8> @ld1_16b(<16 x i8> %V, i8* %bar) { ; CHECK-LABEL: ld1_16b ; Make sure we are using the operands defined by the ABI ; CHECK: ld1.b { v0 }[0], [x0] -; CHECK-NEXT ret - %tmp1 = load i8* %bar +; CHECK-NEXT: ret + %tmp1 = load i8, i8* %bar %tmp2 = insertelement <16 x i8> %V, i8 %tmp1, i32 0 ret <16 x i8> %tmp2 } @@ -813,8 +813,8 @@ define <8 x i16> @ld1_8h(<8 x i16> %V, i16* %bar) { ; CHECK-LABEL: ld1_8h ; Make sure we are using the operands defined by the ABI ; CHECK: ld1.h { v0 }[0], [x0] -; CHECK-NEXT ret - %tmp1 = load i16* %bar +; CHECK-NEXT: ret + %tmp1 = load i16, i16* %bar %tmp2 = insertelement <8 x i16> %V, i16 %tmp1, i32 0 ret <8 x i16> %tmp2 } @@ -823,8 +823,8 @@ define <4 x i32> @ld1_4s(<4 x i32> %V, i32* %bar) { ; CHECK-LABEL: ld1_4s ; Make sure we are using the operands defined by the ABI ; CHECK: ld1.s { v0 }[0], [x0] -; CHECK-NEXT ret - %tmp1 = load i32* %bar +; CHECK-NEXT: ret + %tmp1 = load i32, i32* %bar %tmp2 = insertelement <4 x i32> %V, i32 %tmp1, i32 0 ret <4 x i32> %tmp2 } @@ -833,8 +833,8 @@ define <4 x float> @ld1_4s_float(<4 x float> %V, float* %bar) { ; CHECK-LABEL: ld1_4s_float: ; Make sure we are using the operands defined by the ABI ; CHECK: ld1.s { v0 }[0], [x0] -; CHECK-NEXT ret - %tmp1 = load float* %bar +; CHECK-NEXT: ret + %tmp1 = load float, float* %bar %tmp2 = insertelement <4 x float> %V, float %tmp1, i32 0 ret <4 x float> %tmp2 } @@ -843,8 +843,8 @@ define <2 x i64> @ld1_2d(<2 x i64> %V, i64* %bar) { ; CHECK-LABEL: ld1_2d ; Make sure we are using the operands defined by the ABI ; CHECK: ld1.d { v0 }[0], [x0] -; CHECK-NEXT ret - %tmp1 = load i64* %bar +; CHECK-NEXT: ret + %tmp1 = load i64, i64* %bar %tmp2 = insertelement <2 x i64> %V, i64 %tmp1, i32 0 ret <2 x i64> %tmp2 } @@ -853,8 +853,8 @@ define <2 x double> @ld1_2d_double(<2 x double> %V, double* %bar) { ; CHECK-LABEL: ld1_2d_double: ; Make sure we are using the operands defined by the ABI ; CHECK: ld1.d { v0 }[0], [x0] -; CHECK-NEXT ret - %tmp1 = load double* %bar +; CHECK-NEXT: ret + %tmp1 = load double, double* %bar %tmp2 = insertelement <2 x double> %V, double %tmp1, i32 0 ret <2 x double> %tmp2 } @@ -864,7 +864,7 @@ define <1 x i64> @ld1_1d(<1 x i64>* %p) { ; Make sure we are using the operands defined by the ABI ; CHECK: ldr [[REG:d[0-9]+]], [x0] ; CHECK-NEXT: ret - %tmp = load <1 x i64>* %p, align 8 + %tmp = load <1 x i64>, <1 x i64>* %p, align 8 ret <1 x i64> %tmp } @@ -872,8 +872,8 @@ define <8 x i8> @ld1_8b(<8 x i8> %V, i8* %bar) { ; CHECK-LABEL: ld1_8b ; Make sure we are using the operands defined by the ABI ; CHECK: ld1.b { v0 }[0], [x0] -; CHECK-NEXT ret - %tmp1 = load i8* %bar +; CHECK-NEXT: ret + %tmp1 = load i8, i8* %bar %tmp2 = insertelement <8 x i8> %V, i8 %tmp1, i32 0 ret <8 x i8> %tmp2 } @@ -882,8 +882,8 @@ define <4 x i16> @ld1_4h(<4 x i16> %V, i16* %bar) { ; CHECK-LABEL: ld1_4h ; Make sure we are using the operands defined by the ABI ; CHECK: ld1.h { v0 }[0], [x0] -; CHECK-NEXT ret - %tmp1 = load i16* %bar +; CHECK-NEXT: ret + %tmp1 = load i16, i16* %bar %tmp2 = insertelement <4 x i16> %V, i16 %tmp1, i32 0 ret <4 x i16> %tmp2 } @@ -892,8 +892,8 @@ define <2 x i32> @ld1_2s(<2 x i32> %V, i32* %bar) { ; CHECK-LABEL: ld1_2s: ; Make sure we are using the operands defined by the ABI ; CHECK: ld1.s { v0 }[0], [x0] -; CHECK-NEXT ret - %tmp1 = load i32* %bar +; CHECK-NEXT: ret + %tmp1 = load i32, i32* %bar %tmp2 = insertelement <2 x i32> %V, i32 %tmp1, i32 0 ret <2 x i32> %tmp2 } @@ -902,8 +902,8 @@ define <2 x float> @ld1_2s_float(<2 x float> %V, float* %bar) { ; CHECK-LABEL: ld1_2s_float: ; Make sure we are using the operands defined by the ABI ; CHECK: ld1.s { v0 }[0], [x0] -; CHECK-NEXT ret - %tmp1 = load float* %bar +; CHECK-NEXT: ret + %tmp1 = load float, float* %bar %tmp2 = insertelement <2 x float> %V, float %tmp1, i32 0 ret <2 x float> %tmp2 } @@ -919,12 +919,12 @@ entry: ; CHECK-NEXT: str d[[RESREGNUM]], [x2] ; CHECK-NEXT: ret %tmp = bitcast i8* %a to i32* - %tmp1 = load i32* %tmp, align 4 + %tmp1 = load i32, i32* %tmp, align 4 %tmp2 = insertelement <2 x i32> undef, i32 %tmp1, i32 0 %lane = shufflevector <2 x i32> %tmp2, <2 x i32> undef, <2 x i32> zeroinitializer %tmp3 = bitcast <2 x i32> %lane to <8 x i8> %tmp4 = bitcast i8* %b to i32* - %tmp5 = load i32* %tmp4, align 4 + %tmp5 = load i32, i32* %tmp4, align 4 %tmp6 = insertelement <2 x i32> undef, i32 %tmp5, i32 0 %lane1 = shufflevector <2 x i32> %tmp6, <2 x i32> undef, <2 x i32> zeroinitializer %tmp7 = bitcast <2 x i32> %lane1 to <8 x i8> @@ -945,8 +945,8 @@ entry: ; CHECK-LABEL: ld1r_4s_float ; Make sure we are using the operands defined by the ABI ; CHECK: ld1r.4s { v0 }, [x0] -; CHECK-NEXT ret - %tmp = load float* %x, align 4 +; CHECK-NEXT: ret + %tmp = load float, float* %x, align 4 %tmp1 = insertelement <4 x float> undef, float %tmp, i32 0 %tmp2 = insertelement <4 x float> %tmp1, float %tmp, i32 1 %tmp3 = insertelement <4 x float> %tmp2, float %tmp, i32 2 @@ -959,8 +959,8 @@ entry: ; CHECK-LABEL: ld1r_2s_float ; Make sure we are using the operands defined by the ABI ; CHECK: ld1r.2s { v0 }, [x0] -; CHECK-NEXT ret - %tmp = load float* %x, align 4 +; CHECK-NEXT: ret + %tmp = load float, float* %x, align 4 %tmp1 = insertelement <2 x float> undef, float %tmp, i32 0 %tmp2 = insertelement <2 x float> %tmp1, float %tmp, i32 1 ret <2 x float> %tmp2 @@ -971,8 +971,8 @@ entry: ; CHECK-LABEL: ld1r_2d_double ; Make sure we are using the operands defined by the ABI ; CHECK: ld1r.2d { v0 }, [x0] -; CHECK-NEXT ret - %tmp = load double* %x, align 4 +; CHECK-NEXT: ret + %tmp = load double, double* %x, align 4 %tmp1 = insertelement <2 x double> undef, double %tmp, i32 0 %tmp2 = insertelement <2 x double> %tmp1, double %tmp, i32 1 ret <2 x double> %tmp2 @@ -983,8 +983,8 @@ entry: ; CHECK-LABEL: ld1r_1d_double ; Make sure we are using the operands defined by the ABI ; CHECK: ldr d0, [x0] -; CHECK-NEXT ret - %tmp = load double* %x, align 4 +; CHECK-NEXT: ret + %tmp = load double, double* %x, align 4 %tmp1 = insertelement <1 x double> undef, double %tmp, i32 0 ret <1 x double> %tmp1 } @@ -994,8 +994,8 @@ entry: ; CHECK-LABEL: ld1r_4s_float_shuff ; Make sure we are using the operands defined by the ABI ; CHECK: ld1r.4s { v0 }, [x0] -; CHECK-NEXT ret - %tmp = load float* %x, align 4 +; CHECK-NEXT: ret + %tmp = load float, float* %x, align 4 %tmp1 = insertelement <4 x float> undef, float %tmp, i32 0 %lane = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer ret <4 x float> %lane @@ -1006,8 +1006,8 @@ entry: ; CHECK-LABEL: ld1r_2s_float_shuff ; Make sure we are using the operands defined by the ABI ; CHECK: ld1r.2s { v0 }, [x0] -; CHECK-NEXT ret - %tmp = load float* %x, align 4 +; CHECK-NEXT: ret + %tmp = load float, float* %x, align 4 %tmp1 = insertelement <2 x float> undef, float %tmp, i32 0 %lane = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer ret <2 x float> %lane @@ -1018,8 +1018,8 @@ entry: ; CHECK-LABEL: ld1r_2d_double_shuff ; Make sure we are using the operands defined by the ABI ; CHECK: ld1r.2d { v0 }, [x0] -; CHECK-NEXT ret - %tmp = load double* %x, align 4 +; CHECK-NEXT: ret + %tmp = load double, double* %x, align 4 %tmp1 = insertelement <2 x double> undef, double %tmp, i32 0 %lane = shufflevector <2 x double> %tmp1, <2 x double> undef, <2 x i32> zeroinitializer ret <2 x double> %lane @@ -1030,8 +1030,8 @@ entry: ; CHECK-LABEL: ld1r_1d_double_shuff ; Make sure we are using the operands defined by the ABI ; CHECK: ldr d0, [x0] -; CHECK-NEXT ret - %tmp = load double* %x, align 4 +; CHECK-NEXT: ret + %tmp = load double, double* %x, align 4 %tmp1 = insertelement <1 x double> undef, double %tmp, i32 0 %lane = shufflevector <1 x double> %tmp1, <1 x double> undef, <1 x i32> zeroinitializer ret <1 x double> %lane diff --git a/test/CodeGen/AArch64/arm64-ldp.ll b/test/CodeGen/AArch64/arm64-ldp.ll index a9fa4ca..a192eab 100644 --- a/test/CodeGen/AArch64/arm64-ldp.ll +++ b/test/CodeGen/AArch64/arm64-ldp.ll @@ -5,9 +5,9 @@ ; CHECK: ldp_int ; CHECK: ldp define i32 @ldp_int(i32* %p) nounwind { - %tmp = load i32* %p, align 4 - %add.ptr = getelementptr inbounds i32* %p, i64 1 - %tmp1 = load i32* %add.ptr, align 4 + %tmp = load i32, i32* %p, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i64 1 + %tmp1 = load i32, i32* %add.ptr, align 4 %add = add nsw i32 %tmp1, %tmp ret i32 %add } @@ -15,21 +15,48 @@ define i32 @ldp_int(i32* %p) nounwind { ; CHECK: ldp_sext_int ; CHECK: ldpsw define i64 @ldp_sext_int(i32* %p) nounwind { - %tmp = load i32* %p, align 4 - %add.ptr = getelementptr inbounds i32* %p, i64 1 - %tmp1 = load i32* %add.ptr, align 4 + %tmp = load i32, i32* %p, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i64 1 + %tmp1 = load i32, i32* %add.ptr, align 4 %sexttmp = sext i32 %tmp to i64 %sexttmp1 = sext i32 %tmp1 to i64 %add = add nsw i64 %sexttmp1, %sexttmp ret i64 %add } +; CHECK-LABEL: ldp_half_sext_res0_int: +; CHECK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0] +; CHECK: sxtw x[[DST1]], w[[DST1]] +define i64 @ldp_half_sext_res0_int(i32* %p) nounwind { + %tmp = load i32, i32* %p, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i64 1 + %tmp1 = load i32, i32* %add.ptr, align 4 + %sexttmp = sext i32 %tmp to i64 + %sexttmp1 = zext i32 %tmp1 to i64 + %add = add nsw i64 %sexttmp1, %sexttmp + ret i64 %add +} + +; CHECK-LABEL: ldp_half_sext_res1_int: +; CHECK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0] +; CHECK: sxtw x[[DST2]], w[[DST2]] +define i64 @ldp_half_sext_res1_int(i32* %p) nounwind { + %tmp = load i32, i32* %p, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i64 1 + %tmp1 = load i32, i32* %add.ptr, align 4 + %sexttmp = zext i32 %tmp to i64 + %sexttmp1 = sext i32 %tmp1 to i64 + %add = add nsw i64 %sexttmp1, %sexttmp + ret i64 %add +} + + ; CHECK: ldp_long ; CHECK: ldp define i64 @ldp_long(i64* %p) nounwind { - %tmp = load i64* %p, align 8 - %add.ptr = getelementptr inbounds i64* %p, i64 1 - %tmp1 = load i64* %add.ptr, align 8 + %tmp = load i64, i64* %p, align 8 + %add.ptr = getelementptr inbounds i64, i64* %p, i64 1 + %tmp1 = load i64, i64* %add.ptr, align 8 %add = add nsw i64 %tmp1, %tmp ret i64 %add } @@ -37,9 +64,9 @@ define i64 @ldp_long(i64* %p) nounwind { ; CHECK: ldp_float ; CHECK: ldp define float @ldp_float(float* %p) nounwind { - %tmp = load float* %p, align 4 - %add.ptr = getelementptr inbounds float* %p, i64 1 - %tmp1 = load float* %add.ptr, align 4 + %tmp = load float, float* %p, align 4 + %add.ptr = getelementptr inbounds float, float* %p, i64 1 + %tmp1 = load float, float* %add.ptr, align 4 %add = fadd float %tmp, %tmp1 ret float %add } @@ -47,9 +74,9 @@ define float @ldp_float(float* %p) nounwind { ; CHECK: ldp_double ; CHECK: ldp define double @ldp_double(double* %p) nounwind { - %tmp = load double* %p, align 8 - %add.ptr = getelementptr inbounds double* %p, i64 1 - %tmp1 = load double* %add.ptr, align 8 + %tmp = load double, double* %p, align 8 + %add.ptr = getelementptr inbounds double, double* %p, i64 1 + %tmp1 = load double, double* %add.ptr, align 8 %add = fadd double %tmp, %tmp1 ret double %add } @@ -60,10 +87,10 @@ define i32 @ldur_int(i32* %a) nounwind { ; LDUR_CHK: ldp [[DST1:w[0-9]+]], [[DST2:w[0-9]+]], [x0, #-8] ; LDUR_CHK-NEXT: add w{{[0-9]+}}, [[DST2]], [[DST1]] ; LDUR_CHK-NEXT: ret - %p1 = getelementptr inbounds i32* %a, i32 -1 - %tmp1 = load i32* %p1, align 2 - %p2 = getelementptr inbounds i32* %a, i32 -2 - %tmp2 = load i32* %p2, align 2 + %p1 = getelementptr inbounds i32, i32* %a, i32 -1 + %tmp1 = load i32, i32* %p1, align 2 + %p2 = getelementptr inbounds i32, i32* %a, i32 -2 + %tmp2 = load i32, i32* %p2, align 2 %tmp3 = add i32 %tmp1, %tmp2 ret i32 %tmp3 } @@ -73,25 +100,58 @@ define i64 @ldur_sext_int(i32* %a) nounwind { ; LDUR_CHK: ldpsw [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-8] ; LDUR_CHK-NEXT: add x{{[0-9]+}}, [[DST2]], [[DST1]] ; LDUR_CHK-NEXT: ret - %p1 = getelementptr inbounds i32* %a, i32 -1 - %tmp1 = load i32* %p1, align 2 - %p2 = getelementptr inbounds i32* %a, i32 -2 - %tmp2 = load i32* %p2, align 2 + %p1 = getelementptr inbounds i32, i32* %a, i32 -1 + %tmp1 = load i32, i32* %p1, align 2 + %p2 = getelementptr inbounds i32, i32* %a, i32 -2 + %tmp2 = load i32, i32* %p2, align 2 %sexttmp1 = sext i32 %tmp1 to i64 %sexttmp2 = sext i32 %tmp2 to i64 %tmp3 = add i64 %sexttmp1, %sexttmp2 ret i64 %tmp3 } +define i64 @ldur_half_sext_int_res0(i32* %a) nounwind { +; LDUR_CHK: ldur_half_sext_int_res0 +; LDUR_CHK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0, #-8] +; LDUR_CHK: sxtw x[[DST1]], w[[DST1]] +; LDUR_CHK-NEXT: add x{{[0-9]+}}, x[[DST2]], x[[DST1]] +; LDUR_CHK-NEXT: ret + %p1 = getelementptr inbounds i32, i32* %a, i32 -1 + %tmp1 = load i32, i32* %p1, align 2 + %p2 = getelementptr inbounds i32, i32* %a, i32 -2 + %tmp2 = load i32, i32* %p2, align 2 + %sexttmp1 = zext i32 %tmp1 to i64 + %sexttmp2 = sext i32 %tmp2 to i64 + %tmp3 = add i64 %sexttmp1, %sexttmp2 + ret i64 %tmp3 +} + +define i64 @ldur_half_sext_int_res1(i32* %a) nounwind { +; LDUR_CHK: ldur_half_sext_int_res1 +; LDUR_CHK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0, #-8] +; LDUR_CHK: sxtw x[[DST2]], w[[DST2]] +; LDUR_CHK-NEXT: add x{{[0-9]+}}, x[[DST2]], x[[DST1]] +; LDUR_CHK-NEXT: ret + %p1 = getelementptr inbounds i32, i32* %a, i32 -1 + %tmp1 = load i32, i32* %p1, align 2 + %p2 = getelementptr inbounds i32, i32* %a, i32 -2 + %tmp2 = load i32, i32* %p2, align 2 + %sexttmp1 = sext i32 %tmp1 to i64 + %sexttmp2 = zext i32 %tmp2 to i64 + %tmp3 = add i64 %sexttmp1, %sexttmp2 + ret i64 %tmp3 +} + + define i64 @ldur_long(i64* %a) nounwind ssp { ; LDUR_CHK: ldur_long ; LDUR_CHK: ldp [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-16] ; LDUR_CHK-NEXT: add x{{[0-9]+}}, [[DST2]], [[DST1]] ; LDUR_CHK-NEXT: ret - %p1 = getelementptr inbounds i64* %a, i64 -1 - %tmp1 = load i64* %p1, align 2 - %p2 = getelementptr inbounds i64* %a, i64 -2 - %tmp2 = load i64* %p2, align 2 + %p1 = getelementptr inbounds i64, i64* %a, i64 -1 + %tmp1 = load i64, i64* %p1, align 2 + %p2 = getelementptr inbounds i64, i64* %a, i64 -2 + %tmp2 = load i64, i64* %p2, align 2 %tmp3 = add i64 %tmp1, %tmp2 ret i64 %tmp3 } @@ -101,10 +161,10 @@ define float @ldur_float(float* %a) { ; LDUR_CHK: ldp [[DST1:s[0-9]+]], [[DST2:s[0-9]+]], [x0, #-8] ; LDUR_CHK-NEXT: add s{{[0-9]+}}, [[DST2]], [[DST1]] ; LDUR_CHK-NEXT: ret - %p1 = getelementptr inbounds float* %a, i64 -1 - %tmp1 = load float* %p1, align 2 - %p2 = getelementptr inbounds float* %a, i64 -2 - %tmp2 = load float* %p2, align 2 + %p1 = getelementptr inbounds float, float* %a, i64 -1 + %tmp1 = load float, float* %p1, align 2 + %p2 = getelementptr inbounds float, float* %a, i64 -2 + %tmp2 = load float, float* %p2, align 2 %tmp3 = fadd float %tmp1, %tmp2 ret float %tmp3 } @@ -114,10 +174,10 @@ define double @ldur_double(double* %a) { ; LDUR_CHK: ldp [[DST1:d[0-9]+]], [[DST2:d[0-9]+]], [x0, #-16] ; LDUR_CHK-NEXT: add d{{[0-9]+}}, [[DST2]], [[DST1]] ; LDUR_CHK-NEXT: ret - %p1 = getelementptr inbounds double* %a, i64 -1 - %tmp1 = load double* %p1, align 2 - %p2 = getelementptr inbounds double* %a, i64 -2 - %tmp2 = load double* %p2, align 2 + %p1 = getelementptr inbounds double, double* %a, i64 -1 + %tmp1 = load double, double* %p1, align 2 + %p2 = getelementptr inbounds double, double* %a, i64 -2 + %tmp2 = load double, double* %p2, align 2 %tmp3 = fadd double %tmp1, %tmp2 ret double %tmp3 } @@ -129,10 +189,10 @@ define i64 @pairUpBarelyIn(i64* %a) nounwind ssp { ; LDUR_CHK: ldp [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-256] ; LDUR_CHK-NEXT: add x{{[0-9]+}}, [[DST2]], [[DST1]] ; LDUR_CHK-NEXT: ret - %p1 = getelementptr inbounds i64* %a, i64 -31 - %tmp1 = load i64* %p1, align 2 - %p2 = getelementptr inbounds i64* %a, i64 -32 - %tmp2 = load i64* %p2, align 2 + %p1 = getelementptr inbounds i64, i64* %a, i64 -31 + %tmp1 = load i64, i64* %p1, align 2 + %p2 = getelementptr inbounds i64, i64* %a, i64 -32 + %tmp2 = load i64, i64* %p2, align 2 %tmp3 = add i64 %tmp1, %tmp2 ret i64 %tmp3 } @@ -143,16 +203,50 @@ define i64 @pairUpBarelyInSext(i32* %a) nounwind ssp { ; LDUR_CHK: ldpsw [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-256] ; LDUR_CHK-NEXT: add x{{[0-9]+}}, [[DST2]], [[DST1]] ; LDUR_CHK-NEXT: ret - %p1 = getelementptr inbounds i32* %a, i64 -63 - %tmp1 = load i32* %p1, align 2 - %p2 = getelementptr inbounds i32* %a, i64 -64 - %tmp2 = load i32* %p2, align 2 + %p1 = getelementptr inbounds i32, i32* %a, i64 -63 + %tmp1 = load i32, i32* %p1, align 2 + %p2 = getelementptr inbounds i32, i32* %a, i64 -64 + %tmp2 = load i32, i32* %p2, align 2 %sexttmp1 = sext i32 %tmp1 to i64 %sexttmp2 = sext i32 %tmp2 to i64 %tmp3 = add i64 %sexttmp1, %sexttmp2 ret i64 %tmp3 } +define i64 @pairUpBarelyInHalfSextRes0(i32* %a) nounwind ssp { +; LDUR_CHK: pairUpBarelyInHalfSextRes0 +; LDUR_CHK-NOT: ldur +; LDUR_CHK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0, #-256] +; LDUR_CHK: sxtw x[[DST1]], w[[DST1]] +; LDUR_CHK-NEXT: add x{{[0-9]+}}, x[[DST2]], x[[DST1]] +; LDUR_CHK-NEXT: ret + %p1 = getelementptr inbounds i32, i32* %a, i64 -63 + %tmp1 = load i32, i32* %p1, align 2 + %p2 = getelementptr inbounds i32, i32* %a, i64 -64 + %tmp2 = load i32, i32* %p2, align 2 + %sexttmp1 = zext i32 %tmp1 to i64 + %sexttmp2 = sext i32 %tmp2 to i64 + %tmp3 = add i64 %sexttmp1, %sexttmp2 + ret i64 %tmp3 +} + +define i64 @pairUpBarelyInHalfSextRes1(i32* %a) nounwind ssp { +; LDUR_CHK: pairUpBarelyInHalfSextRes1 +; LDUR_CHK-NOT: ldur +; LDUR_CHK: ldp w[[DST1:[0-9]+]], w[[DST2:[0-9]+]], [x0, #-256] +; LDUR_CHK: sxtw x[[DST2]], w[[DST2]] +; LDUR_CHK-NEXT: add x{{[0-9]+}}, x[[DST2]], x[[DST1]] +; LDUR_CHK-NEXT: ret + %p1 = getelementptr inbounds i32, i32* %a, i64 -63 + %tmp1 = load i32, i32* %p1, align 2 + %p2 = getelementptr inbounds i32, i32* %a, i64 -64 + %tmp2 = load i32, i32* %p2, align 2 + %sexttmp1 = sext i32 %tmp1 to i64 + %sexttmp2 = zext i32 %tmp2 to i64 + %tmp3 = add i64 %sexttmp1, %sexttmp2 + ret i64 %tmp3 +} + define i64 @pairUpBarelyOut(i64* %a) nounwind ssp { ; LDUR_CHK: pairUpBarelyOut ; LDUR_CHK-NOT: ldp @@ -160,10 +254,10 @@ define i64 @pairUpBarelyOut(i64* %a) nounwind ssp { ; are used---just check that there isn't an ldp before the add ; LDUR_CHK: add ; LDUR_CHK-NEXT: ret - %p1 = getelementptr inbounds i64* %a, i64 -32 - %tmp1 = load i64* %p1, align 2 - %p2 = getelementptr inbounds i64* %a, i64 -33 - %tmp2 = load i64* %p2, align 2 + %p1 = getelementptr inbounds i64, i64* %a, i64 -32 + %tmp1 = load i64, i64* %p1, align 2 + %p2 = getelementptr inbounds i64, i64* %a, i64 -33 + %tmp2 = load i64, i64* %p2, align 2 %tmp3 = add i64 %tmp1, %tmp2 ret i64 %tmp3 } @@ -175,10 +269,10 @@ define i64 @pairUpBarelyOutSext(i32* %a) nounwind ssp { ; are used---just check that there isn't an ldp before the add ; LDUR_CHK: add ; LDUR_CHK-NEXT: ret - %p1 = getelementptr inbounds i32* %a, i64 -64 - %tmp1 = load i32* %p1, align 2 - %p2 = getelementptr inbounds i32* %a, i64 -65 - %tmp2 = load i32* %p2, align 2 + %p1 = getelementptr inbounds i32, i32* %a, i64 -64 + %tmp1 = load i32, i32* %p1, align 2 + %p2 = getelementptr inbounds i32, i32* %a, i64 -65 + %tmp2 = load i32, i32* %p2, align 2 %sexttmp1 = sext i32 %tmp1 to i64 %sexttmp2 = sext i32 %tmp2 to i64 %tmp3 = add i64 %sexttmp1, %sexttmp2 @@ -192,17 +286,17 @@ define i64 @pairUpNotAligned(i64* %a) nounwind ssp { ; LDUR_CHK-NEXT: ldur ; LDUR_CHK-NEXT: add ; LDUR_CHK-NEXT: ret - %p1 = getelementptr inbounds i64* %a, i64 -18 + %p1 = getelementptr inbounds i64, i64* %a, i64 -18 %bp1 = bitcast i64* %p1 to i8* - %bp1p1 = getelementptr inbounds i8* %bp1, i64 1 + %bp1p1 = getelementptr inbounds i8, i8* %bp1, i64 1 %dp1 = bitcast i8* %bp1p1 to i64* - %tmp1 = load i64* %dp1, align 1 + %tmp1 = load i64, i64* %dp1, align 1 - %p2 = getelementptr inbounds i64* %a, i64 -17 + %p2 = getelementptr inbounds i64, i64* %a, i64 -17 %bp2 = bitcast i64* %p2 to i8* - %bp2p1 = getelementptr inbounds i8* %bp2, i64 1 + %bp2p1 = getelementptr inbounds i8, i8* %bp2, i64 1 %dp2 = bitcast i8* %bp2p1 to i64* - %tmp2 = load i64* %dp2, align 1 + %tmp2 = load i64, i64* %dp2, align 1 %tmp3 = add i64 %tmp1, %tmp2 ret i64 %tmp3 @@ -215,17 +309,17 @@ define i64 @pairUpNotAlignedSext(i32* %a) nounwind ssp { ; LDUR_CHK-NEXT: ldursw ; LDUR_CHK-NEXT: add ; LDUR_CHK-NEXT: ret - %p1 = getelementptr inbounds i32* %a, i64 -18 + %p1 = getelementptr inbounds i32, i32* %a, i64 -18 %bp1 = bitcast i32* %p1 to i8* - %bp1p1 = getelementptr inbounds i8* %bp1, i64 1 + %bp1p1 = getelementptr inbounds i8, i8* %bp1, i64 1 %dp1 = bitcast i8* %bp1p1 to i32* - %tmp1 = load i32* %dp1, align 1 + %tmp1 = load i32, i32* %dp1, align 1 - %p2 = getelementptr inbounds i32* %a, i64 -17 + %p2 = getelementptr inbounds i32, i32* %a, i64 -17 %bp2 = bitcast i32* %p2 to i8* - %bp2p1 = getelementptr inbounds i8* %bp2, i64 1 + %bp2p1 = getelementptr inbounds i8, i8* %bp2, i64 1 %dp2 = bitcast i8* %bp2p1 to i32* - %tmp2 = load i32* %dp2, align 1 + %tmp2 = load i32, i32* %dp2, align 1 %sexttmp1 = sext i32 %tmp1 to i64 %sexttmp2 = sext i32 %tmp2 to i64 diff --git a/test/CodeGen/AArch64/arm64-ldur.ll b/test/CodeGen/AArch64/arm64-ldur.ll index 2848c06..c4bf397 100644 --- a/test/CodeGen/AArch64/arm64-ldur.ll +++ b/test/CodeGen/AArch64/arm64-ldur.ll @@ -4,32 +4,32 @@ define i64 @_f0(i64* %p) { ; CHECK: f0: ; CHECK: ldur x0, [x0, #-8] ; CHECK-NEXT: ret - %tmp = getelementptr inbounds i64* %p, i64 -1 - %ret = load i64* %tmp, align 2 + %tmp = getelementptr inbounds i64, i64* %p, i64 -1 + %ret = load i64, i64* %tmp, align 2 ret i64 %ret } define i32 @_f1(i32* %p) { ; CHECK: f1: ; CHECK: ldur w0, [x0, #-4] ; CHECK-NEXT: ret - %tmp = getelementptr inbounds i32* %p, i64 -1 - %ret = load i32* %tmp, align 2 + %tmp = getelementptr inbounds i32, i32* %p, i64 -1 + %ret = load i32, i32* %tmp, align 2 ret i32 %ret } define i16 @_f2(i16* %p) { ; CHECK: f2: ; CHECK: ldurh w0, [x0, #-2] ; CHECK-NEXT: ret - %tmp = getelementptr inbounds i16* %p, i64 -1 - %ret = load i16* %tmp, align 2 + %tmp = getelementptr inbounds i16, i16* %p, i64 -1 + %ret = load i16, i16* %tmp, align 2 ret i16 %ret } define i8 @_f3(i8* %p) { ; CHECK: f3: ; CHECK: ldurb w0, [x0, #-1] ; CHECK-NEXT: ret - %tmp = getelementptr inbounds i8* %p, i64 -1 - %ret = load i8* %tmp, align 2 + %tmp = getelementptr inbounds i8, i8* %p, i64 -1 + %ret = load i8, i8* %tmp, align 2 ret i8 %ret } @@ -37,9 +37,9 @@ define i64 @zext32(i8* %a) nounwind ssp { ; CHECK-LABEL: zext32: ; CHECK: ldur w0, [x0, #-12] ; CHECK-NEXT: ret - %p = getelementptr inbounds i8* %a, i64 -12 + %p = getelementptr inbounds i8, i8* %a, i64 -12 %tmp1 = bitcast i8* %p to i32* - %tmp2 = load i32* %tmp1, align 4 + %tmp2 = load i32, i32* %tmp1, align 4 %ret = zext i32 %tmp2 to i64 ret i64 %ret @@ -48,9 +48,9 @@ define i64 @zext16(i8* %a) nounwind ssp { ; CHECK-LABEL: zext16: ; CHECK: ldurh w0, [x0, #-12] ; CHECK-NEXT: ret - %p = getelementptr inbounds i8* %a, i64 -12 + %p = getelementptr inbounds i8, i8* %a, i64 -12 %tmp1 = bitcast i8* %p to i16* - %tmp2 = load i16* %tmp1, align 2 + %tmp2 = load i16, i16* %tmp1, align 2 %ret = zext i16 %tmp2 to i64 ret i64 %ret @@ -59,8 +59,8 @@ define i64 @zext8(i8* %a) nounwind ssp { ; CHECK-LABEL: zext8: ; CHECK: ldurb w0, [x0, #-12] ; CHECK-NEXT: ret - %p = getelementptr inbounds i8* %a, i64 -12 - %tmp2 = load i8* %p, align 1 + %p = getelementptr inbounds i8, i8* %a, i64 -12 + %tmp2 = load i8, i8* %p, align 1 %ret = zext i8 %tmp2 to i64 ret i64 %ret diff --git a/test/CodeGen/AArch64/arm64-memcpy-inline.ll b/test/CodeGen/AArch64/arm64-memcpy-inline.ll index f921a59..2f91ce2 100644 --- a/test/CodeGen/AArch64/arm64-memcpy-inline.ll +++ b/test/CodeGen/AArch64/arm64-memcpy-inline.ll @@ -22,7 +22,7 @@ entry: ; CHECK: strh [[REG1]], [x[[BASEREG2]], #8] ; CHECK: ldr [[REG2:x[0-9]+]], ; CHECK: str [[REG2]], - call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.x* @dst, i32 0, i32 0), i8* getelementptr inbounds (%struct.x* @src, i32 0, i32 0), i32 11, i32 8, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.x, %struct.x* @dst, i32 0, i32 0), i8* getelementptr inbounds (%struct.x, %struct.x* @src, i32 0, i32 0), i32 11, i32 8, i1 false) ret i32 0 } @@ -33,7 +33,7 @@ entry: ; CHECK: stur [[DEST]], [x0, #15] ; CHECK: ldr [[DEST:q[0-9]+]], [x[[BASEREG]]] ; CHECK: str [[DEST]], [x0] - tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([31 x i8]* @.str1, i64 0, i64 0), i64 31, i32 1, i1 false) + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str1, i64 0, i64 0), i64 31, i32 1, i1 false) ret void } @@ -45,7 +45,7 @@ entry: ; CHECK: str [[REG3]], [x0, #32] ; CHECK: ldp [[DEST1:q[0-9]+]], [[DEST2:q[0-9]+]], [x{{[0-9]+}}] ; CHECK: stp [[DEST1]], [[DEST2]], [x0] - tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false) + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8], [36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false) ret void } @@ -56,7 +56,7 @@ entry: ; CHECK: str [[REG4]], [x0, #16] ; CHECK: ldr [[DEST:q[0-9]+]], [x[[BASEREG]]] ; CHECK: str [[DEST]], [x0] - tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false) + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8], [24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false) ret void } @@ -67,7 +67,7 @@ entry: ; CHECK: strh [[REG5]], [x0, #16] ; CHECK: ldr [[REG6:q[0-9]+]], [x{{[0-9]+}}] ; CHECK: str [[REG6]], [x0] - tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false) + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false) ret void } @@ -80,7 +80,7 @@ entry: ; CHECK: movz [[REG8:w[0-9]+]], ; CHECK: movk [[REG8]], ; CHECK: str [[REG8]], [x0] - tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([7 x i8]* @.str5, i64 0, i64 0), i64 7, i32 1, i1 false) + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str5, i64 0, i64 0), i64 7, i32 1, i1 false) ret void } @@ -91,7 +91,7 @@ entry: ; CHECK: stur [[REG9]], [x{{[0-9]+}}, #6] ; CHECK: ldr ; CHECK: str - call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([512 x i8]* @spool.splbuf, i64 0, i64 0), i8* getelementptr inbounds ([14 x i8]* @.str6, i64 0, i64 0), i64 14, i32 1, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([512 x i8], [512 x i8]* @spool.splbuf, i64 0, i64 0), i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str6, i64 0, i64 0), i64 14, i32 1, i1 false) ret void } diff --git a/test/CodeGen/AArch64/arm64-memset-inline.ll b/test/CodeGen/AArch64/arm64-memset-inline.ll index 2e237f4..56959ad 100644 --- a/test/CodeGen/AArch64/arm64-memset-inline.ll +++ b/test/CodeGen/AArch64/arm64-memset-inline.ll @@ -16,7 +16,7 @@ entry: ; CHECK: stp xzr, xzr, [sp, #16] ; CHECK: str xzr, [sp, #8] %buf = alloca [26 x i8], align 1 - %0 = getelementptr inbounds [26 x i8]* %buf, i32 0, i32 0 + %0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0 call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i32 1, i1 false) call void @something(i8* %0) nounwind ret void diff --git a/test/CodeGen/AArch64/arm64-misched-basic-A53.ll b/test/CodeGen/AArch64/arm64-misched-basic-A53.ll index bc7ed7f..6db2104 100644 --- a/test/CodeGen/AArch64/arm64-misched-basic-A53.ll +++ b/test/CodeGen/AArch64/arm64-misched-basic-A53.ll @@ -34,44 +34,44 @@ entry: br label %for.cond for.cond: ; preds = %for.inc, %entry - %2 = load i32* %i, align 4 + %2 = load i32, i32* %i, align 4 %cmp = icmp slt i32 %2, 8 br i1 %cmp, label %for.body, label %for.end for.body: ; preds = %for.cond - %3 = load i32* %i, align 4 + %3 = load i32, i32* %i, align 4 %idxprom = sext i32 %3 to i64 - %arrayidx = getelementptr inbounds [8 x i32]* %x, i32 0, i64 %idxprom - %4 = load i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds [8 x i32], [8 x i32]* %x, i32 0, i64 %idxprom + %4 = load i32, i32* %arrayidx, align 4 %add = add nsw i32 %4, 1 store i32 %add, i32* %xx, align 4 - %5 = load i32* %xx, align 4 + %5 = load i32, i32* %xx, align 4 %add1 = add nsw i32 %5, 12 store i32 %add1, i32* %xx, align 4 - %6 = load i32* %xx, align 4 + %6 = load i32, i32* %xx, align 4 %add2 = add nsw i32 %6, 23 store i32 %add2, i32* %xx, align 4 - %7 = load i32* %xx, align 4 + %7 = load i32, i32* %xx, align 4 %add3 = add nsw i32 %7, 34 store i32 %add3, i32* %xx, align 4 - %8 = load i32* %i, align 4 + %8 = load i32, i32* %i, align 4 %idxprom4 = sext i32 %8 to i64 - %arrayidx5 = getelementptr inbounds [8 x i32]* %y, i32 0, i64 %idxprom4 - %9 = load i32* %arrayidx5, align 4 - %10 = load i32* %yy, align 4 + %arrayidx5 = getelementptr inbounds [8 x i32], [8 x i32]* %y, i32 0, i64 %idxprom4 + %9 = load i32, i32* %arrayidx5, align 4 + %10 = load i32, i32* %yy, align 4 %mul = mul nsw i32 %10, %9 store i32 %mul, i32* %yy, align 4 br label %for.inc for.inc: ; preds = %for.body - %11 = load i32* %i, align 4 + %11 = load i32, i32* %i, align 4 %inc = add nsw i32 %11, 1 store i32 %inc, i32* %i, align 4 br label %for.cond for.end: ; preds = %for.cond - %12 = load i32* %xx, align 4 - %13 = load i32* %yy, align 4 + %12 = load i32, i32* %xx, align 4 + %13 = load i32, i32* %yy, align 4 %add6 = add nsw i32 %12, %13 ret i32 %add6 } @@ -116,7 +116,7 @@ attributes #1 = { nounwind } ; Nothing explicit to check other than llc not crashing. define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(i8* %A, i8** %ptr) { %ld2 = tail call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2.v16i8.p0i8(i8* %A) - %tmp = getelementptr i8* %A, i32 32 + %tmp = getelementptr i8, i8* %A, i32 32 store i8* %tmp, i8** %ptr ret { <16 x i8>, <16 x i8> } %ld2 } diff --git a/test/CodeGen/AArch64/arm64-misched-basic-A57.ll b/test/CodeGen/AArch64/arm64-misched-basic-A57.ll index 238474a..fac5f8a 100644 --- a/test/CodeGen/AArch64/arm64-misched-basic-A57.ll +++ b/test/CodeGen/AArch64/arm64-misched-basic-A57.ll @@ -9,8 +9,8 @@ ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s ; CHECK: ********** MI Scheduling ********** ; CHECK: main:BB#2 -; CHECK LDR -; CHECK Latency : 4 +; CHECK: LDR +; CHECK: Latency : 4 ; CHECK: *** Final schedule for BB#2 *** ; CHECK: LDR ; CHECK: LDR @@ -41,31 +41,31 @@ entry: br label %for.cond for.cond: ; preds = %for.inc, %entry - %2 = load i32* %i, align 4 + %2 = load i32, i32* %i, align 4 %cmp = icmp slt i32 %2, 8 br i1 %cmp, label %for.body, label %for.end for.body: ; preds = %for.cond - %3 = load i32* %yy, align 4 - %4 = load i32* %i, align 4 + %3 = load i32, i32* %yy, align 4 + %4 = load i32, i32* %i, align 4 %idxprom = sext i32 %4 to i64 - %arrayidx = getelementptr inbounds [8 x i32]* %x, i32 0, i64 %idxprom - %5 = load i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds [8 x i32], [8 x i32]* %x, i32 0, i64 %idxprom + %5 = load i32, i32* %arrayidx, align 4 %add = add nsw i32 %5, 1 store i32 %add, i32* %xx, align 4 - %6 = load i32* %xx, align 4 + %6 = load i32, i32* %xx, align 4 %add1 = add nsw i32 %6, 12 store i32 %add1, i32* %xx, align 4 - %7 = load i32* %xx, align 4 + %7 = load i32, i32* %xx, align 4 %add2 = add nsw i32 %7, 23 store i32 %add2, i32* %xx, align 4 - %8 = load i32* %xx, align 4 + %8 = load i32, i32* %xx, align 4 %add3 = add nsw i32 %8, 34 store i32 %add3, i32* %xx, align 4 - %9 = load i32* %i, align 4 + %9 = load i32, i32* %i, align 4 %idxprom4 = sext i32 %9 to i64 - %arrayidx5 = getelementptr inbounds [8 x i32]* %y, i32 0, i64 %idxprom4 - %10 = load i32* %arrayidx5, align 4 + %arrayidx5 = getelementptr inbounds [8 x i32], [8 x i32]* %y, i32 0, i64 %idxprom4 + %10 = load i32, i32* %arrayidx5, align 4 %add4 = add nsw i32 %9, %add %add5 = add nsw i32 %10, %add1 @@ -92,14 +92,14 @@ for.body: ; preds = %for.cond br label %for.inc for.inc: ; preds = %for.body - %11 = load i32* %i, align 4 + %11 = load i32, i32* %i, align 4 %inc = add nsw i32 %11, 1 store i32 %inc, i32* %i, align 4 br label %for.cond for.end: ; preds = %for.cond - %12 = load i32* %xx, align 4 - %13 = load i32* %yy, align 4 + %12 = load i32, i32* %xx, align 4 + %13 = load i32, i32* %yy, align 4 %add67 = add nsw i32 %12, %13 ret i32 %add67 } diff --git a/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll b/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll index cca6bfe..b63200e 100644 --- a/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll +++ b/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll @@ -126,7 +126,7 @@ define <16 x i8> @test_vld1q_dup_s8(i8* %a) { ; CHECK-LABEL: test_vld1q_dup_s8: ; CHECK: ld1r {{{ ?v[0-9]+.16b ?}}}, [x0] entry: - %0 = load i8* %a, align 1 + %0 = load i8, i8* %a, align 1 %1 = insertelement <16 x i8> undef, i8 %0, i32 0 %lane = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> zeroinitializer ret <16 x i8> %lane @@ -136,7 +136,7 @@ define <8 x i16> @test_vld1q_dup_s16(i16* %a) { ; CHECK-LABEL: test_vld1q_dup_s16: ; CHECK: ld1r {{{ ?v[0-9]+.8h ?}}}, [x0] entry: - %0 = load i16* %a, align 2 + %0 = load i16, i16* %a, align 2 %1 = insertelement <8 x i16> undef, i16 %0, i32 0 %lane = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> zeroinitializer ret <8 x i16> %lane @@ -146,7 +146,7 @@ define <4 x i32> @test_vld1q_dup_s32(i32* %a) { ; CHECK-LABEL: test_vld1q_dup_s32: ; CHECK: ld1r {{{ ?v[0-9]+.4s ?}}}, [x0] entry: - %0 = load i32* %a, align 4 + %0 = load i32, i32* %a, align 4 %1 = insertelement <4 x i32> undef, i32 %0, i32 0 %lane = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> zeroinitializer ret <4 x i32> %lane @@ -156,7 +156,7 @@ define <2 x i64> @test_vld1q_dup_s64(i64* %a) { ; CHECK-LABEL: test_vld1q_dup_s64: ; CHECK: ld1r {{{ ?v[0-9]+.2d ?}}}, [x0] entry: - %0 = load i64* %a, align 8 + %0 = load i64, i64* %a, align 8 %1 = insertelement <2 x i64> undef, i64 %0, i32 0 %lane = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> zeroinitializer ret <2 x i64> %lane @@ -166,7 +166,7 @@ define <4 x float> @test_vld1q_dup_f32(float* %a) { ; CHECK-LABEL: test_vld1q_dup_f32: ; CHECK: ld1r {{{ ?v[0-9]+.4s ?}}}, [x0] entry: - %0 = load float* %a, align 4 + %0 = load float, float* %a, align 4 %1 = insertelement <4 x float> undef, float %0, i32 0 %lane = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> zeroinitializer ret <4 x float> %lane @@ -176,7 +176,7 @@ define <2 x double> @test_vld1q_dup_f64(double* %a) { ; CHECK-LABEL: test_vld1q_dup_f64: ; CHECK: ld1r {{{ ?v[0-9]+.2d ?}}}, [x0] entry: - %0 = load double* %a, align 8 + %0 = load double, double* %a, align 8 %1 = insertelement <2 x double> undef, double %0, i32 0 %lane = shufflevector <2 x double> %1, <2 x double> undef, <2 x i32> zeroinitializer ret <2 x double> %lane @@ -186,7 +186,7 @@ define <8 x i8> @test_vld1_dup_s8(i8* %a) { ; CHECK-LABEL: test_vld1_dup_s8: ; CHECK: ld1r {{{ ?v[0-9]+.8b ?}}}, [x0] entry: - %0 = load i8* %a, align 1 + %0 = load i8, i8* %a, align 1 %1 = insertelement <8 x i8> undef, i8 %0, i32 0 %lane = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer ret <8 x i8> %lane @@ -196,7 +196,7 @@ define <4 x i16> @test_vld1_dup_s16(i16* %a) { ; CHECK-LABEL: test_vld1_dup_s16: ; CHECK: ld1r {{{ ?v[0-9]+.4h ?}}}, [x0] entry: - %0 = load i16* %a, align 2 + %0 = load i16, i16* %a, align 2 %1 = insertelement <4 x i16> undef, i16 %0, i32 0 %lane = shufflevector <4 x i16> %1, <4 x i16> undef, <4 x i32> zeroinitializer ret <4 x i16> %lane @@ -206,7 +206,7 @@ define <2 x i32> @test_vld1_dup_s32(i32* %a) { ; CHECK-LABEL: test_vld1_dup_s32: ; CHECK: ld1r {{{ ?v[0-9]+.2s ?}}}, [x0] entry: - %0 = load i32* %a, align 4 + %0 = load i32, i32* %a, align 4 %1 = insertelement <2 x i32> undef, i32 %0, i32 0 %lane = shufflevector <2 x i32> %1, <2 x i32> undef, <2 x i32> zeroinitializer ret <2 x i32> %lane @@ -216,7 +216,7 @@ define <1 x i64> @test_vld1_dup_s64(i64* %a) { ; CHECK-LABEL: test_vld1_dup_s64: ; CHECK: ldr {{d[0-9]+}}, [x0] entry: - %0 = load i64* %a, align 8 + %0 = load i64, i64* %a, align 8 %1 = insertelement <1 x i64> undef, i64 %0, i32 0 ret <1 x i64> %1 } @@ -225,7 +225,7 @@ define <2 x float> @test_vld1_dup_f32(float* %a) { ; CHECK-LABEL: test_vld1_dup_f32: ; CHECK: ld1r {{{ ?v[0-9]+.2s ?}}}, [x0] entry: - %0 = load float* %a, align 4 + %0 = load float, float* %a, align 4 %1 = insertelement <2 x float> undef, float %0, i32 0 %lane = shufflevector <2 x float> %1, <2 x float> undef, <2 x i32> zeroinitializer ret <2 x float> %lane @@ -235,7 +235,7 @@ define <1 x double> @test_vld1_dup_f64(double* %a) { ; CHECK-LABEL: test_vld1_dup_f64: ; CHECK: ldr {{d[0-9]+}}, [x0] entry: - %0 = load double* %a, align 8 + %0 = load double, double* %a, align 8 %1 = insertelement <1 x double> undef, double %0, i32 0 ret <1 x double> %1 } @@ -247,7 +247,7 @@ define <1 x i64> @testDUP.v1i64(i64* %a, i64* %b) #0 { ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}] ; CHECK-DAG: fmov {{d[0-9]+}}, {{x[0-9]+}} ; CHECK-DAG: str {{x[0-9]+}}, [{{x[0-9]+}}] - %1 = load i64* %a, align 8 + %1 = load i64, i64* %a, align 8 store i64 %1, i64* %b, align 8 %vecinit.i = insertelement <1 x i64> undef, i64 %1, i32 0 ret <1 x i64> %vecinit.i @@ -259,7 +259,7 @@ define <1 x double> @testDUP.v1f64(double* %a, double* %b) #0 { ; CHECK-LABEL: testDUP.v1f64: ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}] ; CHECK: str {{d[0-9]+}}, [{{x[0-9]+}}] - %1 = load double* %a, align 8 + %1 = load double, double* %a, align 8 store double %1, double* %b, align 8 %vecinit.i = insertelement <1 x double> undef, double %1, i32 0 ret <1 x double> %vecinit.i @@ -269,7 +269,7 @@ define <16 x i8> @test_vld1q_lane_s8(i8* %a, <16 x i8> %b) { ; CHECK-LABEL: test_vld1q_lane_s8: ; CHECK: ld1 { {{v[0-9]+}}.b }[{{[0-9]+}}], [x0] entry: - %0 = load i8* %a, align 1 + %0 = load i8, i8* %a, align 1 %vld1_lane = insertelement <16 x i8> %b, i8 %0, i32 15 ret <16 x i8> %vld1_lane } @@ -278,7 +278,7 @@ define <8 x i16> @test_vld1q_lane_s16(i16* %a, <8 x i16> %b) { ; CHECK-LABEL: test_vld1q_lane_s16: ; CHECK: ld1 { {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: - %0 = load i16* %a, align 2 + %0 = load i16, i16* %a, align 2 %vld1_lane = insertelement <8 x i16> %b, i16 %0, i32 7 ret <8 x i16> %vld1_lane } @@ -287,7 +287,7 @@ define <4 x i32> @test_vld1q_lane_s32(i32* %a, <4 x i32> %b) { ; CHECK-LABEL: test_vld1q_lane_s32: ; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: - %0 = load i32* %a, align 4 + %0 = load i32, i32* %a, align 4 %vld1_lane = insertelement <4 x i32> %b, i32 %0, i32 3 ret <4 x i32> %vld1_lane } @@ -296,7 +296,7 @@ define <2 x i64> @test_vld1q_lane_s64(i64* %a, <2 x i64> %b) { ; CHECK-LABEL: test_vld1q_lane_s64: ; CHECK: ld1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: - %0 = load i64* %a, align 8 + %0 = load i64, i64* %a, align 8 %vld1_lane = insertelement <2 x i64> %b, i64 %0, i32 1 ret <2 x i64> %vld1_lane } @@ -305,7 +305,7 @@ define <4 x float> @test_vld1q_lane_f32(float* %a, <4 x float> %b) { ; CHECK-LABEL: test_vld1q_lane_f32: ; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: - %0 = load float* %a, align 4 + %0 = load float, float* %a, align 4 %vld1_lane = insertelement <4 x float> %b, float %0, i32 3 ret <4 x float> %vld1_lane } @@ -314,7 +314,7 @@ define <2 x double> @test_vld1q_lane_f64(double* %a, <2 x double> %b) { ; CHECK-LABEL: test_vld1q_lane_f64: ; CHECK: ld1 { {{v[0-9]+}}.d }[{{[0-9]+}}], [x0] entry: - %0 = load double* %a, align 8 + %0 = load double, double* %a, align 8 %vld1_lane = insertelement <2 x double> %b, double %0, i32 1 ret <2 x double> %vld1_lane } @@ -323,7 +323,7 @@ define <8 x i8> @test_vld1_lane_s8(i8* %a, <8 x i8> %b) { ; CHECK-LABEL: test_vld1_lane_s8: ; CHECK: ld1 { {{v[0-9]+}}.b }[{{[0-9]+}}], [x0] entry: - %0 = load i8* %a, align 1 + %0 = load i8, i8* %a, align 1 %vld1_lane = insertelement <8 x i8> %b, i8 %0, i32 7 ret <8 x i8> %vld1_lane } @@ -332,7 +332,7 @@ define <4 x i16> @test_vld1_lane_s16(i16* %a, <4 x i16> %b) { ; CHECK-LABEL: test_vld1_lane_s16: ; CHECK: ld1 { {{v[0-9]+}}.h }[{{[0-9]+}}], [x0] entry: - %0 = load i16* %a, align 2 + %0 = load i16, i16* %a, align 2 %vld1_lane = insertelement <4 x i16> %b, i16 %0, i32 3 ret <4 x i16> %vld1_lane } @@ -341,7 +341,7 @@ define <2 x i32> @test_vld1_lane_s32(i32* %a, <2 x i32> %b) { ; CHECK-LABEL: test_vld1_lane_s32: ; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: - %0 = load i32* %a, align 4 + %0 = load i32, i32* %a, align 4 %vld1_lane = insertelement <2 x i32> %b, i32 %0, i32 1 ret <2 x i32> %vld1_lane } @@ -350,7 +350,7 @@ define <1 x i64> @test_vld1_lane_s64(i64* %a, <1 x i64> %b) { ; CHECK-LABEL: test_vld1_lane_s64: ; CHECK: ldr {{d[0-9]+}}, [x0] entry: - %0 = load i64* %a, align 8 + %0 = load i64, i64* %a, align 8 %vld1_lane = insertelement <1 x i64> undef, i64 %0, i32 0 ret <1 x i64> %vld1_lane } @@ -359,7 +359,7 @@ define <2 x float> @test_vld1_lane_f32(float* %a, <2 x float> %b) { ; CHECK-LABEL: test_vld1_lane_f32: ; CHECK: ld1 { {{v[0-9]+}}.s }[{{[0-9]+}}], [x0] entry: - %0 = load float* %a, align 4 + %0 = load float, float* %a, align 4 %vld1_lane = insertelement <2 x float> %b, float %0, i32 1 ret <2 x float> %vld1_lane } @@ -368,7 +368,7 @@ define <1 x double> @test_vld1_lane_f64(double* %a, <1 x double> %b) { ; CHECK-LABEL: test_vld1_lane_f64: ; CHECK: ldr {{d[0-9]+}}, [x0] entry: - %0 = load double* %a, align 8 + %0 = load double, double* %a, align 8 %vld1_lane = insertelement <1 x double> undef, double %0, i32 0 ret <1 x double> %vld1_lane } diff --git a/test/CodeGen/AArch64/arm64-patchpoint-scratch-regs.ll b/test/CodeGen/AArch64/arm64-patchpoint-scratch-regs.ll index d39722b..5a740d8 100644 --- a/test/CodeGen/AArch64/arm64-patchpoint-scratch-regs.ll +++ b/test/CodeGen/AArch64/arm64-patchpoint-scratch-regs.ll @@ -7,7 +7,7 @@ ; CHECK-NEXT: Ltmp ; CHECK-NEXT: nop define void @clobberScratch(i32* %p) { - %v = load i32* %p + %v = load i32, i32* %p tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 5, i32 20, i8* null, i32 0, i32* %p, i32 %v) store i32 %v, i32* %p diff --git a/test/CodeGen/AArch64/arm64-patchpoint.ll b/test/CodeGen/AArch64/arm64-patchpoint.ll index 278cba5..cf06653 100644 --- a/test/CodeGen/AArch64/arm64-patchpoint.ll +++ b/test/CodeGen/AArch64/arm64-patchpoint.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone < %s | FileCheck %s -; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -fast-isel -fast-isel-abort < %s | FileCheck %s +; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -fast-isel -fast-isel-abort=1 < %s | FileCheck %s ; Trivial patchpoint codegen ; @@ -50,13 +50,13 @@ define i64 @testLowerConstant(i64 %arg, i64 %tmp2, i64 %tmp10, i64* %tmp33, i64 entry: %tmp80 = add i64 %tmp79, -16 %tmp81 = inttoptr i64 %tmp80 to i64* - %tmp82 = load i64* %tmp81, align 8 + %tmp82 = load i64, i64* %tmp81, align 8 tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 14, i32 8, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82) tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 15, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82) - %tmp83 = load i64* %tmp33, align 8 + %tmp83 = load i64, i64* %tmp33, align 8 %tmp84 = add i64 %tmp83, -24 %tmp85 = inttoptr i64 %tmp84 to i64* - %tmp86 = load i64* %tmp85, align 8 + %tmp86 = load i64, i64* %tmp85, align 8 tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 17, i32 8, i64 %arg, i64 %tmp10, i64 %tmp86) tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 18, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86) ret i64 10 diff --git a/test/CodeGen/AArch64/arm64-pic-local-symbol.ll b/test/CodeGen/AArch64/arm64-pic-local-symbol.ll index 627e741..dae243e 100644 --- a/test/CodeGen/AArch64/arm64-pic-local-symbol.ll +++ b/test/CodeGen/AArch64/arm64-pic-local-symbol.ll @@ -7,7 +7,7 @@ define i32 @get() { ; CHECK: get: ; CHECK: adrp x{{[0-9]+}}, a ; CHECK-NEXT: ldr w{{[0-9]+}}, [x{{[0-9]}}, :lo12:a] - %res = load i32* @a, align 4 + %res = load i32, i32* @a, align 4 ret i32 %res } @@ -15,7 +15,7 @@ define void @foo() nounwind { ; CHECK: foo: ; CHECK: adrp x{{[0-9]}}, .L.str ; CHECK-NEXT: add x{{[0-9]}}, x{{[0-9]}}, :lo12:.L.str - tail call void @bar(i8* getelementptr inbounds ([6 x i8]* @.str, i64 0, i64 0)) + tail call void @bar(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i64 0, i64 0)) ret void } diff --git a/test/CodeGen/AArch64/arm64-platform-reg.ll b/test/CodeGen/AArch64/arm64-platform-reg.ll index b0d3ee0..60672aa 100644 --- a/test/CodeGen/AArch64/arm64-platform-reg.ll +++ b/test/CodeGen/AArch64/arm64-platform-reg.ll @@ -11,7 +11,7 @@ @var = global [30 x i64] zeroinitializer define void @keep_live() { - %val = load volatile [30 x i64]* @var + %val = load volatile [30 x i64], [30 x i64]* @var store volatile [30 x i64] %val, [30 x i64]* @var ; CHECK: ldr x18 diff --git a/test/CodeGen/AArch64/arm64-prefetch.ll b/test/CodeGen/AArch64/arm64-prefetch.ll index aac3515..bdeacb2 100644 --- a/test/CodeGen/AArch64/arm64-prefetch.ll +++ b/test/CodeGen/AArch64/arm64-prefetch.ll @@ -35,79 +35,79 @@ entry: ; CHECK: prfum pstl1keep call void @llvm.prefetch(i8* %tmp, i32 1, i32 3, i32 1) - %tmp1 = load i32* %j.addr, align 4, !tbaa !0 + %tmp1 = load i32, i32* %j.addr, align 4, !tbaa !0 %add = add nsw i32 %tmp1, %i %idxprom = sext i32 %add to i64 - %tmp2 = load i32** @a, align 8, !tbaa !3 - %arrayidx = getelementptr inbounds i32* %tmp2, i64 %idxprom + %tmp2 = load i32*, i32** @a, align 8, !tbaa !3 + %arrayidx = getelementptr inbounds i32, i32* %tmp2, i64 %idxprom %tmp3 = bitcast i32* %arrayidx to i8* ; CHECK: prfm pldl1strm call void @llvm.prefetch(i8* %tmp3, i32 0, i32 0, i32 1) - %tmp4 = load i32** @a, align 8, !tbaa !3 - %arrayidx3 = getelementptr inbounds i32* %tmp4, i64 %idxprom + %tmp4 = load i32*, i32** @a, align 8, !tbaa !3 + %arrayidx3 = getelementptr inbounds i32, i32* %tmp4, i64 %idxprom %tmp5 = bitcast i32* %arrayidx3 to i8* ; CHECK: prfm pldl3keep call void @llvm.prefetch(i8* %tmp5, i32 0, i32 1, i32 1) - %tmp6 = load i32** @a, align 8, !tbaa !3 - %arrayidx6 = getelementptr inbounds i32* %tmp6, i64 %idxprom + %tmp6 = load i32*, i32** @a, align 8, !tbaa !3 + %arrayidx6 = getelementptr inbounds i32, i32* %tmp6, i64 %idxprom %tmp7 = bitcast i32* %arrayidx6 to i8* ; CHECK: prfm pldl2keep call void @llvm.prefetch(i8* %tmp7, i32 0, i32 2, i32 1) - %tmp8 = load i32** @a, align 8, !tbaa !3 - %arrayidx9 = getelementptr inbounds i32* %tmp8, i64 %idxprom + %tmp8 = load i32*, i32** @a, align 8, !tbaa !3 + %arrayidx9 = getelementptr inbounds i32, i32* %tmp8, i64 %idxprom %tmp9 = bitcast i32* %arrayidx9 to i8* ; CHECK: prfm pldl1keep call void @llvm.prefetch(i8* %tmp9, i32 0, i32 3, i32 1) - %tmp10 = load i32** @a, align 8, !tbaa !3 - %arrayidx12 = getelementptr inbounds i32* %tmp10, i64 %idxprom + %tmp10 = load i32*, i32** @a, align 8, !tbaa !3 + %arrayidx12 = getelementptr inbounds i32, i32* %tmp10, i64 %idxprom %tmp11 = bitcast i32* %arrayidx12 to i8* ; CHECK: prfm plil1strm call void @llvm.prefetch(i8* %tmp11, i32 0, i32 0, i32 0) - %tmp12 = load i32** @a, align 8, !tbaa !3 - %arrayidx15 = getelementptr inbounds i32* %tmp12, i64 %idxprom + %tmp12 = load i32*, i32** @a, align 8, !tbaa !3 + %arrayidx15 = getelementptr inbounds i32, i32* %tmp12, i64 %idxprom %tmp13 = bitcast i32* %arrayidx3 to i8* ; CHECK: prfm plil3keep call void @llvm.prefetch(i8* %tmp13, i32 0, i32 1, i32 0) - %tmp14 = load i32** @a, align 8, !tbaa !3 - %arrayidx18 = getelementptr inbounds i32* %tmp14, i64 %idxprom + %tmp14 = load i32*, i32** @a, align 8, !tbaa !3 + %arrayidx18 = getelementptr inbounds i32, i32* %tmp14, i64 %idxprom %tmp15 = bitcast i32* %arrayidx6 to i8* ; CHECK: prfm plil2keep call void @llvm.prefetch(i8* %tmp15, i32 0, i32 2, i32 0) - %tmp16 = load i32** @a, align 8, !tbaa !3 - %arrayidx21 = getelementptr inbounds i32* %tmp16, i64 %idxprom + %tmp16 = load i32*, i32** @a, align 8, !tbaa !3 + %arrayidx21 = getelementptr inbounds i32, i32* %tmp16, i64 %idxprom %tmp17 = bitcast i32* %arrayidx9 to i8* ; CHECK: prfm plil1keep call void @llvm.prefetch(i8* %tmp17, i32 0, i32 3, i32 0) - %tmp18 = load i32** @a, align 8, !tbaa !3 - %arrayidx24 = getelementptr inbounds i32* %tmp18, i64 %idxprom + %tmp18 = load i32*, i32** @a, align 8, !tbaa !3 + %arrayidx24 = getelementptr inbounds i32, i32* %tmp18, i64 %idxprom %tmp19 = bitcast i32* %arrayidx12 to i8* ; CHECK: prfm pstl1strm call void @llvm.prefetch(i8* %tmp19, i32 1, i32 0, i32 1) - %tmp20 = load i32** @a, align 8, !tbaa !3 - %arrayidx27 = getelementptr inbounds i32* %tmp20, i64 %idxprom + %tmp20 = load i32*, i32** @a, align 8, !tbaa !3 + %arrayidx27 = getelementptr inbounds i32, i32* %tmp20, i64 %idxprom %tmp21 = bitcast i32* %arrayidx15 to i8* ; CHECK: prfm pstl3keep call void @llvm.prefetch(i8* %tmp21, i32 1, i32 1, i32 1) - %tmp22 = load i32** @a, align 8, !tbaa !3 - %arrayidx30 = getelementptr inbounds i32* %tmp22, i64 %idxprom + %tmp22 = load i32*, i32** @a, align 8, !tbaa !3 + %arrayidx30 = getelementptr inbounds i32, i32* %tmp22, i64 %idxprom %tmp23 = bitcast i32* %arrayidx18 to i8* ; CHECK: prfm pstl2keep call void @llvm.prefetch(i8* %tmp23, i32 1, i32 2, i32 1) - %tmp24 = load i32** @a, align 8, !tbaa !3 - %arrayidx33 = getelementptr inbounds i32* %tmp24, i64 %idxprom + %tmp24 = load i32*, i32** @a, align 8, !tbaa !3 + %arrayidx33 = getelementptr inbounds i32, i32* %tmp24, i64 %idxprom %tmp25 = bitcast i32* %arrayidx21 to i8* ; CHECK: prfm pstl1keep diff --git a/test/CodeGen/AArch64/arm64-redzone.ll b/test/CodeGen/AArch64/arm64-redzone.ll index 9b0c384..837249c 100644 --- a/test/CodeGen/AArch64/arm64-redzone.ll +++ b/test/CodeGen/AArch64/arm64-redzone.ll @@ -9,10 +9,10 @@ define i32 @foo(i32 %a, i32 %b) nounwind ssp { %x = alloca i32, align 4 store i32 %a, i32* %a.addr, align 4 store i32 %b, i32* %b.addr, align 4 - %tmp = load i32* %a.addr, align 4 - %tmp1 = load i32* %b.addr, align 4 + %tmp = load i32, i32* %a.addr, align 4 + %tmp1 = load i32, i32* %b.addr, align 4 %add = add nsw i32 %tmp, %tmp1 store i32 %add, i32* %x, align 4 - %tmp2 = load i32* %x, align 4 + %tmp2 = load i32, i32* %x, align 4 ret i32 %tmp2 } diff --git a/test/CodeGen/AArch64/arm64-register-offset-addressing.ll b/test/CodeGen/AArch64/arm64-register-offset-addressing.ll index 045712b..7078ffc 100644 --- a/test/CodeGen/AArch64/arm64-register-offset-addressing.ll +++ b/test/CodeGen/AArch64/arm64-register-offset-addressing.ll @@ -5,8 +5,8 @@ define i8 @test_64bit_add(i16* %a, i64 %b) { ; CHECK: lsl [[REG:x[0-9]+]], x1, #1 ; CHECK: ldrb w0, [x0, [[REG]]] ; CHECK: ret - %tmp1 = getelementptr inbounds i16* %a, i64 %b - %tmp2 = load i16* %tmp1 + %tmp1 = getelementptr inbounds i16, i16* %a, i64 %b + %tmp2 = load i16, i16* %tmp1 %tmp3 = trunc i16 %tmp2 to i8 ret i8 %tmp3 } @@ -18,8 +18,8 @@ define void @ldst_8bit(i8* %base, i64 %offset) minsize { %off32.sext.tmp = shl i64 %offset, 32 %off32.sext = ashr i64 %off32.sext.tmp, 32 - %addr8_sxtw = getelementptr i8* %base, i64 %off32.sext - %val8_sxtw = load volatile i8* %addr8_sxtw + %addr8_sxtw = getelementptr i8, i8* %base, i64 %off32.sext + %val8_sxtw = load volatile i8, i8* %addr8_sxtw %val32_signed = sext i8 %val8_sxtw to i32 store volatile i32 %val32_signed, i32* @var_32bit ; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] @@ -28,7 +28,7 @@ define void @ldst_8bit(i8* %base, i64 %offset) minsize { %offset_uxtw = and i64 %offset, 4294967295 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw %addr_uxtw = inttoptr i64 %addrint1_uxtw to i8* - %val8_uxtw = load volatile i8* %addr_uxtw + %val8_uxtw = load volatile i8, i8* %addr_uxtw %newval8 = add i8 %val8_uxtw, 1 store volatile i8 %newval8, i8* @var_8bit ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] @@ -44,7 +44,7 @@ define void @ldst_16bit(i16* %base, i64 %offset) minsize { %offset_uxtw = and i64 %offset, 4294967295 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw %addr_uxtw = inttoptr i64 %addrint1_uxtw to i16* - %val8_uxtw = load volatile i16* %addr_uxtw + %val8_uxtw = load volatile i16, i16* %addr_uxtw %newval8 = add i16 %val8_uxtw, 1 store volatile i16 %newval8, i16* @var_16bit ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] @@ -54,7 +54,7 @@ define void @ldst_16bit(i16* %base, i64 %offset) minsize { %offset_sxtw = ashr i64 %offset_sxtw.tmp, 32 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw %addr_sxtw = inttoptr i64 %addrint_sxtw to i16* - %val16_sxtw = load volatile i16* %addr_sxtw + %val16_sxtw = load volatile i16, i16* %addr_sxtw %val64_signed = sext i16 %val16_sxtw to i64 store volatile i64 %val64_signed, i64* @var_64bit ; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] @@ -65,7 +65,7 @@ define void @ldst_16bit(i16* %base, i64 %offset) minsize { %offset2_uxtwN = shl i64 %offset_uxtwN, 1 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i16* - %val32 = load volatile i32* @var_32bit + %val32 = load volatile i32, i32* @var_32bit %val16_trunc32 = trunc i32 %val32 to i16 store volatile i16 %val16_trunc32, i16* %addr_uxtwN ; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #1] @@ -79,7 +79,7 @@ define void @ldst_32bit(i32* %base, i64 %offset) minsize { %offset_uxtw = and i64 %offset, 4294967295 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw %addr_uxtw = inttoptr i64 %addrint1_uxtw to i32* - %val32_uxtw = load volatile i32* %addr_uxtw + %val32_uxtw = load volatile i32, i32* %addr_uxtw %newval32 = add i32 %val32_uxtw, 1 store volatile i32 %newval32, i32* @var_32bit ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] @@ -89,7 +89,7 @@ define void @ldst_32bit(i32* %base, i64 %offset) minsize { %offset_sxtw = ashr i64 %offset_sxtw.tmp, 32 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw %addr_sxtw = inttoptr i64 %addrint_sxtw to i32* - %val32_sxtw = load volatile i32* %addr_sxtw + %val32_sxtw = load volatile i32, i32* %addr_sxtw %val64_signed = sext i32 %val32_sxtw to i64 store volatile i64 %val64_signed, i64* @var_64bit ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] @@ -100,7 +100,7 @@ define void @ldst_32bit(i32* %base, i64 %offset) minsize { %offset2_uxtwN = shl i64 %offset_uxtwN, 2 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i32* - %val32 = load volatile i32* @var_32bit + %val32 = load volatile i32, i32* @var_32bit store volatile i32 %val32, i32* %addr_uxtwN ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #2] ret void @@ -113,7 +113,7 @@ define void @ldst_64bit(i64* %base, i64 %offset) minsize { %offset_uxtw = and i64 %offset, 4294967295 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw %addr_uxtw = inttoptr i64 %addrint1_uxtw to i64* - %val64_uxtw = load volatile i64* %addr_uxtw + %val64_uxtw = load volatile i64, i64* %addr_uxtw %newval8 = add i64 %val64_uxtw, 1 store volatile i64 %newval8, i64* @var_64bit ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] @@ -123,7 +123,7 @@ define void @ldst_64bit(i64* %base, i64 %offset) minsize { %offset_sxtw = ashr i64 %offset_sxtw.tmp, 32 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw %addr_sxtw = inttoptr i64 %addrint_sxtw to i64* - %val64_sxtw = load volatile i64* %addr_sxtw + %val64_sxtw = load volatile i64, i64* %addr_sxtw store volatile i64 %val64_sxtw, i64* @var_64bit ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] @@ -133,7 +133,7 @@ define void @ldst_64bit(i64* %base, i64 %offset) minsize { %offset2_uxtwN = shl i64 %offset_uxtwN, 3 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i64* - %val64 = load volatile i64* @var_64bit + %val64 = load volatile i64, i64* @var_64bit store volatile i64 %val64, i64* %addr_uxtwN ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #3] ret void diff --git a/test/CodeGen/AArch64/arm64-regress-interphase-shift.ll b/test/CodeGen/AArch64/arm64-regress-interphase-shift.ll index fec8933..d376aaf 100644 --- a/test/CodeGen/AArch64/arm64-regress-interphase-shift.ll +++ b/test/CodeGen/AArch64/arm64-regress-interphase-shift.ll @@ -11,7 +11,7 @@ define void @foo(i64* nocapture %d) { ; CHECK-LABEL: foo: ; CHECK: rorv - %tmp = load i64* undef, align 8 + %tmp = load i64, i64* undef, align 8 %sub397 = sub i64 0, %tmp %and398 = and i64 %sub397, 4294967295 %shr404 = lshr i64 %and398, 0 diff --git a/test/CodeGen/AArch64/arm64-return-vector.ll b/test/CodeGen/AArch64/arm64-return-vector.ll index 9457d8b..3262c91 100644 --- a/test/CodeGen/AArch64/arm64-return-vector.ll +++ b/test/CodeGen/AArch64/arm64-return-vector.ll @@ -6,6 +6,6 @@ define <2 x double> @test(<2 x double>* %p) nounwind { ; CHECK: test ; CHECK: ldr q0, [x0] ; CHECK: ret - %tmp1 = load <2 x double>* %p, align 16 + %tmp1 = load <2 x double>, <2 x double>* %p, align 16 ret <2 x double> %tmp1 } diff --git a/test/CodeGen/AArch64/arm64-rev.ll b/test/CodeGen/AArch64/arm64-rev.ll index 30d9f4f..74356d7 100644 --- a/test/CodeGen/AArch64/arm64-rev.ll +++ b/test/CodeGen/AArch64/arm64-rev.ll @@ -64,7 +64,7 @@ entry: define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: test_vrev64D8: ;CHECK: rev64.8b - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> ret <8 x i8> %tmp2 } @@ -72,7 +72,7 @@ define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: test_vrev64D16: ;CHECK: rev64.4h - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ret <4 x i16> %tmp2 } @@ -80,7 +80,7 @@ define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: test_vrev64D32: ;CHECK: rev64.2s - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0> ret <2 x i32> %tmp2 } @@ -88,7 +88,7 @@ define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { ;CHECK-LABEL: test_vrev64Df: ;CHECK: rev64.2s - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0> ret <2 x float> %tmp2 } @@ -96,7 +96,7 @@ define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: test_vrev64Q8: ;CHECK: rev64.16b - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8> ret <16 x i8> %tmp2 } @@ -104,7 +104,7 @@ define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: test_vrev64Q16: ;CHECK: rev64.8h - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> ret <8 x i16> %tmp2 } @@ -112,7 +112,7 @@ define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: test_vrev64Q32: ;CHECK: rev64.4s - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> ret <4 x i32> %tmp2 } @@ -120,7 +120,7 @@ define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { ;CHECK-LABEL: test_vrev64Qf: ;CHECK: rev64.4s - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> ret <4 x float> %tmp2 } @@ -128,7 +128,7 @@ define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: test_vrev32D8: ;CHECK: rev32.8b - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> ret <8 x i8> %tmp2 } @@ -136,7 +136,7 @@ define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: test_vrev32D16: ;CHECK: rev32.4h - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> ret <4 x i16> %tmp2 } @@ -144,7 +144,7 @@ define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: test_vrev32Q8: ;CHECK: rev32.16b - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> ret <16 x i8> %tmp2 } @@ -152,7 +152,7 @@ define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: test_vrev32Q16: ;CHECK: rev32.8h - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> ret <8 x i16> %tmp2 } @@ -160,7 +160,7 @@ define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: test_vrev16D8: ;CHECK: rev16.8b - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> ret <8 x i8> %tmp2 } @@ -168,7 +168,7 @@ define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: test_vrev16Q8: ;CHECK: rev16.16b - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> ret <16 x i8> %tmp2 } @@ -178,7 +178,7 @@ define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind { define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind { ;CHECK-LABEL: test_vrev64D8_undef: ;CHECK: rev64.8b - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0> ret <8 x i8> %tmp2 } @@ -186,7 +186,7 @@ define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind { define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind { ;CHECK-LABEL: test_vrev32Q16_undef: ;CHECK: rev32.8h - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef> ret <8 x i16> %tmp2 } @@ -199,7 +199,7 @@ define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst ; CHECK: st1.h entry: %0 = bitcast <4 x i16>* %source to <8 x i16>* - %tmp2 = load <8 x i16>* %0, align 4 + %tmp2 = load <8 x i16>, <8 x i16>* %0, align 4 %tmp3 = extractelement <8 x i16> %tmp2, i32 6 %tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0 %tmp9 = extractelement <8 x i16> %tmp2, i32 5 @@ -215,9 +215,9 @@ define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest ; CHECK: rev64.4s entry: %0 = bitcast float* %source to <4 x float>* - %tmp2 = load <4 x float>* %0, align 4 + %tmp2 = load <4 x float>, <4 x float>* %0, align 4 %tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0> - %arrayidx8 = getelementptr inbounds <4 x float>* %dest, i32 11 + %arrayidx8 = getelementptr inbounds <4 x float>, <4 x float>* %dest, i32 11 store <4 x float> %tmp5, <4 x float>* %arrayidx8, align 4 ret void } diff --git a/test/CodeGen/AArch64/arm64-scaled_iv.ll b/test/CodeGen/AArch64/arm64-scaled_iv.ll index 987373e..24f04f4 100644 --- a/test/CodeGen/AArch64/arm64-scaled_iv.ll +++ b/test/CodeGen/AArch64/arm64-scaled_iv.ll @@ -17,15 +17,15 @@ for.body: ; preds = %for.body, %entry ; CHECK-NOT: phi %indvars.iv = phi i64 [ 1, %entry ], [ %indvars.iv.next, %for.body ] %tmp = add nsw i64 %indvars.iv, -1 - %arrayidx = getelementptr inbounds double* %b, i64 %tmp - %tmp1 = load double* %arrayidx, align 8 + %arrayidx = getelementptr inbounds double, double* %b, i64 %tmp + %tmp1 = load double, double* %arrayidx, align 8 ; The induction variable should carry the scaling factor: 1 * 8 = 8. ; CHECK: [[IVNEXT]] = add nuw nsw i64 [[IV]], 8 %indvars.iv.next = add i64 %indvars.iv, 1 - %arrayidx2 = getelementptr inbounds double* %c, i64 %indvars.iv.next - %tmp2 = load double* %arrayidx2, align 8 + %arrayidx2 = getelementptr inbounds double, double* %c, i64 %indvars.iv.next + %tmp2 = load double, double* %arrayidx2, align 8 %mul = fmul double %tmp1, %tmp2 - %arrayidx4 = getelementptr inbounds double* %a, i64 %indvars.iv + %arrayidx4 = getelementptr inbounds double, double* %a, i64 %indvars.iv store double %mul, double* %arrayidx4, align 8 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 ; Comparison should be 19 * 8 = 152. diff --git a/test/CodeGen/AArch64/arm64-scvt.ll b/test/CodeGen/AArch64/arm64-scvt.ll index 8baaf22..fc64d7b 100644 --- a/test/CodeGen/AArch64/arm64-scvt.ll +++ b/test/CodeGen/AArch64/arm64-scvt.ll @@ -7,7 +7,7 @@ entry: ; CHECK-LABEL: t1: ; CHECK: ldr s0, [x0] ; CHECK: scvtf s0, s0 - %tmp1 = load i32* %src, align 4 + %tmp1 = load i32, i32* %src, align 4 %tmp2 = sitofp i32 %tmp1 to float ret float %tmp2 } @@ -17,7 +17,7 @@ entry: ; CHECK-LABEL: t2: ; CHECK: ldr s0, [x0] ; CHECK: ucvtf s0, s0 - %tmp1 = load i32* %src, align 4 + %tmp1 = load i32, i32* %src, align 4 %tmp2 = uitofp i32 %tmp1 to float ret float %tmp2 } @@ -27,7 +27,7 @@ entry: ; CHECK-LABEL: t3: ; CHECK: ldr d0, [x0] ; CHECK: scvtf d0, d0 - %tmp1 = load i64* %src, align 4 + %tmp1 = load i64, i64* %src, align 4 %tmp2 = sitofp i64 %tmp1 to double ret double %tmp2 } @@ -37,7 +37,7 @@ entry: ; CHECK-LABEL: t4: ; CHECK: ldr d0, [x0] ; CHECK: ucvtf d0, d0 - %tmp1 = load i64* %src, align 4 + %tmp1 = load i64, i64* %src, align 4 %tmp2 = uitofp i64 %tmp1 to double ret double %tmp2 } @@ -48,7 +48,7 @@ entry: ; CHECK-LABEL: t5: ; CHECK: ldr [[REG:w[0-9]+]], [x0] ; CHECK: scvtf d0, [[REG]] - %tmp1 = load i32* %src, align 4 + %tmp1 = load i32, i32* %src, align 4 %tmp2 = sitofp i32 %tmp1 to double ret double %tmp2 } @@ -75,8 +75,8 @@ define float @fct1(i8* nocapture %sp0) { ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i8* %sp0, i64 1 - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = uitofp i8 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -88,8 +88,8 @@ define float @fct2(i16* nocapture %sp0) { ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i16* %sp0, i64 1 - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = uitofp i16 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -101,8 +101,8 @@ define float @fct3(i32* nocapture %sp0) { ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 1 - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = uitofp i32 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -115,8 +115,8 @@ define float @fct4(i64* nocapture %sp0) { ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i64* %sp0, i64 1 - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = uitofp i64 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -129,8 +129,8 @@ define float @fct5(i8* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i8* %sp0, i64 %offset - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 %offset + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = uitofp i8 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -142,8 +142,8 @@ define float @fct6(i16* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i16* %sp0, i64 %offset - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 %offset + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = uitofp i16 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -155,8 +155,8 @@ define float @fct7(i32* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 %offset - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 %offset + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = uitofp i32 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -169,8 +169,8 @@ define float @fct8(i64* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i64* %sp0, i64 %offset - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 %offset + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = uitofp i64 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -184,8 +184,8 @@ define double @fct9(i8* nocapture %sp0) { ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i8* %sp0, i64 1 - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = uitofp i8 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -197,8 +197,8 @@ define double @fct10(i16* nocapture %sp0) { ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i16* %sp0, i64 1 - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = uitofp i16 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -210,8 +210,8 @@ define double @fct11(i32* nocapture %sp0) { ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 1 - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = uitofp i32 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -223,8 +223,8 @@ define double @fct12(i64* nocapture %sp0) { ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i64* %sp0, i64 1 - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = uitofp i64 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -237,8 +237,8 @@ define double @fct13(i8* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i8* %sp0, i64 %offset - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 %offset + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = uitofp i8 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -250,8 +250,8 @@ define double @fct14(i16* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i16* %sp0, i64 %offset - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 %offset + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = uitofp i16 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -263,8 +263,8 @@ define double @fct15(i32* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 %offset - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 %offset + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = uitofp i32 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -276,8 +276,8 @@ define double @fct16(i64* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i64* %sp0, i64 %offset - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 %offset + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = uitofp i64 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -293,7 +293,7 @@ entry: %bitcast = ptrtoint i8* %sp0 to i64 %add = add i64 %bitcast, -1 %addr = inttoptr i64 %add to i8* - %pix_sp0.0.copyload = load i8* %addr, align 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = uitofp i8 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -307,7 +307,7 @@ define float @fct18(i16* nocapture %sp0) { %bitcast = ptrtoint i16* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i16* - %pix_sp0.0.copyload = load i16* %addr, align 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = uitofp i16 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -321,7 +321,7 @@ define float @fct19(i32* nocapture %sp0) { %bitcast = ptrtoint i32* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i32* - %pix_sp0.0.copyload = load i32* %addr, align 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = uitofp i32 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -336,7 +336,7 @@ define float @fct20(i64* nocapture %sp0) { %bitcast = ptrtoint i64* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i64* - %pix_sp0.0.copyload = load i64* %addr, align 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = uitofp i64 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -353,7 +353,7 @@ entry: %bitcast = ptrtoint i8* %sp0 to i64 %add = add i64 %bitcast, -1 %addr = inttoptr i64 %add to i8* - %pix_sp0.0.copyload = load i8* %addr, align 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = uitofp i8 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -367,7 +367,7 @@ define double @fct22(i16* nocapture %sp0) { %bitcast = ptrtoint i16* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i16* - %pix_sp0.0.copyload = load i16* %addr, align 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = uitofp i16 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -381,7 +381,7 @@ define double @fct23(i32* nocapture %sp0) { %bitcast = ptrtoint i32* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i32* - %pix_sp0.0.copyload = load i32* %addr, align 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = uitofp i32 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -395,7 +395,7 @@ define double @fct24(i64* nocapture %sp0) { %bitcast = ptrtoint i64* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i64* - %pix_sp0.0.copyload = load i64* %addr, align 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = uitofp i64 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -415,8 +415,8 @@ define float @sfct1(i8* nocapture %sp0) { ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]] ; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i8* %sp0, i64 1 - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = sitofp i8 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -429,8 +429,8 @@ define float @sfct2(i16* nocapture %sp0) { ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i16* %sp0, i64 1 - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = sitofp i16 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -442,8 +442,8 @@ define float @sfct3(i32* nocapture %sp0) { ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 1 - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = sitofp i32 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -456,8 +456,8 @@ define float @sfct4(i64* nocapture %sp0) { ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], x[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i64* %sp0, i64 1 - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = sitofp i64 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -476,8 +476,8 @@ define float @sfct5(i8* nocapture %sp0, i64 %offset) { ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]] ; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i8* %sp0, i64 %offset - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 %offset + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = sitofp i8 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -490,8 +490,8 @@ define float @sfct6(i16* nocapture %sp0, i64 %offset) { ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i16* %sp0, i64 %offset - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 %offset + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = sitofp i16 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -503,8 +503,8 @@ define float @sfct7(i32* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 %offset - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 %offset + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = sitofp i32 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -517,8 +517,8 @@ define float @sfct8(i64* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], x[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i64* %sp0, i64 %offset - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 %offset + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = sitofp i64 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -531,8 +531,8 @@ define double @sfct9(i8* nocapture %sp0) { ; CHECK-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i8* %sp0, i64 1 - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = sitofp i8 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -550,8 +550,8 @@ define double @sfct10(i16* nocapture %sp0) { ; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]] ; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i16* %sp0, i64 1 - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = sitofp i16 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -564,8 +564,8 @@ define double @sfct11(i32* nocapture %sp0) { ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 1 - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = sitofp i32 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -577,8 +577,8 @@ define double @sfct12(i64* nocapture %sp0) { ; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[SEXTREG]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i64* %sp0, i64 1 - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = sitofp i64 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -591,8 +591,8 @@ define double @sfct13(i8* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i8* %sp0, i64 %offset - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 %offset + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = sitofp i8 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -610,8 +610,8 @@ define double @sfct14(i16* nocapture %sp0, i64 %offset) { ; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]] ; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i16* %sp0, i64 %offset - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 %offset + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = sitofp i16 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -624,8 +624,8 @@ define double @sfct15(i32* nocapture %sp0, i64 %offset) { ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 %offset - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 %offset + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = sitofp i32 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -637,8 +637,8 @@ define double @sfct16(i64* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[SEXTREG]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i64* %sp0, i64 %offset - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 %offset + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = sitofp i64 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -660,7 +660,7 @@ entry: %bitcast = ptrtoint i8* %sp0 to i64 %add = add i64 %bitcast, -1 %addr = inttoptr i64 %add to i8* - %pix_sp0.0.copyload = load i8* %addr, align 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = sitofp i8 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -675,7 +675,7 @@ define float @sfct18(i16* nocapture %sp0) { %bitcast = ptrtoint i16* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i16* - %pix_sp0.0.copyload = load i16* %addr, align 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = sitofp i16 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -689,7 +689,7 @@ define float @sfct19(i32* nocapture %sp0) { %bitcast = ptrtoint i32* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i32* - %pix_sp0.0.copyload = load i32* %addr, align 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = sitofp i32 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -704,7 +704,7 @@ define float @sfct20(i64* nocapture %sp0) { %bitcast = ptrtoint i64* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i64* - %pix_sp0.0.copyload = load i64* %addr, align 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = sitofp i64 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -721,7 +721,7 @@ entry: %bitcast = ptrtoint i8* %sp0 to i64 %add = add i64 %bitcast, -1 %addr = inttoptr i64 %add to i8* - %pix_sp0.0.copyload = load i8* %addr, align 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = sitofp i8 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -741,7 +741,7 @@ define double @sfct22(i16* nocapture %sp0) { %bitcast = ptrtoint i16* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i16* - %pix_sp0.0.copyload = load i16* %addr, align 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = sitofp i16 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -756,7 +756,7 @@ define double @sfct23(i32* nocapture %sp0) { %bitcast = ptrtoint i32* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i32* - %pix_sp0.0.copyload = load i32* %addr, align 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = sitofp i32 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -770,7 +770,7 @@ define double @sfct24(i64* nocapture %sp0) { %bitcast = ptrtoint i64* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i64* - %pix_sp0.0.copyload = load i64* %addr, align 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = sitofp i64 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -787,7 +787,7 @@ entry: %bitcast = ptrtoint i8* %sp0 to i64 %add = add i64 %bitcast, -1 %addr = inttoptr i64 %add to i8* - %pix_sp0.0.copyload = load i8* %addr, align 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = sitofp i8 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -799,8 +799,8 @@ define double @codesize_sfct11(i32* nocapture %sp0) minsize { ; CHECK-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 1 - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = sitofp i32 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i diff --git a/test/CodeGen/AArch64/arm64-sitofp-combine-chains.ll b/test/CodeGen/AArch64/arm64-sitofp-combine-chains.ll index 10b433b..2113165 100644 --- a/test/CodeGen/AArch64/arm64-sitofp-combine-chains.ll +++ b/test/CodeGen/AArch64/arm64-sitofp-combine-chains.ll @@ -14,7 +14,7 @@ define float @foo() { ; CHECK: ldr [[SREG:s[0-9]+]], [x[[VARBASE]], ; CHECK: str wzr, [x[[VARBASE]], - %val = load i32* @var, align 4 + %val = load i32, i32* @var, align 4 store i32 0, i32* @var, align 4 %fltval = sitofp i32 %val to float diff --git a/test/CodeGen/AArch64/arm64-smaxv.ll b/test/CodeGen/AArch64/arm64-smaxv.ll index 183e667..8cc4502 100644 --- a/test/CodeGen/AArch64/arm64-smaxv.ll +++ b/test/CodeGen/AArch64/arm64-smaxv.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s +; RUN: llc -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false < %s | FileCheck %s define signext i8 @test_vmaxv_s8(<8 x i8> %a1) { ; CHECK: test_vmaxv_s8 @@ -65,6 +65,76 @@ entry: ret i32 %vmaxv.i } +define <8 x i8> @test_vmaxv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) { +; CHECK-LABEL: test_vmaxv_s8_used_by_laneop: +; CHECK: smaxv.8b b[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a2) + %1 = trunc i32 %0 to i8 + %2 = insertelement <8 x i8> %a1, i8 %1, i32 3 + ret <8 x i8> %2 +} + +define <4 x i16> @test_vmaxv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) { +; CHECK-LABEL: test_vmaxv_s16_used_by_laneop: +; CHECK: smaxv.4h h[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a2) + %1 = trunc i32 %0 to i16 + %2 = insertelement <4 x i16> %a1, i16 %1, i32 3 + ret <4 x i16> %2 +} + +define <2 x i32> @test_vmaxv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) { +; CHECK-LABEL: test_vmaxv_s32_used_by_laneop: +; CHECK: smaxp.2s v[[REGNUM:[0-9]+]], v1, v1 +; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v2i32(<2 x i32> %a2) + %1 = insertelement <2 x i32> %a1, i32 %0, i32 1 + ret <2 x i32> %1 +} + +define <16 x i8> @test_vmaxvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) { +; CHECK-LABEL: test_vmaxvq_s8_used_by_laneop: +; CHECK: smaxv.16b b[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a2) + %1 = trunc i32 %0 to i8 + %2 = insertelement <16 x i8> %a1, i8 %1, i32 3 + ret <16 x i8> %2 +} + +define <8 x i16> @test_vmaxvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) { +; CHECK-LABEL: test_vmaxvq_s16_used_by_laneop: +; CHECK: smaxv.8h h[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a2) + %1 = trunc i32 %0 to i16 + %2 = insertelement <8 x i16> %a1, i16 %1, i32 3 + ret <8 x i16> %2 +} + +define <4 x i32> @test_vmaxvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) { +; CHECK-LABEL: test_vmaxvq_s32_used_by_laneop: +; CHECK: smaxv.4s s[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a2) + %1 = insertelement <4 x i32> %a1, i32 %0, i32 3 + ret <4 x i32> %1 +} + declare i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32>) declare i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16>) declare i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8>) diff --git a/test/CodeGen/AArch64/arm64-sminv.ll b/test/CodeGen/AArch64/arm64-sminv.ll index 195c4e5..c1650b5 100644 --- a/test/CodeGen/AArch64/arm64-sminv.ll +++ b/test/CodeGen/AArch64/arm64-sminv.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s | FileCheck %s +; RUN: llc -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false < %s | FileCheck %s define signext i8 @test_vminv_s8(<8 x i8> %a1) { ; CHECK: test_vminv_s8 @@ -65,6 +65,76 @@ entry: ret i32 %vminv.i } +define <8 x i8> @test_vminv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) { +; CHECK-LABEL: test_vminv_s8_used_by_laneop: +; CHECK: sminv.8b b[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a2) + %1 = trunc i32 %0 to i8 + %2 = insertelement <8 x i8> %a1, i8 %1, i32 3 + ret <8 x i8> %2 +} + +define <4 x i16> @test_vminv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) { +; CHECK-LABEL: test_vminv_s16_used_by_laneop: +; CHECK: sminv.4h h[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a2) + %1 = trunc i32 %0 to i16 + %2 = insertelement <4 x i16> %a1, i16 %1, i32 3 + ret <4 x i16> %2 +} + +define <2 x i32> @test_vminv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) { +; CHECK-LABEL: test_vminv_s32_used_by_laneop: +; CHECK: sminp.2s v[[REGNUM:[0-9]+]], v1, v1 +; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a2) + %1 = insertelement <2 x i32> %a1, i32 %0, i32 1 + ret <2 x i32> %1 +} + +define <16 x i8> @test_vminvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) { +; CHECK-LABEL: test_vminvq_s8_used_by_laneop: +; CHECK: sminv.16b b[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a2) + %1 = trunc i32 %0 to i8 + %2 = insertelement <16 x i8> %a1, i8 %1, i32 3 + ret <16 x i8> %2 +} + +define <8 x i16> @test_vminvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) { +; CHECK-LABEL: test_vminvq_s16_used_by_laneop: +; CHECK: sminv.8h h[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a2) + %1 = trunc i32 %0 to i16 + %2 = insertelement <8 x i16> %a1, i16 %1, i32 3 + ret <8 x i16> %2 +} + +define <4 x i32> @test_vminvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) { +; CHECK-LABEL: test_vminvq_s32_used_by_laneop: +; CHECK: sminv.4s s[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a2) + %1 = insertelement <4 x i32> %a1, i32 %0, i32 3 + ret <4 x i32> %1 +} + declare i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32>) declare i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16>) declare i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8>) diff --git a/test/CodeGen/AArch64/arm64-spill-lr.ll b/test/CodeGen/AArch64/arm64-spill-lr.ll index fb6588e..8810908 100644 --- a/test/CodeGen/AArch64/arm64-spill-lr.ll +++ b/test/CodeGen/AArch64/arm64-spill-lr.ll @@ -11,31 +11,31 @@ entry: %stack = alloca [128 x i32], align 4 %0 = bitcast [128 x i32]* %stack to i8* %idxprom = sext i32 %a to i64 - %arrayidx = getelementptr inbounds [128 x i32]* %stack, i64 0, i64 %idxprom + %arrayidx = getelementptr inbounds [128 x i32], [128 x i32]* %stack, i64 0, i64 %idxprom store i32 %b, i32* %arrayidx, align 4 - %1 = load volatile i32* @bar, align 4 - %2 = load volatile i32* @bar, align 4 - %3 = load volatile i32* @bar, align 4 - %4 = load volatile i32* @bar, align 4 - %5 = load volatile i32* @bar, align 4 - %6 = load volatile i32* @bar, align 4 - %7 = load volatile i32* @bar, align 4 - %8 = load volatile i32* @bar, align 4 - %9 = load volatile i32* @bar, align 4 - %10 = load volatile i32* @bar, align 4 - %11 = load volatile i32* @bar, align 4 - %12 = load volatile i32* @bar, align 4 - %13 = load volatile i32* @bar, align 4 - %14 = load volatile i32* @bar, align 4 - %15 = load volatile i32* @bar, align 4 - %16 = load volatile i32* @bar, align 4 - %17 = load volatile i32* @bar, align 4 - %18 = load volatile i32* @bar, align 4 - %19 = load volatile i32* @bar, align 4 - %20 = load volatile i32* @bar, align 4 + %1 = load volatile i32, i32* @bar, align 4 + %2 = load volatile i32, i32* @bar, align 4 + %3 = load volatile i32, i32* @bar, align 4 + %4 = load volatile i32, i32* @bar, align 4 + %5 = load volatile i32, i32* @bar, align 4 + %6 = load volatile i32, i32* @bar, align 4 + %7 = load volatile i32, i32* @bar, align 4 + %8 = load volatile i32, i32* @bar, align 4 + %9 = load volatile i32, i32* @bar, align 4 + %10 = load volatile i32, i32* @bar, align 4 + %11 = load volatile i32, i32* @bar, align 4 + %12 = load volatile i32, i32* @bar, align 4 + %13 = load volatile i32, i32* @bar, align 4 + %14 = load volatile i32, i32* @bar, align 4 + %15 = load volatile i32, i32* @bar, align 4 + %16 = load volatile i32, i32* @bar, align 4 + %17 = load volatile i32, i32* @bar, align 4 + %18 = load volatile i32, i32* @bar, align 4 + %19 = load volatile i32, i32* @bar, align 4 + %20 = load volatile i32, i32* @bar, align 4 %idxprom1 = sext i32 %c to i64 - %arrayidx2 = getelementptr inbounds [128 x i32]* %stack, i64 0, i64 %idxprom1 - %21 = load i32* %arrayidx2, align 4 + %arrayidx2 = getelementptr inbounds [128 x i32], [128 x i32]* %stack, i64 0, i64 %idxprom1 + %21 = load i32, i32* %arrayidx2, align 4 %factor = mul i32 %h, -2 %factor67 = mul i32 %g, -2 %factor68 = mul i32 %f, -2 diff --git a/test/CodeGen/AArch64/arm64-spill.ll b/test/CodeGen/AArch64/arm64-spill.ll index 47cdc2b..9c0cf38 100644 --- a/test/CodeGen/AArch64/arm64-spill.ll +++ b/test/CodeGen/AArch64/arm64-spill.ll @@ -8,7 +8,7 @@ ; CHECK: st1.2d define void @fpr128(<4 x float>* %p) nounwind ssp { entry: - %x = load <4 x float>* %p, align 16 + %x = load <4 x float>, <4 x float>* %p, align 16 call void asm sideeffect "; inlineasm", "~{q0},~{q1},~{q2},~{q3},~{q4},~{q5},~{q6},~{q7},~{q8},~{q9},~{q10},~{q11},~{q12},~{q13},~{q14},~{q15},~{q16},~{q17},~{q18},~{q19},~{q20},~{q21},~{q22},~{q23},~{q24},~{q25},~{q26},~{q27},~{q28},~{q29},~{q30},~{q31},~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{fp},~{lr},~{sp},~{memory}"() nounwind store <4 x float> %x, <4 x float>* %p, align 16 ret void diff --git a/test/CodeGen/AArch64/arm64-st1.ll b/test/CodeGen/AArch64/arm64-st1.ll index 76d52f4..0387a91 100644 --- a/test/CodeGen/AArch64/arm64-st1.ll +++ b/test/CodeGen/AArch64/arm64-st1.ll @@ -12,7 +12,7 @@ define void @st1lane_ro_16b(<16 x i8> %A, i8* %D, i64 %offset) { ; CHECK-LABEL: st1lane_ro_16b ; CHECK: add x[[XREG:[0-9]+]], x0, x1 ; CHECK: st1.b { v0 }[1], [x[[XREG]]] - %ptr = getelementptr i8* %D, i64 %offset + %ptr = getelementptr i8, i8* %D, i64 %offset %tmp = extractelement <16 x i8> %A, i32 1 store i8 %tmp, i8* %ptr ret void @@ -22,7 +22,7 @@ define void @st1lane0_ro_16b(<16 x i8> %A, i8* %D, i64 %offset) { ; CHECK-LABEL: st1lane0_ro_16b ; CHECK: add x[[XREG:[0-9]+]], x0, x1 ; CHECK: st1.b { v0 }[0], [x[[XREG]]] - %ptr = getelementptr i8* %D, i64 %offset + %ptr = getelementptr i8, i8* %D, i64 %offset %tmp = extractelement <16 x i8> %A, i32 0 store i8 %tmp, i8* %ptr ret void @@ -40,7 +40,7 @@ define void @st1lane_ro_8h(<8 x i16> %A, i16* %D, i64 %offset) { ; CHECK-LABEL: st1lane_ro_8h ; CHECK: add x[[XREG:[0-9]+]], x0, x1 ; CHECK: st1.h { v0 }[1], [x[[XREG]]] - %ptr = getelementptr i16* %D, i64 %offset + %ptr = getelementptr i16, i16* %D, i64 %offset %tmp = extractelement <8 x i16> %A, i32 1 store i16 %tmp, i16* %ptr ret void @@ -49,7 +49,7 @@ define void @st1lane_ro_8h(<8 x i16> %A, i16* %D, i64 %offset) { define void @st1lane0_ro_8h(<8 x i16> %A, i16* %D, i64 %offset) { ; CHECK-LABEL: st1lane0_ro_8h ; CHECK: str h0, [x0, x1, lsl #1] - %ptr = getelementptr i16* %D, i64 %offset + %ptr = getelementptr i16, i16* %D, i64 %offset %tmp = extractelement <8 x i16> %A, i32 0 store i16 %tmp, i16* %ptr ret void @@ -67,7 +67,7 @@ define void @st1lane_ro_4s(<4 x i32> %A, i32* %D, i64 %offset) { ; CHECK-LABEL: st1lane_ro_4s ; CHECK: add x[[XREG:[0-9]+]], x0, x1 ; CHECK: st1.s { v0 }[1], [x[[XREG]]] - %ptr = getelementptr i32* %D, i64 %offset + %ptr = getelementptr i32, i32* %D, i64 %offset %tmp = extractelement <4 x i32> %A, i32 1 store i32 %tmp, i32* %ptr ret void @@ -76,7 +76,7 @@ define void @st1lane_ro_4s(<4 x i32> %A, i32* %D, i64 %offset) { define void @st1lane0_ro_4s(<4 x i32> %A, i32* %D, i64 %offset) { ; CHECK-LABEL: st1lane0_ro_4s ; CHECK: str s0, [x0, x1, lsl #2] - %ptr = getelementptr i32* %D, i64 %offset + %ptr = getelementptr i32, i32* %D, i64 %offset %tmp = extractelement <4 x i32> %A, i32 0 store i32 %tmp, i32* %ptr ret void @@ -94,7 +94,7 @@ define void @st1lane_ro_4s_float(<4 x float> %A, float* %D, i64 %offset) { ; CHECK-LABEL: st1lane_ro_4s_float ; CHECK: add x[[XREG:[0-9]+]], x0, x1 ; CHECK: st1.s { v0 }[1], [x[[XREG]]] - %ptr = getelementptr float* %D, i64 %offset + %ptr = getelementptr float, float* %D, i64 %offset %tmp = extractelement <4 x float> %A, i32 1 store float %tmp, float* %ptr ret void @@ -103,7 +103,7 @@ define void @st1lane_ro_4s_float(<4 x float> %A, float* %D, i64 %offset) { define void @st1lane0_ro_4s_float(<4 x float> %A, float* %D, i64 %offset) { ; CHECK-LABEL: st1lane0_ro_4s_float ; CHECK: str s0, [x0, x1, lsl #2] - %ptr = getelementptr float* %D, i64 %offset + %ptr = getelementptr float, float* %D, i64 %offset %tmp = extractelement <4 x float> %A, i32 0 store float %tmp, float* %ptr ret void @@ -121,7 +121,7 @@ define void @st1lane_ro_2d(<2 x i64> %A, i64* %D, i64 %offset) { ; CHECK-LABEL: st1lane_ro_2d ; CHECK: add x[[XREG:[0-9]+]], x0, x1 ; CHECK: st1.d { v0 }[1], [x[[XREG]]] - %ptr = getelementptr i64* %D, i64 %offset + %ptr = getelementptr i64, i64* %D, i64 %offset %tmp = extractelement <2 x i64> %A, i32 1 store i64 %tmp, i64* %ptr ret void @@ -130,7 +130,7 @@ define void @st1lane_ro_2d(<2 x i64> %A, i64* %D, i64 %offset) { define void @st1lane0_ro_2d(<2 x i64> %A, i64* %D, i64 %offset) { ; CHECK-LABEL: st1lane0_ro_2d ; CHECK: str d0, [x0, x1, lsl #3] - %ptr = getelementptr i64* %D, i64 %offset + %ptr = getelementptr i64, i64* %D, i64 %offset %tmp = extractelement <2 x i64> %A, i32 0 store i64 %tmp, i64* %ptr ret void @@ -148,7 +148,7 @@ define void @st1lane_ro_2d_double(<2 x double> %A, double* %D, i64 %offset) { ; CHECK-LABEL: st1lane_ro_2d_double ; CHECK: add x[[XREG:[0-9]+]], x0, x1 ; CHECK: st1.d { v0 }[1], [x[[XREG]]] - %ptr = getelementptr double* %D, i64 %offset + %ptr = getelementptr double, double* %D, i64 %offset %tmp = extractelement <2 x double> %A, i32 1 store double %tmp, double* %ptr ret void @@ -157,7 +157,7 @@ define void @st1lane_ro_2d_double(<2 x double> %A, double* %D, i64 %offset) { define void @st1lane0_ro_2d_double(<2 x double> %A, double* %D, i64 %offset) { ; CHECK-LABEL: st1lane0_ro_2d_double ; CHECK: str d0, [x0, x1, lsl #3] - %ptr = getelementptr double* %D, i64 %offset + %ptr = getelementptr double, double* %D, i64 %offset %tmp = extractelement <2 x double> %A, i32 0 store double %tmp, double* %ptr ret void @@ -175,7 +175,7 @@ define void @st1lane_ro_8b(<8 x i8> %A, i8* %D, i64 %offset) { ; CHECK-LABEL: st1lane_ro_8b ; CHECK: add x[[XREG:[0-9]+]], x0, x1 ; CHECK: st1.b { v0 }[1], [x[[XREG]]] - %ptr = getelementptr i8* %D, i64 %offset + %ptr = getelementptr i8, i8* %D, i64 %offset %tmp = extractelement <8 x i8> %A, i32 1 store i8 %tmp, i8* %ptr ret void @@ -185,7 +185,7 @@ define void @st1lane0_ro_8b(<8 x i8> %A, i8* %D, i64 %offset) { ; CHECK-LABEL: st1lane0_ro_8b ; CHECK: add x[[XREG:[0-9]+]], x0, x1 ; CHECK: st1.b { v0 }[0], [x[[XREG]]] - %ptr = getelementptr i8* %D, i64 %offset + %ptr = getelementptr i8, i8* %D, i64 %offset %tmp = extractelement <8 x i8> %A, i32 0 store i8 %tmp, i8* %ptr ret void @@ -203,7 +203,7 @@ define void @st1lane_ro_4h(<4 x i16> %A, i16* %D, i64 %offset) { ; CHECK-LABEL: st1lane_ro_4h ; CHECK: add x[[XREG:[0-9]+]], x0, x1 ; CHECK: st1.h { v0 }[1], [x[[XREG]]] - %ptr = getelementptr i16* %D, i64 %offset + %ptr = getelementptr i16, i16* %D, i64 %offset %tmp = extractelement <4 x i16> %A, i32 1 store i16 %tmp, i16* %ptr ret void @@ -212,7 +212,7 @@ define void @st1lane_ro_4h(<4 x i16> %A, i16* %D, i64 %offset) { define void @st1lane0_ro_4h(<4 x i16> %A, i16* %D, i64 %offset) { ; CHECK-LABEL: st1lane0_ro_4h ; CHECK: str h0, [x0, x1, lsl #1] - %ptr = getelementptr i16* %D, i64 %offset + %ptr = getelementptr i16, i16* %D, i64 %offset %tmp = extractelement <4 x i16> %A, i32 0 store i16 %tmp, i16* %ptr ret void @@ -230,7 +230,7 @@ define void @st1lane_ro_2s(<2 x i32> %A, i32* %D, i64 %offset) { ; CHECK-LABEL: st1lane_ro_2s ; CHECK: add x[[XREG:[0-9]+]], x0, x1 ; CHECK: st1.s { v0 }[1], [x[[XREG]]] - %ptr = getelementptr i32* %D, i64 %offset + %ptr = getelementptr i32, i32* %D, i64 %offset %tmp = extractelement <2 x i32> %A, i32 1 store i32 %tmp, i32* %ptr ret void @@ -239,7 +239,7 @@ define void @st1lane_ro_2s(<2 x i32> %A, i32* %D, i64 %offset) { define void @st1lane0_ro_2s(<2 x i32> %A, i32* %D, i64 %offset) { ; CHECK-LABEL: st1lane0_ro_2s ; CHECK: str s0, [x0, x1, lsl #2] - %ptr = getelementptr i32* %D, i64 %offset + %ptr = getelementptr i32, i32* %D, i64 %offset %tmp = extractelement <2 x i32> %A, i32 0 store i32 %tmp, i32* %ptr ret void @@ -257,7 +257,7 @@ define void @st1lane_ro_2s_float(<2 x float> %A, float* %D, i64 %offset) { ; CHECK-LABEL: st1lane_ro_2s_float ; CHECK: add x[[XREG:[0-9]+]], x0, x1 ; CHECK: st1.s { v0 }[1], [x[[XREG]]] - %ptr = getelementptr float* %D, i64 %offset + %ptr = getelementptr float, float* %D, i64 %offset %tmp = extractelement <2 x float> %A, i32 1 store float %tmp, float* %ptr ret void @@ -266,7 +266,7 @@ define void @st1lane_ro_2s_float(<2 x float> %A, float* %D, i64 %offset) { define void @st1lane0_ro_2s_float(<2 x float> %A, float* %D, i64 %offset) { ; CHECK-LABEL: st1lane0_ro_2s_float ; CHECK: str s0, [x0, x1, lsl #2] - %ptr = getelementptr float* %D, i64 %offset + %ptr = getelementptr float, float* %D, i64 %offset %tmp = extractelement <2 x float> %A, i32 0 store float %tmp, float* %ptr ret void @@ -374,21 +374,21 @@ declare void @llvm.aarch64.neon.st4lane.v2i64.p0i64(<2 x i64>, <2 x i64>, <2 x i define void @st2_8b(<8 x i8> %A, <8 x i8> %B, i8* %P) nounwind { ; CHECK-LABEL: st2_8b -; CHECK st2.8b +; CHECK: st2.8b call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %A, <8 x i8> %B, i8* %P) ret void } define void @st3_8b(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, i8* %P) nounwind { ; CHECK-LABEL: st3_8b -; CHECK st3.8b +; CHECK: st3.8b call void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, i8* %P) ret void } define void @st4_8b(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %P) nounwind { ; CHECK-LABEL: st4_8b -; CHECK st4.8b +; CHECK: st4.8b call void @llvm.aarch64.neon.st4.v8i8.p0i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i8* %P) ret void } @@ -399,21 +399,21 @@ declare void @llvm.aarch64.neon.st4.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, <8 x define void @st2_16b(<16 x i8> %A, <16 x i8> %B, i8* %P) nounwind { ; CHECK-LABEL: st2_16b -; CHECK st2.16b +; CHECK: st2.16b call void @llvm.aarch64.neon.st2.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, i8* %P) ret void } define void @st3_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, i8* %P) nounwind { ; CHECK-LABEL: st3_16b -; CHECK st3.16b +; CHECK: st3.16b call void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, i8* %P) ret void } define void @st4_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %P) nounwind { ; CHECK-LABEL: st4_16b -; CHECK st4.16b +; CHECK: st4.16b call void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i8* %P) ret void } @@ -424,21 +424,21 @@ declare void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, define void @st2_4h(<4 x i16> %A, <4 x i16> %B, i16* %P) nounwind { ; CHECK-LABEL: st2_4h -; CHECK st2.4h +; CHECK: st2.4h call void @llvm.aarch64.neon.st2.v4i16.p0i16(<4 x i16> %A, <4 x i16> %B, i16* %P) ret void } define void @st3_4h(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, i16* %P) nounwind { ; CHECK-LABEL: st3_4h -; CHECK st3.4h +; CHECK: st3.4h call void @llvm.aarch64.neon.st3.v4i16.p0i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, i16* %P) ret void } define void @st4_4h(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %P) nounwind { ; CHECK-LABEL: st4_4h -; CHECK st4.4h +; CHECK: st4.4h call void @llvm.aarch64.neon.st4.v4i16.p0i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i16* %P) ret void } @@ -449,21 +449,21 @@ declare void @llvm.aarch64.neon.st4.v4i16.p0i16(<4 x i16>, <4 x i16>, <4 x i16>, define void @st2_8h(<8 x i16> %A, <8 x i16> %B, i16* %P) nounwind { ; CHECK-LABEL: st2_8h -; CHECK st2.8h +; CHECK: st2.8h call void @llvm.aarch64.neon.st2.v8i16.p0i16(<8 x i16> %A, <8 x i16> %B, i16* %P) ret void } define void @st3_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, i16* %P) nounwind { ; CHECK-LABEL: st3_8h -; CHECK st3.8h +; CHECK: st3.8h call void @llvm.aarch64.neon.st3.v8i16.p0i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, i16* %P) ret void } define void @st4_8h(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %P) nounwind { ; CHECK-LABEL: st4_8h -; CHECK st4.8h +; CHECK: st4.8h call void @llvm.aarch64.neon.st4.v8i16.p0i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i16* %P) ret void } @@ -474,21 +474,21 @@ declare void @llvm.aarch64.neon.st4.v8i16.p0i16(<8 x i16>, <8 x i16>, <8 x i16>, define void @st2_2s(<2 x i32> %A, <2 x i32> %B, i32* %P) nounwind { ; CHECK-LABEL: st2_2s -; CHECK st2.2s +; CHECK: st2.2s call void @llvm.aarch64.neon.st2.v2i32.p0i32(<2 x i32> %A, <2 x i32> %B, i32* %P) ret void } define void @st3_2s(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32* %P) nounwind { ; CHECK-LABEL: st3_2s -; CHECK st3.2s +; CHECK: st3.2s call void @llvm.aarch64.neon.st3.v2i32.p0i32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, i32* %P) ret void } define void @st4_2s(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %P) nounwind { ; CHECK-LABEL: st4_2s -; CHECK st4.2s +; CHECK: st4.2s call void @llvm.aarch64.neon.st4.v2i32.p0i32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i32* %P) ret void } @@ -499,21 +499,21 @@ declare void @llvm.aarch64.neon.st4.v2i32.p0i32(<2 x i32>, <2 x i32>, <2 x i32>, define void @st2_4s(<4 x i32> %A, <4 x i32> %B, i32* %P) nounwind { ; CHECK-LABEL: st2_4s -; CHECK st2.4s +; CHECK: st2.4s call void @llvm.aarch64.neon.st2.v4i32.p0i32(<4 x i32> %A, <4 x i32> %B, i32* %P) ret void } define void @st3_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32* %P) nounwind { ; CHECK-LABEL: st3_4s -; CHECK st3.4s +; CHECK: st3.4s call void @llvm.aarch64.neon.st3.v4i32.p0i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, i32* %P) ret void } define void @st4_4s(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %P) nounwind { ; CHECK-LABEL: st4_4s -; CHECK st4.4s +; CHECK: st4.4s call void @llvm.aarch64.neon.st4.v4i32.p0i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i32* %P) ret void } @@ -522,23 +522,24 @@ declare void @llvm.aarch64.neon.st2.v4i32.p0i32(<4 x i32>, <4 x i32>, i32*) noun declare void @llvm.aarch64.neon.st3.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, i32*) nounwind readonly declare void @llvm.aarch64.neon.st4.v4i32.p0i32(<4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32*) nounwind readonly +; If there's only one element, st2/3/4 don't make much sense, stick to st1. define void @st2_1d(<1 x i64> %A, <1 x i64> %B, i64* %P) nounwind { ; CHECK-LABEL: st2_1d -; CHECK st1.2d +; CHECK: st1.1d call void @llvm.aarch64.neon.st2.v1i64.p0i64(<1 x i64> %A, <1 x i64> %B, i64* %P) ret void } define void @st3_1d(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, i64* %P) nounwind { ; CHECK-LABEL: st3_1d -; CHECK st1.3d +; CHECK: st1.1d call void @llvm.aarch64.neon.st3.v1i64.p0i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, i64* %P) ret void } define void @st4_1d(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %P) nounwind { ; CHECK-LABEL: st4_1d -; CHECK st1.4d +; CHECK: st1.1d call void @llvm.aarch64.neon.st4.v1i64.p0i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64* %P) ret void } @@ -549,21 +550,21 @@ declare void @llvm.aarch64.neon.st4.v1i64.p0i64(<1 x i64>, <1 x i64>, <1 x i64>, define void @st2_2d(<2 x i64> %A, <2 x i64> %B, i64* %P) nounwind { ; CHECK-LABEL: st2_2d -; CHECK st2.2d +; CHECK: st2.2d call void @llvm.aarch64.neon.st2.v2i64.p0i64(<2 x i64> %A, <2 x i64> %B, i64* %P) ret void } define void @st3_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, i64* %P) nounwind { ; CHECK-LABEL: st3_2d -; CHECK st2.3d +; CHECK: st3.2d call void @llvm.aarch64.neon.st3.v2i64.p0i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, i64* %P) ret void } define void @st4_2d(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %P) nounwind { ; CHECK-LABEL: st4_2d -; CHECK st2.4d +; CHECK: st4.2d call void @llvm.aarch64.neon.st4.v2i64.p0i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64* %P) ret void } diff --git a/test/CodeGen/AArch64/arm64-stack-no-frame.ll b/test/CodeGen/AArch64/arm64-stack-no-frame.ll index b5970c0..22a6707 100644 --- a/test/CodeGen/AArch64/arm64-stack-no-frame.ll +++ b/test/CodeGen/AArch64/arm64-stack-no-frame.ll @@ -9,10 +9,10 @@ define void @test_stack_no_frame() { ; CHECK: test_stack_no_frame ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]] %local = alloca [20 x i64] - %val = load volatile [20 x i64]* @global, align 8 + %val = load volatile [20 x i64], [20 x i64]* @global, align 8 store volatile [20 x i64] %val, [20 x i64]* %local, align 8 - %val2 = load volatile [20 x i64]* %local, align 8 + %val2 = load volatile [20 x i64], [20 x i64]* %local, align 8 store volatile [20 x i64] %val2, [20 x i64]* @global, align 8 ; CHECK: add sp, sp, #[[STACKSIZE]] diff --git a/test/CodeGen/AArch64/arm64-stackmap.ll b/test/CodeGen/AArch64/arm64-stackmap.ll index 144c2fd..29e4484 100644 --- a/test/CodeGen/AArch64/arm64-stackmap.ll +++ b/test/CodeGen/AArch64/arm64-stackmap.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=arm64-apple-darwin < %s | FileCheck %s -; RUN: llc -mtriple=arm64-apple-darwin -fast-isel -fast-isel-abort < %s | FileCheck %s +; RUN: llc -mtriple=arm64-apple-darwin -fast-isel -fast-isel-abort=1 < %s | FileCheck %s ; ; Note: Print verbose stackmaps using -debug-only=stackmaps. diff --git a/test/CodeGen/AArch64/arm64-stp.ll b/test/CodeGen/AArch64/arm64-stp.ll index 40bdf22..4d76396 100644 --- a/test/CodeGen/AArch64/arm64-stp.ll +++ b/test/CodeGen/AArch64/arm64-stp.ll @@ -6,7 +6,7 @@ ; CHECK: stp w0, w1, [x2] define void @stp_int(i32 %a, i32 %b, i32* nocapture %p) nounwind { store i32 %a, i32* %p, align 4 - %add.ptr = getelementptr inbounds i32* %p, i64 1 + %add.ptr = getelementptr inbounds i32, i32* %p, i64 1 store i32 %b, i32* %add.ptr, align 4 ret void } @@ -15,7 +15,7 @@ define void @stp_int(i32 %a, i32 %b, i32* nocapture %p) nounwind { ; CHECK: stp x0, x1, [x2] define void @stp_long(i64 %a, i64 %b, i64* nocapture %p) nounwind { store i64 %a, i64* %p, align 8 - %add.ptr = getelementptr inbounds i64* %p, i64 1 + %add.ptr = getelementptr inbounds i64, i64* %p, i64 1 store i64 %b, i64* %add.ptr, align 8 ret void } @@ -24,7 +24,7 @@ define void @stp_long(i64 %a, i64 %b, i64* nocapture %p) nounwind { ; CHECK: stp s0, s1, [x0] define void @stp_float(float %a, float %b, float* nocapture %p) nounwind { store float %a, float* %p, align 4 - %add.ptr = getelementptr inbounds float* %p, i64 1 + %add.ptr = getelementptr inbounds float, float* %p, i64 1 store float %b, float* %add.ptr, align 4 ret void } @@ -33,7 +33,7 @@ define void @stp_float(float %a, float %b, float* nocapture %p) nounwind { ; CHECK: stp d0, d1, [x0] define void @stp_double(double %a, double %b, double* nocapture %p) nounwind { store double %a, double* %p, align 8 - %add.ptr = getelementptr inbounds double* %p, i64 1 + %add.ptr = getelementptr inbounds double, double* %p, i64 1 store double %b, double* %add.ptr, align 8 ret void } @@ -43,9 +43,9 @@ define void @stur_int(i32 %a, i32 %b, i32* nocapture %p) nounwind { ; STUR_CHK: stur_int ; STUR_CHK: stp w{{[0-9]+}}, {{w[0-9]+}}, [x{{[0-9]+}}, #-8] ; STUR_CHK-NEXT: ret - %p1 = getelementptr inbounds i32* %p, i32 -1 + %p1 = getelementptr inbounds i32, i32* %p, i32 -1 store i32 %a, i32* %p1, align 2 - %p2 = getelementptr inbounds i32* %p, i32 -2 + %p2 = getelementptr inbounds i32, i32* %p, i32 -2 store i32 %b, i32* %p2, align 2 ret void } @@ -54,9 +54,9 @@ define void @stur_long(i64 %a, i64 %b, i64* nocapture %p) nounwind { ; STUR_CHK: stur_long ; STUR_CHK: stp x{{[0-9]+}}, {{x[0-9]+}}, [x{{[0-9]+}}, #-16] ; STUR_CHK-NEXT: ret - %p1 = getelementptr inbounds i64* %p, i32 -1 + %p1 = getelementptr inbounds i64, i64* %p, i32 -1 store i64 %a, i64* %p1, align 2 - %p2 = getelementptr inbounds i64* %p, i32 -2 + %p2 = getelementptr inbounds i64, i64* %p, i32 -2 store i64 %b, i64* %p2, align 2 ret void } @@ -65,9 +65,9 @@ define void @stur_float(float %a, float %b, float* nocapture %p) nounwind { ; STUR_CHK: stur_float ; STUR_CHK: stp s{{[0-9]+}}, {{s[0-9]+}}, [x{{[0-9]+}}, #-8] ; STUR_CHK-NEXT: ret - %p1 = getelementptr inbounds float* %p, i32 -1 + %p1 = getelementptr inbounds float, float* %p, i32 -1 store float %a, float* %p1, align 2 - %p2 = getelementptr inbounds float* %p, i32 -2 + %p2 = getelementptr inbounds float, float* %p, i32 -2 store float %b, float* %p2, align 2 ret void } @@ -76,9 +76,9 @@ define void @stur_double(double %a, double %b, double* nocapture %p) nounwind { ; STUR_CHK: stur_double ; STUR_CHK: stp d{{[0-9]+}}, {{d[0-9]+}}, [x{{[0-9]+}}, #-16] ; STUR_CHK-NEXT: ret - %p1 = getelementptr inbounds double* %p, i32 -1 + %p1 = getelementptr inbounds double, double* %p, i32 -1 store double %a, double* %p1, align 2 - %p2 = getelementptr inbounds double* %p, i32 -2 + %p2 = getelementptr inbounds double, double* %p, i32 -2 store double %b, double* %p2, align 2 ret void } diff --git a/test/CodeGen/AArch64/arm64-strict-align.ll b/test/CodeGen/AArch64/arm64-strict-align.ll index 5d13704..b707527 100644 --- a/test/CodeGen/AArch64/arm64-strict-align.ll +++ b/test/CodeGen/AArch64/arm64-strict-align.ll @@ -10,7 +10,7 @@ define i32 @f0(i32* nocapture %p) nounwind { ; CHECK: ldr w0, [x0] ; CHECK: ret - %tmp = load i32* %p, align 2 + %tmp = load i32, i32* %p, align 2 ret i32 %tmp } @@ -21,6 +21,6 @@ define i64 @f1(i64* nocapture %p) nounwind { ; CHECK: ldr x0, [x0] ; CHECK: ret - %tmp = load i64* %p, align 4 + %tmp = load i64, i64* %p, align 4 ret i64 %tmp } diff --git a/test/CodeGen/AArch64/arm64-stur.ll b/test/CodeGen/AArch64/arm64-stur.ll index a2e684d..5f4cb9f 100644 --- a/test/CodeGen/AArch64/arm64-stur.ll +++ b/test/CodeGen/AArch64/arm64-stur.ll @@ -6,7 +6,7 @@ define void @foo1(i32* %p, i64 %val) nounwind { ; CHECK: stur w1, [x0, #-4] ; CHECK-NEXT: ret %tmp1 = trunc i64 %val to i32 - %ptr = getelementptr inbounds i32* %p, i64 -1 + %ptr = getelementptr inbounds i32, i32* %p, i64 -1 store i32 %tmp1, i32* %ptr, align 4 ret void } @@ -15,7 +15,7 @@ define void @foo2(i16* %p, i64 %val) nounwind { ; CHECK: sturh w1, [x0, #-2] ; CHECK-NEXT: ret %tmp1 = trunc i64 %val to i16 - %ptr = getelementptr inbounds i16* %p, i64 -1 + %ptr = getelementptr inbounds i16, i16* %p, i64 -1 store i16 %tmp1, i16* %ptr, align 2 ret void } @@ -24,7 +24,7 @@ define void @foo3(i8* %p, i64 %val) nounwind { ; CHECK: sturb w1, [x0, #-1] ; CHECK-NEXT: ret %tmp1 = trunc i64 %val to i8 - %ptr = getelementptr inbounds i8* %p, i64 -1 + %ptr = getelementptr inbounds i8, i8* %p, i64 -1 store i8 %tmp1, i8* %ptr, align 1 ret void } @@ -33,7 +33,7 @@ define void @foo4(i16* %p, i32 %val) nounwind { ; CHECK: sturh w1, [x0, #-2] ; CHECK-NEXT: ret %tmp1 = trunc i32 %val to i16 - %ptr = getelementptr inbounds i16* %p, i32 -1 + %ptr = getelementptr inbounds i16, i16* %p, i32 -1 store i16 %tmp1, i16* %ptr, align 2 ret void } @@ -42,7 +42,7 @@ define void @foo5(i8* %p, i32 %val) nounwind { ; CHECK: sturb w1, [x0, #-1] ; CHECK-NEXT: ret %tmp1 = trunc i32 %val to i8 - %ptr = getelementptr inbounds i8* %p, i32 -1 + %ptr = getelementptr inbounds i8, i8* %p, i32 -1 store i8 %tmp1, i8* %ptr, align 1 ret void } @@ -53,7 +53,7 @@ define void @foo(%struct.X* nocapture %p) nounwind optsize ssp { ; CHECK: stur xzr, [x0, #12] ; CHECK-NEXT: stur xzr, [x0, #4] ; CHECK-NEXT: ret - %B = getelementptr inbounds %struct.X* %p, i64 0, i32 1 + %B = getelementptr inbounds %struct.X, %struct.X* %p, i64 0, i32 1 %val = bitcast i64* %B to i8* call void @llvm.memset.p0i8.i64(i8* %val, i8 0, i64 16, i32 1, i1 false) ret void diff --git a/test/CodeGen/AArch64/arm64-this-return.ll b/test/CodeGen/AArch64/arm64-this-return.ll index 30f5b9b..3be1a69 100644 --- a/test/CodeGen/AArch64/arm64-this-return.ll +++ b/test/CodeGen/AArch64/arm64-this-return.ll @@ -23,7 +23,7 @@ entry: ; CHECK: b {{_?B_ctor_base}} %0 = bitcast %struct.C* %this to %struct.A* %call = tail call %struct.A* @A_ctor_base(%struct.A* %0) - %1 = getelementptr inbounds %struct.C* %this, i32 0, i32 0 + %1 = getelementptr inbounds %struct.C, %struct.C* %this, i32 0, i32 0 %call2 = tail call %struct.B* @B_ctor_base(%struct.B* %1, i32 %x) ret %struct.C* %this } @@ -37,7 +37,7 @@ entry: ; CHECK-NOT: b {{_?B_ctor_base_nothisret}} %0 = bitcast %struct.C* %this to %struct.A* %call = tail call %struct.A* @A_ctor_base_nothisret(%struct.A* %0) - %1 = getelementptr inbounds %struct.C* %this, i32 0, i32 0 + %1 = getelementptr inbounds %struct.C, %struct.C* %this, i32 0, i32 0 %call2 = tail call %struct.B* @B_ctor_base_nothisret(%struct.B* %1, i32 %x) ret %struct.C* %this } @@ -65,7 +65,7 @@ entry: ; CHECK: bl {{_?B_ctor_complete}} ; CHECK-NOT: mov x0, {{x[0-9]+}} ; CHECK: b {{_?B_ctor_complete}} - %b = getelementptr inbounds %struct.D* %this, i32 0, i32 0 + %b = getelementptr inbounds %struct.D, %struct.D* %this, i32 0, i32 0 %call = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x) %call2 = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x) ret %struct.D* %this @@ -75,9 +75,9 @@ define %struct.E* @E_ctor_base(%struct.E* %this, i32 %x) { entry: ; CHECK-LABEL: E_ctor_base: ; CHECK-NOT: b {{_?B_ctor_complete}} - %b = getelementptr inbounds %struct.E* %this, i32 0, i32 0 + %b = getelementptr inbounds %struct.E, %struct.E* %this, i32 0, i32 0 %call = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x) - %b2 = getelementptr inbounds %struct.E* %this, i32 0, i32 1 + %b2 = getelementptr inbounds %struct.E, %struct.E* %this, i32 0, i32 1 %call2 = tail call %struct.B* @B_ctor_complete(%struct.B* %b2, i32 %x) ret %struct.E* %this } diff --git a/test/CodeGen/AArch64/arm64-tls-darwin.ll b/test/CodeGen/AArch64/arm64-tls-darwin.ll index 5e8ec33..fa4e833 100644 --- a/test/CodeGen/AArch64/arm64-tls-darwin.ll +++ b/test/CodeGen/AArch64/arm64-tls-darwin.ll @@ -13,6 +13,6 @@ define i8 @get_var() { ; CHECK: blr [[TLV_GET_ADDR]] ; CHECK: ldrb w0, [x0] - %val = load i8* @var, align 1 + %val = load i8, i8* @var, align 1 ret i8 %val } diff --git a/test/CodeGen/AArch64/arm64-tls-dynamic-together.ll b/test/CodeGen/AArch64/arm64-tls-dynamic-together.ll index 3daae62..f94f88a 100644 --- a/test/CodeGen/AArch64/arm64-tls-dynamic-together.ll +++ b/test/CodeGen/AArch64/arm64-tls-dynamic-together.ll @@ -10,7 +10,7 @@ define i32 @test_generaldynamic() { ; CHECK-LABEL: test_generaldynamic: - %val = load i32* @general_dynamic_var + %val = load i32, i32* @general_dynamic_var ret i32 %val ; CHECK: .tlsdesccall general_dynamic_var diff --git a/test/CodeGen/AArch64/arm64-tls-dynamics.ll b/test/CodeGen/AArch64/arm64-tls-dynamics.ll index 30ea63b..88700a1 100644 --- a/test/CodeGen/AArch64/arm64-tls-dynamics.ll +++ b/test/CodeGen/AArch64/arm64-tls-dynamics.ll @@ -1,30 +1,44 @@ -; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s +; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -aarch64-elf-ldtls-generation=1 -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-RELOC %s +; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOLD %s +; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -filetype=obj < %s | llvm-objdump -r - | FileCheck --check-prefix=CHECK-NOLD-RELOC %s @general_dynamic_var = external thread_local global i32 define i32 @test_generaldynamic() { ; CHECK-LABEL: test_generaldynamic: - %val = load i32* @general_dynamic_var + %val = load i32, i32* @general_dynamic_var ret i32 %val - ; FIXME: the adrp instructions are redundant (if harmless). -; CHECK: adrp [[TLSDESC_HI:x[0-9]+]], :tlsdesc:general_dynamic_var -; CHECK: add x0, [[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var -; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var] -; CHECK: .tlsdesccall general_dynamic_var +; CHECK-NEXT: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var] +; CHECK-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var +; CHECK-NEXT: .tlsdesccall general_dynamic_var ; CHECK-NEXT: blr [[CALLEE]] +; CHECK-NOLD: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var +; CHECK-NOLD-NEXT: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var] +; CHECK-NOLD-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var +; CHECK-NOLD-NEXT: .tlsdesccall general_dynamic_var +; CHECK-NOLD-NEXT: blr [[CALLEE]] + + ; CHECK: mrs x[[TP:[0-9]+]], TPIDR_EL0 ; CHECK: ldr w0, [x[[TP]], x0] +; CHECK-NOLD: mrs x[[TP:[0-9]+]], TPIDR_EL0 +; CHECK-NOLD: ldr w0, [x[[TP]], x0] ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL + } define i32* @test_generaldynamic_addr() { @@ -32,21 +46,25 @@ define i32* @test_generaldynamic_addr() { ret i32* @general_dynamic_var - ; FIXME: the adrp instructions are redundant (if harmless). -; CHECK: adrp [[TLSDESC_HI:x[0-9]+]], :tlsdesc:general_dynamic_var -; CHECK: add x0, [[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:general_dynamic_var -; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var] -; CHECK: .tlsdesccall general_dynamic_var +; CHECK-NEXT: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var] +; CHECK-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:general_dynamic_var +; CHECK-NEXT: .tlsdesccall general_dynamic_var ; CHECK-NEXT: blr [[CALLEE]] ; CHECK: mrs [[TP:x[0-9]+]], TPIDR_EL0 ; CHECK: add x0, [[TP]], x0 ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL + +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL + } @local_dynamic_var = external thread_local(localdynamic) global i32 @@ -54,58 +72,75 @@ define i32* @test_generaldynamic_addr() { define i32 @test_localdynamic() { ; CHECK-LABEL: test_localdynamic: - %val = load i32* @local_dynamic_var + %val = load i32, i32* @local_dynamic_var ret i32 %val ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_ -; CHECK: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_ -; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_ -; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_] -; CHECK: .tlsdesccall _TLS_MODULE_BASE_ +; CHECK-NEXT: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_] +; CHECK-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_ +; CHECK-NEXT: .tlsdesccall _TLS_MODULE_BASE_ ; CHECK-NEXT: blr [[CALLEE]] - -; CHECK: movz [[DTP_OFFSET:x[0-9]+]], #:dtprel_g1:local_dynamic_var -; CHECK: movk [[DTP_OFFSET]], #:dtprel_g0_nc:local_dynamic_var - -; CHECK: add x[[TPREL:[0-9]+]], x0, [[DTP_OFFSET]] - +; CHECK-NEXT: add x[[TPOFF:[0-9]+]], x0, :dtprel_hi12:local_dynamic_var +; CHECK-NEXT: add x[[TPOFF]], x[[TPOFF]], :dtprel_lo12_nc:local_dynamic_var ; CHECK: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0 +; CHECK: ldr w0, [x[[TPIDR]], x[[TPOFF]]] + +; CHECK-NOLD: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:local_dynamic_var +; CHECK-NOLD-NEXT: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:local_dynamic_var] +; CHECK-NOLD-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:local_dynamic_var +; CHECK-NOLD-NEXT: .tlsdesccall local_dynamic_var +; CHECK-NOLD-NEXT: blr [[CALLEE]] +; CHECK-NOLD: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0 +; CHECK-NOLD: ldr w0, [x[[TPIDR]], x0] -; CHECK: ldr w0, [x[[TPIDR]], x[[TPREL]]] ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL +; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_HI12 +; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC + +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL } define i32* @test_localdynamic_addr() { ; CHECK-LABEL: test_localdynamic_addr: - ret i32* @local_dynamic_var - ; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_ -; CHECK: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_ -; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_ -; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_] -; CHECK: .tlsdesccall _TLS_MODULE_BASE_ +; CHECK-NEXT: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_] +; CHECK-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_ +; CHECK-NEXT: .tlsdesccall _TLS_MODULE_BASE_ ; CHECK-NEXT: blr [[CALLEE]] - -; CHECK: movz [[DTP_OFFSET:x[0-9]+]], #:dtprel_g1:local_dynamic_var -; CHECK: movk [[DTP_OFFSET]], #:dtprel_g0_nc:local_dynamic_var - -; CHECK: add [[TPREL:x[0-9]+]], x0, [[DTP_OFFSET]] - -; CHECK: mrs [[TPIDR:x[0-9]+]], TPIDR_EL0 - -; CHECK: add x0, [[TPIDR]], [[TPREL]] +; CHECK-NEXT: add x[[TPOFF:[0-9]+]], x0, :dtprel_hi12:local_dynamic_var +; CHECK-NEXT: add x[[TPOFF]], x[[TPOFF]], :dtprel_lo12_nc:local_dynamic_var +; CHECK: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0 +; CHECK: add x0, x[[TPIDR]], x[[TPOFF]] + +; CHECK-NOLD: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:local_dynamic_var +; CHECK-NOLD-NEXT: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:local_dynamic_var] +; CHECK-NOLD-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:local_dynamic_var +; CHECK-NOLD-NEXT: .tlsdesccall local_dynamic_var +; CHECK-NOLD-NEXT: blr [[CALLEE]] +; CHECK-NOLD: mrs x[[TPIDR:[0-9]+]], TPIDR_EL0 +; CHECK-NOLD: add x0, x[[TPIDR]], x0 + ret i32* @local_dynamic_var ; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 -; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC +; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL +; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_HI12 +; CHECK-RELOC: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC +; CHECK-NOLD-RELOC: R_AARCH64_TLSDESC_CALL } ; The entire point of the local-dynamic access model is to have a single call to @@ -116,17 +151,16 @@ define i32* @test_localdynamic_addr() { define i32 @test_localdynamic_deduplicate() { ; CHECK-LABEL: test_localdynamic_deduplicate: - %val = load i32* @local_dynamic_var - %val2 = load i32* @local_dynamic_var2 + %val = load i32, i32* @local_dynamic_var + %val2 = load i32, i32* @local_dynamic_var2 %sum = add i32 %val, %val2 ret i32 %sum -; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_ -; CHECK: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_ -; CHECK: adrp x[[TLSDESC_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_ -; CHECK: ldr [[CALLEE:x[0-9]+]], [x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_] -; CHECK: .tlsdesccall _TLS_MODULE_BASE_ +; CHECK: adrp x[[DTPREL_HI:[0-9]+]], :tlsdesc:_TLS_MODULE_BASE_ +; CHECK-NEXT: ldr [[CALLEE:x[0-9]+]], [x[[DTPREL_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE_] +; CHECK-NEXT: add x0, x[[TLSDESC_HI]], :tlsdesc_lo12:_TLS_MODULE_BASE +; CHECK-NEXT: .tlsdesccall _TLS_MODULE_BASE_ ; CHECK-NEXT: blr [[CALLEE]] ; CHECK-NOT: _TLS_MODULE_BASE_ diff --git a/test/CodeGen/AArch64/arm64-tls-execs.ll b/test/CodeGen/AArch64/arm64-tls-execs.ll index f0130d8..deced69 100644 --- a/test/CodeGen/AArch64/arm64-tls-execs.ll +++ b/test/CodeGen/AArch64/arm64-tls-execs.ll @@ -5,7 +5,7 @@ define i32 @test_initial_exec() { ; CHECK-LABEL: test_initial_exec: - %val = load i32* @initial_exec_var + %val = load i32, i32* @initial_exec_var ; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var ; CHECK: ldr x[[TP_OFFSET:[0-9]+]], [x[[GOTADDR]], :gottprel_lo12:initial_exec_var] @@ -36,16 +36,15 @@ define i32* @test_initial_exec_addr() { define i32 @test_local_exec() { ; CHECK-LABEL: test_local_exec: - %val = load i32* @local_exec_var + %val = load i32, i32* @local_exec_var -; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var // encoding: [0bAAA{{[01]+}},A,0b101AAAAA,0x92] -; CHECK: movk [[TP_OFFSET]], #:tprel_g0_nc:local_exec_var -; CHECK: mrs x[[TP:[0-9]+]], TPIDR_EL0 -; CHECK: ldr w0, [x[[TP]], [[TP_OFFSET]]] - -; CHECK-RELOC: R_AARCH64_TLSLE_MOVW_TPREL_G1 -; CHECK-RELOC: R_AARCH64_TLSLE_MOVW_TPREL_G0_NC +; CHECK: mrs x[[R1:[0-9]+]], TPIDR_EL0 +; CHECK: add x[[R2:[0-9]+]], x[[R1]], :tprel_hi12:local_exec_var +; CHECK: add x[[R3:[0-9]+]], x[[R2]], :tprel_lo12_nc:local_exec_var +; CHECK: ldr w0, [x[[R3]]] +; CHECK-RELOC: R_AARCH64_TLSLE_ADD_TPREL_HI12 +; CHECK-RELOC: R_AARCH64_TLSLE_ADD_TPREL_LO12_NC ret i32 %val } @@ -53,11 +52,11 @@ define i32* @test_local_exec_addr() { ; CHECK-LABEL: test_local_exec_addr: ret i32* @local_exec_var -; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var -; CHECK: movk [[TP_OFFSET]], #:tprel_g0_nc:local_exec_var -; CHECK: mrs [[TP:x[0-9]+]], TPIDR_EL0 -; CHECK: add x0, [[TP]], [[TP_OFFSET]] +; CHECK: mrs x[[R1:[0-9]+]], TPIDR_EL0 +; CHECK: add x[[R2:[0-9]+]], x[[R1]], :tprel_hi12:local_exec_var +; CHECK: add x0, x[[R2]], :tprel_lo12_nc:local_exec_var +; CHECK: ret -; CHECK-RELOC: R_AARCH64_TLSLE_MOVW_TPREL_G1 -; CHECK-RELOC: R_AARCH64_TLSLE_MOVW_TPREL_G0_NC +; CHECK-RELOC: R_AARCH64_TLSLE_ADD_TPREL_HI12 +; CHECK-RELOC: R_AARCH64_TLSLE_ADD_TPREL_LO12_NC } diff --git a/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll b/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll index 923742d..1b1681d 100644 --- a/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll +++ b/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll @@ -8,11 +8,11 @@ define i32 @func(i32 %i, i32 %j, i32 %k) #0 { entry: ; CHECK: ldr {{w[0-9]+}}, [x[[REG:[0-9]+]], #4] ; CHECK: str {{w[0-9]+}}, [x[[REG]], #8] - %0 = load i32** @a, align 8, !tbaa !1 - %arrayidx = getelementptr inbounds i32* %0, i64 2 + %0 = load i32*, i32** @a, align 8, !tbaa !1 + %arrayidx = getelementptr inbounds i32, i32* %0, i64 2 store i32 %i, i32* %arrayidx, align 4, !tbaa !5 - %arrayidx1 = getelementptr inbounds i32* %0, i64 1 - %1 = load i32* %arrayidx1, align 4, !tbaa !5 + %arrayidx1 = getelementptr inbounds i32, i32* %0, i64 1 + %1 = load i32, i32* %arrayidx1, align 4, !tbaa !5 %add = add nsw i32 %k, %i store i32 %add, i32* @m, align 4, !tbaa !5 ret i32 %1 diff --git a/test/CodeGen/AArch64/arm64-trn.ll b/test/CodeGen/AArch64/arm64-trn.ll index 2db7a14..92ccf05 100644 --- a/test/CodeGen/AArch64/arm64-trn.ll +++ b/test/CodeGen/AArch64/arm64-trn.ll @@ -5,8 +5,8 @@ define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: trn1.8b ;CHECK: trn2.8b ;CHECK-NEXT: add.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> %tmp5 = add <8 x i8> %tmp3, %tmp4 @@ -18,8 +18,8 @@ define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK: trn1.4h ;CHECK: trn2.4h ;CHECK-NEXT: add.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6> %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7> %tmp5 = add <4 x i16> %tmp3, %tmp4 @@ -32,8 +32,8 @@ define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK: zip1.2s ;CHECK: zip2.2s ;CHECK-NEXT: add.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 0, i32 2> %tmp4 = shufflevector <2 x i32> %tmp1, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 3> %tmp5 = add <2 x i32> %tmp3, %tmp4 @@ -45,8 +45,8 @@ define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK: zip1.2s ;CHECK: zip2.2s ;CHECK-NEXT: fadd.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2> %tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3> %tmp5 = fadd <2 x float> %tmp3, %tmp4 @@ -58,8 +58,8 @@ define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK: trn1.16b ;CHECK: trn2.16b ;CHECK-NEXT: add.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30> %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31> %tmp5 = add <16 x i8> %tmp3, %tmp4 @@ -71,8 +71,8 @@ define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK: trn1.8h ;CHECK: trn2.8h ;CHECK-NEXT: add.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> %tmp5 = add <8 x i16> %tmp3, %tmp4 @@ -84,8 +84,8 @@ define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK: trn1.4s ;CHECK: trn2.4s ;CHECK-NEXT: add.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6> %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7> %tmp5 = add <4 x i32> %tmp3, %tmp4 @@ -97,8 +97,8 @@ define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK: trn1.4s ;CHECK: trn2.4s ;CHECK-NEXT: fadd.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6> %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7> %tmp5 = fadd <4 x float> %tmp3, %tmp4 @@ -112,8 +112,8 @@ define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: trn1.8b ;CHECK: trn2.8b ;CHECK-NEXT: add.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 2, i32 10, i32 undef, i32 12, i32 6, i32 14> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 undef, i32 undef, i32 15> %tmp5 = add <8 x i8> %tmp3, %tmp4 @@ -125,8 +125,8 @@ define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK: trn1.8h ;CHECK: trn2.8h ;CHECK-NEXT: add.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 undef, i32 undef, i32 4, i32 12, i32 6, i32 14> %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 undef, i32 3, i32 11, i32 5, i32 13, i32 undef, i32 undef> %tmp5 = add <8 x i16> %tmp3, %tmp4 diff --git a/test/CodeGen/AArch64/arm64-trunc-store.ll b/test/CodeGen/AArch64/arm64-trunc-store.ll index cf15247..7cde629 100644 --- a/test/CodeGen/AArch64/arm64-trunc-store.ll +++ b/test/CodeGen/AArch64/arm64-trunc-store.ll @@ -25,10 +25,10 @@ define void @fct32(i32 %arg, i64 %var) { ; CHECK-NEXT: str w1, {{\[}}[[GLOBALADDR]], w[[OFFSETREGNUM]], sxtw #2] ; CHECK-NEXT: ret bb: - %.pre37 = load i32** @zptr32, align 8 + %.pre37 = load i32*, i32** @zptr32, align 8 %dec = add nsw i32 %arg, -1 %idxprom8 = sext i32 %dec to i64 - %arrayidx9 = getelementptr inbounds i32* %.pre37, i64 %idxprom8 + %arrayidx9 = getelementptr inbounds i32, i32* %.pre37, i64 %idxprom8 %tmp = trunc i64 %var to i32 store i32 %tmp, i32* %arrayidx9, align 4 ret void @@ -45,10 +45,10 @@ define void @fct16(i32 %arg, i64 %var) { ; CHECK-NEXT: strh w1, {{\[}}[[GLOBALADDR]], w[[OFFSETREGNUM]], sxtw #1] ; CHECK-NEXT: ret bb: - %.pre37 = load i16** @zptr16, align 8 + %.pre37 = load i16*, i16** @zptr16, align 8 %dec = add nsw i32 %arg, -1 %idxprom8 = sext i32 %dec to i64 - %arrayidx9 = getelementptr inbounds i16* %.pre37, i64 %idxprom8 + %arrayidx9 = getelementptr inbounds i16, i16* %.pre37, i64 %idxprom8 %tmp = trunc i64 %var to i16 store i16 %tmp, i16* %arrayidx9, align 4 ret void @@ -65,10 +65,10 @@ define void @fct8(i32 %arg, i64 %var) { ; CHECK-NEXT: sturb w1, {{\[}}[[ADDR]], #-1] ; CHECK-NEXT: ret bb: - %.pre37 = load i8** @zptr8, align 8 + %.pre37 = load i8*, i8** @zptr8, align 8 %dec = add nsw i32 %arg, -1 %idxprom8 = sext i32 %dec to i64 - %arrayidx9 = getelementptr inbounds i8* %.pre37, i64 %idxprom8 + %arrayidx9 = getelementptr inbounds i8, i8* %.pre37, i64 %idxprom8 %tmp = trunc i64 %var to i8 store i8 %tmp, i8* %arrayidx9, align 4 ret void diff --git a/test/CodeGen/AArch64/arm64-umaxv.ll b/test/CodeGen/AArch64/arm64-umaxv.ll index d523f31..a77f228 100644 --- a/test/CodeGen/AArch64/arm64-umaxv.ll +++ b/test/CodeGen/AArch64/arm64-umaxv.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s +; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s define i32 @vmax_u8x8(<8 x i8> %a) nounwind ssp { ; CHECK-LABEL: vmax_u8x8: @@ -86,7 +86,79 @@ return: ret i32 %retval.0 } +define <8 x i8> @test_vmaxv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) { +; CHECK-LABEL: test_vmaxv_u8_used_by_laneop: +; CHECK: umaxv.8b b[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a2) + %1 = trunc i32 %0 to i8 + %2 = insertelement <8 x i8> %a1, i8 %1, i32 3 + ret <8 x i8> %2 +} + +define <4 x i16> @test_vmaxv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) { +; CHECK-LABEL: test_vmaxv_u16_used_by_laneop: +; CHECK: umaxv.4h h[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a2) + %1 = trunc i32 %0 to i16 + %2 = insertelement <4 x i16> %a1, i16 %1, i32 3 + ret <4 x i16> %2 +} + +define <2 x i32> @test_vmaxv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) { +; CHECK-LABEL: test_vmaxv_u32_used_by_laneop: +; CHECK: umaxp.2s v[[REGNUM:[0-9]+]], v1, v1 +; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32> %a2) + %1 = insertelement <2 x i32> %a1, i32 %0, i32 1 + ret <2 x i32> %1 +} + +define <16 x i8> @test_vmaxvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) { +; CHECK-LABEL: test_vmaxvq_u8_used_by_laneop: +; CHECK: umaxv.16b b[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a2) + %1 = trunc i32 %0 to i8 + %2 = insertelement <16 x i8> %a1, i8 %1, i32 3 + ret <16 x i8> %2 +} + +define <8 x i16> @test_vmaxvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) { +; CHECK-LABEL: test_vmaxvq_u16_used_by_laneop: +; CHECK: umaxv.8h h[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a2) + %1 = trunc i32 %0 to i16 + %2 = insertelement <8 x i16> %a1, i16 %1, i32 3 + ret <8 x i16> %2 +} + +define <4 x i32> @test_vmaxvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) { +; CHECK-LABEL: test_vmaxvq_u32_used_by_laneop: +; CHECK: umaxv.4s s[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> %a2) + %1 = insertelement <4 x i32> %a1, i32 %0, i32 3 + ret <4 x i32> %1 +} + declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) nounwind readnone declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>) nounwind readnone declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>) nounwind readnone declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) nounwind readnone +declare i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32>) nounwind readnone +declare i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32>) nounwind readnone diff --git a/test/CodeGen/AArch64/arm64-uminv.ll b/test/CodeGen/AArch64/arm64-uminv.ll index 3bade4b..2181db4 100644 --- a/test/CodeGen/AArch64/arm64-uminv.ll +++ b/test/CodeGen/AArch64/arm64-uminv.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s +; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s define i32 @vmin_u8x8(<8 x i8> %a) nounwind ssp { ; CHECK-LABEL: vmin_u8x8: @@ -86,7 +86,78 @@ return: ret i32 %retval.0 } +define <8 x i8> @test_vminv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) { +; CHECK-LABEL: test_vminv_u8_used_by_laneop: +; CHECK: uminv.8b b[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a2) + %1 = trunc i32 %0 to i8 + %2 = insertelement <8 x i8> %a1, i8 %1, i32 3 + ret <8 x i8> %2 +} + +define <4 x i16> @test_vminv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) { +; CHECK-LABEL: test_vminv_u16_used_by_laneop: +; CHECK: uminv.4h h[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a2) + %1 = trunc i32 %0 to i16 + %2 = insertelement <4 x i16> %a1, i16 %1, i32 3 + ret <4 x i16> %2 +} + +define <2 x i32> @test_vminv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) { +; CHECK-LABEL: test_vminv_u32_used_by_laneop: +; CHECK: uminp.2s v[[REGNUM:[0-9]+]], v1, v1 +; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v2i32(<2 x i32> %a2) + %1 = insertelement <2 x i32> %a1, i32 %0, i32 1 + ret <2 x i32> %1 +} + +define <16 x i8> @test_vminvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) { +; CHECK-LABEL: test_vminvq_u8_used_by_laneop: +; CHECK: uminv.16b b[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %a2) + %1 = trunc i32 %0 to i8 + %2 = insertelement <16 x i8> %a1, i8 %1, i32 3 + ret <16 x i8> %2 +} + +define <8 x i16> @test_vminvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) { +; CHECK-LABEL: test_vminvq_u16_used_by_laneop: +; CHECK: uminv.8h h[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> %a2) + %1 = trunc i32 %0 to i16 + %2 = insertelement <8 x i16> %a1, i16 %1, i32 3 + ret <8 x i16> %2 +} + +define <4 x i32> @test_vminvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) { +; CHECK-LABEL: test_vminvq_u32_used_by_laneop: +; CHECK: uminv.4s s[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32> %a2) + %1 = insertelement <4 x i32> %a1, i32 %0, i32 3 + ret <4 x i32> %1 +} declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>) nounwind readnone declare i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16>) nounwind readnone declare i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16>) nounwind readnone declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>) nounwind readnone +declare i32 @llvm.aarch64.neon.uminv.i32.v2i32(<2 x i32>) nounwind readnone +declare i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32>) nounwind readnone diff --git a/test/CodeGen/AArch64/arm64-unaligned_ldst.ll b/test/CodeGen/AArch64/arm64-unaligned_ldst.ll index 20b80c0..dab8b0f 100644 --- a/test/CodeGen/AArch64/arm64-unaligned_ldst.ll +++ b/test/CodeGen/AArch64/arm64-unaligned_ldst.ll @@ -9,7 +9,7 @@ entry: ; CHECK: str [[X0]], [x0] %tmp1 = bitcast i8* %b to i64* %tmp2 = bitcast i8* %a to i64* - %tmp3 = load i64* %tmp1, align 1 + %tmp3 = load i64, i64* %tmp1, align 1 store i64 %tmp3, i64* %tmp2, align 1 ret void } @@ -22,7 +22,7 @@ entry: ; CHECK: str [[W0]], [x0] %tmp1 = bitcast i8* %b to i32* %tmp2 = bitcast i8* %a to i32* - %tmp3 = load i32* %tmp1, align 1 + %tmp3 = load i32, i32* %tmp1, align 1 store i32 %tmp3, i32* %tmp2, align 1 ret void } @@ -35,7 +35,7 @@ entry: ; CHECK: strh [[W0]], [x0] %tmp1 = bitcast i8* %b to i16* %tmp2 = bitcast i8* %a to i16* - %tmp3 = load i16* %tmp1, align 1 + %tmp3 = load i16, i16* %tmp1, align 1 store i16 %tmp3, i16* %tmp2, align 1 ret void } diff --git a/test/CodeGen/AArch64/arm64-uzp.ll b/test/CodeGen/AArch64/arm64-uzp.ll index cdd8d31..517ebae 100644 --- a/test/CodeGen/AArch64/arm64-uzp.ll +++ b/test/CodeGen/AArch64/arm64-uzp.ll @@ -5,8 +5,8 @@ define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: uzp1.8b ;CHECK: uzp2.8b ;CHECK-NEXT: add.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %tmp5 = add <8 x i8> %tmp3, %tmp4 @@ -18,8 +18,8 @@ define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK: uzp1.4h ;CHECK: uzp2.4h ;CHECK-NEXT: add.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %tmp5 = add <4 x i16> %tmp3, %tmp4 @@ -31,8 +31,8 @@ define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK: uzp1.16b ;CHECK: uzp2.16b ;CHECK-NEXT: add.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> %tmp5 = add <16 x i8> %tmp3, %tmp4 @@ -44,8 +44,8 @@ define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK: uzp1.8h ;CHECK: uzp2.8h ;CHECK-NEXT: add.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> %tmp5 = add <8 x i16> %tmp3, %tmp4 @@ -57,8 +57,8 @@ define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK: uzp1.4s ;CHECK: uzp2.4s ;CHECK-NEXT: add.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %tmp5 = add <4 x i32> %tmp3, %tmp4 @@ -70,8 +70,8 @@ define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK: uzp1.4s ;CHECK: uzp2.4s ;CHECK-NEXT: fadd.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %tmp5 = fadd <4 x float> %tmp3, %tmp4 @@ -85,8 +85,8 @@ define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: uzp1.8b ;CHECK: uzp2.8b ;CHECK-NEXT: add.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15> %tmp5 = add <8 x i8> %tmp3, %tmp4 @@ -98,8 +98,8 @@ define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK: uzp1.8h ;CHECK: uzp2.8h ;CHECK-NEXT: add.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14> %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15> %tmp5 = add <8 x i16> %tmp3, %tmp4 diff --git a/test/CodeGen/AArch64/arm64-vabs.ll b/test/CodeGen/AArch64/arm64-vabs.ll index fae2b90..a52c4eb 100644 --- a/test/CodeGen/AArch64/arm64-vabs.ll +++ b/test/CodeGen/AArch64/arm64-vabs.ll @@ -4,8 +4,8 @@ define <8 x i16> @sabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: sabdl8h: ;CHECK: sabdl.8h - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) %tmp4 = zext <8 x i8> %tmp3 to <8 x i16> ret <8 x i16> %tmp4 @@ -14,8 +14,8 @@ define <8 x i16> @sabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @sabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: sabdl4s: ;CHECK: sabdl.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) %tmp4 = zext <4 x i16> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -24,8 +24,8 @@ define <4 x i32> @sabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @sabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: sabdl2d: ;CHECK: sabdl.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) %tmp4 = zext <2 x i32> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -34,8 +34,8 @@ define <2 x i64> @sabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @sabdl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: sabdl2_8h: ;CHECK: sabdl2.8h - %load1 = load <16 x i8>* %A - %load2 = load <16 x i8>* %B + %load1 = load <16 x i8>, <16 x i8>* %A + %load2 = load <16 x i8>, <16 x i8>* %B %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) @@ -46,8 +46,8 @@ define <8 x i16> @sabdl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @sabdl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sabdl2_4s: ;CHECK: sabdl2.4s - %load1 = load <8 x i16>* %A - %load2 = load <8 x i16>* %B + %load1 = load <8 x i16>, <8 x i16>* %A + %load2 = load <8 x i16>, <8 x i16>* %B %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) @@ -58,8 +58,8 @@ define <4 x i32> @sabdl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @sabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sabdl2_2d: ;CHECK: sabdl2.2d - %load1 = load <4 x i32>* %A - %load2 = load <4 x i32>* %B + %load1 = load <4 x i32>, <4 x i32>* %A + %load2 = load <4 x i32>, <4 x i32>* %B %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) @@ -70,8 +70,8 @@ define <2 x i64> @sabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <8 x i16> @uabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: uabdl8h: ;CHECK: uabdl.8h - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) %tmp4 = zext <8 x i8> %tmp3 to <8 x i16> ret <8 x i16> %tmp4 @@ -80,8 +80,8 @@ define <8 x i16> @uabdl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @uabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: uabdl4s: ;CHECK: uabdl.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) %tmp4 = zext <4 x i16> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -90,8 +90,8 @@ define <4 x i32> @uabdl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @uabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: uabdl2d: ;CHECK: uabdl.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) %tmp4 = zext <2 x i32> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -100,8 +100,8 @@ define <2 x i64> @uabdl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @uabdl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: uabdl2_8h: ;CHECK: uabdl2.8h - %load1 = load <16 x i8>* %A - %load2 = load <16 x i8>* %B + %load1 = load <16 x i8>, <16 x i8>* %A + %load2 = load <16 x i8>, <16 x i8>* %B %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> @@ -113,8 +113,8 @@ define <8 x i16> @uabdl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @uabdl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: uabdl2_4s: ;CHECK: uabdl2.4s - %load1 = load <8 x i16>* %A - %load2 = load <8 x i16>* %B + %load1 = load <8 x i16>, <8 x i16>* %A + %load2 = load <8 x i16>, <8 x i16>* %B %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) @@ -125,8 +125,8 @@ define <4 x i32> @uabdl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @uabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: uabdl2_2d: ;CHECK: uabdl2.2d - %load1 = load <4 x i32>* %A - %load2 = load <4 x i32>* %B + %load1 = load <4 x i32>, <4 x i32>* %A + %load2 = load <4 x i32>, <4 x i32>* %B %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) @@ -137,8 +137,8 @@ define <2 x i64> @uabdl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x float> @fabd_2s(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: fabd_2s: ;CHECK: fabd.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.aarch64.neon.fabd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -146,8 +146,8 @@ define <2 x float> @fabd_2s(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x float> @fabd_4s(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: fabd_4s: ;CHECK: fabd.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.aarch64.neon.fabd.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } @@ -155,8 +155,8 @@ define <4 x float> @fabd_4s(<4 x float>* %A, <4 x float>* %B) nounwind { define <2 x double> @fabd_2d(<2 x double>* %A, <2 x double>* %B) nounwind { ;CHECK-LABEL: fabd_2d: ;CHECK: fabd.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B %tmp3 = call <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double> %tmp1, <2 x double> %tmp2) ret <2 x double> %tmp3 } @@ -168,8 +168,8 @@ declare <2 x double> @llvm.aarch64.neon.fabd.v2f64(<2 x double>, <2 x double>) n define <8 x i8> @sabd_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: sabd_8b: ;CHECK: sabd.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -177,8 +177,8 @@ define <8 x i8> @sabd_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @sabd_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: sabd_16b: ;CHECK: sabd.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -186,8 +186,8 @@ define <16 x i8> @sabd_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @sabd_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: sabd_4h: ;CHECK: sabd.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -195,8 +195,8 @@ define <4 x i16> @sabd_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @sabd_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sabd_8h: ;CHECK: sabd.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -204,8 +204,8 @@ define <8 x i16> @sabd_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @sabd_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: sabd_2s: ;CHECK: sabd.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -213,8 +213,8 @@ define <2 x i32> @sabd_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @sabd_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sabd_4s: ;CHECK: sabd.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -229,8 +229,8 @@ declare <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32>, <4 x i32>) nounwind r define <8 x i8> @uabd_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: uabd_8b: ;CHECK: uabd.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -238,8 +238,8 @@ define <8 x i8> @uabd_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @uabd_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: uabd_16b: ;CHECK: uabd.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -247,8 +247,8 @@ define <16 x i8> @uabd_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @uabd_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: uabd_4h: ;CHECK: uabd.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -256,8 +256,8 @@ define <4 x i16> @uabd_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @uabd_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: uabd_8h: ;CHECK: uabd.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -265,8 +265,8 @@ define <8 x i16> @uabd_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @uabd_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: uabd_2s: ;CHECK: uabd.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -274,8 +274,8 @@ define <2 x i32> @uabd_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @uabd_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: uabd_4s: ;CHECK: uabd.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -290,7 +290,7 @@ declare <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32>, <4 x i32>) nounwind r define <8 x i8> @sqabs_8b(<8 x i8>* %A) nounwind { ;CHECK-LABEL: sqabs_8b: ;CHECK: sqabs.8b - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqabs.v8i8(<8 x i8> %tmp1) ret <8 x i8> %tmp3 } @@ -298,7 +298,7 @@ define <8 x i8> @sqabs_8b(<8 x i8>* %A) nounwind { define <16 x i8> @sqabs_16b(<16 x i8>* %A) nounwind { ;CHECK-LABEL: sqabs_16b: ;CHECK: sqabs.16b - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqabs.v16i8(<16 x i8> %tmp1) ret <16 x i8> %tmp3 } @@ -306,7 +306,7 @@ define <16 x i8> @sqabs_16b(<16 x i8>* %A) nounwind { define <4 x i16> @sqabs_4h(<4 x i16>* %A) nounwind { ;CHECK-LABEL: sqabs_4h: ;CHECK: sqabs.4h - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqabs.v4i16(<4 x i16> %tmp1) ret <4 x i16> %tmp3 } @@ -314,7 +314,7 @@ define <4 x i16> @sqabs_4h(<4 x i16>* %A) nounwind { define <8 x i16> @sqabs_8h(<8 x i16>* %A) nounwind { ;CHECK-LABEL: sqabs_8h: ;CHECK: sqabs.8h - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqabs.v8i16(<8 x i16> %tmp1) ret <8 x i16> %tmp3 } @@ -322,7 +322,7 @@ define <8 x i16> @sqabs_8h(<8 x i16>* %A) nounwind { define <2 x i32> @sqabs_2s(<2 x i32>* %A) nounwind { ;CHECK-LABEL: sqabs_2s: ;CHECK: sqabs.2s - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqabs.v2i32(<2 x i32> %tmp1) ret <2 x i32> %tmp3 } @@ -330,7 +330,7 @@ define <2 x i32> @sqabs_2s(<2 x i32>* %A) nounwind { define <4 x i32> @sqabs_4s(<4 x i32>* %A) nounwind { ;CHECK-LABEL: sqabs_4s: ;CHECK: sqabs.4s - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqabs.v4i32(<4 x i32> %tmp1) ret <4 x i32> %tmp3 } @@ -345,7 +345,7 @@ declare <4 x i32> @llvm.aarch64.neon.sqabs.v4i32(<4 x i32>) nounwind readnone define <8 x i8> @sqneg_8b(<8 x i8>* %A) nounwind { ;CHECK-LABEL: sqneg_8b: ;CHECK: sqneg.8b - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqneg.v8i8(<8 x i8> %tmp1) ret <8 x i8> %tmp3 } @@ -353,7 +353,7 @@ define <8 x i8> @sqneg_8b(<8 x i8>* %A) nounwind { define <16 x i8> @sqneg_16b(<16 x i8>* %A) nounwind { ;CHECK-LABEL: sqneg_16b: ;CHECK: sqneg.16b - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqneg.v16i8(<16 x i8> %tmp1) ret <16 x i8> %tmp3 } @@ -361,7 +361,7 @@ define <16 x i8> @sqneg_16b(<16 x i8>* %A) nounwind { define <4 x i16> @sqneg_4h(<4 x i16>* %A) nounwind { ;CHECK-LABEL: sqneg_4h: ;CHECK: sqneg.4h - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqneg.v4i16(<4 x i16> %tmp1) ret <4 x i16> %tmp3 } @@ -369,7 +369,7 @@ define <4 x i16> @sqneg_4h(<4 x i16>* %A) nounwind { define <8 x i16> @sqneg_8h(<8 x i16>* %A) nounwind { ;CHECK-LABEL: sqneg_8h: ;CHECK: sqneg.8h - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqneg.v8i16(<8 x i16> %tmp1) ret <8 x i16> %tmp3 } @@ -377,7 +377,7 @@ define <8 x i16> @sqneg_8h(<8 x i16>* %A) nounwind { define <2 x i32> @sqneg_2s(<2 x i32>* %A) nounwind { ;CHECK-LABEL: sqneg_2s: ;CHECK: sqneg.2s - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqneg.v2i32(<2 x i32> %tmp1) ret <2 x i32> %tmp3 } @@ -385,7 +385,7 @@ define <2 x i32> @sqneg_2s(<2 x i32>* %A) nounwind { define <4 x i32> @sqneg_4s(<4 x i32>* %A) nounwind { ;CHECK-LABEL: sqneg_4s: ;CHECK: sqneg.4s - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqneg.v4i32(<4 x i32> %tmp1) ret <4 x i32> %tmp3 } @@ -400,7 +400,7 @@ declare <4 x i32> @llvm.aarch64.neon.sqneg.v4i32(<4 x i32>) nounwind readnone define <8 x i8> @abs_8b(<8 x i8>* %A) nounwind { ;CHECK-LABEL: abs_8b: ;CHECK: abs.8b - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.abs.v8i8(<8 x i8> %tmp1) ret <8 x i8> %tmp3 } @@ -408,7 +408,7 @@ define <8 x i8> @abs_8b(<8 x i8>* %A) nounwind { define <16 x i8> @abs_16b(<16 x i8>* %A) nounwind { ;CHECK-LABEL: abs_16b: ;CHECK: abs.16b - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = call <16 x i8> @llvm.aarch64.neon.abs.v16i8(<16 x i8> %tmp1) ret <16 x i8> %tmp3 } @@ -416,7 +416,7 @@ define <16 x i8> @abs_16b(<16 x i8>* %A) nounwind { define <4 x i16> @abs_4h(<4 x i16>* %A) nounwind { ;CHECK-LABEL: abs_4h: ;CHECK: abs.4h - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.abs.v4i16(<4 x i16> %tmp1) ret <4 x i16> %tmp3 } @@ -424,7 +424,7 @@ define <4 x i16> @abs_4h(<4 x i16>* %A) nounwind { define <8 x i16> @abs_8h(<8 x i16>* %A) nounwind { ;CHECK-LABEL: abs_8h: ;CHECK: abs.8h - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i16> @llvm.aarch64.neon.abs.v8i16(<8 x i16> %tmp1) ret <8 x i16> %tmp3 } @@ -432,7 +432,7 @@ define <8 x i16> @abs_8h(<8 x i16>* %A) nounwind { define <2 x i32> @abs_2s(<2 x i32>* %A) nounwind { ;CHECK-LABEL: abs_2s: ;CHECK: abs.2s - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.abs.v2i32(<2 x i32> %tmp1) ret <2 x i32> %tmp3 } @@ -440,7 +440,7 @@ define <2 x i32> @abs_2s(<2 x i32>* %A) nounwind { define <4 x i32> @abs_4s(<4 x i32>* %A) nounwind { ;CHECK-LABEL: abs_4s: ;CHECK: abs.4s - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i32> @llvm.aarch64.neon.abs.v4i32(<4 x i32> %tmp1) ret <4 x i32> %tmp3 } @@ -471,9 +471,9 @@ declare i64 @llvm.aarch64.neon.abs.i64(i64) nounwind readnone define <8 x i16> @sabal8h(<8 x i8>* %A, <8 x i8>* %B, <8 x i16>* %C) nounwind { ;CHECK-LABEL: sabal8h: ;CHECK: sabal.8h - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i16>* %C + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i16>, <8 x i16>* %C %tmp4 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16> %tmp5 = add <8 x i16> %tmp3, %tmp4.1 @@ -483,9 +483,9 @@ define <8 x i16> @sabal8h(<8 x i8>* %A, <8 x i8>* %B, <8 x i16>* %C) nounwind { define <4 x i32> @sabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: sabal4s: ;CHECK: sabal.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32> %tmp5 = add <4 x i32> %tmp3, %tmp4.1 @@ -495,9 +495,9 @@ define <4 x i32> @sabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind define <2 x i64> @sabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: sabal2d: ;CHECK: sabal.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i64>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp4 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64> %tmp4.1.1 = zext <2 x i32> %tmp4 to <2 x i64> @@ -508,9 +508,9 @@ define <2 x i64> @sabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind define <8 x i16> @sabal2_8h(<16 x i8>* %A, <16 x i8>* %B, <8 x i16>* %C) nounwind { ;CHECK-LABEL: sabal2_8h: ;CHECK: sabal2.8h - %load1 = load <16 x i8>* %A - %load2 = load <16 x i8>* %B - %tmp3 = load <8 x i16>* %C + %load1 = load <16 x i8>, <16 x i8>* %A + %load2 = load <16 x i8>, <16 x i8>* %B + %tmp3 = load <8 x i16>, <8 x i16>* %C %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %tmp4 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) @@ -522,9 +522,9 @@ define <8 x i16> @sabal2_8h(<16 x i8>* %A, <16 x i8>* %B, <8 x i16>* %C) nounwin define <4 x i32> @sabal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: sabal2_4s: ;CHECK: sabal2.4s - %load1 = load <8 x i16>* %A - %load2 = load <8 x i16>* %B - %tmp3 = load <4 x i32>* %C + %load1 = load <8 x i16>, <8 x i16>* %A + %load2 = load <8 x i16>, <8 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp4 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) @@ -536,9 +536,9 @@ define <4 x i32> @sabal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwin define <2 x i64> @sabal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: sabal2_2d: ;CHECK: sabal2.2d - %load1 = load <4 x i32>* %A - %load2 = load <4 x i32>* %B - %tmp3 = load <2 x i64>* %C + %load1 = load <4 x i32>, <4 x i32>* %A + %load2 = load <4 x i32>, <4 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp4 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) @@ -550,9 +550,9 @@ define <2 x i64> @sabal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwin define <8 x i16> @uabal8h(<8 x i8>* %A, <8 x i8>* %B, <8 x i16>* %C) nounwind { ;CHECK-LABEL: uabal8h: ;CHECK: uabal.8h - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B - %tmp3 = load <8 x i16>* %C + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B + %tmp3 = load <8 x i16>, <8 x i16>* %C %tmp4 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) %tmp4.1 = zext <8 x i8> %tmp4 to <8 x i16> %tmp5 = add <8 x i16> %tmp3, %tmp4.1 @@ -562,9 +562,9 @@ define <8 x i16> @uabal8h(<8 x i8>* %A, <8 x i8>* %B, <8 x i16>* %C) nounwind { define <4 x i32> @uabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: uabal4s: ;CHECK: uabal.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) %tmp4.1 = zext <4 x i16> %tmp4 to <4 x i32> %tmp5 = add <4 x i32> %tmp3, %tmp4.1 @@ -574,9 +574,9 @@ define <4 x i32> @uabal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind define <2 x i64> @uabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: uabal2d: ;CHECK: uabal.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i64>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp4 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) %tmp4.1 = zext <2 x i32> %tmp4 to <2 x i64> %tmp5 = add <2 x i64> %tmp3, %tmp4.1 @@ -586,9 +586,9 @@ define <2 x i64> @uabal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind define <8 x i16> @uabal2_8h(<16 x i8>* %A, <16 x i8>* %B, <8 x i16>* %C) nounwind { ;CHECK-LABEL: uabal2_8h: ;CHECK: uabal2.8h - %load1 = load <16 x i8>* %A - %load2 = load <16 x i8>* %B - %tmp3 = load <8 x i16>* %C + %load1 = load <16 x i8>, <16 x i8>* %A + %load2 = load <16 x i8>, <16 x i8>* %B + %tmp3 = load <8 x i16>, <8 x i16>* %C %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %tmp4 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) @@ -600,9 +600,9 @@ define <8 x i16> @uabal2_8h(<16 x i8>* %A, <16 x i8>* %B, <8 x i16>* %C) nounwin define <4 x i32> @uabal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: uabal2_4s: ;CHECK: uabal2.4s - %load1 = load <8 x i16>* %A - %load2 = load <8 x i16>* %B - %tmp3 = load <4 x i32>* %C + %load1 = load <8 x i16>, <8 x i16>* %A + %load2 = load <8 x i16>, <8 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp4 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) @@ -614,9 +614,9 @@ define <4 x i32> @uabal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwin define <2 x i64> @uabal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: uabal2_2d: ;CHECK: uabal2.2d - %load1 = load <4 x i32>* %A - %load2 = load <4 x i32>* %B - %tmp3 = load <2 x i64>* %C + %load1 = load <4 x i32>, <4 x i32>* %A + %load2 = load <4 x i32>, <4 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp4 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) @@ -628,10 +628,10 @@ define <2 x i64> @uabal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwin define <8 x i8> @saba_8b(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ;CHECK-LABEL: saba_8b: ;CHECK: saba.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) - %tmp4 = load <8 x i8>* %C + %tmp4 = load <8 x i8>, <8 x i8>* %C %tmp5 = add <8 x i8> %tmp3, %tmp4 ret <8 x i8> %tmp5 } @@ -639,10 +639,10 @@ define <8 x i8> @saba_8b(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { define <16 x i8> @saba_16b(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind { ;CHECK-LABEL: saba_16b: ;CHECK: saba.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) - %tmp4 = load <16 x i8>* %C + %tmp4 = load <16 x i8>, <16 x i8>* %C %tmp5 = add <16 x i8> %tmp3, %tmp4 ret <16 x i8> %tmp5 } @@ -650,10 +650,10 @@ define <16 x i8> @saba_16b(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind define <4 x i16> @saba_4h(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ;CHECK-LABEL: saba_4h: ;CHECK: saba.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) - %tmp4 = load <4 x i16>* %C + %tmp4 = load <4 x i16>, <4 x i16>* %C %tmp5 = add <4 x i16> %tmp3, %tmp4 ret <4 x i16> %tmp5 } @@ -661,10 +661,10 @@ define <4 x i16> @saba_4h(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind define <8 x i16> @saba_8h(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { ;CHECK-LABEL: saba_8h: ;CHECK: saba.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) - %tmp4 = load <8 x i16>* %C + %tmp4 = load <8 x i16>, <8 x i16>* %C %tmp5 = add <8 x i16> %tmp3, %tmp4 ret <8 x i16> %tmp5 } @@ -672,10 +672,10 @@ define <8 x i16> @saba_8h(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind define <2 x i32> @saba_2s(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ;CHECK-LABEL: saba_2s: ;CHECK: saba.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) - %tmp4 = load <2 x i32>* %C + %tmp4 = load <2 x i32>, <2 x i32>* %C %tmp5 = add <2 x i32> %tmp3, %tmp4 ret <2 x i32> %tmp5 } @@ -683,10 +683,10 @@ define <2 x i32> @saba_2s(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind define <4 x i32> @saba_4s(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: saba_4s: ;CHECK: saba.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) - %tmp4 = load <4 x i32>* %C + %tmp4 = load <4 x i32>, <4 x i32>* %C %tmp5 = add <4 x i32> %tmp3, %tmp4 ret <4 x i32> %tmp5 } @@ -694,10 +694,10 @@ define <4 x i32> @saba_4s(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind define <8 x i8> @uaba_8b(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ;CHECK-LABEL: uaba_8b: ;CHECK: uaba.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) - %tmp4 = load <8 x i8>* %C + %tmp4 = load <8 x i8>, <8 x i8>* %C %tmp5 = add <8 x i8> %tmp3, %tmp4 ret <8 x i8> %tmp5 } @@ -705,10 +705,10 @@ define <8 x i8> @uaba_8b(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { define <16 x i8> @uaba_16b(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind { ;CHECK-LABEL: uaba_16b: ;CHECK: uaba.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) - %tmp4 = load <16 x i8>* %C + %tmp4 = load <16 x i8>, <16 x i8>* %C %tmp5 = add <16 x i8> %tmp3, %tmp4 ret <16 x i8> %tmp5 } @@ -716,10 +716,10 @@ define <16 x i8> @uaba_16b(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind define <4 x i16> @uaba_4h(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ;CHECK-LABEL: uaba_4h: ;CHECK: uaba.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) - %tmp4 = load <4 x i16>* %C + %tmp4 = load <4 x i16>, <4 x i16>* %C %tmp5 = add <4 x i16> %tmp3, %tmp4 ret <4 x i16> %tmp5 } @@ -727,10 +727,10 @@ define <4 x i16> @uaba_4h(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind define <8 x i16> @uaba_8h(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { ;CHECK-LABEL: uaba_8h: ;CHECK: uaba.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) - %tmp4 = load <8 x i16>* %C + %tmp4 = load <8 x i16>, <8 x i16>* %C %tmp5 = add <8 x i16> %tmp3, %tmp4 ret <8 x i16> %tmp5 } @@ -738,10 +738,10 @@ define <8 x i16> @uaba_8h(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind define <2 x i32> @uaba_2s(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ;CHECK-LABEL: uaba_2s: ;CHECK: uaba.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) - %tmp4 = load <2 x i32>* %C + %tmp4 = load <2 x i32>, <2 x i32>* %C %tmp5 = add <2 x i32> %tmp3, %tmp4 ret <2 x i32> %tmp5 } @@ -749,10 +749,10 @@ define <2 x i32> @uaba_2s(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind define <4 x i32> @uaba_4s(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: uaba_4s: ;CHECK: uaba.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) - %tmp4 = load <4 x i32>* %C + %tmp4 = load <4 x i32>, <4 x i32>* %C %tmp5 = add <4 x i32> %tmp3, %tmp4 ret <4 x i32> %tmp5 } diff --git a/test/CodeGen/AArch64/arm64-vadd.ll b/test/CodeGen/AArch64/arm64-vadd.ll index 9ed8aa6..e3d8dd2 100644 --- a/test/CodeGen/AArch64/arm64-vadd.ll +++ b/test/CodeGen/AArch64/arm64-vadd.ll @@ -3,8 +3,8 @@ define <8 x i8> @addhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: addhn8b: ;CHECK: addhn.8b - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @addhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i16> @addhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: addhn4h: ;CHECK: addhn.4h - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @addhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i32> @addhn2s(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: addhn2s: ;CHECK: addhn.2s - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.addhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i32> %tmp3 } @@ -65,8 +65,8 @@ declare <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16>, <8 x i16>) nounwind re define <8 x i8> @raddhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: raddhn8b: ;CHECK: raddhn.8b - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i8> %tmp3 } @@ -74,8 +74,8 @@ define <8 x i8> @raddhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i16> @raddhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: raddhn4h: ;CHECK: raddhn.4h - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i16> %tmp3 } @@ -83,8 +83,8 @@ define <4 x i16> @raddhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i32> @raddhn2s(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: raddhn2s: ;CHECK: raddhn.2s - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i32> %tmp3 } @@ -126,8 +126,8 @@ declare <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16>, <8 x i16>) nounwind r define <8 x i16> @saddl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: saddl8h: ;CHECK: saddl.8h - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = sext <8 x i8> %tmp1 to <8 x i16> %tmp4 = sext <8 x i8> %tmp2 to <8 x i16> %tmp5 = add <8 x i16> %tmp3, %tmp4 @@ -137,8 +137,8 @@ define <8 x i16> @saddl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @saddl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: saddl4s: ;CHECK: saddl.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = sext <4 x i16> %tmp1 to <4 x i32> %tmp4 = sext <4 x i16> %tmp2 to <4 x i32> %tmp5 = add <4 x i32> %tmp3, %tmp4 @@ -148,8 +148,8 @@ define <4 x i32> @saddl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @saddl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: saddl2d: ;CHECK: saddl.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = sext <2 x i32> %tmp1 to <2 x i64> %tmp4 = sext <2 x i32> %tmp2 to <2 x i64> %tmp5 = add <2 x i64> %tmp3, %tmp4 @@ -207,8 +207,8 @@ define <2 x i64> @saddl2_2d(<4 x i32> %a, <4 x i32> %b) nounwind { define <8 x i16> @uaddl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: uaddl8h: ;CHECK: uaddl.8h - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = zext <8 x i8> %tmp1 to <8 x i16> %tmp4 = zext <8 x i8> %tmp2 to <8 x i16> %tmp5 = add <8 x i16> %tmp3, %tmp4 @@ -218,8 +218,8 @@ define <8 x i16> @uaddl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @uaddl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: uaddl4s: ;CHECK: uaddl.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = zext <4 x i16> %tmp1 to <4 x i32> %tmp4 = zext <4 x i16> %tmp2 to <4 x i32> %tmp5 = add <4 x i32> %tmp3, %tmp4 @@ -229,8 +229,8 @@ define <4 x i32> @uaddl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @uaddl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: uaddl2d: ;CHECK: uaddl.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = zext <2 x i32> %tmp1 to <2 x i64> %tmp4 = zext <2 x i32> %tmp2 to <2 x i64> %tmp5 = add <2 x i64> %tmp3, %tmp4 @@ -289,8 +289,8 @@ define <2 x i64> @uaddl2_2d(<4 x i32> %a, <4 x i32> %b) nounwind { define <8 x i16> @uaddw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: uaddw8h: ;CHECK: uaddw.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = zext <8 x i8> %tmp2 to <8 x i16> %tmp4 = add <8 x i16> %tmp1, %tmp3 ret <8 x i16> %tmp4 @@ -299,8 +299,8 @@ define <8 x i16> @uaddw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @uaddw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: uaddw4s: ;CHECK: uaddw.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = zext <4 x i16> %tmp2 to <4 x i32> %tmp4 = add <4 x i32> %tmp1, %tmp3 ret <4 x i32> %tmp4 @@ -309,8 +309,8 @@ define <4 x i32> @uaddw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @uaddw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: uaddw2d: ;CHECK: uaddw.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = zext <2 x i32> %tmp2 to <2 x i64> %tmp4 = add <2 x i64> %tmp1, %tmp3 ret <2 x i64> %tmp4 @@ -319,9 +319,9 @@ define <2 x i64> @uaddw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @uaddw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: uaddw2_8h: ;CHECK: uaddw2.8h - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A - %tmp2 = load <16 x i8>* %B + %tmp2 = load <16 x i8>, <16 x i8>* %B %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %ext2 = zext <8 x i8> %high2 to <8 x i16> @@ -332,9 +332,9 @@ define <8 x i16> @uaddw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @uaddw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: uaddw2_4s: ;CHECK: uaddw2.4s - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A - %tmp2 = load <8 x i16>* %B + %tmp2 = load <8 x i16>, <8 x i16>* %B %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %ext2 = zext <4 x i16> %high2 to <4 x i32> @@ -345,9 +345,9 @@ define <4 x i32> @uaddw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @uaddw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: uaddw2_2d: ;CHECK: uaddw2.2d - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A - %tmp2 = load <4 x i32>* %B + %tmp2 = load <4 x i32>, <4 x i32>* %B %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %ext2 = zext <2 x i32> %high2 to <2 x i64> @@ -358,8 +358,8 @@ define <2 x i64> @uaddw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind { define <8 x i16> @saddw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: saddw8h: ;CHECK: saddw.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = sext <8 x i8> %tmp2 to <8 x i16> %tmp4 = add <8 x i16> %tmp1, %tmp3 ret <8 x i16> %tmp4 @@ -368,8 +368,8 @@ define <8 x i16> @saddw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @saddw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: saddw4s: ;CHECK: saddw.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = sext <4 x i16> %tmp2 to <4 x i32> %tmp4 = add <4 x i32> %tmp1, %tmp3 ret <4 x i32> %tmp4 @@ -378,8 +378,8 @@ define <4 x i32> @saddw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @saddw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: saddw2d: ;CHECK: saddw.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = sext <2 x i32> %tmp2 to <2 x i64> %tmp4 = add <2 x i64> %tmp1, %tmp3 ret <2 x i64> %tmp4 @@ -388,9 +388,9 @@ define <2 x i64> @saddw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @saddw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: saddw2_8h: ;CHECK: saddw2.8h - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A - %tmp2 = load <16 x i8>* %B + %tmp2 = load <16 x i8>, <16 x i8>* %B %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %ext2 = sext <8 x i8> %high2 to <8 x i16> @@ -401,9 +401,9 @@ define <8 x i16> @saddw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @saddw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: saddw2_4s: ;CHECK: saddw2.4s - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A - %tmp2 = load <8 x i16>* %B + %tmp2 = load <8 x i16>, <8 x i16>* %B %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %ext2 = sext <4 x i16> %high2 to <4 x i32> @@ -414,9 +414,9 @@ define <4 x i32> @saddw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @saddw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: saddw2_2d: ;CHECK: saddw2.2d - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A - %tmp2 = load <4 x i32>* %B + %tmp2 = load <4 x i32>, <4 x i32>* %B %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %ext2 = sext <2 x i32> %high2 to <2 x i64> @@ -427,7 +427,7 @@ define <2 x i64> @saddw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind { define <4 x i16> @saddlp4h(<8 x i8>* %A) nounwind { ;CHECK-LABEL: saddlp4h: ;CHECK: saddlp.4h - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> %tmp1) ret <4 x i16> %tmp3 } @@ -435,7 +435,7 @@ define <4 x i16> @saddlp4h(<8 x i8>* %A) nounwind { define <2 x i32> @saddlp2s(<4 x i16>* %A) nounwind { ;CHECK-LABEL: saddlp2s: ;CHECK: saddlp.2s - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> %tmp1) ret <2 x i32> %tmp3 } @@ -443,7 +443,7 @@ define <2 x i32> @saddlp2s(<4 x i16>* %A) nounwind { define <1 x i64> @saddlp1d(<2 x i32>* %A) nounwind { ;CHECK-LABEL: saddlp1d: ;CHECK: saddlp.1d - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp3 = call <1 x i64> @llvm.aarch64.neon.saddlp.v1i64.v2i32(<2 x i32> %tmp1) ret <1 x i64> %tmp3 } @@ -451,7 +451,7 @@ define <1 x i64> @saddlp1d(<2 x i32>* %A) nounwind { define <8 x i16> @saddlp8h(<16 x i8>* %A) nounwind { ;CHECK-LABEL: saddlp8h: ;CHECK: saddlp.8h - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> %tmp1) ret <8 x i16> %tmp3 } @@ -459,7 +459,7 @@ define <8 x i16> @saddlp8h(<16 x i8>* %A) nounwind { define <4 x i32> @saddlp4s(<8 x i16>* %A) nounwind { ;CHECK-LABEL: saddlp4s: ;CHECK: saddlp.4s - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> %tmp1) ret <4 x i32> %tmp3 } @@ -467,7 +467,7 @@ define <4 x i32> @saddlp4s(<8 x i16>* %A) nounwind { define <2 x i64> @saddlp2d(<4 x i32>* %A) nounwind { ;CHECK-LABEL: saddlp2d: ;CHECK: saddlp.2d - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32> %tmp1) ret <2 x i64> %tmp3 } @@ -483,7 +483,7 @@ declare <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32>) nounwind read define <4 x i16> @uaddlp4h(<8 x i8>* %A) nounwind { ;CHECK-LABEL: uaddlp4h: ;CHECK: uaddlp.4h - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %tmp1) ret <4 x i16> %tmp3 } @@ -491,7 +491,7 @@ define <4 x i16> @uaddlp4h(<8 x i8>* %A) nounwind { define <2 x i32> @uaddlp2s(<4 x i16>* %A) nounwind { ;CHECK-LABEL: uaddlp2s: ;CHECK: uaddlp.2s - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> %tmp1) ret <2 x i32> %tmp3 } @@ -499,7 +499,7 @@ define <2 x i32> @uaddlp2s(<4 x i16>* %A) nounwind { define <1 x i64> @uaddlp1d(<2 x i32>* %A) nounwind { ;CHECK-LABEL: uaddlp1d: ;CHECK: uaddlp.1d - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp3 = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %tmp1) ret <1 x i64> %tmp3 } @@ -507,7 +507,7 @@ define <1 x i64> @uaddlp1d(<2 x i32>* %A) nounwind { define <8 x i16> @uaddlp8h(<16 x i8>* %A) nounwind { ;CHECK-LABEL: uaddlp8h: ;CHECK: uaddlp.8h - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %tmp1) ret <8 x i16> %tmp3 } @@ -515,7 +515,7 @@ define <8 x i16> @uaddlp8h(<16 x i8>* %A) nounwind { define <4 x i32> @uaddlp4s(<8 x i16>* %A) nounwind { ;CHECK-LABEL: uaddlp4s: ;CHECK: uaddlp.4s - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> %tmp1) ret <4 x i32> %tmp3 } @@ -523,7 +523,7 @@ define <4 x i32> @uaddlp4s(<8 x i16>* %A) nounwind { define <2 x i64> @uaddlp2d(<4 x i32>* %A) nounwind { ;CHECK-LABEL: uaddlp2d: ;CHECK: uaddlp.2d - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> %tmp1) ret <2 x i64> %tmp3 } @@ -539,9 +539,9 @@ declare <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32>) nounwind read define <4 x i16> @sadalp4h(<8 x i8>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: sadalp4h: ;CHECK: sadalp.4h - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> %tmp1) - %tmp4 = load <4 x i16>* %B + %tmp4 = load <4 x i16>, <4 x i16>* %B %tmp5 = add <4 x i16> %tmp3, %tmp4 ret <4 x i16> %tmp5 } @@ -549,9 +549,9 @@ define <4 x i16> @sadalp4h(<8 x i8>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @sadalp2s(<4 x i16>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: sadalp2s: ;CHECK: sadalp.2s - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> %tmp1) - %tmp4 = load <2 x i32>* %B + %tmp4 = load <2 x i32>, <2 x i32>* %B %tmp5 = add <2 x i32> %tmp3, %tmp4 ret <2 x i32> %tmp5 } @@ -559,9 +559,9 @@ define <2 x i32> @sadalp2s(<4 x i16>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @sadalp8h(<16 x i8>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sadalp8h: ;CHECK: sadalp.8h - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> %tmp1) - %tmp4 = load <8 x i16>* %B + %tmp4 = load <8 x i16>, <8 x i16>* %B %tmp5 = add <8 x i16> %tmp3, %tmp4 ret <8 x i16> %tmp5 } @@ -569,9 +569,9 @@ define <8 x i16> @sadalp8h(<16 x i8>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @sadalp4s(<8 x i16>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sadalp4s: ;CHECK: sadalp.4s - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> %tmp1) - %tmp4 = load <4 x i32>* %B + %tmp4 = load <4 x i32>, <4 x i32>* %B %tmp5 = add <4 x i32> %tmp3, %tmp4 ret <4 x i32> %tmp5 } @@ -579,9 +579,9 @@ define <4 x i32> @sadalp4s(<8 x i16>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @sadalp2d(<4 x i32>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: sadalp2d: ;CHECK: sadalp.2d - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32> %tmp1) - %tmp4 = load <2 x i64>* %B + %tmp4 = load <2 x i64>, <2 x i64>* %B %tmp5 = add <2 x i64> %tmp3, %tmp4 ret <2 x i64> %tmp5 } @@ -589,9 +589,9 @@ define <2 x i64> @sadalp2d(<4 x i32>* %A, <2 x i64>* %B) nounwind { define <4 x i16> @uadalp4h(<8 x i8>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: uadalp4h: ;CHECK: uadalp.4h - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %tmp1) - %tmp4 = load <4 x i16>* %B + %tmp4 = load <4 x i16>, <4 x i16>* %B %tmp5 = add <4 x i16> %tmp3, %tmp4 ret <4 x i16> %tmp5 } @@ -599,9 +599,9 @@ define <4 x i16> @uadalp4h(<8 x i8>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @uadalp2s(<4 x i16>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: uadalp2s: ;CHECK: uadalp.2s - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> %tmp1) - %tmp4 = load <2 x i32>* %B + %tmp4 = load <2 x i32>, <2 x i32>* %B %tmp5 = add <2 x i32> %tmp3, %tmp4 ret <2 x i32> %tmp5 } @@ -609,9 +609,9 @@ define <2 x i32> @uadalp2s(<4 x i16>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @uadalp8h(<16 x i8>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: uadalp8h: ;CHECK: uadalp.8h - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %tmp1) - %tmp4 = load <8 x i16>* %B + %tmp4 = load <8 x i16>, <8 x i16>* %B %tmp5 = add <8 x i16> %tmp3, %tmp4 ret <8 x i16> %tmp5 } @@ -619,9 +619,9 @@ define <8 x i16> @uadalp8h(<16 x i8>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @uadalp4s(<8 x i16>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: uadalp4s: ;CHECK: uadalp.4s - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> %tmp1) - %tmp4 = load <4 x i32>* %B + %tmp4 = load <4 x i32>, <4 x i32>* %B %tmp5 = add <4 x i32> %tmp3, %tmp4 ret <4 x i32> %tmp5 } @@ -629,9 +629,9 @@ define <4 x i32> @uadalp4s(<8 x i16>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @uadalp2d(<4 x i32>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: uadalp2d: ;CHECK: uadalp.2d - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> %tmp1) - %tmp4 = load <2 x i64>* %B + %tmp4 = load <2 x i64>, <2 x i64>* %B %tmp5 = add <2 x i64> %tmp3, %tmp4 ret <2 x i64> %tmp5 } @@ -639,8 +639,8 @@ define <2 x i64> @uadalp2d(<4 x i32>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @addp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: addp_8b: ;CHECK: addp.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.addp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -648,8 +648,8 @@ define <8 x i8> @addp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @addp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: addp_16b: ;CHECK: addp.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.addp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -657,8 +657,8 @@ define <16 x i8> @addp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @addp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: addp_4h: ;CHECK: addp.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -666,8 +666,8 @@ define <4 x i16> @addp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @addp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: addp_8h: ;CHECK: addp.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.addp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -675,8 +675,8 @@ define <8 x i16> @addp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @addp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: addp_2s: ;CHECK: addp.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.addp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -684,8 +684,8 @@ define <2 x i32> @addp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @addp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: addp_4s: ;CHECK: addp.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.addp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -693,8 +693,8 @@ define <4 x i32> @addp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @addp_2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: addp_2d: ;CHECK: addp.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -710,8 +710,8 @@ declare <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64>, <2 x i64>) nounwind r define <2 x float> @faddp_2s(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: faddp_2s: ;CHECK: faddp.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.aarch64.neon.addp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -719,8 +719,8 @@ define <2 x float> @faddp_2s(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x float> @faddp_4s(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: faddp_4s: ;CHECK: faddp.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.aarch64.neon.addp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } @@ -728,8 +728,8 @@ define <4 x float> @faddp_4s(<4 x float>* %A, <4 x float>* %B) nounwind { define <2 x double> @faddp_2d(<2 x double>* %A, <2 x double>* %B) nounwind { ;CHECK-LABEL: faddp_2d: ;CHECK: faddp.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B %tmp3 = call <2 x double> @llvm.aarch64.neon.addp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2) ret <2 x double> %tmp3 } @@ -805,8 +805,8 @@ define <2 x i64> @ssubl2_duplhs(i32 %lhs, <4 x i32> %rhs) { define <8 x i8> @addhn8b_natural(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: addhn8b_natural: ;CHECK: addhn.8b - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %sum = add <8 x i16> %tmp1, %tmp2 %high_bits = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> %narrowed = trunc <8 x i16> %high_bits to <8 x i8> @@ -816,8 +816,8 @@ define <8 x i8> @addhn8b_natural(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i16> @addhn4h_natural(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: addhn4h_natural: ;CHECK: addhn.4h - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %sum = add <4 x i32> %tmp1, %tmp2 %high_bits = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16> %narrowed = trunc <4 x i32> %high_bits to <4 x i16> @@ -827,8 +827,8 @@ define <4 x i16> @addhn4h_natural(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i32> @addhn2s_natural(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: addhn2s_natural: ;CHECK: addhn.2s - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %sum = add <2 x i64> %tmp1, %tmp2 %high_bits = lshr <2 x i64> %sum, <i64 32, i64 32> %narrowed = trunc <2 x i64> %high_bits to <2 x i32> @@ -838,8 +838,8 @@ define <2 x i32> @addhn2s_natural(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <16 x i8> @addhn2_16b_natural(<8 x i8> %low, <8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: addhn2_16b_natural: ;CHECK: addhn2.16b - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %sum = add <8 x i16> %tmp1, %tmp2 %high_bits = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> %narrowed = trunc <8 x i16> %high_bits to <8 x i8> @@ -850,8 +850,8 @@ define <16 x i8> @addhn2_16b_natural(<8 x i8> %low, <8 x i16>* %A, <8 x i16>* %B define <8 x i16> @addhn2_8h_natural(<4 x i16> %low, <4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: addhn2_8h_natural: ;CHECK: addhn2.8h - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %sum = add <4 x i32> %tmp1, %tmp2 %high_bits = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16> %narrowed = trunc <4 x i32> %high_bits to <4 x i16> @@ -862,8 +862,8 @@ define <8 x i16> @addhn2_8h_natural(<4 x i16> %low, <4 x i32>* %A, <4 x i32>* %B define <4 x i32> @addhn2_4s_natural(<2 x i32> %low, <2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: addhn2_4s_natural: ;CHECK: addhn2.4s - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %sum = add <2 x i64> %tmp1, %tmp2 %high_bits = lshr <2 x i64> %sum, <i64 32, i64 32> %narrowed = trunc <2 x i64> %high_bits to <2 x i32> @@ -874,8 +874,8 @@ define <4 x i32> @addhn2_4s_natural(<2 x i32> %low, <2 x i64>* %A, <2 x i64>* %B define <8 x i8> @subhn8b_natural(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: subhn8b_natural: ;CHECK: subhn.8b - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %diff = sub <8 x i16> %tmp1, %tmp2 %high_bits = lshr <8 x i16> %diff, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> %narrowed = trunc <8 x i16> %high_bits to <8 x i8> @@ -885,8 +885,8 @@ define <8 x i8> @subhn8b_natural(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i16> @subhn4h_natural(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: subhn4h_natural: ;CHECK: subhn.4h - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %diff = sub <4 x i32> %tmp1, %tmp2 %high_bits = lshr <4 x i32> %diff, <i32 16, i32 16, i32 16, i32 16> %narrowed = trunc <4 x i32> %high_bits to <4 x i16> @@ -896,8 +896,8 @@ define <4 x i16> @subhn4h_natural(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i32> @subhn2s_natural(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: subhn2s_natural: ;CHECK: subhn.2s - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %diff = sub <2 x i64> %tmp1, %tmp2 %high_bits = lshr <2 x i64> %diff, <i64 32, i64 32> %narrowed = trunc <2 x i64> %high_bits to <2 x i32> @@ -907,8 +907,8 @@ define <2 x i32> @subhn2s_natural(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <16 x i8> @subhn2_16b_natural(<8 x i8> %low, <8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: subhn2_16b_natural: ;CHECK: subhn2.16b - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %diff = sub <8 x i16> %tmp1, %tmp2 %high_bits = lshr <8 x i16> %diff, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> %narrowed = trunc <8 x i16> %high_bits to <8 x i8> @@ -919,8 +919,8 @@ define <16 x i8> @subhn2_16b_natural(<8 x i8> %low, <8 x i16>* %A, <8 x i16>* %B define <8 x i16> @subhn2_8h_natural(<4 x i16> %low, <4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: subhn2_8h_natural: ;CHECK: subhn2.8h - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %diff = sub <4 x i32> %tmp1, %tmp2 %high_bits = lshr <4 x i32> %diff, <i32 16, i32 16, i32 16, i32 16> %narrowed = trunc <4 x i32> %high_bits to <4 x i16> @@ -931,8 +931,8 @@ define <8 x i16> @subhn2_8h_natural(<4 x i16> %low, <4 x i32>* %A, <4 x i32>* %B define <4 x i32> @subhn2_4s_natural(<2 x i32> %low, <2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: subhn2_4s_natural: ;CHECK: subhn2.4s - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %diff = sub <2 x i64> %tmp1, %tmp2 %high_bits = lshr <2 x i64> %diff, <i64 32, i64 32> %narrowed = trunc <2 x i64> %high_bits to <2 x i32> diff --git a/test/CodeGen/AArch64/arm64-vaddv.ll b/test/CodeGen/AArch64/arm64-vaddv.ll index 2d92ce6..589319b 100644 --- a/test/CodeGen/AArch64/arm64-vaddv.ll +++ b/test/CodeGen/AArch64/arm64-vaddv.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s -mcpu=cyclone | FileCheck %s +; RUN: llc -march=arm64 -aarch64-neon-syntax=apple < %s -asm-verbose=false -mcpu=cyclone | FileCheck %s define signext i8 @test_vaddv_s8(<8 x i8> %a1) { ; CHECK-LABEL: test_vaddv_s8: @@ -11,6 +11,18 @@ entry: ret i8 %0 } +define <8 x i8> @test_vaddv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) { +; CHECK-LABEL: test_vaddv_s8_used_by_laneop: +; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a2) + %1 = trunc i32 %0 to i8 + %2 = insertelement <8 x i8> %a1, i8 %1, i32 3 + ret <8 x i8> %2 +} + define signext i16 @test_vaddv_s16(<4 x i16> %a1) { ; CHECK-LABEL: test_vaddv_s16: ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0 @@ -22,6 +34,18 @@ entry: ret i16 %0 } +define <4 x i16> @test_vaddv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) { +; CHECK-LABEL: test_vaddv_s16_used_by_laneop: +; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a2) + %1 = trunc i32 %0 to i16 + %2 = insertelement <4 x i16> %a1, i16 %1, i32 3 + ret <4 x i16> %2 +} + define i32 @test_vaddv_s32(<2 x i32> %a1) { ; CHECK-LABEL: test_vaddv_s32: ; 2 x i32 is not supported by the ISA, thus, this is a special case @@ -33,6 +57,17 @@ entry: ret i32 %vaddv.i } +define <2 x i32> @test_vaddv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) { +; CHECK-LABEL: test_vaddv_s32_used_by_laneop: +; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1 +; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32> %a2) + %1 = insertelement <2 x i32> %a1, i32 %0, i32 1 + ret <2 x i32> %1 +} + define i64 @test_vaddv_s64(<2 x i64> %a1) { ; CHECK-LABEL: test_vaddv_s64: ; CHECK: addp.2d [[REGNUM:d[0-9]+]], v0 @@ -43,6 +78,17 @@ entry: ret i64 %vaddv.i } +define <2 x i64> @test_vaddv_s64_used_by_laneop(<2 x i64> %a1, <2 x i64> %a2) { +; CHECK-LABEL: test_vaddv_s64_used_by_laneop: +; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.d v0[1], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64> %a2) + %1 = insertelement <2 x i64> %a1, i64 %0, i64 1 + ret <2 x i64> %1 +} + define zeroext i8 @test_vaddv_u8(<8 x i8> %a1) { ; CHECK-LABEL: test_vaddv_u8: ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0 @@ -54,6 +100,18 @@ entry: ret i8 %0 } +define <8 x i8> @test_vaddv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) { +; CHECK-LABEL: test_vaddv_u8_used_by_laneop: +; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a2) + %1 = trunc i32 %0 to i8 + %2 = insertelement <8 x i8> %a1, i8 %1, i32 3 + ret <8 x i8> %2 +} + define i32 @test_vaddv_u8_masked(<8 x i8> %a1) { ; CHECK-LABEL: test_vaddv_u8_masked: ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0 @@ -76,6 +134,18 @@ entry: ret i16 %0 } +define <4 x i16> @test_vaddv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) { +; CHECK-LABEL: test_vaddv_u16_used_by_laneop: +; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a2) + %1 = trunc i32 %0 to i16 + %2 = insertelement <4 x i16> %a1, i16 %1, i32 3 + ret <4 x i16> %2 +} + define i32 @test_vaddv_u16_masked(<4 x i16> %a1) { ; CHECK-LABEL: test_vaddv_u16_masked: ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0 @@ -98,6 +168,17 @@ entry: ret i32 %vaddv.i } +define <2 x i32> @test_vaddv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) { +; CHECK-LABEL: test_vaddv_u32_used_by_laneop: +; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1 +; CHECK-NEXT: ins.s v0[1], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32> %a2) + %1 = insertelement <2 x i32> %a1, i32 %0, i32 1 + ret <2 x i32> %1 +} + define float @test_vaddv_f32(<2 x float> %a1) { ; CHECK-LABEL: test_vaddv_f32: ; CHECK: faddp.2s s0, v0 @@ -136,6 +217,17 @@ entry: ret i64 %vaddv.i } +define <2 x i64> @test_vaddv_u64_used_by_laneop(<2 x i64> %a1, <2 x i64> %a2) { +; CHECK-LABEL: test_vaddv_u64_used_by_laneop: +; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.d v0[1], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> %a2) + %1 = insertelement <2 x i64> %a1, i64 %0, i64 1 + ret <2 x i64> %1 +} + define <1 x i64> @test_vaddv_u64_to_vec(<2 x i64> %a1) { ; CHECK-LABEL: test_vaddv_u64_to_vec: ; CHECK: addp.2d d0, v0 @@ -159,6 +251,18 @@ entry: ret i8 %0 } +define <16 x i8> @test_vaddvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) { +; CHECK-LABEL: test_vaddvq_s8_used_by_laneop: +; CHECK: addv.16b b[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a2) + %1 = trunc i32 %0 to i8 + %2 = insertelement <16 x i8> %a1, i8 %1, i32 3 + ret <16 x i8> %2 +} + define signext i16 @test_vaddvq_s16(<8 x i16> %a1) { ; CHECK-LABEL: test_vaddvq_s16: ; CHECK: addv.8h h[[REGNUM:[0-9]+]], v0 @@ -170,6 +274,18 @@ entry: ret i16 %0 } +define <8 x i16> @test_vaddvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) { +; CHECK-LABEL: test_vaddvq_s16_used_by_laneop: +; CHECK: addv.8h h[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a2) + %1 = trunc i32 %0 to i16 + %2 = insertelement <8 x i16> %a1, i16 %1, i32 3 + ret <8 x i16> %2 +} + define i32 @test_vaddvq_s32(<4 x i32> %a1) { ; CHECK-LABEL: test_vaddvq_s32: ; CHECK: addv.4s [[REGNUM:s[0-9]+]], v0 @@ -180,6 +296,17 @@ entry: ret i32 %vaddv.i } +define <4 x i32> @test_vaddvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) { +; CHECK-LABEL: test_vaddvq_s32_used_by_laneop: +; CHECK: addv.4s s[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a2) + %1 = insertelement <4 x i32> %a1, i32 %0, i32 3 + ret <4 x i32> %1 +} + define zeroext i8 @test_vaddvq_u8(<16 x i8> %a1) { ; CHECK-LABEL: test_vaddvq_u8: ; CHECK: addv.16b b[[REGNUM:[0-9]+]], v0 @@ -191,6 +318,18 @@ entry: ret i8 %0 } +define <16 x i8> @test_vaddvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) { +; CHECK-LABEL: test_vaddvq_u8_used_by_laneop: +; CHECK: addv.16b b[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.b v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> %a2) + %1 = trunc i32 %0 to i8 + %2 = insertelement <16 x i8> %a1, i8 %1, i32 3 + ret <16 x i8> %2 +} + define zeroext i16 @test_vaddvq_u16(<8 x i16> %a1) { ; CHECK-LABEL: test_vaddvq_u16: ; CHECK: addv.8h h[[REGNUM:[0-9]+]], v0 @@ -202,6 +341,18 @@ entry: ret i16 %0 } +define <8 x i16> @test_vaddvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) { +; CHECK-LABEL: test_vaddvq_u16_used_by_laneop: +; CHECK: addv.8h h[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.h v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> %a2) + %1 = trunc i32 %0 to i16 + %2 = insertelement <8 x i16> %a1, i16 %1, i32 3 + ret <8 x i16> %2 +} + define i32 @test_vaddvq_u32(<4 x i32> %a1) { ; CHECK-LABEL: test_vaddvq_u32: ; CHECK: addv.4s [[REGNUM:s[0-9]+]], v0 @@ -212,6 +363,17 @@ entry: ret i32 %vaddv.i } +define <4 x i32> @test_vaddvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) { +; CHECK-LABEL: test_vaddvq_u32_used_by_laneop: +; CHECK: addv.4s s[[REGNUM:[0-9]+]], v1 +; CHECK-NEXT: ins.s v0[3], v[[REGNUM]][0] +; CHECK-NEXT: ret +entry: + %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> %a2) + %1 = insertelement <4 x i32> %a1, i32 %0, i32 3 + ret <4 x i32> %1 +} + declare i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32>) declare i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16>) diff --git a/test/CodeGen/AArch64/arm64-vbitwise.ll b/test/CodeGen/AArch64/arm64-vbitwise.ll index 93de95e..9cfcaaf 100644 --- a/test/CodeGen/AArch64/arm64-vbitwise.ll +++ b/test/CodeGen/AArch64/arm64-vbitwise.ll @@ -3,7 +3,7 @@ define <8 x i8> @rbit_8b(<8 x i8>* %A) nounwind { ;CHECK-LABEL: rbit_8b: ;CHECK: rbit.8b - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8> %tmp1) ret <8 x i8> %tmp3 } @@ -11,7 +11,7 @@ define <8 x i8> @rbit_8b(<8 x i8>* %A) nounwind { define <16 x i8> @rbit_16b(<16 x i8>* %A) nounwind { ;CHECK-LABEL: rbit_16b: ;CHECK: rbit.16b - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = call <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8> %tmp1) ret <16 x i8> %tmp3 } @@ -22,7 +22,7 @@ declare <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8>) nounwind readnone define <8 x i16> @sxtl8h(<8 x i8>* %A) nounwind { ;CHECK-LABEL: sxtl8h: ;CHECK: sshll.8h - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = sext <8 x i8> %tmp1 to <8 x i16> ret <8 x i16> %tmp2 } @@ -30,7 +30,7 @@ define <8 x i16> @sxtl8h(<8 x i8>* %A) nounwind { define <8 x i16> @uxtl8h(<8 x i8>* %A) nounwind { ;CHECK-LABEL: uxtl8h: ;CHECK: ushll.8h - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = zext <8 x i8> %tmp1 to <8 x i16> ret <8 x i16> %tmp2 } @@ -38,7 +38,7 @@ define <8 x i16> @uxtl8h(<8 x i8>* %A) nounwind { define <4 x i32> @sxtl4s(<4 x i16>* %A) nounwind { ;CHECK-LABEL: sxtl4s: ;CHECK: sshll.4s - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = sext <4 x i16> %tmp1 to <4 x i32> ret <4 x i32> %tmp2 } @@ -46,7 +46,7 @@ define <4 x i32> @sxtl4s(<4 x i16>* %A) nounwind { define <4 x i32> @uxtl4s(<4 x i16>* %A) nounwind { ;CHECK-LABEL: uxtl4s: ;CHECK: ushll.4s - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = zext <4 x i16> %tmp1 to <4 x i32> ret <4 x i32> %tmp2 } @@ -54,7 +54,7 @@ define <4 x i32> @uxtl4s(<4 x i16>* %A) nounwind { define <2 x i64> @sxtl2d(<2 x i32>* %A) nounwind { ;CHECK-LABEL: sxtl2d: ;CHECK: sshll.2d - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = sext <2 x i32> %tmp1 to <2 x i64> ret <2 x i64> %tmp2 } @@ -62,7 +62,7 @@ define <2 x i64> @sxtl2d(<2 x i32>* %A) nounwind { define <2 x i64> @uxtl2d(<2 x i32>* %A) nounwind { ;CHECK-LABEL: uxtl2d: ;CHECK: ushll.2d - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = zext <2 x i32> %tmp1 to <2 x i64> ret <2 x i64> %tmp2 } @@ -76,7 +76,7 @@ entry: ; CHECK: movi.2d [[REG1:v[0-9]+]], #0x0000ff000000ff ; CHECK: and.16b v{{[0-9]+}}, v{{[0-9]+}}, [[REG1]] %0 = bitcast i8* %src to <16 x i8>* - %1 = load <16 x i8>* %0, align 16 + %1 = load <16 x i8>, <16 x i8>* %0, align 16 %and.i = and <16 x i8> %1, <i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0> %2 = bitcast <16 x i8> %and.i to <8 x i16> %vshl_n = shl <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> diff --git a/test/CodeGen/AArch64/arm64-vcmp.ll b/test/CodeGen/AArch64/arm64-vcmp.ll index 982ab09..1b33eb5 100644 --- a/test/CodeGen/AArch64/arm64-vcmp.ll +++ b/test/CodeGen/AArch64/arm64-vcmp.ll @@ -16,8 +16,8 @@ define void @fcmltz_4s(<4 x float> %a, <4 x i16>* %p) nounwind { define <2 x i32> @facge_2s(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: facge_2s: ;CHECK: facge.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.facge.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x i32> %tmp3 } @@ -25,8 +25,8 @@ define <2 x i32> @facge_2s(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x i32> @facge_4s(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: facge_4s: ;CHECK: facge.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.facge.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x i32> %tmp3 } @@ -34,8 +34,8 @@ define <4 x i32> @facge_4s(<4 x float>* %A, <4 x float>* %B) nounwind { define <2 x i64> @facge_2d(<2 x double>* %A, <2 x double>* %B) nounwind { ;CHECK-LABEL: facge_2d: ;CHECK: facge.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.facge.v2i64.v2f64(<2 x double> %tmp1, <2 x double> %tmp2) ret <2 x i64> %tmp3 } @@ -47,8 +47,8 @@ declare <2 x i64> @llvm.aarch64.neon.facge.v2i64.v2f64(<2 x double>, <2 x double define <2 x i32> @facgt_2s(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: facgt_2s: ;CHECK: facgt.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.facgt.v2i32.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x i32> %tmp3 } @@ -56,8 +56,8 @@ define <2 x i32> @facgt_2s(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x i32> @facgt_4s(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: facgt_4s: ;CHECK: facgt.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.facgt.v4i32.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x i32> %tmp3 } @@ -65,8 +65,8 @@ define <4 x i32> @facgt_4s(<4 x float>* %A, <4 x float>* %B) nounwind { define <2 x i64> @facgt_2d(<2 x double>* %A, <2 x double>* %B) nounwind { ;CHECK-LABEL: facgt_2d: ;CHECK: facgt.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.facgt.v2i64.v2f64(<2 x double> %tmp1, <2 x double> %tmp2) ret <2 x i64> %tmp3 } @@ -112,8 +112,8 @@ declare i32 @llvm.aarch64.neon.facgt.i32.f32(float, float) define <8 x i8> @cmtst_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: cmtst_8b: ;CHECK: cmtst.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %commonbits = and <8 x i8> %tmp1, %tmp2 %mask = icmp ne <8 x i8> %commonbits, zeroinitializer %res = sext <8 x i1> %mask to <8 x i8> @@ -123,8 +123,8 @@ define <8 x i8> @cmtst_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @cmtst_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: cmtst_16b: ;CHECK: cmtst.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %commonbits = and <16 x i8> %tmp1, %tmp2 %mask = icmp ne <16 x i8> %commonbits, zeroinitializer %res = sext <16 x i1> %mask to <16 x i8> @@ -134,8 +134,8 @@ define <16 x i8> @cmtst_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @cmtst_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: cmtst_4h: ;CHECK: cmtst.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %commonbits = and <4 x i16> %tmp1, %tmp2 %mask = icmp ne <4 x i16> %commonbits, zeroinitializer %res = sext <4 x i1> %mask to <4 x i16> @@ -145,8 +145,8 @@ define <4 x i16> @cmtst_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @cmtst_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: cmtst_8h: ;CHECK: cmtst.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %commonbits = and <8 x i16> %tmp1, %tmp2 %mask = icmp ne <8 x i16> %commonbits, zeroinitializer %res = sext <8 x i1> %mask to <8 x i16> @@ -156,8 +156,8 @@ define <8 x i16> @cmtst_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @cmtst_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: cmtst_2s: ;CHECK: cmtst.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %commonbits = and <2 x i32> %tmp1, %tmp2 %mask = icmp ne <2 x i32> %commonbits, zeroinitializer %res = sext <2 x i1> %mask to <2 x i32> @@ -167,8 +167,8 @@ define <2 x i32> @cmtst_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @cmtst_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: cmtst_4s: ;CHECK: cmtst.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %commonbits = and <4 x i32> %tmp1, %tmp2 %mask = icmp ne <4 x i32> %commonbits, zeroinitializer %res = sext <4 x i1> %mask to <4 x i32> @@ -178,8 +178,8 @@ define <4 x i32> @cmtst_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @cmtst_2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: cmtst_2d: ;CHECK: cmtst.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %commonbits = and <2 x i64> %tmp1, %tmp2 %mask = icmp ne <2 x i64> %commonbits, zeroinitializer %res = sext <2 x i1> %mask to <2 x i64> diff --git a/test/CodeGen/AArch64/arm64-vcnt.ll b/test/CodeGen/AArch64/arm64-vcnt.ll index 903501e..5cff10c 100644 --- a/test/CodeGen/AArch64/arm64-vcnt.ll +++ b/test/CodeGen/AArch64/arm64-vcnt.ll @@ -3,7 +3,7 @@ define <8 x i8> @cls_8b(<8 x i8>* %A) nounwind { ;CHECK-LABEL: cls_8b: ;CHECK: cls.8b - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.cls.v8i8(<8 x i8> %tmp1) ret <8 x i8> %tmp3 } @@ -11,7 +11,7 @@ define <8 x i8> @cls_8b(<8 x i8>* %A) nounwind { define <16 x i8> @cls_16b(<16 x i8>* %A) nounwind { ;CHECK-LABEL: cls_16b: ;CHECK: cls.16b - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = call <16 x i8> @llvm.aarch64.neon.cls.v16i8(<16 x i8> %tmp1) ret <16 x i8> %tmp3 } @@ -19,7 +19,7 @@ define <16 x i8> @cls_16b(<16 x i8>* %A) nounwind { define <4 x i16> @cls_4h(<4 x i16>* %A) nounwind { ;CHECK-LABEL: cls_4h: ;CHECK: cls.4h - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.cls.v4i16(<4 x i16> %tmp1) ret <4 x i16> %tmp3 } @@ -27,7 +27,7 @@ define <4 x i16> @cls_4h(<4 x i16>* %A) nounwind { define <8 x i16> @cls_8h(<8 x i16>* %A) nounwind { ;CHECK-LABEL: cls_8h: ;CHECK: cls.8h - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i16> @llvm.aarch64.neon.cls.v8i16(<8 x i16> %tmp1) ret <8 x i16> %tmp3 } @@ -35,7 +35,7 @@ define <8 x i16> @cls_8h(<8 x i16>* %A) nounwind { define <2 x i32> @cls_2s(<2 x i32>* %A) nounwind { ;CHECK-LABEL: cls_2s: ;CHECK: cls.2s - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.cls.v2i32(<2 x i32> %tmp1) ret <2 x i32> %tmp3 } @@ -43,7 +43,7 @@ define <2 x i32> @cls_2s(<2 x i32>* %A) nounwind { define <4 x i32> @cls_4s(<4 x i32>* %A) nounwind { ;CHECK-LABEL: cls_4s: ;CHECK: cls.4s - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i32> @llvm.aarch64.neon.cls.v4i32(<4 x i32> %tmp1) ret <4 x i32> %tmp3 } diff --git a/test/CodeGen/AArch64/arm64-vcvt.ll b/test/CodeGen/AArch64/arm64-vcvt.ll index 6570f0e..13d2d28 100644 --- a/test/CodeGen/AArch64/arm64-vcvt.ll +++ b/test/CodeGen/AArch64/arm64-vcvt.ll @@ -675,7 +675,7 @@ define void @autogen_SD28458(<8 x double> %val.f64, <8 x float>* %addr.f32) { ;CHECK: fcvt ;CHECK: ret define void @autogen_SD19225(<8 x double>* %addr.f64, <8 x float>* %addr.f32) { - %A = load <8 x float>* %addr.f32 + %A = load <8 x float>, <8 x float>* %addr.f32 %Tr53 = fpext <8 x float> %A to <8 x double> store <8 x double> %Tr53, <8 x double>* %addr.f64 ret void diff --git a/test/CodeGen/AArch64/arm64-vector-imm.ll b/test/CodeGen/AArch64/arm64-vector-imm.ll index 9fb088b..d3de88d 100644 --- a/test/CodeGen/AArch64/arm64-vector-imm.ll +++ b/test/CodeGen/AArch64/arm64-vector-imm.ll @@ -5,7 +5,7 @@ define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind { ; CHECK-NOT: mov ; CHECK-NOT: mvn ; CHECK: orr - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1> ret <8 x i8> %tmp3 } @@ -15,7 +15,7 @@ define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind { ; CHECK-NOT: mov ; CHECK-NOT: mvn ; CHECK: orr - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1> ret <16 x i8> %tmp3 } @@ -25,7 +25,7 @@ define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind { ; CHECK-NOT: mov ; CHECK-NOT: mvn ; CHECK: bic - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > ret <8 x i8> %tmp3 } @@ -35,7 +35,7 @@ define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind { ; CHECK-NOT: mov ; CHECK-NOT: mvn ; CHECK: bic - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 > ret <16 x i8> %tmp3 } diff --git a/test/CodeGen/AArch64/arm64-vector-ldst.ll b/test/CodeGen/AArch64/arm64-vector-ldst.ll index c001915..26b9d62 100644 --- a/test/CodeGen/AArch64/arm64-vector-ldst.ll +++ b/test/CodeGen/AArch64/arm64-vector-ldst.ll @@ -12,8 +12,8 @@ entry: ; CHECK-LABEL: t1: ; CHECK: ldr x[[REG:[0-9]+]], [x0] ; CHECK: str q0, [x[[REG]]] - %tmp1 = load %type1** %argtable, align 8 - %tmp2 = getelementptr inbounds %type1* %tmp1, i64 0, i32 0 + %tmp1 = load %type1*, %type1** %argtable, align 8 + %tmp2 = getelementptr inbounds %type1, %type1* %tmp1, i64 0, i32 0 store <16 x i8> zeroinitializer, <16 x i8>* %tmp2, align 16 ret void } @@ -23,8 +23,8 @@ entry: ; CHECK-LABEL: t2: ; CHECK: ldr x[[REG:[0-9]+]], [x0] ; CHECK: str d0, [x[[REG]]] - %tmp1 = load %type2** %argtable, align 8 - %tmp2 = getelementptr inbounds %type2* %tmp1, i64 0, i32 0 + %tmp1 = load %type2*, %type2** %argtable, align 8 + %tmp2 = getelementptr inbounds %type2, %type2* %tmp1, i64 0, i32 0 store <8 x i8> zeroinitializer, <8 x i8>* %tmp2, align 8 ret void } @@ -51,10 +51,10 @@ entry: ; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]] ; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]] - %arrayidx = getelementptr inbounds <2 x i64>* %array, i64 %offset - %tmp = load <2 x i64>* %arrayidx, align 16 - %tmp1 = load <2 x i64>** @globalArray64x2, align 8 - %arrayidx1 = getelementptr inbounds <2 x i64>* %tmp1, i64 %offset + %arrayidx = getelementptr inbounds <2 x i64>, <2 x i64>* %array, i64 %offset + %tmp = load <2 x i64>, <2 x i64>* %arrayidx, align 16 + %tmp1 = load <2 x i64>*, <2 x i64>** @globalArray64x2, align 8 + %arrayidx1 = getelementptr inbounds <2 x i64>, <2 x i64>* %tmp1, i64 %offset store <2 x i64> %tmp, <2 x i64>* %arrayidx1, align 16 ret void } @@ -65,10 +65,10 @@ entry: ; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48] ; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: str [[DEST]], {{\[}}[[BASE]], #80] - %arrayidx = getelementptr inbounds <2 x i64>* %array, i64 3 - %tmp = load <2 x i64>* %arrayidx, align 16 - %tmp1 = load <2 x i64>** @globalArray64x2, align 8 - %arrayidx1 = getelementptr inbounds <2 x i64>* %tmp1, i64 5 + %arrayidx = getelementptr inbounds <2 x i64>, <2 x i64>* %array, i64 3 + %tmp = load <2 x i64>, <2 x i64>* %arrayidx, align 16 + %tmp1 = load <2 x i64>*, <2 x i64>** @globalArray64x2, align 8 + %arrayidx1 = getelementptr inbounds <2 x i64>, <2 x i64>* %tmp1, i64 5 store <2 x i64> %tmp, <2 x i64>* %arrayidx1, align 16 ret void } @@ -80,10 +80,10 @@ entry: ; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]] ; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]] - %arrayidx = getelementptr inbounds <4 x i32>* %array, i64 %offset - %tmp = load <4 x i32>* %arrayidx, align 16 - %tmp1 = load <4 x i32>** @globalArray32x4, align 8 - %arrayidx1 = getelementptr inbounds <4 x i32>* %tmp1, i64 %offset + %arrayidx = getelementptr inbounds <4 x i32>, <4 x i32>* %array, i64 %offset + %tmp = load <4 x i32>, <4 x i32>* %arrayidx, align 16 + %tmp1 = load <4 x i32>*, <4 x i32>** @globalArray32x4, align 8 + %arrayidx1 = getelementptr inbounds <4 x i32>, <4 x i32>* %tmp1, i64 %offset store <4 x i32> %tmp, <4 x i32>* %arrayidx1, align 16 ret void } @@ -94,10 +94,10 @@ entry: ; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48] ; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: str [[DEST]], {{\[}}[[BASE]], #80] - %arrayidx = getelementptr inbounds <4 x i32>* %array, i64 3 - %tmp = load <4 x i32>* %arrayidx, align 16 - %tmp1 = load <4 x i32>** @globalArray32x4, align 8 - %arrayidx1 = getelementptr inbounds <4 x i32>* %tmp1, i64 5 + %arrayidx = getelementptr inbounds <4 x i32>, <4 x i32>* %array, i64 3 + %tmp = load <4 x i32>, <4 x i32>* %arrayidx, align 16 + %tmp1 = load <4 x i32>*, <4 x i32>** @globalArray32x4, align 8 + %arrayidx1 = getelementptr inbounds <4 x i32>, <4 x i32>* %tmp1, i64 5 store <4 x i32> %tmp, <4 x i32>* %arrayidx1, align 16 ret void } @@ -109,10 +109,10 @@ entry: ; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]] ; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]] - %arrayidx = getelementptr inbounds <8 x i16>* %array, i64 %offset - %tmp = load <8 x i16>* %arrayidx, align 16 - %tmp1 = load <8 x i16>** @globalArray16x8, align 8 - %arrayidx1 = getelementptr inbounds <8 x i16>* %tmp1, i64 %offset + %arrayidx = getelementptr inbounds <8 x i16>, <8 x i16>* %array, i64 %offset + %tmp = load <8 x i16>, <8 x i16>* %arrayidx, align 16 + %tmp1 = load <8 x i16>*, <8 x i16>** @globalArray16x8, align 8 + %arrayidx1 = getelementptr inbounds <8 x i16>, <8 x i16>* %tmp1, i64 %offset store <8 x i16> %tmp, <8 x i16>* %arrayidx1, align 16 ret void } @@ -123,10 +123,10 @@ entry: ; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48] ; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: str [[DEST]], {{\[}}[[BASE]], #80] - %arrayidx = getelementptr inbounds <8 x i16>* %array, i64 3 - %tmp = load <8 x i16>* %arrayidx, align 16 - %tmp1 = load <8 x i16>** @globalArray16x8, align 8 - %arrayidx1 = getelementptr inbounds <8 x i16>* %tmp1, i64 5 + %arrayidx = getelementptr inbounds <8 x i16>, <8 x i16>* %array, i64 3 + %tmp = load <8 x i16>, <8 x i16>* %arrayidx, align 16 + %tmp1 = load <8 x i16>*, <8 x i16>** @globalArray16x8, align 8 + %arrayidx1 = getelementptr inbounds <8 x i16>, <8 x i16>* %tmp1, i64 5 store <8 x i16> %tmp, <8 x i16>* %arrayidx1, align 16 ret void } @@ -138,10 +138,10 @@ entry: ; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]] ; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]] - %arrayidx = getelementptr inbounds <16 x i8>* %array, i64 %offset - %tmp = load <16 x i8>* %arrayidx, align 16 - %tmp1 = load <16 x i8>** @globalArray8x16, align 8 - %arrayidx1 = getelementptr inbounds <16 x i8>* %tmp1, i64 %offset + %arrayidx = getelementptr inbounds <16 x i8>, <16 x i8>* %array, i64 %offset + %tmp = load <16 x i8>, <16 x i8>* %arrayidx, align 16 + %tmp1 = load <16 x i8>*, <16 x i8>** @globalArray8x16, align 8 + %arrayidx1 = getelementptr inbounds <16 x i8>, <16 x i8>* %tmp1, i64 %offset store <16 x i8> %tmp, <16 x i8>* %arrayidx1, align 16 ret void } @@ -152,10 +152,10 @@ entry: ; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48] ; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: str [[DEST]], {{\[}}[[BASE]], #80] - %arrayidx = getelementptr inbounds <16 x i8>* %array, i64 3 - %tmp = load <16 x i8>* %arrayidx, align 16 - %tmp1 = load <16 x i8>** @globalArray8x16, align 8 - %arrayidx1 = getelementptr inbounds <16 x i8>* %tmp1, i64 5 + %arrayidx = getelementptr inbounds <16 x i8>, <16 x i8>* %array, i64 3 + %tmp = load <16 x i8>, <16 x i8>* %arrayidx, align 16 + %tmp1 = load <16 x i8>*, <16 x i8>** @globalArray8x16, align 8 + %arrayidx1 = getelementptr inbounds <16 x i8>, <16 x i8>* %tmp1, i64 5 store <16 x i8> %tmp, <16 x i8>* %arrayidx1, align 16 ret void } @@ -167,10 +167,10 @@ entry: ; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]] ; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]] - %arrayidx = getelementptr inbounds <1 x i64>* %array, i64 %offset - %tmp = load <1 x i64>* %arrayidx, align 8 - %tmp1 = load <1 x i64>** @globalArray64x1, align 8 - %arrayidx1 = getelementptr inbounds <1 x i64>* %tmp1, i64 %offset + %arrayidx = getelementptr inbounds <1 x i64>, <1 x i64>* %array, i64 %offset + %tmp = load <1 x i64>, <1 x i64>* %arrayidx, align 8 + %tmp1 = load <1 x i64>*, <1 x i64>** @globalArray64x1, align 8 + %arrayidx1 = getelementptr inbounds <1 x i64>, <1 x i64>* %tmp1, i64 %offset store <1 x i64> %tmp, <1 x i64>* %arrayidx1, align 8 ret void } @@ -181,10 +181,10 @@ entry: ; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24] ; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: str [[DEST]], {{\[}}[[BASE]], #40] - %arrayidx = getelementptr inbounds <1 x i64>* %array, i64 3 - %tmp = load <1 x i64>* %arrayidx, align 8 - %tmp1 = load <1 x i64>** @globalArray64x1, align 8 - %arrayidx1 = getelementptr inbounds <1 x i64>* %tmp1, i64 5 + %arrayidx = getelementptr inbounds <1 x i64>, <1 x i64>* %array, i64 3 + %tmp = load <1 x i64>, <1 x i64>* %arrayidx, align 8 + %tmp1 = load <1 x i64>*, <1 x i64>** @globalArray64x1, align 8 + %arrayidx1 = getelementptr inbounds <1 x i64>, <1 x i64>* %tmp1, i64 5 store <1 x i64> %tmp, <1 x i64>* %arrayidx1, align 8 ret void } @@ -196,10 +196,10 @@ entry: ; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]] ; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]] - %arrayidx = getelementptr inbounds <2 x i32>* %array, i64 %offset - %tmp = load <2 x i32>* %arrayidx, align 8 - %tmp1 = load <2 x i32>** @globalArray32x2, align 8 - %arrayidx1 = getelementptr inbounds <2 x i32>* %tmp1, i64 %offset + %arrayidx = getelementptr inbounds <2 x i32>, <2 x i32>* %array, i64 %offset + %tmp = load <2 x i32>, <2 x i32>* %arrayidx, align 8 + %tmp1 = load <2 x i32>*, <2 x i32>** @globalArray32x2, align 8 + %arrayidx1 = getelementptr inbounds <2 x i32>, <2 x i32>* %tmp1, i64 %offset store <2 x i32> %tmp, <2 x i32>* %arrayidx1, align 8 ret void } @@ -210,10 +210,10 @@ entry: ; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24] ; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: str [[DEST]], {{\[}}[[BASE]], #40] - %arrayidx = getelementptr inbounds <2 x i32>* %array, i64 3 - %tmp = load <2 x i32>* %arrayidx, align 8 - %tmp1 = load <2 x i32>** @globalArray32x2, align 8 - %arrayidx1 = getelementptr inbounds <2 x i32>* %tmp1, i64 5 + %arrayidx = getelementptr inbounds <2 x i32>, <2 x i32>* %array, i64 3 + %tmp = load <2 x i32>, <2 x i32>* %arrayidx, align 8 + %tmp1 = load <2 x i32>*, <2 x i32>** @globalArray32x2, align 8 + %arrayidx1 = getelementptr inbounds <2 x i32>, <2 x i32>* %tmp1, i64 5 store <2 x i32> %tmp, <2 x i32>* %arrayidx1, align 8 ret void } @@ -225,10 +225,10 @@ entry: ; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]] ; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]] - %arrayidx = getelementptr inbounds <4 x i16>* %array, i64 %offset - %tmp = load <4 x i16>* %arrayidx, align 8 - %tmp1 = load <4 x i16>** @globalArray16x4, align 8 - %arrayidx1 = getelementptr inbounds <4 x i16>* %tmp1, i64 %offset + %arrayidx = getelementptr inbounds <4 x i16>, <4 x i16>* %array, i64 %offset + %tmp = load <4 x i16>, <4 x i16>* %arrayidx, align 8 + %tmp1 = load <4 x i16>*, <4 x i16>** @globalArray16x4, align 8 + %arrayidx1 = getelementptr inbounds <4 x i16>, <4 x i16>* %tmp1, i64 %offset store <4 x i16> %tmp, <4 x i16>* %arrayidx1, align 8 ret void } @@ -239,10 +239,10 @@ entry: ; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24] ; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: str [[DEST]], {{\[}}[[BASE]], #40] - %arrayidx = getelementptr inbounds <4 x i16>* %array, i64 3 - %tmp = load <4 x i16>* %arrayidx, align 8 - %tmp1 = load <4 x i16>** @globalArray16x4, align 8 - %arrayidx1 = getelementptr inbounds <4 x i16>* %tmp1, i64 5 + %arrayidx = getelementptr inbounds <4 x i16>, <4 x i16>* %array, i64 3 + %tmp = load <4 x i16>, <4 x i16>* %arrayidx, align 8 + %tmp1 = load <4 x i16>*, <4 x i16>** @globalArray16x4, align 8 + %arrayidx1 = getelementptr inbounds <4 x i16>, <4 x i16>* %tmp1, i64 5 store <4 x i16> %tmp, <4 x i16>* %arrayidx1, align 8 ret void } @@ -254,10 +254,10 @@ entry: ; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]] ; CHECK: ldr [[BASE:x[0-9]+]], ; CHECK: str [[DEST]], {{\[}}[[BASE]], [[SHIFTEDOFFSET]]] - %arrayidx = getelementptr inbounds <8 x i8>* %array, i64 %offset - %tmp = load <8 x i8>* %arrayidx, align 8 - %tmp1 = load <8 x i8>** @globalArray8x8, align 8 - %arrayidx1 = getelementptr inbounds <8 x i8>* %tmp1, i64 %offset + %arrayidx = getelementptr inbounds <8 x i8>, <8 x i8>* %array, i64 %offset + %tmp = load <8 x i8>, <8 x i8>* %arrayidx, align 8 + %tmp1 = load <8 x i8>*, <8 x i8>** @globalArray8x8, align 8 + %arrayidx1 = getelementptr inbounds <8 x i8>, <8 x i8>* %tmp1, i64 %offset store <8 x i8> %tmp, <8 x i8>* %arrayidx1, align 8 ret void } @@ -270,7 +270,7 @@ define <1 x i64> @fct0() nounwind readonly ssp { entry: ; CHECK-LABEL: fct0: ; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3] - %0 = load <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <1 x i64>*), align 8 + %0 = load <1 x i64>, <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <1 x i64>*), align 8 ret <1 x i64> %0 } @@ -278,7 +278,7 @@ define <2 x i32> @fct1() nounwind readonly ssp { entry: ; CHECK-LABEL: fct1: ; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3] - %0 = load <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <2 x i32>*), align 8 + %0 = load <2 x i32>, <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <2 x i32>*), align 8 ret <2 x i32> %0 } @@ -286,7 +286,7 @@ define <4 x i16> @fct2() nounwind readonly ssp { entry: ; CHECK-LABEL: fct2: ; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3] - %0 = load <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <4 x i16>*), align 8 + %0 = load <4 x i16>, <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <4 x i16>*), align 8 ret <4 x i16> %0 } @@ -294,7 +294,7 @@ define <8 x i8> @fct3() nounwind readonly ssp { entry: ; CHECK-LABEL: fct3: ; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3] - %0 = load <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <8 x i8>*), align 8 + %0 = load <8 x i8>, <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <8 x i8>*), align 8 ret <8 x i8> %0 } @@ -302,7 +302,7 @@ define <2 x i64> @fct4() nounwind readonly ssp { entry: ; CHECK-LABEL: fct4: ; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3] - %0 = load <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <2 x i64>*), align 16 + %0 = load <2 x i64>, <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <2 x i64>*), align 16 ret <2 x i64> %0 } @@ -310,7 +310,7 @@ define <4 x i32> @fct5() nounwind readonly ssp { entry: ; CHECK-LABEL: fct5: ; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3] - %0 = load <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <4 x i32>*), align 16 + %0 = load <4 x i32>, <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <4 x i32>*), align 16 ret <4 x i32> %0 } @@ -318,7 +318,7 @@ define <8 x i16> @fct6() nounwind readonly ssp { entry: ; CHECK-LABEL: fct6: ; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3] - %0 = load <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <8 x i16>*), align 16 + %0 = load <8 x i16>, <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <8 x i16>*), align 16 ret <8 x i16> %0 } @@ -326,7 +326,7 @@ define <16 x i8> @fct7() nounwind readonly ssp { entry: ; CHECK-LABEL: fct7: ; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3] - %0 = load <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <16 x i8>*), align 16 + %0 = load <16 x i8>, <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <16 x i8>*), align 16 ret <16 x i8> %0 } @@ -335,8 +335,8 @@ entry: ; CHECK-LABEL: fct8: ; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3] ; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4] - %0 = load <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <1 x i64>*), align 8 - store <1 x i64> %0, <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <1 x i64>*), align 8 + %0 = load <1 x i64>, <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <1 x i64>*), align 8 + store <1 x i64> %0, <1 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <1 x i64>*), align 8 ret void } @@ -345,8 +345,8 @@ entry: ; CHECK-LABEL: fct9: ; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3] ; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4] - %0 = load <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <2 x i32>*), align 8 - store <2 x i32> %0, <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <2 x i32>*), align 8 + %0 = load <2 x i32>, <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <2 x i32>*), align 8 + store <2 x i32> %0, <2 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <2 x i32>*), align 8 ret void } @@ -355,8 +355,8 @@ entry: ; CHECK-LABEL: fct10: ; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3] ; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4] - %0 = load <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <4 x i16>*), align 8 - store <4 x i16> %0, <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <4 x i16>*), align 8 + %0 = load <4 x i16>, <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <4 x i16>*), align 8 + store <4 x i16> %0, <4 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <4 x i16>*), align 8 ret void } @@ -365,8 +365,8 @@ entry: ; CHECK-LABEL: fct11: ; CHECK: ldur [[DESTREG:d[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3] ; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4] - %0 = load <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <8 x i8>*), align 8 - store <8 x i8> %0, <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <8 x i8>*), align 8 + %0 = load <8 x i8>, <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <8 x i8>*), align 8 + store <8 x i8> %0, <8 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <8 x i8>*), align 8 ret void } @@ -375,8 +375,8 @@ entry: ; CHECK-LABEL: fct12: ; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3] ; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4] - %0 = load <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <2 x i64>*), align 16 - store <2 x i64> %0, <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <2 x i64>*), align 16 + %0 = load <2 x i64>, <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <2 x i64>*), align 16 + store <2 x i64> %0, <2 x i64>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <2 x i64>*), align 16 ret void } @@ -385,8 +385,8 @@ entry: ; CHECK-LABEL: fct13: ; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3] ; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4] - %0 = load <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <4 x i32>*), align 16 - store <4 x i32> %0, <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <4 x i32>*), align 16 + %0 = load <4 x i32>, <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <4 x i32>*), align 16 + store <4 x i32> %0, <4 x i32>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <4 x i32>*), align 16 ret void } @@ -395,8 +395,8 @@ entry: ; CHECK-LABEL: fct14: ; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3] ; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4] - %0 = load <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <8 x i16>*), align 16 - store <8 x i16> %0, <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <8 x i16>*), align 16 + %0 = load <8 x i16>, <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <8 x i16>*), align 16 + store <8 x i16> %0, <8 x i16>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <8 x i16>*), align 16 ret void } @@ -405,8 +405,8 @@ entry: ; CHECK-LABEL: fct15: ; CHECK: ldur [[DESTREG:q[0-9]+]], {{\[}}[[BASEREG:x[0-9]+]], #3] ; CHECK: stur [[DESTREG]], {{\[}}[[BASEREG]], #4] - %0 = load <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 3) to <16 x i8>*), align 16 - store <16 x i8> %0, <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8]* @str, i64 0, i64 4) to <16 x i8>*), align 16 + %0 = load <16 x i8>, <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 3) to <16 x i8>*), align 16 + store <16 x i8> %0, <16 x i8>* bitcast (i8* getelementptr inbounds ([63 x i8], [63 x i8]* @str, i64 0, i64 4) to <16 x i8>*), align 16 ret void } @@ -419,8 +419,8 @@ define <8 x i8> @fct16(i8* nocapture %sp0) { ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1] ; CHECK-NEXT: mul.8b v0, v[[REGNUM]], v[[REGNUM]] entry: - %addr = getelementptr i8* %sp0, i64 1 - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %vec = insertelement <8 x i8> undef, i8 %pix_sp0.0.copyload, i32 0 %vmull.i = mul <8 x i8> %vec, %vec ret <8 x i8> %vmull.i @@ -431,8 +431,8 @@ define <16 x i8> @fct17(i8* nocapture %sp0) { ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1] ; CHECK-NEXT: mul.16b v0, v[[REGNUM]], v[[REGNUM]] entry: - %addr = getelementptr i8* %sp0, i64 1 - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %vec = insertelement <16 x i8> undef, i8 %pix_sp0.0.copyload, i32 0 %vmull.i = mul <16 x i8> %vec, %vec ret <16 x i8> %vmull.i @@ -443,8 +443,8 @@ define <4 x i16> @fct18(i16* nocapture %sp0) { ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2] ; CHECK-NEXT: mul.4h v0, v[[REGNUM]], v[[REGNUM]] entry: - %addr = getelementptr i16* %sp0, i64 1 - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %vec = insertelement <4 x i16> undef, i16 %pix_sp0.0.copyload, i32 0 %vmull.i = mul <4 x i16> %vec, %vec ret <4 x i16> %vmull.i @@ -455,8 +455,8 @@ define <8 x i16> @fct19(i16* nocapture %sp0) { ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2] ; CHECK-NEXT: mul.8h v0, v[[REGNUM]], v[[REGNUM]] entry: - %addr = getelementptr i16* %sp0, i64 1 - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %vec = insertelement <8 x i16> undef, i16 %pix_sp0.0.copyload, i32 0 %vmull.i = mul <8 x i16> %vec, %vec ret <8 x i16> %vmull.i @@ -467,8 +467,8 @@ define <2 x i32> @fct20(i32* nocapture %sp0) { ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4] ; CHECK-NEXT: mul.2s v0, v[[REGNUM]], v[[REGNUM]] entry: - %addr = getelementptr i32* %sp0, i64 1 - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0 %vmull.i = mul <2 x i32> %vec, %vec ret <2 x i32> %vmull.i @@ -479,8 +479,8 @@ define <4 x i32> @fct21(i32* nocapture %sp0) { ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4] ; CHECK-NEXT: mul.4s v0, v[[REGNUM]], v[[REGNUM]] entry: - %addr = getelementptr i32* %sp0, i64 1 - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %vec = insertelement <4 x i32> undef, i32 %pix_sp0.0.copyload, i32 0 %vmull.i = mul <4 x i32> %vec, %vec ret <4 x i32> %vmull.i @@ -490,8 +490,8 @@ define <1 x i64> @fct22(i64* nocapture %sp0) { ; CHECK-LABEL: fct22: ; CHECK: ldr d0, [x0, #8] entry: - %addr = getelementptr i64* %sp0, i64 1 - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %vec = insertelement <1 x i64> undef, i64 %pix_sp0.0.copyload, i32 0 ret <1 x i64> %vec } @@ -500,8 +500,8 @@ define <2 x i64> @fct23(i64* nocapture %sp0) { ; CHECK-LABEL: fct23: ; CHECK: ldr d[[REGNUM:[0-9]+]], [x0, #8] entry: - %addr = getelementptr i64* %sp0, i64 1 - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %vec = insertelement <2 x i64> undef, i64 %pix_sp0.0.copyload, i32 0 ret <2 x i64> %vec } @@ -513,8 +513,8 @@ define <8 x i8> @fct24(i8* nocapture %sp0, i64 %offset) { ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1] ; CHECK-NEXT: mul.8b v0, v[[REGNUM]], v[[REGNUM]] entry: - %addr = getelementptr i8* %sp0, i64 %offset - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 %offset + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %vec = insertelement <8 x i8> undef, i8 %pix_sp0.0.copyload, i32 0 %vmull.i = mul <8 x i8> %vec, %vec ret <8 x i8> %vmull.i @@ -525,8 +525,8 @@ define <16 x i8> @fct25(i8* nocapture %sp0, i64 %offset) { ; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1] ; CHECK-NEXT: mul.16b v0, v[[REGNUM]], v[[REGNUM]] entry: - %addr = getelementptr i8* %sp0, i64 %offset - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 %offset + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %vec = insertelement <16 x i8> undef, i8 %pix_sp0.0.copyload, i32 0 %vmull.i = mul <16 x i8> %vec, %vec ret <16 x i8> %vmull.i @@ -537,8 +537,8 @@ define <4 x i16> @fct26(i16* nocapture %sp0, i64 %offset) { ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1] ; CHECK-NEXT: mul.4h v0, v[[REGNUM]], v[[REGNUM]] entry: - %addr = getelementptr i16* %sp0, i64 %offset - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 %offset + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %vec = insertelement <4 x i16> undef, i16 %pix_sp0.0.copyload, i32 0 %vmull.i = mul <4 x i16> %vec, %vec ret <4 x i16> %vmull.i @@ -549,8 +549,8 @@ define <8 x i16> @fct27(i16* nocapture %sp0, i64 %offset) { ; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1] ; CHECK-NEXT: mul.8h v0, v[[REGNUM]], v[[REGNUM]] entry: - %addr = getelementptr i16* %sp0, i64 %offset - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 %offset + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %vec = insertelement <8 x i16> undef, i16 %pix_sp0.0.copyload, i32 0 %vmull.i = mul <8 x i16> %vec, %vec ret <8 x i16> %vmull.i @@ -561,8 +561,8 @@ define <2 x i32> @fct28(i32* nocapture %sp0, i64 %offset) { ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2] ; CHECK-NEXT: mul.2s v0, v[[REGNUM]], v[[REGNUM]] entry: - %addr = getelementptr i32* %sp0, i64 %offset - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 %offset + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0 %vmull.i = mul <2 x i32> %vec, %vec ret <2 x i32> %vmull.i @@ -573,8 +573,8 @@ define <4 x i32> @fct29(i32* nocapture %sp0, i64 %offset) { ; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2] ; CHECK-NEXT: mul.4s v0, v[[REGNUM]], v[[REGNUM]] entry: - %addr = getelementptr i32* %sp0, i64 %offset - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 %offset + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %vec = insertelement <4 x i32> undef, i32 %pix_sp0.0.copyload, i32 0 %vmull.i = mul <4 x i32> %vec, %vec ret <4 x i32> %vmull.i @@ -584,8 +584,8 @@ define <1 x i64> @fct30(i64* nocapture %sp0, i64 %offset) { ; CHECK-LABEL: fct30: ; CHECK: ldr d0, [x0, x1, lsl #3] entry: - %addr = getelementptr i64* %sp0, i64 %offset - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 %offset + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %vec = insertelement <1 x i64> undef, i64 %pix_sp0.0.copyload, i32 0 ret <1 x i64> %vec } @@ -594,8 +594,8 @@ define <2 x i64> @fct31(i64* nocapture %sp0, i64 %offset) { ; CHECK-LABEL: fct31: ; CHECK: ldr d0, [x0, x1, lsl #3] entry: - %addr = getelementptr i64* %sp0, i64 %offset - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 %offset + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %vec = insertelement <2 x i64> undef, i64 %pix_sp0.0.copyload, i32 0 ret <2 x i64> %vec } diff --git a/test/CodeGen/AArch64/arm64-vext.ll b/test/CodeGen/AArch64/arm64-vext.ll index 2240dfd..fa57eeb 100644 --- a/test/CodeGen/AArch64/arm64-vext.ll +++ b/test/CodeGen/AArch64/arm64-vext.ll @@ -6,12 +6,12 @@ define void @test_vext_s8() nounwind ssp { %xS8x8 = alloca <8 x i8>, align 8 %__a = alloca <8 x i8>, align 8 %__b = alloca <8 x i8>, align 8 - %tmp = load <8 x i8>* %xS8x8, align 8 + %tmp = load <8 x i8>, <8 x i8>* %xS8x8, align 8 store <8 x i8> %tmp, <8 x i8>* %__a, align 8 - %tmp1 = load <8 x i8>* %xS8x8, align 8 + %tmp1 = load <8 x i8>, <8 x i8>* %xS8x8, align 8 store <8 x i8> %tmp1, <8 x i8>* %__b, align 8 - %tmp2 = load <8 x i8>* %__a, align 8 - %tmp3 = load <8 x i8>* %__b, align 8 + %tmp2 = load <8 x i8>, <8 x i8>* %__a, align 8 + %tmp3 = load <8 x i8>, <8 x i8>* %__b, align 8 %vext = shufflevector <8 x i8> %tmp2, <8 x i8> %tmp3, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8> store <8 x i8> %vext, <8 x i8>* %xS8x8, align 8 ret void @@ -23,12 +23,12 @@ define void @test_vext_u8() nounwind ssp { %xU8x8 = alloca <8 x i8>, align 8 %__a = alloca <8 x i8>, align 8 %__b = alloca <8 x i8>, align 8 - %tmp = load <8 x i8>* %xU8x8, align 8 + %tmp = load <8 x i8>, <8 x i8>* %xU8x8, align 8 store <8 x i8> %tmp, <8 x i8>* %__a, align 8 - %tmp1 = load <8 x i8>* %xU8x8, align 8 + %tmp1 = load <8 x i8>, <8 x i8>* %xU8x8, align 8 store <8 x i8> %tmp1, <8 x i8>* %__b, align 8 - %tmp2 = load <8 x i8>* %__a, align 8 - %tmp3 = load <8 x i8>* %__b, align 8 + %tmp2 = load <8 x i8>, <8 x i8>* %__a, align 8 + %tmp3 = load <8 x i8>, <8 x i8>* %__b, align 8 %vext = shufflevector <8 x i8> %tmp2, <8 x i8> %tmp3, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9> store <8 x i8> %vext, <8 x i8>* %xU8x8, align 8 ret void @@ -40,12 +40,12 @@ define void @test_vext_p8() nounwind ssp { %xP8x8 = alloca <8 x i8>, align 8 %__a = alloca <8 x i8>, align 8 %__b = alloca <8 x i8>, align 8 - %tmp = load <8 x i8>* %xP8x8, align 8 + %tmp = load <8 x i8>, <8 x i8>* %xP8x8, align 8 store <8 x i8> %tmp, <8 x i8>* %__a, align 8 - %tmp1 = load <8 x i8>* %xP8x8, align 8 + %tmp1 = load <8 x i8>, <8 x i8>* %xP8x8, align 8 store <8 x i8> %tmp1, <8 x i8>* %__b, align 8 - %tmp2 = load <8 x i8>* %__a, align 8 - %tmp3 = load <8 x i8>* %__b, align 8 + %tmp2 = load <8 x i8>, <8 x i8>* %__a, align 8 + %tmp3 = load <8 x i8>, <8 x i8>* %__b, align 8 %vext = shufflevector <8 x i8> %tmp2, <8 x i8> %tmp3, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10> store <8 x i8> %vext, <8 x i8>* %xP8x8, align 8 ret void @@ -57,13 +57,13 @@ define void @test_vext_s16() nounwind ssp { %xS16x4 = alloca <4 x i16>, align 8 %__a = alloca <4 x i16>, align 8 %__b = alloca <4 x i16>, align 8 - %tmp = load <4 x i16>* %xS16x4, align 8 + %tmp = load <4 x i16>, <4 x i16>* %xS16x4, align 8 store <4 x i16> %tmp, <4 x i16>* %__a, align 8 - %tmp1 = load <4 x i16>* %xS16x4, align 8 + %tmp1 = load <4 x i16>, <4 x i16>* %xS16x4, align 8 store <4 x i16> %tmp1, <4 x i16>* %__b, align 8 - %tmp2 = load <4 x i16>* %__a, align 8 + %tmp2 = load <4 x i16>, <4 x i16>* %__a, align 8 %tmp3 = bitcast <4 x i16> %tmp2 to <8 x i8> - %tmp4 = load <4 x i16>* %__b, align 8 + %tmp4 = load <4 x i16>, <4 x i16>* %__b, align 8 %tmp5 = bitcast <4 x i16> %tmp4 to <8 x i8> %tmp6 = bitcast <8 x i8> %tmp3 to <4 x i16> %tmp7 = bitcast <8 x i8> %tmp5 to <4 x i16> @@ -78,13 +78,13 @@ define void @test_vext_u16() nounwind ssp { %xU16x4 = alloca <4 x i16>, align 8 %__a = alloca <4 x i16>, align 8 %__b = alloca <4 x i16>, align 8 - %tmp = load <4 x i16>* %xU16x4, align 8 + %tmp = load <4 x i16>, <4 x i16>* %xU16x4, align 8 store <4 x i16> %tmp, <4 x i16>* %__a, align 8 - %tmp1 = load <4 x i16>* %xU16x4, align 8 + %tmp1 = load <4 x i16>, <4 x i16>* %xU16x4, align 8 store <4 x i16> %tmp1, <4 x i16>* %__b, align 8 - %tmp2 = load <4 x i16>* %__a, align 8 + %tmp2 = load <4 x i16>, <4 x i16>* %__a, align 8 %tmp3 = bitcast <4 x i16> %tmp2 to <8 x i8> - %tmp4 = load <4 x i16>* %__b, align 8 + %tmp4 = load <4 x i16>, <4 x i16>* %__b, align 8 %tmp5 = bitcast <4 x i16> %tmp4 to <8 x i8> %tmp6 = bitcast <8 x i8> %tmp3 to <4 x i16> %tmp7 = bitcast <8 x i8> %tmp5 to <4 x i16> @@ -99,13 +99,13 @@ define void @test_vext_p16() nounwind ssp { %xP16x4 = alloca <4 x i16>, align 8 %__a = alloca <4 x i16>, align 8 %__b = alloca <4 x i16>, align 8 - %tmp = load <4 x i16>* %xP16x4, align 8 + %tmp = load <4 x i16>, <4 x i16>* %xP16x4, align 8 store <4 x i16> %tmp, <4 x i16>* %__a, align 8 - %tmp1 = load <4 x i16>* %xP16x4, align 8 + %tmp1 = load <4 x i16>, <4 x i16>* %xP16x4, align 8 store <4 x i16> %tmp1, <4 x i16>* %__b, align 8 - %tmp2 = load <4 x i16>* %__a, align 8 + %tmp2 = load <4 x i16>, <4 x i16>* %__a, align 8 %tmp3 = bitcast <4 x i16> %tmp2 to <8 x i8> - %tmp4 = load <4 x i16>* %__b, align 8 + %tmp4 = load <4 x i16>, <4 x i16>* %__b, align 8 %tmp5 = bitcast <4 x i16> %tmp4 to <8 x i8> %tmp6 = bitcast <8 x i8> %tmp3 to <4 x i16> %tmp7 = bitcast <8 x i8> %tmp5 to <4 x i16> @@ -120,13 +120,13 @@ define void @test_vext_s32() nounwind ssp { %xS32x2 = alloca <2 x i32>, align 8 %__a = alloca <2 x i32>, align 8 %__b = alloca <2 x i32>, align 8 - %tmp = load <2 x i32>* %xS32x2, align 8 + %tmp = load <2 x i32>, <2 x i32>* %xS32x2, align 8 store <2 x i32> %tmp, <2 x i32>* %__a, align 8 - %tmp1 = load <2 x i32>* %xS32x2, align 8 + %tmp1 = load <2 x i32>, <2 x i32>* %xS32x2, align 8 store <2 x i32> %tmp1, <2 x i32>* %__b, align 8 - %tmp2 = load <2 x i32>* %__a, align 8 + %tmp2 = load <2 x i32>, <2 x i32>* %__a, align 8 %tmp3 = bitcast <2 x i32> %tmp2 to <8 x i8> - %tmp4 = load <2 x i32>* %__b, align 8 + %tmp4 = load <2 x i32>, <2 x i32>* %__b, align 8 %tmp5 = bitcast <2 x i32> %tmp4 to <8 x i8> %tmp6 = bitcast <8 x i8> %tmp3 to <2 x i32> %tmp7 = bitcast <8 x i8> %tmp5 to <2 x i32> @@ -141,13 +141,13 @@ define void @test_vext_u32() nounwind ssp { %xU32x2 = alloca <2 x i32>, align 8 %__a = alloca <2 x i32>, align 8 %__b = alloca <2 x i32>, align 8 - %tmp = load <2 x i32>* %xU32x2, align 8 + %tmp = load <2 x i32>, <2 x i32>* %xU32x2, align 8 store <2 x i32> %tmp, <2 x i32>* %__a, align 8 - %tmp1 = load <2 x i32>* %xU32x2, align 8 + %tmp1 = load <2 x i32>, <2 x i32>* %xU32x2, align 8 store <2 x i32> %tmp1, <2 x i32>* %__b, align 8 - %tmp2 = load <2 x i32>* %__a, align 8 + %tmp2 = load <2 x i32>, <2 x i32>* %__a, align 8 %tmp3 = bitcast <2 x i32> %tmp2 to <8 x i8> - %tmp4 = load <2 x i32>* %__b, align 8 + %tmp4 = load <2 x i32>, <2 x i32>* %__b, align 8 %tmp5 = bitcast <2 x i32> %tmp4 to <8 x i8> %tmp6 = bitcast <8 x i8> %tmp3 to <2 x i32> %tmp7 = bitcast <8 x i8> %tmp5 to <2 x i32> @@ -162,13 +162,13 @@ define void @test_vext_f32() nounwind ssp { %xF32x2 = alloca <2 x float>, align 8 %__a = alloca <2 x float>, align 8 %__b = alloca <2 x float>, align 8 - %tmp = load <2 x float>* %xF32x2, align 8 + %tmp = load <2 x float>, <2 x float>* %xF32x2, align 8 store <2 x float> %tmp, <2 x float>* %__a, align 8 - %tmp1 = load <2 x float>* %xF32x2, align 8 + %tmp1 = load <2 x float>, <2 x float>* %xF32x2, align 8 store <2 x float> %tmp1, <2 x float>* %__b, align 8 - %tmp2 = load <2 x float>* %__a, align 8 + %tmp2 = load <2 x float>, <2 x float>* %__a, align 8 %tmp3 = bitcast <2 x float> %tmp2 to <8 x i8> - %tmp4 = load <2 x float>* %__b, align 8 + %tmp4 = load <2 x float>, <2 x float>* %__b, align 8 %tmp5 = bitcast <2 x float> %tmp4 to <8 x i8> %tmp6 = bitcast <8 x i8> %tmp3 to <2 x float> %tmp7 = bitcast <8 x i8> %tmp5 to <2 x float> @@ -184,13 +184,13 @@ define void @test_vext_s64() nounwind ssp { %xS64x1 = alloca <1 x i64>, align 8 %__a = alloca <1 x i64>, align 8 %__b = alloca <1 x i64>, align 8 - %tmp = load <1 x i64>* %xS64x1, align 8 + %tmp = load <1 x i64>, <1 x i64>* %xS64x1, align 8 store <1 x i64> %tmp, <1 x i64>* %__a, align 8 - %tmp1 = load <1 x i64>* %xS64x1, align 8 + %tmp1 = load <1 x i64>, <1 x i64>* %xS64x1, align 8 store <1 x i64> %tmp1, <1 x i64>* %__b, align 8 - %tmp2 = load <1 x i64>* %__a, align 8 + %tmp2 = load <1 x i64>, <1 x i64>* %__a, align 8 %tmp3 = bitcast <1 x i64> %tmp2 to <8 x i8> - %tmp4 = load <1 x i64>* %__b, align 8 + %tmp4 = load <1 x i64>, <1 x i64>* %__b, align 8 %tmp5 = bitcast <1 x i64> %tmp4 to <8 x i8> %tmp6 = bitcast <8 x i8> %tmp3 to <1 x i64> %tmp7 = bitcast <8 x i8> %tmp5 to <1 x i64> @@ -206,13 +206,13 @@ define void @test_vext_u64() nounwind ssp { %xU64x1 = alloca <1 x i64>, align 8 %__a = alloca <1 x i64>, align 8 %__b = alloca <1 x i64>, align 8 - %tmp = load <1 x i64>* %xU64x1, align 8 + %tmp = load <1 x i64>, <1 x i64>* %xU64x1, align 8 store <1 x i64> %tmp, <1 x i64>* %__a, align 8 - %tmp1 = load <1 x i64>* %xU64x1, align 8 + %tmp1 = load <1 x i64>, <1 x i64>* %xU64x1, align 8 store <1 x i64> %tmp1, <1 x i64>* %__b, align 8 - %tmp2 = load <1 x i64>* %__a, align 8 + %tmp2 = load <1 x i64>, <1 x i64>* %__a, align 8 %tmp3 = bitcast <1 x i64> %tmp2 to <8 x i8> - %tmp4 = load <1 x i64>* %__b, align 8 + %tmp4 = load <1 x i64>, <1 x i64>* %__b, align 8 %tmp5 = bitcast <1 x i64> %tmp4 to <8 x i8> %tmp6 = bitcast <8 x i8> %tmp3 to <1 x i64> %tmp7 = bitcast <8 x i8> %tmp5 to <1 x i64> @@ -227,12 +227,12 @@ define void @test_vextq_s8() nounwind ssp { %xS8x16 = alloca <16 x i8>, align 16 %__a = alloca <16 x i8>, align 16 %__b = alloca <16 x i8>, align 16 - %tmp = load <16 x i8>* %xS8x16, align 16 + %tmp = load <16 x i8>, <16 x i8>* %xS8x16, align 16 store <16 x i8> %tmp, <16 x i8>* %__a, align 16 - %tmp1 = load <16 x i8>* %xS8x16, align 16 + %tmp1 = load <16 x i8>, <16 x i8>* %xS8x16, align 16 store <16 x i8> %tmp1, <16 x i8>* %__b, align 16 - %tmp2 = load <16 x i8>* %__a, align 16 - %tmp3 = load <16 x i8>* %__b, align 16 + %tmp2 = load <16 x i8>, <16 x i8>* %__a, align 16 + %tmp3 = load <16 x i8>, <16 x i8>* %__b, align 16 %vext = shufflevector <16 x i8> %tmp2, <16 x i8> %tmp3, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19> store <16 x i8> %vext, <16 x i8>* %xS8x16, align 16 ret void @@ -244,12 +244,12 @@ define void @test_vextq_u8() nounwind ssp { %xU8x16 = alloca <16 x i8>, align 16 %__a = alloca <16 x i8>, align 16 %__b = alloca <16 x i8>, align 16 - %tmp = load <16 x i8>* %xU8x16, align 16 + %tmp = load <16 x i8>, <16 x i8>* %xU8x16, align 16 store <16 x i8> %tmp, <16 x i8>* %__a, align 16 - %tmp1 = load <16 x i8>* %xU8x16, align 16 + %tmp1 = load <16 x i8>, <16 x i8>* %xU8x16, align 16 store <16 x i8> %tmp1, <16 x i8>* %__b, align 16 - %tmp2 = load <16 x i8>* %__a, align 16 - %tmp3 = load <16 x i8>* %__b, align 16 + %tmp2 = load <16 x i8>, <16 x i8>* %__a, align 16 + %tmp3 = load <16 x i8>, <16 x i8>* %__b, align 16 %vext = shufflevector <16 x i8> %tmp2, <16 x i8> %tmp3, <16 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20> store <16 x i8> %vext, <16 x i8>* %xU8x16, align 16 ret void @@ -261,12 +261,12 @@ define void @test_vextq_p8() nounwind ssp { %xP8x16 = alloca <16 x i8>, align 16 %__a = alloca <16 x i8>, align 16 %__b = alloca <16 x i8>, align 16 - %tmp = load <16 x i8>* %xP8x16, align 16 + %tmp = load <16 x i8>, <16 x i8>* %xP8x16, align 16 store <16 x i8> %tmp, <16 x i8>* %__a, align 16 - %tmp1 = load <16 x i8>* %xP8x16, align 16 + %tmp1 = load <16 x i8>, <16 x i8>* %xP8x16, align 16 store <16 x i8> %tmp1, <16 x i8>* %__b, align 16 - %tmp2 = load <16 x i8>* %__a, align 16 - %tmp3 = load <16 x i8>* %__b, align 16 + %tmp2 = load <16 x i8>, <16 x i8>* %__a, align 16 + %tmp3 = load <16 x i8>, <16 x i8>* %__b, align 16 %vext = shufflevector <16 x i8> %tmp2, <16 x i8> %tmp3, <16 x i32> <i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21> store <16 x i8> %vext, <16 x i8>* %xP8x16, align 16 ret void @@ -278,13 +278,13 @@ define void @test_vextq_s16() nounwind ssp { %xS16x8 = alloca <8 x i16>, align 16 %__a = alloca <8 x i16>, align 16 %__b = alloca <8 x i16>, align 16 - %tmp = load <8 x i16>* %xS16x8, align 16 + %tmp = load <8 x i16>, <8 x i16>* %xS16x8, align 16 store <8 x i16> %tmp, <8 x i16>* %__a, align 16 - %tmp1 = load <8 x i16>* %xS16x8, align 16 + %tmp1 = load <8 x i16>, <8 x i16>* %xS16x8, align 16 store <8 x i16> %tmp1, <8 x i16>* %__b, align 16 - %tmp2 = load <8 x i16>* %__a, align 16 + %tmp2 = load <8 x i16>, <8 x i16>* %__a, align 16 %tmp3 = bitcast <8 x i16> %tmp2 to <16 x i8> - %tmp4 = load <8 x i16>* %__b, align 16 + %tmp4 = load <8 x i16>, <8 x i16>* %__b, align 16 %tmp5 = bitcast <8 x i16> %tmp4 to <16 x i8> %tmp6 = bitcast <16 x i8> %tmp3 to <8 x i16> %tmp7 = bitcast <16 x i8> %tmp5 to <8 x i16> @@ -299,13 +299,13 @@ define void @test_vextq_u16() nounwind ssp { %xU16x8 = alloca <8 x i16>, align 16 %__a = alloca <8 x i16>, align 16 %__b = alloca <8 x i16>, align 16 - %tmp = load <8 x i16>* %xU16x8, align 16 + %tmp = load <8 x i16>, <8 x i16>* %xU16x8, align 16 store <8 x i16> %tmp, <8 x i16>* %__a, align 16 - %tmp1 = load <8 x i16>* %xU16x8, align 16 + %tmp1 = load <8 x i16>, <8 x i16>* %xU16x8, align 16 store <8 x i16> %tmp1, <8 x i16>* %__b, align 16 - %tmp2 = load <8 x i16>* %__a, align 16 + %tmp2 = load <8 x i16>, <8 x i16>* %__a, align 16 %tmp3 = bitcast <8 x i16> %tmp2 to <16 x i8> - %tmp4 = load <8 x i16>* %__b, align 16 + %tmp4 = load <8 x i16>, <8 x i16>* %__b, align 16 %tmp5 = bitcast <8 x i16> %tmp4 to <16 x i8> %tmp6 = bitcast <16 x i8> %tmp3 to <8 x i16> %tmp7 = bitcast <16 x i8> %tmp5 to <8 x i16> @@ -320,13 +320,13 @@ define void @test_vextq_p16() nounwind ssp { %xP16x8 = alloca <8 x i16>, align 16 %__a = alloca <8 x i16>, align 16 %__b = alloca <8 x i16>, align 16 - %tmp = load <8 x i16>* %xP16x8, align 16 + %tmp = load <8 x i16>, <8 x i16>* %xP16x8, align 16 store <8 x i16> %tmp, <8 x i16>* %__a, align 16 - %tmp1 = load <8 x i16>* %xP16x8, align 16 + %tmp1 = load <8 x i16>, <8 x i16>* %xP16x8, align 16 store <8 x i16> %tmp1, <8 x i16>* %__b, align 16 - %tmp2 = load <8 x i16>* %__a, align 16 + %tmp2 = load <8 x i16>, <8 x i16>* %__a, align 16 %tmp3 = bitcast <8 x i16> %tmp2 to <16 x i8> - %tmp4 = load <8 x i16>* %__b, align 16 + %tmp4 = load <8 x i16>, <8 x i16>* %__b, align 16 %tmp5 = bitcast <8 x i16> %tmp4 to <16 x i8> %tmp6 = bitcast <16 x i8> %tmp3 to <8 x i16> %tmp7 = bitcast <16 x i8> %tmp5 to <8 x i16> @@ -341,13 +341,13 @@ define void @test_vextq_s32() nounwind ssp { %xS32x4 = alloca <4 x i32>, align 16 %__a = alloca <4 x i32>, align 16 %__b = alloca <4 x i32>, align 16 - %tmp = load <4 x i32>* %xS32x4, align 16 + %tmp = load <4 x i32>, <4 x i32>* %xS32x4, align 16 store <4 x i32> %tmp, <4 x i32>* %__a, align 16 - %tmp1 = load <4 x i32>* %xS32x4, align 16 + %tmp1 = load <4 x i32>, <4 x i32>* %xS32x4, align 16 store <4 x i32> %tmp1, <4 x i32>* %__b, align 16 - %tmp2 = load <4 x i32>* %__a, align 16 + %tmp2 = load <4 x i32>, <4 x i32>* %__a, align 16 %tmp3 = bitcast <4 x i32> %tmp2 to <16 x i8> - %tmp4 = load <4 x i32>* %__b, align 16 + %tmp4 = load <4 x i32>, <4 x i32>* %__b, align 16 %tmp5 = bitcast <4 x i32> %tmp4 to <16 x i8> %tmp6 = bitcast <16 x i8> %tmp3 to <4 x i32> %tmp7 = bitcast <16 x i8> %tmp5 to <4 x i32> @@ -362,13 +362,13 @@ define void @test_vextq_u32() nounwind ssp { %xU32x4 = alloca <4 x i32>, align 16 %__a = alloca <4 x i32>, align 16 %__b = alloca <4 x i32>, align 16 - %tmp = load <4 x i32>* %xU32x4, align 16 + %tmp = load <4 x i32>, <4 x i32>* %xU32x4, align 16 store <4 x i32> %tmp, <4 x i32>* %__a, align 16 - %tmp1 = load <4 x i32>* %xU32x4, align 16 + %tmp1 = load <4 x i32>, <4 x i32>* %xU32x4, align 16 store <4 x i32> %tmp1, <4 x i32>* %__b, align 16 - %tmp2 = load <4 x i32>* %__a, align 16 + %tmp2 = load <4 x i32>, <4 x i32>* %__a, align 16 %tmp3 = bitcast <4 x i32> %tmp2 to <16 x i8> - %tmp4 = load <4 x i32>* %__b, align 16 + %tmp4 = load <4 x i32>, <4 x i32>* %__b, align 16 %tmp5 = bitcast <4 x i32> %tmp4 to <16 x i8> %tmp6 = bitcast <16 x i8> %tmp3 to <4 x i32> %tmp7 = bitcast <16 x i8> %tmp5 to <4 x i32> @@ -383,13 +383,13 @@ define void @test_vextq_f32() nounwind ssp { %xF32x4 = alloca <4 x float>, align 16 %__a = alloca <4 x float>, align 16 %__b = alloca <4 x float>, align 16 - %tmp = load <4 x float>* %xF32x4, align 16 + %tmp = load <4 x float>, <4 x float>* %xF32x4, align 16 store <4 x float> %tmp, <4 x float>* %__a, align 16 - %tmp1 = load <4 x float>* %xF32x4, align 16 + %tmp1 = load <4 x float>, <4 x float>* %xF32x4, align 16 store <4 x float> %tmp1, <4 x float>* %__b, align 16 - %tmp2 = load <4 x float>* %__a, align 16 + %tmp2 = load <4 x float>, <4 x float>* %__a, align 16 %tmp3 = bitcast <4 x float> %tmp2 to <16 x i8> - %tmp4 = load <4 x float>* %__b, align 16 + %tmp4 = load <4 x float>, <4 x float>* %__b, align 16 %tmp5 = bitcast <4 x float> %tmp4 to <16 x i8> %tmp6 = bitcast <16 x i8> %tmp3 to <4 x float> %tmp7 = bitcast <16 x i8> %tmp5 to <4 x float> @@ -404,13 +404,13 @@ define void @test_vextq_s64() nounwind ssp { %xS64x2 = alloca <2 x i64>, align 16 %__a = alloca <2 x i64>, align 16 %__b = alloca <2 x i64>, align 16 - %tmp = load <2 x i64>* %xS64x2, align 16 + %tmp = load <2 x i64>, <2 x i64>* %xS64x2, align 16 store <2 x i64> %tmp, <2 x i64>* %__a, align 16 - %tmp1 = load <2 x i64>* %xS64x2, align 16 + %tmp1 = load <2 x i64>, <2 x i64>* %xS64x2, align 16 store <2 x i64> %tmp1, <2 x i64>* %__b, align 16 - %tmp2 = load <2 x i64>* %__a, align 16 + %tmp2 = load <2 x i64>, <2 x i64>* %__a, align 16 %tmp3 = bitcast <2 x i64> %tmp2 to <16 x i8> - %tmp4 = load <2 x i64>* %__b, align 16 + %tmp4 = load <2 x i64>, <2 x i64>* %__b, align 16 %tmp5 = bitcast <2 x i64> %tmp4 to <16 x i8> %tmp6 = bitcast <16 x i8> %tmp3 to <2 x i64> %tmp7 = bitcast <16 x i8> %tmp5 to <2 x i64> @@ -425,13 +425,13 @@ define void @test_vextq_u64() nounwind ssp { %xU64x2 = alloca <2 x i64>, align 16 %__a = alloca <2 x i64>, align 16 %__b = alloca <2 x i64>, align 16 - %tmp = load <2 x i64>* %xU64x2, align 16 + %tmp = load <2 x i64>, <2 x i64>* %xU64x2, align 16 store <2 x i64> %tmp, <2 x i64>* %__a, align 16 - %tmp1 = load <2 x i64>* %xU64x2, align 16 + %tmp1 = load <2 x i64>, <2 x i64>* %xU64x2, align 16 store <2 x i64> %tmp1, <2 x i64>* %__b, align 16 - %tmp2 = load <2 x i64>* %__a, align 16 + %tmp2 = load <2 x i64>, <2 x i64>* %__a, align 16 %tmp3 = bitcast <2 x i64> %tmp2 to <16 x i8> - %tmp4 = load <2 x i64>* %__b, align 16 + %tmp4 = load <2 x i64>, <2 x i64>* %__b, align 16 %tmp5 = bitcast <2 x i64> %tmp4 to <16 x i8> %tmp6 = bitcast <16 x i8> %tmp3 to <2 x i64> %tmp7 = bitcast <16 x i8> %tmp5 to <2 x i64> diff --git a/test/CodeGen/AArch64/arm64-vhadd.ll b/test/CodeGen/AArch64/arm64-vhadd.ll index 6178bf9..2e82b2a 100644 --- a/test/CodeGen/AArch64/arm64-vhadd.ll +++ b/test/CodeGen/AArch64/arm64-vhadd.ll @@ -3,8 +3,8 @@ define <8 x i8> @shadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: shadd8b: ;CHECK: shadd.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.shadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @shadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @shadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: shadd16b: ;CHECK: shadd.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.shadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -21,8 +21,8 @@ define <16 x i8> @shadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @shadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: shadd4h: ;CHECK: shadd.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.shadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -30,8 +30,8 @@ define <4 x i16> @shadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @shadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: shadd8h: ;CHECK: shadd.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -39,8 +39,8 @@ define <8 x i16> @shadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @shadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: shadd2s: ;CHECK: shadd.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.shadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -48,8 +48,8 @@ define <2 x i32> @shadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @shadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: shadd4s: ;CHECK: shadd.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.shadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -57,8 +57,8 @@ define <4 x i32> @shadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <8 x i8> @uhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: uhadd8b: ;CHECK: uhadd.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.uhadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -66,8 +66,8 @@ define <8 x i8> @uhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @uhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: uhadd16b: ;CHECK: uhadd.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.uhadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -75,8 +75,8 @@ define <16 x i8> @uhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @uhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: uhadd4h: ;CHECK: uhadd.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.uhadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -84,8 +84,8 @@ define <4 x i16> @uhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @uhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: uhadd8h: ;CHECK: uhadd.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -93,8 +93,8 @@ define <8 x i16> @uhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @uhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: uhadd2s: ;CHECK: uhadd.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.uhadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -102,8 +102,8 @@ define <2 x i32> @uhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @uhadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: uhadd4s: ;CHECK: uhadd.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.uhadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -127,8 +127,8 @@ declare <4 x i32> @llvm.aarch64.neon.uhadd.v4i32(<4 x i32>, <4 x i32>) nounwind define <8 x i8> @srhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: srhadd8b: ;CHECK: srhadd.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.srhadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -136,8 +136,8 @@ define <8 x i8> @srhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @srhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: srhadd16b: ;CHECK: srhadd.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.srhadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -145,8 +145,8 @@ define <16 x i8> @srhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @srhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: srhadd4h: ;CHECK: srhadd.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.srhadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -154,8 +154,8 @@ define <4 x i16> @srhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @srhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: srhadd8h: ;CHECK: srhadd.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -163,8 +163,8 @@ define <8 x i16> @srhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @srhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: srhadd2s: ;CHECK: srhadd.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.srhadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -172,8 +172,8 @@ define <2 x i32> @srhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @srhadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: srhadd4s: ;CHECK: srhadd.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.srhadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -181,8 +181,8 @@ define <4 x i32> @srhadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <8 x i8> @urhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: urhadd8b: ;CHECK: urhadd.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.urhadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -190,8 +190,8 @@ define <8 x i8> @urhadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @urhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: urhadd16b: ;CHECK: urhadd.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.urhadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -199,8 +199,8 @@ define <16 x i8> @urhadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @urhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: urhadd4h: ;CHECK: urhadd.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.urhadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -208,8 +208,8 @@ define <4 x i16> @urhadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @urhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: urhadd8h: ;CHECK: urhadd.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -217,8 +217,8 @@ define <8 x i16> @urhadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @urhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: urhadd2s: ;CHECK: urhadd.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.urhadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -226,8 +226,8 @@ define <2 x i32> @urhadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @urhadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: urhadd4s: ;CHECK: urhadd.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.urhadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } diff --git a/test/CodeGen/AArch64/arm64-vhsub.ll b/test/CodeGen/AArch64/arm64-vhsub.ll index 13bfda3..e50fd3d 100644 --- a/test/CodeGen/AArch64/arm64-vhsub.ll +++ b/test/CodeGen/AArch64/arm64-vhsub.ll @@ -3,8 +3,8 @@ define <8 x i8> @shsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: shsub8b: ;CHECK: shsub.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.shsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @shsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @shsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: shsub16b: ;CHECK: shsub.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.shsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -21,8 +21,8 @@ define <16 x i8> @shsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @shsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: shsub4h: ;CHECK: shsub.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.shsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -30,8 +30,8 @@ define <4 x i16> @shsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @shsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: shsub8h: ;CHECK: shsub.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.shsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -39,8 +39,8 @@ define <8 x i16> @shsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @shsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: shsub2s: ;CHECK: shsub.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.shsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -48,8 +48,8 @@ define <2 x i32> @shsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @shsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: shsub4s: ;CHECK: shsub.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.shsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -57,8 +57,8 @@ define <4 x i32> @shsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <8 x i8> @uhsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: uhsub8b: ;CHECK: uhsub.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.uhsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -66,8 +66,8 @@ define <8 x i8> @uhsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @uhsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: uhsub16b: ;CHECK: uhsub.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.uhsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -75,8 +75,8 @@ define <16 x i8> @uhsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @uhsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: uhsub4h: ;CHECK: uhsub.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.uhsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -84,8 +84,8 @@ define <4 x i16> @uhsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @uhsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: uhsub8h: ;CHECK: uhsub.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.uhsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -93,8 +93,8 @@ define <8 x i16> @uhsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @uhsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: uhsub2s: ;CHECK: uhsub.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.uhsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -102,8 +102,8 @@ define <2 x i32> @uhsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @uhsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: uhsub4s: ;CHECK: uhsub.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.uhsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } diff --git a/test/CodeGen/AArch64/arm64-virtual_base.ll b/test/CodeGen/AArch64/arm64-virtual_base.ll index cb95954..703d81a 100644 --- a/test/CodeGen/AArch64/arm64-virtual_base.ll +++ b/test/CodeGen/AArch64/arm64-virtual_base.ll @@ -39,9 +39,9 @@ define void @Precompute_Patch_Values(%struct.Bicubic_Patch_Struct* %Shape) { ; CHECK-NEXT: stur [[VAL2]], {{\[}}sp, #216] entry: %Control_Points = alloca [16 x [3 x double]], align 8 - %arraydecay5.3.1 = getelementptr inbounds [16 x [3 x double]]* %Control_Points, i64 0, i64 9, i64 0 + %arraydecay5.3.1 = getelementptr inbounds [16 x [3 x double]], [16 x [3 x double]]* %Control_Points, i64 0, i64 9, i64 0 %tmp14 = bitcast double* %arraydecay5.3.1 to i8* - %arraydecay11.3.1 = getelementptr inbounds %struct.Bicubic_Patch_Struct* %Shape, i64 0, i32 12, i64 1, i64 3, i64 0 + %arraydecay11.3.1 = getelementptr inbounds %struct.Bicubic_Patch_Struct, %struct.Bicubic_Patch_Struct* %Shape, i64 0, i32 12, i64 1, i64 3, i64 0 %tmp15 = bitcast double* %arraydecay11.3.1 to i8* call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp15, i64 24, i32 1, i1 false) ret void diff --git a/test/CodeGen/AArch64/arm64-vmax.ll b/test/CodeGen/AArch64/arm64-vmax.ll index 3f2c134..7e36323 100644 --- a/test/CodeGen/AArch64/arm64-vmax.ll +++ b/test/CodeGen/AArch64/arm64-vmax.ll @@ -3,8 +3,8 @@ define <8 x i8> @smax_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: smax_8b: ;CHECK: smax.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.smax.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @smax_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @smax_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: smax_16b: ;CHECK: smax.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.smax.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -21,8 +21,8 @@ define <16 x i8> @smax_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @smax_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: smax_4h: ;CHECK: smax.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.smax.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -30,8 +30,8 @@ define <4 x i16> @smax_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @smax_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: smax_8h: ;CHECK: smax.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.smax.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -39,8 +39,8 @@ define <8 x i16> @smax_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @smax_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: smax_2s: ;CHECK: smax.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -48,8 +48,8 @@ define <2 x i32> @smax_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @smax_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: smax_4s: ;CHECK: smax.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -64,8 +64,8 @@ declare <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32>, <4 x i32>) nounwind r define <8 x i8> @umax_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: umax_8b: ;CHECK: umax.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.umax.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -73,8 +73,8 @@ define <8 x i8> @umax_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @umax_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: umax_16b: ;CHECK: umax.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.umax.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -82,8 +82,8 @@ define <16 x i8> @umax_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @umax_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: umax_4h: ;CHECK: umax.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.umax.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -91,8 +91,8 @@ define <4 x i16> @umax_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @umax_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: umax_8h: ;CHECK: umax.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.umax.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -100,8 +100,8 @@ define <8 x i16> @umax_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @umax_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: umax_2s: ;CHECK: umax.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -109,8 +109,8 @@ define <2 x i32> @umax_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @umax_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: umax_4s: ;CHECK: umax.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -125,8 +125,8 @@ declare <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32>, <4 x i32>) nounwind r define <8 x i8> @smin_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: smin_8b: ;CHECK: smin.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.smin.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -134,8 +134,8 @@ define <8 x i8> @smin_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @smin_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: smin_16b: ;CHECK: smin.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.smin.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -143,8 +143,8 @@ define <16 x i8> @smin_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @smin_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: smin_4h: ;CHECK: smin.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.smin.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -152,8 +152,8 @@ define <4 x i16> @smin_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @smin_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: smin_8h: ;CHECK: smin.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.smin.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -161,8 +161,8 @@ define <8 x i16> @smin_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @smin_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: smin_2s: ;CHECK: smin.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.smin.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -170,8 +170,8 @@ define <2 x i32> @smin_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @smin_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: smin_4s: ;CHECK: smin.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -186,8 +186,8 @@ declare <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32>, <4 x i32>) nounwind r define <8 x i8> @umin_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: umin_8b: ;CHECK: umin.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.umin.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -195,8 +195,8 @@ define <8 x i8> @umin_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @umin_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: umin_16b: ;CHECK: umin.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.umin.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -204,8 +204,8 @@ define <16 x i8> @umin_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @umin_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: umin_4h: ;CHECK: umin.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.umin.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -213,8 +213,8 @@ define <4 x i16> @umin_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @umin_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: umin_8h: ;CHECK: umin.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.umin.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -222,8 +222,8 @@ define <8 x i16> @umin_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @umin_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: umin_2s: ;CHECK: umin.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -231,8 +231,8 @@ define <2 x i32> @umin_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @umin_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: umin_4s: ;CHECK: umin.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -249,8 +249,8 @@ declare <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32>, <4 x i32>) nounwind r define <8 x i8> @smaxp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: smaxp_8b: ;CHECK: smaxp.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.smaxp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -258,8 +258,8 @@ define <8 x i8> @smaxp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @smaxp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: smaxp_16b: ;CHECK: smaxp.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.smaxp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -267,8 +267,8 @@ define <16 x i8> @smaxp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @smaxp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: smaxp_4h: ;CHECK: smaxp.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.smaxp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -276,8 +276,8 @@ define <4 x i16> @smaxp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @smaxp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: smaxp_8h: ;CHECK: smaxp.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.smaxp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -285,8 +285,8 @@ define <8 x i16> @smaxp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @smaxp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: smaxp_2s: ;CHECK: smaxp.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.smaxp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -294,8 +294,8 @@ define <2 x i32> @smaxp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @smaxp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: smaxp_4s: ;CHECK: smaxp.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.smaxp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -310,8 +310,8 @@ declare <4 x i32> @llvm.aarch64.neon.smaxp.v4i32(<4 x i32>, <4 x i32>) nounwind define <8 x i8> @umaxp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: umaxp_8b: ;CHECK: umaxp.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.umaxp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -319,8 +319,8 @@ define <8 x i8> @umaxp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @umaxp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: umaxp_16b: ;CHECK: umaxp.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.umaxp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -328,8 +328,8 @@ define <16 x i8> @umaxp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @umaxp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: umaxp_4h: ;CHECK: umaxp.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.umaxp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -337,8 +337,8 @@ define <4 x i16> @umaxp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @umaxp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: umaxp_8h: ;CHECK: umaxp.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.umaxp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -346,8 +346,8 @@ define <8 x i16> @umaxp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @umaxp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: umaxp_2s: ;CHECK: umaxp.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.umaxp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -355,8 +355,8 @@ define <2 x i32> @umaxp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @umaxp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: umaxp_4s: ;CHECK: umaxp.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.umaxp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -373,8 +373,8 @@ declare <4 x i32> @llvm.aarch64.neon.umaxp.v4i32(<4 x i32>, <4 x i32>) nounwind define <8 x i8> @sminp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: sminp_8b: ;CHECK: sminp.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.sminp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -382,8 +382,8 @@ define <8 x i8> @sminp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @sminp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: sminp_16b: ;CHECK: sminp.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.sminp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -391,8 +391,8 @@ define <16 x i8> @sminp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @sminp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: sminp_4h: ;CHECK: sminp.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.sminp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -400,8 +400,8 @@ define <4 x i16> @sminp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @sminp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sminp_8h: ;CHECK: sminp.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.sminp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -409,8 +409,8 @@ define <8 x i16> @sminp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @sminp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: sminp_2s: ;CHECK: sminp.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.sminp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -418,8 +418,8 @@ define <2 x i32> @sminp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @sminp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sminp_4s: ;CHECK: sminp.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.sminp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -434,8 +434,8 @@ declare <4 x i32> @llvm.aarch64.neon.sminp.v4i32(<4 x i32>, <4 x i32>) nounwind define <8 x i8> @uminp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: uminp_8b: ;CHECK: uminp.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.uminp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -443,8 +443,8 @@ define <8 x i8> @uminp_8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <16 x i8> @uminp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: uminp_16b: ;CHECK: uminp.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.uminp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -452,8 +452,8 @@ define <16 x i8> @uminp_16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i16> @uminp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: uminp_4h: ;CHECK: uminp.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.uminp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -461,8 +461,8 @@ define <4 x i16> @uminp_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @uminp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: uminp_8h: ;CHECK: uminp.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.uminp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -470,8 +470,8 @@ define <8 x i16> @uminp_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @uminp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: uminp_2s: ;CHECK: uminp.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.uminp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -479,8 +479,8 @@ define <2 x i32> @uminp_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @uminp_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: uminp_4s: ;CHECK: uminp.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.uminp.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -495,8 +495,8 @@ declare <4 x i32> @llvm.aarch64.neon.uminp.v4i32(<4 x i32>, <4 x i32>) nounwind define <2 x float> @fmax_2s(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: fmax_2s: ;CHECK: fmax.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.aarch64.neon.fmax.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -504,8 +504,8 @@ define <2 x float> @fmax_2s(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x float> @fmax_4s(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: fmax_4s: ;CHECK: fmax.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.aarch64.neon.fmax.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } @@ -513,8 +513,8 @@ define <4 x float> @fmax_4s(<4 x float>* %A, <4 x float>* %B) nounwind { define <2 x double> @fmax_2d(<2 x double>* %A, <2 x double>* %B) nounwind { ;CHECK-LABEL: fmax_2d: ;CHECK: fmax.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B %tmp3 = call <2 x double> @llvm.aarch64.neon.fmax.v2f64(<2 x double> %tmp1, <2 x double> %tmp2) ret <2 x double> %tmp3 } @@ -526,8 +526,8 @@ declare <2 x double> @llvm.aarch64.neon.fmax.v2f64(<2 x double>, <2 x double>) n define <2 x float> @fmaxp_2s(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: fmaxp_2s: ;CHECK: fmaxp.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.aarch64.neon.fmaxp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -535,8 +535,8 @@ define <2 x float> @fmaxp_2s(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x float> @fmaxp_4s(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: fmaxp_4s: ;CHECK: fmaxp.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.aarch64.neon.fmaxp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } @@ -544,8 +544,8 @@ define <4 x float> @fmaxp_4s(<4 x float>* %A, <4 x float>* %B) nounwind { define <2 x double> @fmaxp_2d(<2 x double>* %A, <2 x double>* %B) nounwind { ;CHECK-LABEL: fmaxp_2d: ;CHECK: fmaxp.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B %tmp3 = call <2 x double> @llvm.aarch64.neon.fmaxp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2) ret <2 x double> %tmp3 } @@ -557,8 +557,8 @@ declare <2 x double> @llvm.aarch64.neon.fmaxp.v2f64(<2 x double>, <2 x double>) define <2 x float> @fmin_2s(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: fmin_2s: ;CHECK: fmin.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.aarch64.neon.fmin.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -566,8 +566,8 @@ define <2 x float> @fmin_2s(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x float> @fmin_4s(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: fmin_4s: ;CHECK: fmin.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.aarch64.neon.fmin.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } @@ -575,8 +575,8 @@ define <4 x float> @fmin_4s(<4 x float>* %A, <4 x float>* %B) nounwind { define <2 x double> @fmin_2d(<2 x double>* %A, <2 x double>* %B) nounwind { ;CHECK-LABEL: fmin_2d: ;CHECK: fmin.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B %tmp3 = call <2 x double> @llvm.aarch64.neon.fmin.v2f64(<2 x double> %tmp1, <2 x double> %tmp2) ret <2 x double> %tmp3 } @@ -588,8 +588,8 @@ declare <2 x double> @llvm.aarch64.neon.fmin.v2f64(<2 x double>, <2 x double>) n define <2 x float> @fminp_2s(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: fminp_2s: ;CHECK: fminp.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.aarch64.neon.fminp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -597,8 +597,8 @@ define <2 x float> @fminp_2s(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x float> @fminp_4s(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: fminp_4s: ;CHECK: fminp.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.aarch64.neon.fminp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } @@ -606,8 +606,8 @@ define <4 x float> @fminp_4s(<4 x float>* %A, <4 x float>* %B) nounwind { define <2 x double> @fminp_2d(<2 x double>* %A, <2 x double>* %B) nounwind { ;CHECK-LABEL: fminp_2d: ;CHECK: fminp.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B %tmp3 = call <2 x double> @llvm.aarch64.neon.fminp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2) ret <2 x double> %tmp3 } @@ -619,8 +619,8 @@ declare <2 x double> @llvm.aarch64.neon.fminp.v2f64(<2 x double>, <2 x double>) define <2 x float> @fminnmp_2s(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: fminnmp_2s: ;CHECK: fminnmp.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.aarch64.neon.fminnmp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -628,8 +628,8 @@ define <2 x float> @fminnmp_2s(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x float> @fminnmp_4s(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: fminnmp_4s: ;CHECK: fminnmp.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.aarch64.neon.fminnmp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } @@ -637,8 +637,8 @@ define <4 x float> @fminnmp_4s(<4 x float>* %A, <4 x float>* %B) nounwind { define <2 x double> @fminnmp_2d(<2 x double>* %A, <2 x double>* %B) nounwind { ;CHECK-LABEL: fminnmp_2d: ;CHECK: fminnmp.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B %tmp3 = call <2 x double> @llvm.aarch64.neon.fminnmp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2) ret <2 x double> %tmp3 } @@ -650,8 +650,8 @@ declare <2 x double> @llvm.aarch64.neon.fminnmp.v2f64(<2 x double>, <2 x double> define <2 x float> @fmaxnmp_2s(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: fmaxnmp_2s: ;CHECK: fmaxnmp.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.aarch64.neon.fmaxnmp.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -659,8 +659,8 @@ define <2 x float> @fmaxnmp_2s(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x float> @fmaxnmp_4s(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: fmaxnmp_4s: ;CHECK: fmaxnmp.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.aarch64.neon.fmaxnmp.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } @@ -668,8 +668,8 @@ define <4 x float> @fmaxnmp_4s(<4 x float>* %A, <4 x float>* %B) nounwind { define <2 x double> @fmaxnmp_2d(<2 x double>* %A, <2 x double>* %B) nounwind { ;CHECK-LABEL: fmaxnmp_2d: ;CHECK: fmaxnmp.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B %tmp3 = call <2 x double> @llvm.aarch64.neon.fmaxnmp.v2f64(<2 x double> %tmp1, <2 x double> %tmp2) ret <2 x double> %tmp3 } diff --git a/test/CodeGen/AArch64/arm64-vmul.ll b/test/CodeGen/AArch64/arm64-vmul.ll index 6fa60fe..3df847e 100644 --- a/test/CodeGen/AArch64/arm64-vmul.ll +++ b/test/CodeGen/AArch64/arm64-vmul.ll @@ -4,8 +4,8 @@ define <8 x i16> @smull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: smull8h: ;CHECK: smull.8h - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i16> %tmp3 } @@ -13,8 +13,8 @@ define <8 x i16> @smull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @smull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: smull4s: ;CHECK: smull.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i32> %tmp3 } @@ -22,8 +22,8 @@ define <4 x i32> @smull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @smull2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: smull2d: ;CHECK: smull.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i64> %tmp3 } @@ -35,8 +35,8 @@ declare <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32>, <2 x i32>) nounwind define <8 x i16> @umull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: umull8h: ;CHECK: umull.8h - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i16> %tmp3 } @@ -44,8 +44,8 @@ define <8 x i16> @umull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @umull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: umull4s: ;CHECK: umull.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i32> %tmp3 } @@ -53,8 +53,8 @@ define <4 x i32> @umull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @umull2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: umull2d: ;CHECK: umull.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i64> %tmp3 } @@ -66,8 +66,8 @@ declare <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32>, <2 x i32>) nounwind define <4 x i32> @sqdmull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: sqdmull4s: ;CHECK: sqdmull.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i32> %tmp3 } @@ -75,8 +75,8 @@ define <4 x i32> @sqdmull4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @sqdmull2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: sqdmull2d: ;CHECK: sqdmull.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i64> %tmp3 } @@ -84,8 +84,8 @@ define <2 x i64> @sqdmull2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @sqdmull2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sqdmull2_4s: ;CHECK: sqdmull2.4s - %load1 = load <8 x i16>* %A - %load2 = load <8 x i16>* %B + %load1 = load <8 x i16>, <8 x i16>* %A + %load2 = load <8 x i16>, <8 x i16>* %B %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) @@ -95,8 +95,8 @@ define <4 x i32> @sqdmull2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @sqdmull2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sqdmull2_2d: ;CHECK: sqdmull2.2d - %load1 = load <4 x i32>* %A - %load2 = load <4 x i32>* %B + %load1 = load <4 x i32>, <4 x i32>* %A + %load2 = load <4 x i32>, <4 x i32>* %B %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) @@ -110,8 +110,8 @@ declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>) nounwin define <8 x i16> @pmull8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: pmull8h: ;CHECK: pmull.8h - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i16> %tmp3 } @@ -121,8 +121,8 @@ declare <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8>, <8 x i8>) nounwind re define <4 x i16> @sqdmulh_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: sqdmulh_4h: ;CHECK: sqdmulh.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -130,8 +130,8 @@ define <4 x i16> @sqdmulh_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @sqdmulh_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sqdmulh_8h: ;CHECK: sqdmulh.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -139,8 +139,8 @@ define <8 x i16> @sqdmulh_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @sqdmulh_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: sqdmulh_2s: ;CHECK: sqdmulh.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -148,8 +148,8 @@ define <2 x i32> @sqdmulh_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @sqdmulh_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sqdmulh_4s: ;CHECK: sqdmulh.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -157,8 +157,8 @@ define <4 x i32> @sqdmulh_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define i32 @sqdmulh_1s(i32* %A, i32* %B) nounwind { ;CHECK-LABEL: sqdmulh_1s: ;CHECK: sqdmulh s0, {{s[0-9]+}}, {{s[0-9]+}} - %tmp1 = load i32* %A - %tmp2 = load i32* %B + %tmp1 = load i32, i32* %A + %tmp2 = load i32, i32* %B %tmp3 = call i32 @llvm.aarch64.neon.sqdmulh.i32(i32 %tmp1, i32 %tmp2) ret i32 %tmp3 } @@ -172,8 +172,8 @@ declare i32 @llvm.aarch64.neon.sqdmulh.i32(i32, i32) nounwind readnone define <4 x i16> @sqrdmulh_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: sqrdmulh_4h: ;CHECK: sqrdmulh.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -181,8 +181,8 @@ define <4 x i16> @sqrdmulh_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <8 x i16> @sqrdmulh_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sqrdmulh_8h: ;CHECK: sqrdmulh.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -190,8 +190,8 @@ define <8 x i16> @sqrdmulh_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i32> @sqrdmulh_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: sqrdmulh_2s: ;CHECK: sqrdmulh.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -199,8 +199,8 @@ define <2 x i32> @sqrdmulh_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <4 x i32> @sqrdmulh_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sqrdmulh_4s: ;CHECK: sqrdmulh.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -208,8 +208,8 @@ define <4 x i32> @sqrdmulh_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define i32 @sqrdmulh_1s(i32* %A, i32* %B) nounwind { ;CHECK-LABEL: sqrdmulh_1s: ;CHECK: sqrdmulh s0, {{s[0-9]+}}, {{s[0-9]+}} - %tmp1 = load i32* %A - %tmp2 = load i32* %B + %tmp1 = load i32, i32* %A + %tmp2 = load i32, i32* %B %tmp3 = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %tmp1, i32 %tmp2) ret i32 %tmp3 } @@ -223,8 +223,8 @@ declare i32 @llvm.aarch64.neon.sqrdmulh.i32(i32, i32) nounwind readnone define <2 x float> @fmulx_2s(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: fmulx_2s: ;CHECK: fmulx.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -232,8 +232,8 @@ define <2 x float> @fmulx_2s(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x float> @fmulx_4s(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: fmulx_4s: ;CHECK: fmulx.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } @@ -241,8 +241,8 @@ define <4 x float> @fmulx_4s(<4 x float>* %A, <4 x float>* %B) nounwind { define <2 x double> @fmulx_2d(<2 x double>* %A, <2 x double>* %B) nounwind { ;CHECK-LABEL: fmulx_2d: ;CHECK: fmulx.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B %tmp3 = call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> %tmp1, <2 x double> %tmp2) ret <2 x double> %tmp3 } @@ -254,9 +254,9 @@ declare <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double>, <2 x double>) define <4 x i32> @smlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: smlal4s: ;CHECK: smlal.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) %tmp5 = add <4 x i32> %tmp3, %tmp4 ret <4 x i32> %tmp5 @@ -265,9 +265,9 @@ define <4 x i32> @smlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind define <2 x i64> @smlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: smlal2d: ;CHECK: smlal.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i64>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp4 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) %tmp5 = add <2 x i64> %tmp3, %tmp4 ret <2 x i64> %tmp5 @@ -276,9 +276,9 @@ define <2 x i64> @smlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind define <4 x i32> @smlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: smlsl4s: ;CHECK: smlsl.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) %tmp5 = sub <4 x i32> %tmp3, %tmp4 ret <4 x i32> %tmp5 @@ -287,9 +287,9 @@ define <4 x i32> @smlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind define <2 x i64> @smlsl2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: smlsl2d: ;CHECK: smlsl.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i64>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp4 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) %tmp5 = sub <2 x i64> %tmp3, %tmp4 ret <2 x i64> %tmp5 @@ -303,9 +303,9 @@ declare <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>) define <4 x i32> @sqdmlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: sqdmlal4s: ;CHECK: sqdmlal.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4) ret <4 x i32> %tmp5 @@ -314,9 +314,9 @@ define <4 x i32> @sqdmlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwin define <2 x i64> @sqdmlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: sqdmlal2d: ;CHECK: sqdmlal.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i64>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4) ret <2 x i64> %tmp5 @@ -325,9 +325,9 @@ define <2 x i64> @sqdmlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwin define <4 x i32> @sqdmlal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: sqdmlal2_4s: ;CHECK: sqdmlal2.4s - %load1 = load <8 x i16>* %A - %load2 = load <8 x i16>* %B - %tmp3 = load <4 x i32>* %C + %load1 = load <8 x i16>, <8 x i16>* %A + %load2 = load <8 x i16>, <8 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) @@ -338,9 +338,9 @@ define <4 x i32> @sqdmlal2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounw define <2 x i64> @sqdmlal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: sqdmlal2_2d: ;CHECK: sqdmlal2.2d - %load1 = load <4 x i32>* %A - %load2 = load <4 x i32>* %B - %tmp3 = load <2 x i64>* %C + %load1 = load <4 x i32>, <4 x i32>* %A + %load2 = load <4 x i32>, <4 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) @@ -351,9 +351,9 @@ define <2 x i64> @sqdmlal2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounw define <4 x i32> @sqdmlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: sqdmlsl4s: ;CHECK: sqdmlsl.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp4) ret <4 x i32> %tmp5 @@ -362,9 +362,9 @@ define <4 x i32> @sqdmlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwin define <2 x i64> @sqdmlsl2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: sqdmlsl2d: ;CHECK: sqdmlsl.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i64>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp4) ret <2 x i64> %tmp5 @@ -373,9 +373,9 @@ define <2 x i64> @sqdmlsl2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwin define <4 x i32> @sqdmlsl2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: sqdmlsl2_4s: ;CHECK: sqdmlsl2.4s - %load1 = load <8 x i16>* %A - %load2 = load <8 x i16>* %B - %tmp3 = load <4 x i32>* %C + %load1 = load <8 x i16>, <8 x i16>* %A + %load2 = load <8 x i16>, <8 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) @@ -386,9 +386,9 @@ define <4 x i32> @sqdmlsl2_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) nounw define <2 x i64> @sqdmlsl2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: sqdmlsl2_2d: ;CHECK: sqdmlsl2.2d - %load1 = load <4 x i32>* %A - %load2 = load <4 x i32>* %B - %tmp3 = load <2 x i64>* %C + %load1 = load <4 x i32>, <4 x i32>* %A + %load2 = load <4 x i32>, <4 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) @@ -399,9 +399,9 @@ define <2 x i64> @sqdmlsl2_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) nounw define <4 x i32> @umlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: umlal4s: ;CHECK: umlal.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) %tmp5 = add <4 x i32> %tmp3, %tmp4 ret <4 x i32> %tmp5 @@ -410,9 +410,9 @@ define <4 x i32> @umlal4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind define <2 x i64> @umlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: umlal2d: ;CHECK: umlal.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i64>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp4 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) %tmp5 = add <2 x i64> %tmp3, %tmp4 ret <2 x i64> %tmp5 @@ -421,9 +421,9 @@ define <2 x i64> @umlal2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind define <4 x i32> @umlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind { ;CHECK-LABEL: umlsl4s: ;CHECK: umlsl.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) %tmp5 = sub <4 x i32> %tmp3, %tmp4 ret <4 x i32> %tmp5 @@ -432,9 +432,9 @@ define <4 x i32> @umlsl4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nounwind define <2 x i64> @umlsl2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind { ;CHECK-LABEL: umlsl2d: ;CHECK: umlsl.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i64>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp4 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) %tmp5 = sub <2 x i64> %tmp3, %tmp4 ret <2 x i64> %tmp5 @@ -443,9 +443,9 @@ define <2 x i64> @umlsl2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nounwind define <2 x float> @fmla_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind { ;CHECK-LABEL: fmla_2s: ;CHECK: fmla.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B - %tmp3 = load <2 x float>* %C + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B + %tmp3 = load <2 x float>, <2 x float>* %C %tmp4 = call <2 x float> @llvm.fma.v2f32(<2 x float> %tmp1, <2 x float> %tmp2, <2 x float> %tmp3) ret <2 x float> %tmp4 } @@ -453,9 +453,9 @@ define <2 x float> @fmla_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) n define <4 x float> @fmla_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind { ;CHECK-LABEL: fmla_4s: ;CHECK: fmla.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B - %tmp3 = load <4 x float>* %C + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B + %tmp3 = load <4 x float>, <4 x float>* %C %tmp4 = call <4 x float> @llvm.fma.v4f32(<4 x float> %tmp1, <4 x float> %tmp2, <4 x float> %tmp3) ret <4 x float> %tmp4 } @@ -463,9 +463,9 @@ define <4 x float> @fmla_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) n define <2 x double> @fmla_2d(<2 x double>* %A, <2 x double>* %B, <2 x double>* %C) nounwind { ;CHECK-LABEL: fmla_2d: ;CHECK: fmla.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B - %tmp3 = load <2 x double>* %C + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B + %tmp3 = load <2 x double>, <2 x double>* %C %tmp4 = call <2 x double> @llvm.fma.v2f64(<2 x double> %tmp1, <2 x double> %tmp2, <2 x double> %tmp3) ret <2 x double> %tmp4 } @@ -477,9 +477,9 @@ declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) n define <2 x float> @fmls_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind { ;CHECK-LABEL: fmls_2s: ;CHECK: fmls.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B - %tmp3 = load <2 x float>* %C + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B + %tmp3 = load <2 x float>, <2 x float>* %C %tmp4 = fsub <2 x float> <float -0.0, float -0.0>, %tmp2 %tmp5 = call <2 x float> @llvm.fma.v2f32(<2 x float> %tmp1, <2 x float> %tmp4, <2 x float> %tmp3) ret <2 x float> %tmp5 @@ -488,9 +488,9 @@ define <2 x float> @fmls_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) n define <4 x float> @fmls_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind { ;CHECK-LABEL: fmls_4s: ;CHECK: fmls.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B - %tmp3 = load <4 x float>* %C + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B + %tmp3 = load <4 x float>, <4 x float>* %C %tmp4 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %tmp2 %tmp5 = call <4 x float> @llvm.fma.v4f32(<4 x float> %tmp1, <4 x float> %tmp4, <4 x float> %tmp3) ret <4 x float> %tmp5 @@ -499,9 +499,9 @@ define <4 x float> @fmls_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) n define <2 x double> @fmls_2d(<2 x double>* %A, <2 x double>* %B, <2 x double>* %C) nounwind { ;CHECK-LABEL: fmls_2d: ;CHECK: fmls.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B - %tmp3 = load <2 x double>* %C + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B + %tmp3 = load <2 x double>, <2 x double>* %C %tmp4 = fsub <2 x double> <double -0.0, double -0.0>, %tmp2 %tmp5 = call <2 x double> @llvm.fma.v2f64(<2 x double> %tmp1, <2 x double> %tmp4, <2 x double> %tmp3) ret <2 x double> %tmp5 @@ -510,9 +510,9 @@ define <2 x double> @fmls_2d(<2 x double>* %A, <2 x double>* %B, <2 x double>* % define <2 x float> @fmls_commuted_neg_2s(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind { ;CHECK-LABEL: fmls_commuted_neg_2s: ;CHECK: fmls.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B - %tmp3 = load <2 x float>* %C + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B + %tmp3 = load <2 x float>, <2 x float>* %C %tmp4 = fsub <2 x float> <float -0.0, float -0.0>, %tmp2 %tmp5 = call <2 x float> @llvm.fma.v2f32(<2 x float> %tmp4, <2 x float> %tmp1, <2 x float> %tmp3) ret <2 x float> %tmp5 @@ -521,9 +521,9 @@ define <2 x float> @fmls_commuted_neg_2s(<2 x float>* %A, <2 x float>* %B, <2 x define <4 x float> @fmls_commuted_neg_4s(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind { ;CHECK-LABEL: fmls_commuted_neg_4s: ;CHECK: fmls.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B - %tmp3 = load <4 x float>* %C + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B + %tmp3 = load <4 x float>, <4 x float>* %C %tmp4 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %tmp2 %tmp5 = call <4 x float> @llvm.fma.v4f32(<4 x float> %tmp4, <4 x float> %tmp1, <4 x float> %tmp3) ret <4 x float> %tmp5 @@ -532,9 +532,9 @@ define <4 x float> @fmls_commuted_neg_4s(<4 x float>* %A, <4 x float>* %B, <4 x define <2 x double> @fmls_commuted_neg_2d(<2 x double>* %A, <2 x double>* %B, <2 x double>* %C) nounwind { ;CHECK-LABEL: fmls_commuted_neg_2d: ;CHECK: fmls.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B - %tmp3 = load <2 x double>* %C + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B + %tmp3 = load <2 x double>, <2 x double>* %C %tmp4 = fsub <2 x double> <double -0.0, double -0.0>, %tmp2 %tmp5 = call <2 x double> @llvm.fma.v2f64(<2 x double> %tmp4, <2 x double> %tmp1, <2 x double> %tmp3) ret <2 x double> %tmp5 @@ -609,8 +609,8 @@ define <4 x i16> @mul_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: mul_4h: ;CHECK-NOT: dup ;CHECK: mul.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp4 = mul <4 x i16> %tmp1, %tmp3 ret <4 x i16> %tmp4 @@ -620,8 +620,8 @@ define <8 x i16> @mul_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: mul_8h: ;CHECK-NOT: dup ;CHECK: mul.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp2, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %tmp4 = mul <8 x i16> %tmp1, %tmp3 ret <8 x i16> %tmp4 @@ -631,8 +631,8 @@ define <2 x i32> @mul_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: mul_2s: ;CHECK-NOT: dup ;CHECK: mul.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1> %tmp4 = mul <2 x i32> %tmp1, %tmp3 ret <2 x i32> %tmp4 @@ -642,8 +642,8 @@ define <4 x i32> @mul_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: mul_4s: ;CHECK-NOT: dup ;CHECK: mul.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = shufflevector <4 x i32> %tmp2, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp4 = mul <4 x i32> %tmp1, %tmp3 ret <4 x i32> %tmp4 @@ -661,8 +661,8 @@ define <2 x float> @fmul_lane_2s(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: fmul_lane_2s: ;CHECK-NOT: dup ;CHECK: fmul.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = shufflevector <2 x float> %tmp2, <2 x float> %tmp2, <2 x i32> <i32 1, i32 1> %tmp4 = fmul <2 x float> %tmp1, %tmp3 ret <2 x float> %tmp4 @@ -672,8 +672,8 @@ define <4 x float> @fmul_lane_4s(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: fmul_lane_4s: ;CHECK-NOT: dup ;CHECK: fmul.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = shufflevector <4 x float> %tmp2, <4 x float> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp4 = fmul <4 x float> %tmp1, %tmp3 ret <4 x float> %tmp4 @@ -683,8 +683,8 @@ define <2 x double> @fmul_lane_2d(<2 x double>* %A, <2 x double>* %B) nounwind { ;CHECK-LABEL: fmul_lane_2d: ;CHECK-NOT: dup ;CHECK: fmul.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B %tmp3 = shufflevector <2 x double> %tmp2, <2 x double> %tmp2, <2 x i32> <i32 1, i32 1> %tmp4 = fmul <2 x double> %tmp1, %tmp3 ret <2 x double> %tmp4 @@ -714,8 +714,8 @@ define <2 x float> @fmulx_lane_2s(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: fmulx_lane_2s: ;CHECK-NOT: dup ;CHECK: fmulx.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = shufflevector <2 x float> %tmp2, <2 x float> %tmp2, <2 x i32> <i32 1, i32 1> %tmp4 = call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> %tmp1, <2 x float> %tmp3) ret <2 x float> %tmp4 @@ -725,8 +725,8 @@ define <4 x float> @fmulx_lane_4s(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: fmulx_lane_4s: ;CHECK-NOT: dup ;CHECK: fmulx.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = shufflevector <4 x float> %tmp2, <4 x float> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp4 = call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> %tmp1, <4 x float> %tmp3) ret <4 x float> %tmp4 @@ -736,8 +736,8 @@ define <2 x double> @fmulx_lane_2d(<2 x double>* %A, <2 x double>* %B) nounwind ;CHECK-LABEL: fmulx_lane_2d: ;CHECK-NOT: dup ;CHECK: fmulx.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B %tmp3 = shufflevector <2 x double> %tmp2, <2 x double> %tmp2, <2 x i32> <i32 1, i32 1> %tmp4 = call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> %tmp1, <2 x double> %tmp3) ret <2 x double> %tmp4 @@ -747,8 +747,8 @@ define <4 x i16> @sqdmulh_lane_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: sqdmulh_lane_4h: ;CHECK-NOT: dup ;CHECK: sqdmulh.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp4 = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp3) ret <4 x i16> %tmp4 @@ -758,8 +758,8 @@ define <8 x i16> @sqdmulh_lane_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sqdmulh_lane_8h: ;CHECK-NOT: dup ;CHECK: sqdmulh.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp2, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %tmp4 = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp3) ret <8 x i16> %tmp4 @@ -769,8 +769,8 @@ define <2 x i32> @sqdmulh_lane_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: sqdmulh_lane_2s: ;CHECK-NOT: dup ;CHECK: sqdmulh.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1> %tmp4 = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp3) ret <2 x i32> %tmp4 @@ -780,8 +780,8 @@ define <4 x i32> @sqdmulh_lane_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sqdmulh_lane_4s: ;CHECK-NOT: dup ;CHECK: sqdmulh.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = shufflevector <4 x i32> %tmp2, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp3) ret <4 x i32> %tmp4 @@ -800,8 +800,8 @@ define <4 x i16> @sqrdmulh_lane_4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: sqrdmulh_lane_4h: ;CHECK-NOT: dup ;CHECK: sqrdmulh.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp4 = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp3) ret <4 x i16> %tmp4 @@ -811,8 +811,8 @@ define <8 x i16> @sqrdmulh_lane_8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sqrdmulh_lane_8h: ;CHECK-NOT: dup ;CHECK: sqrdmulh.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp2, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %tmp4 = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp3) ret <8 x i16> %tmp4 @@ -822,8 +822,8 @@ define <2 x i32> @sqrdmulh_lane_2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: sqrdmulh_lane_2s: ;CHECK-NOT: dup ;CHECK: sqrdmulh.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1> %tmp4 = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp3) ret <2 x i32> %tmp4 @@ -833,8 +833,8 @@ define <4 x i32> @sqrdmulh_lane_4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sqrdmulh_lane_4s: ;CHECK-NOT: dup ;CHECK: sqrdmulh.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = shufflevector <4 x i32> %tmp2, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp3) ret <4 x i32> %tmp4 @@ -853,8 +853,8 @@ define <4 x i32> @sqdmull_lane_4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: sqdmull_lane_4s: ;CHECK-NOT: dup ;CHECK: sqdmull.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3) ret <4 x i32> %tmp4 @@ -864,8 +864,8 @@ define <2 x i64> @sqdmull_lane_2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: sqdmull_lane_2d: ;CHECK-NOT: dup ;CHECK: sqdmull.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1> %tmp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3) ret <2 x i64> %tmp4 @@ -875,8 +875,8 @@ define <4 x i32> @sqdmull2_lane_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sqdmull2_lane_4s: ;CHECK-NOT: dup ;CHECK: sqdmull2.4s - %load1 = load <8 x i16>* %A - %load2 = load <8 x i16>* %B + %load1 = load <8 x i16>, <8 x i16>* %A + %load2 = load <8 x i16>, <8 x i16>* %B %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) @@ -887,8 +887,8 @@ define <2 x i64> @sqdmull2_lane_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sqdmull2_lane_2d: ;CHECK-NOT: dup ;CHECK: sqdmull2.2d - %load1 = load <4 x i32>* %A - %load2 = load <4 x i32>* %B + %load1 = load <4 x i32>, <4 x i32>* %A + %load2 = load <4 x i32>, <4 x i32>* %B %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 1, i32 1> %tmp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) @@ -899,8 +899,8 @@ define <4 x i32> @umull_lane_4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: umull_lane_4s: ;CHECK-NOT: dup ;CHECK: umull.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp4 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3) ret <4 x i32> %tmp4 @@ -910,8 +910,8 @@ define <2 x i64> @umull_lane_2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: umull_lane_2d: ;CHECK-NOT: dup ;CHECK: umull.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1> %tmp4 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3) ret <2 x i64> %tmp4 @@ -921,8 +921,8 @@ define <4 x i32> @smull_lane_4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: smull_lane_4s: ;CHECK-NOT: dup ;CHECK: smull.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp4 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp3) ret <4 x i32> %tmp4 @@ -932,8 +932,8 @@ define <2 x i64> @smull_lane_2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: smull_lane_2d: ;CHECK-NOT: dup ;CHECK: smull.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1> %tmp4 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp3) ret <2 x i64> %tmp4 @@ -943,9 +943,9 @@ define <4 x i32> @smlal_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nou ;CHECK-LABEL: smlal_lane_4s: ;CHECK-NOT: dup ;CHECK: smlal.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp5 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4) %tmp6 = add <4 x i32> %tmp3, %tmp5 @@ -956,9 +956,9 @@ define <2 x i64> @smlal_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nou ;CHECK-LABEL: smlal_lane_2d: ;CHECK-NOT: dup ;CHECK: smlal.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i64>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1> %tmp5 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4) %tmp6 = add <2 x i64> %tmp3, %tmp5 @@ -969,9 +969,9 @@ define <4 x i32> @sqdmlal_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) n ;CHECK-LABEL: sqdmlal_lane_4s: ;CHECK-NOT: dup ;CHECK: sqdmlal.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4) %tmp6 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp5) @@ -982,9 +982,9 @@ define <2 x i64> @sqdmlal_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) n ;CHECK-LABEL: sqdmlal_lane_2d: ;CHECK-NOT: dup ;CHECK: sqdmlal.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i64>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1> %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4) %tmp6 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp5) @@ -995,9 +995,9 @@ define <4 x i32> @sqdmlal2_lane_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) ;CHECK-LABEL: sqdmlal2_lane_4s: ;CHECK-NOT: dup ;CHECK: sqdmlal2.4s - %load1 = load <8 x i16>* %A - %load2 = load <8 x i16>* %B - %tmp3 = load <4 x i32>* %C + %load1 = load <8 x i16>, <8 x i16>* %A + %load2 = load <8 x i16>, <8 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) @@ -1009,9 +1009,9 @@ define <2 x i64> @sqdmlal2_lane_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) ;CHECK-LABEL: sqdmlal2_lane_2d: ;CHECK-NOT: dup ;CHECK: sqdmlal2.2d - %load1 = load <4 x i32>* %A - %load2 = load <4 x i32>* %B - %tmp3 = load <2 x i64>* %C + %load1 = load <4 x i32>, <4 x i32>* %A + %load2 = load <4 x i32>, <4 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 1, i32 1> %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) @@ -1069,9 +1069,9 @@ define <4 x i32> @umlal_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nou ;CHECK-LABEL: umlal_lane_4s: ;CHECK-NOT: dup ;CHECK: umlal.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp5 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4) %tmp6 = add <4 x i32> %tmp3, %tmp5 @@ -1082,9 +1082,9 @@ define <2 x i64> @umlal_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nou ;CHECK-LABEL: umlal_lane_2d: ;CHECK-NOT: dup ;CHECK: umlal.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i64>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1> %tmp5 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4) %tmp6 = add <2 x i64> %tmp3, %tmp5 @@ -1096,9 +1096,9 @@ define <4 x i32> @smlsl_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nou ;CHECK-LABEL: smlsl_lane_4s: ;CHECK-NOT: dup ;CHECK: smlsl.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp5 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4) %tmp6 = sub <4 x i32> %tmp3, %tmp5 @@ -1109,9 +1109,9 @@ define <2 x i64> @smlsl_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nou ;CHECK-LABEL: smlsl_lane_2d: ;CHECK-NOT: dup ;CHECK: smlsl.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i64>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1> %tmp5 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4) %tmp6 = sub <2 x i64> %tmp3, %tmp5 @@ -1122,9 +1122,9 @@ define <4 x i32> @sqdmlsl_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) n ;CHECK-LABEL: sqdmlsl_lane_4s: ;CHECK-NOT: dup ;CHECK: sqdmlsl.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4) %tmp6 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %tmp3, <4 x i32> %tmp5) @@ -1135,9 +1135,9 @@ define <2 x i64> @sqdmlsl_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) n ;CHECK-LABEL: sqdmlsl_lane_2d: ;CHECK-NOT: dup ;CHECK: sqdmlsl.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i64>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1> %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4) %tmp6 = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %tmp3, <2 x i64> %tmp5) @@ -1148,9 +1148,9 @@ define <4 x i32> @sqdmlsl2_lane_4s(<8 x i16>* %A, <8 x i16>* %B, <4 x i32>* %C) ;CHECK-LABEL: sqdmlsl2_lane_4s: ;CHECK-NOT: dup ;CHECK: sqdmlsl2.4s - %load1 = load <8 x i16>* %A - %load2 = load <8 x i16>* %B - %tmp3 = load <4 x i32>* %C + %load1 = load <8 x i16>, <8 x i16>* %A + %load2 = load <8 x i16>, <8 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp5 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) @@ -1162,9 +1162,9 @@ define <2 x i64> @sqdmlsl2_lane_2d(<4 x i32>* %A, <4 x i32>* %B, <2 x i64>* %C) ;CHECK-LABEL: sqdmlsl2_lane_2d: ;CHECK-NOT: dup ;CHECK: sqdmlsl2.2d - %load1 = load <4 x i32>* %A - %load2 = load <4 x i32>* %B - %tmp3 = load <2 x i64>* %C + %load1 = load <4 x i32>, <4 x i32>* %A + %load2 = load <4 x i32>, <4 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 1, i32 1> %tmp5 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) @@ -1176,9 +1176,9 @@ define <4 x i32> @umlsl_lane_4s(<4 x i16>* %A, <4 x i16>* %B, <4 x i32>* %C) nou ;CHECK-LABEL: umlsl_lane_4s: ;CHECK-NOT: dup ;CHECK: umlsl.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i32>* %C + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B + %tmp3 = load <4 x i32>, <4 x i32>* %C %tmp4 = shufflevector <4 x i16> %tmp2, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp5 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp4) %tmp6 = sub <4 x i32> %tmp3, %tmp5 @@ -1189,9 +1189,9 @@ define <2 x i64> @umlsl_lane_2d(<2 x i32>* %A, <2 x i32>* %B, <2 x i64>* %C) nou ;CHECK-LABEL: umlsl_lane_2d: ;CHECK-NOT: dup ;CHECK: umlsl.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i64>* %C + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B + %tmp3 = load <2 x i64>, <2 x i64>* %C %tmp4 = shufflevector <2 x i32> %tmp2, <2 x i32> %tmp2, <2 x i32> <i32 1, i32 1> %tmp5 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp4) %tmp6 = sub <2 x i64> %tmp3, %tmp5 diff --git a/test/CodeGen/AArch64/arm64-volatile.ll b/test/CodeGen/AArch64/arm64-volatile.ll index e00ac5a..28facb6 100644 --- a/test/CodeGen/AArch64/arm64-volatile.ll +++ b/test/CodeGen/AArch64/arm64-volatile.ll @@ -4,10 +4,10 @@ define i64 @normal_load(i64* nocapture %bar) nounwind readonly { ; CHECK: ldp ; CHECK-NEXT: add ; CHECK-NEXT: ret - %add.ptr = getelementptr inbounds i64* %bar, i64 1 - %tmp = load i64* %add.ptr, align 8 - %add.ptr1 = getelementptr inbounds i64* %bar, i64 2 - %tmp1 = load i64* %add.ptr1, align 8 + %add.ptr = getelementptr inbounds i64, i64* %bar, i64 1 + %tmp = load i64, i64* %add.ptr, align 8 + %add.ptr1 = getelementptr inbounds i64, i64* %bar, i64 2 + %tmp1 = load i64, i64* %add.ptr1, align 8 %add = add nsw i64 %tmp1, %tmp ret i64 %add } @@ -18,10 +18,10 @@ define i64 @volatile_load(i64* nocapture %bar) nounwind { ; CHECK-NEXT: ldr ; CHECK-NEXT: add ; CHECK-NEXT: ret - %add.ptr = getelementptr inbounds i64* %bar, i64 1 - %tmp = load volatile i64* %add.ptr, align 8 - %add.ptr1 = getelementptr inbounds i64* %bar, i64 2 - %tmp1 = load volatile i64* %add.ptr1, align 8 + %add.ptr = getelementptr inbounds i64, i64* %bar, i64 1 + %tmp = load volatile i64, i64* %add.ptr, align 8 + %add.ptr1 = getelementptr inbounds i64, i64* %bar, i64 2 + %tmp1 = load volatile i64, i64* %add.ptr1, align 8 %add = add nsw i64 %tmp1, %tmp ret i64 %add } diff --git a/test/CodeGen/AArch64/arm64-vqadd.ll b/test/CodeGen/AArch64/arm64-vqadd.ll index 20f7e2c..9932899 100644 --- a/test/CodeGen/AArch64/arm64-vqadd.ll +++ b/test/CodeGen/AArch64/arm64-vqadd.ll @@ -3,8 +3,8 @@ define <8 x i8> @sqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: sqadd8b: ;CHECK: sqadd.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @sqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @sqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: sqadd4h: ;CHECK: sqadd.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @sqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @sqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: sqadd2s: ;CHECK: sqadd.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @sqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i8> @uqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: uqadd8b: ;CHECK: uqadd.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -39,8 +39,8 @@ define <8 x i8> @uqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @uqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: uqadd4h: ;CHECK: uqadd.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -48,8 +48,8 @@ define <4 x i16> @uqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @uqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: uqadd2s: ;CHECK: uqadd.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -57,8 +57,8 @@ define <2 x i32> @uqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @sqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: sqadd16b: ;CHECK: sqadd.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -66,8 +66,8 @@ define <16 x i8> @sqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @sqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sqadd8h: ;CHECK: sqadd.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -75,8 +75,8 @@ define <8 x i16> @sqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @sqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sqadd4s: ;CHECK: sqadd.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -84,8 +84,8 @@ define <4 x i32> @sqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @sqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: sqadd2d: ;CHECK: sqadd.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -93,8 +93,8 @@ define <2 x i64> @sqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <16 x i8> @uqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: uqadd16b: ;CHECK: uqadd.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -102,8 +102,8 @@ define <16 x i8> @uqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @uqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: uqadd8h: ;CHECK: uqadd.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -111,8 +111,8 @@ define <8 x i16> @uqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @uqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: uqadd4s: ;CHECK: uqadd.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -120,8 +120,8 @@ define <4 x i32> @uqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @uqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: uqadd2d: ;CHECK: uqadd.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -149,8 +149,8 @@ declare <2 x i64> @llvm.aarch64.neon.uqadd.v2i64(<2 x i64>, <2 x i64>) nounwind define <8 x i8> @usqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: usqadd8b: ;CHECK: usqadd.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -158,8 +158,8 @@ define <8 x i8> @usqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @usqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: usqadd4h: ;CHECK: usqadd.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -167,8 +167,8 @@ define <4 x i16> @usqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @usqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: usqadd2s: ;CHECK: usqadd.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.usqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -176,8 +176,8 @@ define <2 x i32> @usqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @usqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: usqadd16b: ;CHECK: usqadd.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.usqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -185,8 +185,8 @@ define <16 x i8> @usqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @usqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: usqadd8h: ;CHECK: usqadd.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.usqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -194,8 +194,8 @@ define <8 x i16> @usqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @usqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: usqadd4s: ;CHECK: usqadd.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.usqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -203,8 +203,8 @@ define <4 x i32> @usqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @usqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: usqadd2d: ;CHECK: usqadd.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.usqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -238,8 +238,8 @@ declare <2 x i64> @llvm.aarch64.neon.usqadd.v2i64(<2 x i64>, <2 x i64>) nounwind define <8 x i8> @suqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: suqadd8b: ;CHECK: suqadd.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.suqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -247,8 +247,8 @@ define <8 x i8> @suqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @suqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: suqadd4h: ;CHECK: suqadd.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.suqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -256,8 +256,8 @@ define <4 x i16> @suqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @suqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: suqadd2s: ;CHECK: suqadd.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.suqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -265,8 +265,8 @@ define <2 x i32> @suqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @suqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: suqadd16b: ;CHECK: suqadd.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.suqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -274,8 +274,8 @@ define <16 x i8> @suqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @suqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: suqadd8h: ;CHECK: suqadd.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.suqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -283,8 +283,8 @@ define <8 x i16> @suqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @suqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: suqadd4s: ;CHECK: suqadd.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.suqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -292,8 +292,8 @@ define <4 x i32> @suqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @suqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: suqadd2d: ;CHECK: suqadd.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.suqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } diff --git a/test/CodeGen/AArch64/arm64-vqsub.ll b/test/CodeGen/AArch64/arm64-vqsub.ll index dde3ac3..4fc588d 100644 --- a/test/CodeGen/AArch64/arm64-vqsub.ll +++ b/test/CodeGen/AArch64/arm64-vqsub.ll @@ -3,8 +3,8 @@ define <8 x i8> @sqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: sqsub8b: ;CHECK: sqsub.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @sqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @sqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: sqsub4h: ;CHECK: sqsub.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @sqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @sqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: sqsub2s: ;CHECK: sqsub.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @sqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i8> @uqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: uqsub8b: ;CHECK: uqsub.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -39,8 +39,8 @@ define <8 x i8> @uqsub8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @uqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: uqsub4h: ;CHECK: uqsub.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -48,8 +48,8 @@ define <4 x i16> @uqsub4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @uqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: uqsub2s: ;CHECK: uqsub.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -57,8 +57,8 @@ define <2 x i32> @uqsub2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @sqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: sqsub16b: ;CHECK: sqsub.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -66,8 +66,8 @@ define <16 x i8> @sqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @sqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sqsub8h: ;CHECK: sqsub.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -75,8 +75,8 @@ define <8 x i16> @sqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @sqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sqsub4s: ;CHECK: sqsub.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -84,8 +84,8 @@ define <4 x i32> @sqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @sqsub2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: sqsub2d: ;CHECK: sqsub.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -93,8 +93,8 @@ define <2 x i64> @sqsub2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <16 x i8> @uqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: uqsub16b: ;CHECK: uqsub.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -102,8 +102,8 @@ define <16 x i8> @uqsub16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @uqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: uqsub8h: ;CHECK: uqsub.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -111,8 +111,8 @@ define <8 x i16> @uqsub8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @uqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: uqsub4s: ;CHECK: uqsub.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -120,8 +120,8 @@ define <4 x i32> @uqsub4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @uqsub2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: uqsub2d: ;CHECK: uqsub.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqsub.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } diff --git a/test/CodeGen/AArch64/arm64-vshift.ll b/test/CodeGen/AArch64/arm64-vshift.ll index 65bd50c..d5a1248 100644 --- a/test/CodeGen/AArch64/arm64-vshift.ll +++ b/test/CodeGen/AArch64/arm64-vshift.ll @@ -3,8 +3,8 @@ define <8 x i8> @sqshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: sqshl8b: ;CHECK: sqshl.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @sqshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @sqshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: sqshl4h: ;CHECK: sqshl.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @sqshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @sqshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: sqshl2s: ;CHECK: sqshl.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -30,8 +30,8 @@ define <2 x i32> @sqshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i8> @uqshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: uqshl8b: ;CHECK: uqshl.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -39,8 +39,8 @@ define <8 x i8> @uqshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @uqshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: uqshl4h: ;CHECK: uqshl.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -48,8 +48,8 @@ define <4 x i16> @uqshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @uqshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: uqshl2s: ;CHECK: uqshl.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -57,8 +57,8 @@ define <2 x i32> @uqshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @sqshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: sqshl16b: ;CHECK: sqshl.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -66,8 +66,8 @@ define <16 x i8> @sqshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @sqshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sqshl8h: ;CHECK: sqshl.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -75,8 +75,8 @@ define <8 x i16> @sqshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @sqshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sqshl4s: ;CHECK: sqshl.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -84,8 +84,8 @@ define <4 x i32> @sqshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @sqshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: sqshl2d: ;CHECK: sqshl.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -93,8 +93,8 @@ define <2 x i64> @sqshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <16 x i8> @uqshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: uqshl16b: ;CHECK: uqshl.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -102,8 +102,8 @@ define <16 x i8> @uqshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @uqshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: uqshl8h: ;CHECK: uqshl.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -111,8 +111,8 @@ define <8 x i16> @uqshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @uqshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: uqshl4s: ;CHECK: uqshl.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -120,8 +120,8 @@ define <4 x i32> @uqshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @uqshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: uqshl2d: ;CHECK: uqshl.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -149,8 +149,8 @@ declare <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64>, <2 x i64>) nounwind define <8 x i8> @srshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: srshl8b: ;CHECK: srshl.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -158,8 +158,8 @@ define <8 x i8> @srshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @srshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: srshl4h: ;CHECK: srshl.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -167,8 +167,8 @@ define <4 x i16> @srshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @srshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: srshl2s: ;CHECK: srshl.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -176,8 +176,8 @@ define <2 x i32> @srshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i8> @urshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: urshl8b: ;CHECK: urshl.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -185,8 +185,8 @@ define <8 x i8> @urshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @urshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: urshl4h: ;CHECK: urshl.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -194,8 +194,8 @@ define <4 x i16> @urshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @urshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: urshl2s: ;CHECK: urshl.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -203,8 +203,8 @@ define <2 x i32> @urshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @srshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: srshl16b: ;CHECK: srshl.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -212,8 +212,8 @@ define <16 x i8> @srshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @srshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: srshl8h: ;CHECK: srshl.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -221,8 +221,8 @@ define <8 x i16> @srshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @srshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: srshl4s: ;CHECK: srshl.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -230,8 +230,8 @@ define <4 x i32> @srshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @srshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: srshl2d: ;CHECK: srshl.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -239,8 +239,8 @@ define <2 x i64> @srshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <16 x i8> @urshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: urshl16b: ;CHECK: urshl.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -248,8 +248,8 @@ define <16 x i8> @urshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @urshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: urshl8h: ;CHECK: urshl.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -257,8 +257,8 @@ define <8 x i16> @urshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @urshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: urshl4s: ;CHECK: urshl.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -266,8 +266,8 @@ define <4 x i32> @urshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @urshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: urshl2d: ;CHECK: urshl.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -295,8 +295,8 @@ declare <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64>, <2 x i64>) nounwind define <8 x i8> @sqrshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: sqrshl8b: ;CHECK: sqrshl.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -304,8 +304,8 @@ define <8 x i8> @sqrshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @sqrshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: sqrshl4h: ;CHECK: sqrshl.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -313,8 +313,8 @@ define <4 x i16> @sqrshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @sqrshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: sqrshl2s: ;CHECK: sqrshl.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -322,8 +322,8 @@ define <2 x i32> @sqrshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i8> @uqrshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: uqrshl8b: ;CHECK: uqrshl.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqrshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) ret <8 x i8> %tmp3 } @@ -331,8 +331,8 @@ define <8 x i8> @uqrshl8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @uqrshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: uqrshl4h: ;CHECK: uqrshl.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqrshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) ret <4 x i16> %tmp3 } @@ -340,8 +340,8 @@ define <4 x i16> @uqrshl4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @uqrshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: uqrshl2s: ;CHECK: uqrshl.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqrshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) ret <2 x i32> %tmp3 } @@ -349,8 +349,8 @@ define <2 x i32> @uqrshl2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @sqrshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: sqrshl16b: ;CHECK: sqrshl.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqrshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -358,8 +358,8 @@ define <16 x i8> @sqrshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @sqrshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sqrshl8h: ;CHECK: sqrshl.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqrshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -367,8 +367,8 @@ define <8 x i16> @sqrshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @sqrshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sqrshl4s: ;CHECK: sqrshl.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqrshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -376,8 +376,8 @@ define <4 x i32> @sqrshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @sqrshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: sqrshl2d: ;CHECK: sqrshl.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqrshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -385,8 +385,8 @@ define <2 x i64> @sqrshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <16 x i8> @uqrshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: uqrshl16b: ;CHECK: uqrshl.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqrshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) ret <16 x i8> %tmp3 } @@ -394,8 +394,8 @@ define <16 x i8> @uqrshl16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @uqrshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: uqrshl8h: ;CHECK: uqrshl.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqrshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i16> %tmp3 } @@ -403,8 +403,8 @@ define <8 x i16> @uqrshl8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @uqrshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: uqrshl4s: ;CHECK: uqrshl.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqrshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i32> %tmp3 } @@ -412,8 +412,8 @@ define <4 x i32> @uqrshl4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @uqrshl2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: uqrshl2d: ;CHECK: uqrshl.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqrshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i64> %tmp3 } @@ -441,7 +441,7 @@ declare <2 x i64> @llvm.aarch64.neon.uqrshl.v2i64(<2 x i64>, <2 x i64>) nounwind define <8 x i8> @urshr8b(<8 x i8>* %A) nounwind { ;CHECK-LABEL: urshr8b: ;CHECK: urshr.8b - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>) ret <8 x i8> %tmp3 } @@ -449,7 +449,7 @@ define <8 x i8> @urshr8b(<8 x i8>* %A) nounwind { define <4 x i16> @urshr4h(<4 x i16>* %A) nounwind { ;CHECK-LABEL: urshr4h: ;CHECK: urshr.4h - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>) ret <4 x i16> %tmp3 } @@ -457,7 +457,7 @@ define <4 x i16> @urshr4h(<4 x i16>* %A) nounwind { define <2 x i32> @urshr2s(<2 x i32>* %A) nounwind { ;CHECK-LABEL: urshr2s: ;CHECK: urshr.2s - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>) ret <2 x i32> %tmp3 } @@ -465,7 +465,7 @@ define <2 x i32> @urshr2s(<2 x i32>* %A) nounwind { define <16 x i8> @urshr16b(<16 x i8>* %A) nounwind { ;CHECK-LABEL: urshr16b: ;CHECK: urshr.16b - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>) ret <16 x i8> %tmp3 } @@ -473,7 +473,7 @@ define <16 x i8> @urshr16b(<16 x i8>* %A) nounwind { define <8 x i16> @urshr8h(<8 x i16>* %A) nounwind { ;CHECK-LABEL: urshr8h: ;CHECK: urshr.8h - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>) ret <8 x i16> %tmp3 } @@ -481,7 +481,7 @@ define <8 x i16> @urshr8h(<8 x i16>* %A) nounwind { define <4 x i32> @urshr4s(<4 x i32>* %A) nounwind { ;CHECK-LABEL: urshr4s: ;CHECK: urshr.4s - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>) ret <4 x i32> %tmp3 } @@ -489,7 +489,7 @@ define <4 x i32> @urshr4s(<4 x i32>* %A) nounwind { define <2 x i64> @urshr2d(<2 x i64>* %A) nounwind { ;CHECK-LABEL: urshr2d: ;CHECK: urshr.2d - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>) ret <2 x i64> %tmp3 } @@ -497,7 +497,7 @@ define <2 x i64> @urshr2d(<2 x i64>* %A) nounwind { define <8 x i8> @srshr8b(<8 x i8>* %A) nounwind { ;CHECK-LABEL: srshr8b: ;CHECK: srshr.8b - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>) ret <8 x i8> %tmp3 } @@ -505,7 +505,7 @@ define <8 x i8> @srshr8b(<8 x i8>* %A) nounwind { define <4 x i16> @srshr4h(<4 x i16>* %A) nounwind { ;CHECK-LABEL: srshr4h: ;CHECK: srshr.4h - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>) ret <4 x i16> %tmp3 } @@ -513,7 +513,7 @@ define <4 x i16> @srshr4h(<4 x i16>* %A) nounwind { define <2 x i32> @srshr2s(<2 x i32>* %A) nounwind { ;CHECK-LABEL: srshr2s: ;CHECK: srshr.2s - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>) ret <2 x i32> %tmp3 } @@ -521,7 +521,7 @@ define <2 x i32> @srshr2s(<2 x i32>* %A) nounwind { define <16 x i8> @srshr16b(<16 x i8>* %A) nounwind { ;CHECK-LABEL: srshr16b: ;CHECK: srshr.16b - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>) ret <16 x i8> %tmp3 } @@ -529,7 +529,7 @@ define <16 x i8> @srshr16b(<16 x i8>* %A) nounwind { define <8 x i16> @srshr8h(<8 x i16>* %A) nounwind { ;CHECK-LABEL: srshr8h: ;CHECK: srshr.8h - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>) ret <8 x i16> %tmp3 } @@ -537,7 +537,7 @@ define <8 x i16> @srshr8h(<8 x i16>* %A) nounwind { define <4 x i32> @srshr4s(<4 x i32>* %A) nounwind { ;CHECK-LABEL: srshr4s: ;CHECK: srshr.4s - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>) ret <4 x i32> %tmp3 } @@ -545,7 +545,7 @@ define <4 x i32> @srshr4s(<4 x i32>* %A) nounwind { define <2 x i64> @srshr2d(<2 x i64>* %A) nounwind { ;CHECK-LABEL: srshr2d: ;CHECK: srshr.2d - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>) ret <2 x i64> %tmp3 } @@ -553,7 +553,7 @@ define <2 x i64> @srshr2d(<2 x i64>* %A) nounwind { define <8 x i8> @sqshlu8b(<8 x i8>* %A) nounwind { ;CHECK-LABEL: sqshlu8b: ;CHECK: sqshlu.8b v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>) ret <8 x i8> %tmp3 } @@ -561,7 +561,7 @@ define <8 x i8> @sqshlu8b(<8 x i8>* %A) nounwind { define <4 x i16> @sqshlu4h(<4 x i16>* %A) nounwind { ;CHECK-LABEL: sqshlu4h: ;CHECK: sqshlu.4h v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) ret <4 x i16> %tmp3 } @@ -569,7 +569,7 @@ define <4 x i16> @sqshlu4h(<4 x i16>* %A) nounwind { define <2 x i32> @sqshlu2s(<2 x i32>* %A) nounwind { ;CHECK-LABEL: sqshlu2s: ;CHECK: sqshlu.2s v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>) ret <2 x i32> %tmp3 } @@ -577,7 +577,7 @@ define <2 x i32> @sqshlu2s(<2 x i32>* %A) nounwind { define <16 x i8> @sqshlu16b(<16 x i8>* %A) nounwind { ;CHECK-LABEL: sqshlu16b: ;CHECK: sqshlu.16b v0, {{v[0-9]+}}, #1 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>) ret <16 x i8> %tmp3 } @@ -585,7 +585,7 @@ define <16 x i8> @sqshlu16b(<16 x i8>* %A) nounwind { define <8 x i16> @sqshlu8h(<8 x i16>* %A) nounwind { ;CHECK-LABEL: sqshlu8h: ;CHECK: sqshlu.8h v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>) ret <8 x i16> %tmp3 } @@ -593,7 +593,7 @@ define <8 x i16> @sqshlu8h(<8 x i16>* %A) nounwind { define <4 x i32> @sqshlu4s(<4 x i32>* %A) nounwind { ;CHECK-LABEL: sqshlu4s: ;CHECK: sqshlu.4s v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqshlu.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) ret <4 x i32> %tmp3 } @@ -601,7 +601,7 @@ define <4 x i32> @sqshlu4s(<4 x i32>* %A) nounwind { define <2 x i64> @sqshlu2d(<2 x i64>* %A) nounwind { ;CHECK-LABEL: sqshlu2d: ;CHECK: sqshlu.2d v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>) ret <2 x i64> %tmp3 } @@ -619,7 +619,7 @@ declare <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64>, <2 x i64>) nounwind define <8 x i8> @rshrn8b(<8 x i16>* %A) nounwind { ;CHECK-LABEL: rshrn8b: ;CHECK: rshrn.8b v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %tmp1, i32 1) ret <8 x i8> %tmp3 } @@ -627,7 +627,7 @@ define <8 x i8> @rshrn8b(<8 x i16>* %A) nounwind { define <4 x i16> @rshrn4h(<4 x i32>* %A) nounwind { ;CHECK-LABEL: rshrn4h: ;CHECK: rshrn.4h v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %tmp1, i32 1) ret <4 x i16> %tmp3 } @@ -635,7 +635,7 @@ define <4 x i16> @rshrn4h(<4 x i32>* %A) nounwind { define <2 x i32> @rshrn2s(<2 x i64>* %A) nounwind { ;CHECK-LABEL: rshrn2s: ;CHECK: rshrn.2s v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %tmp1, i32 1) ret <2 x i32> %tmp3 } @@ -643,8 +643,8 @@ define <2 x i32> @rshrn2s(<2 x i64>* %A) nounwind { define <16 x i8> @rshrn16b(<8 x i8> *%ret, <8 x i16>* %A) nounwind { ;CHECK-LABEL: rshrn16b: ;CHECK: rshrn2.16b v0, {{v[0-9]+}}, #1 - %out = load <8 x i8>* %ret - %tmp1 = load <8 x i16>* %A + %out = load <8 x i8>, <8 x i8>* %ret + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %tmp1, i32 1) %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ret <16 x i8> %tmp4 @@ -653,8 +653,8 @@ define <16 x i8> @rshrn16b(<8 x i8> *%ret, <8 x i16>* %A) nounwind { define <8 x i16> @rshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind { ;CHECK-LABEL: rshrn8h: ;CHECK: rshrn2.8h v0, {{v[0-9]+}}, #1 - %out = load <4 x i16>* %ret - %tmp1 = load <4 x i32>* %A + %out = load <4 x i16>, <4 x i16>* %ret + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %tmp1, i32 1) %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ret <8 x i16> %tmp4 @@ -663,8 +663,8 @@ define <8 x i16> @rshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind { define <4 x i32> @rshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind { ;CHECK-LABEL: rshrn4s: ;CHECK: rshrn2.4s v0, {{v[0-9]+}}, #1 - %out = load <2 x i32>* %ret - %tmp1 = load <2 x i64>* %A + %out = load <2 x i32>, <2 x i32>* %ret + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %tmp1, i32 1) %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ret <4 x i32> %tmp4 @@ -677,7 +677,7 @@ declare <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64>, i32) nounwind readno define <8 x i8> @shrn8b(<8 x i16>* %A) nounwind { ;CHECK-LABEL: shrn8b: ;CHECK: shrn.8b v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8> ret <8 x i8> %tmp3 @@ -686,7 +686,7 @@ define <8 x i8> @shrn8b(<8 x i16>* %A) nounwind { define <4 x i16> @shrn4h(<4 x i32>* %A) nounwind { ;CHECK-LABEL: shrn4h: ;CHECK: shrn.4h v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1> %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16> ret <4 x i16> %tmp3 @@ -695,7 +695,7 @@ define <4 x i16> @shrn4h(<4 x i32>* %A) nounwind { define <2 x i32> @shrn2s(<2 x i64>* %A) nounwind { ;CHECK-LABEL: shrn2s: ;CHECK: shrn.2s v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = lshr <2 x i64> %tmp1, <i64 1, i64 1> %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32> ret <2 x i32> %tmp3 @@ -704,8 +704,8 @@ define <2 x i32> @shrn2s(<2 x i64>* %A) nounwind { define <16 x i8> @shrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind { ;CHECK-LABEL: shrn16b: ;CHECK: shrn2.16b v0, {{v[0-9]+}}, #1 - %out = load <8 x i8>* %ret - %tmp1 = load <8 x i16>* %A + %out = load <8 x i8>, <8 x i8>* %ret + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8> %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> @@ -715,8 +715,8 @@ define <16 x i8> @shrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind { define <8 x i16> @shrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind { ;CHECK-LABEL: shrn8h: ;CHECK: shrn2.8h v0, {{v[0-9]+}}, #1 - %out = load <4 x i16>* %ret - %tmp1 = load <4 x i32>* %A + %out = load <4 x i16>, <4 x i16>* %ret + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1> %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16> %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> @@ -726,8 +726,8 @@ define <8 x i16> @shrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind { define <4 x i32> @shrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind { ;CHECK-LABEL: shrn4s: ;CHECK: shrn2.4s v0, {{v[0-9]+}}, #1 - %out = load <2 x i32>* %ret - %tmp1 = load <2 x i64>* %A + %out = load <2 x i32>, <2 x i32>* %ret + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp2 = lshr <2 x i64> %tmp1, <i64 1, i64 1> %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32> %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3> @@ -748,7 +748,7 @@ define i32 @sqshrn1s(i64 %A) nounwind { define <8 x i8> @sqshrn8b(<8 x i16>* %A) nounwind { ;CHECK-LABEL: sqshrn8b: ;CHECK: sqshrn.8b v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1) ret <8 x i8> %tmp3 } @@ -756,7 +756,7 @@ define <8 x i8> @sqshrn8b(<8 x i16>* %A) nounwind { define <4 x i16> @sqshrn4h(<4 x i32>* %A) nounwind { ;CHECK-LABEL: sqshrn4h: ;CHECK: sqshrn.4h v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1) ret <4 x i16> %tmp3 } @@ -764,7 +764,7 @@ define <4 x i16> @sqshrn4h(<4 x i32>* %A) nounwind { define <2 x i32> @sqshrn2s(<2 x i64>* %A) nounwind { ;CHECK-LABEL: sqshrn2s: ;CHECK: sqshrn.2s v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> %tmp1, i32 1) ret <2 x i32> %tmp3 } @@ -773,8 +773,8 @@ define <2 x i32> @sqshrn2s(<2 x i64>* %A) nounwind { define <16 x i8> @sqshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind { ;CHECK-LABEL: sqshrn16b: ;CHECK: sqshrn2.16b v0, {{v[0-9]+}}, #1 - %out = load <8 x i8>* %ret - %tmp1 = load <8 x i16>* %A + %out = load <8 x i8>, <8 x i8>* %ret + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1) %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ret <16 x i8> %tmp4 @@ -783,8 +783,8 @@ define <16 x i8> @sqshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind { define <8 x i16> @sqshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind { ;CHECK-LABEL: sqshrn8h: ;CHECK: sqshrn2.8h v0, {{v[0-9]+}}, #1 - %out = load <4 x i16>* %ret - %tmp1 = load <4 x i32>* %A + %out = load <4 x i16>, <4 x i16>* %ret + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1) %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ret <8 x i16> %tmp4 @@ -793,8 +793,8 @@ define <8 x i16> @sqshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind { define <4 x i32> @sqshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind { ;CHECK-LABEL: sqshrn4s: ;CHECK: sqshrn2.4s v0, {{v[0-9]+}}, #1 - %out = load <2 x i32>* %ret - %tmp1 = load <2 x i64>* %A + %out = load <2 x i32>, <2 x i32>* %ret + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> %tmp1, i32 1) %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ret <4 x i32> %tmp4 @@ -815,7 +815,7 @@ define i32 @sqshrun1s(i64 %A) nounwind { define <8 x i8> @sqshrun8b(<8 x i16>* %A) nounwind { ;CHECK-LABEL: sqshrun8b: ;CHECK: sqshrun.8b v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16> %tmp1, i32 1) ret <8 x i8> %tmp3 } @@ -823,7 +823,7 @@ define <8 x i8> @sqshrun8b(<8 x i16>* %A) nounwind { define <4 x i16> @sqshrun4h(<4 x i32>* %A) nounwind { ;CHECK-LABEL: sqshrun4h: ;CHECK: sqshrun.4h v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> %tmp1, i32 1) ret <4 x i16> %tmp3 } @@ -831,7 +831,7 @@ define <4 x i16> @sqshrun4h(<4 x i32>* %A) nounwind { define <2 x i32> @sqshrun2s(<2 x i64>* %A) nounwind { ;CHECK-LABEL: sqshrun2s: ;CHECK: sqshrun.2s v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64> %tmp1, i32 1) ret <2 x i32> %tmp3 } @@ -839,8 +839,8 @@ define <2 x i32> @sqshrun2s(<2 x i64>* %A) nounwind { define <16 x i8> @sqshrun16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind { ;CHECK-LABEL: sqshrun16b: ;CHECK: sqshrun2.16b v0, {{v[0-9]+}}, #1 - %out = load <8 x i8>* %ret - %tmp1 = load <8 x i16>* %A + %out = load <8 x i8>, <8 x i8>* %ret + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16> %tmp1, i32 1) %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ret <16 x i8> %tmp4 @@ -849,8 +849,8 @@ define <16 x i8> @sqshrun16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind { define <8 x i16> @sqshrun8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind { ;CHECK-LABEL: sqshrun8h: ;CHECK: sqshrun2.8h v0, {{v[0-9]+}}, #1 - %out = load <4 x i16>* %ret - %tmp1 = load <4 x i32>* %A + %out = load <4 x i16>, <4 x i16>* %ret + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> %tmp1, i32 1) %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ret <8 x i16> %tmp4 @@ -859,8 +859,8 @@ define <8 x i16> @sqshrun8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind { define <4 x i32> @sqshrun4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind { ;CHECK-LABEL: sqshrun4s: ;CHECK: sqshrun2.4s v0, {{v[0-9]+}}, #1 - %out = load <2 x i32>* %ret - %tmp1 = load <2 x i64>* %A + %out = load <2 x i32>, <2 x i32>* %ret + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64> %tmp1, i32 1) %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ret <4 x i32> %tmp4 @@ -881,7 +881,7 @@ define i32 @sqrshrn1s(i64 %A) nounwind { define <8 x i8> @sqrshrn8b(<8 x i16>* %A) nounwind { ;CHECK-LABEL: sqrshrn8b: ;CHECK: sqrshrn.8b v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %tmp1, i32 1) ret <8 x i8> %tmp3 } @@ -889,7 +889,7 @@ define <8 x i8> @sqrshrn8b(<8 x i16>* %A) nounwind { define <4 x i16> @sqrshrn4h(<4 x i32>* %A) nounwind { ;CHECK-LABEL: sqrshrn4h: ;CHECK: sqrshrn.4h v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %tmp1, i32 1) ret <4 x i16> %tmp3 } @@ -897,7 +897,7 @@ define <4 x i16> @sqrshrn4h(<4 x i32>* %A) nounwind { define <2 x i32> @sqrshrn2s(<2 x i64>* %A) nounwind { ;CHECK-LABEL: sqrshrn2s: ;CHECK: sqrshrn.2s v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> %tmp1, i32 1) ret <2 x i32> %tmp3 } @@ -905,8 +905,8 @@ define <2 x i32> @sqrshrn2s(<2 x i64>* %A) nounwind { define <16 x i8> @sqrshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind { ;CHECK-LABEL: sqrshrn16b: ;CHECK: sqrshrn2.16b v0, {{v[0-9]+}}, #1 - %out = load <8 x i8>* %ret - %tmp1 = load <8 x i16>* %A + %out = load <8 x i8>, <8 x i8>* %ret + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %tmp1, i32 1) %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ret <16 x i8> %tmp4 @@ -915,8 +915,8 @@ define <16 x i8> @sqrshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind { define <8 x i16> @sqrshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind { ;CHECK-LABEL: sqrshrn8h: ;CHECK: sqrshrn2.8h v0, {{v[0-9]+}}, #1 - %out = load <4 x i16>* %ret - %tmp1 = load <4 x i32>* %A + %out = load <4 x i16>, <4 x i16>* %ret + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %tmp1, i32 1) %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ret <8 x i16> %tmp4 @@ -925,8 +925,8 @@ define <8 x i16> @sqrshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind { define <4 x i32> @sqrshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind { ;CHECK-LABEL: sqrshrn4s: ;CHECK: sqrshrn2.4s v0, {{v[0-9]+}}, #1 - %out = load <2 x i32>* %ret - %tmp1 = load <2 x i64>* %A + %out = load <2 x i32>, <2 x i32>* %ret + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> %tmp1, i32 1) %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ret <4 x i32> %tmp4 @@ -947,7 +947,7 @@ define i32 @sqrshrun1s(i64 %A) nounwind { define <8 x i8> @sqrshrun8b(<8 x i16>* %A) nounwind { ;CHECK-LABEL: sqrshrun8b: ;CHECK: sqrshrun.8b v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %tmp1, i32 1) ret <8 x i8> %tmp3 } @@ -955,7 +955,7 @@ define <8 x i8> @sqrshrun8b(<8 x i16>* %A) nounwind { define <4 x i16> @sqrshrun4h(<4 x i32>* %A) nounwind { ;CHECK-LABEL: sqrshrun4h: ;CHECK: sqrshrun.4h v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %tmp1, i32 1) ret <4 x i16> %tmp3 } @@ -963,7 +963,7 @@ define <4 x i16> @sqrshrun4h(<4 x i32>* %A) nounwind { define <2 x i32> @sqrshrun2s(<2 x i64>* %A) nounwind { ;CHECK-LABEL: sqrshrun2s: ;CHECK: sqrshrun.2s v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64> %tmp1, i32 1) ret <2 x i32> %tmp3 } @@ -971,8 +971,8 @@ define <2 x i32> @sqrshrun2s(<2 x i64>* %A) nounwind { define <16 x i8> @sqrshrun16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind { ;CHECK-LABEL: sqrshrun16b: ;CHECK: sqrshrun2.16b v0, {{v[0-9]+}}, #1 - %out = load <8 x i8>* %ret - %tmp1 = load <8 x i16>* %A + %out = load <8 x i8>, <8 x i8>* %ret + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %tmp1, i32 1) %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ret <16 x i8> %tmp4 @@ -981,8 +981,8 @@ define <16 x i8> @sqrshrun16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind { define <8 x i16> @sqrshrun8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind { ;CHECK-LABEL: sqrshrun8h: ;CHECK: sqrshrun2.8h v0, {{v[0-9]+}}, #1 - %out = load <4 x i16>* %ret - %tmp1 = load <4 x i32>* %A + %out = load <4 x i16>, <4 x i16>* %ret + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %tmp1, i32 1) %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ret <8 x i16> %tmp4 @@ -991,8 +991,8 @@ define <8 x i16> @sqrshrun8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind { define <4 x i32> @sqrshrun4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind { ;CHECK-LABEL: sqrshrun4s: ;CHECK: sqrshrun2.4s v0, {{v[0-9]+}}, #1 - %out = load <2 x i32>* %ret - %tmp1 = load <2 x i64>* %A + %out = load <2 x i32>, <2 x i32>* %ret + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64> %tmp1, i32 1) %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ret <4 x i32> %tmp4 @@ -1013,7 +1013,7 @@ define i32 @uqrshrn1s(i64 %A) nounwind { define <8 x i8> @uqrshrn8b(<8 x i16>* %A) nounwind { ;CHECK-LABEL: uqrshrn8b: ;CHECK: uqrshrn.8b v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %tmp1, i32 1) ret <8 x i8> %tmp3 } @@ -1021,7 +1021,7 @@ define <8 x i8> @uqrshrn8b(<8 x i16>* %A) nounwind { define <4 x i16> @uqrshrn4h(<4 x i32>* %A) nounwind { ;CHECK-LABEL: uqrshrn4h: ;CHECK: uqrshrn.4h v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %tmp1, i32 1) ret <4 x i16> %tmp3 } @@ -1029,7 +1029,7 @@ define <4 x i16> @uqrshrn4h(<4 x i32>* %A) nounwind { define <2 x i32> @uqrshrn2s(<2 x i64>* %A) nounwind { ;CHECK-LABEL: uqrshrn2s: ;CHECK: uqrshrn.2s v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64> %tmp1, i32 1) ret <2 x i32> %tmp3 } @@ -1037,8 +1037,8 @@ define <2 x i32> @uqrshrn2s(<2 x i64>* %A) nounwind { define <16 x i8> @uqrshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind { ;CHECK-LABEL: uqrshrn16b: ;CHECK: uqrshrn2.16b v0, {{v[0-9]+}}, #1 - %out = load <8 x i8>* %ret - %tmp1 = load <8 x i16>* %A + %out = load <8 x i8>, <8 x i8>* %ret + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %tmp1, i32 1) %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ret <16 x i8> %tmp4 @@ -1047,8 +1047,8 @@ define <16 x i8> @uqrshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind { define <8 x i16> @uqrshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind { ;CHECK-LABEL: uqrshrn8h: ;CHECK: uqrshrn2.8h v0, {{v[0-9]+}}, #1 - %out = load <4 x i16>* %ret - %tmp1 = load <4 x i32>* %A + %out = load <4 x i16>, <4 x i16>* %ret + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %tmp1, i32 1) %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ret <8 x i16> %tmp4 @@ -1057,8 +1057,8 @@ define <8 x i16> @uqrshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind { define <4 x i32> @uqrshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind { ;CHECK-LABEL: uqrshrn4s: ;CHECK: uqrshrn2.4s v0, {{v[0-9]+}}, #1 - %out = load <2 x i32>* %ret - %tmp1 = load <2 x i64>* %A + %out = load <2 x i32>, <2 x i32>* %ret + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64> %tmp1, i32 1) %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ret <4 x i32> %tmp4 @@ -1079,7 +1079,7 @@ define i32 @uqshrn1s(i64 %A) nounwind { define <8 x i8> @uqshrn8b(<8 x i16>* %A) nounwind { ;CHECK-LABEL: uqshrn8b: ;CHECK: uqshrn.8b v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1) ret <8 x i8> %tmp3 } @@ -1087,7 +1087,7 @@ define <8 x i8> @uqshrn8b(<8 x i16>* %A) nounwind { define <4 x i16> @uqshrn4h(<4 x i32>* %A) nounwind { ;CHECK-LABEL: uqshrn4h: ;CHECK: uqshrn.4h v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1) ret <4 x i16> %tmp3 } @@ -1095,7 +1095,7 @@ define <4 x i16> @uqshrn4h(<4 x i32>* %A) nounwind { define <2 x i32> @uqshrn2s(<2 x i64>* %A) nounwind { ;CHECK-LABEL: uqshrn2s: ;CHECK: uqshrn.2s v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> %tmp1, i32 1) ret <2 x i32> %tmp3 } @@ -1103,8 +1103,8 @@ define <2 x i32> @uqshrn2s(<2 x i64>* %A) nounwind { define <16 x i8> @uqshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind { ;CHECK-LABEL: uqshrn16b: ;CHECK: uqshrn2.16b v0, {{v[0-9]+}}, #1 - %out = load <8 x i8>* %ret - %tmp1 = load <8 x i16>* %A + %out = load <8 x i8>, <8 x i8>* %ret + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1) %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ret <16 x i8> %tmp4 @@ -1113,8 +1113,8 @@ define <16 x i8> @uqshrn16b(<8 x i8>* %ret, <8 x i16>* %A) nounwind { define <8 x i16> @uqshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind { ;CHECK-LABEL: uqshrn8h: ;CHECK: uqshrn2.8h v0, {{v[0-9]+}}, #1 - %out = load <4 x i16>* %ret - %tmp1 = load <4 x i32>* %A + %out = load <4 x i16>, <4 x i16>* %ret + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1) %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ret <8 x i16> %tmp4 @@ -1123,8 +1123,8 @@ define <8 x i16> @uqshrn8h(<4 x i16>* %ret, <4 x i32>* %A) nounwind { define <4 x i32> @uqshrn4s(<2 x i32>* %ret, <2 x i64>* %A) nounwind { ;CHECK-LABEL: uqshrn4s: ;CHECK: uqshrn2.4s v0, {{v[0-9]+}}, #1 - %out = load <2 x i32>* %ret - %tmp1 = load <2 x i64>* %A + %out = load <2 x i32>, <2 x i32>* %ret + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> %tmp1, i32 1) %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ret <4 x i32> %tmp4 @@ -1138,7 +1138,7 @@ declare <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64>, i32) nounwind readn define <8 x i16> @ushll8h(<8 x i8>* %A) nounwind { ;CHECK-LABEL: ushll8h: ;CHECK: ushll.8h v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = zext <8 x i8> %tmp1 to <8 x i16> %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> ret <8 x i16> %tmp3 @@ -1147,7 +1147,7 @@ define <8 x i16> @ushll8h(<8 x i8>* %A) nounwind { define <4 x i32> @ushll4s(<4 x i16>* %A) nounwind { ;CHECK-LABEL: ushll4s: ;CHECK: ushll.4s v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = zext <4 x i16> %tmp1 to <4 x i32> %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1> ret <4 x i32> %tmp3 @@ -1156,7 +1156,7 @@ define <4 x i32> @ushll4s(<4 x i16>* %A) nounwind { define <2 x i64> @ushll2d(<2 x i32>* %A) nounwind { ;CHECK-LABEL: ushll2d: ;CHECK: ushll.2d v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = zext <2 x i32> %tmp1 to <2 x i64> %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1> ret <2 x i64> %tmp3 @@ -1165,7 +1165,7 @@ define <2 x i64> @ushll2d(<2 x i32>* %A) nounwind { define <8 x i16> @ushll2_8h(<16 x i8>* %A) nounwind { ;CHECK-LABEL: ushll2_8h: ;CHECK: ushll2.8h v0, {{v[0-9]+}}, #1 - %load1 = load <16 x i8>* %A + %load1 = load <16 x i8>, <16 x i8>* %A %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %tmp2 = zext <8 x i8> %tmp1 to <8 x i16> %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> @@ -1175,7 +1175,7 @@ define <8 x i16> @ushll2_8h(<16 x i8>* %A) nounwind { define <4 x i32> @ushll2_4s(<8 x i16>* %A) nounwind { ;CHECK-LABEL: ushll2_4s: ;CHECK: ushll2.4s v0, {{v[0-9]+}}, #1 - %load1 = load <8 x i16>* %A + %load1 = load <8 x i16>, <8 x i16>* %A %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp2 = zext <4 x i16> %tmp1 to <4 x i32> %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1> @@ -1185,7 +1185,7 @@ define <4 x i32> @ushll2_4s(<8 x i16>* %A) nounwind { define <2 x i64> @ushll2_2d(<4 x i32>* %A) nounwind { ;CHECK-LABEL: ushll2_2d: ;CHECK: ushll2.2d v0, {{v[0-9]+}}, #1 - %load1 = load <4 x i32>* %A + %load1 = load <4 x i32>, <4 x i32>* %A %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp2 = zext <2 x i32> %tmp1 to <2 x i64> %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1> @@ -1195,7 +1195,7 @@ define <2 x i64> @ushll2_2d(<4 x i32>* %A) nounwind { define <8 x i16> @sshll8h(<8 x i8>* %A) nounwind { ;CHECK-LABEL: sshll8h: ;CHECK: sshll.8h v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = sext <8 x i8> %tmp1 to <8 x i16> %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> ret <8 x i16> %tmp3 @@ -1204,7 +1204,7 @@ define <8 x i16> @sshll8h(<8 x i8>* %A) nounwind { define <4 x i32> @sshll4s(<4 x i16>* %A) nounwind { ;CHECK-LABEL: sshll4s: ;CHECK: sshll.4s v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = sext <4 x i16> %tmp1 to <4 x i32> %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1> ret <4 x i32> %tmp3 @@ -1213,7 +1213,7 @@ define <4 x i32> @sshll4s(<4 x i16>* %A) nounwind { define <2 x i64> @sshll2d(<2 x i32>* %A) nounwind { ;CHECK-LABEL: sshll2d: ;CHECK: sshll.2d v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = sext <2 x i32> %tmp1 to <2 x i64> %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1> ret <2 x i64> %tmp3 @@ -1222,7 +1222,7 @@ define <2 x i64> @sshll2d(<2 x i32>* %A) nounwind { define <8 x i16> @sshll2_8h(<16 x i8>* %A) nounwind { ;CHECK-LABEL: sshll2_8h: ;CHECK: sshll2.8h v0, {{v[0-9]+}}, #1 - %load1 = load <16 x i8>* %A + %load1 = load <16 x i8>, <16 x i8>* %A %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %tmp2 = sext <8 x i8> %tmp1 to <8 x i16> %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> @@ -1232,7 +1232,7 @@ define <8 x i16> @sshll2_8h(<16 x i8>* %A) nounwind { define <4 x i32> @sshll2_4s(<8 x i16>* %A) nounwind { ;CHECK-LABEL: sshll2_4s: ;CHECK: sshll2.4s v0, {{v[0-9]+}}, #1 - %load1 = load <8 x i16>* %A + %load1 = load <8 x i16>, <8 x i16>* %A %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %tmp2 = sext <4 x i16> %tmp1 to <4 x i32> %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1> @@ -1242,7 +1242,7 @@ define <4 x i32> @sshll2_4s(<8 x i16>* %A) nounwind { define <2 x i64> @sshll2_2d(<4 x i32>* %A) nounwind { ;CHECK-LABEL: sshll2_2d: ;CHECK: sshll2.2d v0, {{v[0-9]+}}, #1 - %load1 = load <4 x i32>* %A + %load1 = load <4 x i32>, <4 x i32>* %A %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %tmp2 = sext <2 x i32> %tmp1 to <2 x i64> %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1> @@ -1252,7 +1252,7 @@ define <2 x i64> @sshll2_2d(<4 x i32>* %A) nounwind { define <8 x i8> @sqshli8b(<8 x i8>* %A) nounwind { ;CHECK-LABEL: sqshli8b: ;CHECK: sqshl.8b v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>) ret <8 x i8> %tmp3 } @@ -1260,7 +1260,7 @@ define <8 x i8> @sqshli8b(<8 x i8>* %A) nounwind { define <4 x i16> @sqshli4h(<4 x i16>* %A) nounwind { ;CHECK-LABEL: sqshli4h: ;CHECK: sqshl.4h v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) ret <4 x i16> %tmp3 } @@ -1268,7 +1268,7 @@ define <4 x i16> @sqshli4h(<4 x i16>* %A) nounwind { define <2 x i32> @sqshli2s(<2 x i32>* %A) nounwind { ;CHECK-LABEL: sqshli2s: ;CHECK: sqshl.2s v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>) ret <2 x i32> %tmp3 } @@ -1276,7 +1276,7 @@ define <2 x i32> @sqshli2s(<2 x i32>* %A) nounwind { define <16 x i8> @sqshli16b(<16 x i8>* %A) nounwind { ;CHECK-LABEL: sqshli16b: ;CHECK: sqshl.16b v0, {{v[0-9]+}}, #1 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>) ret <16 x i8> %tmp3 } @@ -1284,7 +1284,7 @@ define <16 x i8> @sqshli16b(<16 x i8>* %A) nounwind { define <8 x i16> @sqshli8h(<8 x i16>* %A) nounwind { ;CHECK-LABEL: sqshli8h: ;CHECK: sqshl.8h v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>) ret <8 x i16> %tmp3 } @@ -1292,7 +1292,7 @@ define <8 x i16> @sqshli8h(<8 x i16>* %A) nounwind { define <4 x i32> @sqshli4s(<4 x i32>* %A) nounwind { ;CHECK-LABEL: sqshli4s: ;CHECK: sqshl.4s v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) ret <4 x i32> %tmp3 } @@ -1300,7 +1300,7 @@ define <4 x i32> @sqshli4s(<4 x i32>* %A) nounwind { define <2 x i64> @sqshli2d(<2 x i64>* %A) nounwind { ;CHECK-LABEL: sqshli2d: ;CHECK: sqshl.2d v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>) ret <2 x i64> %tmp3 } @@ -1308,7 +1308,7 @@ define <2 x i64> @sqshli2d(<2 x i64>* %A) nounwind { define <8 x i8> @uqshli8b(<8 x i8>* %A) nounwind { ;CHECK-LABEL: uqshli8b: ;CHECK: uqshl.8b v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>) ret <8 x i8> %tmp3 } @@ -1317,7 +1317,7 @@ define <8 x i8> @uqshli8b_1(<8 x i8>* %A) nounwind { ;CHECK-LABEL: uqshli8b_1: ;CHECK: movi.8b [[REG:v[0-9]+]], #0x8 ;CHECK: uqshl.8b v0, v0, [[REG]] - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>) ret <8 x i8> %tmp3 } @@ -1325,7 +1325,7 @@ define <8 x i8> @uqshli8b_1(<8 x i8>* %A) nounwind { define <4 x i16> @uqshli4h(<4 x i16>* %A) nounwind { ;CHECK-LABEL: uqshli4h: ;CHECK: uqshl.4h v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) ret <4 x i16> %tmp3 } @@ -1333,7 +1333,7 @@ define <4 x i16> @uqshli4h(<4 x i16>* %A) nounwind { define <2 x i32> @uqshli2s(<2 x i32>* %A) nounwind { ;CHECK-LABEL: uqshli2s: ;CHECK: uqshl.2s v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>) ret <2 x i32> %tmp3 } @@ -1341,7 +1341,7 @@ define <2 x i32> @uqshli2s(<2 x i32>* %A) nounwind { define <16 x i8> @uqshli16b(<16 x i8>* %A) nounwind { ;CHECK-LABEL: uqshli16b: ;CHECK: uqshl.16b - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>) ret <16 x i8> %tmp3 } @@ -1349,7 +1349,7 @@ define <16 x i8> @uqshli16b(<16 x i8>* %A) nounwind { define <8 x i16> @uqshli8h(<8 x i16>* %A) nounwind { ;CHECK-LABEL: uqshli8h: ;CHECK: uqshl.8h v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>) ret <8 x i16> %tmp3 } @@ -1357,7 +1357,7 @@ define <8 x i16> @uqshli8h(<8 x i16>* %A) nounwind { define <4 x i32> @uqshli4s(<4 x i32>* %A) nounwind { ;CHECK-LABEL: uqshli4s: ;CHECK: uqshl.4s v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>) ret <4 x i32> %tmp3 } @@ -1365,7 +1365,7 @@ define <4 x i32> @uqshli4s(<4 x i32>* %A) nounwind { define <2 x i64> @uqshli2d(<2 x i64>* %A) nounwind { ;CHECK-LABEL: uqshli2d: ;CHECK: uqshl.2d v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>) ret <2 x i64> %tmp3 } @@ -1373,9 +1373,9 @@ define <2 x i64> @uqshli2d(<2 x i64>* %A) nounwind { define <8 x i8> @ursra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: ursra8b: ;CHECK: ursra.8b v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>) - %tmp4 = load <8 x i8>* %B + %tmp4 = load <8 x i8>, <8 x i8>* %B %tmp5 = add <8 x i8> %tmp3, %tmp4 ret <8 x i8> %tmp5 } @@ -1383,9 +1383,9 @@ define <8 x i8> @ursra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @ursra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: ursra4h: ;CHECK: ursra.4h v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>) - %tmp4 = load <4 x i16>* %B + %tmp4 = load <4 x i16>, <4 x i16>* %B %tmp5 = add <4 x i16> %tmp3, %tmp4 ret <4 x i16> %tmp5 } @@ -1393,9 +1393,9 @@ define <4 x i16> @ursra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @ursra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: ursra2s: ;CHECK: ursra.2s v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>) - %tmp4 = load <2 x i32>* %B + %tmp4 = load <2 x i32>, <2 x i32>* %B %tmp5 = add <2 x i32> %tmp3, %tmp4 ret <2 x i32> %tmp5 } @@ -1403,9 +1403,9 @@ define <2 x i32> @ursra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @ursra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: ursra16b: ;CHECK: ursra.16b v0, {{v[0-9]+}}, #1 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>) - %tmp4 = load <16 x i8>* %B + %tmp4 = load <16 x i8>, <16 x i8>* %B %tmp5 = add <16 x i8> %tmp3, %tmp4 ret <16 x i8> %tmp5 } @@ -1413,9 +1413,9 @@ define <16 x i8> @ursra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @ursra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: ursra8h: ;CHECK: ursra.8h v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>) - %tmp4 = load <8 x i16>* %B + %tmp4 = load <8 x i16>, <8 x i16>* %B %tmp5 = add <8 x i16> %tmp3, %tmp4 ret <8 x i16> %tmp5 } @@ -1423,9 +1423,9 @@ define <8 x i16> @ursra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @ursra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: ursra4s: ;CHECK: ursra.4s v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>) - %tmp4 = load <4 x i32>* %B + %tmp4 = load <4 x i32>, <4 x i32>* %B %tmp5 = add <4 x i32> %tmp3, %tmp4 ret <4 x i32> %tmp5 } @@ -1433,9 +1433,9 @@ define <4 x i32> @ursra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @ursra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: ursra2d: ;CHECK: ursra.2d v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>) - %tmp4 = load <2 x i64>* %B + %tmp4 = load <2 x i64>, <2 x i64>* %B %tmp5 = add <2 x i64> %tmp3, %tmp4 ret <2 x i64> %tmp5 } @@ -1443,9 +1443,9 @@ define <2 x i64> @ursra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @srsra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: srsra8b: ;CHECK: srsra.8b v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>) - %tmp4 = load <8 x i8>* %B + %tmp4 = load <8 x i8>, <8 x i8>* %B %tmp5 = add <8 x i8> %tmp3, %tmp4 ret <8 x i8> %tmp5 } @@ -1453,9 +1453,9 @@ define <8 x i8> @srsra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @srsra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: srsra4h: ;CHECK: srsra.4h v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp3 = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>) - %tmp4 = load <4 x i16>* %B + %tmp4 = load <4 x i16>, <4 x i16>* %B %tmp5 = add <4 x i16> %tmp3, %tmp4 ret <4 x i16> %tmp5 } @@ -1463,9 +1463,9 @@ define <4 x i16> @srsra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @srsra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: srsra2s: ;CHECK: srsra.2s v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>) - %tmp4 = load <2 x i32>* %B + %tmp4 = load <2 x i32>, <2 x i32>* %B %tmp5 = add <2 x i32> %tmp3, %tmp4 ret <2 x i32> %tmp5 } @@ -1473,9 +1473,9 @@ define <2 x i32> @srsra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @srsra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: srsra16b: ;CHECK: srsra.16b v0, {{v[0-9]+}}, #1 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>) - %tmp4 = load <16 x i8>* %B + %tmp4 = load <16 x i8>, <16 x i8>* %B %tmp5 = add <16 x i8> %tmp3, %tmp4 ret <16 x i8> %tmp5 } @@ -1483,9 +1483,9 @@ define <16 x i8> @srsra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @srsra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: srsra8h: ;CHECK: srsra.8h v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>) - %tmp4 = load <8 x i16>* %B + %tmp4 = load <8 x i16>, <8 x i16>* %B %tmp5 = add <8 x i16> %tmp3, %tmp4 ret <8 x i16> %tmp5 } @@ -1493,9 +1493,9 @@ define <8 x i16> @srsra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @srsra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: srsra4s: ;CHECK: srsra.4s v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>) - %tmp4 = load <4 x i32>* %B + %tmp4 = load <4 x i32>, <4 x i32>* %B %tmp5 = add <4 x i32> %tmp3, %tmp4 ret <4 x i32> %tmp5 } @@ -1503,9 +1503,9 @@ define <4 x i32> @srsra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @srsra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: srsra2d: ;CHECK: srsra.2d v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>) - %tmp4 = load <2 x i64>* %B + %tmp4 = load <2 x i64>, <2 x i64>* %B %tmp5 = add <2 x i64> %tmp3, %tmp4 ret <2 x i64> %tmp5 } @@ -1513,9 +1513,9 @@ define <2 x i64> @srsra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @usra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: usra8b: ;CHECK: usra.8b v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = lshr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> - %tmp4 = load <8 x i8>* %B + %tmp4 = load <8 x i8>, <8 x i8>* %B %tmp5 = add <8 x i8> %tmp3, %tmp4 ret <8 x i8> %tmp5 } @@ -1523,9 +1523,9 @@ define <8 x i8> @usra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @usra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: usra4h: ;CHECK: usra.4h v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp3 = lshr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1> - %tmp4 = load <4 x i16>* %B + %tmp4 = load <4 x i16>, <4 x i16>* %B %tmp5 = add <4 x i16> %tmp3, %tmp4 ret <4 x i16> %tmp5 } @@ -1533,9 +1533,9 @@ define <4 x i16> @usra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @usra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: usra2s: ;CHECK: usra.2s v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp3 = lshr <2 x i32> %tmp1, <i32 1, i32 1> - %tmp4 = load <2 x i32>* %B + %tmp4 = load <2 x i32>, <2 x i32>* %B %tmp5 = add <2 x i32> %tmp3, %tmp4 ret <2 x i32> %tmp5 } @@ -1543,9 +1543,9 @@ define <2 x i32> @usra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @usra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: usra16b: ;CHECK: usra.16b v0, {{v[0-9]+}}, #1 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = lshr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> - %tmp4 = load <16 x i8>* %B + %tmp4 = load <16 x i8>, <16 x i8>* %B %tmp5 = add <16 x i8> %tmp3, %tmp4 ret <16 x i8> %tmp5 } @@ -1553,9 +1553,9 @@ define <16 x i8> @usra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @usra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: usra8h: ;CHECK: usra.8h v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> - %tmp4 = load <8 x i16>* %B + %tmp4 = load <8 x i16>, <8 x i16>* %B %tmp5 = add <8 x i16> %tmp3, %tmp4 ret <8 x i16> %tmp5 } @@ -1563,9 +1563,9 @@ define <8 x i16> @usra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @usra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: usra4s: ;CHECK: usra.4s v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1> - %tmp4 = load <4 x i32>* %B + %tmp4 = load <4 x i32>, <4 x i32>* %B %tmp5 = add <4 x i32> %tmp3, %tmp4 ret <4 x i32> %tmp5 } @@ -1573,9 +1573,9 @@ define <4 x i32> @usra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @usra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: usra2d: ;CHECK: usra.2d v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = lshr <2 x i64> %tmp1, <i64 1, i64 1> - %tmp4 = load <2 x i64>* %B + %tmp4 = load <2 x i64>, <2 x i64>* %B %tmp5 = add <2 x i64> %tmp3, %tmp4 ret <2 x i64> %tmp5 } @@ -1583,9 +1583,9 @@ define <2 x i64> @usra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @ssra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: ssra8b: ;CHECK: ssra.8b v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = ashr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> - %tmp4 = load <8 x i8>* %B + %tmp4 = load <8 x i8>, <8 x i8>* %B %tmp5 = add <8 x i8> %tmp3, %tmp4 ret <8 x i8> %tmp5 } @@ -1593,9 +1593,9 @@ define <8 x i8> @ssra8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @ssra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: ssra4h: ;CHECK: ssra.4h v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp3 = ashr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1> - %tmp4 = load <4 x i16>* %B + %tmp4 = load <4 x i16>, <4 x i16>* %B %tmp5 = add <4 x i16> %tmp3, %tmp4 ret <4 x i16> %tmp5 } @@ -1603,9 +1603,9 @@ define <4 x i16> @ssra4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @ssra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: ssra2s: ;CHECK: ssra.2s v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp3 = ashr <2 x i32> %tmp1, <i32 1, i32 1> - %tmp4 = load <2 x i32>* %B + %tmp4 = load <2 x i32>, <2 x i32>* %B %tmp5 = add <2 x i32> %tmp3, %tmp4 ret <2 x i32> %tmp5 } @@ -1613,9 +1613,9 @@ define <2 x i32> @ssra2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @ssra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: ssra16b: ;CHECK: ssra.16b v0, {{v[0-9]+}}, #1 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp3 = ashr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> - %tmp4 = load <16 x i8>* %B + %tmp4 = load <16 x i8>, <16 x i8>* %B %tmp5 = add <16 x i8> %tmp3, %tmp4 ret <16 x i8> %tmp5 } @@ -1623,9 +1623,9 @@ define <16 x i8> @ssra16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @ssra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: ssra8h: ;CHECK: ssra.8h v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp3 = ashr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> - %tmp4 = load <8 x i16>* %B + %tmp4 = load <8 x i16>, <8 x i16>* %B %tmp5 = add <8 x i16> %tmp3, %tmp4 ret <8 x i16> %tmp5 } @@ -1633,9 +1633,9 @@ define <8 x i16> @ssra8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @ssra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: ssra4s: ;CHECK: ssra.4s v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = ashr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1> - %tmp4 = load <4 x i32>* %B + %tmp4 = load <4 x i32>, <4 x i32>* %B %tmp5 = add <4 x i32> %tmp3, %tmp4 ret <4 x i32> %tmp5 } @@ -1643,9 +1643,9 @@ define <4 x i32> @ssra4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @ssra2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: ssra2d: ;CHECK: ssra.2d v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A %tmp3 = ashr <2 x i64> %tmp1, <i64 1, i64 1> - %tmp4 = load <2 x i64>* %B + %tmp4 = load <2 x i64>, <2 x i64>* %B %tmp5 = add <2 x i64> %tmp3, %tmp4 ret <2 x i64> %tmp5 } @@ -1655,8 +1655,8 @@ define <8 x i8> @shr_orr8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: shr.8b v0, {{v[0-9]+}}, #1 ;CHECK-NEXT: orr.8b ;CHECK-NEXT: ret - %tmp1 = load <8 x i8>* %A - %tmp4 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp4 = load <8 x i8>, <8 x i8>* %B %tmp3 = lshr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> %tmp5 = or <8 x i8> %tmp3, %tmp4 ret <8 x i8> %tmp5 @@ -1667,8 +1667,8 @@ define <4 x i16> @shr_orr4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK: shr.4h v0, {{v[0-9]+}}, #1 ;CHECK-NEXT: orr.8b ;CHECK-NEXT: ret - %tmp1 = load <4 x i16>* %A - %tmp4 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp4 = load <4 x i16>, <4 x i16>* %B %tmp3 = lshr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1> %tmp5 = or <4 x i16> %tmp3, %tmp4 ret <4 x i16> %tmp5 @@ -1679,8 +1679,8 @@ define <2 x i32> @shr_orr2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK: shr.2s v0, {{v[0-9]+}}, #1 ;CHECK-NEXT: orr.8b ;CHECK-NEXT: ret - %tmp1 = load <2 x i32>* %A - %tmp4 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp4 = load <2 x i32>, <2 x i32>* %B %tmp3 = lshr <2 x i32> %tmp1, <i32 1, i32 1> %tmp5 = or <2 x i32> %tmp3, %tmp4 ret <2 x i32> %tmp5 @@ -1691,8 +1691,8 @@ define <16 x i8> @shr_orr16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK: shr.16b v0, {{v[0-9]+}}, #1 ;CHECK-NEXT: orr.16b ;CHECK-NEXT: ret - %tmp1 = load <16 x i8>* %A - %tmp4 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp4 = load <16 x i8>, <16 x i8>* %B %tmp3 = lshr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> %tmp5 = or <16 x i8> %tmp3, %tmp4 ret <16 x i8> %tmp5 @@ -1703,8 +1703,8 @@ define <8 x i16> @shr_orr8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK: shr.8h v0, {{v[0-9]+}}, #1 ;CHECK-NEXT: orr.16b ;CHECK-NEXT: ret - %tmp1 = load <8 x i16>* %A - %tmp4 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp4 = load <8 x i16>, <8 x i16>* %B %tmp3 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %tmp5 = or <8 x i16> %tmp3, %tmp4 ret <8 x i16> %tmp5 @@ -1715,8 +1715,8 @@ define <4 x i32> @shr_orr4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK: shr.4s v0, {{v[0-9]+}}, #1 ;CHECK-NEXT: orr.16b ;CHECK-NEXT: ret - %tmp1 = load <4 x i32>* %A - %tmp4 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp4 = load <4 x i32>, <4 x i32>* %B %tmp3 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1> %tmp5 = or <4 x i32> %tmp3, %tmp4 ret <4 x i32> %tmp5 @@ -1727,8 +1727,8 @@ define <2 x i64> @shr_orr2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK: shr.2d v0, {{v[0-9]+}}, #1 ;CHECK-NEXT: orr.16b ;CHECK-NEXT: ret - %tmp1 = load <2 x i64>* %A - %tmp4 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp4 = load <2 x i64>, <2 x i64>* %B %tmp3 = lshr <2 x i64> %tmp1, <i64 1, i64 1> %tmp5 = or <2 x i64> %tmp3, %tmp4 ret <2 x i64> %tmp5 @@ -1739,8 +1739,8 @@ define <8 x i8> @shl_orr8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: shl.8b v0, {{v[0-9]+}}, #1 ;CHECK-NEXT: orr.8b ;CHECK-NEXT: ret - %tmp1 = load <8 x i8>* %A - %tmp4 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp4 = load <8 x i8>, <8 x i8>* %B %tmp3 = shl <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> %tmp5 = or <8 x i8> %tmp3, %tmp4 ret <8 x i8> %tmp5 @@ -1751,8 +1751,8 @@ define <4 x i16> @shl_orr4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK: shl.4h v0, {{v[0-9]+}}, #1 ;CHECK-NEXT: orr.8b ;CHECK-NEXT: ret - %tmp1 = load <4 x i16>* %A - %tmp4 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp4 = load <4 x i16>, <4 x i16>* %B %tmp3 = shl <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1> %tmp5 = or <4 x i16> %tmp3, %tmp4 ret <4 x i16> %tmp5 @@ -1763,8 +1763,8 @@ define <2 x i32> @shl_orr2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK: shl.2s v0, {{v[0-9]+}}, #1 ;CHECK-NEXT: orr.8b ;CHECK-NEXT: ret - %tmp1 = load <2 x i32>* %A - %tmp4 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp4 = load <2 x i32>, <2 x i32>* %B %tmp3 = shl <2 x i32> %tmp1, <i32 1, i32 1> %tmp5 = or <2 x i32> %tmp3, %tmp4 ret <2 x i32> %tmp5 @@ -1775,8 +1775,8 @@ define <16 x i8> @shl_orr16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK: shl.16b v0, {{v[0-9]+}}, #1 ;CHECK-NEXT: orr.16b ;CHECK-NEXT: ret - %tmp1 = load <16 x i8>* %A - %tmp4 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp4 = load <16 x i8>, <16 x i8>* %B %tmp3 = shl <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> %tmp5 = or <16 x i8> %tmp3, %tmp4 ret <16 x i8> %tmp5 @@ -1787,8 +1787,8 @@ define <8 x i16> @shl_orr8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK: shl.8h v0, {{v[0-9]+}}, #1 ;CHECK-NEXT: orr.16b ;CHECK-NEXT: ret - %tmp1 = load <8 x i16>* %A - %tmp4 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp4 = load <8 x i16>, <8 x i16>* %B %tmp3 = shl <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %tmp5 = or <8 x i16> %tmp3, %tmp4 ret <8 x i16> %tmp5 @@ -1799,8 +1799,8 @@ define <4 x i32> @shl_orr4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK: shl.4s v0, {{v[0-9]+}}, #1 ;CHECK-NEXT: orr.16b ;CHECK-NEXT: ret - %tmp1 = load <4 x i32>* %A - %tmp4 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp4 = load <4 x i32>, <4 x i32>* %B %tmp3 = shl <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1> %tmp5 = or <4 x i32> %tmp3, %tmp4 ret <4 x i32> %tmp5 @@ -1811,8 +1811,8 @@ define <2 x i64> @shl_orr2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK: shl.2d v0, {{v[0-9]+}}, #1 ;CHECK-NEXT: orr.16b ;CHECK-NEXT: ret - %tmp1 = load <2 x i64>* %A - %tmp4 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp4 = load <2 x i64>, <2 x i64>* %B %tmp3 = shl <2 x i64> %tmp1, <i64 1, i64 1> %tmp5 = or <2 x i64> %tmp3, %tmp4 ret <2 x i64> %tmp5 @@ -1838,8 +1838,8 @@ define <4 x i32> @shll_high(<8 x i16> %in) { define <8 x i8> @sli8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: sli8b: ;CHECK: sli.8b v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.vsli.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, i32 1) ret <8 x i8> %tmp3 } @@ -1847,8 +1847,8 @@ define <8 x i8> @sli8b(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @sli4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: sli4h: ;CHECK: sli.4h v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.vsli.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, i32 1) ret <4 x i16> %tmp3 } @@ -1856,8 +1856,8 @@ define <4 x i16> @sli4h(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @sli2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: sli2s: ;CHECK: sli.2s v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.vsli.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, i32 1) ret <2 x i32> %tmp3 } @@ -1865,8 +1865,8 @@ define <2 x i32> @sli2s(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <1 x i64> @sli1d(<1 x i64>* %A, <1 x i64>* %B) nounwind { ;CHECK-LABEL: sli1d: ;CHECK: sli d0, {{d[0-9]+}}, #1 - %tmp1 = load <1 x i64>* %A - %tmp2 = load <1 x i64>* %B + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = load <1 x i64>, <1 x i64>* %B %tmp3 = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, i32 1) ret <1 x i64> %tmp3 } @@ -1874,8 +1874,8 @@ define <1 x i64> @sli1d(<1 x i64>* %A, <1 x i64>* %B) nounwind { define <16 x i8> @sli16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: sli16b: ;CHECK: sli.16b v0, {{v[0-9]+}}, #1 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = call <16 x i8> @llvm.aarch64.neon.vsli.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, i32 1) ret <16 x i8> %tmp3 } @@ -1883,8 +1883,8 @@ define <16 x i8> @sli16b(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @sli8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: sli8h: ;CHECK: sli.8h v0, {{v[0-9]+}}, #1 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i16> @llvm.aarch64.neon.vsli.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, i32 1) ret <8 x i16> %tmp3 } @@ -1892,8 +1892,8 @@ define <8 x i16> @sli8h(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @sli4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: sli4s: ;CHECK: sli.4s v0, {{v[0-9]+}}, #1 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i32> @llvm.aarch64.neon.vsli.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, i32 1) ret <4 x i32> %tmp3 } @@ -1901,8 +1901,8 @@ define <4 x i32> @sli4s(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @sli2d(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: sli2d: ;CHECK: sli.2d v0, {{v[0-9]+}}, #1 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i64> @llvm.aarch64.neon.vsli.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, i32 1) ret <2 x i64> %tmp3 } diff --git a/test/CodeGen/AArch64/arm64-vshr.ll b/test/CodeGen/AArch64/arm64-vshr.ll index 21eb579..8d263f2 100644 --- a/test/CodeGen/AArch64/arm64-vshr.ll +++ b/test/CodeGen/AArch64/arm64-vshr.ll @@ -10,8 +10,8 @@ entry: %b.addr = alloca <8 x i16>, align 16 store <8 x i16> %a, <8 x i16>* %a.addr, align 16 store <8 x i16> %b, <8 x i16>* %b.addr, align 16 - %0 = load <8 x i16>* %a.addr, align 16 - %1 = load <8 x i16>* %b.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %a.addr, align 16 + %1 = load <8 x i16>, <8 x i16>* %b.addr, align 16 %shr = ashr <8 x i16> %0, %1 ret <8 x i16> %shr } @@ -25,8 +25,8 @@ entry: %b.addr = alloca <4 x i32>, align 32 store <4 x i32> %a, <4 x i32>* %a.addr, align 32 store <4 x i32> %b, <4 x i32>* %b.addr, align 32 - %0 = load <4 x i32>* %a.addr, align 32 - %1 = load <4 x i32>* %b.addr, align 32 + %0 = load <4 x i32>, <4 x i32>* %a.addr, align 32 + %1 = load <4 x i32>, <4 x i32>* %b.addr, align 32 %shr = ashr <4 x i32> %0, %1 ret <4 x i32> %shr } @@ -40,8 +40,8 @@ entry: %b.addr = alloca <8 x i16>, align 16 store <8 x i16> %a, <8 x i16>* %a.addr, align 16 store <8 x i16> %b, <8 x i16>* %b.addr, align 16 - %0 = load <8 x i16>* %a.addr, align 16 - %1 = load <8 x i16>* %b.addr, align 16 + %0 = load <8 x i16>, <8 x i16>* %a.addr, align 16 + %1 = load <8 x i16>, <8 x i16>* %b.addr, align 16 %shr = lshr <8 x i16> %0, %1 ret <8 x i16> %shr } diff --git a/test/CodeGen/AArch64/arm64-vsqrt.ll b/test/CodeGen/AArch64/arm64-vsqrt.ll index 02b7c7e..20aebd9 100644 --- a/test/CodeGen/AArch64/arm64-vsqrt.ll +++ b/test/CodeGen/AArch64/arm64-vsqrt.ll @@ -3,8 +3,8 @@ define <2 x float> @frecps_2s(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: frecps_2s: ;CHECK: frecps.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -12,8 +12,8 @@ define <2 x float> @frecps_2s(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x float> @frecps_4s(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: frecps_4s: ;CHECK: frecps.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } @@ -21,8 +21,8 @@ define <4 x float> @frecps_4s(<4 x float>* %A, <4 x float>* %B) nounwind { define <2 x double> @frecps_2d(<2 x double>* %A, <2 x double>* %B) nounwind { ;CHECK-LABEL: frecps_2d: ;CHECK: frecps.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B %tmp3 = call <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double> %tmp1, <2 x double> %tmp2) ret <2 x double> %tmp3 } @@ -35,8 +35,8 @@ declare <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double>, <2 x double>) define <2 x float> @frsqrts_2s(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK-LABEL: frsqrts_2s: ;CHECK: frsqrts.2s - %tmp1 = load <2 x float>* %A - %tmp2 = load <2 x float>* %B + %tmp1 = load <2 x float>, <2 x float>* %A + %tmp2 = load <2 x float>, <2 x float>* %B %tmp3 = call <2 x float> @llvm.aarch64.neon.frsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) ret <2 x float> %tmp3 } @@ -44,8 +44,8 @@ define <2 x float> @frsqrts_2s(<2 x float>* %A, <2 x float>* %B) nounwind { define <4 x float> @frsqrts_4s(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK-LABEL: frsqrts_4s: ;CHECK: frsqrts.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = call <4 x float> @llvm.aarch64.neon.frsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) ret <4 x float> %tmp3 } @@ -53,8 +53,8 @@ define <4 x float> @frsqrts_4s(<4 x float>* %A, <4 x float>* %B) nounwind { define <2 x double> @frsqrts_2d(<2 x double>* %A, <2 x double>* %B) nounwind { ;CHECK-LABEL: frsqrts_2d: ;CHECK: frsqrts.2d - %tmp1 = load <2 x double>* %A - %tmp2 = load <2 x double>* %B + %tmp1 = load <2 x double>, <2 x double>* %A + %tmp2 = load <2 x double>, <2 x double>* %B %tmp3 = call <2 x double> @llvm.aarch64.neon.frsqrts.v2f64(<2 x double> %tmp1, <2 x double> %tmp2) ret <2 x double> %tmp3 } @@ -66,7 +66,7 @@ declare <2 x double> @llvm.aarch64.neon.frsqrts.v2f64(<2 x double>, <2 x double> define <2 x float> @frecpe_2s(<2 x float>* %A) nounwind { ;CHECK-LABEL: frecpe_2s: ;CHECK: frecpe.2s - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp3 = call <2 x float> @llvm.aarch64.neon.frecpe.v2f32(<2 x float> %tmp1) ret <2 x float> %tmp3 } @@ -74,7 +74,7 @@ define <2 x float> @frecpe_2s(<2 x float>* %A) nounwind { define <4 x float> @frecpe_4s(<4 x float>* %A) nounwind { ;CHECK-LABEL: frecpe_4s: ;CHECK: frecpe.4s - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp3 = call <4 x float> @llvm.aarch64.neon.frecpe.v4f32(<4 x float> %tmp1) ret <4 x float> %tmp3 } @@ -82,7 +82,7 @@ define <4 x float> @frecpe_4s(<4 x float>* %A) nounwind { define <2 x double> @frecpe_2d(<2 x double>* %A) nounwind { ;CHECK-LABEL: frecpe_2d: ;CHECK: frecpe.2d - %tmp1 = load <2 x double>* %A + %tmp1 = load <2 x double>, <2 x double>* %A %tmp3 = call <2 x double> @llvm.aarch64.neon.frecpe.v2f64(<2 x double> %tmp1) ret <2 x double> %tmp3 } @@ -90,7 +90,7 @@ define <2 x double> @frecpe_2d(<2 x double>* %A) nounwind { define float @frecpe_s(float* %A) nounwind { ;CHECK-LABEL: frecpe_s: ;CHECK: frecpe s0, {{s[0-9]+}} - %tmp1 = load float* %A + %tmp1 = load float, float* %A %tmp3 = call float @llvm.aarch64.neon.frecpe.f32(float %tmp1) ret float %tmp3 } @@ -98,7 +98,7 @@ define float @frecpe_s(float* %A) nounwind { define double @frecpe_d(double* %A) nounwind { ;CHECK-LABEL: frecpe_d: ;CHECK: frecpe d0, {{d[0-9]+}} - %tmp1 = load double* %A + %tmp1 = load double, double* %A %tmp3 = call double @llvm.aarch64.neon.frecpe.f64(double %tmp1) ret double %tmp3 } @@ -112,7 +112,7 @@ declare double @llvm.aarch64.neon.frecpe.f64(double) nounwind readnone define float @frecpx_s(float* %A) nounwind { ;CHECK-LABEL: frecpx_s: ;CHECK: frecpx s0, {{s[0-9]+}} - %tmp1 = load float* %A + %tmp1 = load float, float* %A %tmp3 = call float @llvm.aarch64.neon.frecpx.f32(float %tmp1) ret float %tmp3 } @@ -120,7 +120,7 @@ define float @frecpx_s(float* %A) nounwind { define double @frecpx_d(double* %A) nounwind { ;CHECK-LABEL: frecpx_d: ;CHECK: frecpx d0, {{d[0-9]+}} - %tmp1 = load double* %A + %tmp1 = load double, double* %A %tmp3 = call double @llvm.aarch64.neon.frecpx.f64(double %tmp1) ret double %tmp3 } @@ -131,7 +131,7 @@ declare double @llvm.aarch64.neon.frecpx.f64(double) nounwind readnone define <2 x float> @frsqrte_2s(<2 x float>* %A) nounwind { ;CHECK-LABEL: frsqrte_2s: ;CHECK: frsqrte.2s - %tmp1 = load <2 x float>* %A + %tmp1 = load <2 x float>, <2 x float>* %A %tmp3 = call <2 x float> @llvm.aarch64.neon.frsqrte.v2f32(<2 x float> %tmp1) ret <2 x float> %tmp3 } @@ -139,7 +139,7 @@ define <2 x float> @frsqrte_2s(<2 x float>* %A) nounwind { define <4 x float> @frsqrte_4s(<4 x float>* %A) nounwind { ;CHECK-LABEL: frsqrte_4s: ;CHECK: frsqrte.4s - %tmp1 = load <4 x float>* %A + %tmp1 = load <4 x float>, <4 x float>* %A %tmp3 = call <4 x float> @llvm.aarch64.neon.frsqrte.v4f32(<4 x float> %tmp1) ret <4 x float> %tmp3 } @@ -147,7 +147,7 @@ define <4 x float> @frsqrte_4s(<4 x float>* %A) nounwind { define <2 x double> @frsqrte_2d(<2 x double>* %A) nounwind { ;CHECK-LABEL: frsqrte_2d: ;CHECK: frsqrte.2d - %tmp1 = load <2 x double>* %A + %tmp1 = load <2 x double>, <2 x double>* %A %tmp3 = call <2 x double> @llvm.aarch64.neon.frsqrte.v2f64(<2 x double> %tmp1) ret <2 x double> %tmp3 } @@ -155,7 +155,7 @@ define <2 x double> @frsqrte_2d(<2 x double>* %A) nounwind { define float @frsqrte_s(float* %A) nounwind { ;CHECK-LABEL: frsqrte_s: ;CHECK: frsqrte s0, {{s[0-9]+}} - %tmp1 = load float* %A + %tmp1 = load float, float* %A %tmp3 = call float @llvm.aarch64.neon.frsqrte.f32(float %tmp1) ret float %tmp3 } @@ -163,7 +163,7 @@ define float @frsqrte_s(float* %A) nounwind { define double @frsqrte_d(double* %A) nounwind { ;CHECK-LABEL: frsqrte_d: ;CHECK: frsqrte d0, {{d[0-9]+}} - %tmp1 = load double* %A + %tmp1 = load double, double* %A %tmp3 = call double @llvm.aarch64.neon.frsqrte.f64(double %tmp1) ret double %tmp3 } @@ -177,7 +177,7 @@ declare double @llvm.aarch64.neon.frsqrte.f64(double) nounwind readnone define <2 x i32> @urecpe_2s(<2 x i32>* %A) nounwind { ;CHECK-LABEL: urecpe_2s: ;CHECK: urecpe.2s - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.urecpe.v2i32(<2 x i32> %tmp1) ret <2 x i32> %tmp3 } @@ -185,7 +185,7 @@ define <2 x i32> @urecpe_2s(<2 x i32>* %A) nounwind { define <4 x i32> @urecpe_4s(<4 x i32>* %A) nounwind { ;CHECK-LABEL: urecpe_4s: ;CHECK: urecpe.4s - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i32> @llvm.aarch64.neon.urecpe.v4i32(<4 x i32> %tmp1) ret <4 x i32> %tmp3 } @@ -196,7 +196,7 @@ declare <4 x i32> @llvm.aarch64.neon.urecpe.v4i32(<4 x i32>) nounwind readnone define <2 x i32> @ursqrte_2s(<2 x i32>* %A) nounwind { ;CHECK-LABEL: ursqrte_2s: ;CHECK: ursqrte.2s - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp3 = call <2 x i32> @llvm.aarch64.neon.ursqrte.v2i32(<2 x i32> %tmp1) ret <2 x i32> %tmp3 } @@ -204,7 +204,7 @@ define <2 x i32> @ursqrte_2s(<2 x i32>* %A) nounwind { define <4 x i32> @ursqrte_4s(<4 x i32>* %A) nounwind { ;CHECK-LABEL: ursqrte_4s: ;CHECK: ursqrte.4s - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp3 = call <4 x i32> @llvm.aarch64.neon.ursqrte.v4i32(<4 x i32> %tmp1) ret <4 x i32> %tmp3 } diff --git a/test/CodeGen/AArch64/arm64-vsra.ll b/test/CodeGen/AArch64/arm64-vsra.ll index 5e9cef3..d480dfe 100644 --- a/test/CodeGen/AArch64/arm64-vsra.ll +++ b/test/CodeGen/AArch64/arm64-vsra.ll @@ -3,8 +3,8 @@ define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vsras8: ;CHECK: ssra.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = ashr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > %tmp4 = add <8 x i8> %tmp1, %tmp3 ret <8 x i8> %tmp4 @@ -13,8 +13,8 @@ define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vsras16: ;CHECK: ssra.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = ashr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 > %tmp4 = add <4 x i16> %tmp1, %tmp3 ret <4 x i16> %tmp4 @@ -23,8 +23,8 @@ define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vsras32: ;CHECK: ssra.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = ashr <2 x i32> %tmp2, < i32 31, i32 31 > %tmp4 = add <2 x i32> %tmp1, %tmp3 ret <2 x i32> %tmp4 @@ -33,8 +33,8 @@ define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vsraQs8: ;CHECK: ssra.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = ashr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > %tmp4 = add <16 x i8> %tmp1, %tmp3 ret <16 x i8> %tmp4 @@ -43,8 +43,8 @@ define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vsraQs16: ;CHECK: ssra.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = ashr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 > %tmp4 = add <8 x i16> %tmp1, %tmp3 ret <8 x i16> %tmp4 @@ -53,8 +53,8 @@ define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vsraQs32: ;CHECK: ssra.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = ashr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 > %tmp4 = add <4 x i32> %tmp1, %tmp3 ret <4 x i32> %tmp4 @@ -63,8 +63,8 @@ define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vsraQs64: ;CHECK: ssra.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = ashr <2 x i64> %tmp2, < i64 63, i64 63 > %tmp4 = add <2 x i64> %tmp1, %tmp3 ret <2 x i64> %tmp4 @@ -73,8 +73,8 @@ define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vsrau8: ;CHECK: usra.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = lshr <8 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > %tmp4 = add <8 x i8> %tmp1, %tmp3 ret <8 x i8> %tmp4 @@ -83,8 +83,8 @@ define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: vsrau16: ;CHECK: usra.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = lshr <4 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15 > %tmp4 = add <4 x i16> %tmp1, %tmp3 ret <4 x i16> %tmp4 @@ -93,8 +93,8 @@ define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: vsrau32: ;CHECK: usra.2s - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = lshr <2 x i32> %tmp2, < i32 31, i32 31 > %tmp4 = add <2 x i32> %tmp1, %tmp3 ret <2 x i32> %tmp4 @@ -104,8 +104,8 @@ define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: vsraQu8: ;CHECK: usra.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = lshr <16 x i8> %tmp2, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > %tmp4 = add <16 x i8> %tmp1, %tmp3 ret <16 x i8> %tmp4 @@ -114,8 +114,8 @@ define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vsraQu16: ;CHECK: usra.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = lshr <8 x i16> %tmp2, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 > %tmp4 = add <8 x i16> %tmp1, %tmp3 ret <8 x i16> %tmp4 @@ -124,8 +124,8 @@ define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: vsraQu32: ;CHECK: usra.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = lshr <4 x i32> %tmp2, < i32 31, i32 31, i32 31, i32 31 > %tmp4 = add <4 x i32> %tmp1, %tmp3 ret <4 x i32> %tmp4 @@ -134,8 +134,8 @@ define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: vsraQu64: ;CHECK: usra.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = lshr <2 x i64> %tmp2, < i64 63, i64 63 > %tmp4 = add <2 x i64> %tmp1, %tmp3 ret <2 x i64> %tmp4 diff --git a/test/CodeGen/AArch64/arm64-vsub.ll b/test/CodeGen/AArch64/arm64-vsub.ll index c2c8755..6b44b56 100644 --- a/test/CodeGen/AArch64/arm64-vsub.ll +++ b/test/CodeGen/AArch64/arm64-vsub.ll @@ -3,8 +3,8 @@ define <8 x i8> @subhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: subhn8b: ;CHECK: subhn.8b - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i8> %tmp3 } @@ -12,8 +12,8 @@ define <8 x i8> @subhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i16> @subhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: subhn4h: ;CHECK: subhn.4h - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.subhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i16> %tmp3 } @@ -21,8 +21,8 @@ define <4 x i16> @subhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i32> @subhn2s(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: subhn2s: ;CHECK: subhn.2s - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.subhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i32> %tmp3 } @@ -64,8 +64,8 @@ declare <8 x i8> @llvm.aarch64.neon.subhn.v8i8(<8 x i16>, <8 x i16>) nounwind re define <8 x i8> @rsubhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: rsubhn8b: ;CHECK: rsubhn.8b - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) ret <8 x i8> %tmp3 } @@ -73,8 +73,8 @@ define <8 x i8> @rsubhn8b(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <4 x i16> @rsubhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: rsubhn4h: ;CHECK: rsubhn.4h - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) ret <4 x i16> %tmp3 } @@ -82,8 +82,8 @@ define <4 x i16> @rsubhn4h(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <2 x i32> @rsubhn2s(<2 x i64>* %A, <2 x i64>* %B) nounwind { ;CHECK-LABEL: rsubhn2s: ;CHECK: rsubhn.2s - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i64>, <2 x i64>* %B %tmp3 = call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2) ret <2 x i32> %tmp3 } @@ -125,8 +125,8 @@ declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind r define <8 x i16> @ssubl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: ssubl8h: ;CHECK: ssubl.8h - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = sext <8 x i8> %tmp1 to <8 x i16> %tmp4 = sext <8 x i8> %tmp2 to <8 x i16> %tmp5 = sub <8 x i16> %tmp3, %tmp4 @@ -136,8 +136,8 @@ define <8 x i16> @ssubl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @ssubl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: ssubl4s: ;CHECK: ssubl.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = sext <4 x i16> %tmp1 to <4 x i32> %tmp4 = sext <4 x i16> %tmp2 to <4 x i32> %tmp5 = sub <4 x i32> %tmp3, %tmp4 @@ -147,8 +147,8 @@ define <4 x i32> @ssubl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @ssubl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: ssubl2d: ;CHECK: ssubl.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = sext <2 x i32> %tmp1 to <2 x i64> %tmp4 = sext <2 x i32> %tmp2 to <2 x i64> %tmp5 = sub <2 x i64> %tmp3, %tmp4 @@ -158,11 +158,11 @@ define <2 x i64> @ssubl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @ssubl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: ssubl2_8h: ;CHECK: ssubl2.8h - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %high1 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %ext1 = sext <8 x i8> %high1 to <8 x i16> - %tmp2 = load <16 x i8>* %B + %tmp2 = load <16 x i8>, <16 x i8>* %B %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %ext2 = sext <8 x i8> %high2 to <8 x i16> @@ -173,11 +173,11 @@ define <8 x i16> @ssubl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @ssubl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: ssubl2_4s: ;CHECK: ssubl2.4s - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %high1 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %ext1 = sext <4 x i16> %high1 to <4 x i32> - %tmp2 = load <8 x i16>* %B + %tmp2 = load <8 x i16>, <8 x i16>* %B %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %ext2 = sext <4 x i16> %high2 to <4 x i32> @@ -188,11 +188,11 @@ define <4 x i32> @ssubl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @ssubl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: ssubl2_2d: ;CHECK: ssubl2.2d - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %high1 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %ext1 = sext <2 x i32> %high1 to <2 x i64> - %tmp2 = load <4 x i32>* %B + %tmp2 = load <4 x i32>, <4 x i32>* %B %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %ext2 = sext <2 x i32> %high2 to <2 x i64> @@ -203,8 +203,8 @@ define <2 x i64> @ssubl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <8 x i16> @usubl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: usubl8h: ;CHECK: usubl.8h - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = zext <8 x i8> %tmp1 to <8 x i16> %tmp4 = zext <8 x i8> %tmp2 to <8 x i16> %tmp5 = sub <8 x i16> %tmp3, %tmp4 @@ -214,8 +214,8 @@ define <8 x i16> @usubl8h(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @usubl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: usubl4s: ;CHECK: usubl.4s - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = zext <4 x i16> %tmp1 to <4 x i32> %tmp4 = zext <4 x i16> %tmp2 to <4 x i32> %tmp5 = sub <4 x i32> %tmp3, %tmp4 @@ -225,8 +225,8 @@ define <4 x i32> @usubl4s(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @usubl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: usubl2d: ;CHECK: usubl.2d - %tmp1 = load <2 x i32>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = zext <2 x i32> %tmp1 to <2 x i64> %tmp4 = zext <2 x i32> %tmp2 to <2 x i64> %tmp5 = sub <2 x i64> %tmp3, %tmp4 @@ -236,11 +236,11 @@ define <2 x i64> @usubl2d(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @usubl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: usubl2_8h: ;CHECK: usubl2.8h - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %high1 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %ext1 = zext <8 x i8> %high1 to <8 x i16> - %tmp2 = load <16 x i8>* %B + %tmp2 = load <16 x i8>, <16 x i8>* %B %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %ext2 = zext <8 x i8> %high2 to <8 x i16> @@ -251,11 +251,11 @@ define <8 x i16> @usubl2_8h(<16 x i8>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @usubl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: usubl2_4s: ;CHECK: usubl2.4s - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %high1 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %ext1 = zext <4 x i16> %high1 to <4 x i32> - %tmp2 = load <8 x i16>* %B + %tmp2 = load <8 x i16>, <8 x i16>* %B %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %ext2 = zext <4 x i16> %high2 to <4 x i32> @@ -266,11 +266,11 @@ define <4 x i32> @usubl2_4s(<8 x i16>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @usubl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: usubl2_2d: ;CHECK: usubl2.2d - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %high1 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %ext1 = zext <2 x i32> %high1 to <2 x i64> - %tmp2 = load <4 x i32>* %B + %tmp2 = load <4 x i32>, <4 x i32>* %B %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %ext2 = zext <2 x i32> %high2 to <2 x i64> @@ -281,8 +281,8 @@ define <2 x i64> @usubl2_2d(<4 x i32>* %A, <4 x i32>* %B) nounwind { define <8 x i16> @ssubw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: ssubw8h: ;CHECK: ssubw.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = sext <8 x i8> %tmp2 to <8 x i16> %tmp4 = sub <8 x i16> %tmp1, %tmp3 ret <8 x i16> %tmp4 @@ -291,8 +291,8 @@ define <8 x i16> @ssubw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @ssubw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: ssubw4s: ;CHECK: ssubw.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = sext <4 x i16> %tmp2 to <4 x i32> %tmp4 = sub <4 x i32> %tmp1, %tmp3 ret <4 x i32> %tmp4 @@ -301,8 +301,8 @@ define <4 x i32> @ssubw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @ssubw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: ssubw2d: ;CHECK: ssubw.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = sext <2 x i32> %tmp2 to <2 x i64> %tmp4 = sub <2 x i64> %tmp1, %tmp3 ret <2 x i64> %tmp4 @@ -311,9 +311,9 @@ define <2 x i64> @ssubw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @ssubw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: ssubw2_8h: ;CHECK: ssubw2.8h - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A - %tmp2 = load <16 x i8>* %B + %tmp2 = load <16 x i8>, <16 x i8>* %B %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %ext2 = sext <8 x i8> %high2 to <8 x i16> @@ -324,9 +324,9 @@ define <8 x i16> @ssubw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @ssubw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: ssubw2_4s: ;CHECK: ssubw2.4s - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A - %tmp2 = load <8 x i16>* %B + %tmp2 = load <8 x i16>, <8 x i16>* %B %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %ext2 = sext <4 x i16> %high2 to <4 x i32> @@ -337,9 +337,9 @@ define <4 x i32> @ssubw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @ssubw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: ssubw2_2d: ;CHECK: ssubw2.2d - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A - %tmp2 = load <4 x i32>* %B + %tmp2 = load <4 x i32>, <4 x i32>* %B %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %ext2 = sext <2 x i32> %high2 to <2 x i64> @@ -350,8 +350,8 @@ define <2 x i64> @ssubw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind { define <8 x i16> @usubw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: usubw8h: ;CHECK: usubw.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = zext <8 x i8> %tmp2 to <8 x i16> %tmp4 = sub <8 x i16> %tmp1, %tmp3 ret <8 x i16> %tmp4 @@ -360,8 +360,8 @@ define <8 x i16> @usubw8h(<8 x i16>* %A, <8 x i8>* %B) nounwind { define <4 x i32> @usubw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind { ;CHECK-LABEL: usubw4s: ;CHECK: usubw.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = zext <4 x i16> %tmp2 to <4 x i32> %tmp4 = sub <4 x i32> %tmp1, %tmp3 ret <4 x i32> %tmp4 @@ -370,8 +370,8 @@ define <4 x i32> @usubw4s(<4 x i32>* %A, <4 x i16>* %B) nounwind { define <2 x i64> @usubw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind { ;CHECK-LABEL: usubw2d: ;CHECK: usubw.2d - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = load <2 x i32>, <2 x i32>* %B %tmp3 = zext <2 x i32> %tmp2 to <2 x i64> %tmp4 = sub <2 x i64> %tmp1, %tmp3 ret <2 x i64> %tmp4 @@ -380,9 +380,9 @@ define <2 x i64> @usubw2d(<2 x i64>* %A, <2 x i32>* %B) nounwind { define <8 x i16> @usubw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind { ;CHECK-LABEL: usubw2_8h: ;CHECK: usubw2.8h - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A - %tmp2 = load <16 x i8>* %B + %tmp2 = load <16 x i8>, <16 x i8>* %B %high2 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %ext2 = zext <8 x i8> %high2 to <8 x i16> @@ -393,9 +393,9 @@ define <8 x i16> @usubw2_8h(<8 x i16>* %A, <16 x i8>* %B) nounwind { define <4 x i32> @usubw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: usubw2_4s: ;CHECK: usubw2.4s - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A - %tmp2 = load <8 x i16>* %B + %tmp2 = load <8 x i16>, <8 x i16>* %B %high2 = shufflevector <8 x i16> %tmp2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %ext2 = zext <4 x i16> %high2 to <4 x i32> @@ -406,9 +406,9 @@ define <4 x i32> @usubw2_4s(<4 x i32>* %A, <8 x i16>* %B) nounwind { define <2 x i64> @usubw2_2d(<2 x i64>* %A, <4 x i32>* %B) nounwind { ;CHECK-LABEL: usubw2_2d: ;CHECK: usubw2.2d - %tmp1 = load <2 x i64>* %A + %tmp1 = load <2 x i64>, <2 x i64>* %A - %tmp2 = load <4 x i32>* %B + %tmp2 = load <4 x i32>, <4 x i32>* %B %high2 = shufflevector <4 x i32> %tmp2, <4 x i32> undef, <2 x i32> <i32 2, i32 3> %ext2 = zext <2 x i32> %high2 to <2 x i64> diff --git a/test/CodeGen/AArch64/arm64-weak-reference.ll b/test/CodeGen/AArch64/arm64-weak-reference.ll index b2135e0..e8074de 100644 --- a/test/CodeGen/AArch64/arm64-weak-reference.ll +++ b/test/CodeGen/AArch64/arm64-weak-reference.ll @@ -5,6 +5,6 @@ define i32 @fn() nounwind ssp { ; CHECK-LABEL: fn: ; CHECK: .weak_reference - %val = load i32* @x, align 4 + %val = load i32, i32* @x, align 4 ret i32 %val } diff --git a/test/CodeGen/AArch64/arm64-xaluo.ll b/test/CodeGen/AArch64/arm64-xaluo.ll index 59ce684..ce9c0a6 100644 --- a/test/CodeGen/AArch64/arm64-xaluo.ll +++ b/test/CodeGen/AArch64/arm64-xaluo.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s ; ; Get the actual value of the overflow bit. diff --git a/test/CodeGen/AArch64/arm64-zextload-unscaled.ll b/test/CodeGen/AArch64/arm64-zextload-unscaled.ll index c475dbd..321cf10 100644 --- a/test/CodeGen/AArch64/arm64-zextload-unscaled.ll +++ b/test/CodeGen/AArch64/arm64-zextload-unscaled.ll @@ -6,8 +6,8 @@ define void @test_zextloadi1_unscaled(i1* %base) { ; CHECK-LABEL: test_zextloadi1_unscaled: ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-7] - %addr = getelementptr i1* %base, i32 -7 - %val = load i1* %addr, align 1 + %addr = getelementptr i1, i1* %base, i32 -7 + %val = load i1, i1* %addr, align 1 %extended = zext i1 %val to i32 store i32 %extended, i32* @var32, align 4 @@ -18,8 +18,8 @@ define void @test_zextloadi8_unscaled(i8* %base) { ; CHECK-LABEL: test_zextloadi8_unscaled: ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-7] - %addr = getelementptr i8* %base, i32 -7 - %val = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %base, i32 -7 + %val = load i8, i8* %addr, align 1 %extended = zext i8 %val to i32 store i32 %extended, i32* @var32, align 4 @@ -30,8 +30,8 @@ define void @test_zextloadi16_unscaled(i16* %base) { ; CHECK-LABEL: test_zextloadi16_unscaled: ; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #-14] - %addr = getelementptr i16* %base, i32 -7 - %val = load i16* %addr, align 2 + %addr = getelementptr i16, i16* %base, i32 -7 + %val = load i16, i16* %addr, align 2 %extended = zext i16 %val to i32 store i32 %extended, i32* @var32, align 4 diff --git a/test/CodeGen/AArch64/arm64-zip.ll b/test/CodeGen/AArch64/arm64-zip.ll index 304b280..ddce002 100644 --- a/test/CodeGen/AArch64/arm64-zip.ll +++ b/test/CodeGen/AArch64/arm64-zip.ll @@ -5,8 +5,8 @@ define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: zip1.8b ;CHECK: zip2.8b ;CHECK-NEXT: add.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> %tmp5 = add <8 x i8> %tmp3, %tmp4 @@ -18,8 +18,8 @@ define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK: zip1.4h ;CHECK: zip2.4h ;CHECK-NEXT: add.4h - %tmp1 = load <4 x i16>* %A - %tmp2 = load <4 x i16>* %B + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = load <4 x i16>, <4 x i16>* %B %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5> %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7> %tmp5 = add <4 x i16> %tmp3, %tmp4 @@ -31,8 +31,8 @@ define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK: zip1.16b ;CHECK: zip2.16b ;CHECK-NEXT: add.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> %tmp5 = add <16 x i8> %tmp3, %tmp4 @@ -44,8 +44,8 @@ define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK: zip1.8h ;CHECK: zip2.8h ;CHECK-NEXT: add.8h - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = load <8 x i16>, <8 x i16>* %B %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> %tmp5 = add <8 x i16> %tmp3, %tmp4 @@ -57,8 +57,8 @@ define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK: zip1.4s ;CHECK: zip2.4s ;CHECK-NEXT: add.4s - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = load <4 x i32>, <4 x i32>* %B %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5> %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7> %tmp5 = add <4 x i32> %tmp3, %tmp4 @@ -70,8 +70,8 @@ define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK: zip1.4s ;CHECK: zip2.4s ;CHECK-NEXT: fadd.4s - %tmp1 = load <4 x float>* %A - %tmp2 = load <4 x float>* %B + %tmp1 = load <4 x float>, <4 x float>* %A + %tmp2 = load <4 x float>, <4 x float>* %B %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5> %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7> %tmp5 = fadd <4 x float> %tmp3, %tmp4 @@ -85,8 +85,8 @@ define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: zip1.8b ;CHECK: zip2.8b ;CHECK-NEXT: add.8b - %tmp1 = load <8 x i8>* %A - %tmp2 = load <8 x i8>* %B + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = load <8 x i8>, <8 x i8>* %B %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 undef, i32 1, i32 9, i32 undef, i32 10, i32 3, i32 11> %tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 undef, i32 undef, i32 15> %tmp5 = add <8 x i8> %tmp3, %tmp4 @@ -98,8 +98,8 @@ define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK: zip1.16b ;CHECK: zip2.16b ;CHECK-NEXT: add.16b - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = load <16 x i8>, <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 undef, i32 undef, i32 undef, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> %tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 undef, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 undef, i32 14, i32 30, i32 undef, i32 31> %tmp5 = add <16 x i8> %tmp3, %tmp4 diff --git a/test/CodeGen/AArch64/assertion-rc-mismatch.ll b/test/CodeGen/AArch64/assertion-rc-mismatch.ll index bcf206e..c216c44 100644 --- a/test/CodeGen/AArch64/assertion-rc-mismatch.ll +++ b/test/CodeGen/AArch64/assertion-rc-mismatch.ll @@ -11,8 +11,8 @@ if: br label %end else: %tmp3 = call i8* @llvm.returnaddress(i32 0) - %ptr = getelementptr inbounds i8* %tmp3, i64 -16 - %ld = load i8* %ptr, align 4 + %ptr = getelementptr inbounds i8, i8* %tmp3, i64 -16 + %ld = load i8, i8* %ptr, align 4 %tmp2 = inttoptr i8 %ld to i8* br label %end end: diff --git a/test/CodeGen/AArch64/atomic-ops-not-barriers.ll b/test/CodeGen/AArch64/atomic-ops-not-barriers.ll index da095a0..44e7771 100644 --- a/test/CodeGen/AArch64/atomic-ops-not-barriers.ll +++ b/test/CodeGen/AArch64/atomic-ops-not-barriers.ll @@ -4,7 +4,7 @@ define i32 @foo(i32* %var, i1 %cond) { ; CHECK-LABEL: foo: br i1 %cond, label %atomic_ver, label %simple_ver simple_ver: - %oldval = load i32* %var + %oldval = load i32, i32* %var %newval = add nsw i32 %oldval, -1 store i32 %newval, i32* %var br label %somewhere diff --git a/test/CodeGen/AArch64/atomic-ops.ll b/test/CodeGen/AArch64/atomic-ops.ll index ef209e9..cb90cae 100644 --- a/test/CodeGen/AArch64/atomic-ops.ll +++ b/test/CodeGen/AArch64/atomic-ops.ll @@ -972,7 +972,7 @@ define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { define i8 @test_atomic_load_monotonic_i8() nounwind { ; CHECK-LABEL: test_atomic_load_monotonic_i8: - %val = load atomic i8* @var8 monotonic, align 1 + %val = load atomic i8, i8* @var8 monotonic, align 1 ; CHECK-NOT: dmb ; CHECK: adrp x[[HIADDR:[0-9]+]], var8 ; CHECK: ldrb w0, [x[[HIADDR]], {{#?}}:lo12:var8] @@ -986,7 +986,7 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind { %addr_int = add i64 %base, %off %addr = inttoptr i64 %addr_int to i8* - %val = load atomic i8* %addr monotonic, align 1 + %val = load atomic i8, i8* %addr monotonic, align 1 ; CHECK-NOT: dmb ; CHECK: ldrb w0, [x0, x1] ; CHECK-NOT: dmb @@ -996,7 +996,7 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind { define i8 @test_atomic_load_acquire_i8() nounwind { ; CHECK-LABEL: test_atomic_load_acquire_i8: - %val = load atomic i8* @var8 acquire, align 1 + %val = load atomic i8, i8* @var8 acquire, align 1 ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK-NOT: dmb @@ -1009,7 +1009,7 @@ define i8 @test_atomic_load_acquire_i8() nounwind { define i8 @test_atomic_load_seq_cst_i8() nounwind { ; CHECK-LABEL: test_atomic_load_seq_cst_i8: - %val = load atomic i8* @var8 seq_cst, align 1 + %val = load atomic i8, i8* @var8 seq_cst, align 1 ; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var8 ; CHECK-NOT: dmb @@ -1022,7 +1022,7 @@ define i8 @test_atomic_load_seq_cst_i8() nounwind { define i16 @test_atomic_load_monotonic_i16() nounwind { ; CHECK-LABEL: test_atomic_load_monotonic_i16: - %val = load atomic i16* @var16 monotonic, align 2 + %val = load atomic i16, i16* @var16 monotonic, align 2 ; CHECK-NOT: dmb ; CHECK: adrp x[[HIADDR:[0-9]+]], var16 ; CHECK-NOT: dmb @@ -1037,7 +1037,7 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind %addr_int = add i64 %base, %off %addr = inttoptr i64 %addr_int to i32* - %val = load atomic i32* %addr monotonic, align 4 + %val = load atomic i32, i32* %addr monotonic, align 4 ; CHECK-NOT: dmb ; CHECK: ldr w0, [x0, x1] ; CHECK-NOT: dmb @@ -1047,7 +1047,7 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind define i64 @test_atomic_load_seq_cst_i64() nounwind { ; CHECK-LABEL: test_atomic_load_seq_cst_i64: - %val = load atomic i64* @var64 seq_cst, align 8 + %val = load atomic i64, i64* @var64 seq_cst, align 8 ; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var64 ; CHECK-NOT: dmb diff --git a/test/CodeGen/AArch64/basic-pic.ll b/test/CodeGen/AArch64/basic-pic.ll index 62d41bc..8765a6d 100644 --- a/test/CodeGen/AArch64/basic-pic.ll +++ b/test/CodeGen/AArch64/basic-pic.ll @@ -5,7 +5,7 @@ define i32 @get_globalvar() { ; CHECK-LABEL: get_globalvar: - %val = load i32* @var + %val = load i32, i32* @var ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var ; CHECK: ldr x[[GOTLOC:[0-9]+]], [x[[GOTHI]], {{#?}}:got_lo12:var] ; CHECK: ldr w0, [x[[GOTLOC]]] @@ -16,7 +16,7 @@ define i32 @get_globalvar() { define i32* @get_globalvaraddr() { ; CHECK-LABEL: get_globalvaraddr: - %val = load i32* @var + %val = load i32, i32* @var ; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var ; CHECK: ldr x0, [x[[GOTHI]], {{#?}}:got_lo12:var] @@ -28,7 +28,7 @@ define i32* @get_globalvaraddr() { define i32 @get_hiddenvar() { ; CHECK-LABEL: get_hiddenvar: - %val = load i32* @hiddenvar + %val = load i32, i32* @hiddenvar ; CHECK: adrp x[[HI:[0-9]+]], hiddenvar ; CHECK: ldr w0, [x[[HI]], {{#?}}:lo12:hiddenvar] @@ -38,7 +38,7 @@ define i32 @get_hiddenvar() { define i32* @get_hiddenvaraddr() { ; CHECK-LABEL: get_hiddenvaraddr: - %val = load i32* @hiddenvar + %val = load i32, i32* @hiddenvar ; CHECK: adrp [[HI:x[0-9]+]], hiddenvar ; CHECK: add x0, [[HI]], {{#?}}:lo12:hiddenvar diff --git a/test/CodeGen/AArch64/bitfield-insert-0.ll b/test/CodeGen/AArch64/bitfield-insert-0.ll index da0ed8a..21f3895 100644 --- a/test/CodeGen/AArch64/bitfield-insert-0.ll +++ b/test/CodeGen/AArch64/bitfield-insert-0.ll @@ -6,10 +6,10 @@ define void @test_bfi0(i32* %existing, i32* %new) { ; CHECK: bfxil {{w[0-9]+}}, {{w[0-9]+}}, #0, #18 - %oldval = load volatile i32* %existing + %oldval = load volatile i32, i32* %existing %oldval_keep = and i32 %oldval, 4294705152 ; 0xfffc_0000 - %newval = load volatile i32* %new + %newval = load volatile i32, i32* %new %newval_masked = and i32 %newval, 262143 ; = 0x0003_ffff %combined = or i32 %newval_masked, %oldval_keep diff --git a/test/CodeGen/AArch64/bitfield-insert.ll b/test/CodeGen/AArch64/bitfield-insert.ll index 2369a55..9b731fa 100644 --- a/test/CodeGen/AArch64/bitfield-insert.ll +++ b/test/CodeGen/AArch64/bitfield-insert.ll @@ -28,10 +28,10 @@ define void @test_whole32(i32* %existing, i32* %new) { ; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #26, #5 - %oldval = load volatile i32* %existing + %oldval = load volatile i32, i32* %existing %oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff - %newval = load volatile i32* %new + %newval = load volatile i32, i32* %new %newval_shifted = shl i32 %newval, 26 %newval_masked = and i32 %newval_shifted, 2080374784 ; = 0x7c000000 @@ -47,10 +47,10 @@ define void @test_whole64(i64* %existing, i64* %new) { ; CHECK-NOT: and ; CHECK: ret - %oldval = load volatile i64* %existing + %oldval = load volatile i64, i64* %existing %oldval_keep = and i64 %oldval, 18446742974265032703 ; = 0xffffff0003ffffffL - %newval = load volatile i64* %new + %newval = load volatile i64, i64* %new %newval_shifted = shl i64 %newval, 26 %newval_masked = and i64 %newval_shifted, 1099444518912 ; = 0xfffc000000 @@ -68,10 +68,10 @@ define void @test_whole32_from64(i64* %existing, i64* %new) { ; CHECK: ret - %oldval = load volatile i64* %existing + %oldval = load volatile i64, i64* %existing %oldval_keep = and i64 %oldval, 4294901760 ; = 0xffff0000 - %newval = load volatile i64* %new + %newval = load volatile i64, i64* %new %newval_masked = and i64 %newval, 65535 ; = 0xffff %combined = or i64 %oldval_keep, %newval_masked @@ -86,10 +86,10 @@ define void @test_32bit_masked(i32 *%existing, i32 *%new) { ; CHECK: and ; CHECK: bfi [[INSERT:w[0-9]+]], {{w[0-9]+}}, #3, #4 - %oldval = load volatile i32* %existing + %oldval = load volatile i32, i32* %existing %oldval_keep = and i32 %oldval, 135 ; = 0x87 - %newval = load volatile i32* %new + %newval = load volatile i32, i32* %new %newval_shifted = shl i32 %newval, 3 %newval_masked = and i32 %newval_shifted, 120 ; = 0x78 @@ -104,10 +104,10 @@ define void @test_64bit_masked(i64 *%existing, i64 *%new) { ; CHECK: and ; CHECK: bfi [[INSERT:x[0-9]+]], {{x[0-9]+}}, #40, #8 - %oldval = load volatile i64* %existing + %oldval = load volatile i64, i64* %existing %oldval_keep = and i64 %oldval, 1095216660480 ; = 0xff_0000_0000 - %newval = load volatile i64* %new + %newval = load volatile i64, i64* %new %newval_shifted = shl i64 %newval, 40 %newval_masked = and i64 %newval_shifted, 280375465082880 ; = 0xff00_0000_0000 @@ -124,10 +124,10 @@ define void @test_32bit_complexmask(i32 *%existing, i32 *%new) { ; CHECK: and ; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #3, #4 - %oldval = load volatile i32* %existing + %oldval = load volatile i32, i32* %existing %oldval_keep = and i32 %oldval, 647 ; = 0x287 - %newval = load volatile i32* %new + %newval = load volatile i32, i32* %new %newval_shifted = shl i32 %newval, 3 %newval_masked = and i32 %newval_shifted, 120 ; = 0x278 @@ -144,10 +144,10 @@ define void @test_32bit_badmask(i32 *%existing, i32 *%new) { ; CHECK-NOT: bfm ; CHECK: ret - %oldval = load volatile i32* %existing + %oldval = load volatile i32, i32* %existing %oldval_keep = and i32 %oldval, 135 ; = 0x87 - %newval = load volatile i32* %new + %newval = load volatile i32, i32* %new %newval_shifted = shl i32 %newval, 3 %newval_masked = and i32 %newval_shifted, 632 ; = 0x278 @@ -164,10 +164,10 @@ define void @test_64bit_badmask(i64 *%existing, i64 *%new) { ; CHECK-NOT: bfm ; CHECK: ret - %oldval = load volatile i64* %existing + %oldval = load volatile i64, i64* %existing %oldval_keep = and i64 %oldval, 135 ; = 0x87 - %newval = load volatile i64* %new + %newval = load volatile i64, i64* %new %newval_shifted = shl i64 %newval, 3 %newval_masked = and i64 %newval_shifted, 664 ; = 0x278 @@ -182,10 +182,10 @@ define void @test_64bit_badmask(i64 *%existing, i64 *%new) { define void @test_32bit_with_shr(i32* %existing, i32* %new) { ; CHECK-LABEL: test_32bit_with_shr: - %oldval = load volatile i32* %existing + %oldval = load volatile i32, i32* %existing %oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff - %newval = load i32* %new + %newval = load i32, i32* %new %newval_shifted = shl i32 %newval, 12 %newval_masked = and i32 %newval_shifted, 2080374784 ; = 0x7c000000 diff --git a/test/CodeGen/AArch64/bitfield.ll b/test/CodeGen/AArch64/bitfield.ll index 0e12653..78399c8 100644 --- a/test/CodeGen/AArch64/bitfield.ll +++ b/test/CodeGen/AArch64/bitfield.ll @@ -180,7 +180,7 @@ define i32 @test_ubfx32(i32* %addr) { ; CHECK-LABEL: test_ubfx32: ; CHECK: ubfx {{w[0-9]+}}, {{w[0-9]+}}, #23, #3 - %fields = load i32* %addr + %fields = load i32, i32* %addr %shifted = lshr i32 %fields, 23 %masked = and i32 %shifted, 7 ret i32 %masked @@ -189,7 +189,7 @@ define i32 @test_ubfx32(i32* %addr) { define i64 @test_ubfx64(i64* %addr) { ; CHECK-LABEL: test_ubfx64: ; CHECK: ubfx {{x[0-9]+}}, {{x[0-9]+}}, #25, #10 - %fields = load i64* %addr + %fields = load i64, i64* %addr %shifted = lshr i64 %fields, 25 %masked = and i64 %shifted, 1023 ret i64 %masked @@ -199,7 +199,7 @@ define i32 @test_sbfx32(i32* %addr) { ; CHECK-LABEL: test_sbfx32: ; CHECK: sbfx {{w[0-9]+}}, {{w[0-9]+}}, #6, #3 - %fields = load i32* %addr + %fields = load i32, i32* %addr %shifted = shl i32 %fields, 23 %extended = ashr i32 %shifted, 29 ret i32 %extended @@ -209,7 +209,7 @@ define i64 @test_sbfx64(i64* %addr) { ; CHECK-LABEL: test_sbfx64: ; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #63 - %fields = load i64* %addr + %fields = load i64, i64* %addr %shifted = shl i64 %fields, 1 %extended = ashr i64 %shifted, 1 ret i64 %extended diff --git a/test/CodeGen/AArch64/blockaddress.ll b/test/CodeGen/AArch64/blockaddress.ll index 3a5dbdc..e93c69f 100644 --- a/test/CodeGen/AArch64/blockaddress.ll +++ b/test/CodeGen/AArch64/blockaddress.ll @@ -6,7 +6,7 @@ define void @test_blockaddress() { ; CHECK-LABEL: test_blockaddress: store volatile i8* blockaddress(@test_blockaddress, %block), i8** @addr - %val = load volatile i8** @addr + %val = load volatile i8*, i8** @addr indirectbr i8* %val, [label %block] ; CHECK: adrp [[DEST_HI:x[0-9]+]], [[DEST_LBL:.Ltmp[0-9]+]] ; CHECK: add [[DEST:x[0-9]+]], [[DEST_HI]], {{#?}}:lo12:[[DEST_LBL]] diff --git a/test/CodeGen/AArch64/bool-loads.ll b/test/CodeGen/AArch64/bool-loads.ll index 881aeaa..b0ee1b4 100644 --- a/test/CodeGen/AArch64/bool-loads.ll +++ b/test/CodeGen/AArch64/bool-loads.ll @@ -5,7 +5,7 @@ define i32 @test_sextloadi32() { ; CHECK-LABEL: test_sextloadi32 - %val = load i1* @var + %val = load i1, i1* @var %ret = sext i1 %val to i32 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var] ; CHECK: {{sbfx x[0-9]+, x[0-9]+, #0, #1|sbfx w[0-9]+, w[0-9]+, #0, #1}} @@ -17,7 +17,7 @@ define i32 @test_sextloadi32() { define i64 @test_sextloadi64() { ; CHECK-LABEL: test_sextloadi64 - %val = load i1* @var + %val = load i1, i1* @var %ret = sext i1 %val to i64 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var] ; CHECK: {{sbfx x[0-9]+, x[0-9]+, #0, #1}} @@ -32,7 +32,7 @@ define i32 @test_zextloadi32() { ; It's not actually necessary that "ret" is next, but as far as LLVM ; is concerned only 0 or 1 should be loadable so no extension is ; necessary. - %val = load i1* @var + %val = load i1, i1* @var %ret = zext i1 %val to i32 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var] @@ -46,7 +46,7 @@ define i64 @test_zextloadi64() { ; It's not actually necessary that "ret" is next, but as far as LLVM ; is concerned only 0 or 1 should be loadable so no extension is ; necessary. - %val = load i1* @var + %val = load i1, i1* @var %ret = zext i1 %val to i64 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var] diff --git a/test/CodeGen/AArch64/br-to-eh-lpad.ll b/test/CodeGen/AArch64/br-to-eh-lpad.ll index 20bffd9..e948b87 100644 --- a/test/CodeGen/AArch64/br-to-eh-lpad.ll +++ b/test/CodeGen/AArch64/br-to-eh-lpad.ll @@ -30,12 +30,12 @@ invoke.cont7: unreachable if.end50.thread: - tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str1, i64 0, i64 0), i32 125) - tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str1, i64 0, i64 0), i32 128) + tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @.str1, i64 0, i64 0), i32 125) + tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @.str1, i64 0, i64 0), i32 128) unreachable invoke.cont33: - tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str1, i64 0, i64 0), i32 119) + tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @.str1, i64 0, i64 0), i32 119) unreachable invoke.cont41: @@ -51,7 +51,7 @@ lpad40: br label %finally.catchall finally.catchall: - tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str1, i64 0, i64 0), i32 125) + tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @.str1, i64 0, i64 0), i32 125) unreachable } diff --git a/test/CodeGen/AArch64/breg.ll b/test/CodeGen/AArch64/breg.ll index 9524044..42061a8 100644 --- a/test/CodeGen/AArch64/breg.ll +++ b/test/CodeGen/AArch64/breg.ll @@ -4,7 +4,7 @@ define void @foo() { ; CHECK-LABEL: foo: - %lab = load i8** @stored_label + %lab = load i8*, i8** @stored_label indirectbr i8* %lab, [label %otherlab, label %retlab] ; CHECK: adrp {{x[0-9]+}}, stored_label ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:stored_label] diff --git a/test/CodeGen/AArch64/callee-save.ll b/test/CodeGen/AArch64/callee-save.ll index 046e6ce..1234039 100644 --- a/test/CodeGen/AArch64/callee-save.ll +++ b/test/CodeGen/AArch64/callee-save.ll @@ -12,38 +12,38 @@ define void @foo() { ; Create lots of live variables to exhaust the supply of ; caller-saved registers - %val1 = load volatile float* @var - %val2 = load volatile float* @var - %val3 = load volatile float* @var - %val4 = load volatile float* @var - %val5 = load volatile float* @var - %val6 = load volatile float* @var - %val7 = load volatile float* @var - %val8 = load volatile float* @var - %val9 = load volatile float* @var - %val10 = load volatile float* @var - %val11 = load volatile float* @var - %val12 = load volatile float* @var - %val13 = load volatile float* @var - %val14 = load volatile float* @var - %val15 = load volatile float* @var - %val16 = load volatile float* @var - %val17 = load volatile float* @var - %val18 = load volatile float* @var - %val19 = load volatile float* @var - %val20 = load volatile float* @var - %val21 = load volatile float* @var - %val22 = load volatile float* @var - %val23 = load volatile float* @var - %val24 = load volatile float* @var - %val25 = load volatile float* @var - %val26 = load volatile float* @var - %val27 = load volatile float* @var - %val28 = load volatile float* @var - %val29 = load volatile float* @var - %val30 = load volatile float* @var - %val31 = load volatile float* @var - %val32 = load volatile float* @var + %val1 = load volatile float, float* @var + %val2 = load volatile float, float* @var + %val3 = load volatile float, float* @var + %val4 = load volatile float, float* @var + %val5 = load volatile float, float* @var + %val6 = load volatile float, float* @var + %val7 = load volatile float, float* @var + %val8 = load volatile float, float* @var + %val9 = load volatile float, float* @var + %val10 = load volatile float, float* @var + %val11 = load volatile float, float* @var + %val12 = load volatile float, float* @var + %val13 = load volatile float, float* @var + %val14 = load volatile float, float* @var + %val15 = load volatile float, float* @var + %val16 = load volatile float, float* @var + %val17 = load volatile float, float* @var + %val18 = load volatile float, float* @var + %val19 = load volatile float, float* @var + %val20 = load volatile float, float* @var + %val21 = load volatile float, float* @var + %val22 = load volatile float, float* @var + %val23 = load volatile float, float* @var + %val24 = load volatile float, float* @var + %val25 = load volatile float, float* @var + %val26 = load volatile float, float* @var + %val27 = load volatile float, float* @var + %val28 = load volatile float, float* @var + %val29 = load volatile float, float* @var + %val30 = load volatile float, float* @var + %val31 = load volatile float, float* @var + %val32 = load volatile float, float* @var store volatile float %val1, float* @var store volatile float %val2, float* @var diff --git a/test/CodeGen/AArch64/cmpwithshort.ll b/test/CodeGen/AArch64/cmpwithshort.ll index 14efdcc..6590997 100644 --- a/test/CodeGen/AArch64/cmpwithshort.ll +++ b/test/CodeGen/AArch64/cmpwithshort.ll @@ -5,8 +5,8 @@ define i16 @test_1cmp_signed_1(i16* %ptr1) { ; CHECK: ldrsh ; CHECK-NEXT: cmn entry: - %addr = getelementptr inbounds i16* %ptr1, i16 0 - %val = load i16* %addr, align 2 + %addr = getelementptr inbounds i16, i16* %ptr1, i16 0 + %val = load i16, i16* %addr, align 2 %cmp = icmp eq i16 %val, -1 br i1 %cmp, label %if, label %if.then if: @@ -20,8 +20,8 @@ define i16 @test_1cmp_signed_2(i16* %ptr1) { ; CHECK: ldrsh ; CHECK-NEXT: cmn entry: - %addr = getelementptr inbounds i16* %ptr1, i16 0 - %val = load i16* %addr, align 2 + %addr = getelementptr inbounds i16, i16* %ptr1, i16 0 + %val = load i16, i16* %addr, align 2 %cmp = icmp sge i16 %val, -1 br i1 %cmp, label %if, label %if.then if: @@ -35,8 +35,8 @@ define i16 @test_1cmp_unsigned_1(i16* %ptr1) { ; CHECK: ldrsh ; CHECK-NEXT: cmn entry: - %addr = getelementptr inbounds i16* %ptr1, i16 0 - %val = load i16* %addr, align 2 + %addr = getelementptr inbounds i16, i16* %ptr1, i16 0 + %val = load i16, i16* %addr, align 2 %cmp = icmp uge i16 %val, -1 br i1 %cmp, label %if, label %if.then if: diff --git a/test/CodeGen/AArch64/code-model-large-abs.ll b/test/CodeGen/AArch64/code-model-large-abs.ll index ca92500..1680815 100644 --- a/test/CodeGen/AArch64/code-model-large-abs.ll +++ b/test/CodeGen/AArch64/code-model-large-abs.ll @@ -18,7 +18,7 @@ define i8* @global_addr() { define i8 @global_i8() { ; CHECK-LABEL: global_i8: - %val = load i8* @var8 + %val = load i8, i8* @var8 ret i8 %val ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8 @@ -29,7 +29,7 @@ define i8 @global_i8() { define i16 @global_i16() { ; CHECK-LABEL: global_i16: - %val = load i16* @var16 + %val = load i16, i16* @var16 ret i16 %val ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16 @@ -40,7 +40,7 @@ define i16 @global_i16() { define i32 @global_i32() { ; CHECK-LABEL: global_i32: - %val = load i32* @var32 + %val = load i32, i32* @var32 ret i32 %val ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32 @@ -51,7 +51,7 @@ define i32 @global_i32() { define i64 @global_i64() { ; CHECK-LABEL: global_i64: - %val = load i64* @var64 + %val = load i64, i64* @var64 ret i64 %val ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64 diff --git a/test/CodeGen/AArch64/combine-comparisons-by-cse.ll b/test/CodeGen/AArch64/combine-comparisons-by-cse.ll index 3686a1f..c78faba 100644 --- a/test/CodeGen/AArch64/combine-comparisons-by-cse.ll +++ b/test/CodeGen/AArch64/combine-comparisons-by-cse.ll @@ -15,13 +15,13 @@ define i32 @combine_gt_ge_10() #0 { ; CHECK-NOT: cmp ; CHECK: b.lt entry: - %0 = load i32* @a, align 4 + %0 = load i32, i32* @a, align 4 %cmp = icmp sgt i32 %0, 10 br i1 %cmp, label %land.lhs.true, label %lor.lhs.false land.lhs.true: ; preds = %entry - %1 = load i32* @b, align 4 - %2 = load i32* @c, align 4 + %1 = load i32, i32* @b, align 4 + %2 = load i32, i32* @c, align 4 %cmp1 = icmp eq i32 %1, %2 br i1 %cmp1, label %return, label %land.lhs.true3 @@ -30,8 +30,8 @@ lor.lhs.false: ; preds = %entry br i1 %cmp2, label %land.lhs.true3, label %if.end land.lhs.true3: ; preds = %lor.lhs.false, %land.lhs.true - %3 = load i32* @b, align 4 - %4 = load i32* @d, align 4 + %3 = load i32, i32* @b, align 4 + %4 = load i32, i32* @d, align 4 %cmp4 = icmp eq i32 %3, %4 br i1 %cmp4, label %return, label %if.end @@ -52,13 +52,13 @@ define i32 @combine_gt_lt_5() #0 { ; CHECK-NOT: cmp ; CHECK: b.ge entry: - %0 = load i32* @a, align 4 + %0 = load i32, i32* @a, align 4 %cmp = icmp sgt i32 %0, 5 br i1 %cmp, label %land.lhs.true, label %lor.lhs.false land.lhs.true: ; preds = %entry - %1 = load i32* @b, align 4 - %2 = load i32* @c, align 4 + %1 = load i32, i32* @b, align 4 + %2 = load i32, i32* @c, align 4 %cmp1 = icmp eq i32 %1, %2 br i1 %cmp1, label %return, label %if.end @@ -67,8 +67,8 @@ lor.lhs.false: ; preds = %entry br i1 %cmp2, label %land.lhs.true3, label %if.end land.lhs.true3: ; preds = %lor.lhs.false - %3 = load i32* @b, align 4 - %4 = load i32* @d, align 4 + %3 = load i32, i32* @b, align 4 + %4 = load i32, i32* @d, align 4 %cmp4 = icmp eq i32 %3, %4 br i1 %cmp4, label %return, label %if.end @@ -89,13 +89,13 @@ define i32 @combine_lt_ge_5() #0 { ; CHECK-NOT: cmp ; CHECK: b.gt entry: - %0 = load i32* @a, align 4 + %0 = load i32, i32* @a, align 4 %cmp = icmp slt i32 %0, 5 br i1 %cmp, label %land.lhs.true, label %lor.lhs.false land.lhs.true: ; preds = %entry - %1 = load i32* @b, align 4 - %2 = load i32* @c, align 4 + %1 = load i32, i32* @b, align 4 + %2 = load i32, i32* @c, align 4 %cmp1 = icmp eq i32 %1, %2 br i1 %cmp1, label %return, label %land.lhs.true3 @@ -104,8 +104,8 @@ lor.lhs.false: ; preds = %entry br i1 %cmp2, label %land.lhs.true3, label %if.end land.lhs.true3: ; preds = %lor.lhs.false, %land.lhs.true - %3 = load i32* @b, align 4 - %4 = load i32* @d, align 4 + %3 = load i32, i32* @b, align 4 + %4 = load i32, i32* @d, align 4 %cmp4 = icmp eq i32 %3, %4 br i1 %cmp4, label %return, label %if.end @@ -126,13 +126,13 @@ define i32 @combine_lt_gt_5() #0 { ; CHECK-NOT: cmp ; CHECK: b.le entry: - %0 = load i32* @a, align 4 + %0 = load i32, i32* @a, align 4 %cmp = icmp slt i32 %0, 5 br i1 %cmp, label %land.lhs.true, label %lor.lhs.false land.lhs.true: ; preds = %entry - %1 = load i32* @b, align 4 - %2 = load i32* @c, align 4 + %1 = load i32, i32* @b, align 4 + %2 = load i32, i32* @c, align 4 %cmp1 = icmp eq i32 %1, %2 br i1 %cmp1, label %return, label %if.end @@ -141,8 +141,8 @@ lor.lhs.false: ; preds = %entry br i1 %cmp2, label %land.lhs.true3, label %if.end land.lhs.true3: ; preds = %lor.lhs.false - %3 = load i32* @b, align 4 - %4 = load i32* @d, align 4 + %3 = load i32, i32* @b, align 4 + %4 = load i32, i32* @d, align 4 %cmp4 = icmp eq i32 %3, %4 br i1 %cmp4, label %return, label %if.end @@ -163,13 +163,13 @@ define i32 @combine_gt_lt_n5() #0 { ; CHECK-NOT: cmn ; CHECK: b.ge entry: - %0 = load i32* @a, align 4 + %0 = load i32, i32* @a, align 4 %cmp = icmp sgt i32 %0, -5 br i1 %cmp, label %land.lhs.true, label %lor.lhs.false land.lhs.true: ; preds = %entry - %1 = load i32* @b, align 4 - %2 = load i32* @c, align 4 + %1 = load i32, i32* @b, align 4 + %2 = load i32, i32* @c, align 4 %cmp1 = icmp eq i32 %1, %2 br i1 %cmp1, label %return, label %if.end @@ -178,8 +178,8 @@ lor.lhs.false: ; preds = %entry br i1 %cmp2, label %land.lhs.true3, label %if.end land.lhs.true3: ; preds = %lor.lhs.false - %3 = load i32* @b, align 4 - %4 = load i32* @d, align 4 + %3 = load i32, i32* @b, align 4 + %4 = load i32, i32* @d, align 4 %cmp4 = icmp eq i32 %3, %4 br i1 %cmp4, label %return, label %if.end @@ -200,13 +200,13 @@ define i32 @combine_lt_gt_n5() #0 { ; CHECK-NOT: cmn ; CHECK: b.le entry: - %0 = load i32* @a, align 4 + %0 = load i32, i32* @a, align 4 %cmp = icmp slt i32 %0, -5 br i1 %cmp, label %land.lhs.true, label %lor.lhs.false land.lhs.true: ; preds = %entry - %1 = load i32* @b, align 4 - %2 = load i32* @c, align 4 + %1 = load i32, i32* @b, align 4 + %2 = load i32, i32* @c, align 4 %cmp1 = icmp eq i32 %1, %2 br i1 %cmp1, label %return, label %if.end @@ -215,8 +215,8 @@ lor.lhs.false: ; preds = %entry br i1 %cmp2, label %land.lhs.true3, label %if.end land.lhs.true3: ; preds = %lor.lhs.false - %3 = load i32* @b, align 4 - %4 = load i32* @d, align 4 + %3 = load i32, i32* @b, align 4 + %4 = load i32, i32* @d, align 4 %cmp4 = icmp eq i32 %3, %4 br i1 %cmp4, label %return, label %if.end @@ -237,18 +237,18 @@ declare %struct.Struct* @Update(%struct.Struct*) #1 ; no checks for this case, it just should be processed without errors define void @combine_non_adjacent_cmp_br(%struct.Struct* nocapture readonly %hdCall) #0 { entry: - %size = getelementptr inbounds %struct.Struct* %hdCall, i64 0, i32 0 - %0 = load i64* %size, align 8 + %size = getelementptr inbounds %struct.Struct, %struct.Struct* %hdCall, i64 0, i32 0 + %0 = load i64, i64* %size, align 8 br label %land.rhs land.rhs: %rp.06 = phi i64 [ %0, %entry ], [ %sub, %while.body ] - %1 = load i64* inttoptr (i64 24 to i64*), align 8 + %1 = load i64, i64* inttoptr (i64 24 to i64*), align 8 %cmp2 = icmp sgt i64 %1, 0 br i1 %cmp2, label %while.body, label %while.end while.body: - %2 = load %struct.Struct** @glob, align 8 + %2 = load %struct.Struct*, %struct.Struct** @glob, align 8 %call = tail call %struct.Struct* @Update(%struct.Struct* %2) #2 %sub = add nsw i64 %rp.06, -2 %cmp = icmp slt i64 %0, %rp.06 @@ -268,7 +268,7 @@ define i32 @do_nothing_if_resultant_opcodes_would_differ() #0 { ; CHECK: cmp ; CHECK: b.gt entry: - %0 = load i32* @a, align 4 + %0 = load i32, i32* @a, align 4 %cmp4 = icmp slt i32 %0, -1 br i1 %cmp4, label %while.body.preheader, label %while.end @@ -283,7 +283,7 @@ while.body: ; preds = %while.body, %while. br i1 %cmp, label %while.body, label %while.cond.while.end_crit_edge while.cond.while.end_crit_edge: ; preds = %while.body - %.pre = load i32* @a, align 4 + %.pre = load i32, i32* @a, align 4 br label %while.end while.end: ; preds = %while.cond.while.end_crit_edge, %entry @@ -292,8 +292,8 @@ while.end: ; preds = %while.cond.while.en br i1 %cmp1, label %land.lhs.true, label %if.end land.lhs.true: ; preds = %while.end - %2 = load i32* @b, align 4 - %3 = load i32* @d, align 4 + %2 = load i32, i32* @b, align 4 + %3 = load i32, i32* @d, align 4 %cmp2 = icmp eq i32 %2, %3 br i1 %cmp2, label %return, label %if.end @@ -312,7 +312,7 @@ define i32 @do_nothing_if_compares_can_not_be_adjusted_to_each_other() #0 { ; CHECK: cmn ; CHECK: b.lt entry: - %0 = load i32* @a, align 4 + %0 = load i32, i32* @a, align 4 %cmp4 = icmp slt i32 %0, 1 br i1 %cmp4, label %while.body.preheader, label %while.end @@ -330,13 +330,13 @@ while.end.loopexit: ; preds = %while.body br label %while.end while.end: ; preds = %while.end.loopexit, %entry - %1 = load i32* @c, align 4 + %1 = load i32, i32* @c, align 4 %cmp1 = icmp sgt i32 %1, -3 br i1 %cmp1, label %land.lhs.true, label %if.end land.lhs.true: ; preds = %while.end - %2 = load i32* @b, align 4 - %3 = load i32* @d, align 4 + %2 = load i32, i32* @b, align 4 + %3 = load i32, i32* @d, align 4 %cmp2 = icmp eq i32 %2, %3 br i1 %cmp2, label %return, label %if.end @@ -374,8 +374,8 @@ entry: br i1 %cmp, label %land.lhs.true, label %if.end land.lhs.true: ; preds = %entry - %arrayidx = getelementptr inbounds i8** %argv, i64 1 - %0 = load i8** %arrayidx, align 8 + %arrayidx = getelementptr inbounds i8*, i8** %argv, i64 1 + %0 = load i8*, i8** %arrayidx, align 8 %cmp1 = icmp eq i8* %0, null br i1 %cmp1, label %if.end, label %return diff --git a/test/CodeGen/AArch64/compare-branch.ll b/test/CodeGen/AArch64/compare-branch.ll index a1a87cf..4e0f69d 100644 --- a/test/CodeGen/AArch64/compare-branch.ll +++ b/test/CodeGen/AArch64/compare-branch.ll @@ -6,25 +6,25 @@ define void @foo() { ; CHECK-LABEL: foo: - %val1 = load volatile i32* @var32 + %val1 = load volatile i32, i32* @var32 %tst1 = icmp eq i32 %val1, 0 br i1 %tst1, label %end, label %test2 ; CHECK: cbz {{w[0-9]+}}, .LBB test2: - %val2 = load volatile i32* @var32 + %val2 = load volatile i32, i32* @var32 %tst2 = icmp ne i32 %val2, 0 br i1 %tst2, label %end, label %test3 ; CHECK: cbnz {{w[0-9]+}}, .LBB test3: - %val3 = load volatile i64* @var64 + %val3 = load volatile i64, i64* @var64 %tst3 = icmp eq i64 %val3, 0 br i1 %tst3, label %end, label %test4 ; CHECK: cbz {{x[0-9]+}}, .LBB test4: - %val4 = load volatile i64* @var64 + %val4 = load volatile i64, i64* @var64 %tst4 = icmp ne i64 %val4, 0 br i1 %tst4, label %end, label %test5 ; CHECK: cbnz {{x[0-9]+}}, .LBB diff --git a/test/CodeGen/AArch64/complex-copy-noneon.ll b/test/CodeGen/AArch64/complex-copy-noneon.ll index 4ae5478..b7c7043 100644 --- a/test/CodeGen/AArch64/complex-copy-noneon.ll +++ b/test/CodeGen/AArch64/complex-copy-noneon.ll @@ -8,13 +8,13 @@ define void @store_combine() nounwind { %src = alloca { double, double }, align 8 %dst = alloca { double, double }, align 8 - %src.realp = getelementptr inbounds { double, double }* %src, i32 0, i32 0 - %src.real = load double* %src.realp - %src.imagp = getelementptr inbounds { double, double }* %src, i32 0, i32 1 - %src.imag = load double* %src.imagp + %src.realp = getelementptr inbounds { double, double }, { double, double }* %src, i32 0, i32 0 + %src.real = load double, double* %src.realp + %src.imagp = getelementptr inbounds { double, double }, { double, double }* %src, i32 0, i32 1 + %src.imag = load double, double* %src.imagp - %dst.realp = getelementptr inbounds { double, double }* %dst, i32 0, i32 0 - %dst.imagp = getelementptr inbounds { double, double }* %dst, i32 0, i32 1 + %dst.realp = getelementptr inbounds { double, double }, { double, double }* %dst, i32 0, i32 0 + %dst.imagp = getelementptr inbounds { double, double }, { double, double }* %dst, i32 0, i32 1 store double %src.real, double* %dst.realp store double %src.imag, double* %dst.imagp ret void diff --git a/test/CodeGen/AArch64/complex-int-to-fp.ll b/test/CodeGen/AArch64/complex-int-to-fp.ll index 5c943f9..1102553 100644 --- a/test/CodeGen/AArch64/complex-int-to-fp.ll +++ b/test/CodeGen/AArch64/complex-int-to-fp.ll @@ -4,7 +4,7 @@ ; CHECK: scvtf ; CHECK: ret define void @autogen_SD19655(<2 x i64>* %addr, <2 x float>* %addrfloat) { - %T = load <2 x i64>* %addr + %T = load <2 x i64>, <2 x i64>* %addr %F = sitofp <2 x i64> %T to <2 x float> store <2 x float> %F, <2 x float>* %addrfloat ret void diff --git a/test/CodeGen/AArch64/concat_vector-truncate-combine.ll b/test/CodeGen/AArch64/concat_vector-truncate-combine.ll new file mode 100644 index 0000000..c510e27 --- /dev/null +++ b/test/CodeGen/AArch64/concat_vector-truncate-combine.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s -mtriple arm64-apple-darwin -asm-verbose=false | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +define <4 x i16> @test_concat_truncate_v2i64_to_v4i16(<2 x i64> %a, <2 x i64> %b) #0 { +entry: +; CHECK-LABEL: test_concat_truncate_v2i64_to_v4i16: +; CHECK-NEXT: uzp1.4s v0, v0, v1 +; CHECK-NEXT: xtn.4h v0, v0 +; CHECK-NEXT: ret + %at = trunc <2 x i64> %a to <2 x i16> + %bt = trunc <2 x i64> %b to <2 x i16> + %shuffle = shufflevector <2 x i16> %at, <2 x i16> %bt, <4 x i32> <i32 0, i32 1, i32 2, i32 3> + ret <4 x i16> %shuffle +} + +define <8 x i8> @test_concat_truncate_v4i32_to_v8i8(<4 x i32> %a, <4 x i32> %b) #0 { +entry: +; CHECK-LABEL: test_concat_truncate_v4i32_to_v8i8: +; CHECK-NEXT: uzp1.8h v0, v0, v1 +; CHECK-NEXT: xtn.8b v0, v0 +; CHECK-NEXT: ret + %at = trunc <4 x i32> %a to <4 x i8> + %bt = trunc <4 x i32> %b to <4 x i8> + %shuffle = shufflevector <4 x i8> %at, <4 x i8> %bt, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + ret <8 x i8> %shuffle +} + +define <8 x i16> @test_concat_truncate_v4i32_to_v8i16(<4 x i32> %a, <4 x i32> %b) #0 { +entry: +; CHECK-LABEL: test_concat_truncate_v4i32_to_v8i16: +; CHECK-NEXT: xtn.4h v0, v0 +; CHECK-NEXT: xtn2.8h v0, v1 +; CHECK-NEXT: ret + %at = trunc <4 x i32> %a to <4 x i16> + %bt = trunc <4 x i32> %b to <4 x i16> + %shuffle = shufflevector <4 x i16> %at, <4 x i16> %bt, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + ret <8 x i16> %shuffle +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AArch64/dag-combine-invaraints.ll b/test/CodeGen/AArch64/dag-combine-invaraints.ll index 115fc64..3614133 100644 --- a/test/CodeGen/AArch64/dag-combine-invaraints.ll +++ b/test/CodeGen/AArch64/dag-combine-invaraints.ll @@ -12,15 +12,15 @@ main_: store i32 0, i32* %tmp store i32 15, i32* %i32T, align 4 store i32 5, i32* %i32F, align 4 - %tmp6 = load i32* %tmp, align 4 + %tmp6 = load i32, i32* %tmp, align 4 %tmp7 = icmp ne i32 %tmp6, 0 %tmp8 = xor i1 %tmp7, true - %tmp9 = load i32* %i32T, align 4 - %tmp10 = load i32* %i32F, align 4 + %tmp9 = load i32, i32* %i32T, align 4 + %tmp10 = load i32, i32* %i32F, align 4 %DHSelect = select i1 %tmp8, i32 %tmp9, i32 %tmp10 store i32 %DHSelect, i32* %i32X, align 4 - %tmp15 = load i32* %i32X, align 4 - %tmp17 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str2, i32 0, i32 0), i32 %tmp15) + %tmp15 = load i32, i32* %i32X, align 4 + %tmp17 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str2, i32 0, i32 0), i32 %tmp15) ret i32 0 ; CHECK: main: diff --git a/test/CodeGen/AArch64/dp-3source.ll b/test/CodeGen/AArch64/dp-3source.ll index bd96ec7..3982fea 100644 --- a/test/CodeGen/AArch64/dp-3source.ll +++ b/test/CodeGen/AArch64/dp-3source.ll @@ -168,8 +168,8 @@ define i64 @test_umnegl(i32 %lhs, i32 %rhs) { define void @test_mneg(){ ; CHECK-LABEL: test_mneg: - %1 = load i32* @a, align 4 - %2 = load i32* @b, align 4 + %1 = load i32, i32* @a, align 4 + %2 = load i32, i32* @b, align 4 %3 = sub i32 0, %1 %4 = mul i32 %2, %3 store i32 %4, i32* @c, align 4 diff --git a/test/CodeGen/AArch64/dp1.ll b/test/CodeGen/AArch64/dp1.ll index 662b415..4247afa 100644 --- a/test/CodeGen/AArch64/dp1.ll +++ b/test/CodeGen/AArch64/dp1.ll @@ -5,7 +5,7 @@ define void @rev_i32() { ; CHECK-LABEL: rev_i32: - %val0_tmp = load i32* @var32 + %val0_tmp = load i32, i32* @var32 %val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp) ; CHECK: rev {{w[0-9]+}}, {{w[0-9]+}} store volatile i32 %val1_tmp, i32* @var32 @@ -14,7 +14,7 @@ define void @rev_i32() { define void @rev_i64() { ; CHECK-LABEL: rev_i64: - %val0_tmp = load i64* @var64 + %val0_tmp = load i64, i64* @var64 %val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp) ; CHECK: rev {{x[0-9]+}}, {{x[0-9]+}} store volatile i64 %val1_tmp, i64* @var64 @@ -23,7 +23,7 @@ define void @rev_i64() { define void @rev32_i64() { ; CHECK-LABEL: rev32_i64: - %val0_tmp = load i64* @var64 + %val0_tmp = load i64, i64* @var64 %val1_tmp = shl i64 %val0_tmp, 32 %val5_tmp = sub i64 64, 32 %val2_tmp = lshr i64 %val0_tmp, %val5_tmp @@ -36,7 +36,7 @@ define void @rev32_i64() { define void @rev16_i32() { ; CHECK-LABEL: rev16_i32: - %val0_tmp = load i32* @var32 + %val0_tmp = load i32, i32* @var32 %val1_tmp = shl i32 %val0_tmp, 16 %val2_tmp = lshr i32 %val0_tmp, 16 %val3_tmp = or i32 %val1_tmp, %val2_tmp @@ -48,7 +48,7 @@ define void @rev16_i32() { define void @clz_zerodef_i32() { ; CHECK-LABEL: clz_zerodef_i32: - %val0_tmp = load i32* @var32 + %val0_tmp = load i32, i32* @var32 %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 0) ; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}} store volatile i32 %val4_tmp, i32* @var32 @@ -57,7 +57,7 @@ define void @clz_zerodef_i32() { define void @clz_zerodef_i64() { ; CHECK-LABEL: clz_zerodef_i64: - %val0_tmp = load i64* @var64 + %val0_tmp = load i64, i64* @var64 %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 0) ; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}} store volatile i64 %val4_tmp, i64* @var64 @@ -66,7 +66,7 @@ define void @clz_zerodef_i64() { define void @clz_zeroundef_i32() { ; CHECK-LABEL: clz_zeroundef_i32: - %val0_tmp = load i32* @var32 + %val0_tmp = load i32, i32* @var32 %val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 1) ; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}} store volatile i32 %val4_tmp, i32* @var32 @@ -75,7 +75,7 @@ define void @clz_zeroundef_i32() { define void @clz_zeroundef_i64() { ; CHECK-LABEL: clz_zeroundef_i64: - %val0_tmp = load i64* @var64 + %val0_tmp = load i64, i64* @var64 %val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 1) ; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}} store volatile i64 %val4_tmp, i64* @var64 @@ -84,7 +84,7 @@ define void @clz_zeroundef_i64() { define void @cttz_zerodef_i32() { ; CHECK-LABEL: cttz_zerodef_i32: - %val0_tmp = load i32* @var32 + %val0_tmp = load i32, i32* @var32 %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 0) ; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}} ; CHECK: clz {{w[0-9]+}}, [[REVERSED]] @@ -94,7 +94,7 @@ define void @cttz_zerodef_i32() { define void @cttz_zerodef_i64() { ; CHECK-LABEL: cttz_zerodef_i64: - %val0_tmp = load i64* @var64 + %val0_tmp = load i64, i64* @var64 %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 0) ; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}} ; CHECK: clz {{x[0-9]+}}, [[REVERSED]] @@ -104,7 +104,7 @@ define void @cttz_zerodef_i64() { define void @cttz_zeroundef_i32() { ; CHECK-LABEL: cttz_zeroundef_i32: - %val0_tmp = load i32* @var32 + %val0_tmp = load i32, i32* @var32 %val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 1) ; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}} ; CHECK: clz {{w[0-9]+}}, [[REVERSED]] @@ -114,7 +114,7 @@ define void @cttz_zeroundef_i32() { define void @cttz_zeroundef_i64() { ; CHECK-LABEL: cttz_zeroundef_i64: - %val0_tmp = load i64* @var64 + %val0_tmp = load i64, i64* @var64 %val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 1) ; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}} ; CHECK: clz {{x[0-9]+}}, [[REVERSED]] @@ -126,7 +126,7 @@ define void @cttz_zeroundef_i64() { ; ISelLowering. define void @ctpop_i32() { ; CHECK-LABEL: ctpop_i32: - %val0_tmp = load i32* @var32 + %val0_tmp = load i32, i32* @var32 %val4_tmp = call i32 @llvm.ctpop.i32(i32 %val0_tmp) store volatile i32 %val4_tmp, i32* @var32 ret void @@ -134,7 +134,7 @@ define void @ctpop_i32() { define void @ctpop_i64() { ; CHECK-LABEL: ctpop_i64: - %val0_tmp = load i64* @var64 + %val0_tmp = load i64, i64* @var64 %val4_tmp = call i64 @llvm.ctpop.i64(i64 %val0_tmp) store volatile i64 %val4_tmp, i64* @var64 ret void diff --git a/test/CodeGen/AArch64/dp2.ll b/test/CodeGen/AArch64/dp2.ll index 71b3169..0cd2d7e 100644 --- a/test/CodeGen/AArch64/dp2.ll +++ b/test/CodeGen/AArch64/dp2.ll @@ -7,8 +7,8 @@ define void @rorv_i64() { ; CHECK-LABEL: rorv_i64: - %val0_tmp = load i64* @var64_0 - %val1_tmp = load i64* @var64_1 + %val0_tmp = load i64, i64* @var64_0 + %val1_tmp = load i64, i64* @var64_1 %val2_tmp = sub i64 64, %val1_tmp %val3_tmp = shl i64 %val0_tmp, %val2_tmp %val4_tmp = lshr i64 %val0_tmp, %val1_tmp @@ -20,8 +20,8 @@ define void @rorv_i64() { define void @asrv_i64() { ; CHECK-LABEL: asrv_i64: - %val0_tmp = load i64* @var64_0 - %val1_tmp = load i64* @var64_1 + %val0_tmp = load i64, i64* @var64_0 + %val1_tmp = load i64, i64* @var64_1 %val4_tmp = ashr i64 %val0_tmp, %val1_tmp ; CHECK: {{asr|asrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} store volatile i64 %val4_tmp, i64* @var64_1 @@ -30,8 +30,8 @@ define void @asrv_i64() { define void @lsrv_i64() { ; CHECK-LABEL: lsrv_i64: - %val0_tmp = load i64* @var64_0 - %val1_tmp = load i64* @var64_1 + %val0_tmp = load i64, i64* @var64_0 + %val1_tmp = load i64, i64* @var64_1 %val4_tmp = lshr i64 %val0_tmp, %val1_tmp ; CHECK: {{lsr|lsrv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} store volatile i64 %val4_tmp, i64* @var64_0 @@ -40,8 +40,8 @@ define void @lsrv_i64() { define void @lslv_i64() { ; CHECK-LABEL: lslv_i64: - %val0_tmp = load i64* @var64_0 - %val1_tmp = load i64* @var64_1 + %val0_tmp = load i64, i64* @var64_0 + %val1_tmp = load i64, i64* @var64_1 %val4_tmp = shl i64 %val0_tmp, %val1_tmp ; CHECK: {{lsl|lslv}} {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} store volatile i64 %val4_tmp, i64* @var64_1 @@ -50,8 +50,8 @@ define void @lslv_i64() { define void @udiv_i64() { ; CHECK-LABEL: udiv_i64: - %val0_tmp = load i64* @var64_0 - %val1_tmp = load i64* @var64_1 + %val0_tmp = load i64, i64* @var64_0 + %val1_tmp = load i64, i64* @var64_1 %val4_tmp = udiv i64 %val0_tmp, %val1_tmp ; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} store volatile i64 %val4_tmp, i64* @var64_0 @@ -60,8 +60,8 @@ define void @udiv_i64() { define void @sdiv_i64() { ; CHECK-LABEL: sdiv_i64: - %val0_tmp = load i64* @var64_0 - %val1_tmp = load i64* @var64_1 + %val0_tmp = load i64, i64* @var64_0 + %val1_tmp = load i64, i64* @var64_1 %val4_tmp = sdiv i64 %val0_tmp, %val1_tmp ; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} store volatile i64 %val4_tmp, i64* @var64_1 @@ -71,8 +71,8 @@ define void @sdiv_i64() { define void @lsrv_i32() { ; CHECK-LABEL: lsrv_i32: - %val0_tmp = load i32* @var32_0 - %val1_tmp = load i32* @var32_1 + %val0_tmp = load i32, i32* @var32_0 + %val1_tmp = load i32, i32* @var32_1 %val2_tmp = add i32 1, %val1_tmp %val4_tmp = lshr i32 %val0_tmp, %val2_tmp ; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} @@ -82,8 +82,8 @@ define void @lsrv_i32() { define void @lslv_i32() { ; CHECK-LABEL: lslv_i32: - %val0_tmp = load i32* @var32_0 - %val1_tmp = load i32* @var32_1 + %val0_tmp = load i32, i32* @var32_0 + %val1_tmp = load i32, i32* @var32_1 %val2_tmp = add i32 1, %val1_tmp %val4_tmp = shl i32 %val0_tmp, %val2_tmp ; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} @@ -93,8 +93,8 @@ define void @lslv_i32() { define void @rorv_i32() { ; CHECK-LABEL: rorv_i32: - %val0_tmp = load i32* @var32_0 - %val6_tmp = load i32* @var32_1 + %val0_tmp = load i32, i32* @var32_0 + %val6_tmp = load i32, i32* @var32_1 %val1_tmp = add i32 1, %val6_tmp %val2_tmp = sub i32 32, %val1_tmp %val3_tmp = shl i32 %val0_tmp, %val2_tmp @@ -107,8 +107,8 @@ define void @rorv_i32() { define void @asrv_i32() { ; CHECK-LABEL: asrv_i32: - %val0_tmp = load i32* @var32_0 - %val1_tmp = load i32* @var32_1 + %val0_tmp = load i32, i32* @var32_0 + %val1_tmp = load i32, i32* @var32_1 %val2_tmp = add i32 1, %val1_tmp %val4_tmp = ashr i32 %val0_tmp, %val2_tmp ; CHECK: {{asr|asrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} @@ -118,8 +118,8 @@ define void @asrv_i32() { define void @sdiv_i32() { ; CHECK-LABEL: sdiv_i32: - %val0_tmp = load i32* @var32_0 - %val1_tmp = load i32* @var32_1 + %val0_tmp = load i32, i32* @var32_0 + %val1_tmp = load i32, i32* @var32_1 %val4_tmp = sdiv i32 %val0_tmp, %val1_tmp ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} store volatile i32 %val4_tmp, i32* @var32_1 @@ -128,8 +128,8 @@ define void @sdiv_i32() { define void @udiv_i32() { ; CHECK-LABEL: udiv_i32: - %val0_tmp = load i32* @var32_0 - %val1_tmp = load i32* @var32_1 + %val0_tmp = load i32, i32* @var32_0 + %val1_tmp = load i32, i32* @var32_1 %val4_tmp = udiv i32 %val0_tmp, %val1_tmp ; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} store volatile i32 %val4_tmp, i32* @var32_0 @@ -141,7 +141,7 @@ define void @udiv_i32() { define i32 @test_lsl32() { ; CHECK-LABEL: test_lsl32: - %val = load i32* @var32_0 + %val = load i32, i32* @var32_0 %ret = shl i32 1, %val ; CHECK: {{lsl|lslv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} @@ -151,7 +151,7 @@ define i32 @test_lsl32() { define i32 @test_lsr32() { ; CHECK-LABEL: test_lsr32: - %val = load i32* @var32_0 + %val = load i32, i32* @var32_0 %ret = lshr i32 1, %val ; CHECK: {{lsr|lsrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} @@ -161,7 +161,7 @@ define i32 @test_lsr32() { define i32 @test_asr32(i32 %in) { ; CHECK-LABEL: test_asr32: - %val = load i32* @var32_0 + %val = load i32, i32* @var32_0 %ret = ashr i32 %in, %val ; CHECK: {{asr|asrv}} {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} diff --git a/test/CodeGen/AArch64/eliminate-trunc.ll b/test/CodeGen/AArch64/eliminate-trunc.ll index ea86a08..bc4ac7d 100644 --- a/test/CodeGen/AArch64/eliminate-trunc.ll +++ b/test/CodeGen/AArch64/eliminate-trunc.ll @@ -14,11 +14,11 @@ entry: for.body4.us: %indvars.iv = phi i64 [ 0, %for.body4.lr.ph.us ], [ %indvars.iv.next, %for.body4.us ] - %arrayidx6.us = getelementptr inbounds [8 x i8]* %a, i64 %indvars.iv26, i64 %indvars.iv - %0 = load i8* %arrayidx6.us, align 1 + %arrayidx6.us = getelementptr inbounds [8 x i8], [8 x i8]* %a, i64 %indvars.iv26, i64 %indvars.iv + %0 = load i8, i8* %arrayidx6.us, align 1 %idxprom7.us = zext i8 %0 to i64 - %arrayidx8.us = getelementptr inbounds i8* %box, i64 %idxprom7.us - %1 = load i8* %arrayidx8.us, align 1 + %arrayidx8.us = getelementptr inbounds i8, i8* %box, i64 %idxprom7.us + %1 = load i8, i8* %arrayidx8.us, align 1 store i8 %1, i8* %arrayidx6.us, align 1 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %2 = trunc i64 %indvars.iv.next to i32 diff --git a/test/CodeGen/AArch64/extern-weak.ll b/test/CodeGen/AArch64/extern-weak.ll index f647c4b..2203c0c 100644 --- a/test/CodeGen/AArch64/extern-weak.ll +++ b/test/CodeGen/AArch64/extern-weak.ll @@ -31,7 +31,7 @@ define i32()* @foo() { @arr_var = extern_weak global [10 x i32] define i32* @bar() { - %addr = getelementptr [10 x i32]* @arr_var, i32 0, i32 5 + %addr = getelementptr [10 x i32], [10 x i32]* @arr_var, i32 0, i32 5 ; CHECK: adrp x[[ADDRHI:[0-9]+]], :got:arr_var diff --git a/test/CodeGen/AArch64/f16-convert.ll b/test/CodeGen/AArch64/f16-convert.ll index d1f49a91..8caa1f5 100644 --- a/test/CodeGen/AArch64/f16-convert.ll +++ b/test/CodeGen/AArch64/f16-convert.ll @@ -6,7 +6,7 @@ define float @load0(i16* nocapture readonly %a) nounwind { ; CHECK-NEXT: fcvt s0, [[HREG]] ; CHECK-NEXT: ret - %tmp = load i16* %a, align 2 + %tmp = load i16, i16* %a, align 2 %tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp) ret float %tmp1 } @@ -17,7 +17,7 @@ define double @load1(i16* nocapture readonly %a) nounwind { ; CHECK-NEXT: fcvt d0, [[HREG]] ; CHECK-NEXT: ret - %tmp = load i16* %a, align 2 + %tmp = load i16, i16* %a, align 2 %conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp) ret double %conv } @@ -29,8 +29,8 @@ define float @load2(i16* nocapture readonly %a, i32 %i) nounwind { ; CHECK-NEXT: ret %idxprom = sext i32 %i to i64 - %arrayidx = getelementptr inbounds i16* %a, i64 %idxprom - %tmp = load i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, i16* %a, i64 %idxprom + %tmp = load i16, i16* %arrayidx, align 2 %tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp) ret float %tmp1 } @@ -42,8 +42,8 @@ define double @load3(i16* nocapture readonly %a, i32 %i) nounwind { ; CHECK-NEXT: ret %idxprom = sext i32 %i to i64 - %arrayidx = getelementptr inbounds i16* %a, i64 %idxprom - %tmp = load i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, i16* %a, i64 %idxprom + %tmp = load i16, i16* %arrayidx, align 2 %conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp) ret double %conv } @@ -54,8 +54,8 @@ define float @load4(i16* nocapture readonly %a, i64 %i) nounwind { ; CHECK-NEXT: fcvt s0, [[HREG]] ; CHECK-NEXT: ret - %arrayidx = getelementptr inbounds i16* %a, i64 %i - %tmp = load i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, i16* %a, i64 %i + %tmp = load i16, i16* %arrayidx, align 2 %tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp) ret float %tmp1 } @@ -66,8 +66,8 @@ define double @load5(i16* nocapture readonly %a, i64 %i) nounwind { ; CHECK-NEXT: fcvt d0, [[HREG]] ; CHECK-NEXT: ret - %arrayidx = getelementptr inbounds i16* %a, i64 %i - %tmp = load i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, i16* %a, i64 %i + %tmp = load i16, i16* %arrayidx, align 2 %conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp) ret double %conv } @@ -78,8 +78,8 @@ define float @load6(i16* nocapture readonly %a) nounwind { ; CHECK-NEXT: fcvt s0, [[HREG]] ; CHECK-NEXT: ret - %arrayidx = getelementptr inbounds i16* %a, i64 10 - %tmp = load i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, i16* %a, i64 10 + %tmp = load i16, i16* %arrayidx, align 2 %tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp) ret float %tmp1 } @@ -90,8 +90,8 @@ define double @load7(i16* nocapture readonly %a) nounwind { ; CHECK-NEXT: fcvt d0, [[HREG]] ; CHECK-NEXT: ret - %arrayidx = getelementptr inbounds i16* %a, i64 10 - %tmp = load i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, i16* %a, i64 10 + %tmp = load i16, i16* %arrayidx, align 2 %conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp) ret double %conv } @@ -102,8 +102,8 @@ define float @load8(i16* nocapture readonly %a) nounwind { ; CHECK-NEXT: fcvt s0, [[HREG]] ; CHECK-NEXT: ret - %arrayidx = getelementptr inbounds i16* %a, i64 -10 - %tmp = load i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, i16* %a, i64 -10 + %tmp = load i16, i16* %arrayidx, align 2 %tmp1 = tail call float @llvm.convert.from.fp16.f32(i16 %tmp) ret float %tmp1 } @@ -114,8 +114,8 @@ define double @load9(i16* nocapture readonly %a) nounwind { ; CHECK-NEXT: fcvt d0, [[HREG]] ; CHECK-NEXT: ret - %arrayidx = getelementptr inbounds i16* %a, i64 -10 - %tmp = load i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, i16* %a, i64 -10 + %tmp = load i16, i16* %arrayidx, align 2 %conv = tail call double @llvm.convert.from.fp16.f64(i16 %tmp) ret double %conv } @@ -152,7 +152,7 @@ define void @store2(i16* nocapture %a, i32 %i, float %val) nounwind { %tmp = tail call i16 @llvm.convert.to.fp16.f32(float %val) %idxprom = sext i32 %i to i64 - %arrayidx = getelementptr inbounds i16* %a, i64 %idxprom + %arrayidx = getelementptr inbounds i16, i16* %a, i64 %idxprom store i16 %tmp, i16* %arrayidx, align 2 ret void } @@ -167,7 +167,7 @@ define void @store3(i16* nocapture %a, i32 %i, double %val) nounwind { %conv = fptrunc double %val to float %tmp = tail call i16 @llvm.convert.to.fp16.f32(float %conv) %idxprom = sext i32 %i to i64 - %arrayidx = getelementptr inbounds i16* %a, i64 %idxprom + %arrayidx = getelementptr inbounds i16, i16* %a, i64 %idxprom store i16 %tmp, i16* %arrayidx, align 2 ret void } @@ -179,7 +179,7 @@ define void @store4(i16* nocapture %a, i64 %i, float %val) nounwind { ; CHECK-NEXT: ret %tmp = tail call i16 @llvm.convert.to.fp16.f32(float %val) - %arrayidx = getelementptr inbounds i16* %a, i64 %i + %arrayidx = getelementptr inbounds i16, i16* %a, i64 %i store i16 %tmp, i16* %arrayidx, align 2 ret void } @@ -193,7 +193,7 @@ define void @store5(i16* nocapture %a, i64 %i, double %val) nounwind { %conv = fptrunc double %val to float %tmp = tail call i16 @llvm.convert.to.fp16.f32(float %conv) - %arrayidx = getelementptr inbounds i16* %a, i64 %i + %arrayidx = getelementptr inbounds i16, i16* %a, i64 %i store i16 %tmp, i16* %arrayidx, align 2 ret void } @@ -205,7 +205,7 @@ define void @store6(i16* nocapture %a, float %val) nounwind { ; CHECK-NEXT: ret %tmp = tail call i16 @llvm.convert.to.fp16.f32(float %val) - %arrayidx = getelementptr inbounds i16* %a, i64 10 + %arrayidx = getelementptr inbounds i16, i16* %a, i64 10 store i16 %tmp, i16* %arrayidx, align 2 ret void } @@ -219,7 +219,7 @@ define void @store7(i16* nocapture %a, double %val) nounwind { %conv = fptrunc double %val to float %tmp = tail call i16 @llvm.convert.to.fp16.f32(float %conv) - %arrayidx = getelementptr inbounds i16* %a, i64 10 + %arrayidx = getelementptr inbounds i16, i16* %a, i64 10 store i16 %tmp, i16* %arrayidx, align 2 ret void } @@ -231,7 +231,7 @@ define void @store8(i16* nocapture %a, float %val) nounwind { ; CHECK-NEXT: ret %tmp = tail call i16 @llvm.convert.to.fp16.f32(float %val) - %arrayidx = getelementptr inbounds i16* %a, i64 -10 + %arrayidx = getelementptr inbounds i16, i16* %a, i64 -10 store i16 %tmp, i16* %arrayidx, align 2 ret void } @@ -245,7 +245,7 @@ define void @store9(i16* nocapture %a, double %val) nounwind { %conv = fptrunc double %val to float %tmp = tail call i16 @llvm.convert.to.fp16.f32(float %conv) - %arrayidx = getelementptr inbounds i16* %a, i64 -10 + %arrayidx = getelementptr inbounds i16, i16* %a, i64 -10 store i16 %tmp, i16* %arrayidx, align 2 ret void } diff --git a/test/CodeGen/AArch64/fast-isel-addressing-modes.ll b/test/CodeGen/AArch64/fast-isel-addressing-modes.ll index d86f00d..6ab6a66 100644 --- a/test/CodeGen/AArch64/fast-isel-addressing-modes.ll +++ b/test/CodeGen/AArch64/fast-isel-addressing-modes.ll @@ -1,53 +1,53 @@ ; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SDAG -; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FAST ; Load / Store Base Register only define zeroext i1 @load_breg_i1(i1* %a) { ; CHECK-LABEL: load_breg_i1 ; CHECK: ldrb {{w[0-9]+}}, [x0] - %1 = load i1* %a + %1 = load i1, i1* %a ret i1 %1 } define zeroext i8 @load_breg_i8(i8* %a) { ; CHECK-LABEL: load_breg_i8 ; CHECK: ldrb {{w[0-9]+}}, [x0] - %1 = load i8* %a + %1 = load i8, i8* %a ret i8 %1 } define zeroext i16 @load_breg_i16(i16* %a) { ; CHECK-LABEL: load_breg_i16 ; CHECK: ldrh {{w[0-9]+}}, [x0] - %1 = load i16* %a + %1 = load i16, i16* %a ret i16 %1 } define i32 @load_breg_i32(i32* %a) { ; CHECK-LABEL: load_breg_i32 ; CHECK: ldr {{w[0-9]+}}, [x0] - %1 = load i32* %a + %1 = load i32, i32* %a ret i32 %1 } define i64 @load_breg_i64(i64* %a) { ; CHECK-LABEL: load_breg_i64 ; CHECK: ldr {{x[0-9]+}}, [x0] - %1 = load i64* %a + %1 = load i64, i64* %a ret i64 %1 } define float @load_breg_f32(float* %a) { ; CHECK-LABEL: load_breg_f32 ; CHECK: ldr {{s[0-9]+}}, [x0] - %1 = load float* %a + %1 = load float, float* %a ret float %1 } define double @load_breg_f64(double* %a) { ; CHECK-LABEL: load_breg_f64 ; CHECK: ldr {{d[0-9]+}}, [x0] - %1 = load double* %a + %1 = load double, double* %a ret double %1 } @@ -113,7 +113,7 @@ define i32 @load_immoff_1() { ; CHECK: orr {{w|x}}[[REG:[0-9]+]], {{wzr|xzr}}, #0x80 ; CHECK: ldr {{w[0-9]+}}, {{\[}}x[[REG]]{{\]}} %1 = inttoptr i64 128 to i32* - %2 = load i32* %1 + %2 = load i32, i32* %1 ret i32 %2 } @@ -124,7 +124,7 @@ define i32 @load_breg_immoff_1(i64 %a) { ; CHECK: ldur {{w[0-9]+}}, [x0, #-256] %1 = add i64 %a, -256 %2 = inttoptr i64 %1 to i32* - %3 = load i32* %2 + %3 = load i32, i32* %2 ret i32 %3 } @@ -135,7 +135,7 @@ define i32 @load_breg_immoff_2(i64 %a) { ; CHECK-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}} %1 = add i64 %a, -257 %2 = inttoptr i64 %1 to i32* - %3 = load i32* %2 + %3 = load i32, i32* %2 ret i32 %3 } @@ -145,7 +145,7 @@ define i32 @load_breg_immoff_3(i64 %a) { ; CHECK: ldur {{w[0-9]+}}, [x0, #255] %1 = add i64 %a, 255 %2 = inttoptr i64 %1 to i32* - %3 = load i32* %2 + %3 = load i32, i32* %2 ret i32 %3 } @@ -156,7 +156,7 @@ define i32 @load_breg_immoff_4(i64 %a) { ; CHECK-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}} %1 = add i64 %a, 257 %2 = inttoptr i64 %1 to i32* - %3 = load i32* %2 + %3 = load i32, i32* %2 ret i32 %3 } @@ -166,7 +166,7 @@ define i32 @load_breg_immoff_5(i64 %a) { ; CHECK: ldr {{w[0-9]+}}, [x0, #16380] %1 = add i64 %a, 16380 %2 = inttoptr i64 %1 to i32* - %3 = load i32* %2 + %3 = load i32, i32* %2 ret i32 %3 } @@ -180,7 +180,7 @@ define i32 @load_breg_immoff_6(i64 %a) { ; FAST-NEXT: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}} %1 = add i64 %a, 16384 %2 = inttoptr i64 %1 to i32* - %3 = load i32* %2 + %3 = load i32, i32* %2 ret i32 %3 } @@ -255,7 +255,7 @@ define i64 @load_breg_immoff_7(i64 %a) { ; CHECK: ldr {{x[0-9]+}}, [x0, #48] %1 = add i64 %a, 48 %2 = inttoptr i64 %1 to i64* - %3 = load i64* %2 + %3 = load i64, i64* %2 ret i64 %3 } @@ -265,7 +265,7 @@ define i64 @load_breg_immoff_8(i64 %a) { ; CHECK: ldr {{x[0-9]+}}, [x0, #48] %1 = add i64 48, %a %2 = inttoptr i64 %1 to i64* - %3 = load i64* %2 + %3 = load i64, i64* %2 ret i64 %3 } @@ -275,7 +275,7 @@ define i64 @load_breg_offreg_1(i64 %a, i64 %b) { ; CHECK: ldr {{x[0-9]+}}, [x0, x1] %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i64* - %3 = load i64* %2 + %3 = load i64, i64* %2 ret i64 %3 } @@ -285,7 +285,7 @@ define i64 @load_breg_offreg_2(i64 %a, i64 %b) { ; CHECK: ldr {{x[0-9]+}}, [x1, x0] %1 = add i64 %b, %a %2 = inttoptr i64 %1 to i64* - %3 = load i64* %2 + %3 = load i64, i64* %2 ret i64 %3 } @@ -297,7 +297,7 @@ define i64 @load_breg_offreg_immoff_1(i64 %a, i64 %b) { %1 = add i64 %a, %b %2 = add i64 %1, 48 %3 = inttoptr i64 %2 to i64* - %4 = load i64* %3 + %4 = load i64, i64* %3 ret i64 %4 } @@ -312,7 +312,7 @@ define i64 @load_breg_offreg_immoff_2(i64 %a, i64 %b) { %1 = add i64 %a, %b %2 = add i64 %1, 61440 %3 = inttoptr i64 %2 to i64* - %4 = load i64* %3 + %4 = load i64, i64* %3 ret i64 %4 } @@ -323,7 +323,7 @@ define i32 @load_shift_offreg_1(i64 %a) { ; CHECK: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}} %1 = shl i64 %a, 2 %2 = inttoptr i64 %1 to i32* - %3 = load i32* %2 + %3 = load i32, i32* %2 ret i32 %3 } @@ -333,7 +333,7 @@ define i32 @load_mul_offreg_1(i64 %a) { ; CHECK: ldr {{w[0-9]+}}, {{\[}}[[REG]]{{\]}} %1 = mul i64 %a, 4 %2 = inttoptr i64 %1 to i32* - %3 = load i32* %2 + %3 = load i32, i32* %2 ret i32 %3 } @@ -344,7 +344,7 @@ define i32 @load_breg_shift_offreg_1(i64 %a, i64 %b) { %1 = shl i64 %a, 2 %2 = add i64 %1, %b %3 = inttoptr i64 %2 to i32* - %4 = load i32* %3 + %4 = load i32, i32* %3 ret i32 %4 } @@ -354,7 +354,7 @@ define i32 @load_breg_shift_offreg_2(i64 %a, i64 %b) { %1 = shl i64 %a, 2 %2 = add i64 %b, %1 %3 = inttoptr i64 %2 to i32* - %4 = load i32* %3 + %4 = load i32, i32* %3 ret i32 %4 } @@ -369,7 +369,7 @@ define i32 @load_breg_shift_offreg_3(i64 %a, i64 %b) { %2 = shl i64 %b, 2 %3 = add i64 %1, %2 %4 = inttoptr i64 %3 to i32* - %5 = load i32* %4 + %5 = load i32, i32* %4 ret i32 %5 } @@ -384,7 +384,7 @@ define i32 @load_breg_shift_offreg_4(i64 %a, i64 %b) { %2 = shl i64 %b, 2 %3 = add i64 %2, %1 %4 = inttoptr i64 %3 to i32* - %5 = load i32* %4 + %5 = load i32, i32* %4 ret i32 %5 } @@ -399,7 +399,7 @@ define i32 @load_breg_shift_offreg_5(i64 %a, i64 %b) { %2 = shl i64 %b, 3 %3 = add i64 %1, %2 %4 = inttoptr i64 %3 to i32* - %5 = load i32* %4 + %5 = load i32, i32* %4 ret i32 %5 } @@ -409,7 +409,7 @@ define i32 @load_breg_mul_offreg_1(i64 %a, i64 %b) { %1 = mul i64 %a, 4 %2 = add i64 %1, %b %3 = inttoptr i64 %2 to i32* - %4 = load i32* %3 + %4 = load i32, i32* %3 ret i32 %4 } @@ -419,7 +419,7 @@ define zeroext i8 @load_breg_and_offreg_1(i64 %a, i64 %b) { %1 = and i64 %a, 4294967295 %2 = add i64 %1, %b %3 = inttoptr i64 %2 to i8* - %4 = load i8* %3 + %4 = load i8, i8* %3 ret i8 %4 } @@ -430,7 +430,7 @@ define zeroext i16 @load_breg_and_offreg_2(i64 %a, i64 %b) { %2 = shl i64 %1, 1 %3 = add i64 %2, %b %4 = inttoptr i64 %3 to i16* - %5 = load i16* %4 + %5 = load i16, i16* %4 ret i16 %5 } @@ -441,7 +441,7 @@ define i32 @load_breg_and_offreg_3(i64 %a, i64 %b) { %2 = shl i64 %1, 2 %3 = add i64 %2, %b %4 = inttoptr i64 %3 to i32* - %5 = load i32* %4 + %5 = load i32, i32* %4 ret i32 %5 } @@ -452,7 +452,7 @@ define i64 @load_breg_and_offreg_4(i64 %a, i64 %b) { %2 = shl i64 %1, 3 %3 = add i64 %2, %b %4 = inttoptr i64 %3 to i64* - %5 = load i64* %4 + %5 = load i64, i64* %4 ret i64 %5 } @@ -464,7 +464,7 @@ define i64 @load_breg_and_offreg_5(i64 %a, i64 %b, i64 %c) { %1 = and i64 %a, %c %2 = add i64 %1, %b %3 = inttoptr i64 %2 to i64* - %4 = load i64* %3 + %4 = load i64, i64* %3 ret i64 %4 } @@ -476,7 +476,7 @@ define i64 @load_breg_and_offreg_6(i64 %a, i64 %b, i64 %c) { %2 = shl i64 %1, 3 %3 = add i64 %2, %b %4 = inttoptr i64 %3 to i64* - %5 = load i64* %4 + %5 = load i64, i64* %4 ret i64 %5 } @@ -488,7 +488,7 @@ define i32 @load_breg_zext_shift_offreg_1(i32 %a, i64 %b) { %2 = shl i64 %1, 2 %3 = add i64 %2, %b %4 = inttoptr i64 %3 to i32* - %5 = load i32* %4 + %5 = load i32, i32* %4 ret i32 %5 } @@ -499,7 +499,7 @@ define i32 @load_breg_zext_shift_offreg_2(i32 %a, i64 %b) { %2 = shl i64 %1, 2 %3 = add i64 %b, %2 %4 = inttoptr i64 %3 to i32* - %5 = load i32* %4 + %5 = load i32, i32* %4 ret i32 %5 } @@ -510,7 +510,7 @@ define i32 @load_breg_zext_mul_offreg_1(i32 %a, i64 %b) { %2 = mul i64 %1, 4 %3 = add i64 %2, %b %4 = inttoptr i64 %3 to i32* - %5 = load i32* %4 + %5 = load i32, i32* %4 ret i32 %5 } @@ -521,7 +521,7 @@ define i32 @load_breg_sext_shift_offreg_1(i32 %a, i64 %b) { %2 = shl i64 %1, 2 %3 = add i64 %2, %b %4 = inttoptr i64 %3 to i32* - %5 = load i32* %4 + %5 = load i32, i32* %4 ret i32 %5 } @@ -532,7 +532,7 @@ define i32 @load_breg_sext_shift_offreg_2(i32 %a, i64 %b) { %2 = shl i64 %1, 2 %3 = add i64 %b, %2 %4 = inttoptr i64 %3 to i32* - %5 = load i32* %4 + %5 = load i32, i32* %4 ret i32 %5 } @@ -546,7 +546,7 @@ define i32 @load_breg_sext_shift_offreg_3(i32 %a, i64 %b) { %3 = shl i64 %2, 2 %4 = add i64 %b, %3 %5 = inttoptr i64 %4 to i32* - %6 = load i32* %5 + %6 = load i32, i32* %5 ret i32 %6 } @@ -558,7 +558,7 @@ define i32 @load_breg_sext_mul_offreg_1(i32 %a, i64 %b) { %2 = mul i64 %1, 4 %3 = add i64 %2, %b %4 = inttoptr i64 %3 to i32* - %5 = load i32* %4 + %5 = load i32, i32* %4 ret i32 %5 } @@ -571,7 +571,7 @@ define i64 @load_sext_shift_offreg_imm1(i32 %a) { %2 = shl i64 %1, 3 %3 = add i64 %2, 8 %4 = inttoptr i64 %3 to i64* - %5 = load i64* %4 + %5 = load i64, i64* %4 ret i64 %5 } @@ -585,7 +585,7 @@ define i64 @load_breg_sext_shift_offreg_imm1(i32 %a, i64 %b) { %3 = add i64 %b, %2 %4 = add i64 %3, 8 %5 = inttoptr i64 %4 to i64* - %6 = load i64* %5 + %6 = load i64, i64* %5 ret i64 %6 } @@ -594,7 +594,7 @@ define i64 @kill_reg(i64 %a) { %1 = sub i64 %a, 8 %2 = add i64 %1, 96 %3 = inttoptr i64 %2 to i64* - %4 = load i64* %3 + %4 = load i64, i64* %3 %5 = add i64 %2, %4 ret i64 %5 } @@ -621,7 +621,7 @@ define i32 @load_fi(i64 %i) { %3 = mul i64 %i, 4 %4 = add i64 %2, %3 %5 = inttoptr i64 %4 to i32* - %6 = load i32* %5, align 4 + %6 = load i32, i32* %5, align 4 ret i32 %6 } diff --git a/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll b/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll index bc4a210..da6ddbf 100644 --- a/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll +++ b/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s ; CHECK-label: test_or ; CHECK: cbnz w0, {{LBB[0-9]+_2}} diff --git a/test/CodeGen/AArch64/fast-isel-branch_weights.ll b/test/CodeGen/AArch64/fast-isel-branch_weights.ll index 70dbdf2..ff57bbb 100644 --- a/test/CodeGen/AArch64/fast-isel-branch_weights.ll +++ b/test/CodeGen/AArch64/fast-isel-branch_weights.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=arm64-apple-darwin -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s ; Test if the BBs are reordred according to their branch weights. define i64 @branch_weights_test(i64 %a, i64 %b) { diff --git a/test/CodeGen/AArch64/fast-isel-call-return.ll b/test/CodeGen/AArch64/fast-isel-call-return.ll index 9b10969..a03b12e 100644 --- a/test/CodeGen/AArch64/fast-isel-call-return.ll +++ b/test/CodeGen/AArch64/fast-isel-call-return.ll @@ -1,4 +1,4 @@ -; RUN: llc -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" target triple = "aarch64-linux-gnu" diff --git a/test/CodeGen/AArch64/fast-isel-cbz.ll b/test/CodeGen/AArch64/fast-isel-cbz.ll index 6e31a04..a407b26 100644 --- a/test/CodeGen/AArch64/fast-isel-cbz.ll +++ b/test/CodeGen/AArch64/fast-isel-cbz.ll @@ -1,4 +1,4 @@ -; RUN: llc -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s +; RUN: llc -fast-isel -fast-isel-abort=1 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s define i32 @icmp_eq_i1(i1 %a) { ; CHECK-LABEL: icmp_eq_i1 diff --git a/test/CodeGen/AArch64/fast-isel-cmp-branch.ll b/test/CodeGen/AArch64/fast-isel-cmp-branch.ll index 3651f19..1ac358f 100644 --- a/test/CodeGen/AArch64/fast-isel-cmp-branch.ll +++ b/test/CodeGen/AArch64/fast-isel-cmp-branch.ll @@ -1,5 +1,5 @@ ; RUN: llc -aarch64-atomic-cfg-tidy=0 -mtriple=aarch64-apple-darwin < %s | FileCheck %s -; RUN: llc -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=0 -mtriple=aarch64-apple-darwin < %s | FileCheck %s +; RUN: llc -fast-isel -fast-isel-abort=1 -aarch64-atomic-cfg-tidy=0 -mtriple=aarch64-apple-darwin < %s | FileCheck %s define i32 @fcmp_oeq(float %x, float %y) { ; CHECK-LABEL: fcmp_oeq diff --git a/test/CodeGen/AArch64/fast-isel-folding.ll b/test/CodeGen/AArch64/fast-isel-folding.ll index 6b524ff..883933b 100644 --- a/test/CodeGen/AArch64/fast-isel-folding.ll +++ b/test/CodeGen/AArch64/fast-isel-folding.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-apple-darwin -O0 -fast-isel-abort -verify-machineinstrs < %s +; RUN: llc -mtriple=aarch64-apple-darwin -O0 -fast-isel-abort=1 -verify-machineinstrs < %s ; Test that we don't fold the shift. define i64 @fold_shift_test(i64 %a, i1 %c) { diff --git a/test/CodeGen/AArch64/fast-isel-gep.ll b/test/CodeGen/AArch64/fast-isel-gep.ll index 4dc0a05..33adcdc 100644 --- a/test/CodeGen/AArch64/fast-isel-gep.ll +++ b/test/CodeGen/AArch64/fast-isel-gep.ll @@ -1,11 +1,11 @@ -; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s %struct.foo = type { i32, i64, float, double } define double* @test_struct(%struct.foo* %f) { ; CHECK-LABEL: test_struct ; CHECK: add x0, x0, #24 - %1 = getelementptr inbounds %struct.foo* %f, i64 0, i32 3 + %1 = getelementptr inbounds %struct.foo, %struct.foo* %f, i64 0, i32 3 ret double* %1 } @@ -13,21 +13,21 @@ define i32* @test_array1(i32* %a, i64 %i) { ; CHECK-LABEL: test_array1 ; CHECK: orr [[REG:x[0-9]+]], xzr, #0x4 ; CHECK-NEXT: madd x0, x1, [[REG]], x0 - %1 = getelementptr inbounds i32* %a, i64 %i + %1 = getelementptr inbounds i32, i32* %a, i64 %i ret i32* %1 } define i32* @test_array2(i32* %a) { ; CHECK-LABEL: test_array2 ; CHECK: add x0, x0, #16 - %1 = getelementptr inbounds i32* %a, i64 4 + %1 = getelementptr inbounds i32, i32* %a, i64 4 ret i32* %1 } define i32* @test_array3(i32* %a) { ; CHECK-LABEL: test_array3 ; CHECK: add x0, x0, #1, lsl #12 - %1 = getelementptr inbounds i32* %a, i64 1024 + %1 = getelementptr inbounds i32, i32* %a, i64 1024 ret i32* %1 } @@ -35,7 +35,7 @@ define i32* @test_array4(i32* %a) { ; CHECK-LABEL: test_array4 ; CHECK: movz [[REG:x[0-9]+]], #0x1008 ; CHECK-NEXR: add x0, x0, [[REG]] - %1 = getelementptr inbounds i32* %a, i64 1026 + %1 = getelementptr inbounds i32, i32* %a, i64 1026 ret i32* %1 } @@ -44,6 +44,6 @@ define i32* @test_array5(i32* %a, i32 %i) { ; CHECK: sxtw [[REG1:x[0-9]+]], w1 ; CHECK-NEXT: orr [[REG2:x[0-9]+]], xzr, #0x4 ; CHECK-NEXT: madd {{x[0-9]+}}, [[REG1]], [[REG2]], x0 - %1 = getelementptr inbounds i32* %a, i32 %i + %1 = getelementptr inbounds i32, i32* %a, i32 %i ret i32* %1 } diff --git a/test/CodeGen/AArch64/fast-isel-int-ext.ll b/test/CodeGen/AArch64/fast-isel-int-ext.ll index 866feba..4b2cab5 100644 --- a/test/CodeGen/AArch64/fast-isel-int-ext.ll +++ b/test/CodeGen/AArch64/fast-isel-int-ext.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s ; ; Test that we only use the sign/zero extend in the address calculation when @@ -13,7 +13,7 @@ define i64 @load_addr_shift_zext1(i32 %a, i64 %b) { %2 = shl i64 %1, 3 %3 = add i64 %b, %2 %4 = inttoptr i64 %3 to i64* - %5 = load i64* %4 + %5 = load i64, i64* %4 ret i64 %5 } @@ -24,7 +24,7 @@ define i64 @load_addr_shift_zext2(i32 zeroext %a, i64 %b) { %2 = shl i64 %1, 3 %3 = add i64 %b, %2 %4 = inttoptr i64 %3 to i64* - %5 = load i64* %4 + %5 = load i64, i64* %4 ret i64 %5 } @@ -35,7 +35,7 @@ define i64 @load_addr_shift_zext3(i32 signext %a, i64 %b) { %2 = shl i64 %1, 3 %3 = add i64 %b, %2 %4 = inttoptr i64 %3 to i64* - %5 = load i64* %4 + %5 = load i64, i64* %4 ret i64 %5 } @@ -46,7 +46,7 @@ define i64 @load_addr_shift_sext1(i32 %a, i64 %b) { %2 = shl i64 %1, 3 %3 = add i64 %b, %2 %4 = inttoptr i64 %3 to i64* - %5 = load i64* %4 + %5 = load i64, i64* %4 ret i64 %5 } @@ -57,7 +57,7 @@ define i64 @load_addr_shift_sext2(i32 zeroext %a, i64 %b) { %2 = shl i64 %1, 3 %3 = add i64 %b, %2 %4 = inttoptr i64 %3 to i64* - %5 = load i64* %4 + %5 = load i64, i64* %4 ret i64 %5 } @@ -68,7 +68,7 @@ define i64 @load_addr_shift_sext3(i32 signext %a, i64 %b) { %2 = shl i64 %1, 3 %3 = add i64 %b, %2 %4 = inttoptr i64 %3 to i64* - %5 = load i64* %4 + %5 = load i64, i64* %4 ret i64 %5 } @@ -82,7 +82,7 @@ define i64 @load_addr_mul_zext1(i32 %a, i64 %b) { %2 = mul i64 %1, 8 %3 = add i64 %b, %2 %4 = inttoptr i64 %3 to i64* - %5 = load i64* %4 + %5 = load i64, i64* %4 ret i64 %5 } @@ -93,7 +93,7 @@ define i64 @load_addr_mul_zext2(i32 zeroext %a, i64 %b) { %2 = mul i64 %1, 8 %3 = add i64 %b, %2 %4 = inttoptr i64 %3 to i64* - %5 = load i64* %4 + %5 = load i64, i64* %4 ret i64 %5 } @@ -104,7 +104,7 @@ define i64 @load_addr_mul_zext3(i32 signext %a, i64 %b) { %2 = mul i64 %1, 8 %3 = add i64 %b, %2 %4 = inttoptr i64 %3 to i64* - %5 = load i64* %4 + %5 = load i64, i64* %4 ret i64 %5 } @@ -115,7 +115,7 @@ define i64 @load_addr_mul_sext1(i32 %a, i64 %b) { %2 = mul i64 %1, 8 %3 = add i64 %b, %2 %4 = inttoptr i64 %3 to i64* - %5 = load i64* %4 + %5 = load i64, i64* %4 ret i64 %5 } @@ -126,7 +126,7 @@ define i64 @load_addr_mul_sext2(i32 zeroext %a, i64 %b) { %2 = mul i64 %1, 8 %3 = add i64 %b, %2 %4 = inttoptr i64 %3 to i64* - %5 = load i64* %4 + %5 = load i64, i64* %4 ret i64 %5 } @@ -137,7 +137,7 @@ define i64 @load_addr_mul_sext3(i32 signext %a, i64 %b) { %2 = mul i64 %1, 8 %3 = add i64 %b, %2 %4 = inttoptr i64 %3 to i64* - %5 = load i64* %4 + %5 = load i64, i64* %4 ret i64 %5 } @@ -153,7 +153,7 @@ define i32 @load_unscaled_zext_i8_to_i32(i64 %a) { ; CHECK-NOT: uxtb %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i8* - %3 = load i8* %2 + %3 = load i8, i8* %2 %4 = zext i8 %3 to i32 ret i32 %4 } @@ -164,7 +164,7 @@ define i32 @load_unscaled_zext_i16_to_i32(i64 %a) { ; CHECK-NOT: uxth %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i16* - %3 = load i16* %2 + %3 = load i16, i16* %2 %4 = zext i16 %3 to i32 ret i32 %4 } @@ -175,7 +175,7 @@ define i64 @load_unscaled_zext_i8_to_i64(i64 %a) { ; CHECK-NOT: uxtb %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i8* - %3 = load i8* %2 + %3 = load i8, i8* %2 %4 = zext i8 %3 to i64 ret i64 %4 } @@ -186,7 +186,7 @@ define i64 @load_unscaled_zext_i16_to_i64(i64 %a) { ; CHECK-NOT: uxth %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i16* - %3 = load i16* %2 + %3 = load i16, i16* %2 %4 = zext i16 %3 to i64 ret i64 %4 } @@ -197,7 +197,7 @@ define i64 @load_unscaled_zext_i32_to_i64(i64 %a) { ; CHECK-NOT: uxtw %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i32* - %3 = load i32* %2 + %3 = load i32, i32* %2 %4 = zext i32 %3 to i64 ret i64 %4 } @@ -208,7 +208,7 @@ define i32 @load_unscaled_sext_i8_to_i32(i64 %a) { ; CHECK-NOT: sxtb %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i8* - %3 = load i8* %2 + %3 = load i8, i8* %2 %4 = sext i8 %3 to i32 ret i32 %4 } @@ -219,7 +219,7 @@ define i32 @load_unscaled_sext_i16_to_i32(i64 %a) { ; CHECK-NOT: sxth %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i16* - %3 = load i16* %2 + %3 = load i16, i16* %2 %4 = sext i16 %3 to i32 ret i32 %4 } @@ -230,7 +230,7 @@ define i64 @load_unscaled_sext_i8_to_i64(i64 %a) { ; CHECK-NOT: sxtb %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i8* - %3 = load i8* %2 + %3 = load i8, i8* %2 %4 = sext i8 %3 to i64 ret i64 %4 } @@ -241,7 +241,7 @@ define i64 @load_unscaled_sext_i16_to_i64(i64 %a) { ; CHECK-NOT: sxth %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i16* - %3 = load i16* %2 + %3 = load i16, i16* %2 %4 = sext i16 %3 to i64 ret i64 %4 } @@ -252,7 +252,7 @@ define i64 @load_unscaled_sext_i32_to_i64(i64 %a) { ; CHECK-NOT: sxtw %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i32* - %3 = load i32* %2 + %3 = load i32, i32* %2 %4 = sext i32 %3 to i64 ret i64 %4 } @@ -264,7 +264,7 @@ define i32 @load_register_zext_i8_to_i32(i64 %a, i64 %b) { ; CHECK-NOT: uxtb %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i8* - %3 = load i8* %2 + %3 = load i8, i8* %2 %4 = zext i8 %3 to i32 ret i32 %4 } @@ -275,7 +275,7 @@ define i32 @load_register_zext_i16_to_i32(i64 %a, i64 %b) { ; CHECK-NOT: uxth %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i16* - %3 = load i16* %2 + %3 = load i16, i16* %2 %4 = zext i16 %3 to i32 ret i32 %4 } @@ -286,7 +286,7 @@ define i64 @load_register_zext_i8_to_i64(i64 %a, i64 %b) { ; CHECK-NOT: uxtb %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i8* - %3 = load i8* %2 + %3 = load i8, i8* %2 %4 = zext i8 %3 to i64 ret i64 %4 } @@ -297,7 +297,7 @@ define i64 @load_register_zext_i16_to_i64(i64 %a, i64 %b) { ; CHECK-NOT: uxth %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i16* - %3 = load i16* %2 + %3 = load i16, i16* %2 %4 = zext i16 %3 to i64 ret i64 %4 } @@ -308,7 +308,7 @@ define i64 @load_register_zext_i32_to_i64(i64 %a, i64 %b) { ; CHECK-NOT: uxtw %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i32* - %3 = load i32* %2 + %3 = load i32, i32* %2 %4 = zext i32 %3 to i64 ret i64 %4 } @@ -319,7 +319,7 @@ define i32 @load_register_sext_i8_to_i32(i64 %a, i64 %b) { ; CHECK-NOT: sxtb %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i8* - %3 = load i8* %2 + %3 = load i8, i8* %2 %4 = sext i8 %3 to i32 ret i32 %4 } @@ -330,7 +330,7 @@ define i32 @load_register_sext_i16_to_i32(i64 %a, i64 %b) { ; CHECK-NOT: sxth %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i16* - %3 = load i16* %2 + %3 = load i16, i16* %2 %4 = sext i16 %3 to i32 ret i32 %4 } @@ -341,7 +341,7 @@ define i64 @load_register_sext_i8_to_i64(i64 %a, i64 %b) { ; CHECK-NOT: sxtb %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i8* - %3 = load i8* %2 + %3 = load i8, i8* %2 %4 = sext i8 %3 to i64 ret i64 %4 } @@ -352,7 +352,7 @@ define i64 @load_register_sext_i16_to_i64(i64 %a, i64 %b) { ; CHECK-NOT: sxth %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i16* - %3 = load i16* %2 + %3 = load i16, i16* %2 %4 = sext i16 %3 to i64 ret i64 %4 } @@ -363,7 +363,7 @@ define i64 @load_register_sext_i32_to_i64(i64 %a, i64 %b) { ; CHECK-NOT: sxtw %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i32* - %3 = load i32* %2 + %3 = load i32, i32* %2 %4 = sext i32 %3 to i64 ret i64 %4 } @@ -376,7 +376,7 @@ define i32 @load_extend_zext_i8_to_i32(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i8* - %4 = load i8* %3 + %4 = load i8, i8* %3 %5 = zext i8 %4 to i32 ret i32 %5 } @@ -388,7 +388,7 @@ define i32 @load_extend_zext_i16_to_i32(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i16* - %4 = load i16* %3 + %4 = load i16, i16* %3 %5 = zext i16 %4 to i32 ret i32 %5 } @@ -400,7 +400,7 @@ define i64 @load_extend_zext_i8_to_i64(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i8* - %4 = load i8* %3 + %4 = load i8, i8* %3 %5 = zext i8 %4 to i64 ret i64 %5 } @@ -412,7 +412,7 @@ define i64 @load_extend_zext_i16_to_i64(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i16* - %4 = load i16* %3 + %4 = load i16, i16* %3 %5 = zext i16 %4 to i64 ret i64 %5 } @@ -424,7 +424,7 @@ define i64 @load_extend_zext_i32_to_i64(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i32* - %4 = load i32* %3 + %4 = load i32, i32* %3 %5 = zext i32 %4 to i64 ret i64 %5 } @@ -436,7 +436,7 @@ define i32 @load_extend_sext_i8_to_i32(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i8* - %4 = load i8* %3 + %4 = load i8, i8* %3 %5 = sext i8 %4 to i32 ret i32 %5 } @@ -448,7 +448,7 @@ define i32 @load_extend_sext_i16_to_i32(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i16* - %4 = load i16* %3 + %4 = load i16, i16* %3 %5 = sext i16 %4 to i32 ret i32 %5 } @@ -460,7 +460,7 @@ define i64 @load_extend_sext_i8_to_i64(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i8* - %4 = load i8* %3 + %4 = load i8, i8* %3 %5 = sext i8 %4 to i64 ret i64 %5 } @@ -472,7 +472,7 @@ define i64 @load_extend_sext_i16_to_i64(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i16* - %4 = load i16* %3 + %4 = load i16, i16* %3 %5 = sext i16 %4 to i64 ret i64 %5 } @@ -484,7 +484,7 @@ define i64 @load_extend_sext_i32_to_i64(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i32* - %4 = load i32* %3 + %4 = load i32, i32* %3 %5 = sext i32 %4 to i64 ret i64 %5 } diff --git a/test/CodeGen/AArch64/fast-isel-int-ext2.ll b/test/CodeGen/AArch64/fast-isel-int-ext2.ll index 8df26b2..93741d6 100644 --- a/test/CodeGen/AArch64/fast-isel-int-ext2.ll +++ b/test/CodeGen/AArch64/fast-isel-int-ext2.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=false -disable-cgp-branch-opts -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -aarch64-atomic-cfg-tidy=false -disable-cgp-branch-opts -verify-machineinstrs < %s | FileCheck %s ; ; Test folding of the sign-/zero-extend into the load instruction. @@ -11,7 +11,7 @@ define i32 @load_unscaled_zext_i8_to_i32(i64 %a) { ; CHECK-NOT: uxtb %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i8* - %3 = load i8* %2 + %3 = load i8, i8* %2 br label %bb2 bb2: @@ -25,7 +25,7 @@ define i32 @load_unscaled_zext_i16_to_i32(i64 %a) { ; CHECK-NOT: uxth %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i16* - %3 = load i16* %2 + %3 = load i16, i16* %2 br label %bb2 bb2: @@ -39,7 +39,7 @@ define i64 @load_unscaled_zext_i8_to_i64(i64 %a) { ; CHECK-NOT: uxtb %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i8* - %3 = load i8* %2 + %3 = load i8, i8* %2 br label %bb2 bb2: @@ -53,7 +53,7 @@ define i64 @load_unscaled_zext_i16_to_i64(i64 %a) { ; CHECK-NOT: uxth %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i16* - %3 = load i16* %2 + %3 = load i16, i16* %2 br label %bb2 bb2: @@ -67,7 +67,7 @@ define i64 @load_unscaled_zext_i32_to_i64(i64 %a) { ; CHECK-NOT: uxtw %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i32* - %3 = load i32* %2 + %3 = load i32, i32* %2 br label %bb2 bb2: @@ -81,7 +81,7 @@ define i32 @load_unscaled_sext_i8_to_i32(i64 %a) { ; CHECK-NOT: sxtb %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i8* - %3 = load i8* %2 + %3 = load i8, i8* %2 br label %bb2 bb2: @@ -95,7 +95,7 @@ define i32 @load_unscaled_sext_i16_to_i32(i64 %a) { ; CHECK-NOT: sxth %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i16* - %3 = load i16* %2 + %3 = load i16, i16* %2 br label %bb2 bb2: @@ -109,7 +109,7 @@ define i64 @load_unscaled_sext_i8_to_i64(i64 %a) { ; CHECK-NOT: sxtb %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i8* - %3 = load i8* %2 + %3 = load i8, i8* %2 br label %bb2 bb2: @@ -123,7 +123,7 @@ define i64 @load_unscaled_sext_i16_to_i64(i64 %a) { ; CHECK-NOT: sxth %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i16* - %3 = load i16* %2 + %3 = load i16, i16* %2 br label %bb2 bb2: @@ -137,7 +137,7 @@ define i64 @load_unscaled_sext_i32_to_i64(i64 %a) { ; CHECK-NOT: sxtw %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i32* - %3 = load i32* %2 + %3 = load i32, i32* %2 br label %bb2 bb2: @@ -152,7 +152,7 @@ define i32 @load_register_zext_i8_to_i32(i64 %a, i64 %b) { ; CHECK-NOT: uxtb %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i8* - %3 = load i8* %2 + %3 = load i8, i8* %2 br label %bb2 bb2: @@ -166,7 +166,7 @@ define i32 @load_register_zext_i16_to_i32(i64 %a, i64 %b) { ; CHECK-NOT: uxth %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i16* - %3 = load i16* %2 + %3 = load i16, i16* %2 br label %bb2 bb2: @@ -180,7 +180,7 @@ define i64 @load_register_zext_i8_to_i64(i64 %a, i64 %b) { ; CHECK-NOT: uxtb %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i8* - %3 = load i8* %2 + %3 = load i8, i8* %2 br label %bb2 bb2: @@ -194,7 +194,7 @@ define i64 @load_register_zext_i16_to_i64(i64 %a, i64 %b) { ; CHECK-NOT: uxth %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i16* - %3 = load i16* %2 + %3 = load i16, i16* %2 br label %bb2 bb2: @@ -208,7 +208,7 @@ define i64 @load_register_zext_i32_to_i64(i64 %a, i64 %b) { ; CHECK-NOT: uxtw %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i32* - %3 = load i32* %2 + %3 = load i32, i32* %2 br label %bb2 bb2: @@ -222,7 +222,7 @@ define i32 @load_register_sext_i8_to_i32(i64 %a, i64 %b) { ; CHECK-NOT: sxtb %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i8* - %3 = load i8* %2 + %3 = load i8, i8* %2 br label %bb2 bb2: @@ -236,7 +236,7 @@ define i32 @load_register_sext_i16_to_i32(i64 %a, i64 %b) { ; CHECK-NOT: sxth %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i16* - %3 = load i16* %2 + %3 = load i16, i16* %2 br label %bb2 bb2: @@ -250,7 +250,7 @@ define i64 @load_register_sext_i8_to_i64(i64 %a, i64 %b) { ; CHECK-NOT: sxtb %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i8* - %3 = load i8* %2 + %3 = load i8, i8* %2 br label %bb2 bb2: @@ -264,7 +264,7 @@ define i64 @load_register_sext_i16_to_i64(i64 %a, i64 %b) { ; CHECK-NOT: sxth %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i16* - %3 = load i16* %2 + %3 = load i16, i16* %2 br label %bb2 bb2: @@ -278,7 +278,7 @@ define i64 @load_register_sext_i32_to_i64(i64 %a, i64 %b) { ; CHECK-NOT: sxtw %1 = add i64 %a, %b %2 = inttoptr i64 %1 to i32* - %3 = load i32* %2 + %3 = load i32, i32* %2 br label %bb2 bb2: @@ -294,7 +294,7 @@ define i32 @load_extend_zext_i8_to_i32(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i8* - %4 = load i8* %3 + %4 = load i8, i8* %3 br label %bb2 bb2: @@ -309,7 +309,7 @@ define i32 @load_extend_zext_i16_to_i32(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i16* - %4 = load i16* %3 + %4 = load i16, i16* %3 br label %bb2 bb2: @@ -324,7 +324,7 @@ define i64 @load_extend_zext_i8_to_i64(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i8* - %4 = load i8* %3 + %4 = load i8, i8* %3 br label %bb2 bb2: @@ -339,7 +339,7 @@ define i64 @load_extend_zext_i16_to_i64(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i16* - %4 = load i16* %3 + %4 = load i16, i16* %3 br label %bb2 bb2: @@ -354,7 +354,7 @@ define i64 @load_extend_zext_i32_to_i64(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i32* - %4 = load i32* %3 + %4 = load i32, i32* %3 br label %bb2 bb2: @@ -369,7 +369,7 @@ define i32 @load_extend_sext_i8_to_i32(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i8* - %4 = load i8* %3 + %4 = load i8, i8* %3 br label %bb2 bb2: @@ -384,7 +384,7 @@ define i32 @load_extend_sext_i16_to_i32(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i16* - %4 = load i16* %3 + %4 = load i16, i16* %3 br label %bb2 bb2: @@ -399,7 +399,7 @@ define i64 @load_extend_sext_i8_to_i64(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i8* - %4 = load i8* %3 + %4 = load i8, i8* %3 br label %bb2 bb2: @@ -414,7 +414,7 @@ define i64 @load_extend_sext_i16_to_i64(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i16* - %4 = load i16* %3 + %4 = load i16, i16* %3 br label %bb2 bb2: @@ -429,7 +429,7 @@ define i64 @load_extend_sext_i32_to_i64(i64 %a, i32 %b) { %1 = sext i32 %b to i64 %2 = add i64 %a, %1 %3 = inttoptr i64 %2 to i32* - %4 = load i32* %3 + %4 = load i32, i32* %3 br label %bb2 bb2: diff --git a/test/CodeGen/AArch64/fast-isel-int-ext3.ll b/test/CodeGen/AArch64/fast-isel-int-ext3.ll index 5d55a6b..83740c8 100644 --- a/test/CodeGen/AArch64/fast-isel-int-ext3.ll +++ b/test/CodeGen/AArch64/fast-isel-int-ext3.ll @@ -11,7 +11,7 @@ define i32 @load_unscaled_zext_i8_to_i32(i64 %a) { ; CHECK: uxtb w0, [[REG]] %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i8 addrspace(256)* - %3 = load i8 addrspace(256)* %2 + %3 = load i8, i8 addrspace(256)* %2 %4 = zext i8 %3 to i32 ret i32 %4 } @@ -22,7 +22,7 @@ define i32 @load_unscaled_zext_i16_to_i32(i64 %a) { ; CHECK: uxth w0, [[REG]] %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i16 addrspace(256)* - %3 = load i16 addrspace(256)* %2 + %3 = load i16, i16 addrspace(256)* %2 %4 = zext i16 %3 to i32 ret i32 %4 } @@ -33,7 +33,7 @@ define i64 @load_unscaled_zext_i8_to_i64(i64 %a) { ; CHECK: ubfx x0, x[[REG]], #0, #8 %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i8 addrspace(256)* - %3 = load i8 addrspace(256)* %2 + %3 = load i8, i8 addrspace(256)* %2 %4 = zext i8 %3 to i64 ret i64 %4 } @@ -44,7 +44,7 @@ define i64 @load_unscaled_zext_i16_to_i64(i64 %a) { ; CHECK: ubfx x0, x[[REG]], #0, #16 %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i16 addrspace(256)* - %3 = load i16 addrspace(256)* %2 + %3 = load i16, i16 addrspace(256)* %2 %4 = zext i16 %3 to i64 ret i64 %4 } @@ -55,7 +55,7 @@ define i64 @load_unscaled_zext_i32_to_i64(i64 %a) { ; CHECK: ubfx x0, x[[REG]], #0, #32 %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i32 addrspace(256)* - %3 = load i32 addrspace(256)* %2 + %3 = load i32, i32 addrspace(256)* %2 %4 = zext i32 %3 to i64 ret i64 %4 } @@ -66,7 +66,7 @@ define i32 @load_unscaled_sext_i8_to_i32(i64 %a) { ; CHECK: sxtb w0, [[REG]] %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i8 addrspace(256)* - %3 = load i8 addrspace(256)* %2 + %3 = load i8, i8 addrspace(256)* %2 %4 = sext i8 %3 to i32 ret i32 %4 } @@ -77,7 +77,7 @@ define i32 @load_unscaled_sext_i16_to_i32(i64 %a) { ; CHECK: sxth w0, [[REG]] %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i16 addrspace(256)* - %3 = load i16 addrspace(256)* %2 + %3 = load i16, i16 addrspace(256)* %2 %4 = sext i16 %3 to i32 ret i32 %4 } @@ -88,7 +88,7 @@ define i64 @load_unscaled_sext_i8_to_i64(i64 %a) { ; CHECK: sxtb x0, [[REG]] %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i8 addrspace(256)* - %3 = load i8 addrspace(256)* %2 + %3 = load i8, i8 addrspace(256)* %2 %4 = sext i8 %3 to i64 ret i64 %4 } @@ -99,7 +99,7 @@ define i64 @load_unscaled_sext_i16_to_i64(i64 %a) { ; CHECK: sxth x0, [[REG]] %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i16 addrspace(256)* - %3 = load i16 addrspace(256)* %2 + %3 = load i16, i16 addrspace(256)* %2 %4 = sext i16 %3 to i64 ret i64 %4 } @@ -110,7 +110,7 @@ define i64 @load_unscaled_sext_i32_to_i64(i64 %a) { ; CHECK: sxtw x0, [[REG]] %1 = sub i64 %a, 8 %2 = inttoptr i64 %1 to i32 addrspace(256)* - %3 = load i32 addrspace(256)* %2 + %3 = load i32, i32 addrspace(256)* %2 %4 = sext i32 %3 to i64 ret i64 %4 } diff --git a/test/CodeGen/AArch64/fast-isel-int-ext4.ll b/test/CodeGen/AArch64/fast-isel-int-ext4.ll index f25bb98..1ab951b 100644 --- a/test/CodeGen/AArch64/fast-isel-int-ext4.ll +++ b/test/CodeGen/AArch64/fast-isel-int-ext4.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s define i32 @kill_flag(i16 signext %a) { ; CHECK-LABEL: kill_flag diff --git a/test/CodeGen/AArch64/fast-isel-logic-op.ll b/test/CodeGen/AArch64/fast-isel-logic-op.ll index 2c7486e..89c5f2c 100644 --- a/test/CodeGen/AArch64/fast-isel-logic-op.ll +++ b/test/CodeGen/AArch64/fast-isel-logic-op.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s ; AND define zeroext i1 @and_rr_i1(i1 signext %a, i1 signext %b) { diff --git a/test/CodeGen/AArch64/fast-isel-memcpy.ll b/test/CodeGen/AArch64/fast-isel-memcpy.ll index 9161dad..07595a9 100644 --- a/test/CodeGen/AArch64/fast-isel-memcpy.ll +++ b/test/CodeGen/AArch64/fast-isel-memcpy.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s ; Test that we don't segfault. ; CHECK-LABEL: test diff --git a/test/CodeGen/AArch64/fast-isel-mul.ll b/test/CodeGen/AArch64/fast-isel-mul.ll index f2fda27..9d6fd00 100644 --- a/test/CodeGen/AArch64/fast-isel-mul.ll +++ b/test/CodeGen/AArch64/fast-isel-mul.ll @@ -1,4 +1,4 @@ -; RUN: llc -fast-isel -fast-isel-abort -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s +; RUN: llc -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s define zeroext i8 @test_mul8(i8 %lhs, i8 %rhs) { ; CHECK-LABEL: test_mul8: diff --git a/test/CodeGen/AArch64/fast-isel-runtime-libcall.ll b/test/CodeGen/AArch64/fast-isel-runtime-libcall.ll index 8d2d39a..34d7983 100644 --- a/test/CodeGen/AArch64/fast-isel-runtime-libcall.ll +++ b/test/CodeGen/AArch64/fast-isel-runtime-libcall.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -code-model=small -verify-machineinstrs < %s | FileCheck %s --check-prefix=SMALL -; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -code-model=large -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -code-model=small -verify-machineinstrs < %s | FileCheck %s --check-prefix=SMALL +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -code-model=large -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE define float @frem_f32(float %a, float %b) { ; SMALL-LABEL: frem_f32 diff --git a/test/CodeGen/AArch64/fast-isel-sdiv.ll b/test/CodeGen/AArch64/fast-isel-sdiv.ll index 3080776..3c8de43 100644 --- a/test/CodeGen/AArch64/fast-isel-sdiv.ll +++ b/test/CodeGen/AArch64/fast-isel-sdiv.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s define i32 @sdiv_i32_exact(i32 %a) { ; CHECK-LABEL: sdiv_i32_exact diff --git a/test/CodeGen/AArch64/fast-isel-select.ll b/test/CodeGen/AArch64/fast-isel-select.ll index 928e9d4..e06f74c 100644 --- a/test/CodeGen/AArch64/fast-isel-select.ll +++ b/test/CodeGen/AArch64/fast-isel-select.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s ; First test the different supported value types for select. define zeroext i1 @select_i1(i1 zeroext %c, i1 zeroext %a, i1 zeroext %b) { diff --git a/test/CodeGen/AArch64/fast-isel-shift.ll b/test/CodeGen/AArch64/fast-isel-shift.ll index ce4ba49..36fab0d 100644 --- a/test/CodeGen/AArch64/fast-isel-shift.ll +++ b/test/CodeGen/AArch64/fast-isel-shift.ll @@ -1,4 +1,4 @@ -; RUN: llc -fast-isel -fast-isel-abort -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -fast-isel -fast-isel-abort=1 -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s ; CHECK-LABEL: asr_zext_i1_i16 ; CHECK: uxth {{w[0-9]*}}, wzr diff --git a/test/CodeGen/AArch64/fast-isel-sqrt.ll b/test/CodeGen/AArch64/fast-isel-sqrt.ll index 1331d5c..80a0a46 100644 --- a/test/CodeGen/AArch64/fast-isel-sqrt.ll +++ b/test/CodeGen/AArch64/fast-isel-sqrt.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=arm64-apple-darwin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=arm64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=arm64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s define float @test_sqrt_f32(float %a) { ; CHECK-LABEL: test_sqrt_f32 diff --git a/test/CodeGen/AArch64/fast-isel-tbz.ll b/test/CodeGen/AArch64/fast-isel-tbz.ll index a5f02ff..5988267 100644 --- a/test/CodeGen/AArch64/fast-isel-tbz.ll +++ b/test/CodeGen/AArch64/fast-isel-tbz.ll @@ -1,5 +1,5 @@ ; RUN: llc -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK %s -; RUN: llc -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK --check-prefix=FAST %s +; RUN: llc -fast-isel -fast-isel-abort=1 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK --check-prefix=FAST %s define i32 @icmp_eq_i8(i8 zeroext %a) { ; CHECK-LABEL: icmp_eq_i8 diff --git a/test/CodeGen/AArch64/fast-isel-trunc.ll b/test/CodeGen/AArch64/fast-isel-trunc.ll index 55937eb..af58abe 100644 --- a/test/CodeGen/AArch64/fast-isel-trunc.ll +++ b/test/CodeGen/AArch64/fast-isel-trunc.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s ; Test that %1 doesn't get the kill flag set before its last use. define i32 @test_trunc(i32 %a) { diff --git a/test/CodeGen/AArch64/fast-isel-vector-arithmetic.ll b/test/CodeGen/AArch64/fast-isel-vector-arithmetic.ll index eaa0db5..82b8d47 100644 --- a/test/CodeGen/AArch64/fast-isel-vector-arithmetic.ll +++ b/test/CodeGen/AArch64/fast-isel-vector-arithmetic.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -fast-isel-abort-args -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=2 -verify-machineinstrs < %s | FileCheck %s ; Vector Integer Add define <8 x i8> @add_v8i8_rr(<8 x i8> %a, <8 x i8> %b) { diff --git a/test/CodeGen/AArch64/fast-isel-vret.ll b/test/CodeGen/AArch64/fast-isel-vret.ll index 9ad9227..d8a56ce 100644 --- a/test/CodeGen/AArch64/fast-isel-vret.ll +++ b/test/CodeGen/AArch64/fast-isel-vret.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s ; Test that we don't abort fast-isle for ret define <8 x i8> @ret_v8i8(<8 x i8> %a, <8 x i8> %b) { diff --git a/test/CodeGen/AArch64/floatdp_1source.ll b/test/CodeGen/AArch64/floatdp_1source.ll index 8c02787..ec7d32d 100644 --- a/test/CodeGen/AArch64/floatdp_1source.ll +++ b/test/CodeGen/AArch64/floatdp_1source.ll @@ -27,7 +27,7 @@ declare double @nearbyint(double) readonly define void @simple_float() { ; CHECK-LABEL: simple_float: - %val1 = load volatile float* @varfloat + %val1 = load volatile float, float* @varfloat %valabs = call float @fabsf(float %val1) store volatile float %valabs, float* @varfloat @@ -66,7 +66,7 @@ define void @simple_float() { define void @simple_double() { ; CHECK-LABEL: simple_double: - %val1 = load volatile double* @vardouble + %val1 = load volatile double, double* @vardouble %valabs = call double @fabs(double %val1) store volatile double %valabs, double* @vardouble @@ -106,9 +106,9 @@ define void @simple_double() { define void @converts() { ; CHECK-LABEL: converts: - %val16 = load volatile half* @varhalf - %val32 = load volatile float* @varfloat - %val64 = load volatile double* @vardouble + %val16 = load volatile half, half* @varhalf + %val32 = load volatile float, float* @varfloat + %val64 = load volatile double, double* @vardouble %val16to32 = fpext half %val16 to float store volatile float %val16to32, float* @varfloat diff --git a/test/CodeGen/AArch64/floatdp_2source.ll b/test/CodeGen/AArch64/floatdp_2source.ll index 2622717..30e2856 100644 --- a/test/CodeGen/AArch64/floatdp_2source.ll +++ b/test/CodeGen/AArch64/floatdp_2source.ll @@ -5,7 +5,7 @@ define void @testfloat() { ; CHECK-LABEL: testfloat: - %val1 = load float* @varfloat + %val1 = load float, float* @varfloat %val2 = fadd float %val1, %val1 ; CHECK: fadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} @@ -33,7 +33,7 @@ define void @testfloat() { define void @testdouble() { ; CHECK-LABEL: testdouble: - %val1 = load double* @vardouble + %val1 = load double, double* @vardouble %val2 = fadd double %val1, %val1 ; CHECK: fadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} diff --git a/test/CodeGen/AArch64/fp128-folding.ll b/test/CodeGen/AArch64/fp128-folding.ll index 892b19c..5027e83 100644 --- a/test/CodeGen/AArch64/fp128-folding.ll +++ b/test/CodeGen/AArch64/fp128-folding.ll @@ -8,7 +8,7 @@ define fp128 @test_folding() { ; CHECK-LABEL: test_folding: %l = alloca i32 store i32 42, i32* %l - %val = load i32* %l + %val = load i32, i32* %l %fpval = sitofp i32 %val to fp128 ; If the value is loaded from a constant pool into an fp128, it's been folded ; successfully. diff --git a/test/CodeGen/AArch64/fp16-instructions.ll b/test/CodeGen/AArch64/fp16-instructions.ll index 7a44cd1..ba96694 100644 --- a/test/CodeGen/AArch64/fp16-instructions.ll +++ b/test/CodeGen/AArch64/fp16-instructions.ll @@ -52,7 +52,7 @@ define half @load_h(half* %a) { entry: ; CHECK-LABEL: load_h: ; CHECK: ldr h0, [x0] - %0 = load half* %a, align 4 + %0 = load half, half* %a, align 4 ret half %0 } diff --git a/test/CodeGen/AArch64/fp16-v4-instructions.ll b/test/CodeGen/AArch64/fp16-v4-instructions.ll index 8e89681..6db4e97 100644 --- a/test/CodeGen/AArch64/fp16-v4-instructions.ll +++ b/test/CodeGen/AArch64/fp16-v4-instructions.ll @@ -12,6 +12,15 @@ entry: } +define <4 x half> @build_h4(<4 x half> %a) { +entry: +; CHECK-LABEL: build_h4: +; CHECK: movz [[GPR:w[0-9]+]], #0x3ccd +; CHECK: dup v0.4h, [[GPR]] + ret <4 x half> <half 0xH3CCD, half 0xH3CCD, half 0xH3CCD, half 0xH3CCD> +} + + define <4 x half> @sub_h(<4 x half> %a, <4 x half> %b) { entry: ; CHECK-LABEL: sub_h: @@ -52,7 +61,7 @@ define <4 x half> @load_h(<4 x half>* %a) { entry: ; CHECK-LABEL: load_h: ; CHECK: ldr d0, [x0] - %0 = load <4 x half>* %a, align 4 + %0 = load <4 x half>, <4 x half>* %a, align 4 ret <4 x half> %0 } diff --git a/test/CodeGen/AArch64/fp16-v8-instructions.ll b/test/CodeGen/AArch64/fp16-v8-instructions.ll index b75f160..e51c0c5 100644 --- a/test/CodeGen/AArch64/fp16-v8-instructions.ll +++ b/test/CodeGen/AArch64/fp16-v8-instructions.ll @@ -164,7 +164,7 @@ define <8 x half> @load_h(<8 x half>* %a) { entry: ; CHECK-LABEL: load_h: ; CHECK: ldr q0, [x0] - %0 = load <8 x half>* %a, align 4 + %0 = load <8 x half>, <8 x half>* %a, align 4 ret <8 x half> %0 } diff --git a/test/CodeGen/AArch64/fp16-vector-load-store.ll b/test/CodeGen/AArch64/fp16-vector-load-store.ll index edbbffe..b71b39f 100644 --- a/test/CodeGen/AArch64/fp16-vector-load-store.ll +++ b/test/CodeGen/AArch64/fp16-vector-load-store.ll @@ -5,7 +5,7 @@ define <4 x half> @load_64(<4 x half>* nocapture readonly %a) #0 { ; CHECK-LABEL: load_64: ; CHECK: ldr d0, [x0] entry: - %0 = load <4 x half>* %a, align 8 + %0 = load <4 x half>, <4 x half>* %a, align 8 ret <4 x half> %0 } @@ -14,7 +14,7 @@ define <8 x half> @load_128(<8 x half>* nocapture readonly %a) #0 { ; CHECK-LABEL: load_128: ; CHECK: ldr q0, [x0] entry: - %0 = load <8 x half>* %a, align 16 + %0 = load <8 x half>, <8 x half>* %a, align 16 ret <8 x half> %0 } @@ -23,7 +23,7 @@ define <4 x half> @load_dup_64(half* nocapture readonly %a) #0 { ; CHECK-LABEL: load_dup_64: ; CHECK: ld1r { v0.4h }, [x0] entry: - %0 = load half* %a, align 2 + %0 = load half, half* %a, align 2 %1 = insertelement <4 x half> undef, half %0, i32 0 %2 = shufflevector <4 x half> %1, <4 x half> undef, <4 x i32> zeroinitializer ret <4 x half> %2 @@ -34,7 +34,7 @@ define <8 x half> @load_dup_128(half* nocapture readonly %a) #0 { ; CHECK-LABEL: load_dup_128: ; CHECK: ld1r { v0.8h }, [x0] entry: - %0 = load half* %a, align 2 + %0 = load half, half* %a, align 2 %1 = insertelement <8 x half> undef, half %0, i32 0 %2 = shufflevector <8 x half> %1, <8 x half> undef, <8 x i32> zeroinitializer ret <8 x half> %2 @@ -45,7 +45,7 @@ define <4 x half> @load_lane_64(half* nocapture readonly %a, <4 x half> %b) #0 { ; CHECK-LABEL: load_lane_64: ; CHECK: ld1 { v0.h }[2], [x0] entry: - %0 = load half* %a, align 2 + %0 = load half, half* %a, align 2 %1 = insertelement <4 x half> %b, half %0, i32 2 ret <4 x half> %1 } @@ -55,7 +55,7 @@ define <8 x half> @load_lane_128(half* nocapture readonly %a, <8 x half> %b) #0 ; CHECK-LABEL: load_lane_128: ; CHECK: ld1 { v0.h }[5], [x0] entry: - %0 = load half* %a, align 2 + %0 = load half, half* %a, align 2 %1 = insertelement <8 x half> %b, half %0, i32 5 ret <8 x half> %1 } diff --git a/test/CodeGen/AArch64/fpimm.ll b/test/CodeGen/AArch64/fpimm.ll index b7db918..6acb111 100644 --- a/test/CodeGen/AArch64/fpimm.ll +++ b/test/CodeGen/AArch64/fpimm.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE -; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE +; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE @varf32 = global float 0.0 @varf64 = global double 0.0 @@ -8,7 +8,7 @@ define void @check_float() { ; CHECK-LABEL: check_float: - %val = load float* @varf32 + %val = load float, float* @varf32 %newval1 = fadd float %val, 8.5 store volatile float %newval1, float* @varf32 ; CHECK-DAG: fmov [[EIGHT5:s[0-9]+]], #8.5 @@ -24,7 +24,7 @@ define void @check_float() { define void @check_double() { ; CHECK-LABEL: check_double: - %val = load double* @varf64 + %val = load double, double* @varf64 %newval1 = fadd double %val, 8.5 store volatile double %newval1, double* @varf64 ; CHECK-DAG: fmov {{d[0-9]+}}, #8.5 diff --git a/test/CodeGen/AArch64/frameaddr.ll b/test/CodeGen/AArch64/frameaddr.ll index d6bb50e..d965809 100644 --- a/test/CodeGen/AArch64/frameaddr.ll +++ b/test/CodeGen/AArch64/frameaddr.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s define i8* @test_frameaddress0() nounwind { entry: diff --git a/test/CodeGen/AArch64/free-zext.ll b/test/CodeGen/AArch64/free-zext.ll index d69105e..cff11f8 100644 --- a/test/CodeGen/AArch64/free-zext.ll +++ b/test/CodeGen/AArch64/free-zext.ll @@ -5,9 +5,9 @@ define i64 @test_free_zext(i8* %a, i16* %b) { ; CHECK-DAG: ldrb w[[A:[0-9]+]], [x0] ; CHECK: ldrh w[[B:[0-9]+]], [x1] ; CHECK: add x0, x[[B]], x[[A]] - %1 = load i8* %a, align 1 + %1 = load i8, i8* %a, align 1 %conv = zext i8 %1 to i64 - %2 = load i16* %b, align 2 + %2 = load i16, i16* %b, align 2 %conv1 = zext i16 %2 to i64 %add = add nsw i64 %conv1, %conv ret i64 %add diff --git a/test/CodeGen/AArch64/func-argpassing.ll b/test/CodeGen/AArch64/func-argpassing.ll index 9fc9a5f..9100ae3 100644 --- a/test/CodeGen/AArch64/func-argpassing.ll +++ b/test/CodeGen/AArch64/func-argpassing.ll @@ -34,16 +34,16 @@ define void @add_floats(float %val1, float %val2) { ; with memcpy. define void @take_struct(%myStruct* byval %structval) { ; CHECK-LABEL: take_struct: - %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2 - %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0 + %addr0 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 2 + %addr1 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 0 - %val0 = load volatile i32* %addr0 + %val0 = load volatile i32, i32* %addr0 ; Some weird move means x0 is used for one access ; CHECK: ldr [[REG32:w[0-9]+]], [{{x[0-9]+|sp}}, #12] store volatile i32 %val0, i32* @var32 ; CHECK: str [[REG32]], [{{x[0-9]+}}, {{#?}}:lo12:var32] - %val1 = load volatile i64* %addr1 + %val1 = load volatile i64, i64* %addr1 ; CHECK: ldr [[REG64:x[0-9]+]], [{{x[0-9]+|sp}}] store volatile i64 %val1, i64* @var64 ; CHECK: str [[REG64]], [{{x[0-9]+}}, {{#?}}:lo12:var64] @@ -55,16 +55,16 @@ define void @take_struct(%myStruct* byval %structval) { define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %structval) { ; CHECK-LABEL: check_byval_align: - %addr0 = getelementptr %myStruct* %structval, i64 0, i32 2 - %addr1 = getelementptr %myStruct* %structval, i64 0, i32 0 + %addr0 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 2 + %addr1 = getelementptr %myStruct, %myStruct* %structval, i64 0, i32 0 - %val0 = load volatile i32* %addr0 + %val0 = load volatile i32, i32* %addr0 ; Some weird move means x0 is used for one access ; CHECK: ldr [[REG32:w[0-9]+]], [sp, #28] store i32 %val0, i32* @var32 ; CHECK: str [[REG32]], [{{x[0-9]+}}, {{#?}}:lo12:var32] - %val1 = load volatile i64* %addr1 + %val1 = load volatile i64, i64* %addr1 ; CHECK: ldr [[REG64:x[0-9]+]], [sp, #16] store i64 %val1, i64* @var64 ; CHECK: str [[REG64]], [{{x[0-9]+}}, {{#?}}:lo12:var64] @@ -74,7 +74,7 @@ define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %st define i32 @return_int() { ; CHECK-LABEL: return_int: - %val = load i32* @var32 + %val = load i32, i32* @var32 ret i32 %val ; CHECK: ldr w0, [{{x[0-9]+}}, {{#?}}:lo12:var32] ; Make sure epilogue follows @@ -94,7 +94,7 @@ define double @return_double() { define [2 x i64] @return_struct() { ; CHECK-LABEL: return_struct: %addr = bitcast %myStruct* @varstruct to [2 x i64]* - %val = load [2 x i64]* %addr + %val = load [2 x i64], [2 x i64]* %addr ret [2 x i64] %val ; CHECK: add x[[VARSTRUCT:[0-9]+]], {{x[0-9]+}}, :lo12:varstruct ; CHECK: ldp x0, x1, [x[[VARSTRUCT]]] @@ -108,9 +108,9 @@ define [2 x i64] @return_struct() { ; if LLVM does it to %myStruct too. So this is the simplest check define void @return_large_struct(%myStruct* sret %retval) { ; CHECK-LABEL: return_large_struct: - %addr0 = getelementptr %myStruct* %retval, i64 0, i32 0 - %addr1 = getelementptr %myStruct* %retval, i64 0, i32 1 - %addr2 = getelementptr %myStruct* %retval, i64 0, i32 2 + %addr0 = getelementptr %myStruct, %myStruct* %retval, i64 0, i32 0 + %addr1 = getelementptr %myStruct, %myStruct* %retval, i64 0, i32 1 + %addr2 = getelementptr %myStruct, %myStruct* %retval, i64 0, i32 2 store i64 42, i64* %addr0 store i8 2, i8* %addr1 @@ -129,8 +129,8 @@ define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var i32* %var6, %myStruct* byval %struct, i32* byval %stacked, double %notstacked) { ; CHECK-LABEL: struct_on_stack: - %addr = getelementptr %myStruct* %struct, i64 0, i32 0 - %val64 = load volatile i64* %addr + %addr = getelementptr %myStruct, %myStruct* %struct, i64 0, i32 0 + %val64 = load volatile i64, i64* %addr store volatile i64 %val64, i64* @var64 ; Currently nothing on local stack, so struct should be at sp ; CHECK: ldr [[VAL64:x[0-9]+]], [sp] @@ -141,7 +141,7 @@ define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var ; CHECK: str d0, [{{x[0-9]+}}, {{#?}}:lo12:vardouble ; CHECK-NOFP-NOT: str d0, - %retval = load volatile i32* %stacked + %retval = load volatile i32, i32* %stacked ret i32 %retval ; CHECK-LE: ldr w0, [sp, #16] } diff --git a/test/CodeGen/AArch64/func-calls.ll b/test/CodeGen/AArch64/func-calls.ll index 16157f8..22a3315 100644 --- a/test/CodeGen/AArch64/func-calls.ll +++ b/test/CodeGen/AArch64/func-calls.ll @@ -21,15 +21,15 @@ declare void @take_floats(float %val1, float %val2) define void @simple_args() { ; CHECK-LABEL: simple_args: - %char1 = load i8* @var8 - %char2 = load i8* @var8_2 + %char1 = load i8, i8* @var8 + %char2 = load i8, i8* @var8_2 call void @take_i8s(i8 %char1, i8 %char2) ; CHECK-DAG: ldrb w0, [{{x[0-9]+}}, {{#?}}:lo12:var8] ; CHECK-DAG: ldrb w1, [{{x[0-9]+}}, {{#?}}:lo12:var8_2] ; CHECK: bl take_i8s - %float1 = load float* @varfloat - %float2 = load float* @varfloat_2 + %float1 = load float, float* @varfloat + %float2 = load float, float* @varfloat_2 call void @take_floats(float %float1, float %float2) ; CHECK-DAG: ldr s1, [{{x[0-9]+}}, {{#?}}:lo12:varfloat_2] ; CHECK-DAG: ldr s0, [{{x[0-9]+}}, {{#?}}:lo12:varfloat] @@ -124,7 +124,7 @@ declare void @check_i128_regalign(i32 %val0, i128 %val1) define void @check_i128_align() { ; CHECK-LABEL: check_i128_align: - %val = load i128* @var128 + %val = load i128, i128* @var128 call void @check_i128_stackalign(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 42, i128 %val) @@ -152,7 +152,7 @@ define void @check_i128_align() { define void @check_indirect_call() { ; CHECK-LABEL: check_indirect_call: - %func = load void()** @fptr + %func = load void()*, void()** @fptr call void %func() ; CHECK: ldr [[FPTR:x[0-9]+]], [{{x[0-9]+}}, {{#?}}:lo12:fptr] ; CHECK: blr [[FPTR]] diff --git a/test/CodeGen/AArch64/funcptr_cast.ll b/test/CodeGen/AArch64/funcptr_cast.ll index a00b7bc..506485e 100644 --- a/test/CodeGen/AArch64/funcptr_cast.ll +++ b/test/CodeGen/AArch64/funcptr_cast.ll @@ -6,7 +6,7 @@ define i8 @test() { ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, :lo12:foo ; CHECK: ldrb w0, [{{x[0-9]+}}] entry: - %0 = load i8* bitcast (void (...)* @foo to i8*), align 1 + %0 = load i8, i8* bitcast (void (...)* @foo to i8*), align 1 ret i8 %0 } diff --git a/test/CodeGen/AArch64/function-subtarget-features.ll b/test/CodeGen/AArch64/function-subtarget-features.ll new file mode 100644 index 0000000..fca6c93 --- /dev/null +++ b/test/CodeGen/AArch64/function-subtarget-features.ll @@ -0,0 +1,21 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" +target triple = "aarch64--linux-gnu" + +; This test verifies that we can enable subtarget features via +; the function attributes and generate appropriate code (or, +; in this case, select the instruction at all). + +; Function Attrs: nounwind +define <16 x i8> @foo(<16 x i8> %data, <16 x i8> %key) #0 { + %vaeseq_v.i = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key) + ret <16 x i8> %vaeseq_v.i +} + +; CHECK: foo +; CHECK: aese + +; Function Attrs: nounwind readnone +declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8>, <16 x i8>) + +attributes #0 = { nounwind "target-features"="+neon,+crc,+crypto" } diff --git a/test/CodeGen/AArch64/ghc-cc.ll b/test/CodeGen/AArch64/ghc-cc.ll index 505bd5f..01ed785 100644 --- a/test/CodeGen/AArch64/ghc-cc.ll +++ b/test/CodeGen/AArch64/ghc-cc.ll @@ -51,7 +51,7 @@ entry: ; CHECK-NEXT: bl bar_i64 ; CHECK-NEXT: ret - %0 = load i64* @base + %0 = load i64, i64* @base tail call ghccc void @bar_i64( i64 %0 ) nounwind ret void } @@ -64,7 +64,7 @@ entry: ; CHECK-NEXT: bl bar_float ; CHECK-NEXT: ret - %0 = load float* @f1 + %0 = load float, float* @f1 tail call ghccc void @bar_float( float %0 ) nounwind ret void } @@ -77,7 +77,7 @@ entry: ; CHECK-NEXT: bl bar_double ; CHECK-NEXT: ret - %0 = load double* @d1 + %0 = load double, double* @d1 tail call ghccc void @bar_double( double %0 ) nounwind ret void } diff --git a/test/CodeGen/AArch64/global-alignment.ll b/test/CodeGen/AArch64/global-alignment.ll index 451b9d6..657778e 100644 --- a/test/CodeGen/AArch64/global-alignment.ll +++ b/test/CodeGen/AArch64/global-alignment.ll @@ -11,7 +11,7 @@ define i64 @test_align32() { ; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load. - %val = load i64* %addr + %val = load i64, i64* %addr ; CHECK: adrp [[HIBITS:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[HIBITS]], {{#?}}:lo12:var32 ; CHECK: ldr x0, [x[[ADDR]]] @@ -25,7 +25,7 @@ define i64 @test_align64() { ; However, var64 *is* properly aligned and emitting an adrp/add/ldr would be ; inefficient. - %val = load i64* %addr + %val = load i64, i64* %addr ; CHECK: adrp x[[HIBITS:[0-9]+]], var64 ; CHECK-NOT: add x[[HIBITS]] ; CHECK: ldr x0, [x[[HIBITS]], {{#?}}:lo12:var64] @@ -39,7 +39,7 @@ define i64 @test_var32_align64() { ; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to ; emit an "LDR x0, [x0, #:lo12:var32] instruction to implement this load. - %val = load i64* %addr + %val = load i64, i64* %addr ; CHECK: adrp x[[HIBITS:[0-9]+]], var32_align64 ; CHECK-NOT: add x[[HIBITS]] ; CHECK: ldr x0, [x[[HIBITS]], {{#?}}:lo12:var32_align64] @@ -52,7 +52,7 @@ define i64 @test_var32_alias() { %addr = bitcast [3 x i32]* @alias to i64* ; Test that we can find the alignment for aliases. - %val = load i64* %addr + %val = load i64, i64* %addr ; CHECK: adrp x[[HIBITS:[0-9]+]], alias ; CHECK-NOT: add x[[HIBITS]] ; CHECK: ldr x0, [x[[HIBITS]], {{#?}}:lo12:alias] @@ -68,7 +68,7 @@ define i64 @test_yet_another_var() { ; @yet_another_var has a preferred alignment of 8, but that's not enough if ; we're going to be linking against other things. Its ABI alignment is only 4 ; so we can't fold the load. - %val = load i64* bitcast({i32, i32}* @yet_another_var to i64*) + %val = load i64, i64* bitcast({i32, i32}* @yet_another_var to i64*) ; CHECK: adrp [[HIBITS:x[0-9]+]], yet_another_var ; CHECK: add x[[ADDR:[0-9]+]], [[HIBITS]], {{#?}}:lo12:yet_another_var ; CHECK: ldr x0, [x[[ADDR]]] diff --git a/test/CodeGen/AArch64/global-merge-1.ll b/test/CodeGen/AArch64/global-merge-1.ll index 7dc8da1..b404389 100644 --- a/test/CodeGen/AArch64/global-merge-1.ll +++ b/test/CodeGen/AArch64/global-merge-1.ll @@ -1,11 +1,11 @@ -; RUN: llc %s -mtriple=aarch64-none-linux-gnu -enable-global-merge -o - | FileCheck %s -; RUN: llc %s -mtriple=aarch64-none-linux-gnu -enable-global-merge -global-merge-on-external -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-none-linux-gnu -O3 -enable-global-merge -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-none-linux-gnu -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s -; RUN: llc %s -mtriple=aarch64-linux-gnuabi -enable-global-merge -o - | FileCheck %s -; RUN: llc %s -mtriple=aarch64-linux-gnuabi -enable-global-merge -global-merge-on-external -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-linux-gnuabi -O3 -enable-global-merge -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-linux-gnuabi -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s -; RUN: llc %s -mtriple=aarch64-apple-ios -enable-global-merge -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS -; RUN: llc %s -mtriple=aarch64-apple-ios -enable-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS +; RUN: llc %s -mtriple=aarch64-apple-ios -O3 -enable-global-merge -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS +; RUN: llc %s -mtriple=aarch64-apple-ios -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS @m = internal global i32 0, align 4 @n = internal global i32 0, align 4 diff --git a/test/CodeGen/AArch64/global-merge-2.ll b/test/CodeGen/AArch64/global-merge-2.ll index 70b700c..d5967b9 100644 --- a/test/CodeGen/AArch64/global-merge-2.ll +++ b/test/CodeGen/AArch64/global-merge-2.ll @@ -1,6 +1,6 @@ -; RUN: llc %s -mtriple=aarch64-none-linux-gnu -enable-global-merge -global-merge-on-external -o - | FileCheck %s -; RUN: llc %s -mtriple=aarch64-linux-gnuabi -enable-global-merge -global-merge-on-external -o - | FileCheck %s -; RUN: llc %s -mtriple=aarch64-apple-ios -enable-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS +; RUN: llc %s -mtriple=aarch64-none-linux-gnu -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-linux-gnuabi -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-apple-ios -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS @x = global i32 0, align 4 @y = global i32 0, align 4 diff --git a/test/CodeGen/AArch64/global-merge-3.ll b/test/CodeGen/AArch64/global-merge-3.ll index d455d40..15035c0 100644 --- a/test/CodeGen/AArch64/global-merge-3.ll +++ b/test/CodeGen/AArch64/global-merge-3.ll @@ -1,6 +1,6 @@ -; RUN: llc %s -mtriple=aarch64-none-linux-gnu -enable-global-merge -global-merge-on-external -o - | FileCheck %s -; RUN: llc %s -mtriple=aarch64-linux-gnuabi -enable-global-merge -global-merge-on-external -o - | FileCheck %s -; RUN: llc %s -mtriple=aarch64-apple-ios -enable-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS +; RUN: llc %s -mtriple=aarch64-none-linux-gnu -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-linux-gnuabi -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-apple-ios -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS @x = global [1000 x i32] zeroinitializer, align 1 @y = global [1000 x i32] zeroinitializer, align 1 @@ -12,8 +12,8 @@ define void @f1(i32 %a1, i32 %a2, i32 %a3) { ;CHECK-APPLE-IOS: add x8, x8, __MergedGlobals_x@PAGEOFF ;CHECK-APPLE-IOS: adrp x9, __MergedGlobals_y@PAGE ;CHECK-APPLE-IOS: add x9, x9, __MergedGlobals_y@PAGEOFF - %x3 = getelementptr inbounds [1000 x i32]* @x, i32 0, i64 3 - %y3 = getelementptr inbounds [1000 x i32]* @y, i32 0, i64 3 + %x3 = getelementptr inbounds [1000 x i32], [1000 x i32]* @x, i32 0, i64 3 + %y3 = getelementptr inbounds [1000 x i32], [1000 x i32]* @y, i32 0, i64 3 store i32 %a1, i32* %x3, align 4 store i32 %a2, i32* %y3, align 4 store i32 %a3, i32* @z, align 4 diff --git a/test/CodeGen/AArch64/global-merge-4.ll b/test/CodeGen/AArch64/global-merge-4.ll index a525ccd..8fb7747 100644 --- a/test/CodeGen/AArch64/global-merge-4.ll +++ b/test/CodeGen/AArch64/global-merge-4.ll @@ -1,4 +1,4 @@ -; RUN: llc %s -mtriple=aarch64-linux-gnuabi -enable-global-merge -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-linux-gnuabi -O3 -enable-global-merge -o - | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128" target triple = "arm64-apple-ios7.0.0" @@ -10,25 +10,25 @@ target triple = "arm64-apple-ios7.0.0" ; Function Attrs: nounwind ssp define internal void @initialize() #0 { %1 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2 - store i32 %1, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 0), align 4 + store i32 %1, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 0), align 4 %2 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2 - store i32 %2, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 0), align 4 + store i32 %2, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 0), align 4 %3 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2 - store i32 %3, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 1), align 4 + store i32 %3, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 1), align 4 %4 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2 - store i32 %4, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 1), align 4 + store i32 %4, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 1), align 4 %5 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2 - store i32 %5, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 2), align 4 + store i32 %5, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 2), align 4 %6 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2 - store i32 %6, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 2), align 4 + store i32 %6, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 2), align 4 %7 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2 - store i32 %7, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 3), align 4 + store i32 %7, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 3), align 4 %8 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2 - store i32 %8, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 3), align 4 + store i32 %8, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 3), align 4 %9 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2 - store i32 %9, i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 4), align 4 + store i32 %9, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 4), align 4 %10 = tail call i32 bitcast (i32 (...)* @calc to i32 ()*)() #2 - store i32 %10, i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 4), align 4 + store i32 %10, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 4), align 4 ret void } @@ -36,32 +36,32 @@ declare i32 @calc(...) ; Function Attrs: nounwind ssp define internal void @calculate() #0 { - %1 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 0), align 4 - %2 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 0), align 4 + %1 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 0), align 4 + %2 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 0), align 4 %3 = mul nsw i32 %2, %1 - store i32 %3, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 0), align 4 - %4 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 1), align 4 - %5 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 1), align 4 + store i32 %3, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i64 0, i64 0), align 4 + %4 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 1), align 4 + %5 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 1), align 4 %6 = mul nsw i32 %5, %4 - store i32 %6, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 1), align 4 - %7 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 2), align 4 - %8 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 2), align 4 + store i32 %6, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i64 0, i64 1), align 4 + %7 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 2), align 4 + %8 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 2), align 4 %9 = mul nsw i32 %8, %7 - store i32 %9, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 2), align 4 - %10 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 3), align 4 - %11 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 3), align 4 + store i32 %9, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i64 0, i64 2), align 4 + %10 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 3), align 4 + %11 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 3), align 4 %12 = mul nsw i32 %11, %10 - store i32 %12, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 3), align 4 - %13 = load i32* getelementptr inbounds ([5 x i32]* @bar, i64 0, i64 4), align 4 - %14 = load i32* getelementptr inbounds ([5 x i32]* @baz, i64 0, i64 4), align 4 + store i32 %12, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i64 0, i64 3), align 4 + %13 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @bar, i64 0, i64 4), align 4 + %14 = load i32, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @baz, i64 0, i64 4), align 4 %15 = mul nsw i32 %14, %13 - store i32 %15, i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 4), align 4 + store i32 %15, i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i64 0, i64 4), align 4 ret void } ; Function Attrs: nounwind readnone ssp define internal i32* @returnFoo() #1 { - ret i32* getelementptr inbounds ([5 x i32]* @foo, i64 0, i64 0) + ret i32* getelementptr inbounds ([5 x i32], [5 x i32]* @foo, i64 0, i64 0) } ;CHECK: .type _MergedGlobals,@object // @_MergedGlobals diff --git a/test/CodeGen/AArch64/half.ll b/test/CodeGen/AArch64/half.ll index a46094b..d4cbbc9 100644 --- a/test/CodeGen/AArch64/half.ll +++ b/test/CodeGen/AArch64/half.ll @@ -4,7 +4,7 @@ define void @test_load_store(half* %in, half* %out) { ; CHECK-LABEL: test_load_store: ; CHECK: ldr [[TMP:h[0-9]+]], [x0] ; CHECK: str [[TMP]], [x1] - %val = load half* %in + %val = load half, half* %in store half %val, half* %out ret void } @@ -12,7 +12,7 @@ define void @test_load_store(half* %in, half* %out) { define i16 @test_bitcast_from_half(half* %addr) { ; CHECK-LABEL: test_bitcast_from_half: ; CHECK: ldrh w0, [x0] - %val = load half* %addr + %val = load half, half* %addr %val_int = bitcast half %val to i16 ret i16 %val_int } @@ -50,7 +50,7 @@ define float @test_extend32(half* %addr) { ; CHECK-LABEL: test_extend32: ; CHECK: fcvt {{s[0-9]+}}, {{h[0-9]+}} - %val16 = load half* %addr + %val16 = load half, half* %addr %val32 = fpext half %val16 to float ret float %val32 } @@ -59,7 +59,7 @@ define double @test_extend64(half* %addr) { ; CHECK-LABEL: test_extend64: ; CHECK: fcvt {{d[0-9]+}}, {{h[0-9]+}} - %val16 = load half* %addr + %val16 = load half, half* %addr %val32 = fpext half %val16 to double ret double %val32 } diff --git a/test/CodeGen/AArch64/i1-contents.ll b/test/CodeGen/AArch64/i1-contents.ll index 7f133fc..a3830e4 100644 --- a/test/CodeGen/AArch64/i1-contents.ll +++ b/test/CodeGen/AArch64/i1-contents.ll @@ -32,7 +32,7 @@ define i1 @produce_i1_ret() { ; CHECK-LABEL: produce_i1_ret: ; CHECK: ldr [[VAR32:w[0-9]+]], [{{x[0-9]+}}, :lo12:var] ; CHECK: and w0, [[VAR32]], #{{0x1|0xff}} - %val = load %big* @var + %val = load %big, %big* @var %val1 = trunc %big %val to i1 ret i1 %val1 } @@ -42,7 +42,7 @@ define void @produce_i1_arg() { ; CHECK: ldr [[VAR32:w[0-9]+]], [{{x[0-9]+}}, :lo12:var] ; CHECK: and w0, [[VAR32]], #{{0x1|0xff}} ; CHECK: bl consume_i1_arg - %val = load %big* @var + %val = load %big, %big* @var %val1 = trunc %big %val to i1 call void @consume_i1_arg(i1 %val1) ret void diff --git a/test/CodeGen/AArch64/i128-align.ll b/test/CodeGen/AArch64/i128-align.ll index a1b4d6f..c948739 100644 --- a/test/CodeGen/AArch64/i128-align.ll +++ b/test/CodeGen/AArch64/i128-align.ll @@ -8,7 +8,7 @@ define i64 @check_size() { ; CHECK-LABEL: check_size: %starti = ptrtoint %struct* @var to i64 - %endp = getelementptr %struct* @var, i64 1 + %endp = getelementptr %struct, %struct* @var, i64 1 %endi = ptrtoint %struct* %endp to i64 %diff = sub i64 %endi, %starti @@ -20,7 +20,7 @@ define i64 @check_field() { ; CHECK-LABEL: check_field: %starti = ptrtoint %struct* @var to i64 - %endp = getelementptr %struct* @var, i64 0, i32 1 + %endp = getelementptr %struct, %struct* @var, i64 0, i32 1 %endi = ptrtoint i128* %endp to i64 %diff = sub i64 %endi, %starti diff --git a/test/CodeGen/AArch64/inline-asm-globaladdress.ll b/test/CodeGen/AArch64/inline-asm-globaladdress.ll new file mode 100644 index 0000000..adebaba --- /dev/null +++ b/test/CodeGen/AArch64/inline-asm-globaladdress.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -mtriple aarch64-gnu-linux | FileCheck %s +; RUN: llc < %s -mtriple arm64-apple-darwin | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +; CHECK-LABEL: test_inlineasm_globaladdress: +; CHECK: b {{_?}}test_symbol +define void @test_inlineasm_globaladdress() { + call void asm sideeffect "b $0", "i"(void ()* @test_symbol) + ret void +} + +; CHECK-LABEL: test_inlineasm_globaladdress_offset: +; CHECK: b {{_?}}test_symbol+4 +define void @test_inlineasm_globaladdress_offset() { + call void asm sideeffect "b $0", "i"(void ()* bitcast (i8* getelementptr (i8, i8* bitcast (void ()* @test_symbol to i8*), i64 4) to void ()*)) + ret void +} + +declare void @test_symbol() diff --git a/test/CodeGen/AArch64/intrinsics-memory-barrier.ll b/test/CodeGen/AArch64/intrinsics-memory-barrier.ll index 09e34ae..2a73fee 100644 --- a/test/CodeGen/AArch64/intrinsics-memory-barrier.ll +++ b/test/CodeGen/AArch64/intrinsics-memory-barrier.ll @@ -22,7 +22,7 @@ define void @test_dmb_reordering(i32 %a, i32 %b, i32* %d) { call void @llvm.aarch64.dmb(i32 15); CHECK: dmb sy - %d1 = getelementptr i32* %d, i64 1 + %d1 = getelementptr i32, i32* %d, i64 1 store i32 %b, i32* %d1 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #4] ret void @@ -34,7 +34,7 @@ define void @test_dsb_reordering(i32 %a, i32 %b, i32* %d) { call void @llvm.aarch64.dsb(i32 15); CHECK: dsb sy - %d1 = getelementptr i32* %d, i64 1 + %d1 = getelementptr i32, i32* %d, i64 1 store i32 %b, i32* %d1 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #4] ret void @@ -46,7 +46,7 @@ define void @test_isb_reordering(i32 %a, i32 %b, i32* %d) { call void @llvm.aarch64.isb(i32 15); CHECK: isb - %d1 = getelementptr i32* %d, i64 1 + %d1 = getelementptr i32, i32* %d, i64 1 store i32 %b, i32* %d1 ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #4] ret void diff --git a/test/CodeGen/AArch64/ldst-opt.ll b/test/CodeGen/AArch64/ldst-opt.ll index e4f4295..b2c11c7 100644 --- a/test/CodeGen/AArch64/ldst-opt.ll +++ b/test/CodeGen/AArch64/ldst-opt.ll @@ -30,11 +30,11 @@ define void @load-pre-indexed-word(%struct.word* %ptr) nounwind { ; CHECK-LABEL: load-pre-indexed-word ; CHECK: ldr w{{[0-9]+}}, [x{{[0-9]+}}, #32]! entry: - %a = getelementptr inbounds %struct.word* %ptr, i64 0, i32 1, i32 0 - %add = load i32* %a, align 4 + %a = getelementptr inbounds %struct.word, %struct.word* %ptr, i64 0, i32 1, i32 0 + %add = load i32, i32* %a, align 4 br label %bar bar: - %c = getelementptr inbounds %struct.word* %ptr, i64 0, i32 1 + %c = getelementptr inbounds %struct.word, %struct.word* %ptr, i64 0, i32 1 tail call void @bar_word(%s.word* %c, i32 %add) ret void } @@ -43,11 +43,11 @@ define void @store-pre-indexed-word(%struct.word* %ptr, i32 %val) nounwind { ; CHECK-LABEL: store-pre-indexed-word ; CHECK: str w{{[0-9]+}}, [x{{[0-9]+}}, #32]! entry: - %a = getelementptr inbounds %struct.word* %ptr, i64 0, i32 1, i32 0 + %a = getelementptr inbounds %struct.word, %struct.word* %ptr, i64 0, i32 1, i32 0 store i32 %val, i32* %a, align 4 br label %bar bar: - %c = getelementptr inbounds %struct.word* %ptr, i64 0, i32 1 + %c = getelementptr inbounds %struct.word, %struct.word* %ptr, i64 0, i32 1 tail call void @bar_word(%s.word* %c, i32 %val) ret void } @@ -58,11 +58,11 @@ define void @load-pre-indexed-doubleword(%struct.doubleword* %ptr) nounwind { ; CHECK-LABEL: load-pre-indexed-doubleword ; CHECK: ldr x{{[0-9]+}}, [x{{[0-9]+}}, #32]! entry: - %a = getelementptr inbounds %struct.doubleword* %ptr, i64 0, i32 1, i32 0 - %add = load i64* %a, align 4 + %a = getelementptr inbounds %struct.doubleword, %struct.doubleword* %ptr, i64 0, i32 1, i32 0 + %add = load i64, i64* %a, align 4 br label %bar bar: - %c = getelementptr inbounds %struct.doubleword* %ptr, i64 0, i32 1 + %c = getelementptr inbounds %struct.doubleword, %struct.doubleword* %ptr, i64 0, i32 1 tail call void @bar_doubleword(%s.doubleword* %c, i64 %add) ret void } @@ -71,11 +71,11 @@ define void @store-pre-indexed-doubleword(%struct.doubleword* %ptr, i64 %val) no ; CHECK-LABEL: store-pre-indexed-doubleword ; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}, #32]! entry: - %a = getelementptr inbounds %struct.doubleword* %ptr, i64 0, i32 1, i32 0 + %a = getelementptr inbounds %struct.doubleword, %struct.doubleword* %ptr, i64 0, i32 1, i32 0 store i64 %val, i64* %a, align 4 br label %bar bar: - %c = getelementptr inbounds %struct.doubleword* %ptr, i64 0, i32 1 + %c = getelementptr inbounds %struct.doubleword, %struct.doubleword* %ptr, i64 0, i32 1 tail call void @bar_doubleword(%s.doubleword* %c, i64 %val) ret void } @@ -86,11 +86,11 @@ define void @load-pre-indexed-quadword(%struct.quadword* %ptr) nounwind { ; CHECK-LABEL: load-pre-indexed-quadword ; CHECK: ldr q{{[0-9]+}}, [x{{[0-9]+}}, #32]! entry: - %a = getelementptr inbounds %struct.quadword* %ptr, i64 0, i32 1, i32 0 - %add = load fp128* %a, align 4 + %a = getelementptr inbounds %struct.quadword, %struct.quadword* %ptr, i64 0, i32 1, i32 0 + %add = load fp128, fp128* %a, align 4 br label %bar bar: - %c = getelementptr inbounds %struct.quadword* %ptr, i64 0, i32 1 + %c = getelementptr inbounds %struct.quadword, %struct.quadword* %ptr, i64 0, i32 1 tail call void @bar_quadword(%s.quadword* %c, fp128 %add) ret void } @@ -99,11 +99,11 @@ define void @store-pre-indexed-quadword(%struct.quadword* %ptr, fp128 %val) noun ; CHECK-LABEL: store-pre-indexed-quadword ; CHECK: str q{{[0-9]+}}, [x{{[0-9]+}}, #32]! entry: - %a = getelementptr inbounds %struct.quadword* %ptr, i64 0, i32 1, i32 0 + %a = getelementptr inbounds %struct.quadword, %struct.quadword* %ptr, i64 0, i32 1, i32 0 store fp128 %val, fp128* %a, align 4 br label %bar bar: - %c = getelementptr inbounds %struct.quadword* %ptr, i64 0, i32 1 + %c = getelementptr inbounds %struct.quadword, %struct.quadword* %ptr, i64 0, i32 1 tail call void @bar_quadword(%s.quadword* %c, fp128 %val) ret void } @@ -114,11 +114,11 @@ define void @load-pre-indexed-float(%struct.float* %ptr) nounwind { ; CHECK-LABEL: load-pre-indexed-float ; CHECK: ldr s{{[0-9]+}}, [x{{[0-9]+}}, #32]! entry: - %a = getelementptr inbounds %struct.float* %ptr, i64 0, i32 1, i32 0 - %add = load float* %a, align 4 + %a = getelementptr inbounds %struct.float, %struct.float* %ptr, i64 0, i32 1, i32 0 + %add = load float, float* %a, align 4 br label %bar bar: - %c = getelementptr inbounds %struct.float* %ptr, i64 0, i32 1 + %c = getelementptr inbounds %struct.float, %struct.float* %ptr, i64 0, i32 1 tail call void @bar_float(%s.float* %c, float %add) ret void } @@ -127,11 +127,11 @@ define void @store-pre-indexed-float(%struct.float* %ptr, float %val) nounwind { ; CHECK-LABEL: store-pre-indexed-float ; CHECK: str s{{[0-9]+}}, [x{{[0-9]+}}, #32]! entry: - %a = getelementptr inbounds %struct.float* %ptr, i64 0, i32 1, i32 0 + %a = getelementptr inbounds %struct.float, %struct.float* %ptr, i64 0, i32 1, i32 0 store float %val, float* %a, align 4 br label %bar bar: - %c = getelementptr inbounds %struct.float* %ptr, i64 0, i32 1 + %c = getelementptr inbounds %struct.float, %struct.float* %ptr, i64 0, i32 1 tail call void @bar_float(%s.float* %c, float %val) ret void } @@ -142,11 +142,11 @@ define void @load-pre-indexed-double(%struct.double* %ptr) nounwind { ; CHECK-LABEL: load-pre-indexed-double ; CHECK: ldr d{{[0-9]+}}, [x{{[0-9]+}}, #32]! entry: - %a = getelementptr inbounds %struct.double* %ptr, i64 0, i32 1, i32 0 - %add = load double* %a, align 4 + %a = getelementptr inbounds %struct.double, %struct.double* %ptr, i64 0, i32 1, i32 0 + %add = load double, double* %a, align 4 br label %bar bar: - %c = getelementptr inbounds %struct.double* %ptr, i64 0, i32 1 + %c = getelementptr inbounds %struct.double, %struct.double* %ptr, i64 0, i32 1 tail call void @bar_double(%s.double* %c, double %add) ret void } @@ -155,11 +155,11 @@ define void @store-pre-indexed-double(%struct.double* %ptr, double %val) nounwin ; CHECK-LABEL: store-pre-indexed-double ; CHECK: str d{{[0-9]+}}, [x{{[0-9]+}}, #32]! entry: - %a = getelementptr inbounds %struct.double* %ptr, i64 0, i32 1, i32 0 + %a = getelementptr inbounds %struct.double, %struct.double* %ptr, i64 0, i32 1, i32 0 store double %val, double* %a, align 4 br label %bar bar: - %c = getelementptr inbounds %struct.double* %ptr, i64 0, i32 1 + %c = getelementptr inbounds %struct.double, %struct.double* %ptr, i64 0, i32 1 tail call void @bar_double(%s.double* %c, double %val) ret void } @@ -186,15 +186,15 @@ define i32 @load-pre-indexed-word2(%pre.struct.i32** %this, i1 %cond, ; CHECK: ldr w{{[0-9]+}}, [x{{[0-9]+}}, #4]! br i1 %cond, label %if.then, label %if.end if.then: - %load1 = load %pre.struct.i32** %this - %gep1 = getelementptr inbounds %pre.struct.i32* %load1, i64 0, i32 1 + %load1 = load %pre.struct.i32*, %pre.struct.i32** %this + %gep1 = getelementptr inbounds %pre.struct.i32, %pre.struct.i32* %load1, i64 0, i32 1 br label %return if.end: - %gep2 = getelementptr inbounds %pre.struct.i32* %load2, i64 0, i32 2 + %gep2 = getelementptr inbounds %pre.struct.i32, %pre.struct.i32* %load2, i64 0, i32 2 br label %return return: %retptr = phi i32* [ %gep1, %if.then ], [ %gep2, %if.end ] - %ret = load i32* %retptr + %ret = load i32, i32* %retptr ret i32 %ret } @@ -204,15 +204,15 @@ define i64 @load-pre-indexed-doubleword2(%pre.struct.i64** %this, i1 %cond, ; CHECK: ldr x{{[0-9]+}}, [x{{[0-9]+}}, #8]! br i1 %cond, label %if.then, label %if.end if.then: - %load1 = load %pre.struct.i64** %this - %gep1 = getelementptr inbounds %pre.struct.i64* %load1, i64 0, i32 1 + %load1 = load %pre.struct.i64*, %pre.struct.i64** %this + %gep1 = getelementptr inbounds %pre.struct.i64, %pre.struct.i64* %load1, i64 0, i32 1 br label %return if.end: - %gep2 = getelementptr inbounds %pre.struct.i64* %load2, i64 0, i32 2 + %gep2 = getelementptr inbounds %pre.struct.i64, %pre.struct.i64* %load2, i64 0, i32 2 br label %return return: %retptr = phi i64* [ %gep1, %if.then ], [ %gep2, %if.end ] - %ret = load i64* %retptr + %ret = load i64, i64* %retptr ret i64 %ret } @@ -222,15 +222,15 @@ define <2 x i64> @load-pre-indexed-quadword2(%pre.struct.i128** %this, i1 %cond, ; CHECK: ldr q{{[0-9]+}}, [x{{[0-9]+}}, #16]! br i1 %cond, label %if.then, label %if.end if.then: - %load1 = load %pre.struct.i128** %this - %gep1 = getelementptr inbounds %pre.struct.i128* %load1, i64 0, i32 1 + %load1 = load %pre.struct.i128*, %pre.struct.i128** %this + %gep1 = getelementptr inbounds %pre.struct.i128, %pre.struct.i128* %load1, i64 0, i32 1 br label %return if.end: - %gep2 = getelementptr inbounds %pre.struct.i128* %load2, i64 0, i32 2 + %gep2 = getelementptr inbounds %pre.struct.i128, %pre.struct.i128* %load2, i64 0, i32 2 br label %return return: %retptr = phi <2 x i64>* [ %gep1, %if.then ], [ %gep2, %if.end ] - %ret = load <2 x i64>* %retptr + %ret = load <2 x i64>, <2 x i64>* %retptr ret <2 x i64> %ret } @@ -240,15 +240,15 @@ define float @load-pre-indexed-float2(%pre.struct.float** %this, i1 %cond, ; CHECK: ldr s{{[0-9]+}}, [x{{[0-9]+}}, #4]! br i1 %cond, label %if.then, label %if.end if.then: - %load1 = load %pre.struct.float** %this - %gep1 = getelementptr inbounds %pre.struct.float* %load1, i64 0, i32 1 + %load1 = load %pre.struct.float*, %pre.struct.float** %this + %gep1 = getelementptr inbounds %pre.struct.float, %pre.struct.float* %load1, i64 0, i32 1 br label %return if.end: - %gep2 = getelementptr inbounds %pre.struct.float* %load2, i64 0, i32 2 + %gep2 = getelementptr inbounds %pre.struct.float, %pre.struct.float* %load2, i64 0, i32 2 br label %return return: %retptr = phi float* [ %gep1, %if.then ], [ %gep2, %if.end ] - %ret = load float* %retptr + %ret = load float, float* %retptr ret float %ret } @@ -258,15 +258,15 @@ define double @load-pre-indexed-double2(%pre.struct.double** %this, i1 %cond, ; CHECK: ldr d{{[0-9]+}}, [x{{[0-9]+}}, #8]! br i1 %cond, label %if.then, label %if.end if.then: - %load1 = load %pre.struct.double** %this - %gep1 = getelementptr inbounds %pre.struct.double* %load1, i64 0, i32 1 + %load1 = load %pre.struct.double*, %pre.struct.double** %this + %gep1 = getelementptr inbounds %pre.struct.double, %pre.struct.double* %load1, i64 0, i32 1 br label %return if.end: - %gep2 = getelementptr inbounds %pre.struct.double* %load2, i64 0, i32 2 + %gep2 = getelementptr inbounds %pre.struct.double, %pre.struct.double* %load2, i64 0, i32 2 br label %return return: %retptr = phi double* [ %gep1, %if.then ], [ %gep2, %if.end ] - %ret = load double* %retptr + %ret = load double, double* %retptr ret double %ret } @@ -287,11 +287,11 @@ define void @store-pre-indexed-word2(%pre.struct.i32** %this, i1 %cond, ; CHECK: str w{{[0-9]+}}, [x{{[0-9]+}}, #4]! br i1 %cond, label %if.then, label %if.end if.then: - %load1 = load %pre.struct.i32** %this - %gep1 = getelementptr inbounds %pre.struct.i32* %load1, i64 0, i32 1 + %load1 = load %pre.struct.i32*, %pre.struct.i32** %this + %gep1 = getelementptr inbounds %pre.struct.i32, %pre.struct.i32* %load1, i64 0, i32 1 br label %return if.end: - %gep2 = getelementptr inbounds %pre.struct.i32* %load2, i64 0, i32 2 + %gep2 = getelementptr inbounds %pre.struct.i32, %pre.struct.i32* %load2, i64 0, i32 2 br label %return return: %retptr = phi i32* [ %gep1, %if.then ], [ %gep2, %if.end ] @@ -306,11 +306,11 @@ define void @store-pre-indexed-doubleword2(%pre.struct.i64** %this, i1 %cond, ; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}, #8]! br i1 %cond, label %if.then, label %if.end if.then: - %load1 = load %pre.struct.i64** %this - %gep1 = getelementptr inbounds %pre.struct.i64* %load1, i64 0, i32 1 + %load1 = load %pre.struct.i64*, %pre.struct.i64** %this + %gep1 = getelementptr inbounds %pre.struct.i64, %pre.struct.i64* %load1, i64 0, i32 1 br label %return if.end: - %gep2 = getelementptr inbounds %pre.struct.i64* %load2, i64 0, i32 2 + %gep2 = getelementptr inbounds %pre.struct.i64, %pre.struct.i64* %load2, i64 0, i32 2 br label %return return: %retptr = phi i64* [ %gep1, %if.then ], [ %gep2, %if.end ] @@ -325,11 +325,11 @@ define void @store-pre-indexed-quadword2(%pre.struct.i128** %this, i1 %cond, ; CHECK: str q{{[0-9]+}}, [x{{[0-9]+}}, #16]! br i1 %cond, label %if.then, label %if.end if.then: - %load1 = load %pre.struct.i128** %this - %gep1 = getelementptr inbounds %pre.struct.i128* %load1, i64 0, i32 1 + %load1 = load %pre.struct.i128*, %pre.struct.i128** %this + %gep1 = getelementptr inbounds %pre.struct.i128, %pre.struct.i128* %load1, i64 0, i32 1 br label %return if.end: - %gep2 = getelementptr inbounds %pre.struct.i128* %load2, i64 0, i32 2 + %gep2 = getelementptr inbounds %pre.struct.i128, %pre.struct.i128* %load2, i64 0, i32 2 br label %return return: %retptr = phi <2 x i64>* [ %gep1, %if.then ], [ %gep2, %if.end ] @@ -344,11 +344,11 @@ define void @store-pre-indexed-float2(%pre.struct.float** %this, i1 %cond, ; CHECK: str s{{[0-9]+}}, [x{{[0-9]+}}, #4]! br i1 %cond, label %if.then, label %if.end if.then: - %load1 = load %pre.struct.float** %this - %gep1 = getelementptr inbounds %pre.struct.float* %load1, i64 0, i32 1 + %load1 = load %pre.struct.float*, %pre.struct.float** %this + %gep1 = getelementptr inbounds %pre.struct.float, %pre.struct.float* %load1, i64 0, i32 1 br label %return if.end: - %gep2 = getelementptr inbounds %pre.struct.float* %load2, i64 0, i32 2 + %gep2 = getelementptr inbounds %pre.struct.float, %pre.struct.float* %load2, i64 0, i32 2 br label %return return: %retptr = phi float* [ %gep1, %if.then ], [ %gep2, %if.end ] @@ -363,11 +363,11 @@ define void @store-pre-indexed-double2(%pre.struct.double** %this, i1 %cond, ; CHECK: str d{{[0-9]+}}, [x{{[0-9]+}}, #8]! br i1 %cond, label %if.then, label %if.end if.then: - %load1 = load %pre.struct.double** %this - %gep1 = getelementptr inbounds %pre.struct.double* %load1, i64 0, i32 1 + %load1 = load %pre.struct.double*, %pre.struct.double** %this + %gep1 = getelementptr inbounds %pre.struct.double, %pre.struct.double* %load1, i64 0, i32 1 br label %return if.end: - %gep2 = getelementptr inbounds %pre.struct.double* %load2, i64 0, i32 2 + %gep2 = getelementptr inbounds %pre.struct.double, %pre.struct.double* %load2, i64 0, i32 2 br label %return return: %retptr = phi double* [ %gep1, %if.then ], [ %gep2, %if.end ] @@ -389,19 +389,19 @@ define void @load-post-indexed-word(i32* %array, i64 %count) nounwind { ; CHECK-LABEL: load-post-indexed-word ; CHECK: ldr w{{[0-9]+}}, [x{{[0-9]+}}], #16 entry: - %gep1 = getelementptr i32* %array, i64 2 + %gep1 = getelementptr i32, i32* %array, i64 2 br label %body body: %iv2 = phi i32* [ %gep3, %body ], [ %gep1, %entry ] %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ] - %gep2 = getelementptr i32* %iv2, i64 -1 - %load = load i32* %gep2 + %gep2 = getelementptr i32, i32* %iv2, i64 -1 + %load = load i32, i32* %gep2 call void @use-word(i32 %load) - %load2 = load i32* %iv2 + %load2 = load i32, i32* %iv2 call void @use-word(i32 %load2) %iv.next = add i64 %iv, -4 - %gep3 = getelementptr i32* %iv2, i64 4 + %gep3 = getelementptr i32, i32* %iv2, i64 4 %cond = icmp eq i64 %iv.next, 0 br i1 %cond, label %exit, label %body @@ -413,19 +413,19 @@ define void @load-post-indexed-doubleword(i64* %array, i64 %count) nounwind { ; CHECK-LABEL: load-post-indexed-doubleword ; CHECK: ldr x{{[0-9]+}}, [x{{[0-9]+}}], #32 entry: - %gep1 = getelementptr i64* %array, i64 2 + %gep1 = getelementptr i64, i64* %array, i64 2 br label %body body: %iv2 = phi i64* [ %gep3, %body ], [ %gep1, %entry ] %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ] - %gep2 = getelementptr i64* %iv2, i64 -1 - %load = load i64* %gep2 + %gep2 = getelementptr i64, i64* %iv2, i64 -1 + %load = load i64, i64* %gep2 call void @use-doubleword(i64 %load) - %load2 = load i64* %iv2 + %load2 = load i64, i64* %iv2 call void @use-doubleword(i64 %load2) %iv.next = add i64 %iv, -4 - %gep3 = getelementptr i64* %iv2, i64 4 + %gep3 = getelementptr i64, i64* %iv2, i64 4 %cond = icmp eq i64 %iv.next, 0 br i1 %cond, label %exit, label %body @@ -437,19 +437,19 @@ define void @load-post-indexed-quadword(<2 x i64>* %array, i64 %count) nounwind ; CHECK-LABEL: load-post-indexed-quadword ; CHECK: ldr q{{[0-9]+}}, [x{{[0-9]+}}], #64 entry: - %gep1 = getelementptr <2 x i64>* %array, i64 2 + %gep1 = getelementptr <2 x i64>, <2 x i64>* %array, i64 2 br label %body body: %iv2 = phi <2 x i64>* [ %gep3, %body ], [ %gep1, %entry ] %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ] - %gep2 = getelementptr <2 x i64>* %iv2, i64 -1 - %load = load <2 x i64>* %gep2 + %gep2 = getelementptr <2 x i64>, <2 x i64>* %iv2, i64 -1 + %load = load <2 x i64>, <2 x i64>* %gep2 call void @use-quadword(<2 x i64> %load) - %load2 = load <2 x i64>* %iv2 + %load2 = load <2 x i64>, <2 x i64>* %iv2 call void @use-quadword(<2 x i64> %load2) %iv.next = add i64 %iv, -4 - %gep3 = getelementptr <2 x i64>* %iv2, i64 4 + %gep3 = getelementptr <2 x i64>, <2 x i64>* %iv2, i64 4 %cond = icmp eq i64 %iv.next, 0 br i1 %cond, label %exit, label %body @@ -461,19 +461,19 @@ define void @load-post-indexed-float(float* %array, i64 %count) nounwind { ; CHECK-LABEL: load-post-indexed-float ; CHECK: ldr s{{[0-9]+}}, [x{{[0-9]+}}], #16 entry: - %gep1 = getelementptr float* %array, i64 2 + %gep1 = getelementptr float, float* %array, i64 2 br label %body body: %iv2 = phi float* [ %gep3, %body ], [ %gep1, %entry ] %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ] - %gep2 = getelementptr float* %iv2, i64 -1 - %load = load float* %gep2 + %gep2 = getelementptr float, float* %iv2, i64 -1 + %load = load float, float* %gep2 call void @use-float(float %load) - %load2 = load float* %iv2 + %load2 = load float, float* %iv2 call void @use-float(float %load2) %iv.next = add i64 %iv, -4 - %gep3 = getelementptr float* %iv2, i64 4 + %gep3 = getelementptr float, float* %iv2, i64 4 %cond = icmp eq i64 %iv.next, 0 br i1 %cond, label %exit, label %body @@ -485,19 +485,19 @@ define void @load-post-indexed-double(double* %array, i64 %count) nounwind { ; CHECK-LABEL: load-post-indexed-double ; CHECK: ldr d{{[0-9]+}}, [x{{[0-9]+}}], #32 entry: - %gep1 = getelementptr double* %array, i64 2 + %gep1 = getelementptr double, double* %array, i64 2 br label %body body: %iv2 = phi double* [ %gep3, %body ], [ %gep1, %entry ] %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ] - %gep2 = getelementptr double* %iv2, i64 -1 - %load = load double* %gep2 + %gep2 = getelementptr double, double* %iv2, i64 -1 + %load = load double, double* %gep2 call void @use-double(double %load) - %load2 = load double* %iv2 + %load2 = load double, double* %iv2 call void @use-double(double %load2) %iv.next = add i64 %iv, -4 - %gep3 = getelementptr double* %iv2, i64 4 + %gep3 = getelementptr double, double* %iv2, i64 4 %cond = icmp eq i64 %iv.next, 0 br i1 %cond, label %exit, label %body @@ -519,18 +519,18 @@ define void @store-post-indexed-word(i32* %array, i64 %count, i32 %val) nounwind ; CHECK-LABEL: store-post-indexed-word ; CHECK: str w{{[0-9]+}}, [x{{[0-9]+}}], #16 entry: - %gep1 = getelementptr i32* %array, i64 2 + %gep1 = getelementptr i32, i32* %array, i64 2 br label %body body: %iv2 = phi i32* [ %gep3, %body ], [ %gep1, %entry ] %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ] - %gep2 = getelementptr i32* %iv2, i64 -1 - %load = load i32* %gep2 + %gep2 = getelementptr i32, i32* %iv2, i64 -1 + %load = load i32, i32* %gep2 call void @use-word(i32 %load) store i32 %val, i32* %iv2 %iv.next = add i64 %iv, -4 - %gep3 = getelementptr i32* %iv2, i64 4 + %gep3 = getelementptr i32, i32* %iv2, i64 4 %cond = icmp eq i64 %iv.next, 0 br i1 %cond, label %exit, label %body @@ -542,18 +542,18 @@ define void @store-post-indexed-doubleword(i64* %array, i64 %count, i64 %val) no ; CHECK-LABEL: store-post-indexed-doubleword ; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}], #32 entry: - %gep1 = getelementptr i64* %array, i64 2 + %gep1 = getelementptr i64, i64* %array, i64 2 br label %body body: %iv2 = phi i64* [ %gep3, %body ], [ %gep1, %entry ] %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ] - %gep2 = getelementptr i64* %iv2, i64 -1 - %load = load i64* %gep2 + %gep2 = getelementptr i64, i64* %iv2, i64 -1 + %load = load i64, i64* %gep2 call void @use-doubleword(i64 %load) store i64 %val, i64* %iv2 %iv.next = add i64 %iv, -4 - %gep3 = getelementptr i64* %iv2, i64 4 + %gep3 = getelementptr i64, i64* %iv2, i64 4 %cond = icmp eq i64 %iv.next, 0 br i1 %cond, label %exit, label %body @@ -565,18 +565,18 @@ define void @store-post-indexed-quadword(<2 x i64>* %array, i64 %count, <2 x i64 ; CHECK-LABEL: store-post-indexed-quadword ; CHECK: str q{{[0-9]+}}, [x{{[0-9]+}}], #64 entry: - %gep1 = getelementptr <2 x i64>* %array, i64 2 + %gep1 = getelementptr <2 x i64>, <2 x i64>* %array, i64 2 br label %body body: %iv2 = phi <2 x i64>* [ %gep3, %body ], [ %gep1, %entry ] %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ] - %gep2 = getelementptr <2 x i64>* %iv2, i64 -1 - %load = load <2 x i64>* %gep2 + %gep2 = getelementptr <2 x i64>, <2 x i64>* %iv2, i64 -1 + %load = load <2 x i64>, <2 x i64>* %gep2 call void @use-quadword(<2 x i64> %load) store <2 x i64> %val, <2 x i64>* %iv2 %iv.next = add i64 %iv, -4 - %gep3 = getelementptr <2 x i64>* %iv2, i64 4 + %gep3 = getelementptr <2 x i64>, <2 x i64>* %iv2, i64 4 %cond = icmp eq i64 %iv.next, 0 br i1 %cond, label %exit, label %body @@ -588,18 +588,18 @@ define void @store-post-indexed-float(float* %array, i64 %count, float %val) nou ; CHECK-LABEL: store-post-indexed-float ; CHECK: str s{{[0-9]+}}, [x{{[0-9]+}}], #16 entry: - %gep1 = getelementptr float* %array, i64 2 + %gep1 = getelementptr float, float* %array, i64 2 br label %body body: %iv2 = phi float* [ %gep3, %body ], [ %gep1, %entry ] %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ] - %gep2 = getelementptr float* %iv2, i64 -1 - %load = load float* %gep2 + %gep2 = getelementptr float, float* %iv2, i64 -1 + %load = load float, float* %gep2 call void @use-float(float %load) store float %val, float* %iv2 %iv.next = add i64 %iv, -4 - %gep3 = getelementptr float* %iv2, i64 4 + %gep3 = getelementptr float, float* %iv2, i64 4 %cond = icmp eq i64 %iv.next, 0 br i1 %cond, label %exit, label %body @@ -611,18 +611,18 @@ define void @store-post-indexed-double(double* %array, i64 %count, double %val) ; CHECK-LABEL: store-post-indexed-double ; CHECK: str d{{[0-9]+}}, [x{{[0-9]+}}], #32 entry: - %gep1 = getelementptr double* %array, i64 2 + %gep1 = getelementptr double, double* %array, i64 2 br label %body body: %iv2 = phi double* [ %gep3, %body ], [ %gep1, %entry ] %iv = phi i64 [ %iv.next, %body ], [ %count, %entry ] - %gep2 = getelementptr double* %iv2, i64 -1 - %load = load double* %gep2 + %gep2 = getelementptr double, double* %iv2, i64 -1 + %load = load double, double* %gep2 call void @use-double(double %load) store double %val, double* %iv2 %iv.next = add i64 %iv, -4 - %gep3 = getelementptr double* %iv2, i64 4 + %gep3 = getelementptr double, double* %iv2, i64 4 %cond = icmp eq i64 %iv.next, 0 br i1 %cond, label %exit, label %body @@ -655,15 +655,15 @@ for.body: %phi1 = phi i32* [ %gep4, %for.body ], [ %b, %0 ] %phi2 = phi i32* [ %gep3, %for.body ], [ %a, %0 ] %i = phi i64 [ %dec.i, %for.body], [ %count, %0 ] - %gep1 = getelementptr i32* %phi1, i64 -1 - %load1 = load i32* %gep1 - %gep2 = getelementptr i32* %phi2, i64 -1 + %gep1 = getelementptr i32, i32* %phi1, i64 -1 + %load1 = load i32, i32* %gep1 + %gep2 = getelementptr i32, i32* %phi2, i64 -1 store i32 %load1, i32* %gep2 - %load2 = load i32* %phi1 + %load2 = load i32, i32* %phi1 store i32 %load2, i32* %phi2 %dec.i = add nsw i64 %i, -1 - %gep3 = getelementptr i32* %phi2, i64 -2 - %gep4 = getelementptr i32* %phi1, i64 -2 + %gep3 = getelementptr i32, i32* %phi2, i64 -2 + %gep4 = getelementptr i32, i32* %phi1, i64 -2 %cond = icmp sgt i64 %dec.i, 0 br i1 %cond, label %for.body, label %end end: @@ -679,15 +679,15 @@ for.body: %phi1 = phi i64* [ %gep4, %for.body ], [ %b, %0 ] %phi2 = phi i64* [ %gep3, %for.body ], [ %a, %0 ] %i = phi i64 [ %dec.i, %for.body], [ %count, %0 ] - %gep1 = getelementptr i64* %phi1, i64 -1 - %load1 = load i64* %gep1 - %gep2 = getelementptr i64* %phi2, i64 -1 + %gep1 = getelementptr i64, i64* %phi1, i64 -1 + %load1 = load i64, i64* %gep1 + %gep2 = getelementptr i64, i64* %phi2, i64 -1 store i64 %load1, i64* %gep2 - %load2 = load i64* %phi1 + %load2 = load i64, i64* %phi1 store i64 %load2, i64* %phi2 %dec.i = add nsw i64 %i, -1 - %gep3 = getelementptr i64* %phi2, i64 -2 - %gep4 = getelementptr i64* %phi1, i64 -2 + %gep3 = getelementptr i64, i64* %phi2, i64 -2 + %gep4 = getelementptr i64, i64* %phi1, i64 -2 %cond = icmp sgt i64 %dec.i, 0 br i1 %cond, label %for.body, label %end end: @@ -703,15 +703,15 @@ for.body: %phi1 = phi <2 x i64>* [ %gep4, %for.body ], [ %b, %0 ] %phi2 = phi <2 x i64>* [ %gep3, %for.body ], [ %a, %0 ] %i = phi i64 [ %dec.i, %for.body], [ %count, %0 ] - %gep1 = getelementptr <2 x i64>* %phi1, i64 -1 - %load1 = load <2 x i64>* %gep1 - %gep2 = getelementptr <2 x i64>* %phi2, i64 -1 + %gep1 = getelementptr <2 x i64>, <2 x i64>* %phi1, i64 -1 + %load1 = load <2 x i64>, <2 x i64>* %gep1 + %gep2 = getelementptr <2 x i64>, <2 x i64>* %phi2, i64 -1 store <2 x i64> %load1, <2 x i64>* %gep2 - %load2 = load <2 x i64>* %phi1 + %load2 = load <2 x i64>, <2 x i64>* %phi1 store <2 x i64> %load2, <2 x i64>* %phi2 %dec.i = add nsw i64 %i, -1 - %gep3 = getelementptr <2 x i64>* %phi2, i64 -2 - %gep4 = getelementptr <2 x i64>* %phi1, i64 -2 + %gep3 = getelementptr <2 x i64>, <2 x i64>* %phi2, i64 -2 + %gep4 = getelementptr <2 x i64>, <2 x i64>* %phi1, i64 -2 %cond = icmp sgt i64 %dec.i, 0 br i1 %cond, label %for.body, label %end end: @@ -727,15 +727,15 @@ for.body: %phi1 = phi float* [ %gep4, %for.body ], [ %b, %0 ] %phi2 = phi float* [ %gep3, %for.body ], [ %a, %0 ] %i = phi i64 [ %dec.i, %for.body], [ %count, %0 ] - %gep1 = getelementptr float* %phi1, i64 -1 - %load1 = load float* %gep1 - %gep2 = getelementptr float* %phi2, i64 -1 + %gep1 = getelementptr float, float* %phi1, i64 -1 + %load1 = load float, float* %gep1 + %gep2 = getelementptr float, float* %phi2, i64 -1 store float %load1, float* %gep2 - %load2 = load float* %phi1 + %load2 = load float, float* %phi1 store float %load2, float* %phi2 %dec.i = add nsw i64 %i, -1 - %gep3 = getelementptr float* %phi2, i64 -2 - %gep4 = getelementptr float* %phi1, i64 -2 + %gep3 = getelementptr float, float* %phi2, i64 -2 + %gep4 = getelementptr float, float* %phi1, i64 -2 %cond = icmp sgt i64 %dec.i, 0 br i1 %cond, label %for.body, label %end end: @@ -751,15 +751,15 @@ for.body: %phi1 = phi double* [ %gep4, %for.body ], [ %b, %0 ] %phi2 = phi double* [ %gep3, %for.body ], [ %a, %0 ] %i = phi i64 [ %dec.i, %for.body], [ %count, %0 ] - %gep1 = getelementptr double* %phi1, i64 -1 - %load1 = load double* %gep1 - %gep2 = getelementptr double* %phi2, i64 -1 + %gep1 = getelementptr double, double* %phi1, i64 -1 + %load1 = load double, double* %gep1 + %gep2 = getelementptr double, double* %phi2, i64 -1 store double %load1, double* %gep2 - %load2 = load double* %phi1 + %load2 = load double, double* %phi1 store double %load2, double* %phi2 %dec.i = add nsw i64 %i, -1 - %gep3 = getelementptr double* %phi2, i64 -2 - %gep4 = getelementptr double* %phi1, i64 -2 + %gep3 = getelementptr double, double* %phi2, i64 -2 + %gep4 = getelementptr double, double* %phi1, i64 -2 %cond = icmp sgt i64 %dec.i, 0 br i1 %cond, label %for.body, label %end end: diff --git a/test/CodeGen/AArch64/ldst-regoffset.ll b/test/CodeGen/AArch64/ldst-regoffset.ll index e2fa08b..85d6db1 100644 --- a/test/CodeGen/AArch64/ldst-regoffset.ll +++ b/test/CodeGen/AArch64/ldst-regoffset.ll @@ -12,14 +12,14 @@ define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) minsize { ; CHECK-LABEL: ldst_8bit: - %addr8_sxtw = getelementptr i8* %base, i32 %off32 - %val8_sxtw = load volatile i8* %addr8_sxtw + %addr8_sxtw = getelementptr i8, i8* %base, i32 %off32 + %val8_sxtw = load volatile i8, i8* %addr8_sxtw %val32_signed = sext i8 %val8_sxtw to i32 store volatile i32 %val32_signed, i32* @var_32bit ; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{[wx][0-9]+}}, sxtw] - %addr_lsl = getelementptr i8* %base, i64 %off64 - %val8_lsl = load volatile i8* %addr_lsl + %addr_lsl = getelementptr i8, i8* %base, i64 %off64 + %val8_lsl = load volatile i8, i8* %addr_lsl %val32_unsigned = zext i8 %val8_lsl to i32 store volatile i32 %val32_unsigned, i32* @var_32bit ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}] @@ -28,7 +28,7 @@ define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) minsize { %offset_uxtw = zext i32 %off32 to i64 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw %addr_uxtw = inttoptr i64 %addrint1_uxtw to i8* - %val8_uxtw = load volatile i8* %addr_uxtw + %val8_uxtw = load volatile i8, i8* %addr_uxtw %newval8 = add i8 %val8_uxtw, 1 store volatile i8 %newval8, i8* @var_8bit ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] @@ -40,14 +40,14 @@ define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) minsize { define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) minsize { ; CHECK-LABEL: ldst_16bit: - %addr8_sxtwN = getelementptr i16* %base, i32 %off32 - %val8_sxtwN = load volatile i16* %addr8_sxtwN + %addr8_sxtwN = getelementptr i16, i16* %base, i32 %off32 + %val8_sxtwN = load volatile i16, i16* %addr8_sxtwN %val32_signed = sext i16 %val8_sxtwN to i32 store volatile i32 %val32_signed, i32* @var_32bit ; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #1] - %addr_lslN = getelementptr i16* %base, i64 %off64 - %val8_lslN = load volatile i16* %addr_lslN + %addr_lslN = getelementptr i16, i16* %base, i64 %off64 + %val8_lslN = load volatile i16, i16* %addr_lslN %val32_unsigned = zext i16 %val8_lslN to i32 store volatile i32 %val32_unsigned, i32* @var_32bit ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #1] @@ -56,7 +56,7 @@ define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) minsize { %offset_uxtw = zext i32 %off32 to i64 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw %addr_uxtw = inttoptr i64 %addrint1_uxtw to i16* - %val8_uxtw = load volatile i16* %addr_uxtw + %val8_uxtw = load volatile i16, i16* %addr_uxtw %newval8 = add i16 %val8_uxtw, 1 store volatile i16 %newval8, i16* @var_16bit ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] @@ -65,7 +65,7 @@ define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) minsize { %offset_sxtw = sext i32 %off32 to i64 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw %addr_sxtw = inttoptr i64 %addrint_sxtw to i16* - %val16_sxtw = load volatile i16* %addr_sxtw + %val16_sxtw = load volatile i16, i16* %addr_sxtw %val64_signed = sext i16 %val16_sxtw to i64 store volatile i64 %val64_signed, i64* @var_64bit ; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{[wx][0-9]+}}, sxtw] @@ -74,7 +74,7 @@ define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) minsize { %base_lsl = ptrtoint i16* %base to i64 %addrint_lsl = add i64 %base_lsl, %off64 %addr_lsl = inttoptr i64 %addrint_lsl to i16* - %val16_lsl = load volatile i16* %addr_lsl + %val16_lsl = load volatile i16, i16* %addr_lsl %val64_unsigned = zext i16 %val16_lsl to i64 store volatile i64 %val64_unsigned, i64* @var_64bit ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}] @@ -84,7 +84,7 @@ define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) minsize { %offset2_uxtwN = shl i64 %offset_uxtwN, 1 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i16* - %val32 = load volatile i32* @var_32bit + %val32 = load volatile i32, i32* @var_32bit %val16_trunc32 = trunc i32 %val32 to i16 store volatile i16 %val16_trunc32, i16* %addr_uxtwN ; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #1] @@ -94,13 +94,13 @@ define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) minsize { define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) minsize { ; CHECK-LABEL: ldst_32bit: - %addr_sxtwN = getelementptr i32* %base, i32 %off32 - %val_sxtwN = load volatile i32* %addr_sxtwN + %addr_sxtwN = getelementptr i32, i32* %base, i32 %off32 + %val_sxtwN = load volatile i32, i32* %addr_sxtwN store volatile i32 %val_sxtwN, i32* @var_32bit ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #2] - %addr_lslN = getelementptr i32* %base, i64 %off64 - %val_lslN = load volatile i32* %addr_lslN + %addr_lslN = getelementptr i32, i32* %base, i64 %off64 + %val_lslN = load volatile i32, i32* %addr_lslN store volatile i32 %val_lslN, i32* @var_32bit ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #2] @@ -108,7 +108,7 @@ define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) minsize { %offset_uxtw = zext i32 %off32 to i64 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw %addr_uxtw = inttoptr i64 %addrint1_uxtw to i32* - %val_uxtw = load volatile i32* %addr_uxtw + %val_uxtw = load volatile i32, i32* %addr_uxtw %newval8 = add i32 %val_uxtw, 1 store volatile i32 %newval8, i32* @var_32bit ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] @@ -118,7 +118,7 @@ define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) minsize { %offset_sxtw = sext i32 %off32 to i64 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw %addr_sxtw = inttoptr i64 %addrint_sxtw to i32* - %val16_sxtw = load volatile i32* %addr_sxtw + %val16_sxtw = load volatile i32, i32* %addr_sxtw %val64_signed = sext i32 %val16_sxtw to i64 store volatile i64 %val64_signed, i64* @var_64bit ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw] @@ -127,7 +127,7 @@ define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) minsize { %base_lsl = ptrtoint i32* %base to i64 %addrint_lsl = add i64 %base_lsl, %off64 %addr_lsl = inttoptr i64 %addrint_lsl to i32* - %val16_lsl = load volatile i32* %addr_lsl + %val16_lsl = load volatile i32, i32* %addr_lsl %val64_unsigned = zext i32 %val16_lsl to i64 store volatile i64 %val64_unsigned, i64* @var_64bit ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}] @@ -137,7 +137,7 @@ define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) minsize { %offset2_uxtwN = shl i64 %offset_uxtwN, 2 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i32* - %val32 = load volatile i32* @var_32bit + %val32 = load volatile i32, i32* @var_32bit store volatile i32 %val32, i32* %addr_uxtwN ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #2] ret void @@ -146,13 +146,13 @@ define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) minsize { define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) minsize { ; CHECK-LABEL: ldst_64bit: - %addr_sxtwN = getelementptr i64* %base, i32 %off32 - %val_sxtwN = load volatile i64* %addr_sxtwN + %addr_sxtwN = getelementptr i64, i64* %base, i32 %off32 + %val_sxtwN = load volatile i64, i64* %addr_sxtwN store volatile i64 %val_sxtwN, i64* @var_64bit ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #3] - %addr_lslN = getelementptr i64* %base, i64 %off64 - %val_lslN = load volatile i64* %addr_lslN + %addr_lslN = getelementptr i64, i64* %base, i64 %off64 + %val_lslN = load volatile i64, i64* %addr_lslN store volatile i64 %val_lslN, i64* @var_64bit ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #3] @@ -160,7 +160,7 @@ define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) minsize { %offset_uxtw = zext i32 %off32 to i64 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw %addr_uxtw = inttoptr i64 %addrint1_uxtw to i64* - %val8_uxtw = load volatile i64* %addr_uxtw + %val8_uxtw = load volatile i64, i64* %addr_uxtw %newval8 = add i64 %val8_uxtw, 1 store volatile i64 %newval8, i64* @var_64bit ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] @@ -169,14 +169,14 @@ define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) minsize { %offset_sxtw = sext i32 %off32 to i64 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw %addr_sxtw = inttoptr i64 %addrint_sxtw to i64* - %val64_sxtw = load volatile i64* %addr_sxtw + %val64_sxtw = load volatile i64, i64* %addr_sxtw store volatile i64 %val64_sxtw, i64* @var_64bit ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw] %base_lsl = ptrtoint i64* %base to i64 %addrint_lsl = add i64 %base_lsl, %off64 %addr_lsl = inttoptr i64 %addrint_lsl to i64* - %val64_lsl = load volatile i64* %addr_lsl + %val64_lsl = load volatile i64, i64* %addr_lsl store volatile i64 %val64_lsl, i64* @var_64bit ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}] @@ -185,7 +185,7 @@ define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) minsize { %offset2_uxtwN = shl i64 %offset_uxtwN, 3 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i64* - %val64 = load volatile i64* @var_64bit + %val64 = load volatile i64, i64* @var_64bit store volatile i64 %val64, i64* %addr_uxtwN ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #3] ret void @@ -194,14 +194,14 @@ define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) minsize { define void @ldst_float(float* %base, i32 %off32, i64 %off64) minsize { ; CHECK-LABEL: ldst_float: - %addr_sxtwN = getelementptr float* %base, i32 %off32 - %val_sxtwN = load volatile float* %addr_sxtwN + %addr_sxtwN = getelementptr float, float* %base, i32 %off32 + %val_sxtwN = load volatile float, float* %addr_sxtwN store volatile float %val_sxtwN, float* @var_float ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #2] ; CHECK-NOFP-NOT: ldr {{s[0-9]+}}, - %addr_lslN = getelementptr float* %base, i64 %off64 - %val_lslN = load volatile float* %addr_lslN + %addr_lslN = getelementptr float, float* %base, i64 %off64 + %val_lslN = load volatile float, float* %addr_lslN store volatile float %val_lslN, float* @var_float ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #2] ; CHECK-NOFP-NOT: ldr {{s[0-9]+}}, @@ -210,7 +210,7 @@ define void @ldst_float(float* %base, i32 %off32, i64 %off64) minsize { %offset_uxtw = zext i32 %off32 to i64 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw %addr_uxtw = inttoptr i64 %addrint1_uxtw to float* - %val_uxtw = load volatile float* %addr_uxtw + %val_uxtw = load volatile float, float* %addr_uxtw store volatile float %val_uxtw, float* @var_float ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] ; CHECK-NOFP-NOT: ldr {{s[0-9]+}}, @@ -219,7 +219,7 @@ define void @ldst_float(float* %base, i32 %off32, i64 %off64) minsize { %offset_sxtw = sext i32 %off32 to i64 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw %addr_sxtw = inttoptr i64 %addrint_sxtw to float* - %val64_sxtw = load volatile float* %addr_sxtw + %val64_sxtw = load volatile float, float* %addr_sxtw store volatile float %val64_sxtw, float* @var_float ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw] ; CHECK-NOFP-NOT: ldr {{s[0-9]+}}, @@ -227,7 +227,7 @@ define void @ldst_float(float* %base, i32 %off32, i64 %off64) minsize { %base_lsl = ptrtoint float* %base to i64 %addrint_lsl = add i64 %base_lsl, %off64 %addr_lsl = inttoptr i64 %addrint_lsl to float* - %val64_lsl = load volatile float* %addr_lsl + %val64_lsl = load volatile float, float* %addr_lsl store volatile float %val64_lsl, float* @var_float ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}] ; CHECK-NOFP-NOT: ldr {{s[0-9]+}}, @@ -237,7 +237,7 @@ define void @ldst_float(float* %base, i32 %off32, i64 %off64) minsize { %offset2_uxtwN = shl i64 %offset_uxtwN, 2 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN %addr_uxtwN = inttoptr i64 %addrint_uxtwN to float* - %val64 = load volatile float* @var_float + %val64 = load volatile float, float* @var_float store volatile float %val64, float* %addr_uxtwN ; CHECK: str {{s[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #2] ; CHECK-NOFP-NOT: ldr {{s[0-9]+}}, @@ -247,14 +247,14 @@ define void @ldst_float(float* %base, i32 %off32, i64 %off64) minsize { define void @ldst_double(double* %base, i32 %off32, i64 %off64) minsize { ; CHECK-LABEL: ldst_double: - %addr_sxtwN = getelementptr double* %base, i32 %off32 - %val_sxtwN = load volatile double* %addr_sxtwN + %addr_sxtwN = getelementptr double, double* %base, i32 %off32 + %val_sxtwN = load volatile double, double* %addr_sxtwN store volatile double %val_sxtwN, double* @var_double ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #3] ; CHECK-NOFP-NOT: ldr {{d[0-9]+}}, - %addr_lslN = getelementptr double* %base, i64 %off64 - %val_lslN = load volatile double* %addr_lslN + %addr_lslN = getelementptr double, double* %base, i64 %off64 + %val_lslN = load volatile double, double* %addr_lslN store volatile double %val_lslN, double* @var_double ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #3] ; CHECK-NOFP-NOT: ldr {{d[0-9]+}}, @@ -263,7 +263,7 @@ define void @ldst_double(double* %base, i32 %off32, i64 %off64) minsize { %offset_uxtw = zext i32 %off32 to i64 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw %addr_uxtw = inttoptr i64 %addrint1_uxtw to double* - %val_uxtw = load volatile double* %addr_uxtw + %val_uxtw = load volatile double, double* %addr_uxtw store volatile double %val_uxtw, double* @var_double ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] ; CHECK-NOFP-NOT: ldr {{d[0-9]+}}, @@ -272,7 +272,7 @@ define void @ldst_double(double* %base, i32 %off32, i64 %off64) minsize { %offset_sxtw = sext i32 %off32 to i64 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw %addr_sxtw = inttoptr i64 %addrint_sxtw to double* - %val64_sxtw = load volatile double* %addr_sxtw + %val64_sxtw = load volatile double, double* %addr_sxtw store volatile double %val64_sxtw, double* @var_double ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw] ; CHECK-NOFP-NOT: ldr {{d[0-9]+}}, @@ -280,7 +280,7 @@ define void @ldst_double(double* %base, i32 %off32, i64 %off64) minsize { %base_lsl = ptrtoint double* %base to i64 %addrint_lsl = add i64 %base_lsl, %off64 %addr_lsl = inttoptr i64 %addrint_lsl to double* - %val64_lsl = load volatile double* %addr_lsl + %val64_lsl = load volatile double, double* %addr_lsl store volatile double %val64_lsl, double* @var_double ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}] ; CHECK-NOFP-NOT: ldr {{d[0-9]+}}, @@ -290,7 +290,7 @@ define void @ldst_double(double* %base, i32 %off32, i64 %off64) minsize { %offset2_uxtwN = shl i64 %offset_uxtwN, 3 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN %addr_uxtwN = inttoptr i64 %addrint_uxtwN to double* - %val64 = load volatile double* @var_double + %val64 = load volatile double, double* @var_double store volatile double %val64, double* %addr_uxtwN ; CHECK: str {{d[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #3] ; CHECK-NOFP-NOT: ldr {{d[0-9]+}}, @@ -301,14 +301,14 @@ define void @ldst_double(double* %base, i32 %off32, i64 %off64) minsize { define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) minsize { ; CHECK-LABEL: ldst_128bit: - %addr_sxtwN = getelementptr fp128* %base, i32 %off32 - %val_sxtwN = load volatile fp128* %addr_sxtwN + %addr_sxtwN = getelementptr fp128, fp128* %base, i32 %off32 + %val_sxtwN = load volatile fp128, fp128* %addr_sxtwN store volatile fp128 %val_sxtwN, fp128* %base ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4] ; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4] - %addr_lslN = getelementptr fp128* %base, i64 %off64 - %val_lslN = load volatile fp128* %addr_lslN + %addr_lslN = getelementptr fp128, fp128* %base, i64 %off64 + %val_lslN = load volatile fp128, fp128* %addr_lslN store volatile fp128 %val_lslN, fp128* %base ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}, lsl #4] ; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4] @@ -317,7 +317,7 @@ define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) minsize { %offset_uxtw = zext i32 %off32 to i64 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw %addr_uxtw = inttoptr i64 %addrint1_uxtw to fp128* - %val_uxtw = load volatile fp128* %addr_uxtw + %val_uxtw = load volatile fp128, fp128* %addr_uxtw store volatile fp128 %val_uxtw, fp128* %base ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw] ; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4] @@ -326,7 +326,7 @@ define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) minsize { %offset_sxtw = sext i32 %off32 to i64 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw %addr_sxtw = inttoptr i64 %addrint_sxtw to fp128* - %val64_sxtw = load volatile fp128* %addr_sxtw + %val64_sxtw = load volatile fp128, fp128* %addr_sxtw store volatile fp128 %val64_sxtw, fp128* %base ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw] ; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4] @@ -334,7 +334,7 @@ define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) minsize { %base_lsl = ptrtoint fp128* %base to i64 %addrint_lsl = add i64 %base_lsl, %off64 %addr_lsl = inttoptr i64 %addrint_lsl to fp128* - %val64_lsl = load volatile fp128* %addr_lsl + %val64_lsl = load volatile fp128, fp128* %addr_lsl store volatile fp128 %val64_lsl, fp128* %base ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}] ; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4] @@ -344,7 +344,7 @@ define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) minsize { %offset2_uxtwN = shl i64 %offset_uxtwN, 4 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN %addr_uxtwN = inttoptr i64 %addrint_uxtwN to fp128* - %val64 = load volatile fp128* %base + %val64 = load volatile fp128, fp128* %base store volatile fp128 %val64, fp128* %addr_uxtwN ; CHECK: str {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, uxtw #4] ; CHECK-NOFP-NOT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw #4] diff --git a/test/CodeGen/AArch64/ldst-unscaledimm.ll b/test/CodeGen/AArch64/ldst-unscaledimm.ll index 1de8443..a362597 100644 --- a/test/CodeGen/AArch64/ldst-unscaledimm.ll +++ b/test/CodeGen/AArch64/ldst-unscaledimm.ll @@ -16,32 +16,32 @@ define void @ldst_8bit() { ; No architectural support for loads to 16-bit or 8-bit since we ; promote i8 during lowering. - %addr_8bit = load i8** @varptr + %addr_8bit = load i8*, i8** @varptr ; match a sign-extending load 8-bit -> 32-bit - %addr_sext32 = getelementptr i8* %addr_8bit, i64 -256 - %val8_sext32 = load volatile i8* %addr_sext32 + %addr_sext32 = getelementptr i8, i8* %addr_8bit, i64 -256 + %val8_sext32 = load volatile i8, i8* %addr_sext32 %val32_signed = sext i8 %val8_sext32 to i32 store volatile i32 %val32_signed, i32* @var_32bit ; CHECK: ldursb {{w[0-9]+}}, [{{x[0-9]+}}, #-256] ; match a zero-extending load volatile 8-bit -> 32-bit - %addr_zext32 = getelementptr i8* %addr_8bit, i64 -12 - %val8_zext32 = load volatile i8* %addr_zext32 + %addr_zext32 = getelementptr i8, i8* %addr_8bit, i64 -12 + %val8_zext32 = load volatile i8, i8* %addr_zext32 %val32_unsigned = zext i8 %val8_zext32 to i32 store volatile i32 %val32_unsigned, i32* @var_32bit ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-12] ; match an any-extending load volatile 8-bit -> 32-bit - %addr_anyext = getelementptr i8* %addr_8bit, i64 -1 - %val8_anyext = load volatile i8* %addr_anyext + %addr_anyext = getelementptr i8, i8* %addr_8bit, i64 -1 + %val8_anyext = load volatile i8, i8* %addr_anyext %newval8 = add i8 %val8_anyext, 1 store volatile i8 %newval8, i8* @var_8bit ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-1] ; match a sign-extending load volatile 8-bit -> 64-bit - %addr_sext64 = getelementptr i8* %addr_8bit, i64 -5 - %val8_sext64 = load volatile i8* %addr_sext64 + %addr_sext64 = getelementptr i8, i8* %addr_8bit, i64 -5 + %val8_sext64 = load volatile i8, i8* %addr_sext64 %val64_signed = sext i8 %val8_sext64 to i64 store volatile i64 %val64_signed, i64* @var_64bit ; CHECK: ldursb {{x[0-9]+}}, [{{x[0-9]+}}, #-5] @@ -49,22 +49,22 @@ define void @ldst_8bit() { ; match a zero-extending load volatile 8-bit -> 64-bit. ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits ; of x0 so it's identical to load volatileing to 32-bits. - %addr_zext64 = getelementptr i8* %addr_8bit, i64 -9 - %val8_zext64 = load volatile i8* %addr_zext64 + %addr_zext64 = getelementptr i8, i8* %addr_8bit, i64 -9 + %val8_zext64 = load volatile i8, i8* %addr_zext64 %val64_unsigned = zext i8 %val8_zext64 to i64 store volatile i64 %val64_unsigned, i64* @var_64bit ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-9] ; truncating store volatile 32-bits to 8-bits - %addr_trunc32 = getelementptr i8* %addr_8bit, i64 -256 - %val32 = load volatile i32* @var_32bit + %addr_trunc32 = getelementptr i8, i8* %addr_8bit, i64 -256 + %val32 = load volatile i32, i32* @var_32bit %val8_trunc32 = trunc i32 %val32 to i8 store volatile i8 %val8_trunc32, i8* %addr_trunc32 ; CHECK: sturb {{w[0-9]+}}, [{{x[0-9]+}}, #-256] ; truncating store volatile 64-bits to 8-bits - %addr_trunc64 = getelementptr i8* %addr_8bit, i64 -1 - %val64 = load volatile i64* @var_64bit + %addr_trunc64 = getelementptr i8, i8* %addr_8bit, i64 -1 + %val64 = load volatile i64, i64* @var_64bit %val8_trunc64 = trunc i64 %val64 to i8 store volatile i8 %val8_trunc64, i8* %addr_trunc64 ; CHECK: sturb {{w[0-9]+}}, [{{x[0-9]+}}, #-1] @@ -77,36 +77,36 @@ define void @ldst_16bit() { ; No architectural support for loads to 16-bit or 16-bit since we ; promote i16 during lowering. - %addr_8bit = load i8** @varptr + %addr_8bit = load i8*, i8** @varptr ; match a sign-extending load 16-bit -> 32-bit - %addr8_sext32 = getelementptr i8* %addr_8bit, i64 -256 + %addr8_sext32 = getelementptr i8, i8* %addr_8bit, i64 -256 %addr_sext32 = bitcast i8* %addr8_sext32 to i16* - %val16_sext32 = load volatile i16* %addr_sext32 + %val16_sext32 = load volatile i16, i16* %addr_sext32 %val32_signed = sext i16 %val16_sext32 to i32 store volatile i32 %val32_signed, i32* @var_32bit ; CHECK: ldursh {{w[0-9]+}}, [{{x[0-9]+}}, #-256] ; match a zero-extending load volatile 16-bit -> 32-bit. With offset that would be unaligned. - %addr8_zext32 = getelementptr i8* %addr_8bit, i64 15 + %addr8_zext32 = getelementptr i8, i8* %addr_8bit, i64 15 %addr_zext32 = bitcast i8* %addr8_zext32 to i16* - %val16_zext32 = load volatile i16* %addr_zext32 + %val16_zext32 = load volatile i16, i16* %addr_zext32 %val32_unsigned = zext i16 %val16_zext32 to i32 store volatile i32 %val32_unsigned, i32* @var_32bit ; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #15] ; match an any-extending load volatile 16-bit -> 32-bit - %addr8_anyext = getelementptr i8* %addr_8bit, i64 -1 + %addr8_anyext = getelementptr i8, i8* %addr_8bit, i64 -1 %addr_anyext = bitcast i8* %addr8_anyext to i16* - %val16_anyext = load volatile i16* %addr_anyext + %val16_anyext = load volatile i16, i16* %addr_anyext %newval16 = add i16 %val16_anyext, 1 store volatile i16 %newval16, i16* @var_16bit ; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #-1] ; match a sign-extending load volatile 16-bit -> 64-bit - %addr8_sext64 = getelementptr i8* %addr_8bit, i64 -5 + %addr8_sext64 = getelementptr i8, i8* %addr_8bit, i64 -5 %addr_sext64 = bitcast i8* %addr8_sext64 to i16* - %val16_sext64 = load volatile i16* %addr_sext64 + %val16_sext64 = load volatile i16, i16* %addr_sext64 %val64_signed = sext i16 %val16_sext64 to i64 store volatile i64 %val64_signed, i64* @var_64bit ; CHECK: ldursh {{x[0-9]+}}, [{{x[0-9]+}}, #-5] @@ -114,25 +114,25 @@ define void @ldst_16bit() { ; match a zero-extending load volatile 16-bit -> 64-bit. ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits ; of x0 so it's identical to load volatileing to 32-bits. - %addr8_zext64 = getelementptr i8* %addr_8bit, i64 9 + %addr8_zext64 = getelementptr i8, i8* %addr_8bit, i64 9 %addr_zext64 = bitcast i8* %addr8_zext64 to i16* - %val16_zext64 = load volatile i16* %addr_zext64 + %val16_zext64 = load volatile i16, i16* %addr_zext64 %val64_unsigned = zext i16 %val16_zext64 to i64 store volatile i64 %val64_unsigned, i64* @var_64bit ; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #9] ; truncating store volatile 32-bits to 16-bits - %addr8_trunc32 = getelementptr i8* %addr_8bit, i64 -256 + %addr8_trunc32 = getelementptr i8, i8* %addr_8bit, i64 -256 %addr_trunc32 = bitcast i8* %addr8_trunc32 to i16* - %val32 = load volatile i32* @var_32bit + %val32 = load volatile i32, i32* @var_32bit %val16_trunc32 = trunc i32 %val32 to i16 store volatile i16 %val16_trunc32, i16* %addr_trunc32 ; CHECK: sturh {{w[0-9]+}}, [{{x[0-9]+}}, #-256] ; truncating store volatile 64-bits to 16-bits - %addr8_trunc64 = getelementptr i8* %addr_8bit, i64 -1 + %addr8_trunc64 = getelementptr i8, i8* %addr_8bit, i64 -1 %addr_trunc64 = bitcast i8* %addr8_trunc64 to i16* - %val64 = load volatile i64* @var_64bit + %val64 = load volatile i64, i64* @var_64bit %val16_trunc64 = trunc i64 %val64 to i16 store volatile i16 %val16_trunc64, i16* %addr_trunc64 ; CHECK: sturh {{w[0-9]+}}, [{{x[0-9]+}}, #-1] @@ -143,41 +143,41 @@ define void @ldst_16bit() { define void @ldst_32bit() { ; CHECK-LABEL: ldst_32bit: - %addr_8bit = load i8** @varptr + %addr_8bit = load i8*, i8** @varptr ; Straight 32-bit load/store - %addr32_8_noext = getelementptr i8* %addr_8bit, i64 1 + %addr32_8_noext = getelementptr i8, i8* %addr_8bit, i64 1 %addr32_noext = bitcast i8* %addr32_8_noext to i32* - %val32_noext = load volatile i32* %addr32_noext + %val32_noext = load volatile i32, i32* %addr32_noext store volatile i32 %val32_noext, i32* %addr32_noext ; CHECK: ldur {{w[0-9]+}}, [{{x[0-9]+}}, #1] ; CHECK: stur {{w[0-9]+}}, [{{x[0-9]+}}, #1] ; Zero-extension to 64-bits - %addr32_8_zext = getelementptr i8* %addr_8bit, i64 -256 + %addr32_8_zext = getelementptr i8, i8* %addr_8bit, i64 -256 %addr32_zext = bitcast i8* %addr32_8_zext to i32* - %val32_zext = load volatile i32* %addr32_zext + %val32_zext = load volatile i32, i32* %addr32_zext %val64_unsigned = zext i32 %val32_zext to i64 store volatile i64 %val64_unsigned, i64* @var_64bit ; CHECK: ldur {{w[0-9]+}}, [{{x[0-9]+}}, #-256] ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit] ; Sign-extension to 64-bits - %addr32_8_sext = getelementptr i8* %addr_8bit, i64 -12 + %addr32_8_sext = getelementptr i8, i8* %addr_8bit, i64 -12 %addr32_sext = bitcast i8* %addr32_8_sext to i32* - %val32_sext = load volatile i32* %addr32_sext + %val32_sext = load volatile i32, i32* %addr32_sext %val64_signed = sext i32 %val32_sext to i64 store volatile i64 %val64_signed, i64* @var_64bit ; CHECK: ldursw {{x[0-9]+}}, [{{x[0-9]+}}, #-12] ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit] ; Truncation from 64-bits - %addr64_8_trunc = getelementptr i8* %addr_8bit, i64 255 + %addr64_8_trunc = getelementptr i8, i8* %addr_8bit, i64 255 %addr64_trunc = bitcast i8* %addr64_8_trunc to i64* - %addr32_8_trunc = getelementptr i8* %addr_8bit, i64 -20 + %addr32_8_trunc = getelementptr i8, i8* %addr_8bit, i64 -20 %addr32_trunc = bitcast i8* %addr32_8_trunc to i32* - %val64_trunc = load volatile i64* %addr64_trunc + %val64_trunc = load volatile i64, i64* %addr64_trunc %val32_trunc = trunc i64 %val64_trunc to i32 store volatile i32 %val32_trunc, i32* %addr32_trunc ; CHECK: ldur {{x[0-9]+}}, [{{x[0-9]+}}, #255] @@ -189,11 +189,11 @@ define void @ldst_32bit() { define void @ldst_float() { ; CHECK-LABEL: ldst_float: - %addr_8bit = load i8** @varptr - %addrfp_8 = getelementptr i8* %addr_8bit, i64 -5 + %addr_8bit = load i8*, i8** @varptr + %addrfp_8 = getelementptr i8, i8* %addr_8bit, i64 -5 %addrfp = bitcast i8* %addrfp_8 to float* - %valfp = load volatile float* %addrfp + %valfp = load volatile float, float* %addrfp ; CHECK: ldur {{s[0-9]+}}, [{{x[0-9]+}}, #-5] ; CHECK-NOFP-NOT: ldur {{s[0-9]+}}, @@ -207,11 +207,11 @@ define void @ldst_float() { define void @ldst_double() { ; CHECK-LABEL: ldst_double: - %addr_8bit = load i8** @varptr - %addrfp_8 = getelementptr i8* %addr_8bit, i64 4 + %addr_8bit = load i8*, i8** @varptr + %addrfp_8 = getelementptr i8, i8* %addr_8bit, i64 4 %addrfp = bitcast i8* %addrfp_8 to double* - %valfp = load volatile double* %addrfp + %valfp = load volatile double, double* %addrfp ; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #4] ; CHECK-NOFP-NOT: ldur {{d[0-9]+}}, diff --git a/test/CodeGen/AArch64/ldst-unsignedimm.ll b/test/CodeGen/AArch64/ldst-unsignedimm.ll index e171d22..9777d3e 100644 --- a/test/CodeGen/AArch64/ldst-unsignedimm.ll +++ b/test/CodeGen/AArch64/ldst-unsignedimm.ll @@ -16,26 +16,26 @@ define void @ldst_8bit() { ; promote i8 during lowering. ; match a sign-extending load 8-bit -> 32-bit - %val8_sext32 = load volatile i8* @var_8bit + %val8_sext32 = load volatile i8, i8* @var_8bit %val32_signed = sext i8 %val8_sext32 to i32 store volatile i32 %val32_signed, i32* @var_32bit ; CHECK: adrp {{x[0-9]+}}, var_8bit ; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit] ; match a zero-extending load volatile 8-bit -> 32-bit - %val8_zext32 = load volatile i8* @var_8bit + %val8_zext32 = load volatile i8, i8* @var_8bit %val32_unsigned = zext i8 %val8_zext32 to i32 store volatile i32 %val32_unsigned, i32* @var_32bit ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit] ; match an any-extending load volatile 8-bit -> 32-bit - %val8_anyext = load volatile i8* @var_8bit + %val8_anyext = load volatile i8, i8* @var_8bit %newval8 = add i8 %val8_anyext, 1 store volatile i8 %newval8, i8* @var_8bit ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit] ; match a sign-extending load volatile 8-bit -> 64-bit - %val8_sext64 = load volatile i8* @var_8bit + %val8_sext64 = load volatile i8, i8* @var_8bit %val64_signed = sext i8 %val8_sext64 to i64 store volatile i64 %val64_signed, i64* @var_64bit ; CHECK: ldrsb {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit] @@ -43,19 +43,19 @@ define void @ldst_8bit() { ; match a zero-extending load volatile 8-bit -> 64-bit. ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits ; of x0 so it's identical to load volatileing to 32-bits. - %val8_zext64 = load volatile i8* @var_8bit + %val8_zext64 = load volatile i8, i8* @var_8bit %val64_unsigned = zext i8 %val8_zext64 to i64 store volatile i64 %val64_unsigned, i64* @var_64bit ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit] ; truncating store volatile 32-bits to 8-bits - %val32 = load volatile i32* @var_32bit + %val32 = load volatile i32, i32* @var_32bit %val8_trunc32 = trunc i32 %val32 to i8 store volatile i8 %val8_trunc32, i8* @var_8bit ; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit] ; truncating store volatile 64-bits to 8-bits - %val64 = load volatile i64* @var_64bit + %val64 = load volatile i64, i64* @var_64bit %val8_trunc64 = trunc i64 %val64 to i8 store volatile i8 %val8_trunc64, i8* @var_8bit ; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit] @@ -70,26 +70,26 @@ define void @ldst_16bit() { ; lowering. ; match a sign-extending load volatile 16-bit -> 32-bit - %val16_sext32 = load volatile i16* @var_16bit + %val16_sext32 = load volatile i16, i16* @var_16bit %val32_signed = sext i16 %val16_sext32 to i32 store volatile i32 %val32_signed, i32* @var_32bit ; CHECK: adrp {{x[0-9]+}}, var_16bit ; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit] ; match a zero-extending load volatile 16-bit -> 32-bit - %val16_zext32 = load volatile i16* @var_16bit + %val16_zext32 = load volatile i16, i16* @var_16bit %val32_unsigned = zext i16 %val16_zext32 to i32 store volatile i32 %val32_unsigned, i32* @var_32bit ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit] ; match an any-extending load volatile 16-bit -> 32-bit - %val16_anyext = load volatile i16* @var_16bit + %val16_anyext = load volatile i16, i16* @var_16bit %newval16 = add i16 %val16_anyext, 1 store volatile i16 %newval16, i16* @var_16bit ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit] ; match a sign-extending load volatile 16-bit -> 64-bit - %val16_sext64 = load volatile i16* @var_16bit + %val16_sext64 = load volatile i16, i16* @var_16bit %val64_signed = sext i16 %val16_sext64 to i64 store volatile i64 %val64_signed, i64* @var_64bit ; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit] @@ -97,19 +97,19 @@ define void @ldst_16bit() { ; match a zero-extending load volatile 16-bit -> 64-bit. ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits ; of x0 so it's identical to load volatileing to 32-bits. - %val16_zext64 = load volatile i16* @var_16bit + %val16_zext64 = load volatile i16, i16* @var_16bit %val64_unsigned = zext i16 %val16_zext64 to i64 store volatile i64 %val64_unsigned, i64* @var_64bit ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit] ; truncating store volatile 32-bits to 16-bits - %val32 = load volatile i32* @var_32bit + %val32 = load volatile i32, i32* @var_32bit %val16_trunc32 = trunc i32 %val32 to i16 store volatile i16 %val16_trunc32, i16* @var_16bit ; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit] ; truncating store volatile 64-bits to 16-bits - %val64 = load volatile i64* @var_64bit + %val64 = load volatile i64, i64* @var_64bit %val16_trunc64 = trunc i64 %val64 to i16 store volatile i16 %val16_trunc64, i16* @var_16bit ; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit] @@ -121,28 +121,28 @@ define void @ldst_32bit() { ; CHECK-LABEL: ldst_32bit: ; Straight 32-bit load/store - %val32_noext = load volatile i32* @var_32bit + %val32_noext = load volatile i32, i32* @var_32bit store volatile i32 %val32_noext, i32* @var_32bit ; CHECK: adrp {{x[0-9]+}}, var_32bit ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit] ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit] ; Zero-extension to 64-bits - %val32_zext = load volatile i32* @var_32bit + %val32_zext = load volatile i32, i32* @var_32bit %val64_unsigned = zext i32 %val32_zext to i64 store volatile i64 %val64_unsigned, i64* @var_64bit ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit] ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit] ; Sign-extension to 64-bits - %val32_sext = load volatile i32* @var_32bit + %val32_sext = load volatile i32, i32* @var_32bit %val64_signed = sext i32 %val32_sext to i64 store volatile i64 %val64_signed, i64* @var_64bit ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit] ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit] ; Truncation from 64-bits - %val64_trunc = load volatile i64* @var_64bit + %val64_trunc = load volatile i64, i64* @var_64bit %val32_trunc = trunc i64 %val64_trunc to i32 store volatile i32 %val32_trunc, i32* @var_32bit ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit] @@ -163,62 +163,62 @@ define void @ldst_32bit() { define void @ldst_complex_offsets() { ; CHECK: ldst_complex_offsets - %arr8_addr = load volatile i8** @arr8 + %arr8_addr = load volatile i8*, i8** @arr8 ; CHECK: adrp {{x[0-9]+}}, arr8 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr8] - %arr8_sub1_addr = getelementptr i8* %arr8_addr, i64 1 - %arr8_sub1 = load volatile i8* %arr8_sub1_addr + %arr8_sub1_addr = getelementptr i8, i8* %arr8_addr, i64 1 + %arr8_sub1 = load volatile i8, i8* %arr8_sub1_addr store volatile i8 %arr8_sub1, i8* @var_8bit ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #1] - %arr8_sub4095_addr = getelementptr i8* %arr8_addr, i64 4095 - %arr8_sub4095 = load volatile i8* %arr8_sub4095_addr + %arr8_sub4095_addr = getelementptr i8, i8* %arr8_addr, i64 4095 + %arr8_sub4095 = load volatile i8, i8* %arr8_sub4095_addr store volatile i8 %arr8_sub4095, i8* @var_8bit ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #4095] - %arr16_addr = load volatile i16** @arr16 + %arr16_addr = load volatile i16*, i16** @arr16 ; CHECK: adrp {{x[0-9]+}}, arr16 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr16] - %arr16_sub1_addr = getelementptr i16* %arr16_addr, i64 1 - %arr16_sub1 = load volatile i16* %arr16_sub1_addr + %arr16_sub1_addr = getelementptr i16, i16* %arr16_addr, i64 1 + %arr16_sub1 = load volatile i16, i16* %arr16_sub1_addr store volatile i16 %arr16_sub1, i16* @var_16bit ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, #2] - %arr16_sub4095_addr = getelementptr i16* %arr16_addr, i64 4095 - %arr16_sub4095 = load volatile i16* %arr16_sub4095_addr + %arr16_sub4095_addr = getelementptr i16, i16* %arr16_addr, i64 4095 + %arr16_sub4095 = load volatile i16, i16* %arr16_sub4095_addr store volatile i16 %arr16_sub4095, i16* @var_16bit ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, #8190] - %arr32_addr = load volatile i32** @arr32 + %arr32_addr = load volatile i32*, i32** @arr32 ; CHECK: adrp {{x[0-9]+}}, arr32 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr32] - %arr32_sub1_addr = getelementptr i32* %arr32_addr, i64 1 - %arr32_sub1 = load volatile i32* %arr32_sub1_addr + %arr32_sub1_addr = getelementptr i32, i32* %arr32_addr, i64 1 + %arr32_sub1 = load volatile i32, i32* %arr32_sub1_addr store volatile i32 %arr32_sub1, i32* @var_32bit ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, #4] - %arr32_sub4095_addr = getelementptr i32* %arr32_addr, i64 4095 - %arr32_sub4095 = load volatile i32* %arr32_sub4095_addr + %arr32_sub4095_addr = getelementptr i32, i32* %arr32_addr, i64 4095 + %arr32_sub4095 = load volatile i32, i32* %arr32_sub4095_addr store volatile i32 %arr32_sub4095, i32* @var_32bit ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, #16380] - %arr64_addr = load volatile i64** @arr64 + %arr64_addr = load volatile i64*, i64** @arr64 ; CHECK: adrp {{x[0-9]+}}, arr64 ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr64] - %arr64_sub1_addr = getelementptr i64* %arr64_addr, i64 1 - %arr64_sub1 = load volatile i64* %arr64_sub1_addr + %arr64_sub1_addr = getelementptr i64, i64* %arr64_addr, i64 1 + %arr64_sub1 = load volatile i64, i64* %arr64_sub1_addr store volatile i64 %arr64_sub1, i64* @var_64bit ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #8] - %arr64_sub4095_addr = getelementptr i64* %arr64_addr, i64 4095 - %arr64_sub4095 = load volatile i64* %arr64_sub4095_addr + %arr64_sub4095_addr = getelementptr i64, i64* %arr64_addr, i64 4095 + %arr64_sub4095 = load volatile i64, i64* %arr64_sub4095_addr store volatile i64 %arr64_sub4095, i64* @var_64bit ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #32760] @@ -228,7 +228,7 @@ define void @ldst_complex_offsets() { define void @ldst_float() { ; CHECK-LABEL: ldst_float: - %valfp = load volatile float* @var_float + %valfp = load volatile float, float* @var_float ; CHECK: adrp {{x[0-9]+}}, var_float ; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_float] ; CHECK-NOFP-NOT: ldr {{s[0-9]+}}, @@ -243,7 +243,7 @@ define void @ldst_float() { define void @ldst_double() { ; CHECK-LABEL: ldst_double: - %valfp = load volatile double* @var_double + %valfp = load volatile double, double* @var_double ; CHECK: adrp {{x[0-9]+}}, var_double ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_double] ; CHECK-NOFP-NOT: ldr {{d[0-9]+}}, diff --git a/test/CodeGen/AArch64/literal_pools_float.ll b/test/CodeGen/AArch64/literal_pools_float.ll index e53b8b6..f5d6a17 100644 --- a/test/CodeGen/AArch64/literal_pools_float.ll +++ b/test/CodeGen/AArch64/literal_pools_float.ll @@ -9,7 +9,7 @@ define void @floating_lits() { ; CHECK-LABEL: floating_lits: - %floatval = load float* @varfloat + %floatval = load float, float* @varfloat %newfloat = fadd float %floatval, 128.0 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI[0-9]+_[0-9]+]] ; CHECK: ldr [[LIT128:s[0-9]+]], [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]] @@ -26,7 +26,7 @@ define void @floating_lits() { store float %newfloat, float* @varfloat - %doubleval = load double* @vardouble + %doubleval = load double, double* @vardouble %newdouble = fadd double %doubleval, 129.0 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI[0-9]+_[0-9]+]] ; CHECK: ldr [[LIT129:d[0-9]+]], [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]] diff --git a/test/CodeGen/AArch64/local_vars.ll b/test/CodeGen/AArch64/local_vars.ll index 2f5b9f2..332d660 100644 --- a/test/CodeGen/AArch64/local_vars.ll +++ b/test/CodeGen/AArch64/local_vars.ll @@ -49,7 +49,7 @@ define void @stack_local() { ; CHECK-LABEL: stack_local: ; CHECK: sub sp, sp, #16 - %val = load i64* @var + %val = load i64, i64* @var store i64 %val, i64* %local_var ; CHECK-DAG: str {{x[0-9]+}}, [sp, #{{[0-9]+}}] diff --git a/test/CodeGen/AArch64/logical_shifted_reg.ll b/test/CodeGen/AArch64/logical_shifted_reg.ll index b249d72..6b3246d 100644 --- a/test/CodeGen/AArch64/logical_shifted_reg.ll +++ b/test/CodeGen/AArch64/logical_shifted_reg.ll @@ -8,8 +8,8 @@ define void @logical_32bit() minsize { ; CHECK-LABEL: logical_32bit: - %val1 = load i32* @var1_32 - %val2 = load i32* @var2_32 + %val1 = load i32, i32* @var1_32 + %val2 = load i32, i32* @var2_32 ; First check basic and/bic/or/orn/eor/eon patterns with no shift %neg_val2 = xor i32 -1, %val2 @@ -98,8 +98,8 @@ define void @logical_32bit() minsize { define void @logical_64bit() minsize { ; CHECK-LABEL: logical_64bit: - %val1 = load i64* @var1_64 - %val2 = load i64* @var2_64 + %val1 = load i64, i64* @var1_64 + %val2 = load i64, i64* @var2_64 ; First check basic and/bic/or/orn/eor/eon patterns with no shift %neg_val2 = xor i64 -1, %val2 @@ -191,8 +191,8 @@ define void @logical_64bit() minsize { define void @flag_setting() { ; CHECK-LABEL: flag_setting: - %val1 = load i64* @var1_64 - %val2 = load i64* @var2_64 + %val1 = load i64, i64* @var1_64 + %val2 = load i64, i64* @var2_64 ; CHECK: tst {{x[0-9]+}}, {{x[0-9]+}} ; CHECK: b.gt .L diff --git a/test/CodeGen/AArch64/machine-copy-prop.ll b/test/CodeGen/AArch64/machine-copy-prop.ll new file mode 100644 index 0000000..6bacf85 --- /dev/null +++ b/test/CodeGen/AArch64/machine-copy-prop.ll @@ -0,0 +1,101 @@ +; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=cortex-a57 -verify-machineinstrs < %s | FileCheck %s + +; This file check a bug in MachineCopyPropagation pass. The last COPY will be +; incorrectly removed if the machine instructions are as follows: +; %Q5_Q6<def> = COPY %Q2_Q3 +; %D5<def> = +; %D3<def> = +; %D3<def> = COPY %D6 +; This is caused by a bug in function SourceNoLongerAvailable(), which fails to +; remove the relationship of D6 and "%Q5_Q6<def> = COPY %Q2_Q3". + +@failed = internal unnamed_addr global i1 false + +; CHECK-LABEL: foo: +; CHECK: ld2 +; CHECK-NOT: // kill: D{{[0-9]+}}<def> D{{[0-9]+}}<kill> +define void @foo(<2 x i32> %shuffle251, <8 x i8> %vtbl1.i, i8* %t2, <2 x i32> %vrsubhn_v2.i1364) { +entry: + %val0 = alloca [2 x i64], align 8 + %val1 = alloca <2 x i64>, align 16 + %vmull = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> <i32 -1, i32 -1>, <2 x i32> %shuffle251) + %vgetq_lane = extractelement <2 x i64> %vmull, i32 0 + %cmp = icmp eq i64 %vgetq_lane, 1 + br i1 %cmp, label %if.end, label %if.then + +if.then: ; preds = %entry + store i1 true, i1* @failed, align 1 + br label %if.end + +if.end: ; preds = %if.then, %entry + tail call void @f2() + %sqdmull = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> <i16 1, i16 0, i16 0, i16 0>, <4 x i16> <i16 2, i16 0, i16 0, i16 0>) + %sqadd = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> zeroinitializer, <4 x i32> %sqdmull) + %shuffle = shufflevector <4 x i32> %sqadd, <4 x i32> undef, <2 x i32> zeroinitializer + %0 = mul <2 x i32> %shuffle, <i32 -1, i32 0> + %sub = add <2 x i32> %0, <i32 1, i32 0> + %sext = sext <2 x i32> %sub to <2 x i64> + %vset_lane603 = shufflevector <2 x i64> %sext, <2 x i64> undef, <1 x i32> zeroinitializer + %t1 = bitcast [2 x i64]* %val0 to i8* + call void @llvm.aarch64.neon.st2lane.v2i64.p0i8(<2 x i64> zeroinitializer, <2 x i64> zeroinitializer, i64 1, i8* %t1) + call void @llvm.aarch64.neon.st2lane.v1i64.p0i8(<1 x i64> <i64 4096>, <1 x i64> <i64 -1>, i64 0, i8* %t2) + %vld2_lane = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i8(<1 x i64> <i64 11>, <1 x i64> <i64 11>, i64 0, i8* %t2) + %vld2_lane.0.extract = extractvalue { <1 x i64>, <1 x i64> } %vld2_lane, 0 + %vld2_lane.1.extract = extractvalue { <1 x i64>, <1 x i64> } %vld2_lane, 1 + %vld2_lane1 = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i8(<1 x i64> %vld2_lane.0.extract, <1 x i64> %vld2_lane.1.extract, i64 0, i8* %t1) + %vld2_lane1.0.extract = extractvalue { <1 x i64>, <1 x i64> } %vld2_lane1, 0 + %vld2_lane1.1.extract = extractvalue { <1 x i64>, <1 x i64> } %vld2_lane1, 1 + %t3 = bitcast <2 x i64>* %val1 to i8* + call void @llvm.aarch64.neon.st2.v1i64.p0i8(<1 x i64> %vld2_lane1.0.extract, <1 x i64> %vld2_lane1.1.extract, i8* %t3) + %t4 = load <2 x i64>, <2 x i64>* %val1, align 16 + %vsubhn = sub <2 x i64> <i64 11, i64 0>, %t4 + %vsubhn1 = lshr <2 x i64> %vsubhn, <i64 32, i64 32> + %vsubhn2 = trunc <2 x i64> %vsubhn1 to <2 x i32> + %neg = xor <2 x i32> %vsubhn2, <i32 -1, i32 -1> + %sqadd1 = call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> <i64 -1>, <1 x i64> <i64 1>) + %sqadd2 = call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> %vset_lane603, <1 x i64> %sqadd1) + %sqadd3 = call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> <i64 1>, <1 x i64> %sqadd2) + %shuffle.i = shufflevector <2 x i32> <i32 undef, i32 0>, <2 x i32> %vrsubhn_v2.i1364, <2 x i32> <i32 1, i32 3> + %cmp.i = icmp uge <2 x i32> %shuffle.i, %neg + %sext.i = sext <2 x i1> %cmp.i to <2 x i32> + %vpadal = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %sext.i) + %t5 = sub <1 x i64> %vpadal, %sqadd3 + %vget_lane1 = extractelement <1 x i64> %t5, i32 0 + %cmp2 = icmp eq i64 %vget_lane1, 15 + br i1 %cmp2, label %if.end2, label %if.then2 + +if.then2: ; preds = %if.end + store i1 true, i1* @failed, align 1 + br label %if.end2 + +if.end2: ; preds = %if.then682, %if.end + call void @f2() + %vext = shufflevector <8 x i8> <i8 undef, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <8 x i8> %vtbl1.i, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8> + %t6 = bitcast <8 x i8> %vext to <2 x i32> + call void @f0(<2 x i32> %t6) + ret void +} + +declare void @f0(<2 x i32>) + +declare <8 x i8> @f1() + +declare void @f2() + +declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>) + +declare void @llvm.aarch64.neon.st2lane.v2i64.p0i8(<2 x i64>, <2 x i64>, i64, i8* nocapture) + +declare void @llvm.aarch64.neon.st2lane.v1i64.p0i8(<1 x i64>, <1 x i64>, i64, i8* nocapture) + +declare { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i8(<1 x i64>, <1 x i64>, i64, i8*) + +declare void @llvm.aarch64.neon.st2.v1i64.p0i8(<1 x i64>, <1 x i64>, i8* nocapture) + +declare <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64>, <1 x i64>) + +declare <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32>) + +declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>) + +declare <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32>, <2 x i32>) diff --git a/test/CodeGen/AArch64/machine_cse.ll b/test/CodeGen/AArch64/machine_cse.ll index bc9ab10..032199e 100644 --- a/test/CodeGen/AArch64/machine_cse.ll +++ b/test/CodeGen/AArch64/machine_cse.ll @@ -14,11 +14,11 @@ define void @combine-sign-comparisons-by-cse(i32 *%arg) { ; CHECK: b.le entry: - %a = load i32* @a, align 4 - %b = load i32* @b, align 4 - %c = load i32* @c, align 4 - %d = load i32* @d, align 4 - %e = load i32* @e, align 4 + %a = load i32, i32* @a, align 4 + %b = load i32, i32* @b, align 4 + %c = load i32, i32* @c, align 4 + %d = load i32, i32* @d, align 4 + %e = load i32, i32* @e, align 4 %cmp = icmp slt i32 %a, %e br i1 %cmp, label %land.lhs.true, label %lor.lhs.false diff --git a/test/CodeGen/AArch64/mul_pow2.ll b/test/CodeGen/AArch64/mul_pow2.ll index efc0ec8..b828223 100644 --- a/test/CodeGen/AArch64/mul_pow2.ll +++ b/test/CodeGen/AArch64/mul_pow2.ll @@ -74,8 +74,7 @@ define i32 @ntest2(i32 %x) { define i32 @ntest3(i32 %x) { ; CHECK-LABEL: ntest3 -; CHECK: add {{w[0-9]+}}, w0, w0, lsl #1 -; CHECK: neg w0, {{w[0-9]+}} +; CHECK: sub w0, w0, w0, lsl #2 %mul = mul nsw i32 %x, -3 ret i32 %mul diff --git a/test/CodeGen/AArch64/neon-fpround_f128.ll b/test/CodeGen/AArch64/neon-fpround_f128.ll index a93f3f2..265664e 100644 --- a/test/CodeGen/AArch64/neon-fpround_f128.ll +++ b/test/CodeGen/AArch64/neon-fpround_f128.ll @@ -3,7 +3,7 @@ define <1 x double> @test_fpround_v1f128(<1 x fp128>* %a) { ; CHECK-LABEL: test_fpround_v1f128: ; CHECK: bl __trunctfdf2 - %b = load <1 x fp128>* %a + %b = load <1 x fp128>, <1 x fp128>* %a %c = fptrunc <1 x fp128> %b to <1 x double> ret <1 x double> %c } @@ -12,7 +12,7 @@ define <2 x double> @test_fpround_v2f128(<2 x fp128>* %a) { ; CHECK-LABEL: test_fpround_v2f128: ; CHECK: bl __trunctfdf2 ; CHECK: bl __trunctfdf2 - %b = load <2 x fp128>* %a + %b = load <2 x fp128>, <2 x fp128>* %a %c = fptrunc <2 x fp128> %b to <2 x double> ret <2 x double> %c } diff --git a/test/CodeGen/AArch64/neon-truncStore-extLoad.ll b/test/CodeGen/AArch64/neon-truncStore-extLoad.ll index 1df3719..0d5ebb3 100644 --- a/test/CodeGen/AArch64/neon-truncStore-extLoad.ll +++ b/test/CodeGen/AArch64/neon-truncStore-extLoad.ll @@ -34,7 +34,7 @@ define void @truncStore.v8i16(<8 x i16> %a, <8 x i8>* %result) { define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) { ; CHECK-LABEL: loadSExt.v4i8: ; CHECK: ldrsb - %a = load <4 x i8>* %ref + %a = load <4 x i8>, <4 x i8>* %ref %conv = sext <4 x i8> %a to <4 x i32> ret <4 x i32> %conv } @@ -42,7 +42,7 @@ define <4 x i32> @loadSExt.v4i8(<4 x i8>* %ref) { define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) { ; CHECK-LABEL: loadZExt.v4i8: ; CHECK: ldrb - %a = load <4 x i8>* %ref + %a = load <4 x i8>, <4 x i8>* %ref %conv = zext <4 x i8> %a to <4 x i32> ret <4 x i32> %conv } @@ -50,7 +50,7 @@ define <4 x i32> @loadZExt.v4i8(<4 x i8>* %ref) { define i32 @loadExt.i32(<4 x i8>* %ref) { ; CHECK-LABEL: loadExt.i32: ; CHECK: ldrb - %a = load <4 x i8>* %ref + %a = load <4 x i8>, <4 x i8>* %ref %vecext = extractelement <4 x i8> %a, i32 0 %conv = zext i8 %vecext to i32 ret i32 %conv diff --git a/test/CodeGen/AArch64/nzcv-save.ll b/test/CodeGen/AArch64/nzcv-save.ll index 32baff3..f8f42ec 100644 --- a/test/CodeGen/AArch64/nzcv-save.ll +++ b/test/CodeGen/AArch64/nzcv-save.ll @@ -7,8 +7,8 @@ ; must be saved for later. define void @f(i256* nocapture %a, i256* nocapture %b, i256* nocapture %cc, i256* nocapture %dd) nounwind uwtable noinline ssp { entry: - %c = load i256* %cc - %d = load i256* %dd + %c = load i256, i256* %cc + %d = load i256, i256* %dd %add = add nsw i256 %c, %d store i256 %add, i256* %a, align 8 %or = or i256 %c, 1606938044258990275541962092341162602522202993782792835301376 diff --git a/test/CodeGen/AArch64/paired-load.ll b/test/CodeGen/AArch64/paired-load.ll index 3dddb9e..e6d2d4f 100644 --- a/test/CodeGen/AArch64/paired-load.ll +++ b/test/CodeGen/AArch64/paired-load.ll @@ -6,10 +6,10 @@ target triple = "aarch64-linux-gnu" ; CHECK: ldp ; CHECK: stp define void @f(i64* %p, i64* %q) { - %addr2 = getelementptr i64* %q, i32 1 - %addr = getelementptr i64* %p, i32 1 - %x = load i64* %p - %y = load i64* %addr + %addr2 = getelementptr i64, i64* %q, i32 1 + %addr = getelementptr i64, i64* %p, i32 1 + %x = load i64, i64* %p + %y = load i64, i64* %addr store i64 %x, i64* %q store i64 %y, i64* %addr2 ret void diff --git a/test/CodeGen/AArch64/pic-eh-stubs.ll b/test/CodeGen/AArch64/pic-eh-stubs.ll index 93ee0e6..f761a87 100644 --- a/test/CodeGen/AArch64/pic-eh-stubs.ll +++ b/test/CodeGen/AArch64/pic-eh-stubs.ll @@ -38,7 +38,7 @@ catch: ; preds = %lpad %3 = extractvalue { i8*, i32 } %0, 0 %4 = tail call i8* @__cxa_begin_catch(i8* %3) nounwind %5 = bitcast i8* %4 to i32* - %exn.scalar = load i32* %5, align 4 + %exn.scalar = load i32, i32* %5, align 4 tail call void @__cxa_end_catch() nounwind br label %return diff --git a/test/CodeGen/AArch64/ragreedy-csr.ll b/test/CodeGen/AArch64/ragreedy-csr.ll index 31ff543..94eeba7 100644 --- a/test/CodeGen/AArch64/ragreedy-csr.ll +++ b/test/CodeGen/AArch64/ragreedy-csr.ll @@ -35,31 +35,31 @@ declare i32 @__maskrune(i32, i64) #7 define fastcc i32 @prune_match(%struct.Connector_struct* nocapture readonly %a, %struct.Connector_struct* nocapture readonly %b) #9 { entry: %label56 = bitcast %struct.Connector_struct* %a to i16* - %0 = load i16* %label56, align 2 + %0 = load i16, i16* %label56, align 2 %label157 = bitcast %struct.Connector_struct* %b to i16* - %1 = load i16* %label157, align 2 + %1 = load i16, i16* %label157, align 2 %cmp = icmp eq i16 %0, %1 br i1 %cmp, label %if.end, label %return, !prof !988 if.end: - %priority = getelementptr inbounds %struct.Connector_struct* %a, i64 0, i32 2 - %2 = load i8* %priority, align 1 - %priority5 = getelementptr inbounds %struct.Connector_struct* %b, i64 0, i32 2 - %3 = load i8* %priority5, align 1 - %string = getelementptr inbounds %struct.Connector_struct* %a, i64 0, i32 5 - %4 = load i8** %string, align 8 - %string7 = getelementptr inbounds %struct.Connector_struct* %b, i64 0, i32 5 - %5 = load i8** %string7, align 8 + %priority = getelementptr inbounds %struct.Connector_struct, %struct.Connector_struct* %a, i64 0, i32 2 + %2 = load i8, i8* %priority, align 1 + %priority5 = getelementptr inbounds %struct.Connector_struct, %struct.Connector_struct* %b, i64 0, i32 2 + %3 = load i8, i8* %priority5, align 1 + %string = getelementptr inbounds %struct.Connector_struct, %struct.Connector_struct* %a, i64 0, i32 5 + %4 = load i8*, i8** %string, align 8 + %string7 = getelementptr inbounds %struct.Connector_struct, %struct.Connector_struct* %b, i64 0, i32 5 + %5 = load i8*, i8** %string7, align 8 br label %while.cond while.cond: %lsr.iv27 = phi i64 [ %lsr.iv.next28, %if.end17 ], [ 0, %if.end ] - %scevgep55 = getelementptr i8* %4, i64 %lsr.iv27 - %6 = load i8* %scevgep55, align 1 + %scevgep55 = getelementptr i8, i8* %4, i64 %lsr.iv27 + %6 = load i8, i8* %scevgep55, align 1 %idxprom.i.i = sext i8 %6 to i64 %isascii.i.i224 = icmp sgt i8 %6, -1 br i1 %isascii.i.i224, label %cond.true.i.i, label %cond.false.i.i, !prof !181 cond.true.i.i: - %arrayidx.i.i = getelementptr inbounds %struct._RuneLocale* @_DefaultRuneLocale, i64 0, i32 5, i64 %idxprom.i.i - %7 = load i32* %arrayidx.i.i, align 4 + %arrayidx.i.i = getelementptr inbounds %struct._RuneLocale, %struct._RuneLocale* @_DefaultRuneLocale, i64 0, i32 5, i64 %idxprom.i.i + %7 = load i32, i32* %arrayidx.i.i, align 4 %and.i.i = and i32 %7, 32768 br label %isupper.exit cond.false.i.i: @@ -75,13 +75,13 @@ lor.rhs: %sunkaddr = ptrtoint i8* %5 to i64 %sunkaddr58 = add i64 %sunkaddr, %lsr.iv27 %sunkaddr59 = inttoptr i64 %sunkaddr58 to i8* - %9 = load i8* %sunkaddr59, align 1 + %9 = load i8, i8* %sunkaddr59, align 1 %idxprom.i.i214 = sext i8 %9 to i64 %isascii.i.i213225 = icmp sgt i8 %9, -1 br i1 %isascii.i.i213225, label %cond.true.i.i217, label %cond.false.i.i219, !prof !181 cond.true.i.i217: - %arrayidx.i.i215 = getelementptr inbounds %struct._RuneLocale* @_DefaultRuneLocale, i64 0, i32 5, i64 %idxprom.i.i214 - %10 = load i32* %arrayidx.i.i215, align 4 + %arrayidx.i.i215 = getelementptr inbounds %struct._RuneLocale, %struct._RuneLocale* @_DefaultRuneLocale, i64 0, i32 5, i64 %idxprom.i.i214 + %10 = load i32, i32* %arrayidx.i.i215, align 4 %and.i.i216 = and i32 %10, 32768 br label %isupper.exit223 cond.false.i.i219: @@ -97,11 +97,11 @@ while.body: %sunkaddr60 = ptrtoint i8* %4 to i64 %sunkaddr61 = add i64 %sunkaddr60, %lsr.iv27 %sunkaddr62 = inttoptr i64 %sunkaddr61 to i8* - %12 = load i8* %sunkaddr62, align 1 + %12 = load i8, i8* %sunkaddr62, align 1 %sunkaddr63 = ptrtoint i8* %5 to i64 %sunkaddr64 = add i64 %sunkaddr63, %lsr.iv27 %sunkaddr65 = inttoptr i64 %sunkaddr64 to i8* - %13 = load i8* %sunkaddr65, align 1 + %13 = load i8, i8* %sunkaddr65, align 1 %cmp14 = icmp eq i8 %12, %13 br i1 %cmp14, label %if.end17, label %return, !prof !991 if.end17: @@ -115,13 +115,13 @@ if.then23: %sunkaddr66 = ptrtoint %struct.Connector_struct* %a to i64 %sunkaddr67 = add i64 %sunkaddr66, 16 %sunkaddr68 = inttoptr i64 %sunkaddr67 to i8** - %16 = load i8** %sunkaddr68, align 8 - %17 = load i8* %16, align 1 + %16 = load i8*, i8** %sunkaddr68, align 8 + %17 = load i8, i8* %16, align 1 %cmp26 = icmp eq i8 %17, 83 %sunkaddr69 = ptrtoint i8* %4 to i64 %sunkaddr70 = add i64 %sunkaddr69, %lsr.iv27 %sunkaddr71 = inttoptr i64 %sunkaddr70 to i8* - %18 = load i8* %sunkaddr71, align 1 + %18 = load i8, i8* %sunkaddr71, align 1 br i1 %cmp26, label %land.lhs.true28, label %while.cond59.preheader, !prof !993 land.lhs.true28: switch i8 %18, label %land.rhs.preheader [ @@ -132,24 +132,24 @@ land.lhs.true35: %sunkaddr72 = ptrtoint i8* %5 to i64 %sunkaddr73 = add i64 %sunkaddr72, %lsr.iv27 %sunkaddr74 = inttoptr i64 %sunkaddr73 to i8* - %19 = load i8* %sunkaddr74, align 1 + %19 = load i8, i8* %sunkaddr74, align 1 switch i8 %19, label %land.rhs.preheader [ i8 112, label %land.lhs.true43 ], !prof !995 land.lhs.true43: %20 = ptrtoint i8* %16 to i64 %21 = sub i64 0, %20 - %scevgep52 = getelementptr i8* %4, i64 %21 - %scevgep53 = getelementptr i8* %scevgep52, i64 %lsr.iv27 - %scevgep54 = getelementptr i8* %scevgep53, i64 -1 + %scevgep52 = getelementptr i8, i8* %4, i64 %21 + %scevgep53 = getelementptr i8, i8* %scevgep52, i64 %lsr.iv27 + %scevgep54 = getelementptr i8, i8* %scevgep53, i64 -1 %cmp45 = icmp eq i8* %scevgep54, null br i1 %cmp45, label %return, label %lor.lhs.false47, !prof !996 lor.lhs.false47: %22 = ptrtoint i8* %16 to i64 %23 = sub i64 0, %22 - %scevgep47 = getelementptr i8* %4, i64 %23 - %scevgep48 = getelementptr i8* %scevgep47, i64 %lsr.iv27 - %scevgep49 = getelementptr i8* %scevgep48, i64 -2 + %scevgep47 = getelementptr i8, i8* %4, i64 %23 + %scevgep48 = getelementptr i8, i8* %scevgep47, i64 %lsr.iv27 + %scevgep49 = getelementptr i8, i8* %scevgep48, i64 -2 %cmp50 = icmp eq i8* %scevgep49, null br i1 %cmp50, label %land.lhs.true52, label %while.cond59.preheader, !prof !997 land.lhs.true52: @@ -157,7 +157,7 @@ land.lhs.true52: %sunkaddr76 = add i64 %sunkaddr75, %lsr.iv27 %sunkaddr77 = add i64 %sunkaddr76, -1 %sunkaddr78 = inttoptr i64 %sunkaddr77 to i8* - %24 = load i8* %sunkaddr78, align 1 + %24 = load i8, i8* %sunkaddr78, align 1 %cmp55 = icmp eq i8 %24, 73 %cmp61233 = icmp eq i8 %18, 0 %or.cond265 = or i1 %cmp55, %cmp61233 @@ -166,14 +166,14 @@ while.cond59.preheader: %cmp61233.old = icmp eq i8 %18, 0 br i1 %cmp61233.old, label %return, label %land.rhs.preheader, !prof !999 land.rhs.preheader: - %scevgep33 = getelementptr i8* %5, i64 %lsr.iv27 - %scevgep43 = getelementptr i8* %4, i64 %lsr.iv27 + %scevgep33 = getelementptr i8, i8* %5, i64 %lsr.iv27 + %scevgep43 = getelementptr i8, i8* %4, i64 %lsr.iv27 br label %land.rhs land.rhs: %lsr.iv = phi i64 [ 0, %land.rhs.preheader ], [ %lsr.iv.next, %if.then83 ] %25 = phi i8 [ %27, %if.then83 ], [ %18, %land.rhs.preheader ] - %scevgep34 = getelementptr i8* %scevgep33, i64 %lsr.iv - %26 = load i8* %scevgep34, align 1 + %scevgep34 = getelementptr i8, i8* %scevgep33, i64 %lsr.iv + %26 = load i8, i8* %scevgep34, align 1 %cmp64 = icmp eq i8 %26, 0 br i1 %cmp64, label %return, label %while.body66, !prof !1000 while.body66: @@ -187,9 +187,9 @@ lor.lhs.false74: %or.cond208 = or i1 %cmp77, %cmp81 br i1 %or.cond208, label %return, label %if.then83, !prof !1002 if.then83: - %scevgep44 = getelementptr i8* %scevgep43, i64 %lsr.iv - %scevgep45 = getelementptr i8* %scevgep44, i64 1 - %27 = load i8* %scevgep45, align 1 + %scevgep44 = getelementptr i8, i8* %scevgep43, i64 %lsr.iv + %scevgep45 = getelementptr i8, i8* %scevgep44, i64 1 + %27 = load i8, i8* %scevgep45, align 1 %cmp61 = icmp eq i8 %27, 0 %lsr.iv.next = add i64 %lsr.iv, 1 br i1 %cmp61, label %return, label %land.rhs, !prof !999 @@ -202,18 +202,18 @@ while.cond95.preheader: %sunkaddr79 = ptrtoint i8* %4 to i64 %sunkaddr80 = add i64 %sunkaddr79, %lsr.iv27 %sunkaddr81 = inttoptr i64 %sunkaddr80 to i8* - %28 = load i8* %sunkaddr81, align 1 + %28 = load i8, i8* %sunkaddr81, align 1 %cmp97238 = icmp eq i8 %28, 0 br i1 %cmp97238, label %return, label %land.rhs99.preheader, !prof !1004 land.rhs99.preheader: - %scevgep31 = getelementptr i8* %5, i64 %lsr.iv27 - %scevgep40 = getelementptr i8* %4, i64 %lsr.iv27 + %scevgep31 = getelementptr i8, i8* %5, i64 %lsr.iv27 + %scevgep40 = getelementptr i8, i8* %4, i64 %lsr.iv27 br label %land.rhs99 land.rhs99: %lsr.iv17 = phi i64 [ 0, %land.rhs99.preheader ], [ %lsr.iv.next18, %if.then117 ] %29 = phi i8 [ %31, %if.then117 ], [ %28, %land.rhs99.preheader ] - %scevgep32 = getelementptr i8* %scevgep31, i64 %lsr.iv17 - %30 = load i8* %scevgep32, align 1 + %scevgep32 = getelementptr i8, i8* %scevgep31, i64 %lsr.iv17 + %30 = load i8, i8* %scevgep32, align 1 %cmp101 = icmp eq i8 %30, 0 br i1 %cmp101, label %return, label %while.body104, !prof !1005 while.body104: @@ -224,9 +224,9 @@ while.body104: %or.cond210 = or i1 %or.cond209, %cmp115 br i1 %or.cond210, label %if.then117, label %return, !prof !1006 if.then117: - %scevgep41 = getelementptr i8* %scevgep40, i64 %lsr.iv17 - %scevgep42 = getelementptr i8* %scevgep41, i64 1 - %31 = load i8* %scevgep42, align 1 + %scevgep41 = getelementptr i8, i8* %scevgep40, i64 %lsr.iv17 + %scevgep42 = getelementptr i8, i8* %scevgep41, i64 1 + %31 = load i8, i8* %scevgep42, align 1 %cmp97 = icmp eq i8 %31, 0 %lsr.iv.next18 = add i64 %lsr.iv17, 1 br i1 %cmp97, label %return, label %land.rhs99, !prof !1004 @@ -239,18 +239,18 @@ while.cond130.preheader: %sunkaddr82 = ptrtoint i8* %4 to i64 %sunkaddr83 = add i64 %sunkaddr82, %lsr.iv27 %sunkaddr84 = inttoptr i64 %sunkaddr83 to i8* - %32 = load i8* %sunkaddr84, align 1 + %32 = load i8, i8* %sunkaddr84, align 1 %cmp132244 = icmp eq i8 %32, 0 br i1 %cmp132244, label %return, label %land.rhs134.preheader, !prof !1008 land.rhs134.preheader: - %scevgep29 = getelementptr i8* %5, i64 %lsr.iv27 - %scevgep37 = getelementptr i8* %4, i64 %lsr.iv27 + %scevgep29 = getelementptr i8, i8* %5, i64 %lsr.iv27 + %scevgep37 = getelementptr i8, i8* %4, i64 %lsr.iv27 br label %land.rhs134 land.rhs134: %lsr.iv22 = phi i64 [ 0, %land.rhs134.preheader ], [ %lsr.iv.next23, %if.then152 ] %33 = phi i8 [ %35, %if.then152 ], [ %32, %land.rhs134.preheader ] - %scevgep30 = getelementptr i8* %scevgep29, i64 %lsr.iv22 - %34 = load i8* %scevgep30, align 1 + %scevgep30 = getelementptr i8, i8* %scevgep29, i64 %lsr.iv22 + %34 = load i8, i8* %scevgep30, align 1 %cmp136 = icmp eq i8 %34, 0 br i1 %cmp136, label %return, label %while.body139, !prof !1009 while.body139: @@ -261,9 +261,9 @@ while.body139: %or.cond212 = or i1 %or.cond211, %cmp150 br i1 %or.cond212, label %if.then152, label %return, !prof !1010 if.then152: - %scevgep38 = getelementptr i8* %scevgep37, i64 %lsr.iv22 - %scevgep39 = getelementptr i8* %scevgep38, i64 1 - %35 = load i8* %scevgep39, align 1 + %scevgep38 = getelementptr i8, i8* %scevgep37, i64 %lsr.iv22 + %scevgep39 = getelementptr i8, i8* %scevgep38, i64 1 + %35 = load i8, i8* %scevgep39, align 1 %cmp132 = icmp eq i8 %35, 0 %lsr.iv.next23 = add i64 %lsr.iv22, 1 br i1 %cmp132, label %return, label %land.rhs134, !prof !1008 diff --git a/test/CodeGen/AArch64/regress-tail-livereg.ll b/test/CodeGen/AArch64/regress-tail-livereg.ll index 03c3f33..965aa0d 100644 --- a/test/CodeGen/AArch64/regress-tail-livereg.ll +++ b/test/CodeGen/AArch64/regress-tail-livereg.ll @@ -5,7 +5,7 @@ declare void @bar() define void @foo() { ; CHECK-LABEL: foo: - %func = load void()** @var + %func = load void()*, void()** @var ; Calling a function encourages @foo to use a callee-saved register, ; which makes it a natural choice for the tail call itself. But we don't diff --git a/test/CodeGen/AArch64/regress-tblgen-chains.ll b/test/CodeGen/AArch64/regress-tblgen-chains.ll index 477d996..0d301bb 100644 --- a/test/CodeGen/AArch64/regress-tblgen-chains.ll +++ b/test/CodeGen/AArch64/regress-tblgen-chains.ll @@ -19,7 +19,7 @@ define i64 @test_chains() { call void @bar(i8* %locvar) ; CHECK: bl {{_?bar}} - %inc.1 = load i8* %locvar + %inc.1 = load i8, i8* %locvar %inc.2 = zext i8 %inc.1 to i64 %inc.3 = add i64 %inc.2, 1 %inc.4 = trunc i64 %inc.3 to i8 @@ -30,7 +30,7 @@ define i64 @test_chains() { ; CHECK: sturb {{w[0-9]+}}, [x29, [[LOCADDR]]] ; CHECK: ldurb {{w[0-9]+}}, [x29, [[LOCADDR]]] - %ret.1 = load i8* %locvar + %ret.1 = load i8, i8* %locvar %ret.2 = zext i8 %ret.1 to i64 ret i64 %ret.2 ; CHECK: ret diff --git a/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll b/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll index c3167e4..66a5ed6 100644 --- a/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll +++ b/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll @@ -7,15 +7,15 @@ define void @test_w29_reserved() { ; CHECK-LABEL: test_w29_reserved: ; CHECK: add x29, sp, #{{[0-9]+}} - %val1 = load volatile i32* @var - %val2 = load volatile i32* @var - %val3 = load volatile i32* @var - %val4 = load volatile i32* @var - %val5 = load volatile i32* @var - %val6 = load volatile i32* @var - %val7 = load volatile i32* @var - %val8 = load volatile i32* @var - %val9 = load volatile i32* @var + %val1 = load volatile i32, i32* @var + %val2 = load volatile i32, i32* @var + %val3 = load volatile i32, i32* @var + %val4 = load volatile i32, i32* @var + %val5 = load volatile i32, i32* @var + %val6 = load volatile i32, i32* @var + %val7 = load volatile i32, i32* @var + %val8 = load volatile i32, i32* @var + %val9 = load volatile i32, i32* @var ; CHECK-NOT: ldr w29, diff --git a/test/CodeGen/AArch64/remat-float0.ll b/test/CodeGen/AArch64/remat-float0.ll new file mode 100644 index 0000000..29af781 --- /dev/null +++ b/test/CodeGen/AArch64/remat-float0.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -verify-machineinstrs | FileCheck %s + +; Check that float 0 gets rematerialized with an fmov of zero reg instead +; of spilled/filled. + +declare void @bar(float) + +define void @foo() { +; CHECK-LABEL: foo: +; CHECK: fmov s0, wzr +; CHECK: bl bar +; CHECK: fmov s0, wzr +; CHECK: bl bar + call void @bar(float 0.000000e+00) + call void asm sideeffect "", "~{s0},~{s1},~{s2},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9},~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19},~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29},~{s30},~{s31}"() + call void @bar(float 0.000000e+00) + ret void +} diff --git a/test/CodeGen/AArch64/rm_redundant_cmp.ll b/test/CodeGen/AArch64/rm_redundant_cmp.ll index 36dc118..f66af7f 100644 --- a/test/CodeGen/AArch64/rm_redundant_cmp.ll +++ b/test/CodeGen/AArch64/rm_redundant_cmp.ll @@ -15,13 +15,13 @@ define void @test_i16_2cmp_signed_1() { ; CHECK-NOT: cmp ; CHECK: b.ne entry: - %0 = load i16* getelementptr inbounds (%struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 1), align 2 - %1 = load i16* getelementptr inbounds (%struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 2), align 2 + %0 = load i16, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 1), align 2 + %1 = load i16, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 2), align 2 %cmp = icmp sgt i16 %0, %1 br i1 %cmp, label %if.then, label %if.else if.then: ; preds = %entry - store i16 %0, i16* getelementptr inbounds (%struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 0), align 2 + store i16 %0, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 0), align 2 br label %if.end8 if.else: ; preds = %entry @@ -29,7 +29,7 @@ if.else: ; preds = %entry br i1 %cmp5, label %if.then7, label %if.end8 if.then7: ; preds = %if.else - store i16 %0, i16* getelementptr inbounds (%struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 0), align 2 + store i16 %0, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 0), align 2 br label %if.end8 if.end8: ; preds = %if.else, %if.then7, %if.then @@ -43,13 +43,13 @@ define void @test_i16_2cmp_signed_2() { ; CHECK-NOT: cmp ; CHECK: b.ge entry: - %0 = load i16* getelementptr inbounds (%struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 1), align 2 - %1 = load i16* getelementptr inbounds (%struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 2), align 2 + %0 = load i16, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 1), align 2 + %1 = load i16, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 2), align 2 %cmp = icmp sgt i16 %0, %1 br i1 %cmp, label %if.then, label %if.else if.then: ; preds = %entry - store i16 %0, i16* getelementptr inbounds (%struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 0), align 2 + store i16 %0, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 0), align 2 br label %if.end8 if.else: ; preds = %entry @@ -57,7 +57,7 @@ if.else: ; preds = %entry br i1 %cmp5, label %if.then7, label %if.end8 if.then7: ; preds = %if.else - store i16 %1, i16* getelementptr inbounds (%struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 0), align 2 + store i16 %1, i16* getelementptr inbounds (%struct.s_signed_i16, %struct.s_signed_i16* @cost_s_i8_i16, i64 0, i32 0), align 2 br label %if.end8 if.end8: ; preds = %if.else, %if.then7, %if.then @@ -71,13 +71,13 @@ define void @test_i16_2cmp_unsigned_1() { ; CHECK-NOT: cmp ; CHECK: b.ne entry: - %0 = load i16* getelementptr inbounds (%struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 1), align 2 - %1 = load i16* getelementptr inbounds (%struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 2), align 2 + %0 = load i16, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 1), align 2 + %1 = load i16, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 2), align 2 %cmp = icmp ugt i16 %0, %1 br i1 %cmp, label %if.then, label %if.else if.then: ; preds = %entry - store i16 %0, i16* getelementptr inbounds (%struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 0), align 2 + store i16 %0, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 0), align 2 br label %if.end8 if.else: ; preds = %entry @@ -85,7 +85,7 @@ if.else: ; preds = %entry br i1 %cmp5, label %if.then7, label %if.end8 if.then7: ; preds = %if.else - store i16 %0, i16* getelementptr inbounds (%struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 0), align 2 + store i16 %0, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 0), align 2 br label %if.end8 if.end8: ; preds = %if.else, %if.then7, %if.then @@ -99,13 +99,13 @@ define void @test_i16_2cmp_unsigned_2() { ; CHECK-NOT: cmp ; CHECK: b.hs entry: - %0 = load i16* getelementptr inbounds (%struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 1), align 2 - %1 = load i16* getelementptr inbounds (%struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 2), align 2 + %0 = load i16, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 1), align 2 + %1 = load i16, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 2), align 2 %cmp = icmp ugt i16 %0, %1 br i1 %cmp, label %if.then, label %if.else if.then: ; preds = %entry - store i16 %0, i16* getelementptr inbounds (%struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 0), align 2 + store i16 %0, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 0), align 2 br label %if.end8 if.else: ; preds = %entry @@ -113,7 +113,7 @@ if.else: ; preds = %entry br i1 %cmp5, label %if.then7, label %if.end8 if.then7: ; preds = %if.else - store i16 %1, i16* getelementptr inbounds (%struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 0), align 2 + store i16 %1, i16* getelementptr inbounds (%struct.s_unsigned_i16, %struct.s_unsigned_i16* @cost_u_i16, i64 0, i32 0), align 2 br label %if.end8 if.end8: ; preds = %if.else, %if.then7, %if.then @@ -136,13 +136,13 @@ define void @test_i8_2cmp_signed_1() { ; CHECK-NOT: cmp ; CHECK: b.ne entry: - %0 = load i8* getelementptr inbounds (%struct.s_signed_i8* @cost_s, i64 0, i32 1), align 2 - %1 = load i8* getelementptr inbounds (%struct.s_signed_i8* @cost_s, i64 0, i32 2), align 2 + %0 = load i8, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 1), align 2 + %1 = load i8, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 2), align 2 %cmp = icmp sgt i8 %0, %1 br i1 %cmp, label %if.then, label %if.else if.then: ; preds = %entry - store i8 %0, i8* getelementptr inbounds (%struct.s_signed_i8* @cost_s, i64 0, i32 0), align 2 + store i8 %0, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 0), align 2 br label %if.end8 if.else: ; preds = %entry @@ -150,7 +150,7 @@ if.else: ; preds = %entry br i1 %cmp5, label %if.then7, label %if.end8 if.then7: ; preds = %if.else - store i8 %0, i8* getelementptr inbounds (%struct.s_signed_i8* @cost_s, i64 0, i32 0), align 2 + store i8 %0, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 0), align 2 br label %if.end8 if.end8: ; preds = %if.else, %if.then7, %if.then @@ -164,13 +164,13 @@ define void @test_i8_2cmp_signed_2() { ; CHECK-NOT: cmp ; CHECK: b.ge entry: - %0 = load i8* getelementptr inbounds (%struct.s_signed_i8* @cost_s, i64 0, i32 1), align 2 - %1 = load i8* getelementptr inbounds (%struct.s_signed_i8* @cost_s, i64 0, i32 2), align 2 + %0 = load i8, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 1), align 2 + %1 = load i8, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 2), align 2 %cmp = icmp sgt i8 %0, %1 br i1 %cmp, label %if.then, label %if.else if.then: ; preds = %entry - store i8 %0, i8* getelementptr inbounds (%struct.s_signed_i8* @cost_s, i64 0, i32 0), align 2 + store i8 %0, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 0), align 2 br label %if.end8 if.else: ; preds = %entry @@ -178,7 +178,7 @@ if.else: ; preds = %entry br i1 %cmp5, label %if.then7, label %if.end8 if.then7: ; preds = %if.else - store i8 %1, i8* getelementptr inbounds (%struct.s_signed_i8* @cost_s, i64 0, i32 0), align 2 + store i8 %1, i8* getelementptr inbounds (%struct.s_signed_i8, %struct.s_signed_i8* @cost_s, i64 0, i32 0), align 2 br label %if.end8 if.end8: ; preds = %if.else, %if.then7, %if.then @@ -192,13 +192,13 @@ define void @test_i8_2cmp_unsigned_1() { ; CHECK-NOT: cmp ; CHECK: b.ne entry: - %0 = load i8* getelementptr inbounds (%struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 1), align 2 - %1 = load i8* getelementptr inbounds (%struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 2), align 2 + %0 = load i8, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 1), align 2 + %1 = load i8, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 2), align 2 %cmp = icmp ugt i8 %0, %1 br i1 %cmp, label %if.then, label %if.else if.then: ; preds = %entry - store i8 %0, i8* getelementptr inbounds (%struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 0), align 2 + store i8 %0, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 0), align 2 br label %if.end8 if.else: ; preds = %entry @@ -206,7 +206,7 @@ if.else: ; preds = %entry br i1 %cmp5, label %if.then7, label %if.end8 if.then7: ; preds = %if.else - store i8 %0, i8* getelementptr inbounds (%struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 0), align 2 + store i8 %0, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 0), align 2 br label %if.end8 if.end8: ; preds = %if.else, %if.then7, %if.then @@ -220,13 +220,13 @@ define void @test_i8_2cmp_unsigned_2() { ; CHECK-NOT: cmp ; CHECK: b.hs entry: - %0 = load i8* getelementptr inbounds (%struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 1), align 2 - %1 = load i8* getelementptr inbounds (%struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 2), align 2 + %0 = load i8, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 1), align 2 + %1 = load i8, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 2), align 2 %cmp = icmp ugt i8 %0, %1 br i1 %cmp, label %if.then, label %if.else if.then: ; preds = %entry - store i8 %0, i8* getelementptr inbounds (%struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 0), align 2 + store i8 %0, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 0), align 2 br label %if.end8 if.else: ; preds = %entry @@ -234,7 +234,7 @@ if.else: ; preds = %entry br i1 %cmp5, label %if.then7, label %if.end8 if.then7: ; preds = %if.else - store i8 %1, i8* getelementptr inbounds (%struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 0), align 2 + store i8 %1, i8* getelementptr inbounds (%struct.s_unsigned_i8, %struct.s_unsigned_i8* @cost_u_i8, i64 0, i32 0), align 2 br label %if.end8 if.end8: ; preds = %if.else, %if.then7, %if.then diff --git a/test/CodeGen/AArch64/sibling-call.ll b/test/CodeGen/AArch64/sibling-call.ll index 34e3bb4..34d45d8 100644 --- a/test/CodeGen/AArch64/sibling-call.ll +++ b/test/CodeGen/AArch64/sibling-call.ll @@ -88,7 +88,7 @@ define void @indirect_tail() { ; CHECK-LABEL: indirect_tail: ; CHECK-NOT: sub sp, sp - %fptr = load void(i32)** @func + %fptr = load void(i32)*, void(i32)** @func tail call void %fptr(i32 42) ret void ; CHECK: ldr [[FPTR:x[1-9]+]], [{{x[0-9]+}}, {{#?}}:lo12:func] diff --git a/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll b/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll index bedbf5f..eb4937e 100644 --- a/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll +++ b/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll @@ -15,7 +15,7 @@ define i32 @test_stack_guard_remat2() { entry: %StackGuardSlot = alloca i8* - %StackGuard = load i8** bitcast (i64** @__stack_chk_guard to i8**) + %StackGuard = load i8*, i8** bitcast (i64** @__stack_chk_guard to i8**) call void @llvm.stackprotector(i8* %StackGuard, i8** %StackGuardSlot) %container = alloca [32 x i8], align 1 call void @llvm.stackprotectorcheck(i8** bitcast (i64** @__stack_chk_guard to i8**)) diff --git a/test/CodeGen/AArch64/stack_guard_remat.ll b/test/CodeGen/AArch64/stack_guard_remat.ll index cee7266..d6bae62 100644 --- a/test/CodeGen/AArch64/stack_guard_remat.ll +++ b/test/CodeGen/AArch64/stack_guard_remat.ll @@ -30,7 +30,7 @@ entry: %a1 = alloca [256 x i32], align 4 %0 = bitcast [256 x i32]* %a1 to i8* call void @llvm.lifetime.start(i64 1024, i8* %0) - %arraydecay = getelementptr inbounds [256 x i32]* %a1, i64 0, i64 0 + %arraydecay = getelementptr inbounds [256 x i32], [256 x i32]* %a1, i64 0, i64 0 call void @foo3(i32* %arraydecay) call void asm sideeffect "foo2", "~{w0},~{w1},~{w2},~{w3},~{w4},~{w5},~{w6},~{w7},~{w8},~{w9},~{w10},~{w11},~{w12},~{w13},~{w14},~{w15},~{w16},~{w17},~{w18},~{w19},~{w20},~{w21},~{w22},~{w23},~{w24},~{w25},~{w26},~{w27},~{w28},~{w29},~{w30}"() call void @llvm.lifetime.end(i64 1024, i8* %0) diff --git a/test/CodeGen/AArch64/tbz-tbnz.ll b/test/CodeGen/AArch64/tbz-tbnz.ll index c77043c..8863f70 100644 --- a/test/CodeGen/AArch64/tbz-tbnz.ll +++ b/test/CodeGen/AArch64/tbz-tbnz.ll @@ -211,7 +211,7 @@ define void @test11(i64 %val1, i64* %ptr) { ; CHECK-NOT: cmp ; CHECK: tbz [[CMP]], #63 - %val = load i64* %ptr + %val = load i64, i64* %ptr %tst = icmp slt i64 %val, 0 br i1 %tst, label %if.then, label %if.end diff --git a/test/CodeGen/AArch64/tst-br.ll b/test/CodeGen/AArch64/tst-br.ll index 5dc7b5d..345c4d9 100644 --- a/test/CodeGen/AArch64/tst-br.ll +++ b/test/CodeGen/AArch64/tst-br.ll @@ -9,8 +9,8 @@ define i32 @test_tbz() { ; CHECK-LABEL: test_tbz: - %val = load i32* @var32 - %val64 = load i64* @var64 + %val = load i32, i32* @var32 + %val64 = load i64, i64* @var64 %tbit0 = and i32 %val, 32768 %tst0 = icmp ne i32 %tbit0, 0 diff --git a/test/CodeGen/AArch64/zero-reg.ll b/test/CodeGen/AArch64/zero-reg.ll index bc112ab..62b2ea3 100644 --- a/test/CodeGen/AArch64/zero-reg.ll +++ b/test/CodeGen/AArch64/zero-reg.ll @@ -21,7 +21,7 @@ define void @test_sp(i32 %val) { ; Important correctness point here is that LLVM doesn't try to use xzr ; as an addressing register: "str w0, [xzr]" is not a valid A64 ; instruction (0b11111 in the Rn field would mean "sp"). - %addr = getelementptr i32* null, i64 0 + %addr = getelementptr i32, i32* null, i64 0 store i32 %val, i32* %addr ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+|sp}}] |