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| author | Stephen Hines <srhines@google.com> | 2014-12-01 14:51:49 -0800 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-12-02 16:08:10 -0800 |
| commit | 37ed9c199ca639565f6ce88105f9e39e898d82d0 (patch) | |
| tree | 8fb36d3910e3ee4c4e1b7422f4f017108efc52f5 /test/MC/Mips | |
| parent | d2327b22152ced7bc46dc629fc908959e8a52d03 (diff) | |
| download | external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.zip external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.gz external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.bz2 | |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
Diffstat (limited to 'test/MC/Mips')
102 files changed, 2227 insertions, 634 deletions
diff --git a/test/MC/Mips/cpload-bad.s b/test/MC/Mips/cpload-bad.s index 7d186f6..803610a 100644 --- a/test/MC/Mips/cpload-bad.s +++ b/test/MC/Mips/cpload-bad.s @@ -3,13 +3,25 @@ .text .option pic2 + .set noreorder + .set mips16 + .cpload $25 +# ASM: :[[@LINE-1]]:17: error: .cpload is not supported in Mips16 mode + + .set nomips16 .set reorder .cpload $25 -# ASM: :[[@LINE-1]]:9: warning: .cpload in reorder section +# ASM: :[[@LINE-1]]:9: warning: .cpload should be inside a noreorder section + .set noreorder .cpload $32 # ASM: :[[@LINE-1]]:17: error: invalid register + .cpload $foo # ASM: :[[@LINE-1]]:17: error: expected register containing function address + .cpload bar # ASM: :[[@LINE-1]]:17: error: expected register containing function address + + .cpload $25 foobar +# ASM: :[[@LINE-1]]:21: error: unexpected token, expected end of statement diff --git a/test/MC/Mips/cpload.s b/test/MC/Mips/cpload.s index bc5e797..46b3ee4 100644 --- a/test/MC/Mips/cpload.s +++ b/test/MC/Mips/cpload.s @@ -1,12 +1,16 @@ # RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ASM # -# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -filetype=obj -o -| \ -# RUN: llvm-objdump -d -r -arch=mips - | \ -# RUN: FileCheck %s -check-prefix=OBJ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+o32 -filetype=obj -o -| \ +# RUN: llvm-objdump -d -r -arch=mips - | \ +# RUN: FileCheck %s -check-prefix=OBJ-O32 -# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -filetype=obj -o -| \ -# RUN: llvm-objdump -d -r -arch=mips - | \ -# RUN: FileCheck %s -check-prefix=OBJ64 +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=-n64,+n32 -filetype=obj -o -| \ +# RUN: llvm-objdump -d -r -arch=mips - | \ +# RUN: FileCheck %s -check-prefix=OBJ-N32 + +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+n64 -filetype=obj -o -| \ +# RUN: llvm-objdump -d -r -arch=mips - | \ +# RUN: FileCheck %s -check-prefix=OBJ-N64 # ASM: .text # ASM: .option pic2 @@ -14,17 +18,22 @@ # ASM: .cpload $25 # ASM: .set reorder -# OBJ: .text -# OBJ: lui $gp, 0 -# OBJ: R_MIPS_HI16 _gp_disp -# OBJ: addiu $gp, $gp, 0 -# OBJ: R_MIPS_LO16 _gp_disp -# OBJ: addu $gp, $gp, $25 +# OBJ-O32: .text +# OBJ-O32: lui $gp, 0 +# OBJ-O32: R_MIPS_HI16 _gp_disp +# OBJ-O32: addiu $gp, $gp, 0 +# OBJ-O32: R_MIPS_LO16 _gp_disp +# OBJ-O32: addu $gp, $gp, $25 + +# OBJ-N32-NOT: .text +# OBJ-N32-NOT: lui $gp, 0 +# OBJ-N32-NOT: addiu $gp, $gp, 0 +# OBJ-N32-NOT: addu $gp, $gp, $25 -# OBJ64: .text -# OBJ64-NOT: lui $gp, 0 -# OBJ64-NOT: addiu $gp, $gp, 0 -# OBJ64-NOT: addu $gp, $gp, $25 +# OBJ-N64-NOT: .text +# OBJ-N64-NOT: lui $gp, 0 +# OBJ-N64-NOT: addiu $gp, $gp, 0 +# OBJ-N64-NOT: addu $gp, $gp, $25 .text .option pic2 diff --git a/test/MC/Mips/elf-objdump.s b/test/MC/Mips/elf-objdump.s deleted file mode 100644 index 6a5c2a5..0000000 --- a/test/MC/Mips/elf-objdump.s +++ /dev/null @@ -1,11 +0,0 @@ -// 32 bit big endian -// RUN: llvm-mc -filetype=obj -triple mips-unknown-linux %s -o - | llvm-objdump -d -triple mips-unknown-linux - | FileCheck %s -// 32 bit little endian -// RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux %s -o - | llvm-objdump -d -triple mips-unknown-linux - | FileCheck %s -// 64 bit big endian -// RUN: llvm-mc -filetype=obj -arch=mips64 -triple mips64-unknown-linux %s -o - | llvm-objdump -d -triple mips-unknown-linux - | FileCheck %s -// 64 bit little endian -// RUN: llvm-mc -filetype=obj -arch=mips64el -triple mips64el-unknown-linux %s -o - | llvm-objdump -d -triple mips-unknown-linux - | FileCheck %s - -// We just want to see if llvm-objdump works at all. -// CHECK: .text diff --git a/test/MC/Mips/elf_eflags.s b/test/MC/Mips/elf_eflags.s index 36f4f9e..1f28ee0 100644 --- a/test/MC/Mips/elf_eflags.s +++ b/test/MC/Mips/elf_eflags.s @@ -1,118 +1,119 @@ -# These *MUST* match the output of gas compiled with the same triple and +# These *MUST* match the output of 'gcc -c' compiled with the same triple and # corresponding options (-mcpu=mips32 -> -mips32 for example). # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r6 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R6 %s -# MIPSEL-MIPS64R6: Flags [ (0xA0001500) +# MIPSEL-MIPS64R6: Flags [ (0xA0000406) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r6 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R6-NAN2008 %s -# MIPSEL-MIPS64R6-NAN2008: Flags [ (0xA0001500) +# MIPSEL-MIPS64R6-NAN2008: Flags [ (0xA0000406) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2 %s -# MIPSEL-MIPS64R2: Flags [ (0x80001100) +# MIPSEL-MIPS64R2: Flags [ (0x80000006) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2-NAN2008 %s -# MIPSEL-MIPS64R2-NAN2008: Flags [ (0x80001500) +# MIPSEL-MIPS64R2-NAN2008: Flags [ (0x80000406) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64 %s -# MIPSEL-MIPS64: Flags [ (0x60001100) +# MIPSEL-MIPS64: Flags [ (0x60000006) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64-NAN2008 %s -# MIPSEL-MIPS64-NAN2008: Flags [ (0x60001500) +# MIPSEL-MIPS64-NAN2008: Flags [ (0x60000406) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r6 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R6 %s -# MIPSEL-MIPS32R6: Flags [ (0x90001400) +# MIPSEL-MIPS32R6: Flags [ (0x90001404) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r6 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R6-NAN2008 %s -# MIPSEL-MIPS32R6-NAN2008: Flags [ (0x90001400) +# MIPSEL-MIPS32R6-NAN2008: Flags [ (0x90001404) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2 %s -# MIPSEL-MIPS32R2: Flags [ (0x70001000) +# MIPSEL-MIPS32R2: Flags [ (0x70001004) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2-NAN2008 %s -# MIPSEL-MIPS32R2-NAN2008: Flags [ (0x70001400) +# MIPSEL-MIPS32R2-NAN2008: Flags [ (0x70001404) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32 %s -# MIPSEL-MIPS32: Flags [ (0x50001000) +# MIPSEL-MIPS32: Flags [ (0x50001004) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32-NAN2008 %s -# MIPSEL-MIPS32-NAN2008: Flags [ (0x50001400) +# MIPSEL-MIPS32-NAN2008: Flags [ (0x50001404) +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 -mattr=-n64,n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32 %s # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32 %s -# MIPS64EL-MIPS64R2-N32: Flags [ (0x80000020) +# MIPS64EL-MIPS64R2-N32: Flags [ (0x80000024) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,n32,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32-NAN2008 %s -# MIPS64EL-MIPS64R2-N32-NAN2008: Flags [ (0x80000420) +# MIPS64EL-MIPS64R2-N32-NAN2008: Flags [ (0x80000424) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -mattr=-n64,n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N32 %s -# MIPS64EL-MIPS64-N32: Flags [ (0x60000020) +# MIPS64EL-MIPS64-N32: Flags [ (0x60000024) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -mattr=-n64,n32,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N32-NAN2008 %s -# MIPS64EL-MIPS64-N32-NAN2008: Flags [ (0x60000420) +# MIPS64EL-MIPS64-N32-NAN2008: Flags [ (0x60000424) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=n64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N64 %s -# MIPS64EL-MIPS64R2-N64: Flags [ (0x80000000) +# MIPS64EL-MIPS64R2-N64: Flags [ (0x80000006) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=n64,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N64-NAN2008 %s -# MIPS64EL-MIPS64R2-N64-NAN2008: Flags [ (0x80000400) +# MIPS64EL-MIPS64R2-N64-NAN2008: Flags [ (0x80000406) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=n64 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N64 %s -# MIPS64EL-MIPS64-N64: Flags [ (0x60000000) +# MIPS64EL-MIPS64-N64: Flags [ (0x60000006) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=n64,+nan2008 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N64-NAN2008 %s -# MIPS64EL-MIPS64-N64-NAN2008: Flags [ (0x60000400) +# MIPS64EL-MIPS64-N64-NAN2008: Flags [ (0x60000406) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,o32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-O32 %s -# MIPS64EL-MIPS64R2-O32: Flags [ (0x80001100) +# MIPS64EL-MIPS64R2-O32: Flags [ (0x80001104) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,o32,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-O32-NAN2008 %s -# MIPS64EL-MIPS64R2-O32-NAN2008: Flags [ (0x80001500) +# MIPS64EL-MIPS64R2-O32-NAN2008: Flags [ (0x80001504) # RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips5 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS5 %s -# MIPS5: Flags [ (0x40000000) +# MIPS5: Flags [ (0x40000006) # RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips5 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS5-NAN2008 %s -# MIPS5-NAN2008: Flags [ (0x40000400) +# MIPS5-NAN2008: Flags [ (0x40000406) # RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips4 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS4 %s -# MIPS4: Flags [ (0x30000000) +# MIPS4: Flags [ (0x30000006) # RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips4 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS4-NAN2008 %s -# MIPS4-NAN2008: Flags [ (0x30000400) +# MIPS4-NAN2008: Flags [ (0x30000406) # RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips3 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS3 %s -# MIPS3: Flags [ (0x20000000) +# MIPS3: Flags [ (0x20000006) # RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips3 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS3-NAN2008 %s -# MIPS3-NAN2008: Flags [ (0x20000400) +# MIPS3-NAN2008: Flags [ (0x20000406) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS2 %s -# MIPSEL-MIPS2: Flags [ (0x10001000) +# MIPSEL-MIPS2: Flags [ (0x10001004) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips2 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS2-NAN2008 %s -# MIPSEL-MIPS2-NAN2008: Flags [ (0x10001400) +# MIPSEL-MIPS2-NAN2008: Flags [ (0x10001404) # RUN: llvm-mc -filetype=obj -triple mips-unknown-linux -mcpu=mips1 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS1 %s -# MIPS1: Flags [ (0x1000) +# MIPS1: Flags [ (0x1004) # RUN: llvm-mc -filetype=obj -triple mips-unknown-linux -mcpu=mips1 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS1-NAN2008 %s -# MIPS1-NAN2008: Flags [ (0x1400) +# MIPS1-NAN2008: Flags [ (0x1404) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=-n64,o32 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-O32 %s -# MIPS64EL-MIPS64-O32: Flags [ (0x60001100) +# MIPS64EL-MIPS64-O32: Flags [ (0x60001104) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=-n64,o32,+nan2008 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-O32-NAN2008 %s -# MIPS64EL-MIPS64-O32-NAN2008: Flags [ (0x60001500) +# MIPS64EL-MIPS64-O32-NAN2008: Flags [ (0x60001504) # Default ABI for MIPS64 is N64 as opposed to GCC/GAS (N32) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2 %s -# MIPS64EL-MIPS64R2: Flags [ (0x80000000) +# MIPS64EL-MIPS64R2: Flags [ (0x80000006) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-NAN2008 %s -# MIPS64EL-MIPS64R2-NAN2008: Flags [ (0x80000400) +# MIPS64EL-MIPS64R2-NAN2008: Flags [ (0x80000406) # Default ABI for MIPS64 is N64 as opposed to GCC/GAS (N32) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64 %s -# MIPS64EL-MIPS64: Flags [ (0x60000000) +# MIPS64EL-MIPS64: Flags [ (0x60000006) # RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-NAN2008 %s -# MIPS64EL-MIPS64-NAN2008: Flags [ (0x60000400) +# MIPS64EL-MIPS64-NAN2008: Flags [ (0x60000406) diff --git a/test/MC/Mips/elf_eflags_abicalls.s b/test/MC/Mips/elf_eflags_abicalls.s index 5f39630..9e9c013 100644 --- a/test/MC/Mips/elf_eflags_abicalls.s +++ b/test/MC/Mips/elf_eflags_abicalls.s @@ -1,6 +1,6 @@ # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| llvm-readobj -h | FileCheck %s -# This *MUST* match the output of gas compiled with the same triple. +# This *MUST* match the output of 'gcc -c' compiled with the same triple. # CHECK: Flags [ (0x50001006) .abicalls diff --git a/test/MC/Mips/elf_eflags_micromips.s b/test/MC/Mips/elf_eflags_micromips.s index 14bbcad..9b7de12 100644 --- a/test/MC/Mips/elf_eflags_micromips.s +++ b/test/MC/Mips/elf_eflags_micromips.s @@ -1,7 +1,7 @@ # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| llvm-readobj -h | FileCheck %s -# This *MUST* match the output of gas compiled with the same triple. -# CHECK: Flags [ (0x52001000) +# This *MUST* match the output of 'gcc -c' compiled with the same triple. +# CHECK: Flags [ (0x52001004) .set micromips f: diff --git a/test/MC/Mips/elf_eflags_mips16.s b/test/MC/Mips/elf_eflags_mips16.s index deac3d4..5143d36 100644 --- a/test/MC/Mips/elf_eflags_mips16.s +++ b/test/MC/Mips/elf_eflags_mips16.s @@ -1,7 +1,7 @@ # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| llvm-readobj -h | FileCheck %s -# This *MUST* match the output of gas compiled with the same triple. -# CHECK: Flags [ (0x54001000) +# This *MUST* match the output of 'gcc -c' compiled with the same triple. +# CHECK: Flags [ (0x54001004) .set mips16 f: diff --git a/test/MC/Mips/elf_eflags_nan2008.s b/test/MC/Mips/elf_eflags_nan2008.s index 71a22be..f690342 100644 --- a/test/MC/Mips/elf_eflags_nan2008.s +++ b/test/MC/Mips/elf_eflags_nan2008.s @@ -4,8 +4,8 @@ # RUN: llvm-mc -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| \ # RUN: FileCheck %s -check-prefix=CHECK-ASM -# This *MUST* match the output of gas compiled with the same triple. -# CHECK-OBJ: Flags [ (0x50001400) +# This *MUST* match the output of 'gcc -c' compiled with the same triple. +# CHECK-OBJ: Flags [ (0x50001404) # CHECK-ASM: .nan 2008 diff --git a/test/MC/Mips/elf_eflags_nanlegacy.s b/test/MC/Mips/elf_eflags_nanlegacy.s index 6897ad2..0fa0787 100644 --- a/test/MC/Mips/elf_eflags_nanlegacy.s +++ b/test/MC/Mips/elf_eflags_nanlegacy.s @@ -4,12 +4,12 @@ # RUN: llvm-mc -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| \ # RUN: FileCheck %s -check-prefix=CHECK-ASM -# This *MUST* match the output of gas compiled with the same triple. -# CHECK-OBJ: Flags [ (0x50001000) +# This *MUST* match the output of 'gcc -c' compiled with the same triple. +# CHECK-OBJ: Flags [ (0x50001004) # CHECK-ASM: .nan 2008 # CHECK-ASM: .nan legacy .nan 2008 -// Let's override the previous directive! +# Let's override the previous directive! .nan legacy diff --git a/test/MC/Mips/elf_eflags_noreorder.s b/test/MC/Mips/elf_eflags_noreorder.s index 3fea18b..fe46b41 100644 --- a/test/MC/Mips/elf_eflags_noreorder.s +++ b/test/MC/Mips/elf_eflags_noreorder.s @@ -1,6 +1,6 @@ # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| llvm-readobj -h | FileCheck %s -# This *MUST* match the output of gas compiled with the same triple. -# CHECK: Flags [ (0x50001001) +# This *MUST* match the output of 'gcc -c' compiled with the same triple. +# CHECK: Flags [ (0x50001005) .set noreorder diff --git a/test/MC/Mips/elf_eflags_pic0.s b/test/MC/Mips/elf_eflags_pic0.s index a78ca03..04115fa 100644 --- a/test/MC/Mips/elf_eflags_pic0.s +++ b/test/MC/Mips/elf_eflags_pic0.s @@ -1,6 +1,6 @@ # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| llvm-readobj -h | FileCheck %s -# This *MUST* match the output of gas compiled with the same triple. +# This *MUST* match the output of 'gcc -c' compiled with the same triple. # CHECK: Flags [ (0x50001004) .abicalls diff --git a/test/MC/Mips/elf_eflags_pic2.s b/test/MC/Mips/elf_eflags_pic2.s index a15208a..692c478 100644 --- a/test/MC/Mips/elf_eflags_pic2.s +++ b/test/MC/Mips/elf_eflags_pic2.s @@ -1,6 +1,6 @@ # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| llvm-readobj -h | FileCheck %s -# This *MUST* match the output of gas compiled with the same triple. +# This *MUST* match the output of 'gcc -c' compiled with the same triple. # CHECK: Flags [ (0x50001006) .option pic2 diff --git a/test/MC/Mips/elf_reginfo.s b/test/MC/Mips/elf_reginfo.s index 5e9ddf8..ba4788a 100644 --- a/test/MC/Mips/elf_reginfo.s +++ b/test/MC/Mips/elf_reginfo.s @@ -14,13 +14,19 @@ # check for .MIPS.options # CHECK_64: Sections [ # CHECK_64: Section { -# CHECK_64: Name: .MIPS.options +# CHECK_64-LABEL: Name: .MIPS.options # CHECK_64-NEXT: Type: SHT_MIPS_OPTIONS # CHECK_64-NEXT: Flags [ (0x8000002) +# CHECK_64: AddressAlignment: 8 +# CHECK_64: EntrySize: 1 +# CHECK_64-LABEL: } # check for .reginfo # CHECK_32: Sections [ # CHECK_32: Section { -# CHECK_32: Name: .reginfo +# CHECK_32-LABEL: Name: .reginfo # CHECK_32-NEXT: Type: SHT_MIPS_REGINFO # CHECK_32-NEXT: Flags [ (0x2) +# CHECK_32: AddressAlignment: 8 +# CHECK_32: EntrySize: 24 +# CHECK_32-LABEL: } diff --git a/test/MC/Mips/micromips-16-bit-instructions.s b/test/MC/Mips/micromips-16-bit-instructions.s index 31bddcc..35855e1 100644 --- a/test/MC/Mips/micromips-16-bit-instructions.s +++ b/test/MC/Mips/micromips-16-bit-instructions.s @@ -9,19 +9,85 @@ #------------------------------------------------------------------------------ # Little endian #------------------------------------------------------------------------------ +# CHECK-EL: addu16 $6, $17, $4 # encoding: [0x42,0x07] +# CHECK-EL: subu16 $5, $16, $3 # encoding: [0xb1,0x06] +# CHECK-EL: andi16 $16, $2, 31 # encoding: [0x29,0x2c] +# CHECK-EL: and16 $16, $2 # encoding: [0x82,0x44] +# CHECK-EL: not16 $17, $3 # encoding: [0x0b,0x44] +# CHECK-EL: or16 $16, $4 # encoding: [0xc4,0x44] +# CHECK-EL: xor16 $17, $5 # encoding: [0x4d,0x44] +# CHECK-EL: sll16 $3, $16, 5 # encoding: [0x8a,0x25] +# CHECK-EL: srl16 $4, $17, 6 # encoding: [0x1d,0x26] +# CHECK-EL: li16 $3, -1 # encoding: [0xff,0xed] +# CHECK-EL: li16 $3, 126 # encoding: [0xfe,0xed] +# CHECK-EL: addiur1sp $7, 4 # encoding: [0x83,0x6f] +# CHECK-EL: addiur2 $6, $7, -1 # encoding: [0x7e,0x6f] +# CHECK-EL: addiur2 $6, $7, 12 # encoding: [0x76,0x6f] +# CHECK-EL: addius5 $7, -2 # encoding: [0xfc,0x4c] +# CHECK-EL: addiusp -16 # encoding: [0xf9,0x4f] # CHECK-EL: mfhi $9 # encoding: [0x09,0x46] # CHECK-EL: mflo $9 # encoding: [0x49,0x46] # CHECK-EL: move $25, $1 # encoding: [0x21,0x0f] -# CHECK-EL: jalr $9 # encoding: [0xc9,0x45] +# CHECK-EL: jrc $9 # encoding: [0xa9,0x45] +# CHECK-NEXT: jalr $9 # encoding: [0xc9,0x45] +# CHECK-EL: jraddiusp 20 # encoding: [0x05,0x47] +# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EL: jalrs16 $9 # encoding: [0xe9,0x45] +# CHECK-EL: move $zero, $zero # encoding: [0x00,0x0c] +# CHECK-EL: jr16 $9 # encoding: [0x89,0x45] +# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ +# CHECK-EB: addu16 $6, $17, $4 # encoding: [0x07,0x42] +# CHECK-EB: subu16 $5, $16, $3 # encoding: [0x06,0xb1] +# CHECK-EB: andi16 $16, $2, 31 # encoding: [0x2c,0x29] +# CHECK-EB: and16 $16, $2 # encoding: [0x44,0x82] +# CHECK-EB: not16 $17, $3 # encoding: [0x44,0x0b] +# CHECK-EB: or16 $16, $4 # encoding: [0x44,0xc4] +# CHECK-EB: xor16 $17, $5 # encoding: [0x44,0x4d] +# CHECK-EB: sll16 $3, $16, 5 # encoding: [0x25,0x8a] +# CHECK-EB: srl16 $4, $17, 6 # encoding: [0x26,0x1d] +# CHECK-EB: li16 $3, -1 # encoding: [0xed,0xff] +# CHECK-EB: li16 $3, 126 # encoding: [0xed,0xfe] +# CHECK-EB: addiur1sp $7, 4 # encoding: [0x6f,0x83] +# CHECK-EB: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e] +# CHECK-EB: addiur2 $6, $7, 12 # encoding: [0x6f,0x76] +# CHECK-EB: addius5 $7, -2 # encoding: [0x4c,0xfc] +# CHECK-EB: addiusp -16 # encoding: [0x4f,0xf9] # CHECK-EB: mfhi $9 # encoding: [0x46,0x09] # CHECK-EB: mflo $9 # encoding: [0x46,0x49] # CHECK-EB: move $25, $1 # encoding: [0x0f,0x21] -# CHECK-EB: jalr $9 # encoding: [0x45,0xc9] +# CHECK-EB: jrc $9 # encoding: [0x45,0xa9] +# CHECK-NEXT: jalr $9 # encoding: [0x45,0xc9] +# CHECK-EB: jraddiusp 20 # encoding: [0x47,0x05] +# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EB: jalrs16 $9 # encoding: [0x45,0xe9] +# CHECK-EB: move $zero, $zero # encoding: [0x0c,0x00] +# CHECK-EB: jr16 $9 # encoding: [0x45,0x89] +# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] + addu16 $6, $17, $4 + subu16 $5, $16, $3 + andi16 $16, $2, 31 + and16 $16, $2 + not16 $17, $3 + or16 $16, $4 + xor16 $17, $5 + sll16 $3, $16, 5 + srl16 $4, $17, 6 + li16 $3, -1 + li16 $3, 126 + addiur1sp $7, 4 + addiur2 $6, $7, -1 + addiur2 $6, $7, 12 + addius5 $7, -2 + addiusp -16 mfhi $9 mflo $9 move $25, $1 + jrc $9 jalr $9 + jraddiusp 20 + jalrs16 $9 + jr16 $9 diff --git a/test/MC/Mips/micromips-branch-instructions.s b/test/MC/Mips/micromips-branch-instructions.s index 84df2a1..cf0aab7 100644 --- a/test/MC/Mips/micromips-branch-instructions.s +++ b/test/MC/Mips/micromips-branch-instructions.s @@ -29,6 +29,10 @@ # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EL: bltz $6, 1332 # encoding: [0x06,0x40,0x9a,0x02] # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EL: bgezals $6, 1332 # encoding: [0x66,0x42,0x9a,0x02] +# CHECK-EL: move $zero, $zero # encoding: [0x00,0x0c] +# CHECK-EL: bltzals $6, 1332 # encoding: [0x26,0x42,0x9a,0x02] +# CHECK-EL: move $zero, $zero # encoding: [0x00,0x0c] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -52,6 +56,10 @@ # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EB: bltz $6, 1332 # encoding: [0x40,0x06,0x02,0x9a] # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EB: bgezals $6, 1332 # encoding: [0x42,0x66,0x02,0x9a] +# CHECK-EB: move $zero, $zero # encoding: [0x0c,0x00] +# CHECK-EB: bltzals $6, 1332 # encoding: [0x42,0x26,0x02,0x9a] +# CHECK-EB: move $zero, $zero # encoding: [0x0c,0x00] b 1332 beq $9,$6,1332 @@ -63,3 +71,5 @@ bne $9,$6,1332 bal 1332 bltz $6,1332 + bgezals $6,1332 + bltzals $6,1332 diff --git a/test/MC/Mips/micromips-control-instructions.s b/test/MC/Mips/micromips-control-instructions.s index aff84c2..e79896d 100644 --- a/test/MC/Mips/micromips-control-instructions.s +++ b/test/MC/Mips/micromips-control-instructions.s @@ -9,6 +9,12 @@ #------------------------------------------------------------------------------ # Little endian #------------------------------------------------------------------------------ +# CHECK-EL: sdbbp # encoding: [0x00,0x00,0x7c,0xdb] +# CHECK-EL: sdbbp 34 # encoding: [0x22,0x00,0x7c,0xdb] +# CHECK-EL: .set push +# CHECK-EL: .set mips32r2 +# CHECK-EL: rdhwr $5, $29 +# CHECK-EL: .set pop # encoding: [0xbd,0x00,0x3c,0x6b] # CHECK-EL: break # encoding: [0x00,0x00,0x07,0x00] # CHECK-EL: break 7 # encoding: [0x07,0x00,0x07,0x00] # CHECK-EL: break 7, 5 # encoding: [0x07,0x00,0x47,0x01] @@ -24,9 +30,19 @@ # CHECK-EL: ei $10 # encoding: [0x0a,0x00,0x7c,0x57] # CHECK-EL: wait # encoding: [0x00,0x00,0x7c,0x93] # CHECK-EL: wait 17 # encoding: [0x11,0x00,0x7c,0x93] +# CHECK-EL: tlbp # encoding: [0x00,0x00,0x7c,0x03] +# CHECK-EL: tlbr # encoding: [0x00,0x00,0x7c,0x13] +# CHECK-EL: tlbwi # encoding: [0x00,0x00,0x7c,0x23] +# CHECK-EL: tlbwr # encoding: [0x00,0x00,0x7c,0x33] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ +# CHECK-EB: sdbbp # encoding: [0x00,0x00,0xdb,0x7c] +# CHECK-EB: sdbbp 34 # encoding: [0x00,0x22,0xdb,0x7c] +# CHECK-EB: .set push +# CHECK-EB: .set mips32r2 +# CHECK-EB: rdhwr $5, $29 +# CHECK-EB: .set pop # encoding: [0x00,0xbd,0x6b,0x3c] # CHECK-EB: break # encoding: [0x00,0x00,0x00,0x07] # CHECK-EB: break 7 # encoding: [0x00,0x07,0x00,0x07] # CHECK-EB: break 7, 5 # encoding: [0x00,0x07,0x01,0x47] @@ -42,7 +58,14 @@ # CHECK-EB: ei $10 # encoding: [0x00,0x0a,0x57,0x7c] # CHECK-EB: wait # encoding: [0x00,0x00,0x93,0x7c] # CHECK-EB: wait 17 # encoding: [0x00,0x11,0x93,0x7c] +# CHECK-EB: tlbp # encoding: [0x00,0x00,0x03,0x7c] +# CHECK-EB: tlbr # encoding: [0x00,0x00,0x13,0x7c] +# CHECK-EB: tlbwi # encoding: [0x00,0x00,0x23,0x7c] +# CHECK-EB: tlbwr # encoding: [0x00,0x00,0x33,0x7c] + sdbbp + sdbbp 34 + rdhwr $5, $29 break break 7 break 7,5 @@ -58,3 +81,7 @@ ei $10 wait wait 17 + tlbp + tlbr + tlbwi + tlbwr diff --git a/test/MC/Mips/micromips-fpu-instructions.s b/test/MC/Mips/micromips-fpu-instructions.s index 5af4f98..0aeb326 100644 --- a/test/MC/Mips/micromips-fpu-instructions.s +++ b/test/MC/Mips/micromips-fpu-instructions.s @@ -53,6 +53,8 @@ # CHECK-EL: ctc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x18] # CHECK-EL: mfc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x20] # CHECK-EL: mtc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x28] +# CHECK-EL: mfhc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x30] +# CHECK-EL: mthc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x38] # CHECK-EL: movz.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x20] # CHECK-EL: movz.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x21] # CHECK-EL: movn.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x20] @@ -116,6 +118,8 @@ # CHECK-EB: ctc1 $6, $0 # encoding: [0x54,0xc0,0x18,0x3b] # CHECK-EB: mfc1 $6, $f8 # encoding: [0x54,0xc8,0x20,0x3b] # CHECK-EB: mtc1 $6, $f8 # encoding: [0x54,0xc8,0x28,0x3b] +# CHECK-EB: mfhc1 $6, $f8 # encoding: [0x54,0xc8,0x30,0x3b] +# CHECK-EB: mthc1 $6, $f8 # encoding: [0x54,0xc8,0x38,0x3b] # CHECK-EB: movz.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x78] # CHECK-EB: movz.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x78] # CHECK-EB: movn.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x38] @@ -175,6 +179,8 @@ ctc1 $6, $0 mfc1 $6, $f8 mtc1 $6, $f8 + mfhc1 $6, $f8 + mthc1 $6, $f8 movz.s $f4, $f6, $7 movz.d $f4, $f6, $7 movn.s $f4, $f6, $7 diff --git a/test/MC/Mips/micromips-invalid.s b/test/MC/Mips/micromips-invalid.s new file mode 100644 index 0000000..779e66e --- /dev/null +++ b/test/MC/Mips/micromips-invalid.s @@ -0,0 +1,31 @@ +# RUN: not llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips 2>%t1 +# RUN: FileCheck %s < %t1 + + addiur1sp $7, 260 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + addiur1sp $7, 241 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: misaligned immediate operand value + addiur1sp $8, 240 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + addius5 $7, 9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + addu16 $6, $14, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + subu16 $5, $16, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + andi16 $16, $10, 0x1f # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + andi16 $16, $2, 17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + and16 $16, $8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + not16 $18, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + or16 $16, $10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + xor16 $15, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sll16 $1, $16, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + srl16 $4, $9, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sll16 $3, $16, 9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + srl16 $4, $5, 15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + li16 $8, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + li16 $4, -2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected + lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected + lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand + swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected + swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected + swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand + lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $24, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand diff --git a/test/MC/Mips/micromips-jump-instructions.s b/test/MC/Mips/micromips-jump-instructions.s index a6c7676..aed18dc 100644 --- a/test/MC/Mips/micromips-jump-instructions.s +++ b/test/MC/Mips/micromips-jump-instructions.s @@ -19,6 +19,10 @@ # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EL: jr $7 # encoding: [0x07,0x00,0x3c,0x0f] # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EL: jals 1328 # encoding: [0x00,0x74,0x98,0x02] +# CHECK-EL: move $zero, $zero # encoding: [0x00,0x0c] +# CHECK-EL: jalrs $ra, $6 # encoding: [0xe6,0x03,0x3c,0x4f] +# CHECK-EL: move $zero, $zero # encoding: [0x00,0x0c] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -32,9 +36,15 @@ # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EB: jr $7 # encoding: [0x00,0x07,0x0f,0x3c] # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EB: jals 1328 # encoding: [0x74,0x00,0x02,0x98] +# CHECK-EB: move $zero, $zero # encoding: [0x0c,0x00] +# CHECK-EB: jalrs $ra, $6 # encoding: [0x03,0xe6,0x4f,0x3c] +# CHECK-EB: move $zero, $zero # encoding: [0x0c,0x00] j 1328 jal 1328 jalr $ra, $6 jr $7 j $7 + jals 1328 + jalrs $ra, $6 diff --git a/test/MC/Mips/micromips-label-test-sections.s b/test/MC/Mips/micromips-label-test-sections.s new file mode 100644 index 0000000..569b64c --- /dev/null +++ b/test/MC/Mips/micromips-label-test-sections.s @@ -0,0 +1,35 @@ +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 \ +# RUN: -mattr=+micromips -filetype=obj -o - | llvm-readobj -t | FileCheck %s + .text + .set micromips +f: + nop +g: + .section .text +h: + nop + +# CHECK: Symbols [ +# CHECK: Symbol { +# CHECK: Name: f +# CHECK: Binding: Local +# CHECK: Type: None +# CHECK: Other: 128 +# CHECK: Section: .text +# CHECK: } +# CHECK: Symbol { +# CHECK: Name: g +# CHECK: Binding: Local +# CHECK: Type: None +# CHECK: Other: 0 +# CHECK: Section: .text +# CHECK: } +# CHECK: Symbol { +# CHECK: Name: h +# CHECK: Binding: Local +# CHECK: Type: None +# CHECK: Other: 128 +# CHECK: Section: .text +# CHECK: } +# CHECK: ] + diff --git a/test/MC/Mips/micromips-label-test.s b/test/MC/Mips/micromips-label-test.s new file mode 100644 index 0000000..cc1566b --- /dev/null +++ b/test/MC/Mips/micromips-label-test.s @@ -0,0 +1,54 @@ +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 \ +# RUN: -mattr=+micromips -filetype=obj -o - | llvm-readobj -t | FileCheck %s + .text + .set nomicromips +f: + nop +g: + .set micromips + nop +h: + .word 0 +i: + nop +j: + .set nomicromips + nop +# CHECK: Symbols [ +# CHECK: Symbol { +# CHECK: Name: f +# CHECK: Binding: Local +# CHECK: Type: None +# CHECK: Other: 0 +# CHECK: Section: .text +# CHECK: } +# CHECK: Symbol { +# CHECK: Name: g +# CHECK: Binding: Local +# CHECK: Type: None +# CHECK: Other: 128 +# CHECK: Section: .text +# CHECK: } +# CHECK: Symbol { +# CHECK: Name: h +# CHECK: Binding: Local +# CHECK: Type: None +# CHECK: Other: 0 +# CHECK: Section: .text +# CHECK: } +# CHECK: Symbol { +# CHECK: Name: i +# CHECK: Binding: Local +# CHECK: Type: None +# CHECK: Other: 128 +# CHECK: Section: .text +# CHECK: } +# CHECK: Symbol { +# CHECK: Name: j +# CHECK: Binding: Local +# CHECK: Type: None +# CHECK: Other: 0 +# CHECK: Section: .text +# CHECK: } +# CHECK: ] + diff --git a/test/MC/Mips/micromips-loadstore-instructions.s b/test/MC/Mips/micromips-loadstore-instructions.s index 8a1b93b..62fa101 100644 --- a/test/MC/Mips/micromips-loadstore-instructions.s +++ b/test/MC/Mips/micromips-loadstore-instructions.s @@ -9,31 +9,49 @@ #------------------------------------------------------------------------------ # Little endian #------------------------------------------------------------------------------ -# CHECK-EL: lb $5, 8($4) # encoding: [0xa4,0x1c,0x08,0x00] -# CHECK-EL: lbu $6, 8($4) # encoding: [0xc4,0x14,0x08,0x00] -# CHECK-EL: lh $2, 8($4) # encoding: [0x44,0x3c,0x08,0x00] -# CHECK-EL: lhu $4, 8($2) # encoding: [0x82,0x34,0x08,0x00] -# CHECK-EL: lw $6, 4($5) # encoding: [0xc5,0xfc,0x04,0x00] -# CHECK-EL: sb $5, 8($4) # encoding: [0xa4,0x18,0x08,0x00] -# CHECK-EL: sh $2, 8($4) # encoding: [0x44,0x38,0x08,0x00] -# CHECK-EL: sw $5, 4($6) # encoding: [0xa6,0xf8,0x04,0x00] -# CHECK-EL: ll $2, 8($4) # encoding: [0x44,0x60,0x08,0x30] -# CHECK-EL: sc $2, 8($4) # encoding: [0x44,0x60,0x08,0xb0] -# CHECK-EL: lwu $2, 8($4) # encoding: [0x44,0x60,0x08,0xe0] +# CHECK-EL: lb $5, 8($4) # encoding: [0xa4,0x1c,0x08,0x00] +# CHECK-EL: lbu $6, 8($4) # encoding: [0xc4,0x14,0x08,0x00] +# CHECK-EL: lh $2, 8($4) # encoding: [0x44,0x3c,0x08,0x00] +# CHECK-EL: lhu $4, 8($2) # encoding: [0x82,0x34,0x08,0x00] +# CHECK-EL: lw $6, 4($5) # encoding: [0xc5,0xfc,0x04,0x00] +# CHECK-EL: sb $5, 8($4) # encoding: [0xa4,0x18,0x08,0x00] +# CHECK-EL: sh $2, 8($4) # encoding: [0x44,0x38,0x08,0x00] +# CHECK-EL: sw $5, 4($6) # encoding: [0xa6,0xf8,0x04,0x00] +# CHECK-EL: ll $2, 8($4) # encoding: [0x44,0x60,0x08,0x30] +# CHECK-EL: sc $2, 8($4) # encoding: [0x44,0x60,0x08,0xb0] +# CHECK-EL: lwu $2, 8($4) # encoding: [0x44,0x60,0x08,0xe0] +# CHECK-EL: lwxs $2, $3($4) # encoding: [0x64,0x00,0x18,0x11] +# CHECK-EL: lwm32 $16, $17, 8($4) # encoding: [0x44,0x20,0x08,0x50] +# CHECK-EL: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x84,0x20,0x08,0x50] +# CHECK-EL: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x24,0x21,0x08,0x50] +# CHECK-EL: lwm32 $16, $17, $18, $19, $ra, 8($4) # encoding: [0x84,0x22,0x08,0x50] +# CHECK-EL: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x24,0x23,0x08,0x50] +# CHECK-EL: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x24,0x23,0x08,0x50] +# CHECK-EL: swm32 $16, $17, 8($4) # encoding: [0x44,0x20,0x08,0xd0] +# CHECK-EL: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x84,0x20,0x08,0xd0] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ -# CHECK-EB: lb $5, 8($4) # encoding: [0x1c,0xa4,0x00,0x08] -# CHECK-EB: lbu $6, 8($4) # encoding: [0x14,0xc4,0x00,0x08] -# CHECK-EB: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08] -# CHECK-EB: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08] -# CHECK-EB: lw $6, 4($5) # encoding: [0xfc,0xc5,0x00,0x04] -# CHECK-EB: sb $5, 8($4) # encoding: [0x18,0xa4,0x00,0x08] -# CHECK-EB: sh $2, 8($4) # encoding: [0x38,0x44,0x00,0x08] -# CHECK-EB: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04] -# CHECK-EB: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08] -# CHECK-EB: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08] -# CHECK-EB: lwu $2, 8($4) # encoding: [0x60,0x44,0xe0,0x08] +# CHECK-EB: lb $5, 8($4) # encoding: [0x1c,0xa4,0x00,0x08] +# CHECK-EB: lbu $6, 8($4) # encoding: [0x14,0xc4,0x00,0x08] +# CHECK-EB: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08] +# CHECK-EB: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08] +# CHECK-EB: lw $6, 4($5) # encoding: [0xfc,0xc5,0x00,0x04] +# CHECK-EB: sb $5, 8($4) # encoding: [0x18,0xa4,0x00,0x08] +# CHECK-EB: sh $2, 8($4) # encoding: [0x38,0x44,0x00,0x08] +# CHECK-EB: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04] +# CHECK-EB: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08] +# CHECK-EB: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08] +# CHECK-EB: lwu $2, 8($4) # encoding: [0x60,0x44,0xe0,0x08] +# CHECK-EB: lwxs $2, $3($4) # encoding: [0x00,0x64,0x11,0x18] +# CHECK-EB: lwm32 $16, $17, 8($4) # encoding: [0x20,0x44,0x50,0x08] +# CHECK-EB: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08] +# CHECK-EB: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4) # encoding: [0x21,0x24,0x50,0x08] +# CHECK-EB: lwm32 $16, $17, $18, $19, $ra, 8($4) # encoding: [0x22,0x84,0x50,0x08] +# CHECK-EB: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08] +# CHECK-EB: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08] +# CHECK-EB: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08] +# CHECK-EB: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08] lb $5, 8($4) lbu $6, 8($4) lh $2, 8($4) @@ -45,3 +63,12 @@ ll $2, 8($4) sc $2, 8($4) lwu $2, 8($4) + lwxs $2, $3($4) + lwm32 $16, $17, 8($4) + lwm32 $16 - $19, 8($4) + lwm32 $16-$23, $30, 8($4) + lwm32 $16-$19, $31, 8($4) + lwm32 $16-$23, $30, $31, 8($4) + lwm32 $16-$23, $30 - $31, 8($4) + swm32 $16, $17, 8($4) + swm32 $16 - $19, 8($4) diff --git a/test/MC/Mips/mips-expansions-bad.s b/test/MC/Mips/mips-expansions-bad.s index a137deb..8d85169 100644 --- a/test/MC/Mips/mips-expansions-bad.s +++ b/test/MC/Mips/mips-expansions-bad.s @@ -2,5 +2,5 @@ # RUN: FileCheck %s < %t1 .text - li $5, 0x100000000 # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled - dli $5, 1 # CHECK: :[[@LINE]]:9: error: instruction requires a CPU feature not currently enabled + li $5, 0x100000000 # CHECK: :[[@LINE]]:9: error: instruction requires a 64-bit architecture + dli $5, 1 # CHECK: :[[@LINE]]:9: error: instruction requires a 64-bit architecture diff --git a/test/MC/Mips/mips-expansions.s b/test/MC/Mips/mips-expansions.s index f0a04a5..bdc76fb 100644 --- a/test/MC/Mips/mips-expansions.s +++ b/test/MC/Mips/mips-expansions.s @@ -17,6 +17,22 @@ # CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c] # CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34] # CHECK: addu $7, $7, $8 # encoding: [0x21,0x38,0xe8,0x00] +# CHECK: lui $8, %hi(symbol) # encoding: [A,A,0x08,0x3c] + # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 +# CHECK: ori $8, $8, %lo(symbol) # encoding: [A,A,0x08,0x35] + # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 +# CHECK: .set mips64 +# CHECK: lui $8, %highest(symbol) # encoding: [A,A,0x08,0x3c] + # fixup A - offset: 0, value: symbol@HIGHEST, kind: fixup_Mips_HIGHEST +# CHECK: ori $8, $8, %higher(symbol) # encoding: [A,A,0x08,0x35] + # fixup A - offset: 0, value: symbol@HIGHER, kind: fixup_Mips_HIGHER +# CHECK: dsll $8, $8, 16 # encoding: [0x38,0x44,0x08,0x00] +# CHECK: ori $8, $8, %hi(symbol) # encoding: [A,A,0x08,0x35] + # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 +# CHECK: dsll $8, $8, 16 # encoding: [0x38,0x44,0x08,0x00] +# CHECK: ori $8, $8, %lo(symbol) # encoding: [A,A,0x08,0x35] + # fixup A - offset: 0, value: symbol@ABS_LO, kind: fixup_Mips_LO16 +# CHECK: .set mips32r2 # CHECK: lui $10, %hi(symbol) # encoding: [A,A,0x0a,0x3c] # CHECK: # fixup A - offset: 0, value: symbol@ABS_HI, kind: fixup_Mips_HI16 # CHECK: addu $10, $10, $4 # encoding: [0x21,0x50,0x44,0x01] @@ -48,6 +64,10 @@ la $7,65538 la $a0, 20($a1) la $7,65538($8) + la $t0, symbol + .set mips64 + la $t0, symbol + .set mips32r2 .set noat lw $t2, symbol($a0) diff --git a/test/MC/Mips/mips-hwr-register-names.s b/test/MC/Mips/mips-hwr-register-names.s new file mode 100644 index 0000000..3849675 --- /dev/null +++ b/test/MC/Mips/mips-hwr-register-names.s @@ -0,0 +1,199 @@ +# Check the hardware registers +# +# FIXME: Use the code generator in order to print the .set directives +# instead of the instruction printer. +# +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r2 | \ +# RUN: FileCheck %s + .set noat + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $hwr_cpunum + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x00,0x3b] + rdhwr $a0,$hwr_cpunum + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $hwr_cpunum + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x00,0x3b] + rdhwr $a0,$0 + + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $5, $hwr_synci_step + # CHECK-NEXT: .set pop # encoding: [0x7c,0x05,0x08,0x3b] + rdhwr $a1,$hwr_synci_step + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $5, $hwr_synci_step + # CHECK-NEXT: .set pop # encoding: [0x7c,0x05,0x08,0x3b] + rdhwr $a1,$1 + + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $6, $hwr_cc + # CHECK-NEXT: .set pop # encoding: [0x7c,0x06,0x10,0x3b] + rdhwr $a2,$hwr_cc + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $6, $hwr_cc + # CHECK-NEXT: .set pop # encoding: [0x7c,0x06,0x10,0x3b] + rdhwr $a2,$2 + + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $7, $hwr_ccres + # CHECK-NEXT: .set pop # encoding: [0x7c,0x07,0x18,0x3b] + rdhwr $a3,$hwr_ccres + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $7, $hwr_ccres + # CHECK-NEXT: .set pop # encoding: [0x7c,0x07,0x18,0x3b] + rdhwr $a3,$3 + + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $4 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x20,0x3b] + rdhwr $a0,$4 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $5 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x28,0x3b] + rdhwr $a0,$5 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $6 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x30,0x3b] + rdhwr $a0,$6 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $7 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x38,0x3b] + rdhwr $a0,$7 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $8 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x40,0x3b] + rdhwr $a0,$8 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $9 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x48,0x3b] + rdhwr $a0,$9 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $10 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x50,0x3b] + rdhwr $a0,$10 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $11 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x58,0x3b] + rdhwr $a0,$11 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $12 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x60,0x3b] + rdhwr $a0,$12 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $13 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x68,0x3b] + rdhwr $a0,$13 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $14 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x70,0x3b] + rdhwr $a0,$14 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $15 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x78,0x3b] + rdhwr $a0,$15 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $16 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x80,0x3b] + rdhwr $a0,$16 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $17 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x88,0x3b] + rdhwr $a0,$17 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $18 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x90,0x3b] + rdhwr $a0,$18 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $19 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0x98,0x3b] + rdhwr $a0,$19 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $20 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0xa0,0x3b] + rdhwr $a0,$20 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $21 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0xa8,0x3b] + rdhwr $a0,$21 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $22 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0xb0,0x3b] + rdhwr $a0,$22 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $23 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0xb8,0x3b] + rdhwr $a0,$23 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $24 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0xc0,0x3b] + rdhwr $a0,$24 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $25 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0xc8,0x3b] + rdhwr $a0,$25 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $26 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0xd0,0x3b] + rdhwr $a0,$26 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $27 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0xd8,0x3b] + rdhwr $a0,$27 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $28 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0xe0,0x3b] + rdhwr $a0,$28 + + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $29 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0xe8,0x3b] + rdhwr $a0,$29 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $29 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0xe8,0x3b] + rdhwr $a0,$hwr_ulr + + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $30 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0xf0,0x3b] + rdhwr $a0,$30 + # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $4, $31 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x04,0xf8,0x3b] + rdhwr $a0,$31 diff --git a/test/MC/Mips/mips-jump-delay-slots.s b/test/MC/Mips/mips-jump-delay-slots.s new file mode 100644 index 0000000..49f6c15 --- /dev/null +++ b/test/MC/Mips/mips-jump-delay-slots.s @@ -0,0 +1,122 @@ +# Verify that every branch and jump instruction is followed by a delay slot +# except for the branch likely instructions. +# +# RUN: llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r2 | FileCheck %s + + .set noat + # CHECK: b 1332 + # CHECK: nop + b 1332 + # CHECK: bc1f 1332 + # CHECK: nop + bc1f 1332 + # CHECK: bc1t 1332 + # CHECK: nop + bc1t 1332 + # CHECK: beq $9, $6, 1332 + # CHECK: nop + beq $9,$6,1332 + # CHECK: bgez $6, 1332 + # CHECK: nop + bgez $6,1332 + # CHECK: bgezal $6, 1332 + # CHECK: nop + bgezal $6,1332 + # CHECK: bgtz $6, 1332 + # CHECK: nop + bgtz $6,1332 + # CHECK: blez $6, 1332 + # CHECK: nop + blez $6,1332 + # CHECK: bltz $6, 1332 + # CHECK: nop + bltz $6,1332 + # CHECK: bne $9, $6, 1332 + # CHECK: nop + bne $9,$6,1332 + # CHECK: bltzal $6, 1332 + # CHECK: nop + bltzal $6,1332 + # CHECK: bal 1332 + # CHECK: nop + bal 1332 + # CHECK: bnez $11, 1332 + # CHECK: nop + bnez $11,1332 + # CHECK: beqz $11, 1332 + # CHECK: nop + beqz $11,1332 + + # CHECK: bc1fl 1332 + # CHECK-NOT: nop + bc1fl 1332 + # CHECK: bc1fl 1332 + # CHECK-NOT: nop + bc1fl $fcc0, 1332 + # CHECK: bc1fl $fcc3, 1332 + # CHECK-NOT: nop + bc1fl $fcc3, 1332 + # CHECK: bc1tl 1332 + # CHECK-NOT: nop + bc1tl 1332 + # CHECK: bc1tl 1332 + # CHECK-NOT: nop + bc1tl $fcc0, 1332 + # CHECK: bc1tl $fcc3, 1332 + # CHECK-NOT: nop + bc1tl $fcc3, 1332 + # CHECK: beql $9, $6, 1332 + # CHECK-NOT: nop + beql $9,$6,1332 + # CHECK: bnel $9, $6, 1332 + # CHECK-NOT: nop + bnel $9,$6,1332 + # CHECK: bgezl $6, 1332 + # CHECK-NOT: nop + bgezl $6,1332 + # CHECK: bgtzl $6, 1332 + # CHECK-NOT: nop + bgtzl $6,1332 + # CHECK: blezl $6, 1332 + # CHECK-NOT: nop + blezl $6,1332 + # CHECK: bltzl $6, 1332 + # CHECK-NOT: nop + bltzl $6,1332 + # CHECK: bgezall $6, 1332 + # CHECK-NOT: nop + bgezall $6,1332 + # CHECK: bltzall $6, 1332 + # CHECK-NOT: nop + bltzall $6,1332 + + # CHECK: j 1328 + # CHECK: nop + j 1328 + # CHECK: jal 1328 + # CHECK: nop + jal 1328 + # CHECK: jalr $6 + # CHECK: nop + jalr $6 + # CHECK: jalr $25 + # CHECK: nop + jalr $31,$25 + # CHECK: jalr $10, $11 + # CHECK: nop + jalr $10,$11 + # CHECK: jr $7 + # CHECK: nop + jr $7 + # CHECK: jr $7 + # CHECK: nop + j $7 + # CHECK: jalr $25 + # CHECK: nop + jal $25 + # CHECK: jalr $4, $25 + # CHECK: nop + jal $4,$25 + # CHECK: jalx lab + # CHECK: nop + jalx lab diff --git a/test/MC/Mips/mips-noat.s b/test/MC/Mips/mips-noat.s index 07db251..f9d4efd 100644 --- a/test/MC/Mips/mips-noat.s +++ b/test/MC/Mips/mips-noat.s @@ -12,7 +12,7 @@ test1: test2: .set noat - lw $2, 65536($2) # ERROR: mips-noat.s:[[@LINE]]:9: error: Pseudo instruction requires $at, which is not available + lw $2, 65536($2) # ERROR: mips-noat.s:[[@LINE]]:9: error: pseudo-instruction requires $at, which is not available # Can we switch it back on successfully? @@ -26,4 +26,4 @@ test3: test4: .set at=$0 - lw $2, 65536($2) # ERROR: mips-noat.s:[[@LINE]]:9: error: Pseudo instruction requires $at, which is not available + lw $2, 65536($2) # ERROR: mips-noat.s:[[@LINE]]:9: error: pseudo-instruction requires $at, which is not available diff --git a/test/MC/Mips/mips-pdr-bad.s b/test/MC/Mips/mips-pdr-bad.s new file mode 100644 index 0000000..40c6ba2 --- /dev/null +++ b/test/MC/Mips/mips-pdr-bad.s @@ -0,0 +1,42 @@ +# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1 +# RUN: FileCheck %s < %t1 -check-prefix=ASM + + .text + + .ent # ASM: :[[@LINE]]:14: error: expected identifier after .ent + .ent bar, # ASM: :[[@LINE]]:19: error: expected number after comma + .ent foo, bar # AMS: :[[@LINE]]:23: error: expected an absolute expression after comma + .ent foo, 5, bar # AMS: :[[@LINE]]:20: error: unexpected token, expected end of statement + + .frame # ASM: :[[@LINE]]:16: error: expected stack register + .frame bar # ASM: :[[@LINE]]:16: error: expected stack register + .frame $f1, 8, # ASM: :[[@LINE]]:16: error: expected general purpose register + .frame $sp # ASM: :[[@LINE]]:20: error: unexpected token, expected comma + .frame $sp, # ASM: :[[@LINE]]:21: error: expected frame size value + .frame $sp, bar # ASM: :[[@LINE]]:25: error: frame size not an absolute expression + .frame $sp, 8 # ASM: :[[@LINE]]:23: error: unexpected token, expected comma + .frame $sp, 8, # ASM: :[[@LINE]]:24: error: expected return register + .frame $sp, 8, $f1 # ASM: :[[@LINE]]:24: error: expected general purpose register + .frame $sp, 8, $ra, foo # ASM: :[[@LINE]]:27: error: unexpected token, expected end of statement + + .mask # ASM: :[[@LINE]]:16: error: expected bitmask value + .mask foo # ASM: :[[@LINE]]:19: error: bitmask not an absolute expression + .mask 0x80000000 # ASM: :[[@LINE]]:26: error: unexpected token, expected comma + .mask 0x80000000, # ASM: :[[@LINE]]:27: error: expected frame offset value + .mask 0x80000000, foo # ASM: :[[@LINE]]:31: error: frame offset not an absolute expression + .mask 0x80000000, -4, bar # ASM: :[[@LINE]]:29: error: unexpected token, expected end of statement + + .fmask # ASM: :[[@LINE]]:17: error: expected bitmask value + .fmask foo # ASM: :[[@LINE]]:20: error: bitmask not an absolute expression + .fmask 0x80000000 # ASM: :[[@LINE]]:27: error: unexpected token, expected comma + .fmask 0x80000000, # ASM: :[[@LINE]]:28: error: expected frame offset value + .fmask 0x80000000, foo # ASM: :[[@LINE]]:32: error: frame offset not an absolute expression + .fmask 0x80000000, -4, bar # ASM: :[[@LINE]]:30: error: unexpected token, expected end of statement + + .end # ASM: :[[@LINE]]:14: error: expected identifier after .end + .ent _local_foo_bar + .end _local_foo_bar, foo # ASM: :[[@LINE]]:28: error: unexpected token, expected end of statement + .end _local_foo_bar + .end _local_foo # ASM: :[[@LINE]]:25: error: .end used without .ent + .ent _local_foo, 2 + .end _local_foo_bar # ASM: :[[@LINE]]:29: error: .end symbol does not match .ent symbol diff --git a/test/MC/Mips/mips-pdr.s b/test/MC/Mips/mips-pdr.s new file mode 100644 index 0000000..372c259 --- /dev/null +++ b/test/MC/Mips/mips-pdr.s @@ -0,0 +1,64 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -filetype=asm | \ +# RUN: FileCheck %s -check-prefix=ASMOUT + +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -filetype=obj -o - | \ +# RUN: llvm-readobj -s -section-data | \ +# RUN: FileCheck %s -check-prefix=OBJOUT + +# ASMOUT: .text +# ASMOUT: .type _local_foo,@function +# ASMOUT: .ent _local_foo +# ASMOUT:_local_foo: +# ASMOUT: .frame $fp,16,$ra +# ASMOUT: .mask 0x10101010,-4 +# ASMOUT: .fmask 0x01010101,-8 +# ASMOUT: .end _local_foo +# ASMOUT: .size local_foo, + +# OBJOUT: Section { +# OBJOUT: Name: .pdr +# OBJOUT: Type: SHT_PROGBITS (0x1) +# OBJOUT: Flags [ (0xB) +# OBJOUT: SHF_ALLOC (0x2) +# OBJOUT: SHF_WRITE (0x1) +# OBJOUT: ] +# OBJOUT: Size: 64 +# OBJOUT: SectionData ( +# OBJOUT: 0000: 00000000 10101010 FFFFFFFC 01010101 +# OBJOUT: 0010: FFFFFFF8 00000010 0000001E 0000001F +# OBJOUT: 0020: 00000000 10101010 FFFFFFFC 01010101 +# OBJOUT: 0030: FFFFFFF8 00000010 0000001E 0000001F +# OBJOUT: ) +# OBJOUT: } + +# We should also check if relocation information was correctly generated. +# OBJOUT: Section { +# OBJOUT: Name: .rel.pdr +# OBJOUT: Type: SHT_REL (0x9) +# OBJOUT: Flags [ (0x0) +# OBJOUT: ] +# OBJOUT: Size: 16 +# OBJOUT: SectionData ( +# OBJOUT: 0000: 00000000 00000202 00000020 00000802 +# OBJOUT: ) +# OBJOUT: } + +.text + .type _local_foo,@function + .ent _local_foo +_local_foo: + .frame $fp,16,$ra + .mask 0x10101010,-4 + .fmask 0x01010101,-8 + .end _local_foo + .size local_foo,.-_local_foo + + .globl _global_foo + .type _global_foo,@function + .ent _global_foo +_global_foo: + .frame $fp,16,$ra + .mask 0x10101010,-4 + .fmask 0x01010101,-8 + .end _global_foo + .size global_foo,.-_global_foo diff --git a/test/MC/Mips/mips-reginfo-fp32.s b/test/MC/Mips/mips-reginfo-fp32.s new file mode 100644 index 0000000..5b31884 --- /dev/null +++ b/test/MC/Mips/mips-reginfo-fp32.s @@ -0,0 +1,34 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -filetype=obj -o - | \ +# RUN: llvm-readobj -s -section-data | \ +# RUN: FileCheck %s + +# CHECK: Section { +# CHECK: Index: +# CHECK: Name: .reginfo +# CHECK: Type: SHT_MIPS_REGINFO (0x70000006) +# CHECK: Flags [ (0x2) +# CHECK: SHF_ALLOC (0x2) +# CHECK: ] +# CHECK: Size: 24 +# CHECK: SectionData ( +# CHECK: 0000: 01010101 00000000 C0007535 00000000 +# CHECK: 0010: 00000000 00000000 +# CHECK: ) +# CHECK: } + +.text + add $0,$0,$0 + add $8,$0,$0 + add $16,$0,$0 + add $24,$0,$0 + +# abs.s - Reads and writes from/to $f0. + abs.s $f0,$f0 +# round.w.d - Reads $f4 and $f5 and writes to $f2. + round.w.d $f2,$f4 +# ceil.w.s - Reads $f8 and writes to $f10. + ceil.w.s $f10, $f8 +# cvt.s.d - Reads from $f12 and $f13 and writes to $f14 + cvt.s.d $f14, $f12 +# abs.d - Reads from $f30 and $f31 and writes to $f30 and $f31. + abs.d $f30,$f30 diff --git a/test/MC/Mips/mips-reginfo-fp64.s b/test/MC/Mips/mips-reginfo-fp64.s new file mode 100644 index 0000000..b60e54e --- /dev/null +++ b/test/MC/Mips/mips-reginfo-fp64.s @@ -0,0 +1,60 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 -mattr=+msa,+fp64 -filetype=obj -o - | \ +# RUN: llvm-readobj -s -section-data | \ +# RUN: FileCheck %s -check-prefix=ELF32 + +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64,-n64,+n32 -filetype=obj -o - | \ +# RUN: llvm-readobj -s -section-data | \ +# RUN: FileCheck %s -check-prefix=ELF32 + +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64,+n64 -filetype=obj -o - | \ +# RUN: llvm-readobj -s -section-data | \ +# RUN: FileCheck %s -check-prefix=ELF64 + +# ELF32: Section { +# ELF32: Name: .reginfo +# ELF32: Type: SHT_MIPS_REGINFO (0x70000006) +# ELF32: Flags [ (0x2) +# ELF32: SHF_ALLOC (0x2) +# ELF32: ] +# ELF32: Size: 24 +# ELF32: SectionData ( +# ELF32: 0000: 01010101 00000000 4C005515 00000000 +# ELF32: 0010: 00000000 00000000 +# ELF32: ) +# ELF32: } + +# ELF64: Section { +# ELF64: Name: .MIPS.options +# ELF64: Type: SHT_MIPS_OPTIONS (0x7000000D) +# ELF64: Flags [ (0x8000002) +# ELF64: SHF_ALLOC (0x2) +# ELF64: SHF_MIPS_NOSTRIP (0x8000000) +# ELF64: ] +# ELF64: Size: 40 +# ELF64: SectionData ( +# ELF64: 0000: 01280000 00000000 01010101 00000000 +# ELF64: 0010: 00000000 4C005515 00000000 00000000 +# ELF64: 0020: 00000000 00000000 +# ELF64: ) +# ELF64: } + +.text + add $0,$0,$0 + add $8,$0,$0 + add $16,$0,$0 + add $24,$0,$0 + +# abs.s - Reads and writes from/to $f0. + abs.s $f0,$f0 +# round.w.d - Reads $f4 and writes to $f2. + round.w.d $f2,$f4 +# ceil.w.s - Reads $f8 and writes to $f10. + ceil.w.s $f10, $f8 +# cvt.s.d - Reads from $f12 and writes to $f14. + cvt.s.d $f14, $f12 +# abs.d - Reads from $f30 and writes to $f30. + abs.d $f30,$f30 + +# Read and write from/to $f26 and $f27 + add_a.b $w26,$w26,$w26 + add_a.b $w27,$w27,$w27 diff --git a/test/MC/Mips/mips1/invalid-mips2.s b/test/MC/Mips/mips1/invalid-mips2.s index 7db261d..29bd223 100644 --- a/test/MC/Mips/mips1/invalid-mips2.s +++ b/test/MC/Mips/mips1/invalid-mips2.s @@ -5,6 +5,18 @@ # RUN: FileCheck %s < %t1 .set noat + bc1fl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1fl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1tl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1tl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + beql $14,$s3,12544 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezl $4,-6858 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgtzl $10,-3738 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + blezl $6,2974 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltzall $6,488 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltzl $s1,-9964 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bnel $gp,$s4,5107 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -13,11 +25,23 @@ round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + teq $0,$3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + teq $5,$7,620 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tge $7,$10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tge $5,$19,340 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgeu $22,$28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tgeu $20,$14,379 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlt $15,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tlt $2,$19,133 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tlti $t6,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tltu $11,$16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tltu $16,$29,1016 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tne $6,$17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + tne $7,$8,885 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tnei $t4,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips1/invalid-mips3.s b/test/MC/Mips/mips1/invalid-mips3.s index d1b0eec..d4be08e 100644 --- a/test/MC/Mips/mips1/invalid-mips3.s +++ b/test/MC/Mips/mips1/invalid-mips3.s @@ -19,6 +19,8 @@ daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddu $24,$2,18079 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddu $19,26943 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -43,6 +45,8 @@ dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsrlv $s3,$14,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubu $15,$11,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubu $14,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips1/invalid-mips32r2.s b/test/MC/Mips/mips1/invalid-mips32r2.s new file mode 100644 index 0000000..679f21f --- /dev/null +++ b/test/MC/Mips/mips1/invalid-mips32r2.s @@ -0,0 +1,11 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips1/invalid-mips4-wrong-error.s b/test/MC/Mips/mips1/invalid-mips4-wrong-error.s index 2016e70..cec30c8 100644 --- a/test/MC/Mips/mips1/invalid-mips4-wrong-error.s +++ b/test/MC/Mips/mips1/invalid-mips4-wrong-error.s @@ -6,6 +6,8 @@ # RUN: FileCheck %s < %t1 .set noat + bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/mips1/invalid-mips5-wrong-error.s b/test/MC/Mips/mips1/invalid-mips5-wrong-error.s index 74473a3..18c0b61 100644 --- a/test/MC/Mips/mips1/invalid-mips5-wrong-error.s +++ b/test/MC/Mips/mips1/invalid-mips5-wrong-error.s @@ -6,41 +6,41 @@ # RUN: FileCheck %s < %t1 .set noat - abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips1/valid.s b/test/MC/Mips/mips1/valid.s index 66e11ba..53ff6a0 100644 --- a/test/MC/Mips/mips1/valid.s +++ b/test/MC/Mips/mips1/valid.s @@ -10,7 +10,10 @@ add.s $f8,$f21,$f24 addi $13,$9,26322 addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] + add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] + add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] addu $9,$a0,$a2 + addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] and $s7,$v0,$12 and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] @@ -97,6 +100,8 @@ srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] sub $s6,$s3,$12 + sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] + sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub.d $f18,$f3,$f17 sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 diff --git a/test/MC/Mips/mips2/invalid-mips3.s b/test/MC/Mips/mips2/invalid-mips3.s index 458c416..e72b228 100644 --- a/test/MC/Mips/mips2/invalid-mips3.s +++ b/test/MC/Mips/mips2/invalid-mips3.s @@ -15,6 +15,8 @@ daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddu $24,$2,18079 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + daddu $19,26943 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -40,6 +42,8 @@ dsrlv $s3,$t2,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsub $a3,$s6,$a4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubu $15,$11,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dsubu $14,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips2/invalid-mips32r2.s b/test/MC/Mips/mips2/invalid-mips32r2.s index 72a570a..6dc8159 100644 --- a/test/MC/Mips/mips2/invalid-mips32r2.s +++ b/test/MC/Mips/mips2/invalid-mips32r2.s @@ -13,7 +13,9 @@ cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips2/invalid-mips4-wrong-error.s b/test/MC/Mips/mips2/invalid-mips4-wrong-error.s index 193f6d7..28a98ba 100644 --- a/test/MC/Mips/mips2/invalid-mips4-wrong-error.s +++ b/test/MC/Mips/mips2/invalid-mips4-wrong-error.s @@ -6,6 +6,8 @@ # RUN: FileCheck %s < %t1 .set noat + bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/mips2/invalid-mips5-wrong-error.s b/test/MC/Mips/mips2/invalid-mips5-wrong-error.s index 0c58c6c..5eaeaa2 100644 --- a/test/MC/Mips/mips2/invalid-mips5-wrong-error.s +++ b/test/MC/Mips/mips2/invalid-mips5-wrong-error.s @@ -6,41 +6,41 @@ # RUN: FileCheck %s < %t1 .set noat - abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips2/valid.s b/test/MC/Mips/mips2/valid.s index 9c3706e..34843bc 100644 --- a/test/MC/Mips/mips2/valid.s +++ b/test/MC/Mips/mips2/valid.s @@ -6,21 +6,36 @@ abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 add $s7,$s2,$a1 + add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] + add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add.d $f1,$f7,$f29 add.s $f8,$f21,$f24 addi $13,$9,26322 addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addu $9,$a0,$a2 + addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] and $s7,$v0,$12 and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1fl $fcc0,50 # CHECK: bc1fl 50 # encoding: [0x45,0x02,0x00,0x0c] + bc1fl 50 # CHECK: bc1fl 50 # encoding: [0x45,0x02,0x00,0x0c] bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1tl $fcc0,-8239 # CHECK: bc1tl -8239 # encoding: [0x45,0x03,0xf7,0xf4] + bc1tl -8239 # CHECK: bc1tl -8239 # encoding: [0x45,0x03,0xf7,0xf4] bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + beql $14,$s3,12544 # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40] + bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] + bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] + bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] + blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] + bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] + bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] + bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 c.sf.d $f30,$f0 @@ -113,6 +128,8 @@ srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] sub $s6,$s3,$12 + sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] + sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub.d $f18,$f3,$f17 sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 @@ -123,15 +140,27 @@ swl $15,13694($s3) swr $s1,-26590($14) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] + teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 + tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] + tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tgei $s1,5025 tgeiu $sp,-28621 + tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] + tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32] + tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlti $14,-21059 tltiu $ra,-5076 + tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] + tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] + tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] + tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tnei $12,-29647 trunc.w.d $f22,$f15 trunc.w.s $f28,$f30 diff --git a/test/MC/Mips/mips3/invalid-mips32r2.s b/test/MC/Mips/mips3/invalid-mips32r2.s new file mode 100644 index 0000000..178e0f0 --- /dev/null +++ b/test/MC/Mips/mips3/invalid-mips32r2.s @@ -0,0 +1,11 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips3/invalid-mips4-wrong-error.s b/test/MC/Mips/mips3/invalid-mips4-wrong-error.s new file mode 100644 index 0000000..c9af39a --- /dev/null +++ b/test/MC/Mips/mips3/invalid-mips4-wrong-error.s @@ -0,0 +1,10 @@ +# Instructions that are invalid and are correctly rejected but use the wrong +# error message at the moment. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/mips3/invalid-mips5-wrong-error.s b/test/MC/Mips/mips3/invalid-mips5-wrong-error.s index 2c0246a..cf809d3 100644 --- a/test/MC/Mips/mips3/invalid-mips5-wrong-error.s +++ b/test/MC/Mips/mips3/invalid-mips5-wrong-error.s @@ -6,41 +6,41 @@ # RUN: FileCheck %s < %t1 .set noat - abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips3/valid.s b/test/MC/Mips/mips3/valid.s index cb209fd..a55576d 100644 --- a/test/MC/Mips/mips3/valid.s +++ b/test/MC/Mips/mips3/valid.s @@ -6,21 +6,36 @@ abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 add $s7,$s2,$a1 + add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] + add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add.d $f1,$f7,$f29 add.s $f8,$f21,$f24 addi $13,$9,26322 addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addu $9,$a0,$a2 + addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] and $s7,$v0,$12 and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1fl $fcc0,50 # CHECK: bc1fl 50 # encoding: [0x45,0x02,0x00,0x0c] + bc1fl 50 # CHECK: bc1fl 50 # encoding: [0x45,0x02,0x00,0x0c] bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1tl $fcc0,-8239 # CHECK: bc1tl -8239 # encoding: [0x45,0x03,0xf7,0xf4] + bc1tl -8239 # CHECK: bc1tl -8239 # encoding: [0x45,0x03,0xf7,0xf4] bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + beql $14,$s3,12544 # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40] + bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] + bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] + bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] + blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] + bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] + bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] + bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 @@ -50,6 +65,8 @@ daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddiu $k0,$s6,-4586 daddu $s3,$at,$ra + daddu $24,$2,18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x64,0x58,0x46,0x9f] + daddu $19,26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f] ddiv $zero,$k0,$s3 ddivu $zero,$s0,$s1 div $zero,$25,$11 @@ -84,6 +101,8 @@ dsubi $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] dsubu $a1,$a1,$k0 + dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f] + dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] eret floor.l.d $f26,$f7 @@ -171,6 +190,8 @@ srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] sub $s6,$s3,$12 + sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] + sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub.d $f18,$f3,$f17 sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 @@ -180,15 +201,27 @@ swl $15,13694($s3) swr $s1,-26590($14) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] + teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 + tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] + tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tgei $s1,5025 tgeiu $sp,-28621 + tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] + tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32] + tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlti $14,-21059 tltiu $ra,-5076 + tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] + tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] + tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] + tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tnei $12,-29647 trunc.l.d $f23,$f23 trunc.l.s $f28,$f31 diff --git a/test/MC/Mips/mips32/abiflags.s b/test/MC/Mips/mips32/abiflags.s index 896dd84..dd772c0 100644 --- a/test/MC/Mips/mips32/abiflags.s +++ b/test/MC/Mips/mips32/abiflags.s @@ -8,27 +8,26 @@ # CHECK-ASM: .module fp=32 # Checking if the Mips.abiflags were correctly emitted. -# CHECK-OBJ: Section { -# CHECK-OBJ: Index: 5 -# CHECK-OBJ: Name: .MIPS.abiflags (12) -# CHECK-OBJ: Type: (0x7000002A) -# CHECK-OBJ: Flags [ (0x2) -# CHECK-OBJ: SHF_ALLOC (0x2) -# CHECK-OBJ: ] -# CHECK-OBJ: Address: 0x0 -# CHECK-OBJ: Offset: 0x50 -# CHECK-OBJ: Size: 24 -# CHECK-OBJ: Link: 0 -# CHECK-OBJ: Info: 0 -# CHECK-OBJ: AddressAlignment: 8 -# CHECK-OBJ: EntrySize: 0 -# CHECK-OBJ: Relocations [ -# CHECK-OBJ: ] -# CHECK-OBJ: SectionData ( -# CHECK-OBJ: 0000: 00002001 01010001 00000000 00000000 |.. .............| -# CHECK-OBJ: 0010: 00000000 00000000 |........| -# CHECK-OBJ: ) -# CHECK-OBJ: } +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ-LABEL: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: SHT_MIPS_ABIFLAGS (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 24 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00002001 01010001 00000000 00000000 |.. .............| +# CHECK-OBJ: 0010: 00000001 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ-LABEL: } .module fp=32 diff --git a/test/MC/Mips/mips32/invalid-mips32r2.s b/test/MC/Mips/mips32/invalid-mips32r2.s index fa6fe32..07a1e8f 100644 --- a/test/MC/Mips/mips32/invalid-mips32r2.s +++ b/test/MC/Mips/mips32/invalid-mips32r2.s @@ -8,7 +8,9 @@ cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32/valid.s b/test/MC/Mips/mips32/valid.s index d330905..d79c390 100644 --- a/test/MC/Mips/mips32/valid.s +++ b/test/MC/Mips/mips32/valid.s @@ -6,23 +6,40 @@ abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 add $s7,$s2,$a1 + add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] + add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add.d $f1,$f7,$f29 add.s $f8,$f21,$f24 addi $13,$9,26322 addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addu $9,$a0,$a2 + addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] and $s7,$v0,$12 and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1fl $fcc0,4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl 4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl $fcc7,27 # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06] bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01] bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1tl $fcc0,4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl 4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl $fcc7,27 # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06] bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + beql $14,$s3,12544 # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40] + bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] + bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] + bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] + blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] + bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] + bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] + bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 @@ -141,6 +158,8 @@ srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] sub $s6,$s3,$12 + sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] + sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub.d $f18,$f3,$f17 sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 @@ -151,15 +170,27 @@ swr $s1,-26590($14) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] + teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 + tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] + tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tgei $s1,5025 tgeiu $sp,-28621 + tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] + tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32] + tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlti $14,-21059 tltiu $ra,-5076 + tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] + tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] + tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] + tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tnei $12,-29647 trunc.w.d $f22,$f15 trunc.w.s $f28,$f30 diff --git a/test/MC/Mips/mips32r2/abiflags.s b/test/MC/Mips/mips32r2/abiflags.s index 41a809a..e3bb15b 100644 --- a/test/MC/Mips/mips32r2/abiflags.s +++ b/test/MC/Mips/mips32r2/abiflags.s @@ -9,27 +9,26 @@ # CHECK-ASM: .set fp=64 # Checking if the Mips.abiflags were correctly emitted. -# CHECK-OBJ: Section { -# CHECK-OBJ: Index: 5 -# CHECK-OBJ: Name: .MIPS.abiflags (12) -# CHECK-OBJ: Type: (0x7000002A) -# CHECK-OBJ: Flags [ (0x2) -# CHECK-OBJ: SHF_ALLOC (0x2) -# CHECK-OBJ: ] -# CHECK-OBJ: Address: 0x0 -# CHECK-OBJ: Offset: 0x50 -# CHECK-OBJ: Size: 24 -# CHECK-OBJ: Link: 0 -# CHECK-OBJ: Info: 0 -# CHECK-OBJ: AddressAlignment: 8 -# CHECK-OBJ: EntrySize: 0 -# CHECK-OBJ: Relocations [ -# CHECK-OBJ: ] -# CHECK-OBJ: SectionData ( -# CHECK-OBJ: 0000: 00002002 01010001 00000000 00000000 |.. .............| -# CHECK-OBJ: 0010: 00000000 00000000 |........| -# CHECK-OBJ: ) -# CHECK-OBJ: } +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ-LABEL: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: SHT_MIPS_ABIFLAGS (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 24 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00002002 01010001 00000000 00000000 |.. .............| +# CHECK-OBJ: 0010: 00000001 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ-LABEL: } .module fp=32 .set fp=64 diff --git a/test/MC/Mips/mips32r2/valid.s b/test/MC/Mips/mips32r2/valid.s index 631c691..4ef5aab 100644 --- a/test/MC/Mips/mips32r2/valid.s +++ b/test/MC/Mips/mips32r2/valid.s @@ -6,23 +6,40 @@ abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 add $s7,$s2,$a1 + add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] + add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add.d $f1,$f7,$f29 add.s $f8,$f21,$f24 addi $13,$9,26322 addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addu $9,$a0,$a2 + addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] and $s7,$v0,$12 and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1fl $fcc0,4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl 4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl $fcc7,27 # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06] bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01] bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1tl $fcc0,4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl 4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl $fcc7,27 # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06] bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + beql $14,$s3,12544 # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40] + bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] + bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] + bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] + blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] + bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] + bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] + bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 @@ -43,13 +60,15 @@ cvt.w.d $f20,$f14 cvt.w.s $f20,$f24 deret - di $s8 + di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00] + di # CHECK: di # encoding: [0x41,0x60,0x60,0x00] div $zero,$25,$11 div.d $f29,$f20,$f27 div.s $f4,$f5,$f15 divu $zero,$25,$15 ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - ei $14 + ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] + ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] eret floor.w.d $f14,$f11 floor.w.s $f8,$f9 @@ -132,7 +151,12 @@ or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] - rdhwr $sp,$11 + # FIXME: Use the code generator in order to print the .set directives + # instead of the instruction printer. + rdhwr $sp,$11 # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $sp, $11 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] @@ -169,6 +193,8 @@ srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] sub $s6,$s3,$12 + sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] + sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub.d $f18,$f3,$f17 sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 @@ -181,15 +207,27 @@ swxc1 $f19,$12($k0) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] + teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 + tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] + tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tgei $s1,5025 tgeiu $sp,-28621 + tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] + tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32] + tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlti $14,-21059 tltiu $ra,-5076 + tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] + tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] + tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] + tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tnei $12,-29647 trunc.w.d $f22,$f15 trunc.w.s $f28,$f30 diff --git a/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s index 52fa5f5..cc7d403 100644 --- a/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s +++ b/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s @@ -5,13 +5,13 @@ # RUN: FileCheck %s < %t1 .set noat - bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips32r6/invalid-mips1.s b/test/MC/Mips/mips32r6/invalid-mips1.s index 44d4fbb..94810f4 100644 --- a/test/MC/Mips/mips32r6/invalid-mips1.s +++ b/test/MC/Mips/mips32r6/invalid-mips1.s @@ -5,6 +5,8 @@ # RUN: FileCheck %s < %t1 .set noat + add $9,$14,15176 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + add $24,-7193 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -22,3 +24,5 @@ multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled # div has been re-encoded. See valid.s # divu has been re-encoded. See valid.s + sub $22,$17,-3126 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sub $13,6512 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s index b799c8e..1cec777 100644 --- a/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s +++ b/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s @@ -6,15 +6,5 @@ # RUN: FileCheck %s < %t1 .set noat - beql $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bgezall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bgezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bgtzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - blezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bltzall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bltzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bnel $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips32r6/invalid-mips2.s b/test/MC/Mips/mips32r6/invalid-mips2.s index bfa2c4c..642d6bd 100644 --- a/test/MC/Mips/mips32r6/invalid-mips2.s +++ b/test/MC/Mips/mips32r6/invalid-mips2.s @@ -6,6 +6,18 @@ .set noat addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1fl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1fl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1tl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1tl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + beql $14,$s3,12544 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bnel $gp,$s4,5107 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezl $4,-6858 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgtzl $10,-3738 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + blezl $6,2974 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltzl $s1,-9964 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltzall $6,488 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s index e63bdd4..3131c5a 100644 --- a/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s +++ b/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s @@ -6,15 +6,11 @@ # RUN: FileCheck %s < %t1 .set noat - bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips32r6/invalid-mips32.s b/test/MC/Mips/mips32r6/invalid-mips32.s index e0889ea..b2330c2 100644 --- a/test/MC/Mips/mips32r6/invalid-mips32.s +++ b/test/MC/Mips/mips32r6/invalid-mips32.s @@ -5,6 +5,8 @@ # RUN: FileCheck %s < %t1 .set noat + bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s index f3131a9..06bf58c 100644 --- a/test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s +++ b/test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s @@ -6,16 +6,6 @@ # RUN: FileCheck %s < %t1 .set noat - beql $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bgezall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bgezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bgtzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - blezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bltzall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bltzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bnel $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips32r6/invalid-mips4.s b/test/MC/Mips/mips32r6/invalid-mips4.s index 8ba2ed8..9d8f02f 100644 --- a/test/MC/Mips/mips32r6/invalid-mips4.s +++ b/test/MC/Mips/mips32r6/invalid-mips4.s @@ -5,6 +5,8 @@ # RUN: FileCheck %s < %t1 .set noat + bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s index 99d10c3..b5d7380 100644 --- a/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s +++ b/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s @@ -5,7 +5,7 @@ # RUN: FileCheck %s < %t1 .set noat - bc1any2f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1any2t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1any4f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1any4t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1any2f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc1any2t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc1any4f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc1any4t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s index f23dbd7..362785b 100644 --- a/test/MC/Mips/mips32r6/valid.s +++ b/test/MC/Mips/mips32r6/valid.s @@ -17,6 +17,7 @@ # FIXME: Add the instructions carried forward from older ISA's and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0xec,0x80,0x00,0x19] + addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0] aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38] aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9] @@ -96,8 +97,12 @@ cmp.sle.d $f2,$f3,$f4 # CHECK: cmp.sle.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8e] cmp.sule.s $f2,$f3,$f4 # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f] cmp.sule.d $f2,$f3,$f4 # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f] + di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00] + di # CHECK: di # encoding: [0x41,0x60,0x60,0x00] div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a] divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b] + ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] + ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00] jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00] lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xc5] @@ -114,6 +119,12 @@ msubf.s $f2,$f3,$f4 # CHECK: msubf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x99] msubf.d $f2,$f3,$f4 # CHECK: msubf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x99] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x35] + # FIXME: Use the code generator in order to print the .set directives + # instead of the instruction printer. + rdhwr $sp,$11 # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $sp, $11 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10] sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10] seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35] @@ -152,3 +163,15 @@ sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] + teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] + tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] + tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] + tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] + tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] + tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32] + tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] + tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] + tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] + tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] + tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] diff --git a/test/MC/Mips/mips4/invalid-mips32r2.s b/test/MC/Mips/mips4/invalid-mips32r2.s new file mode 100644 index 0000000..3e78758 --- /dev/null +++ b/test/MC/Mips/mips4/invalid-mips32r2.s @@ -0,0 +1,11 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips4 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips4/invalid-mips5-wrong-error.s b/test/MC/Mips/mips4/invalid-mips5-wrong-error.s index c6c8968..5c8ab23 100644 --- a/test/MC/Mips/mips4/invalid-mips5-wrong-error.s +++ b/test/MC/Mips/mips4/invalid-mips5-wrong-error.s @@ -6,41 +6,41 @@ # RUN: FileCheck %s < %t1 .set noat - abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips4/valid.s b/test/MC/Mips/mips4/valid.s index 949b91d..c221b76 100644 --- a/test/MC/Mips/mips4/valid.s +++ b/test/MC/Mips/mips4/valid.s @@ -6,23 +6,40 @@ abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 add $s7,$s2,$a1 + add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] + add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add.d $f1,$f7,$f29 add.s $f8,$f21,$f24 addi $13,$9,26322 addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addu $9,$a0,$a2 + addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] and $s7,$v0,$12 and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1fl $fcc0,4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl 4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl $fcc7,27 # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06] bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01] bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1tl $fcc0,4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl 4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl $fcc7,27 # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06] bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + beql $14,$s3,12544 # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40] + bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] + bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] + bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] + blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] + bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] + bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] + bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 @@ -52,6 +69,8 @@ daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddiu $k0,$s6,-4586 daddu $s3,$at,$ra + daddu $24,$2,18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x64,0x58,0x46,0x9f] + daddu $19,26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f] ddiv $zero,$k0,$s3 ddivu $zero,$s0,$s1 div $zero,$25,$11 @@ -86,6 +105,8 @@ dsubi $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] dsubu $a1,$a1,$k0 + dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f] + dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] eret floor.l.d $f26,$f7 @@ -189,6 +210,8 @@ srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] sub $s6,$s3,$12 + sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] + sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub.d $f18,$f3,$f17 sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 @@ -199,15 +222,27 @@ swr $s1,-26590($14) swxc1 $f19,$12($k0) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] + teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 + tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] + tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tgei $s1,5025 tgeiu $sp,-28621 + tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] + tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32] + tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlti $14,-21059 tltiu $ra,-5076 + tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] + tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] + tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] + tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tnei $12,-29647 trunc.l.d $f23,$f23 trunc.l.s $f28,$f31 diff --git a/test/MC/Mips/mips5/invalid-mips32r2.s b/test/MC/Mips/mips5/invalid-mips32r2.s new file mode 100644 index 0000000..a369efa --- /dev/null +++ b/test/MC/Mips/mips5/invalid-mips32r2.s @@ -0,0 +1,11 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips5 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips5/valid.s b/test/MC/Mips/mips5/valid.s index 3afdee1..b93b22f 100644 --- a/test/MC/Mips/mips5/valid.s +++ b/test/MC/Mips/mips5/valid.s @@ -6,23 +6,40 @@ abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 add $s7,$s2,$a1 + add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] + add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add.d $f1,$f7,$f29 add.s $f8,$f21,$f24 addi $13,$9,26322 addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addu $9,$a0,$a2 + addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] and $s7,$v0,$12 and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1fl $fcc0,4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl 4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl $fcc7,27 # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06] bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01] bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1tl $fcc0,4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl 4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl $fcc7,27 # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06] bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + beql $14,$s3,12544 # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40] + bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] + bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] + bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] + blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] + bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] + bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] + bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 @@ -52,6 +69,8 @@ daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddiu $k0,$s6,-4586 daddu $s3,$at,$ra + daddu $24,$2,18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x64,0x58,0x46,0x9f] + daddu $19,26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f] ddiv $zero,$k0,$s3 ddivu $zero,$s0,$s1 div $zero,$25,$11 @@ -86,6 +105,8 @@ dsubi $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] dsubu $a1,$a1,$k0 + dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f] + dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] eret floor.l.d $f26,$f7 @@ -190,6 +211,8 @@ srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] sub $s6,$s3,$12 + sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] + sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub.d $f18,$f3,$f17 sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 @@ -201,15 +224,27 @@ swr $s1,-26590($14) swxc1 $f19,$12($k0) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] + teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 + tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] + tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tgei $s1,5025 tgeiu $sp,-28621 + tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] + tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32] + tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlti $14,-21059 tltiu $ra,-5076 + tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] + tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] + tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] + tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tnei $12,-29647 trunc.l.d $f23,$f23 trunc.l.s $f28,$f31 diff --git a/test/MC/Mips/mips64-register-names-n32-n64.s b/test/MC/Mips/mips64-register-names-n32-n64.s index ee6f88f..efe1cdb 100644 --- a/test/MC/Mips/mips64-register-names-n32-n64.s +++ b/test/MC/Mips/mips64-register-names-n32-n64.s @@ -1,7 +1,11 @@ -# RUN: llvm-mc %s -triple=mips64-unknown-freebsd -show-encoding | FileCheck %s +# RUN: llvm-mc %s -triple=mips64-unknown-freebsd -show-encoding 2>%t0 \ +# RUN: | FileCheck %s +# RUN: FileCheck -check-prefix=WARNING %s < %t0 +# # RUN: llvm-mc %s -triple=mips64-unknown-freebsd -show-encoding \ -# RUN: -mattr=-n64,+n32 | FileCheck %s - +# RUN: -mattr=-n64,+n32 2>%t1 | FileCheck %s +# RUN: FileCheck -check-prefix=WARNING %s < %t1 +# # Check that the register names are mapped to their correct numbers for n32/n64 # Second byte of addiu with $zero at rt contains the number of the source # register. @@ -23,9 +27,25 @@ daddiu $t0, $zero, 0 # [*] # CHECK: encoding: [0x64,0x0c,0x00,0x00] daddiu $t1, $zero, 0 # [*] # CHECK: encoding: [0x64,0x0d,0x00,0x00] daddiu $t2, $zero, 0 # [*] # CHECK: encoding: [0x64,0x0e,0x00,0x00] daddiu $t3, $zero, 0 # [*] # CHECK: encoding: [0x64,0x0f,0x00,0x00] +# WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only available in O32. +# WARNING-NEXT: daddiu $t4, $zero, 0 # {{CHECK}}: encoding: [0x64,0x0c,0x00,0x00] +# WARNING-NEXT: ^~ +# WARNING-NEXT: Did you mean $t0? daddiu $t4, $zero, 0 # CHECK: encoding: [0x64,0x0c,0x00,0x00] +# WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only available in O32. +# WARNING-NEXT: daddiu $t5, $zero, 0 # {{CHECK}}: encoding: [0x64,0x0d,0x00,0x00] +# WARNING-NEXT: ^~ +# WARNING-NEXT: Did you mean $t1? daddiu $t5, $zero, 0 # CHECK: encoding: [0x64,0x0d,0x00,0x00] +# WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only available in O32. +# WARNING-NEXT: daddiu $t6, $zero, 0 # {{CHECK}}: encoding: [0x64,0x0e,0x00,0x00] +# WARNING-NEXT: ^~ +# WARNING-NEXT: Did you mean $t2? daddiu $t6, $zero, 0 # CHECK: encoding: [0x64,0x0e,0x00,0x00] +# WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only available in O32. +# WARNING-NEXT: daddiu $t7, $zero, 0 # {{CHECK}}: encoding: [0x64,0x0f,0x00,0x00] +# WARNING-NEXT: ^~ +# WARNING-NEXT: Did you mean $t3? daddiu $t7, $zero, 0 # CHECK: encoding: [0x64,0x0f,0x00,0x00] daddiu $s0, $zero, 0 # CHECK: encoding: [0x64,0x10,0x00,0x00] daddiu $s1, $zero, 0 # CHECK: encoding: [0x64,0x11,0x00,0x00] diff --git a/test/MC/Mips/mips64/abiflags.s b/test/MC/Mips/mips64/abiflags.s index 557e32a..ecaffcc 100644 --- a/test/MC/Mips/mips64/abiflags.s +++ b/test/MC/Mips/mips64/abiflags.s @@ -8,27 +8,26 @@ # CHECK-ASM: .module fp=64 # Checking if the Mips.abiflags were correctly emitted. -# CHECK-OBJ: Section { -# CHECK-OBJ: Index: 5 -# CHECK-OBJ: Name: .MIPS.abiflags (12) -# CHECK-OBJ: Type: (0x7000002A) -# CHECK-OBJ: Flags [ (0x2) -# CHECK-OBJ: SHF_ALLOC (0x2) -# CHECK-OBJ: ] -# CHECK-OBJ: Address: 0x0 -# CHECK-OBJ: Offset: 0x50 -# CHECK-OBJ: Size: 24 -# CHECK-OBJ: Link: 0 -# CHECK-OBJ: Info: 0 -# CHECK-OBJ: AddressAlignment: 8 -# CHECK-OBJ: EntrySize: 0 -# CHECK-OBJ: Relocations [ -# CHECK-OBJ: ] -# CHECK-OBJ: SectionData ( -# CHECK-OBJ: 0000: 00004001 02020001 00000000 00000000 |..@.............| -# CHECK-OBJ: 0010: 00000000 00000000 |........| -# CHECK-OBJ: ) -# CHECK-OBJ: } +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ-LABEL: Name: .MIPS.abiflags +# CHECK-OBJ: Type: SHT_MIPS_ABIFLAGS (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 24 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00004001 02020001 00000000 00000000 |..@.............| +# CHECK-OBJ: 0010: 00000001 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ-LABEL: } .module fp=64 diff --git a/test/MC/Mips/mips64/invalid-mips32r2.s b/test/MC/Mips/mips64/invalid-mips32r2.s new file mode 100644 index 0000000..bc5d1f0 --- /dev/null +++ b/test/MC/Mips/mips64/invalid-mips32r2.s @@ -0,0 +1,11 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64 \ +# RUN: 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64/valid.s b/test/MC/Mips/mips64/valid.s index 1bd057d..032777e 100644 --- a/test/MC/Mips/mips64/valid.s +++ b/test/MC/Mips/mips64/valid.s @@ -6,23 +6,40 @@ abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 add $s7,$s2,$a1 + add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] + add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add.d $f1,$f7,$f29 add.s $f8,$f21,$f24 addi $13,$9,26322 addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addu $9,$a0,$a2 + addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] and $s7,$v0,$12 and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1fl $fcc0,4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl 4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl $fcc7,27 # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06] bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01] bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1tl $fcc0,4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl 4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl $fcc7,27 # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06] bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + beql $14,$s3,12544 # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40] + bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] + bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] + bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] + blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] + bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] + bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] + bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 @@ -54,6 +71,8 @@ daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddiu $k0,$s6,-4586 daddu $s3,$at,$ra + daddu $24,$2,18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x64,0x58,0x46,0x9f] + daddu $19,26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f] dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25] dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24] deret @@ -91,6 +110,8 @@ dsubi $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] dsubu $a1,$a1,$k0 + dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f] + dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] eret floor.l.d $f26,$f7 @@ -206,6 +227,8 @@ srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] sub $s6,$s3,$12 + sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] + sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub.d $f18,$f3,$f17 sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 @@ -218,15 +241,27 @@ swxc1 $f19,$12($k0) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] + teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 + tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] + tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tgei $s1,5025 tgeiu $sp,-28621 + tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] + tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32] + tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlti $14,-21059 tltiu $ra,-5076 + tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] + tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] + tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] + tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tnei $12,-29647 trunc.l.d $f23,$f23 trunc.l.s $f28,$f31 diff --git a/test/MC/Mips/mips64r2/abiflags.s b/test/MC/Mips/mips64r2/abiflags.s index aa76dee..dc4a1e9 100644 --- a/test/MC/Mips/mips64r2/abiflags.s +++ b/test/MC/Mips/mips64r2/abiflags.s @@ -8,27 +8,26 @@ # CHECK-ASM: .module fp=64 # Checking if the Mips.abiflags were correctly emitted. -# CHECK-OBJ: Section { -# CHECK-OBJ: Index: 5 -# CHECK-OBJ: Name: .MIPS.abiflags (12) -# CHECK-OBJ: Type: (0x7000002A) -# CHECK-OBJ: Flags [ (0x2) -# CHECK-OBJ: SHF_ALLOC (0x2) -# CHECK-OBJ: ] -# CHECK-OBJ: Address: 0x0 -# CHECK-OBJ: Offset: 0x50 -# CHECK-OBJ: Size: 24 -# CHECK-OBJ: Link: 0 -# CHECK-OBJ: Info: 0 -# CHECK-OBJ: AddressAlignment: 8 -# CHECK-OBJ: EntrySize: 0 -# CHECK-OBJ: Relocations [ -# CHECK-OBJ: ] -# CHECK-OBJ: SectionData ( -# CHECK-OBJ: 0000: 00004002 02020001 00000000 00000000 |..@.............| -# CHECK-OBJ: 0010: 00000000 00000000 |........| -# CHECK-OBJ: ) -# CHECK-OBJ: } +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ-LABEL: Name: .MIPS.abiflags +# CHECK-OBJ: Type: SHT_MIPS_ABIFLAGS (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 24 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00004002 02020001 00000000 00000000 |..@.............| +# CHECK-OBJ: 0010: 00000001 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ-LABEL: } .module fp=64 diff --git a/test/MC/Mips/mips64r2/valid.s b/test/MC/Mips/mips64r2/valid.s index 7a2244a..7717238 100644 --- a/test/MC/Mips/mips64r2/valid.s +++ b/test/MC/Mips/mips64r2/valid.s @@ -6,23 +6,40 @@ abs.d $f7,$f25 # CHECK: encoding: abs.s $f9,$f16 add $s7,$s2,$a1 + add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] + add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add.d $f1,$f7,$f29 add.s $f8,$f21,$f24 addi $13,$9,26322 addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] addu $9,$a0,$a2 + addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] and $s7,$v0,$12 and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1fl $fcc0,4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl 4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl $fcc7,27 # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06] bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01] bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1tl $fcc0,4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl 4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl $fcc7,27 # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06] bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + beql $14,$s3,12544 # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40] + bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] + bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] + bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] + blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] + bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] + bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] + bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] c.ngl.d $f29,$f29 c.ngle.d $f0,$f16 @@ -54,10 +71,13 @@ daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddiu $k0,$s6,-4586 daddu $s3,$at,$ra + daddu $24,$2,18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x64,0x58,0x46,0x9f] + daddu $19,26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f] dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25] dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24] deret - di $s8 + di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00] + di # CHECK: di # encoding: [0x41,0x60,0x60,0x00] ddiv $zero,$k0,$s3 ddivu $zero,$s0,$s1 div $zero,$25,$11 @@ -101,8 +121,11 @@ dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] dsubu $a1,$a1,$k0 dsubu $a1,$a1,$k0 + dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f] + dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea] ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] - ei $14 + ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] + ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] eret floor.l.d $f26,$f7 floor.l.s $f12,$f5 @@ -190,7 +213,12 @@ or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] - rdhwr $sp,$11 + # FIXME: Use the code generator in order to print the .set directives + # instead of the instruction printer. + rdhwr $sp,$11 # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $sp, $11 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] @@ -233,6 +261,8 @@ srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] sub $s6,$s3,$12 + sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] + sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub.d $f18,$f3,$f17 sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 @@ -245,15 +275,27 @@ swxc1 $f19,$12($k0) sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] + teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] teqi $s5,-17504 + tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] + tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] tgei $s1,5025 tgeiu $sp,-28621 + tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] + tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32] + tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] tlti $14,-21059 tltiu $ra,-5076 + tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] + tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] + tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] + tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] tnei $12,-29647 trunc.l.d $f23,$f23 trunc.l.s $f28,$f31 diff --git a/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s b/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s index e914c89..5156429 100644 --- a/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s +++ b/test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s @@ -5,13 +5,13 @@ # RUN: FileCheck %s < %t1 .set noat - bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips64r6/invalid-mips1.s b/test/MC/Mips/mips64r6/invalid-mips1.s index 6efd8f4..ce0ab97 100644 --- a/test/MC/Mips/mips64r6/invalid-mips1.s +++ b/test/MC/Mips/mips64r6/invalid-mips1.s @@ -5,6 +5,8 @@ # RUN: FileCheck %s < %t1 .set noat + add $9,$14,15176 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + add $24,-7193 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -25,3 +27,5 @@ multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled # div has been re-encoded. See valid.s # divu has been re-encoded. See valid.s + sub $22,$17,-3126 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sub $13,6512 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64r6/invalid-mips2.s b/test/MC/Mips/mips64r6/invalid-mips2.s index 8a5c50c..a09a051 100644 --- a/test/MC/Mips/mips64r6/invalid-mips2.s +++ b/test/MC/Mips/mips64r6/invalid-mips2.s @@ -6,9 +6,21 @@ .set noat addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1fl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1fl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1tl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1tl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + beql $14,$s3,12544 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezl $4,-6858 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgtzl $10,-3738 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + blezl $6,2974 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltzall $6,488 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltzl $s1,-9964 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bnel $gp,$s4,5107 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s b/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s index 7424f49..eda18ac 100644 --- a/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s +++ b/test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s @@ -9,15 +9,15 @@ ldr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - ldle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - ldre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - sdle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - sdre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + ldle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + ldre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + sdle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + sdre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s b/test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s index cc85f18..8702318 100644 --- a/test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s +++ b/test/MC/Mips/mips64r6/invalid-mips32-wrong-error.s @@ -6,15 +6,11 @@ # RUN: FileCheck %s < %t1 .set noat - bc1fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips64r6/invalid-mips4-wrong-error.s b/test/MC/Mips/mips64r6/invalid-mips4-wrong-error.s index f3131a9..06bf58c 100644 --- a/test/MC/Mips/mips64r6/invalid-mips4-wrong-error.s +++ b/test/MC/Mips/mips64r6/invalid-mips4-wrong-error.s @@ -6,16 +6,6 @@ # RUN: FileCheck %s < %t1 .set noat - beql $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bgezall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bgezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bgtzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - blezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bltzall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bltzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bnel $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips64r6/invalid-mips4.s b/test/MC/Mips/mips64r6/invalid-mips4.s index 706db27..82a1196 100644 --- a/test/MC/Mips/mips64r6/invalid-mips4.s +++ b/test/MC/Mips/mips64r6/invalid-mips4.s @@ -5,6 +5,8 @@ # RUN: FileCheck %s < %t1 .set noat + bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s b/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s index 4fc94e2..ceeb577 100644 --- a/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s +++ b/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s @@ -5,44 +5,44 @@ # RUN: FileCheck %s < %t1 .set noat - abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - alnv.ps $f12,$f18,$f30,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1any2f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1any2t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1any4f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1any4t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - cvt.ps.pw $f3,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + alnv.ps $f12,$f18,$f30,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc1any2f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc1any2t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc1any4f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc1any4t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.le.ps $fcc1,$f7,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.lt.ps $f19,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.nge.ps $f1,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ngl.ps $f21,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ngle.ps $fcc7,$f12,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ngt.ps $fcc5,$f30,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ole.ps $fcc7,$f21,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.seq.ps $fcc6,$f31,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.sf.ps $fcc6,$f4,$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ule.ps $fcc6,$f17,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.ult.ps $fcc7,$f14,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.un.ps $fcc4,$f2,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + cvt.ps.pw $f3,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + madd.ps $f22,$f3,$f14,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + mov.ps $f22,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movf.ps $f10,$f28,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movn.ps $f31,$f31,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s index 34c1dac..3e8fc41 100644 --- a/test/MC/Mips/mips64r6/valid.s +++ b/test/MC/Mips/mips64r6/valid.s @@ -17,6 +17,7 @@ # FIXME: Add the instructions carried forward from older ISA's and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0xec,0x80,0x00,0x19] + addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0] aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38] aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9] @@ -96,13 +97,21 @@ cmp.sle.d $f2,$f3,$f4 # CHECK: cmp.sle.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8e] cmp.sule.s $f2,$f3,$f4 # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f] cmp.sule.d $f2,$f3,$f4 # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f] + daddu $24,$2,18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x64,0x58,0x46,0x9f] + daddu $19,26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f] dalign $4,$2,$3,5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x7c,0x43,0x23,0x64] daui $3,$2,0x1234 # CHECK: daui $3, $2, 4660 # encoding: [0x74,0x62,0x12,0x34] dahi $3,0x5678 # CHECK: dahi $3, 22136 # encoding: [0x04,0x66,0x56,0x78] dati $3,0xabcd # CHECK: dati $3, 43981 # encoding: [0x04,0x7e,0xab,0xcd] dbitswap $4, $2 # CHECK: dbitswap $4, $2 # encoding: [0x7c,0x02,0x20,0x24] + di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00] + di # CHECK: di # encoding: [0x41,0x60,0x60,0x00] div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a] divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b] + dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f] + dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea] + ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] + ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00] jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00] mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda] @@ -146,6 +155,12 @@ seleqz.d $f0, $f2, $f4 # CHECK: seleqz.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x14] selnez.s $f0, $f2, $f4 # CHECK: selnez.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x17] selnez.d $f0, $f2, $f4 # CHECK: selnez.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x17] + # FIXME: Use the code generator in order to print the .set directives + # instead of the instruction printer. + rdhwr $sp,$11 # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $sp, $11 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] rint.s $f2, $f4 # CHECK: rint.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9a] rint.d $f2, $f4 # CHECK: rint.d $f2, $f4 # encoding: [0x46,0x20,0x20,0x9a] class.s $f2, $f4 # CHECK: class.s $f2, $f4 # encoding: [0x46,0x00,0x20,0x9b] @@ -171,3 +186,15 @@ sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] + teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] + tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] + tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] + tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] + tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] + tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32] + tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] + tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] + tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] + tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] + tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] diff --git a/test/MC/Mips/mips_abi_flags_xx.s b/test/MC/Mips/mips_abi_flags_xx.s index 1d65e99..cd6c9de 100644 --- a/test/MC/Mips/mips_abi_flags_xx.s +++ b/test/MC/Mips/mips_abi_flags_xx.s @@ -3,32 +3,40 @@ # # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \ # RUN: llvm-readobj -sections -section-data -section-relocations - | \ -# RUN: FileCheck %s -check-prefix=CHECK-OBJ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-R1 + +# RUN: llvm-mc /dev/null -arch=mips -mcpu=mips32 -mattr=fpxx -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-R1 + +# RUN: llvm-mc /dev/null -arch=mips -mcpu=mips32r6 -mattr=fpxx -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ -check-prefix=CHECK-OBJ-R6 # CHECK-ASM: .module fp=xx # Checking if the Mips.abiflags were correctly emitted. -# CHECK-OBJ: Section { -# CHECK-OBJ: Index: 5 -# CHECK-OBJ: Name: .MIPS.abiflags (12) -# CHECK-OBJ: Type: (0x7000002A) -# CHECK-OBJ: Flags [ (0x2) -# CHECK-OBJ: SHF_ALLOC (0x2) -# CHECK-OBJ: ] -# CHECK-OBJ: Address: 0x0 -# CHECK-OBJ: Offset: 0x50 -# CHECK-OBJ: Size: 24 -# CHECK-OBJ: Link: 0 -# CHECK-OBJ: Info: 0 -# CHECK-OBJ: AddressAlignment: 8 -# CHECK-OBJ: EntrySize: 0 -# CHECK-OBJ: Relocations [ -# CHECK-OBJ: ] -# CHECK-OBJ: SectionData ( -# CHECK-OBJ: 0000: 00002001 01010005 00000000 00000000 |.. .............| -# CHECK-OBJ: 0010: 00000000 00000000 |........| -# CHECK-OBJ: ) -# CHECK-OBJ: } +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ-LABEL: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: SHT_MIPS_ABIFLAGS (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 24 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ-R1: 0000: 00002001 01010005 00000000 00000000 |.. .............| +# CHECK-OBJ-R6: 0000: 00002006 01010005 00000000 00000000 |.. .............| +# CHECK-OBJ: 0010: 00000001 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ-LABEL: } .module fp=xx diff --git a/test/MC/Mips/mips_abi_flags_xx_set.s b/test/MC/Mips/mips_abi_flags_xx_set.s index 56f19d3..a548972 100644 --- a/test/MC/Mips/mips_abi_flags_xx_set.s +++ b/test/MC/Mips/mips_abi_flags_xx_set.s @@ -9,27 +9,26 @@ # CHECK-ASM: .set fp=64 # Checking if the Mips.abiflags were correctly emitted. -# CHECK-OBJ: Section { -# CHECK-OBJ: Index: 5 -# CHECK-OBJ: Name: .MIPS.abiflags (12) -# CHECK-OBJ: Type: (0x7000002A) -# CHECK-OBJ: Flags [ (0x2) -# CHECK-OBJ: SHF_ALLOC (0x2) -# CHECK-OBJ: ] -# CHECK-OBJ: Address: 0x0 -# CHECK-OBJ: Offset: 0x50 -# CHECK-OBJ: Size: 24 -# CHECK-OBJ: Link: 0 -# CHECK-OBJ: Info: 0 -# CHECK-OBJ: AddressAlignment: 8 -# CHECK-OBJ: EntrySize: 0 -# CHECK-OBJ: Relocations [ -# CHECK-OBJ: ] -# CHECK-OBJ: SectionData ( -# CHECK-OBJ: 0000: 00002001 01010005 00000000 00000000 |.. .............| -# CHECK-OBJ: 0010: 00000000 00000000 |........| -# CHECK-OBJ: ) -# CHECK-OBJ: } +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ-LABEL: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: SHT_MIPS_ABIFLAGS (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 24 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00002001 01010005 00000000 00000000 |.. .............| +# CHECK-OBJ: 0010: 00000001 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ-LABEL: } .module fp=xx .set fp=64 diff --git a/test/MC/Mips/mips_directives_bad.s b/test/MC/Mips/mips_directives_bad.s index c823cac..a4512b5 100644 --- a/test/MC/Mips/mips_directives_bad.s +++ b/test/MC/Mips/mips_directives_bad.s @@ -2,7 +2,7 @@ # RUN: not llvm-mc -triple mips-unknown-unknown %s 2>&1 | FileCheck %s .abicalls should have no operands -# CHECK: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token in directive +# CHECK: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token, expected end of statement # CHECK-NEXT: .abicalls should have no operands # CHECK-NEXT: ^ @@ -12,48 +12,48 @@ # Blank option operand .option -# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token in .option directive +# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token, expected identifier # CHECK-NEXT: .option # CHECK-NEXT: ^ # Numeric option operand .option 2 -# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token in .option directive +# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token, expected identifier # CHECK-NEXT: .option 2 # CHECK-NEXT: ^ # Register option operand .option $2 -# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token in .option directive +# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token, expected identifier # CHECK-NEXT: .option $2 # CHECK-NEXT: ^ .option WithBadOption -# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: warning: unknown option in .option directive +# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: warning: unknown option, expected 'pic0' or 'pic2' # CHECK-NEXT: .option WithBadOption # CHECK-NEXT: ^ .option pic0, -# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token in .option pic0 directive +# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token, expected end of statement # CHECK-NEXT: .option pic0, # CHECK-NEXT: ^ .option pic0,pic2 -# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token in .option pic0 directive +# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token, expected end of statement # CHECK-NEXT: .option pic0,pic2 # CHECK-NEXT: ^ .option pic0 pic2 -# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token in .option pic0 directive +# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token, expected end of statement # CHECK-NEXT: .option pic0 pic2 # CHECK-NEXT: ^ .option pic2, -# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token in .option pic2 directive +# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token, expected end of statement # CHECK-NEXT: .option pic2, # CHECK-NEXT: ^ .option pic2 pic3 -# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token in .option pic2 directive +# CHECK-NEXT: :{{[0-9]+}}:{{[0-9]+}}: error: unexpected token, expected end of statement # CHECK-NEXT: .option pic2 pic3 # CHECK-NEXT: ^ diff --git a/test/MC/Mips/msa/abiflags.s b/test/MC/Mips/msa/abiflags.s index 83b83cc..136c035 100644 --- a/test/MC/Mips/msa/abiflags.s +++ b/test/MC/Mips/msa/abiflags.s @@ -9,27 +9,26 @@ # CHECK-ASM: .set fp=64 # Checking if the Mips.abiflags were correctly emitted. -# CHECK-OBJ: Section { -# CHECK-OBJ: Index: 5 -# CHECK-OBJ: Name: .MIPS.abiflags (12) -# CHECK-OBJ: Type: (0x7000002A) -# CHECK-OBJ: Flags [ (0x2) -# CHECK-OBJ: SHF_ALLOC (0x2) -# CHECK-OBJ: ] -# CHECK-OBJ: Address: 0x0 -# CHECK-OBJ: Offset: 0x50 -# CHECK-OBJ: Size: 24 -# CHECK-OBJ: Link: 0 -# CHECK-OBJ: Info: 0 -# CHECK-OBJ: AddressAlignment: 8 -# CHECK-OBJ: EntrySize: 0 -# CHECK-OBJ: Relocations [ -# CHECK-OBJ: ] -# CHECK-OBJ: SectionData ( -# CHECK-OBJ: 0000: 00002002 01030001 00000000 00000200 |.. .............| -# CHECK-OBJ: 0010: 00000000 00000000 |........| -# CHECK-OBJ: ) -# CHECK-OBJ: } +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ-LABEL: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: SHT_MIPS_ABIFLAGS (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 24 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00002002 01030001 00000000 00000200 |.. .............| +# CHECK-OBJ: 0010: 00000001 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ-LABEL: } .module fp=32 .set fp=64 diff --git a/test/MC/Mips/msa/set-msa-directive-bad.s b/test/MC/Mips/msa/set-msa-directive-bad.s new file mode 100644 index 0000000..02cb9a6 --- /dev/null +++ b/test/MC/Mips/msa/set-msa-directive-bad.s @@ -0,0 +1,11 @@ +# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r2 2>%t1 +# RUN: FileCheck %s < %t1 + + .set nomsa + addvi.b $w14, $w12, 14 # CHECK: error: instruction requires a CPU feature not currently enabled + + .set msa + addvi.h $w26, $w17, 4 + + .set nomsa + addvi.w $w19, $w13, 11 # CHECK: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/msa/set-msa-directive.s b/test/MC/Mips/msa/set-msa-directive.s new file mode 100644 index 0000000..461ddba --- /dev/null +++ b/test/MC/Mips/msa/set-msa-directive.s @@ -0,0 +1,22 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 | FileCheck %s + +# CHECK: .set msa +# CHECK: addvi.b $w14, $w12, 14 +# CHECK: addvi.h $w26, $w17, 4 +# CHECK: addvi.w $w19, $w13, 11 +# CHECK: addvi.d $w16, $w19, 7 +# CHECK: subvi.b $w14, $w12, 14 +# CHECK: subvi.h $w26, $w17, 4 +# CHECK: subvi.w $w19, $w13, 11 +# CHECK: subvi.d $w16, $w19, 7 + + .set msa + addvi.b $w14, $w12, 14 + addvi.h $w26, $w17, 4 + addvi.w $w19, $w13, 11 + addvi.d $w16, $w19, 7 + + subvi.b $w14, $w12, 14 + subvi.h $w26, $w17, 4 + subvi.w $w19, $w13, 11 + subvi.d $w16, $w19, 7 diff --git a/test/MC/Mips/nacl-mask.s b/test/MC/Mips/nacl-mask.s index 22286ac..c776460 100644 --- a/test/MC/Mips/nacl-mask.s +++ b/test/MC/Mips/nacl-mask.s @@ -252,10 +252,10 @@ test5: jalr $t9 addiu $4, $zero, 5 -# CHECK-LABEL: test5: +# CHECK: nop # CHECK-NEXT: nop -# CHECK-NEXT: nop +# CHECK-LABEL: test5: # CHECK-NEXT: jal # CHECK-NEXT: addiu $4, $zero, 1 @@ -301,10 +301,11 @@ test6: jalr $t9 sw $sp, 0($sp) -# CHECK-LABEL: test6: + +# CHECK: nop # CHECK-NEXT: nop -# CHECK-NEXT: nop +# CHECK-LABEL: test6: # CHECK-NEXT: jal # CHECK-NEXT: sw $4, 0($sp) diff --git a/test/MC/Mips/nooddspreg-cmdarg.s b/test/MC/Mips/nooddspreg-cmdarg.s index 826db12..52b040e 100644 --- a/test/MC/Mips/nooddspreg-cmdarg.s +++ b/test/MC/Mips/nooddspreg-cmdarg.s @@ -14,27 +14,26 @@ # CHECK-ASM-NOT: .module nooddspreg # Checking if the Mips.abiflags were correctly emitted. -# CHECK-OBJ: Section { -# CHECK-OBJ: Index: 5 -# CHECK-OBJ: Name: .MIPS.abiflags (12) -# CHECK-OBJ: Type: (0x7000002A) -# CHECK-OBJ: Flags [ (0x2) -# CHECK-OBJ: SHF_ALLOC (0x2) -# CHECK-OBJ: ] -# CHECK-OBJ: Address: 0x0 -# CHECK-OBJ: Offset: 0x50 -# CHECK-OBJ: Size: 24 -# CHECK-OBJ: Link: 0 -# CHECK-OBJ: Info: 0 -# CHECK-OBJ: AddressAlignment: 8 -# CHECK-OBJ: EntrySize: 0 -# CHECK-OBJ: Relocations [ -# CHECK-OBJ: ] -# CHECK-OBJ: SectionData ( -# CHECK-OBJ: 0000: 00002001 01020007 00000000 00000000 |.. .............| -# CHECK-OBJ: 0010: 00000000 00000000 |........| -# CHECK-OBJ: ) -# CHECK-OBJ: } +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ-LABEL: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: SHT_MIPS_ABIFLAGS (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 24 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00002001 01020007 00000000 00000000 |.. .............| +# CHECK-OBJ: 0010: 00000000 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ-LABEL: } # INVALID: ERROR: -mno-odd-spreg requires the O32 ABI diff --git a/test/MC/Mips/nooddspreg.s b/test/MC/Mips/nooddspreg.s index 5a283f5..f268ef4 100644 --- a/test/MC/Mips/nooddspreg.s +++ b/test/MC/Mips/nooddspreg.s @@ -14,27 +14,26 @@ # CHECK-ASM: .module nooddspreg # Checking if the Mips.abiflags were correctly emitted. -# CHECK-OBJ: Section { -# CHECK-OBJ: Index: 5 -# CHECK-OBJ: Name: .MIPS.abiflags (12) -# CHECK-OBJ: Type: (0x7000002A) -# CHECK-OBJ: Flags [ (0x2) -# CHECK-OBJ: SHF_ALLOC (0x2) -# CHECK-OBJ: ] -# CHECK-OBJ: Address: 0x0 -# CHECK-OBJ: Offset: 0x50 -# CHECK-OBJ: Size: 24 -# CHECK-OBJ: Link: 0 -# CHECK-OBJ: Info: 0 -# CHECK-OBJ: AddressAlignment: 8 -# CHECK-OBJ: EntrySize: 0 -# CHECK-OBJ: Relocations [ -# CHECK-OBJ: ] -# CHECK-OBJ: SectionData ( -# CHECK-OBJ: 0000: 00002001 01020007 00000000 00000000 |.. .............| -# CHECK-OBJ: 0010: 00000000 00000000 |........| -# CHECK-OBJ: ) -# CHECK-OBJ: } +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ-LABEL: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: SHT_MIPS_ABIFLAGS (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 24 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00002001 01020007 00000000 00000000 |.. .............| +# CHECK-OBJ: 0010: 00000000 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ-LABEL: } # INVALID: '.module nooddspreg' requires the O32 ABI diff --git a/test/MC/Mips/octeon-instructions.s b/test/MC/Mips/octeon-instructions.s index b7c89b4..2922744 100644 --- a/test/MC/Mips/octeon-instructions.s +++ b/test/MC/Mips/octeon-instructions.s @@ -35,6 +35,10 @@ # CHECK: sne $23, $23, $20 # encoding: [0x72,0xf4,0xb8,0x2b] # CHECK: snei $4, $16, -313 # encoding: [0x72,0x04,0xb1,0xef] # CHECK: snei $26, $26, 511 # encoding: [0x73,0x5a,0x7f,0xef] +# CHECK: sync 2 # encoding: [0x00,0x00,0x00,0x8f] +# CHECK: sync 6 # encoding: [0x00,0x00,0x01,0x8f] +# CHECK: sync 4 # encoding: [0x00,0x00,0x01,0x0f] +# CHECK: sync 5 # encoding: [0x00,0x00,0x01,0x4f] # CHECK: v3mulu $21, $10, $21 # encoding: [0x71,0x55,0xa8,0x11] # CHECK: v3mulu $20, $20, $10 # encoding: [0x72,0x8a,0xa0,0x11] # CHECK: vmm0 $3, $19, $16 # encoding: [0x72,0x70,0x18,0x10] @@ -77,6 +81,10 @@ sne $23, $20 snei $4, $16, -313 snei $26, 511 + synciobdma + syncs + syncw + syncws v3mulu $21, $10, $21 v3mulu $20, $10 vmm0 $3, $19, $16 diff --git a/test/MC/Mips/oddspreg.s b/test/MC/Mips/oddspreg.s index f5aa9c0..32ba9e0 100644 --- a/test/MC/Mips/oddspreg.s +++ b/test/MC/Mips/oddspreg.s @@ -15,38 +15,51 @@ # RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 | \ # RUN: FileCheck %s -check-prefix=CHECK-ASM # -# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -filetype=obj -o - | \ +# Repeat the -filetype=obj tests but this time use an empty assembly file. The +# output should be unchanged. +# RUN: llvm-mc /dev/null -arch=mips64 -mcpu=mips64 -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ-ALL -check-prefix=CHECK-OBJ-N64 + +# RUN: llvm-mc /dev/null -arch=mips -mcpu=mips32 -mattr=+fp64 -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ-ALL -check-prefix=CHECK-OBJ-O32 +# +# RUN: llvm-mc /dev/null -arch=mips64 -mcpu=mips64 -mattr=-n64,+n32 -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ-ALL -check-prefix=CHECK-OBJ-N32 + +# RUN: llvm-mc /dev/null -arch=mips64 -mcpu=mips64 -filetype=obj -o - | \ # RUN: llvm-readobj -sections -section-data -section-relocations - | \ # RUN: FileCheck %s -check-prefix=CHECK-OBJ-ALL -check-prefix=CHECK-OBJ-N64 # CHECK-ASM: .module oddspreg # Checking if the Mips.abiflags were correctly emitted. -# CHECK-OBJ-ALL: Section { -# CHECK-OBJ-ALL: Index: 5 -# CHECK-OBJ-ALL: Name: .MIPS.abiflags ({{[0-9]+}}) -# CHECK-OBJ-ALL: Type: (0x7000002A) -# CHECK-OBJ-ALL: Flags [ (0x2) -# CHECK-OBJ-ALL: SHF_ALLOC (0x2) -# CHECK-OBJ-ALL: ] -# CHECK-OBJ-ALL: Address: 0x0 -# CHECK-OBJ-ALL: Offset: 0x{{[0-9A-F]+}} -# CHECK-OBJ-ALL: Size: 24 -# CHECK-OBJ-ALL: Link: 0 -# CHECK-OBJ-ALL: Info: 0 -# CHECK-OBJ-ALL: AddressAlignment: 8 -# CHECK-OBJ-ALL: EntrySize: 0 -# CHECK-OBJ-ALL: Relocations [ -# CHECK-OBJ-ALL: ] -# CHECK-OBJ-ALL: SectionData ( -# CHECK-OBJ-O32: 0000: 00002001 01020006 00000000 00000000 |.. .............| -# CHECK-OBJ-O32: 0010: 00000001 00000000 |........| -# CHECK-OBJ-N32: 0000: 00004001 02020001 00000000 00000000 |..@.............| -# CHECK-OBJ-N32: 0010: 00000001 00000000 |........| -# CHECK-OBJ-N64: 0000: 00004001 02020001 00000000 00000000 |..@.............| -# CHECK-OBJ-N64: 0010: 00000001 00000000 |........| -# CHECK-OBJ-ALL: ) -# CHECK-OBJ-ALL: } +# CHECK-OBJ-ALL: Section { +# CHECK-OBJ-ALL: Index: 5 +# CHECK-OBJ-ALL-LABEL: Name: .MIPS.abiflags ({{[0-9]+}}) +# CHECK-OBJ-ALL: Type: SHT_MIPS_ABIFLAGS (0x7000002A) +# CHECK-OBJ-ALL: Flags [ (0x2) +# CHECK-OBJ-ALL: SHF_ALLOC (0x2) +# CHECK-OBJ-ALL: ] +# CHECK-OBJ-ALL: Address: 0x0 +# CHECK-OBJ-ALL: Size: 24 +# CHECK-OBJ-ALL: Link: 0 +# CHECK-OBJ-ALL: Info: 0 +# CHECK-OBJ-ALL: AddressAlignment: 8 +# CHECK-OBJ-ALL: EntrySize: 24 +# CHECK-OBJ-ALL: Relocations [ +# CHECK-OBJ-ALL: ] +# CHECK-OBJ-ALL: SectionData ( +# CHECK-OBJ-O32: 0000: 00002001 01020006 00000000 00000000 |.. .............| +# CHECK-OBJ-O32: 0010: 00000001 00000000 |........| +# CHECK-OBJ-N32: 0000: 00004001 02020001 00000000 00000000 |..@.............| +# CHECK-OBJ-N32: 0010: 00000001 00000000 |........| +# CHECK-OBJ-N64: 0000: 00004001 02020001 00000000 00000000 |..@.............| +# CHECK-OBJ-N64: 0010: 00000001 00000000 |........| +# CHECK-OBJ-ALL: ) +# CHECK-OBJ-ALL-LABEL: } .module oddspreg add.s $f3, $f1, $f5 diff --git a/test/MC/Mips/set-arch.s b/test/MC/Mips/set-arch.s new file mode 100644 index 0000000..6267468 --- /dev/null +++ b/test/MC/Mips/set-arch.s @@ -0,0 +1,55 @@ +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32 | \ +# RUN: FileCheck %s + + .text + .set arch=mips1 + add $2, $2, $2 + .set arch=mips2 + ll $2, -2($2) + .set arch=mips3 + dadd $2, $2, $2 + .set arch=mips4 + ldxc1 $f8, $2($4) + .set arch=mips5 + luxc1 $f19, $2($4) + .set arch=mips32 + clo $2, $2 + .set arch=mips32r2 + rotr $2, $2, 15 + .set arch=mips32r6 + mod $2, $4, $6 + .set arch=mips64 + daddi $2, $2, 10 + .set arch=mips64r2 + drotr32 $1, $14, 15 + .set arch=mips64r6 + mod $2, $4, $6 + .set arch=cnmips + .set arch=r4000 + dadd $2, $2, $2 + +# CHECK: .set arch=mips1 +# CHECK: add $2, $2, $2 +# CHECK: .set arch=mips2 +# CHECK: ll $2, -2($2) +# CHECK: .set arch=mips3 +# CHECK: dadd $2, $2, $2 +# CHECK: .set arch=mips4 +# CHECK: ldxc1 $f8, $2($4) +# CHECK: .set arch=mips5 +# CHECK: luxc1 $f19, $2($4) +# CHECK: .set arch=mips32 +# CHECK: clo $2, $2 +# CHECK: .set arch=mips32r2 +# CHECK: rotr $2, $2, 15 +# CHECK: .set arch=mips32r6 +# CHECK: mod $2, $4, $6 +# CHECK: .set arch=mips64 +# CHECK: daddi $2, $2, 10 +# CHECK: .set arch=mips64r2 +# CHECK: drotr32 $1, $14, 15 +# CHECK: .set arch=mips64r6 +# CHECK: mod $2, $4, $6 +# CHECK: .set arch=cnmips +# CHECK: .set arch=r4000 +# CHECK: dadd $2, $2, $2 diff --git a/test/MC/Mips/set-at-directive-explicit-at.s b/test/MC/Mips/set-at-directive-explicit-at.s index 1bd26ff..797a2b7 100644 --- a/test/MC/Mips/set-at-directive-explicit-at.s +++ b/test/MC/Mips/set-at-directive-explicit-at.s @@ -7,15 +7,15 @@ .text foo: # CHECK: jr $1 # encoding: [0x08,0x00,0x20,0x00] -# WARNINGS: :[[@LINE+2]]:11: warning: Used $at without ".set noat" +# WARNINGS: :[[@LINE+2]]:11: warning: used $at without ".set noat" .set at=$1 jr $at # CHECK: jr $1 # encoding: [0x08,0x00,0x20,0x00] -# WARNINGS: :[[@LINE+2]]:11: warning: Used $at without ".set noat" +# WARNINGS: :[[@LINE+2]]:11: warning: used $at without ".set noat" .set at=$1 jr $1 -# WARNINGS-NOT: warning: Used $at without ".set noat" +# WARNINGS-NOT: warning: used $at without ".set noat" # CHECK: jr $1 # encoding: [0x08,0x00,0x20,0x00] .set at=$2 @@ -31,12 +31,12 @@ foo: jr $at # CHECK: jr $16 # encoding: [0x08,0x00,0x00,0x02] -# WARNINGS: :[[@LINE+2]]:11: warning: Used $16 with ".set at=$16" +# WARNINGS: :[[@LINE+2]]:11: warning: used $16 with ".set at=$16" .set at=$16 jr $s0 # CHECK: jr $16 # encoding: [0x08,0x00,0x00,0x02] -# WARNINGS: :[[@LINE+2]]:11: warning: Used $16 with ".set at=$16" +# WARNINGS: :[[@LINE+2]]:11: warning: used $16 with ".set at=$16" .set at=$16 jr $16 # WARNINGS-NOT: warning diff --git a/test/MC/Mips/set-mips-directives-bad.s b/test/MC/Mips/set-mips-directives-bad.s new file mode 100644 index 0000000..6726987 --- /dev/null +++ b/test/MC/Mips/set-mips-directives-bad.s @@ -0,0 +1,30 @@ +# RUN: not llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips1 2>%t1 +# RUN: FileCheck %s < %t1 + +# FIXME: At the moment we emit the wrong error message if we try to assemble the +# ll instruction using an unsupported architecture so we just check for "error" +# and ignore the rest of the message. + + .text + .set noreorder + .set mips1 + ll $2,-2($2) # CHECK: error: + .set mips2 + dadd $2,$2,$2 # CHECK: error: instruction requires a CPU feature not currently enabled + .set mips3 + ldxc1 $f8,$2($4) # CHECK: error: instruction requires a CPU feature not currently enabled + .set mips4 + luxc1 $f19,$2($4) # CHECK: error: instruction requires a CPU feature not currently enabled + .set mips5 + clo $2,$2 # CHECK: error: instruction requires a CPU feature not currently enabled + .set mips32 + rotr $2,15 # CHECK: error: instruction requires a CPU feature not currently enabled + .set mips32r2 + mod $2, $4, $6 # CHECK: error:instruction requires a CPU feature not currently enabled + .set mips32r6 + daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled + .set mips64 + drotr32 $1,$14,15 # CHECK: error: instruction requires a CPU feature not currently enabled + .set mips64r2 + mod $2, $4, $6 # CHECK: error: instruction requires a CPU feature not currently enabled + diff --git a/test/MC/Mips/set-mips-directives.s b/test/MC/Mips/set-mips-directives.s new file mode 100644 index 0000000..96c2308 --- /dev/null +++ b/test/MC/Mips/set-mips-directives.s @@ -0,0 +1,51 @@ +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips1 | \ +# RUN: FileCheck %s + + .text + .set noreorder + .set mips1 + add $2, $2, $2 + .set mips2 + ll $2,-2($2) + .set mips3 + dadd $2,$2,$2 + .set mips4 + ldxc1 $f8,$2($4) + .set mips5 + luxc1 $f19,$2($4) + .set mips32 + clo $2,$2 + .set mips32r2 + rotr $2,15 + .set mips32r6 + mod $2, $4, $6 + .set mips64 + daddi $2, $2, 10 + .set mips64r2 + drotr32 $1,$14,15 + .set mips64r6 + mod $2, $4, $6 + +# CHECK: .set noreorder +# CHECK: .set mips1 +# CHECK: add $2, $2, $2 +# CHECK: .set mips2 +# CHECK: ll $2, -2($2) +# CHECK: .set mips3 +# CHECK: dadd $2, $2, $2 +# CHECK: .set mips4 +# CHECK: ldxc1 $f8, $2($4) +# CHECK: .set mips5 +# CHECK: luxc1 $f19, $2($4) +# CHECK: .set mips32 +# CHECK: clo $2, $2 +# CHECK: .set mips32r2 +# CHECK: rotr $2, $2, 15 +# CHECK: .set mips32r6 +# CHECK: mod $2, $4, $6 +# CHECK: .set mips64 +# CHECK: daddi $2, $2, 10 +# CHECK: .set mips64r2 +# CHECK: drotr32 $1, $14, 15 +# CHECK: .set mips64r6 +# CHECK: mod $2, $4, $6 diff --git a/test/MC/Mips/set-mips0-directive.s b/test/MC/Mips/set-mips0-directive.s new file mode 100644 index 0000000..5cb75bb --- /dev/null +++ b/test/MC/Mips/set-mips0-directive.s @@ -0,0 +1,27 @@ +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 | \ +# RUN: FileCheck %s + + .text + rotr $7, $7, 22 + + .set mips32r6 + mod $2, $4, $6 + .set mips0 + rotr $2, $2, 15 + + .set mips3 + dadd $4, $4, $4 + .set mips0 + rotr $3, $3, 19 + +# CHECK: rotr $7, $7, 22 + +# CHECK: .set mips32r6 +# CHECK: mod $2, $4, $6 +# CHECK: .set mips0 +# CHECK: rotr $2, $2, 15 + +# CHECK: .set mips3 +# CHECK: dadd $4, $4, $4 +# CHECK: .set mips0 +# CHECK: rotr $3, $3, 19 diff --git a/test/MC/Mips/set-mips16-directive.s b/test/MC/Mips/set-mips16-directive.s new file mode 100644 index 0000000..cf8090e --- /dev/null +++ b/test/MC/Mips/set-mips16-directive.s @@ -0,0 +1,10 @@ +# RUN: llvm-mc %s -arch=mips | FileCheck %s +# FIXME: Update this test when we have a more mature implementation of Mips16 in the IAS. + +.text +.set mips16 +.set nomips16 + +# CHECK: .text +# CHECK: .set mips16 +# CHECK: .set nomips16 diff --git a/test/MC/Mips/set-nodsp.s b/test/MC/Mips/set-nodsp.s new file mode 100644 index 0000000..f98cefb --- /dev/null +++ b/test/MC/Mips/set-nodsp.s @@ -0,0 +1,12 @@ +# RUN: not llvm-mc %s -mcpu=mips32 -mattr=+dsp -triple mips-unknown-linux 2>%t1 +# RUN: FileCheck %s < %t1 + + lbux $7, $10($11) + + .set nodsp + lbux $6, $10($11) + # CHECK: error: instruction requires a CPU feature not currently enabled + + .set dsp + lbux $5, $10($11) + # CHECK-NOT: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/set-push-pop-directives-bad.s b/test/MC/Mips/set-push-pop-directives-bad.s new file mode 100644 index 0000000..53d8b23 --- /dev/null +++ b/test/MC/Mips/set-push-pop-directives-bad.s @@ -0,0 +1,14 @@ +# RUN: not llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 2>%t1 +# RUN: FileCheck %s < %t1 + + .text + .set pop +# CHECK: :[[@LINE-1]]:14: error: .set pop with no .set push + .set push + .set pop + .set pop +# CHECK: :[[@LINE-1]]:14: error: .set pop with no .set push + .set push foo +# CHECK: :[[@LINE-1]]:19: error: unexpected token, expected end of statement + .set pop bar +# CHECK: :[[@LINE-1]]:18: error: unexpected token, expected end of statement diff --git a/test/MC/Mips/set-push-pop-directives.s b/test/MC/Mips/set-push-pop-directives.s new file mode 100644 index 0000000..5f55b7c --- /dev/null +++ b/test/MC/Mips/set-push-pop-directives.s @@ -0,0 +1,53 @@ +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+msa | \ +# RUN: FileCheck %s +# .set push creates a copy of the current environment. +# .set pop restores the previous environment. +# FIXME: Also test resetting of .set macro/nomacro option. + + .text + # The first environment on the stack (with initial values). + lw $1, 65536($1) + b 1336 + addvi.b $w15, $w13, 18 + + # Create a new environment. + .set push + .set at=$ra # Test the ATReg option. + lw $1, 65536($1) + .set noreorder # Test the Reorder option. + b 1336 + .set nomsa # Test the Features option (ASE). + .set mips32r6 # Test the Features option (ISA). + mod $2, $4, $6 + + # Switch back to the first environment. + .set pop + lw $1, 65536($1) + b 1336 + addvi.b $w15, $w13, 18 + +# CHECK: lui $1, 1 +# CHECK: addu $1, $1, $1 +# CHECK: lw $1, 0($1) +# CHECK: b 1336 +# CHECK: nop +# CHECK: addvi.b $w15, $w13, 18 + +# CHECK: .set push +# CHECK: lui $ra, 1 +# CHECK: addu $ra, $ra, $1 +# CHECK: lw $1, 0($ra) +# CHECK: .set noreorder +# CHECK: b 1336 +# CHECK-NOT: nop +# CHECK: .set nomsa +# CHECK: .set mips32r6 +# CHECK: mod $2, $4, $6 + +# CHECK: .set pop +# CHECK: lui $1, 1 +# CHECK: addu $1, $1, $1 +# CHECK: lw $1, 0($1) +# CHECK: b 1336 +# CHECK: nop +# CHECK: addvi.b $w15, $w13, 18 diff --git a/test/MC/Mips/unaligned-nops.s b/test/MC/Mips/unaligned-nops.s new file mode 100644 index 0000000..ebbbb40 --- /dev/null +++ b/test/MC/Mips/unaligned-nops.s @@ -0,0 +1,4 @@ +# RUN: llvm-mc -filetype=obj -triple=mipsel %s -o %t +.byte 1 +.p2align 2 +foo: |