diff options
Diffstat (limited to 'test/MC/Disassembler/ARM')
69 files changed, 1543 insertions, 595 deletions
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 98daaa7..acc2d9f 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -362,7 +362,3 @@ # CHECK: ldmgt sp!, {r9} 0x00 0x02 0xbd 0xc8 - -# CHECK: cdp2 p10, #0, c6, c12, c0, #7 -0xe0 0x6a 0x0c 0xfe - diff --git a/test/MC/Disassembler/ARM/invalid-BFI-arm.txt b/test/MC/Disassembler/ARM/invalid-BFI-arm.txt deleted file mode 100644 index f7acce9..0000000 --- a/test/MC/Disassembler/ARM/invalid-BFI-arm.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 1: 0| -# ------------------------------------------------------------------------------------------------- -# -# if d == 15 then UNPREDICTABLE; -0x16 0xf0 0xcf 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt deleted file mode 100644 index 356c376..0000000 --- a/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# if cond = '1110' then UNDEFINED -0x6f 0xde diff --git a/test/MC/Disassembler/ARM/invalid-CPS-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS-arm.txt deleted file mode 100644 index e447eb6..0000000 --- a/test/MC/Disassembler/ARM/invalid-CPS-arm.txt +++ /dev/null @@ -1,9 +0,0 @@ -# CPS: various encodings that are ambiguous with other instructions - -# RUN: echo "0x9f 0xff 0x4e 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x80 0x80 0x2c 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0xce 0x3f 0x28 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x80 0x00 0x20 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0xa0 0x00 0x00 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt deleted file mode 100644 index bc8b7e1..0000000 --- a/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# invalid imod value (0b01) -0xc0 0x67 0x4 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt deleted file mode 100644 index 842a52b..0000000 --- a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" - -# invalid (imod, M, iflags) combination -0x93 0x00 0x02 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt b/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt deleted file mode 100644 index 8396156..0000000 --- a/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt +++ /dev/null @@ -1,16 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=1908 Name=t2DMB Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 0: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| -# ------------------------------------------------------------------------------------------------- -# -# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST. -# Reject invalid encodings. -# -# See also A8.6.42 DSB -# All other encodings of option are reserved. It is IMPLEMENTATION DEFINED whether options -# other than SY are implemented. All unsupported and reserved options must execute as a full -# system DSB operation, but software must not rely on this behavior. -0xbf 0xf3 0x51 0x8f diff --git a/test/MC/Disassembler/ARM/invalid-DSB-arm.txt b/test/MC/Disassembler/ARM/invalid-DSB-arm.txt deleted file mode 100644 index 2c6e6a7..0000000 --- a/test/MC/Disassembler/ARM/invalid-DSB-arm.txt +++ /dev/null @@ -1,16 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=102 Name=DSB Format=ARM_FORMAT_MISCFRM(26) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 1: 0: 1| 0: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST. -# Reject invalid encodings. -# -# See also A8.6.42 DSB -# All other encodings of option are reserved. It is IMPLEMENTATION DEFINED whether options -# other than SY are implemented. All unsupported and reserved options must execute as a full -# system DSB operation, but software must not rely on this behavior. -0x40 0xf0 0x7f 0xf5 diff --git a/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt b/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt deleted file mode 100644 index 4297c016..0000000 --- a/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt +++ /dev/null @@ -1,5 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" - -# CBZ / CBNZ not allowed in IT block. - -0xdb 0xbf 0x42 0xbb diff --git a/test/MC/Disassembler/ARM/invalid-IT-thumb.txt b/test/MC/Disassembler/ARM/invalid-IT-thumb.txt deleted file mode 100644 index 1a8ff48..0000000 --- a/test/MC/Disassembler/ARM/invalid-IT-thumb.txt +++ /dev/null @@ -1,3 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown 2>&1 | grep "potentially undefined instruction encoding" - -0xff 0xbf 0x6b 0x80 0x00 0x75 diff --git a/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt b/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt deleted file mode 100644 index 6cff09e..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 0: 1| 1: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 1: 1| 0: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 0| -# ------------------------------------------------------------------------------------------------- -# -# The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined. -0x92 0xb4 0x1f 0xdc - diff --git a/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt b/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt deleted file mode 100644 index 7d8c492..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt +++ /dev/null @@ -1,5 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" - -# Writeback is not allowed is Rn is in the target register list. - -0xb4 0xe8 0x34 0x04 diff --git a/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt deleted file mode 100644 index 68d22de..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" - -# Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1| -# ------------------------------------------------------------------------------------------------- -# -# if wback && (n == 15 || n == t) then UNPREDICTABLE -0x05 0x70 0xd7 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt deleted file mode 100644 index 4df5309..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt +++ /dev/null @@ -1,13 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# A8.6.66 LDRD (immediate) -# if Rn = '1111' then SEE LDRD (literal) -# A8.6.67 LDRD (literal) -# Inst{21} = 0 -0xff 0xe9 0x0 0xeb diff --git a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt deleted file mode 100644 index ecab5a5..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# LDR_PRE/POST has encoding Inst{4} = 0. -0xde 0x69 0x18 0x46 diff --git a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt deleted file mode 100644 index 30cb727..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "potentially undefined instruction encoding" - -# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# if m == 15 then UNPREDICTABLE -0x8f 0x60 0xb7 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt deleted file mode 100644 index 7b7286a..0000000 --- a/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# LDR (register) has encoding Inst{4} = 0. -0xba 0xae 0x9f 0x57 diff --git a/test/MC/Disassembler/ARM/invalid-MCR-arm.txt b/test/MC/Disassembler/ARM/invalid-MCR-arm.txt deleted file mode 100644 index bb4b06c..0000000 --- a/test/MC/Disassembler/ARM/invalid-MCR-arm.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C -0x1b 0x1b 0xa0 0x2e diff --git a/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt deleted file mode 100644 index 528563a..0000000 --- a/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# if d == 15 then UNPREDICTABLE -0x00 0xf0 0x41 0xe3 diff --git a/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt deleted file mode 100644 index 41ec53f..0000000 --- a/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt +++ /dev/null @@ -1,13 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0| -# ------------------------------------------------------------------------------------------------- -# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. -# The instruction is UNPREDICTABLE, and is not a valid intruction. -# -# See also -# A8.6.97 MOV (register) -0x2 0xd0 0xbc 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt deleted file mode 100644 index e5f2a5e..0000000 --- a/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt +++ /dev/null @@ -1,9 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1| -# ------------------------------------------------------------------------------------------------- -# A8.6.89 LSL (register): Inst{7-4} = 0b0001 -0x93 0x42 0xa0 0xd1 diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt deleted file mode 100644 index 3f4c1e5..0000000 --- a/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt +++ /dev/null @@ -1,17 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| -# ------------------------------------------------------------------------------------------------- -# To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. -# The instruction is UNPREDICTABLE, and is not a valid intruction. -# -# See also -# A8.6.88 LSL (immediate) -# A8.6.98 MOV (shifted register), and -# I.1 Instruction encoding diagrams and pseudocode -0x2 0xd1 0xbc 0xf1 - - diff --git a/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt b/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt deleted file mode 100644 index c20ce54..0000000 --- a/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi 2>&1 | FileCheck %s - -# CHECK: invalid instruction encoding -0x00 0x1a 0x50 0xfc diff --git a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt b/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt deleted file mode 100644 index 901667a..0000000 --- a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt +++ /dev/null @@ -1,12 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate) -# The hints instructions have more specific encodings, so if mask == 0, -# we should reject this as an invalid instruction. -0xa7 0xf1 0x20 0x3 diff --git a/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt b/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt deleted file mode 100644 index 499aa86..0000000 --- a/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0| -# ------------------------------------------------------------------------------------------------- -# -# B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction -# A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction -0x32 0xb1 0x99 0xf8 diff --git a/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt b/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt deleted file mode 100644 index 7bc97d5..0000000 --- a/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 0| 0: 1: 1: 1| 0: 1: 0: 1| 0: 1: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# if d == 15 || n == 15 then UNPREDICTABLE; -0x5f 0x54 0xa7 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt b/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt deleted file mode 100644 index fe4f43a..0000000 --- a/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# A8.6.167 -# if d == 15 || n == 15 | m == 15 then UNPREDICTABLE -0x1b 0x68 0xf 0x97 diff --git a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt deleted file mode 100644 index bf9aac4..0000000 --- a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt +++ /dev/null @@ -1,17 +0,0 @@ -# Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1| -# ------------------------------------------------------------------------------------------------- -# Unknown format -# -# B6.1.10 SRS -# Inst{19-8} = 0xd05 -# Inst{7-5} = 0b000 -# RUN: echo "0x83 0x1c 0xc5 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# RUN: echo "0x00 0x00 0x20 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0xff 0xff 0xaf 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x13 0x00 0xa0 0xf8" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt deleted file mode 100644 index 3d5235d..0000000 --- a/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# if BitCount(registers) < 1 then UNPREDICTABLE -0x00 0xc7 diff --git a/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt b/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt deleted file mode 100644 index f67f38e..0000000 --- a/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1| -# ------------------------------------------------------------------------------------------------- -# -# A8.6.223 SXTB -# if d == 15 || m == 15 then UNPREDICTABLE; -0x75 0xf4 0xaf 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt b/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt deleted file mode 100644 index f57c48f..0000000 --- a/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# A8.6.244 UMAAL -# if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; -0x98 0xbf 0x4f 0xf0 diff --git a/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt b/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt deleted file mode 100644 index 113507c..0000000 --- a/test/MC/Disassembler/ARM/invalid-VCVT-arm.txt +++ /dev/null @@ -1,8 +0,0 @@ -# A8.8.307: VCVT (between floating-point and fixed-point, AdvSIMD) -# imm6=0b0xxxxx -> UNDEFINED - -# RUN: echo "0x1e 0xcf 0x92 0xf3" | llvm-mc -disassemble -triple armv7 2>&1 | FileCheck %s - -# RUN: echo "0x3e 0xcf 0x92 0xf3" | llvm-mc -disassemble -triple armv7 2>&1 | FileCheck %s - -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt b/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt deleted file mode 100644 index b76485e..0000000 --- a/test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt +++ /dev/null @@ -1,5 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7 2>&1 | grep "invalid instruction encoding" - -# invalid imm4 value (0b1xxx) -# A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED; -0x8f 0xf9 0xf7 0xf2 diff --git a/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt deleted file mode 100644 index 00b8526..0000000 --- a/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s - -# Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 1: 1: 0: 0| 0: 0: 1: 1| 1: 1: 0: 1| -# ------------------------------------------------------------------------------------------------- -# -# 'a' == 1 and data_size == 8 is invalid -0x3d 0x3c 0xa0 0xf4 -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt deleted file mode 100644 index 9bb0995..0000000 --- a/test/MC/Disassembler/ARM/invalid-VLD1LNd32_UPD-thumb.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s - -0xa0 0xf9 0x10 0x08 -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt deleted file mode 100644 index 58def05..0000000 --- a/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0| -# ------------------------------------------------------------------------------------------------- -# -# A8.6.315 VLD3 (single 3-element structure to all lanes) -# The a bit must be encoded as 0. -0xa2 0xf9 0x92 0x2e diff --git a/test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt deleted file mode 100644 index 84c98bf..0000000 --- a/test/MC/Disassembler/ARM/invalid-VLD4DUPd32_UPD-thumb.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s - -0xa0 0xf9 0xc0 0x0f -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt deleted file mode 100644 index 9024b09..0000000 --- a/test/MC/Disassembler/ARM/invalid-VLD4LNd32_UPD-thumb.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s - -0xa0 0xf9 0x30 0x0b -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt deleted file mode 100644 index 54fcadb..0000000 --- a/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# core registers out of range -0xa5 0xba 0x72 0xed diff --git a/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt b/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt deleted file mode 100644 index e363110..0000000 --- a/test/MC/Disassembler/ARM/invalid-VLDST-arm.txt +++ /dev/null @@ -1,62 +0,0 @@ -# VST1 multi-element, type == 0b0111, align == 0b10 -> undefined -# RUN: echo "0xaf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST1 multi-element, type == 0b0111, align == 0b11 -> undefined -# RUN: echo "0xbf 0xb7 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST1 multi-element, type == 0b1010, align == 0b11 -> undefined -# RUN: echo "0xbf 0x8a 0x03 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST1 multi-element, type == 0b0110, align == 0b10 -> undefined -# RUN: echo "0xaf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST1 multi-element, type == 0b0110, align == 0b11 -> undefined -# RUN: echo "0xbf 0xb6 0x07 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined -# RUN: echo "0x4f 0xa8 0x07 0xf7" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined -# RUN: echo "0x4f 0xa9 0x07 0xf7" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST3 multi-element, size = 0b11 -> undefined -# RUN: echo "0xbf 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST3 multi-element, align = 0b10 -> undefined -# RUN: echo "0x6f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST3 multi-element, align = 0b11 -> undefined -# RUN: echo "0x7f 0xa4 0x0b 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VST4 multi-element, size = 0b11 -> undefined -# RUN: echo "0xcf 0x50 0x03 0xf4" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VLD1 multi-element, type=0b1010 align=0b11 -# RUN: echo "0x24 0xf9 0xbf 0x8a" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# VLD1 multi-element type=0b0111 align=0b1x -# RUN: echo "0x24 0xf9 0xbf 0x87" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# VLD1 multi-element type=0b0010 align=0b1x -# RUN: echo "0x24 0xf9 0xbf 0x86" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# VLD2 multi-element size=0b11 -# RUN: echo "0x60 0xf9 0xcf 0x08" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# VLD2 multi-element type=0b1111 align=0b11 -# RUN: echo "0x60 0xf9 0xbf 0x08" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# VLD2 multi-element type=0b1001 align=0b11 -# RUN: echo "0x60 0xf9 0xbf 0x09" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# VLD3 multi-element size=0b11 -# RUN: echo "0x60 0xf9 0x7f 0x04" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# VLD3 multi-element align=0b1x -# RUN: echo "0x60 0xf9 0xcf 0x04" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# VLD4 multi-element size=0b11 -# RUN: echo "0x60 0xf9 0xcd 0x11" | llvm-mc -triple=thumbv7 -disassemble 2>&1 | FileCheck %s - -# CHECK: invalid instruction encoding - diff --git a/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt b/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt deleted file mode 100644 index 9d6cd5c..0000000 --- a/test/MC/Disassembler/ARM/invalid-VMOV-arm.txt +++ /dev/null @@ -1,7 +0,0 @@ -# VMOV cmode=0b1111 op=1 -# RUN: echo "0x70 0xef 0xc7 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# VMOV cmode=0b1111 op=1 -# RUN: echo "0x30 0x0f 0x80 0xf3" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s - -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt deleted file mode 100644 index e8e5d6f..0000000 --- a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s - -# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# Qm -> bit[0] == 0, otherwise UNDEFINED -0xdb 0xe0 0x40 0xf2 -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt deleted file mode 100644 index 9462812..0000000 --- a/test/MC/Disassembler/ARM/invalid-VST1LNd32_UPD-thumb.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s - -0x80 0xf9 0x10 0x08 -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt deleted file mode 100644 index 99da8ce..0000000 --- a/test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt +++ /dev/null @@ -1,13 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# A8.6.391 VST1 (multiple single elements) -# This encoding looks like: vst1.8 {d0,d1,d2}, [r0:128] -# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list> -# contains two or four registers. rdar://11220250 -0x00 0xf9 0x2f 0x06 diff --git a/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt deleted file mode 100644 index 497822a..0000000 --- a/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt +++ /dev/null @@ -1,18 +0,0 @@ -# Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# A8.6.393 VST2 (multiple 2-element structures) -# type == '1001' and align == '11' ==> UNDEFINED -# RUN: echo "0xb3 0x09 0x03 0xf4" | llvm-mc --disassemble -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s - -# size == '11' ==> UNDEFINED -# RUN: echo "0xc3 0x08 0x03 0xf4" | llvm-mc --disassemble -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s - -# type == '1000' and align == '11' ==> UNDEFINED -# RUN: echo "0xb3 0x08 0x03 0xf4" | llvm-mc --disassemble -triple=armv7-unknown-unknwon -mcpu=cortex-a8 2>&1 | FileCheck %s - -# CHECK: invalid instruction encoding - diff --git a/test/MC/Disassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt deleted file mode 100644 index f6e71bc..0000000 --- a/test/MC/Disassembler/ARM/invalid-VST4LNd32_UPD-thumb.txt +++ /dev/null @@ -1,4 +0,0 @@ -# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble < %s 2>&1 | FileCheck %s - -0x80 0xf9 0x30 0x0b -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-armv7.txt b/test/MC/Disassembler/ARM/invalid-armv7.txt new file mode 100644 index 0000000..be79326 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-armv7.txt @@ -0,0 +1,510 @@ +# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple armv7 2>&1 | FileCheck %s + +# This file is checking ARMv7 encodings which are globally invalid, usually due +# to the constraints of the instructions not being met. For example invalid +# combinations of registers. + + +#------------------------------------------------------------------------------ +# Undefined encodings for bfi +#------------------------------------------------------------------------------ + +# Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# if d == 15 then UNPREDICTABLE; +[0x16 0xf0 0xcf 0xe7] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x16 0xf0 0xcf 0xe7] + +#------------------------------------------------------------------------------ +# Undefined encodings for cdp2 +#------------------------------------------------------------------------------ + +[0xe0 0x6a 0x0c 0xfe] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xe0 0x6a 0x0c 0xfe] + + +#------------------------------------------------------------------------------ +# Undefined encodings for cps* +#------------------------------------------------------------------------------ + +# invalid imod value (0b01) +[0xc0 0x67 0x4 0xf1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xc0 0x67 0x4 0xf1] + +# invalid (imod, M, iflags) combination +[0x93 0x00 0x02 0xf1] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x93 0x00 0x02 0xf1] + +# CPS: various encodings that are ambiguous with other instructions +[0x9f 0xff 0x4e 0xf1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x9f 0xff 0x4e 0xf1] + +[0x80 0x80 0x2c 0xf1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x80 0x80 0x2c 0xf1] + +[0xce 0x3f 0x28 0xf1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xce 0x3f 0x28 0xf1] + +[0x80 0x00 0x20 0xf1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x80 0x00 0x20 0xf1] + +[0xa0 0x00 0x00 0xf1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xa0 0x00 0x00 0xf1] + + +#------------------------------------------------------------------------------ +# Undefined encoding space for hint instructions +#------------------------------------------------------------------------------ + +[0x05 0xf0 0x20 0xe3] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x05 0xf0 0x20 0xe3] + +[0x41 0xf0 0x20 0xe3] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x41 0xf0 0x20 0xe3] + +# FIXME: is it "dbg #14" or not???? +[0xfe 0xf0 0x20 0xe3] +# CHCK: invalid instruction encoding + + +#------------------------------------------------------------------------------ +# Undefined encodings for ldc +#------------------------------------------------------------------------------ + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 0: 1| 1: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 1: 1| 0: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined. + +[0x92 0xb4 0x1f 0xdc] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x92 0xb4 0x1f 0xdc] + + +#------------------------------------------------------------------------------ +# Undefined encodings for ldm +#------------------------------------------------------------------------------ + +# Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction +# A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction + +[0x32 0xb1 0x99 0xf8] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x32 0xb1 0x99 0xf8] + + +#------------------------------------------------------------------------------ +# Undefined encodings for ldr +#------------------------------------------------------------------------------ + +# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if m == 15 then UNPREDICTABLE + +[0x8f 0x60 0xb7 0xe7] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x8f 0x60 0xb7 0xe7] + +# LDR (register) has encoding Inst{4} = 0. +[0xba 0xae 0x9f 0x57] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xba 0xae 0x9f 0x57] + +# LDR_PRE/POST has encoding Inst{4} = 0. +[0xde 0x69 0x18 0x46] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xde 0x69 0x18 0x46] + +# Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1| +# ------------------------------------------------------------------------------------------------- +# +# if wback && (n == 15 || n == t) then UNPREDICTABLE +[0x05 0x70 0xd7 0xe6] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x05 0x70 0xd7 0xe6] + + + +#------------------------------------------------------------------------------ +# Undefined encodings for mcr +#------------------------------------------------------------------------------ + +# Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C + +[0x1b 0x1b 0xa0 0x2e] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x1b 0x1b 0xa0 0x2e] + + +#------------------------------------------------------------------------------ +# Undefined encodings for mov/lsl +#------------------------------------------------------------------------------ + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. +# The instruction is UNPREDICTABLE, and is not a valid intruction. +# +# See also +# A8.6.88 LSL (immediate) +# A8.6.98 MOV (shifted register), and +# I.1 Instruction encoding diagrams and pseudocode + +[0x2 0xd1 0xbc 0xf1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x2 0xd1 0xbc 0xf1] + + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. +# The instruction is UNPREDICTABLE, and is not a valid intruction. +# +# See also +# A8.6.97 MOV (register) + +[0x2 0xd0 0xbc 0xf1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x2 0xd0 0xbc 0xf1] + +# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# A8.6.89 LSL (register): Inst{7-4} = 0b0001 +[0x93 0x42 0xa0 0xd1] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x93 0x42 0xa0 0xd1] + +# Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if d == 15 then UNPREDICTABLE +[0x00 0xf0 0x41 0xe3] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x00 0xf0 0x41 0xe3] + + +#------------------------------------------------------------------------------ +# Undefined encodings for mrrc2 +#------------------------------------------------------------------------------ + +[0x00 0x1a 0x50 0xfc] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x1a 0x50 0xfc] + + +#------------------------------------------------------------------------------ +# Undefined encodings for msr (imm) +#------------------------------------------------------------------------------ + +# Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate) +# The hints instructions have more specific encodings, so if mask == 0, +# we should reject this as an invalid instruction. + +[0xa7 0xf1 0x20 0x3] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xa7 0xf1 0x20 0x3] + + +#------------------------------------------------------------------------------ +# Undefined encodings for sbfx +#------------------------------------------------------------------------------ + +# Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 0| 0: 1: 1: 1| 0: 1: 0: 1| 0: 1: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if d == 15 || n == 15 then UNPREDICTABLE; + +[0x5f 0x54 0xa7 0xe7] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x5f 0x54 0xa7 0xe7] + +#------------------------------------------------------------------------------ +# Undefined encodings for smlad +#------------------------------------------------------------------------------ + +# Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.167 +# if d == 15 || n == 15 | m == 15 then UNPREDICTABLE + +[0x1b 0x68 0xf 0x97] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x1b 0x68 0xf 0x97] + + +#------------------------------------------------------------------------------ +# Undefined encodings for srs +#------------------------------------------------------------------------------ + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# Unknown format +# +# B6.1.10 SRS +# Inst{19-8} = 0xd05 +# Inst{7-5} = 0b000 + +[0x83 0x1c 0xc5 0xf8] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x83 0x1c 0xc5 0xf8] + +[0x00 0x00 0x20 0xf8] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x00 0x20 0xf8] + +[0xff 0xff 0xaf 0xf8] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xff 0xff 0xaf 0xf8] + +[0x13 0x00 0xa0 0xf8] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x13 0x00 0xa0 0xf8] + +#------------------------------------------------------------------------------ +# Undefined encodings for sxtb +#------------------------------------------------------------------------------ + +# Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.223 SXTB +# if d == 15 || m == 15 then UNPREDICTABLE; + +[0x75 0xf4 0xaf 0xe6] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x75 0xf4 0xaf 0xe6] + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON umaal +#------------------------------------------------------------------------------ + +# Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.244 UMAAL +# if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; +[0x98 0xbf 0x4f 0xf0] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x98 0xbf 0x4f 0xf0] + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vcvt (float <-> fixed) +#------------------------------------------------------------------------------ + +# imm6=0b0xxxxx -> UNDEFINED +[0x1e 0xcf 0x92 0xf3] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x1e 0xcf 0x92 0xf3] + +[0x3e 0xcf 0x92 0xf3] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x3e 0xcf 0x92 0xf3] + + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vext +#------------------------------------------------------------------------------ + +# invalid imm4 value (0b1xxx) +# A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED; +[0x8f 0xf9 0xf7 0xf2] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x8f 0xf9 0xf7 0xf2] + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vldmsdb +#------------------------------------------------------------------------------ + +# core registers out of range +[0xa5 0xba 0x72 0xed] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0xa5 0xba 0x72 0xed] + + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vmov +#------------------------------------------------------------------------------ + +# VMOV cmode=0b1111 op=1 is UNDEFINED +[0x70 0xef 0xc7 0xf3] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x70 0xef 0xc7 0xf3] + +# VMOV cmode=0b1111 op=1 is UNDEFINED +[0x30 0x0f 0x80 0xf3] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x30 0x0f 0x80 0xf3] + + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vqadd +#------------------------------------------------------------------------------ + +# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# Qm -> bit[0] == 0, otherwise UNDEFINED +[0xdb 0xe0 0x40 0xf2] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xdb 0xe0 0x40 0xf2] + + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vld/vst +#------------------------------------------------------------------------------ + +# A8.6.393 VST2 (multiple 2-element structures) +[0xb3 0x09 0x03 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xb3 0x09 0x03 0xf4] + +# size == '11' ==> UNDEFINED +[0xc3 0x08 0x03 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xc3 0x08 0x03 0xf4] + +# type == '1000' and align == '11' ==> UNDEFINED +[0xb3 0x08 0x03 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xb3 0x08 0x03 0xf4] + +# VST1 multi-element, type == 0b0111, align == 0b10 -> undefined +[0xaf 0xb7 0x07 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xaf 0xb7 0x07 0xf4] + +# VST1 multi-element, type == 0b0111, align == 0b11 -> undefined +[0xbf 0xb7 0x07 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xbf 0xb7 0x07 0xf4] + +# VST1 multi-element, type == 0b1010, align == 0b11 -> undefined +[0xbf 0x8a 0x03 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xbf 0x8a 0x03 0xf4] + +# VST1 multi-element, type == 0b0110, align == 0b10 -> undefined +[0xaf 0xb6 0x07 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xaf 0xb6 0x07 0xf4] + +# VST1 multi-element, type == 0b0110, align == 0b11 -> undefined +[0xbf 0xb6 0x07 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xbf 0xb6 0x07 0xf4] + +# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined +[0x4f 0xa8 0x07 0xf7] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x4f 0xa8 0x07 0xf7] + +# VST2 multi-element, type == 0b0100, align == 0b11 -> undefined +[0x4f 0xa9 0x07 0xf7] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x4f 0xa9 0x07 0xf7] + +# VST3 multi-element, size = 0b11 -> undefined +[0xbf 0xa4 0x0b 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xbf 0xa4 0x0b 0xf4] + +# VST3 multi-element, align = 0b10 -> undefined +[0x6f 0xa4 0x0b 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x6f 0xa4 0x0b 0xf4] + +# VST3 multi-element, align = 0b11 -> undefined +[0x7f 0xa4 0x0b 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x7f 0xa4 0x0b 0xf4] + +# VST4 multi-element, size = 0b11 -> undefined +[0xcf 0x50 0x03 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xcf 0x50 0x03 0xf4] + + +# Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 1: 1: 0: 0| 0: 0: 1: 1| 1: 1: 0: 1| +# ------------------------------------------------------------------------------------------------- +# +# 'a' == 1 and data_size == 8 is invalid +[0x3d 0x3c 0xa0 0xf4] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x3d 0x3c 0xa0 0xf4] diff --git a/test/MC/Disassembler/ARM/invalid-because-armv7.txt b/test/MC/Disassembler/ARM/invalid-because-armv7.txt new file mode 100644 index 0000000..4bf4833 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-because-armv7.txt @@ -0,0 +1,20 @@ +# RUN: not llvm-mc -disassemble -triple armv7 -show-encoding < %s 2>&1 | FileCheck %s + +# This file is checking encodings that are valid on some triples, but not on the +# ARMv7 triple, probably because the relevant instruction is v8, though there +# could be other reasons. + +# Would be vcvtt.f64.f16 d3, s1 +[0xe0 0x3b 0xb2 0xee] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xe0 0x3b 0xb2 0xee] + +# Would be vcvtb.f16.f64 s4, d1 +[0x41 0x2b 0xb3 0xee] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x41 0x2b 0xb3 0xee] + +# Would be vcvtblt.f16.f64 s4, d1 +[0x41 0x2b 0xb3 0xbe] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x41 0x2b 0xb3 0xbe] diff --git a/test/MC/Disassembler/ARM/invalid-hint-arm.txt b/test/MC/Disassembler/ARM/invalid-hint-arm.txt deleted file mode 100644 index 7da96d8..0000000 --- a/test/MC/Disassembler/ARM/invalid-hint-arm.txt +++ /dev/null @@ -1,13 +0,0 @@ -# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble < %s 2>&1 | FileCheck %s - -#------------------------------------------------------------------------------ -# Undefined encoding space for hint instructions -#------------------------------------------------------------------------------ - -0x05 0xf0 0x20 0xe3 -# CHECK: invalid instruction encoding -0x41 0xf0 0x20 0xe3 -# CHECK: invalid instruction encoding -0xfe 0xf0 0x20 0xe3 -# CHECK: invalid instruction encoding - diff --git a/test/MC/Disassembler/ARM/invalid-hint-thumb.txt b/test/MC/Disassembler/ARM/invalid-hint-thumb.txt deleted file mode 100644 index 1e41336..0000000 --- a/test/MC/Disassembler/ARM/invalid-hint-thumb.txt +++ /dev/null @@ -1,8 +0,0 @@ -# RUN: llvm-mc -triple=thumbv7 -disassemble -show-encoding < %s 2>&1 | FileCheck %s - -#------------------------------------------------------------------------------ -# Undefined encoding space for hint instructions -#------------------------------------------------------------------------------ - -0xaf 0xf3 0x05 0x80 -# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt deleted file mode 100644 index c9f1cf1..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# A8.6.16 B -# if cond<3:1> == '111' then SEE "Related Encodings" -0xaf 0xf7 0x44 0x8b diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt deleted file mode 100644 index eb415f7..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# The unpriviledged Load/Store cannot have SP or PC as Rt. -0x10 0xf8 0x3 0xfe diff --git a/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt deleted file mode 100644 index 6c13560..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" -# XFAIL: * - -# Opcode=1934 Name=t2LDREXD Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 1| 0: 0: 1: 0| 1: 0: 0: 0| 1: 0: 0: 0| 0: 1: 1: 1| 1: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# if t == t2 then UNPREDICTABLE -0xd2 0xe8 0x7f 0x88 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt deleted file mode 100644 index 7f84e08..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# if Rt = '1111' then SEE "Unallocated memory hints" -0xb3 0xf9 0xdf 0xf8 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt deleted file mode 100644 index e44cf95..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints" -0x35 0xf9 0x00 0xfc diff --git a/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt deleted file mode 100644 index 8c0d48b..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt +++ /dev/null @@ -1,5 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# SP and PC are not allowed in the register list on STM instructions in Thumb2. - -0x2d 0xe9 0xf7 0xb6 diff --git a/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt deleted file mode 100644 index 64ba368..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" -# XFAIL: * - -# Opcode=2124 Name=t2STRD_PRE Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 0| 0: 1: 0: 0| 0: 1: 0: 0| 0: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 0| -# ------------------------------------------------------------------------------------------------- -# -# if wback && (n == t || n == t2) then UNPREDICTABLE -0xe4 0xe9 0x02 0x46 diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt deleted file mode 100644 index 243c11d..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt +++ /dev/null @@ -1,11 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 2>&1 | grep "invalid instruction encoding" -# XFAIL: * - -# Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 1: 0| -# ------------------------------------------------------------------------------------------------- -# -# if d == n || d == t then UNPREDICTABLE -0xc2 0xe8 0x42 0x8f diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt deleted file mode 100644 index 7a7c4a5..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 0: 1: 1: 1| 1: 0: 0: 0| 0: 1: 1: 1| 1: 0: 0: 0| -# ------------------------------------------------------------------------------------------------- -# -# if d == n || d == t || d == t2 then UNPREDICTABLE -mc-input.txt:1:1: warning: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt deleted file mode 100644 index 2ad3e7d..0000000 --- a/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt +++ /dev/null @@ -1,10 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 2>&1 | grep "invalid instruction encoding" - -# Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -# ------------------------------------------------------------------------------------------------- -# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| -# ------------------------------------------------------------------------------------------------- -# -# if Rn == '1111' then UNDEFINED -0x4f 0xf8 0xff 0xeb diff --git a/test/MC/Disassembler/ARM/invalid-thumbv7-xfail.txt b/test/MC/Disassembler/ARM/invalid-thumbv7-xfail.txt new file mode 100644 index 0000000..ca5dd65 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-thumbv7-xfail.txt @@ -0,0 +1,38 @@ +# RUN: llvm-mc -disassemble -triple thumbv7 2>&1 | FileCheck %s +# XFAIL: * + +#------------------------------------------------------------------------------ +# Undefined encodings for ldrexd/strexd +#------------------------------------------------------------------------------ + +# FIXME: "ldrexd r8, r8, [r2]" +# Rt == Rt2 is UNPREDICTABLE + +[0xd2 0xe8 0x7f 0x88] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0xd2 0xe8 0x7f 0x88] + +# Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# if d == n || d == t then UNPREDICTABLE + +[0xc2 0xe8 0x42 0x8f] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0xc2 0xe8 0x42 0x8f] + +# Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 0: 1: 1: 1| 1: 0: 0: 0| 0: 1: 1: 1| 1: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if d == n || d == t || d == t2 then UNPREDICTABLE + +# FIXME: should be unpredictable since it's "strexd r8, r7, r8, [r2]" +[0xc2 0xe8 0x78 0x78] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0xc2 0xe8 0x78 0x78] diff --git a/test/MC/Disassembler/ARM/invalid-thumbv7.txt b/test/MC/Disassembler/ARM/invalid-thumbv7.txt new file mode 100644 index 0000000..f465b3c --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-thumbv7.txt @@ -0,0 +1,404 @@ +# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s + +# This file is checking Thumbv7 encodings which are globally invalid, usually due +# to the constraints of the instructions not being met. For example invalid +# combinations of registers. + +#------------------------------------------------------------------------------ +# Undefined encoding for b.cc +#------------------------------------------------------------------------------ + +# Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.16 B +# if cond<3:1> == '111' then SEE "Related Encodings" + +[0xaf 0xf7 0x44 0x8b] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0xaf 0xf7 0x44 0x8b] + +# Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if cond = '1110' then UNDEFINED +[0x6f 0xde] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x6f 0xde] + + +#------------------------------------------------------------------------------ +# Undefined encoding space for hint instructions +#------------------------------------------------------------------------------ + +[0xaf 0xf3 0x05 0x80] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xaf 0xf3 0x05 0x80] + + +#------------------------------------------------------------------------------ +# Undefined encoding for it +#------------------------------------------------------------------------------ + +[0xff 0xbf 0x6b 0x80 0x00 0x75] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0xff 0xbf 0x6b 0x80 0x00 0x75] + +# mask = 0 +[0x50 0xbf 0x00 0x00] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x50 0xbf 0x00 0x00] + +# Two warnings from this block since there are two instructions in there +[0xdb 0xbf 0x42 0xbb] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0xdb 0xbf 0x42 0xbb] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0xdb 0xbf 0x42 0xbb] + +#------------------------------------------------------------------------------ +# Undefined encoding for ldm +#------------------------------------------------------------------------------ + +# Writeback is not allowed is Rn is in the target register list. +[0xb4 0xe8 0x34 0x04] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0xb4 0xe8 0x34 0x04] + + +#------------------------------------------------------------------------------ +# Undefined encoding for ldrd +#------------------------------------------------------------------------------ + +# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.66 LDRD (immediate) +# if Rn = '1111' then SEE LDRD (literal) +# A8.6.67 LDRD (literal) +# Inst{21} = 0 + +[0xff 0xe9 0x0 0xeb] +# CHECK: potentially undefined +# CHECK-NEXT: [0xff 0xe9 0x0 0xeb] + + +#------------------------------------------------------------------------------ +# Undefined encodings for ldrbt +#------------------------------------------------------------------------------ + +# Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# The unpriviledged Load/Store cannot have SP or PC as Rt. +[0x10 0xf8 0x3 0xfe] +# CHECK: potentially undefined instruction encoding +# CHECK-NEXT: [0x10 0xf8 0x3 0xfe] + + +#------------------------------------------------------------------------------ +# Undefined encodings for ldrsh +#------------------------------------------------------------------------------ + +# invalid LDRSHs Rt=PC +[0x30 0xf9 0x00 0xf0] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x30 0xf9 0x00 0xf0] + +# invalid LDRSHi8 Rt=PC +[0x30 0xf9 0x00 0xfc] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x30 0xf9 0x00 0xfc] + +# invalid LDRSHi12 Rt=PC +[0xb0 0xf9 0x00 0xf0] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xb0 0xf9 0x00 0xf0] + +# Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints" +[0x35 0xf9 0x00 0xfc] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x35 0xf9 0x00 0xfc] + +# Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if Rt = '1111' then SEE "Unallocated memory hints" +[0xb3 0xf9 0xdf 0xf8] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xb3 0xf9 0xdf 0xf8] + + +#------------------------------------------------------------------------------ +# Undefined encoding for push +#------------------------------------------------------------------------------ + +# SP and PC are not allowed in the register list on STM instructions in Thumb2. +[0x2d 0xe9 0xf7 0xb6] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x2d 0xe9 0xf7 0xb6] + + +#------------------------------------------------------------------------------ +# Undefined encoding for stmia +#------------------------------------------------------------------------------ + +# Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if BitCount(registers) < 1 then UNPREDICTABLE +[0x00 0xc7] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0xc7] + + +#------------------------------------------------------------------------------ +# Undefined encodings for str +#------------------------------------------------------------------------------ + +# invalid STRi12 Rn=PC +[0xcf 0xf8 0x00 0x00] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xcf 0xf8 0x00 0x00] + +# invalid STRi8 Rn=PC +[0x4f 0xf8 0x00 0x0c] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x4f 0xf8 0x00 0x0c] + +# invalid STRs Rn=PC +[0x4f 0xf8 0x00 0x00] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x4f 0xf8 0x00 0x00] + +# invalid STRBi12 Rn=PC +[0x0f 0xf8 0x00 0x00] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x0f 0xf8 0x00 0x00] + +# invalid STRBi8 Rn=PC +[0x0f 0xf8 0x00 0x0c] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x0f 0xf8 0x00 0x0c] + +# invalid STRBs Rn=PC +[0x0f 0xf8 0x00 0x00] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x0f 0xf8 0x00 0x00] + +# invalid STRHi12 Rn=PC +[0xaf 0xf8 0x00 0x00] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xaf 0xf8 0x00 0x00] + +# invalid STRHi8 Rn=PC +[0x2f 0xf8 0x00 0x0c] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x2f 0xf8 0x00 0x0c] + +# invalid STRHs Rn=PC +[0x2f 0xf8 0x00 0x00] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x2f 0xf8 0x00 0x00] + +# invalid STRBT Rn=PC +[0x0f 0xf8 0x00 0x0e] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x0f 0xf8 0x00 0x0e] + +# invalid STRHT Rn=PC +[0x2f 0xf8 0x00 0x0e] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x2f 0xf8 0x00 0x0e] + +# invalid STRT Rn=PC +[0x4f 0xf8 0x00 0x0e] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x4f 0xf8 0x00 0x0e] + +# Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if Rn == '1111' then UNDEFINED + +[0x4f 0xf8 0xff 0xeb] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x4f 0xf8 0xff 0xeb] + +#------------------------------------------------------------------------------ +# Undefined encodings for strd +#------------------------------------------------------------------------------ + +# Rt == Rn is UNPREDICTABLE +[0xe4 0xe9 0x02 0x46] +# CHECK: warning: potentially undefined instruction encoding +# CHECK-NEXT: [0xe4 0xe9 0x02 0x46] + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON/VFP instructions with invalid predicate bits +#------------------------------------------------------------------------------ + +# VABS +[0x40 0xde 0x00 0x0a] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x40 0xde 0x00 0x0a] + + +# VMLA +[0xf0 0xde 0xe0 0x0b] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xf0 0xde 0xe0 0x0b] + +# VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110) + +# VMOV +[0x00 0xde 0x10 0x0b] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0xde 0x10 0x0b] + +# VDUP +[0xff 0xde 0xf0 0xfb] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xff 0xde 0xf0 0xfb] + + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vld instructions +#------------------------------------------------------------------------------ + +# size = '00' and index_align == '0001' so UNDEFINED +[0xa0 0xf9 0x10 0x08] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xa0 0xf9 0x10 0x08] + + +# vld3 + +# Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.315 VLD3 (single 3-element structure to all lanes) +# The a bit must be encoded as 0. + +[0xa2 0xf9 0x92 0x2e] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xa2 0xf9 0x92 0x2e] + + +# Some vld4 ones +# size == '11' and a == '0' so UNDEFINED +[0xa0 0xf9 0xc0 0x0f] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xa0 0xf9 0xc0 0x0f] + +[0xa0 0xf9 0x30 0x0b] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0xa0 0xf9 0x30 0x0b] + + +# VLD1 multi-element, type=0b1010 align=0b11 +[0x24 0xf9 0xbf 0x8a] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x24 0xf9 0xbf 0x8a] + +# VLD1 multi-element type=0b0111 align=0b1x +[0x24 0xf9 0xbf 0x87] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x24 0xf9 0xbf 0x87] + +# VLD1 multi-element type=0b0010 align=0b1x +[0x24 0xf9 0xbf 0x86] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x24 0xf9 0xbf 0x86] + +# VLD2 multi-element size=0b11 +[0x60 0xf9 0xcf 0x08] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x60 0xf9 0xcf 0x08] + +# VLD2 multi-element type=0b1111 align=0b11 +[0x60 0xf9 0xbf 0x08] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x60 0xf9 0xbf 0x08] + +# VLD2 multi-element type=0b1001 align=0b11 +[0x60 0xf9 0xbf 0x09] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x60 0xf9 0xbf 0x09] + +# VLD3 multi-element size=0b11 +[0x60 0xf9 0x7f 0x04] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x60 0xf9 0x7f 0x04] + +# VLD3 multi-element align=0b1x +[0x60 0xf9 0xcf 0x04] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x60 0xf9 0xcf 0x04] + +# VLD4 multi-element size=0b11 +[0x60 0xf9 0xcd 0x11] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x60 0xf9 0xcd 0x11] + + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vst1 +#------------------------------------------------------------------------------ + +# size == '10' and index_align == '0001' so UNDEFINED +[0x80 0xf9 0x10 0x08] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x80 0xf9 0x10 0x08] + +# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.391 VST1 (multiple single elements) +# This encoding looks like: vst1.8 {d0,d1,d2}, [r0:128] +# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list> +# contains two or four registers. rdar://11220250 +[0x00 0xf9 0x2f 0x06] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0xf9 0x2f 0x06] + +#------------------------------------------------------------------------------ +# Undefined encodings for NEON vst4 +#------------------------------------------------------------------------------ + +[0x80 0xf9 0x30 0x0b] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x80 0xf9 0x30 0x0b] diff --git a/test/MC/Disassembler/ARM/neon-v8.txt b/test/MC/Disassembler/ARM/neon-v8.txt new file mode 100644 index 0000000..8c6e689 --- /dev/null +++ b/test/MC/Disassembler/ARM/neon-v8.txt @@ -0,0 +1,71 @@ +# RUN: llvm-mc -triple armv8-unknown-unknown -mattr=+neon -disassemble < %s | FileCheck %s + +0x11 0x4f 0x05 0xf3 +# CHECK: vmaxnm.f32 d4, d5, d1 +0x5c 0x4f 0x08 0xf3 +# CHECK: vmaxnm.f32 q2, q4, q6 +0x3e 0x5f 0x24 0xf3 +# CHECK: vminnm.f32 d5, d4, d30 +0xd4 0x0f 0x2a 0xf3 +# CHECK: vminnm.f32 q0, q13, q2 + +0x06 0x40 0xbb 0xf3 +# CHECK: vcvta.s32.f32 d4, d6 +0x8a 0xc0 0xbb 0xf3 +# CHECK: vcvta.u32.f32 d12, d10 +0x4c 0x80 0xbb 0xf3 +# CHECK: vcvta.s32.f32 q4, q6 +0xe4 0x80 0xbb 0xf3 +# CHECK: vcvta.u32.f32 q4, q10 + +0x2e 0x13 0xbb 0xf3 +# CHECK: vcvtm.s32.f32 d1, d30 +0x8a 0xc3 0xbb 0xf3 +# CHECK: vcvtm.u32.f32 d12, d10 +0x64 0x23 0xbb 0xf3 +# CHECK: vcvtm.s32.f32 q1, q10 +0xc2 0xa3 0xfb 0xf3 +# CHECK: vcvtm.u32.f32 q13, q1 + +0x21 0xf1 0xbb 0xf3 +# CHECK: vcvtn.s32.f32 d15, d17 +0x83 0x51 0xbb 0xf3 +# CHECK: vcvtn.u32.f32 d5, d3 +0x60 0x61 0xbb 0xf3 +# CHECK: vcvtn.s32.f32 q3, q8 +0xc6 0xa1 0xbb 0xf3 +# CHECK: vcvtn.u32.f32 q5, q3 + +0x25 0xb2 0xbb 0xf3 +# CHECK: vcvtp.s32.f32 d11, d21 +0xa7 0xe2 0xbb 0xf3 +# CHECK: vcvtp.u32.f32 d14, d23 +0x6e 0x82 0xbb 0xf3 +# CHECK: vcvtp.s32.f32 q4, q15 +0xe0 0x22 0xfb 0xf3 +# CHECK: vcvtp.u32.f32 q9, q8 + +0x00 0x34 0xba 0xf3 +# CHECK: vrintn.f32 d3, d0 +0x48 0x24 0xba 0xf3 +# CHECK: vrintn.f32 q1, q4 +0x8c 0x54 0xba 0xf3 +# CHECK: vrintx.f32 d5, d12 +0xc6 0x04 0xba 0xf3 +# CHECK: vrintx.f32 q0, q3 +0x00 0x35 0xba 0xf3 +# CHECK: vrinta.f32 d3, d0 +0x44 0x05 0xfa 0xf3 +# CHECK: vrinta.f32 q8, q2 +0xa2 0xc5 0xba 0xf3 +# CHECK: vrintz.f32 d12, d18 +0xc8 0x25 0xfa 0xf3 +# CHECK: vrintz.f32 q9, q4 +0x80 0x36 0xba 0xf3 +# CHECK: vrintm.f32 d3, d0 +0xc8 0x26 0xba 0xf3 +# CHECK: vrintm.f32 q1, q4 +0x80 0x37 0xba 0xf3 +# CHECK: vrintp.f32 d3, d0 +0xc8 0x27 0xba 0xf3 +# CHECK: vrintp.f32 q1, q4 diff --git a/test/MC/Disassembler/ARM/thumb-neon-v8.txt b/test/MC/Disassembler/ARM/thumb-neon-v8.txt new file mode 100644 index 0000000..27c09ea --- /dev/null +++ b/test/MC/Disassembler/ARM/thumb-neon-v8.txt @@ -0,0 +1,71 @@ +# RUN: llvm-mc -triple thumbv8-unknown-unknown -mattr=+neon -disassemble < %s | FileCheck %s + +0x5 0xff 0x11 0x4f +# CHECK: vmaxnm.f32 d4, d5, d1 +0x08 0xff 0x5c 0x4f +# CHECK: vmaxnm.f32 q2, q4, q6 +0x24 0xff 0x3e 0x5f +# CHECK: vminnm.f32 d5, d4, d30 +0x2a 0xff 0xd4 0x0f +# CHECK: vminnm.f32 q0, q13, q2 + +0xbb 0xff 0x06 0x40 +# CHECK: vcvta.s32.f32 d4, d6 +0xbb 0xff 0x8a 0xc0 +# CHECK: vcvta.u32.f32 d12, d10 +0xbb 0xff 0x4c 0x80 +# CHECK: vcvta.s32.f32 q4, q6 +0xbb 0xff 0xe4 0x80 +# CHECK: vcvta.u32.f32 q4, q10 + +0xbb 0xff 0x2e 0x13 +# CHECK: vcvtm.s32.f32 d1, d30 +0xbb 0xff 0x8a 0xc3 +# CHECK: vcvtm.u32.f32 d12, d10 +0xbb 0xff 0x64 0x23 +# CHECK: vcvtm.s32.f32 q1, q10 +0xfb 0xff 0xc2 0xa3 +# CHECK: vcvtm.u32.f32 q13, q1 + +0xbb 0xff 0x21 0xf1 +# CHECK: vcvtn.s32.f32 d15, d17 +0xbb 0xff 0x83 0x51 +# CHECK: vcvtn.u32.f32 d5, d3 +0xbb 0xff 0x60 0x61 +# CHECK: vcvtn.s32.f32 q3, q8 +0xbb 0xff 0xc6 0xa1 +# CHECK: vcvtn.u32.f32 q5, q3 + +0xbb 0xff 0x25 0xb2 +# CHECK: vcvtp.s32.f32 d11, d21 +0xbb 0xff 0xa7 0xe2 +# CHECK: vcvtp.u32.f32 d14, d23 +0xbb 0xff 0x6e 0x82 +# CHECK: vcvtp.s32.f32 q4, q15 +0xfb 0xff 0xe0 0x22 +# CHECK: vcvtp.u32.f32 q9, q8 + +0xba 0xff 0x00 0x34 +# CHECK: vrintn.f32 d3, d0 +0xba 0xff 0x48 0x24 +# CHECK: vrintn.f32 q1, q4 +0xba 0xff 0x8c 0x54 +# CHECK: vrintx.f32 d5, d12 +0xba 0xff 0xc6 0x04 +# CHECK: vrintx.f32 q0, q3 +0xba 0xff 0x00 0x35 +# CHECK: vrinta.f32 d3, d0 +0xfa 0xff 0x44 0x05 +# CHECK: vrinta.f32 q8, q2 +0xba 0xff 0xa2 0xc5 +# CHECK: vrintz.f32 d12, d18 +0xfa 0xff 0xc8 0x25 +# CHECK: vrintz.f32 q9, q4 +0xba 0xff 0x80 0x36 +# CHECK: vrintm.f32 d3, d0 +0xba 0xff 0xc8 0x26 +# CHECK: vrintm.f32 q1, q4 +0xba 0xff 0x80 0x37 +# CHECK: vrintp.f32 d3, d0 +0xba 0xff 0xc8 0x27 +# CHECK: vrintp.f32 q1, q4 diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt index 757ce6e..84dd075 100644 --- a/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/test/MC/Disassembler/ARM/thumb-tests.txt @@ -221,6 +221,9 @@ # CHECK: stc2 p12, c15, [r9], {137} 0x89 0xfc 0x89 0xfc +# CHECK: stc2 p0, c0, [r0, #0]! +0xa0 0xfd 0x00 0x00 + # CHECK: vmov r1, r0, d11 0x50 0xec 0x1b 0x1b diff --git a/test/MC/Disassembler/ARM/thumb-v8fp.txt b/test/MC/Disassembler/ARM/thumb-v8fp.txt new file mode 100644 index 0000000..3457192 --- /dev/null +++ b/test/MC/Disassembler/ARM/thumb-v8fp.txt @@ -0,0 +1,163 @@ +# RUN: llvm-mc -disassemble -triple thumbv8 -mattr=+v8fp -show-encoding < %s | FileCheck %s + +0xb2 0xee 0xe0 0x3b +# CHECK: vcvtt.f64.f16 d3, s1 + +0xf3 0xee 0xcc 0x2b +# CHECK: vcvtt.f16.f64 s5, d12 + +0xb2 0xee 0x60 0x3b +# CHECK: vcvtb.f64.f16 d3, s1 + +0xb3 0xee 0x41 0x2b +# CHECK: vcvtb.f16.f64 s4, d1 + +0xa8 0xbf # IT block +0xb2 0xee 0xe0 0x3b +# CHECK: vcvttge.f64.f16 d3, s1 + +0xc8 0xbf # IT block +0xf3 0xee 0xcc 0x2b +# CHECK: vcvttgt.f16.f64 s5, d12 + +0x08 0xbf # IT block +0xb2 0xee 0x60 0x3b +# CHECK: vcvtbeq.f64.f16 d3, s1 + +0xb8 0xbf # IT block +0xb3 0xee 0x41 0x2b +# CHECK: vcvtblt.f16.f64 s4, d1 + + +0xbc 0xfe 0xe1 0x1a +# CHECK: vcvta.s32.f32 s2, s3 + +0xbc 0xfe 0xc3 0x1b +# CHECK: vcvta.s32.f64 s2, d3 + +0xbd 0xfe 0xeb 0x3a +# CHECK: vcvtn.s32.f32 s6, s23 + +0xbd 0xfe 0xe7 0x3b +# CHECK: vcvtn.s32.f64 s6, d23 + +0xbe 0xfe 0xc2 0x0a +# CHECK: vcvtp.s32.f32 s0, s4 + +0xbe 0xfe 0xc4 0x0b +# CHECK: vcvtp.s32.f64 s0, d4 + +0xff 0xfe 0xc4 0x8a +# CHECK: vcvtm.s32.f32 s17, s8 + +0xff 0xfe 0xc8 0x8b +# CHECK: vcvtm.s32.f64 s17, d8 + +0xbc 0xfe 0x61 0x1a +# CHECK: vcvta.u32.f32 s2, s3 + +0xbc 0xfe 0x43 0x1b +# CHECK: vcvta.u32.f64 s2, d3 + +0xbd 0xfe 0x6b 0x3a +# CHECK: vcvtn.u32.f32 s6, s23 + +0xbd 0xfe 0x67 0x3b +# CHECK: vcvtn.u32.f64 s6, d23 + +0xbe 0xfe 0x42 0x0a +# CHECK: vcvtp.u32.f32 s0, s4 + +0xbe 0xfe 0x44 0x0b +# CHECK: vcvtp.u32.f64 s0, d4 + +0xff 0xfe 0x44 0x8a +# CHECK: vcvtm.u32.f32 s17, s8 + +0xff 0xfe 0x48 0x8b +# CHECK: vcvtm.u32.f64 s17, d8 + + +0x20 0xfe 0xab 0x2a +# CHECK: vselge.f32 s4, s1, s23 + +0x6f 0xfe 0xa7 0xeb +# CHECK: vselge.f64 d30, d31, d23 + +0x30 0xfe 0x80 0x0a +# CHECK: vselgt.f32 s0, s1, s0 + +0x3a 0xfe 0x24 0x5b +# CHECK: vselgt.f64 d5, d10, d20 + +0x0e 0xfe 0x2b 0xfa +# CHECK: vseleq.f32 s30, s28, s23 + +0x04 0xfe 0x08 0x2b +# CHECK: vseleq.f64 d2, d4, d8 + +0x58 0xfe 0x07 0xaa +# CHECK: vselvs.f32 s21, s16, s14 + +0x11 0xfe 0x2f 0x0b +# CHECK: vselvs.f64 d0, d1, d31 + + +0xc6 0xfe 0x00 0x2a +# CHECK: vmaxnm.f32 s5, s12, s0 + +0x86 0xfe 0xae 0x5b +# CHECK: vmaxnm.f64 d5, d22, d30 + +0x80 0xfe 0x46 0x0a +# CHECK: vminnm.f32 s0, s0, s12 + +0x86 0xfe 0x49 0x4b +# CHECK: vminnm.f64 d4, d6, d9 + + +0xa8 0xbf # IT block +0xb6 0xee 0xcc 0x3b +# CHECK: vrintzge.f64 d3, d12 + +0xf6 0xee 0xcc 0x1a +# CHECK: vrintz.f32 s3, s24 + +0xb8 0xbf # IT block +0xb6 0xee 0x40 0x5b +# CHECK: vrintrlt.f64 d5, d0 + +0xb6 0xee 0x64 0x0a +# CHECK: vrintr.f32 s0, s9 + +0x08 0xbf # IT block +0xf7 0xee 0x6e 0xcb +# CHECK: vrintxeq.f64 d28, d30 + +0x68 0xbf # IT block +0xb7 0xee 0x47 0x5a +# CHECK: vrintxvs.f32 s10, s14 + +0xb8 0xfe 0x44 0x3b +# CHECK: vrinta.f64 d3, d4 + +0xb8 0xfe 0x60 0x6a +# CHECK: vrinta.f32 s12, s1 + +0xb9 0xfe 0x44 0x3b +# CHECK: vrintn.f64 d3, d4 + +0xb9 0xfe 0x60 0x6a +# CHECK: vrintn.f32 s12, s1 + +0xba 0xfe 0x44 0x3b +# CHECK: vrintp.f64 d3, d4 + +0xba 0xfe 0x60 0x6a +# CHECK: vrintp.f32 s12, s1 + +0xbb 0xfe 0x44 0x3b +# CHECK: vrintm.f64 d3, d4 + +0xbb 0xfe 0x60 0x6a +# CHECK: vrintm.f32 s12, s1 diff --git a/test/MC/Disassembler/ARM/thumb1.txt b/test/MC/Disassembler/ARM/thumb1.txt index de9596a..a129abb 100644 --- a/test/MC/Disassembler/ARM/thumb1.txt +++ b/test/MC/Disassembler/ARM/thumb1.txt @@ -54,8 +54,12 @@ #------------------------------------------------------------------------------ # ADR #------------------------------------------------------------------------------ -# CHECK: adr r2, #3 +# CHECK: adr r5, #0 +# CHECK: adr r2, #12 +# CHECK: adr r3, #1020 +0x00 0xa5 0x03 0xa2 +0xff 0xa3 #------------------------------------------------------------------------------ # ASR (immediate) @@ -279,9 +283,11 @@ #------------------------------------------------------------------------------ # CHECK: mov r3, r4 # CHECK: movs r1, r3 +# CHECK: mov r8, r8 0x23 0x46 0x19 0x00 +0xc0 0x46 #------------------------------------------------------------------------------ @@ -310,14 +316,6 @@ #------------------------------------------------------------------------------ -# NOP -#------------------------------------------------------------------------------ -# CHECK: nop - -0xc0 0x46 - - -#------------------------------------------------------------------------------ # ORR #------------------------------------------------------------------------------ # CHECK: orrs r3, r4 diff --git a/test/MC/Disassembler/ARM/thumb2.txt b/test/MC/Disassembler/ARM/thumb2.txt index fc237ab..9fc166f 100644 --- a/test/MC/Disassembler/ARM/thumb2.txt +++ b/test/MC/Disassembler/ARM/thumb2.txt @@ -170,8 +170,10 @@ 0x13 0xf5 0xce 0xa9 # CHECK: b.w #208962 +# CHECK: b.w #-16777216 0x33 0xf0 0x21 0xb8 # rdar://12585795 +0x00 0xf4 0x00 0x90 #------------------------------------------------------------------------------ # BFC @@ -551,6 +553,17 @@ #------------------------------------------------------------------------------ +# LDR(literal) +#------------------------------------------------------------------------------ +# CHECK: ldr.w r4, [pc, #-0] +# CHECK: ldr.w r2, [pc, #-40] +# CHECK: ldr.w r1, [pc, #1024] +0x5f 0xf8 0x00 0x40 +0x5f 0xf8 0x28 0x20 +0xdf 0xf8 0x00 0x14 + + +#------------------------------------------------------------------------------ # LDR(register) #------------------------------------------------------------------------------ # CHECK: ldr.w r1, [r8, r1] @@ -563,6 +576,7 @@ # CHECK: ldr r2, [r4, #255]! # CHECK: ldr r8, [sp, #4]! # CHECK: ldr lr, [sp, #-4]! +# CHECK: ldr lr, [sp, #0]! # CHECK: ldr r2, [r4], #255 # CHECK: ldr r8, [sp], #4 # CHECK: ldr lr, [sp], #-4 @@ -577,6 +591,7 @@ 0x54 0xf8 0xff 0x2f 0x5d 0xf8 0x04 0x8f 0x5d 0xf8 0x04 0xed +0x5d 0xf8 0x00 0xef 0x54 0xf8 0xff 0x2b 0x5d 0xf8 0x04 0x8b 0x5d 0xf8 0x04 0xe9 @@ -610,6 +625,7 @@ # CHECK: ldrb r5, [r8, #255]! # CHECK: ldrb r2, [r5, #4]! # CHECK: ldrb r1, [r4, #-4]! +# CHECK: ldrb r1, [r4, #0]! # CHECK: ldrb lr, [r3], #255 # CHECK: ldrb r9, [r2], #4 # CHECK: ldrb r3, [sp], #-4 @@ -623,12 +639,24 @@ 0x18 0xf8 0xff 0x5f 0x15 0xf8 0x04 0x2f 0x14 0xf8 0x04 0x1d +0x14 0xf8 0x00 0x1f 0x13 0xf8 0xff 0xeb 0x12 0xf8 0x04 0x9b 0x1d 0xf8 0x04 0x39 #------------------------------------------------------------------------------ +# LDRB(literal) +#------------------------------------------------------------------------------ +# CHECK: ldrb.w r6, [pc, #-0] +# CHECK: ldrb.w r10, [pc, #227] +# CHECK: ldrb.w r5, [pc, #0] +0x1f 0xf8 0x00 0x60 +0x9f 0xf8 0xe3 0xa0 +0x9f 0xf8 0x00 0x50 + + +#------------------------------------------------------------------------------ # LDRBT #------------------------------------------------------------------------------ # CHECK: ldrbt r1, [r2] @@ -653,7 +681,9 @@ # CHECK: ldrd r8, r1, [r3] # CHECK: ldrd r0, r1, [r2], #-0 # CHECK: ldrd r0, r1, [r2, #-0]! +# CHECK: ldrd r0, r1, [r2, #0]! # CHECK: ldrd r0, r1, [r2, #-0] +# CHECK: ldrd r1, r1, [r0], #0 0xd6 0xe9 0x06 0x35 0xf6 0xe9 0x06 0x35 @@ -663,7 +693,9 @@ 0xd3 0xe9 0x00 0x81 0x72 0xe8 0x00 0x01 0x72 0xe9 0x00 0x01 +0xf2 0xe9 0x00 0x01 0x52 0xe9 0x00 0x01 +0xf0 0xe8 0x00 0x11 #------------------------------------------------------------------------------ @@ -697,14 +729,12 @@ # CHECK: ldrh.w r5, [r6, #33] # CHECK: ldrh.w r5, [r6, #257] # CHECK: ldrh.w lr, [r7, #257] -# CHECK: ldrh.w r0, [pc, #-21] 0x35 0xf8 0x04 0x5c 0x35 0x8c 0xb6 0xf8 0x21 0x50 0xb6 0xf8 0x01 0x51 0xb7 0xf8 0x01 0xe1 -0x3f 0xf8 0x15 0x00 #------------------------------------------------------------------------------ @@ -719,6 +749,7 @@ # CHECK: ldrh r5, [r8, #255]! # CHECK: ldrh r2, [r5, #4]! # CHECK: ldrh r1, [r4, #-4]! +# CHECK: ldrh r1, [r4, #0]! # CHECK: ldrh lr, [r3], #255 # CHECK: ldrh r9, [r2], #4 # CHECK: ldrh r3, [sp], #-4 @@ -732,12 +763,24 @@ 0x38 0xf8 0xff 0x5f 0x35 0xf8 0x04 0x2f 0x34 0xf8 0x04 0x1d +0x34 0xf8 0x00 0x1f 0x33 0xf8 0xff 0xeb 0x32 0xf8 0x04 0x9b 0x3d 0xf8 0x04 0x39 #------------------------------------------------------------------------------ +# LDRH(literal) +#------------------------------------------------------------------------------ +# CHECK: ldrh.w r7, [pc, #-0] +# CHECK: ldrh.w r5, [pc, #121] +# CHECK: ldrh.w r4, [pc, #0] +0x3f 0xf8 0x00 0x70 +0xbf 0xf8 0x79 0x50 +0xbf 0xf8 0x00 0x40 + + +#------------------------------------------------------------------------------ # LDRSB(immediate) #------------------------------------------------------------------------------ # CHECK: ldrsb r5, [r5, #-4] @@ -765,6 +808,7 @@ # CHECK: ldrsb r5, [r8, #255]! # CHECK: ldrsb r2, [r5, #4]! # CHECK: ldrsb r1, [r4, #-4]! +# CHECK: ldrsb r1, [r4, #0]! # CHECK: ldrsb lr, [r3], #255 # CHECK: ldrsb r9, [r2], #4 # CHECK: ldrsb r3, [sp], #-4 @@ -778,12 +822,24 @@ 0x18 0xf9 0xff 0x5f 0x15 0xf9 0x04 0x2f 0x14 0xf9 0x04 0x1d +0x14 0xf9 0x00 0x1f 0x13 0xf9 0xff 0xeb 0x12 0xf9 0x04 0x9b 0x1d 0xf9 0x04 0x39 #------------------------------------------------------------------------------ +# LDRSB(literal) +#------------------------------------------------------------------------------ +# CHECK: ldrsb.w r0, [pc, #-0] +# CHECK: ldrsb.w r12, [pc, #80] +# CHECK: ldrsb.w r3, [pc, #0] +0x1f 0xf9 0x00 0x00 +0x9f 0xf9 0x50 0xc0 +0x9f 0xf9 0x00 0x30 + + +#------------------------------------------------------------------------------ # LDRSBT #------------------------------------------------------------------------------ # CHECK: ldrsbt r1, [r2] @@ -826,6 +882,7 @@ # CHECK: ldrsh r5, [r8, #255]! # CHECK: ldrsh r2, [r5, #4]! # CHECK: ldrsh r1, [r4, #-4]! +# CHECK: ldrsh r1, [r4, #0]! # CHECK: ldrsh lr, [r3], #255 # CHECK: ldrsh r9, [r2], #4 # CHECK: ldrsh r3, [sp], #-4 @@ -839,12 +896,24 @@ 0x38 0xf9 0xff 0x5f 0x35 0xf9 0x04 0x2f 0x34 0xf9 0x04 0x1d +0x34 0xf9 0x00 0x1f 0x33 0xf9 0xff 0xeb 0x32 0xf9 0x04 0x9b 0x3d 0xf9 0x04 0x39 #------------------------------------------------------------------------------ +# LDRSH(literal) +#------------------------------------------------------------------------------ +# CHECK: ldrsh.w r0, [pc, #-0] +# CHECK: ldrsh.w r10, [pc, #-231] +# CHECK: ldrsh.w r6, [pc, #0] +0x3f 0xf9 0x00 0x00 +0x3f 0xf9 0xe7 0xa0 +0xbf 0xf9 0x00 0x60 + + +#------------------------------------------------------------------------------ # LDRSHT #------------------------------------------------------------------------------ # CHECK: ldrsht r1, [r2] @@ -1237,6 +1306,17 @@ 0x1d 0xf8 0x02 0xf0 #------------------------------------------------------------------------------ +# PLD(literal) +#------------------------------------------------------------------------------ +# CHECK: pld [pc, #-0] +# CHECK: pld [pc, #455] +# CHECK: pld [pc, #0] + +0x1f 0xf8 0x00 0xf0 +0x9f 0xf8 0xc7 0xf1 +0x9f 0xf8 0x00 0xf0 + +#------------------------------------------------------------------------------ # PLI(immediate) #------------------------------------------------------------------------------ # CHECK: pli [r5, #-4] @@ -1268,6 +1348,17 @@ 0x1d 0xf9 0x12 0xf0 0x1d 0xf9 0x02 0xf0 +#------------------------------------------------------------------------------ +# PLI(literal) +#------------------------------------------------------------------------------ +# CHECK: pli [pc, #-0] +# CHECK: pli [pc, #-328] +# CHECK: pli [pc, #0] + +0x1f 0xf9 0x00 0xf0 +0x1f 0xf9 0x48 0xf1 +0x9f 0xf9 0x00 0xf0 + #------------------------------------------------------------------------------ # QADD/QADD16/QADD8 @@ -1837,16 +1928,20 @@ #------------------------------------------------------------------------------ # STRD (immediate) #------------------------------------------------------------------------------ +# CHECK: strd r1, r1, [r0], #0 # CHECK: strd r6, r3, [r5], #-8 # CHECK: strd r8, r5, [r5], #-0 # CHECK: strd r7, r4, [r5], #-4 # CHECK: strd r0, r1, [r2, #-0]! +# CHECK: strd r0, r1, [r2, #0]! # CHECK: strd r0, r1, [r2, #-0] +0xe0 0xe8 0x00 0x11 0x65 0xe8 0x02 0x63 0x65 0xe8 0x00 0x85 0x65 0xe8 0x01 0x74 0x62 0xe9 0x00 0x01 +0xe2 0xe9 0x00 0x01 0x42 0xe9 0x00 0x01 #------------------------------------------------------------------------------ @@ -1878,6 +1973,7 @@ # CHECK: strh r5, [r8, #255]! # CHECK: strh r2, [r5, #4]! # CHECK: strh r1, [r4, #-4]! +# CHECK: strh r1, [r4, #0]! # CHECK: strh lr, [r3], #255 # CHECK: strh r9, [r2], #4 # CHECK: strh r3, [sp], #-4 @@ -1890,6 +1986,7 @@ 0x28 0xf8 0xff 0x5f 0x25 0xf8 0x04 0x2f 0x24 0xf8 0x04 0x1d +0x24 0xf8 0x00 0x1f 0x23 0xf8 0xff 0xeb 0x22 0xf8 0x04 0x9b 0x2d 0xf8 0x04 0x39 @@ -1954,6 +2051,7 @@ # CHECK: sub.w r12, r6, #256 # CHECK: subw r12, r6, #256 # CHECK: subs.w r1, r2, #496 +# CHECK: subs pc, lr, #4 0x0a 0xbf 0x11 0x1f @@ -1965,6 +2063,7 @@ 0xa6 0xf5 0x80 0x7c 0xa6 0xf2 0x00 0x1c 0xb2 0xf5 0xf8 0x71 +0xde 0xf3 0x04 0x8f #------------------------------------------------------------------------------ diff --git a/test/MC/Disassembler/ARM/v8fp.txt b/test/MC/Disassembler/ARM/v8fp.txt new file mode 100644 index 0000000..a6e88b6 --- /dev/null +++ b/test/MC/Disassembler/ARM/v8fp.txt @@ -0,0 +1,155 @@ +# RUN: llvm-mc -disassemble -triple armv8 -mattr=+v8fp -show-encoding < %s | FileCheck %s + +0xe0 0x3b 0xb2 0xee +# CHECK: vcvtt.f64.f16 d3, s1 + +0xcc 0x2b 0xf3 0xee +# CHECK: vcvtt.f16.f64 s5, d12 + +0x60 0x3b 0xb2 0xee +# CHECK: vcvtb.f64.f16 d3, s1 + +0x41 0x2b 0xb3 0xee +# CHECK: vcvtb.f16.f64 s4, d1 + +0xe0 0x3b 0xb2 0xae +# CHECK: vcvttge.f64.f16 d3, s1 + +0xcc 0x2b 0xf3 0xce +# CHECK: vcvttgt.f16.f64 s5, d12 + +0x60 0x3b 0xb2 0x0e +# CHECK: vcvtbeq.f64.f16 d3, s1 + +0x41 0x2b 0xb3 0xbe +# CHECK: vcvtblt.f16.f64 s4, d1 + + +0xe1 0x1a 0xbc 0xfe +# CHECK: vcvta.s32.f32 s2, s3 + +0xc3 0x1b 0xbc 0xfe +# CHECK: vcvta.s32.f64 s2, d3 + +0xeb 0x3a 0xbd 0xfe +# CHECK: vcvtn.s32.f32 s6, s23 + +0xe7 0x3b 0xbd 0xfe +# CHECK: vcvtn.s32.f64 s6, d23 + +0xc2 0x0a 0xbe 0xfe +# CHECK: vcvtp.s32.f32 s0, s4 + +0xc4 0x0b 0xbe 0xfe +# CHECK: vcvtp.s32.f64 s0, d4 + +0xc4 0x8a 0xff 0xfe +# CHECK: vcvtm.s32.f32 s17, s8 + +0xc8 0x8b 0xff 0xfe +# CHECK: vcvtm.s32.f64 s17, d8 + +0x61 0x1a 0xbc 0xfe +# CHECK: vcvta.u32.f32 s2, s3 + +0x43 0x1b 0xbc 0xfe +# CHECK: vcvta.u32.f64 s2, d3 + +0x6b 0x3a 0xbd 0xfe +# CHECK: vcvtn.u32.f32 s6, s23 + +0x67 0x3b 0xbd 0xfe +# CHECK: vcvtn.u32.f64 s6, d23 + +0x42 0x0a 0xbe 0xfe +# CHECK: vcvtp.u32.f32 s0, s4 + +0x44 0x0b 0xbe 0xfe +# CHECK: vcvtp.u32.f64 s0, d4 + +0x44 0x8a 0xff 0xfe +# CHECK: vcvtm.u32.f32 s17, s8 + +0x48 0x8b 0xff 0xfe +# CHECK: vcvtm.u32.f64 s17, d8 + + +0xab 0x2a 0x20 0xfe +# CHECK: vselge.f32 s4, s1, s23 + +0xa7 0xeb 0x6f 0xfe +# CHECK: vselge.f64 d30, d31, d23 + +0x80 0x0a 0x30 0xfe +# CHECK: vselgt.f32 s0, s1, s0 + +0x24 0x5b 0x3a 0xfe +# CHECK: vselgt.f64 d5, d10, d20 + +0x2b 0xfa 0x0e 0xfe +# CHECK: vseleq.f32 s30, s28, s23 + +0x08 0x2b 0x04 0xfe +# CHECK: vseleq.f64 d2, d4, d8 + +0x07 0xaa 0x58 0xfe +# CHECK: vselvs.f32 s21, s16, s14 + +0x2f 0x0b 0x11 0xfe +# CHECK: vselvs.f64 d0, d1, d31 + + +0x00 0x2a 0xc6 0xfe +# CHECK: vmaxnm.f32 s5, s12, s0 + +0xae 0x5b 0x86 0xfe +# CHECK: vmaxnm.f64 d5, d22, d30 + +0x46 0x0a 0x80 0xfe +# CHECK: vminnm.f32 s0, s0, s12 + +0x49 0x4b 0x86 0xfe +# CHECK: vminnm.f64 d4, d6, d9 + + +0xcc 0x3b 0xb6 0xae +# CHECK: vrintzge.f64 d3, d12 + +0xcc 0x1a 0xf6 0xee +# CHECK: vrintz.f32 s3, s24 + +0x40 0x5b 0xb6 0xbe +# CHECK: vrintrlt.f64 d5, d0 + +0x64 0x0a 0xb6 0xee +# CHECK: vrintr.f32 s0, s9 + +0x6e 0xcb 0xf7 0x0e +# CHECK: vrintxeq.f64 d28, d30 + +0x47 0x5a 0xb7 0x6e +# CHECK: vrintxvs.f32 s10, s14 + +0x44 0x3b 0xb8 0xfe +# CHECK: vrinta.f64 d3, d4 + +0x60 0x6a 0xb8 0xfe +# CHECK: vrinta.f32 s12, s1 + +0x44 0x3b 0xb9 0xfe +# CHECK: vrintn.f64 d3, d4 + +0x60 0x6a 0xb9 0xfe +# CHECK: vrintn.f32 s12, s1 + +0x44 0x3b 0xba 0xfe +# CHECK: vrintp.f64 d3, d4 + +0x60 0x6a 0xba 0xfe +# CHECK: vrintp.f32 s12, s1 + +0x44 0x3b 0xbb 0xfe +# CHECK: vrintm.f64 d3, d4 + +0x60 0x6a 0xbb 0xfe +# CHECK: vrintm.f32 s12, s1 |