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* Add a MCAsmInfoELF class and factor some code into it.Rafael Espindola2013-10-162-4/+2
* [AArch64] Add support for NEON scalar signed saturating absolute value andChad Rosier2013-10-151-1/+45
* [AArch64] Add support for NEON scalar integer compare instructions.Chad Rosier2013-10-141-0/+78
* Implement aarch64 neon instruction set AdvSIMD (copy).Kevin Qin2013-10-113-56/+464
* Implement AArch64 vector load/store multiple N-element structure class SIMD(l...Hao Liu2013-10-1011-2/+914
* Revert "Implement AArch64 vector load/store multiple N-element structure clas...Rafael Espindola2013-10-1011-895/+2
* Implement AArch64 vector load/store multiple N-element structure class SIMD(l...Hao Liu2013-10-1011-2/+895
* AArch64: enable MISched by default.Tim Northover2013-10-091-0/+4
* [AArch64] Add support for NEON scalar floating-point reciprocal estimate,Chad Rosier2013-10-081-10/+34
* [AArch64] Add support for NEON scalar signed/unsigned integer to floating-pointChad Rosier2013-10-082-0/+52
* Add a MCTargetStreamer interface.Rafael Espindola2013-10-081-5/+4
* [AArch64] Add support for NEON scalar arithmetic instructions:Chad Rosier2013-10-072-44/+141
* Implement aarch64 neon instruction set AdvSIMD (Across).Jiangning Liu2013-10-052-0/+144
* Implement aarch64 neon instruction set AdvSIMD (3V elem).Jiangning Liu2013-10-046-53/+937
* Initial support for Neon scalar instructions.Jiangning Liu2013-09-246-47/+271
* ISelDAG: spot chain cycles involving MachineNodesTim Northover2013-09-221-0/+1
* Added support for generate DWARF .debug_aranges sections automatically.Richard Mitton2013-09-191-1/+1
* Implement 3 AArch64 neon instructions : umov smov ins.Kevin Qin2013-09-175-14/+468
* AArch64: use RegisterOperand for NEON registers.Tim Northover2013-09-139-271/+230
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-121-2/+3
* Generate compact unwind encoding from CFI directives.Bill Wendling2013-09-092-4/+5
* Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the follow...Jiangning Liu2013-09-092-1/+696
* Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instruc...Hao Liu2013-09-046-38/+805
* Clean up some usage of Triple. The base class has methods for determining if...Cameron Esfahani2013-08-291-1/+1
* A minor change for an obvous problem caused by r188451:Hao Liu2013-08-211-1/+1
* Clang and AArch64 backend patches to support shll/shl and vmovl instructions ...Hao Liu2013-08-154-1/+220
* Update makeLibCall to return both the call and the chain associated with the ...Michael Gottesman2013-08-131-1/+1
* Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for ...NAKAMURA Takumi2013-08-061-0/+2
* AArch64: add initial NEON supportTim Northover2013-08-0117-35/+2649
* AArch64: fix even more JIT failuresTim Northover2013-07-252-4/+4
* Make some arrays 'static const'Craig Topper2013-07-153-43/+51
* Add const qualifier to some static arrays.Craig Topper2013-07-152-6/+6
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector s...Craig Topper2013-07-141-3/+3
* AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and allStephen Lin2013-07-092-5/+26
* Use a OwningPtr instead of a manual delete.Rafael Espindola2013-07-041-5/+3
* Fix leak. Should bring back the valgrind bot.Rafael Espindola2013-07-041-0/+1
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-041-3/+0
* Revert r185595-185596 which broke buildbots.Jakob Stoklund Olesen2013-07-041-0/+3
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-031-3/+0
* Remove address spaces from MC.Rafael Espindola2013-07-023-7/+6
* AArch64: correct CodeGen of MOVZ/MOVK combinations.Tim Northover2013-07-012-10/+14
* The getRegForInlineAsmConstraint function should only accept MVT value types.Chad Rosier2013-06-222-2/+2
* Use pointers to the MCAsmInfo and MCRegInfo.Bill Wendling2013-06-182-6/+6
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineI...David Blaikie2013-06-164-59/+0
* Don't cache the instruction info and register info objects.Bill Wendling2013-06-076-28/+22
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-061-6/+6
* Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha2013-05-311-6/+6
* Order CALLSEQ_START and CALLSEQ_END nodes.Andrew Trick2013-05-291-3/+4
* AArch64: clarify -help messageTim Northover2013-05-281-1/+1
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-253-41/+41
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