| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions. | Craig Topper | 2012-03-25 | 1 | -1/+0 |
| * | remove unused variable | Matt Beaumont-Gay | 2012-03-20 | 1 | -1/+0 |
| * | Require a base pointer for stack realignment when SP may vary dynamically. | Bob Wilson | 2012-03-20 | 1 | -2/+3 |
| * | Remove some redundant checks. | Bob Wilson | 2012-03-20 | 1 | -2/+1 |
| * | Reorder includes to match coding standards. Fix an issue or two exposed by that. | Craig Topper | 2012-03-17 | 1 | -1/+1 |
| * | Split fpscr into two registers: FPSCR and FPSCR_NZCV. | Lang Hames | 2012-03-06 | 1 | -0/+1 |
| * | Use uint16_t instead of unsigned to store registers in reg classes. Reduces s... | Craig Topper | 2012-03-04 | 1 | -13/+13 |
| * | Use uint16_t to store registers in callee saved register tables to reduce siz... | Craig Topper | 2012-03-04 | 1 | -1/+1 |
| * | Enable ARM base pointer when calling functions with large arguments. | Jakob Stoklund Olesen | 2012-02-28 | 1 | -1/+21 |
| * | Remove extra semi-colons. | Chad Rosier | 2012-02-22 | 1 | -1/+1 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -1/+1 |
| * | Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE ba... | Lang Hames | 2012-02-17 | 1 | -1/+0 |
| * | Oop - r150653 + r150654 broke one of my test cases. Backing out for now... | Lang Hames | 2012-02-16 | 1 | -0/+1 |
| * | FPSCR shouldn't be reserved. | Lang Hames | 2012-02-16 | 1 | -1/+0 |
| * | More dead code removal (using -Wunreachable-code) | David Blaikie | 2012-01-20 | 1 | -4/+0 |
| * | Implement ARMBaseRegisterInfo::getCallPreservedMask(). | Jakob Stoklund Olesen | 2012-01-17 | 1 | -19/+5 |
| * | Reapply r146997, "Heed spill slot alignment on ARM." | Jakob Stoklund Olesen | 2012-01-05 | 1 | -1/+1 |
| * | Avoid reserving an ARM base pointer during register allocation. | Jakob Stoklund Olesen | 2012-01-05 | 1 | -2/+17 |
| * | Revert r146997, "Heed spill slot alignment on ARM." | Jakob Stoklund Olesen | 2012-01-03 | 1 | -1/+1 |
| * | Heed spill slot alignment on ARM. | Jakob Stoklund Olesen | 2011-12-20 | 1 | -1/+1 |
| * | ARM target code clean up. Check for iOS, not Darwin where it makes sense. | Evan Cheng | 2011-12-20 | 1 | -3/+3 |
| * | Emit a getMatchingSuperRegClass() implementation for every target. | Jakob Stoklund Olesen | 2011-12-19 | 1 | -98/+0 |
| * | Move global variables in TargetMachine into new TargetOptions class. As an API | Nick Lewycky | 2011-12-02 | 1 | -2/+2 |
| * | Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :( | Chad Rosier | 2011-10-20 | 1 | -2/+5 |
| * | Add support for dynamic stack realignment when in thumb1 mode. | Chad Rosier | 2011-10-18 | 1 | -5/+2 |
| * | Revert r141529. This is causing failures in the test-suite, like bigstack and... | Bill Wendling | 2011-10-11 | 1 | -11/+2 |
| * | When getting the number of bits necessary for addressing mode | Bill Wendling | 2011-10-10 | 1 | -2/+11 |
| * | Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions." | Chad Rosier | 2011-10-01 | 1 | -2/+5 |
| * | Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact | Chad Rosier | 2011-10-01 | 1 | -5/+2 |
| * | Store sub-class lists as a bit vector. | Jakob Stoklund Olesen | 2011-09-30 | 1 | -1/+1 |
| * | Tidy up a bit. | Jim Grosbach | 2011-09-13 | 1 | -152/+78 |
| * | Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical | Evan Cheng | 2011-08-30 | 1 | -0/+7 |
| * | Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode. | Jim Grosbach | 2011-08-24 | 1 | -3/+3 |
| * | Silence a bunch (but not all) "variable written but not read" warnings | Duncan Sands | 2011-08-12 | 1 | -0/+1 |
| * | Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A... | Evan Cheng | 2011-07-20 | 1 | -1/+1 |
| * | Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for | Evan Cheng | 2011-07-18 | 1 | -1/+0 |
| * | Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down | Evan Cheng | 2011-07-18 | 1 | -13/+1 |
| * | Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previ... | Frits van Bommel | 2011-07-18 | 1 | -12/+12 |
| * | Next round of MC refactoring. This patch factor MC table instantiations, MC | Evan Cheng | 2011-07-14 | 1 | -1/+0 |
| * | Remove redundant Thumb2 ADD/SUB SP instruction definitions. | Jim Grosbach | 2011-06-29 | 1 | -4/+0 |
| * | Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. | Evan Cheng | 2011-06-28 | 1 | -2/+1 |
| * | Hide more details in tablegen generated MCRegisterInfo ctor function. | Evan Cheng | 2011-06-28 | 1 | -2/+1 |
| * | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 | 1 | -5/+5 |
| * | More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo. | Evan Cheng | 2011-06-27 | 1 | -1/+1 |
| * | Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc | Evan Cheng | 2011-06-27 | 1 | -1/+3 |
| * | Starting to refactor Target to separate out code that's needed to fully describe | Evan Cheng | 2011-06-24 | 1 | -3/+4 |
| * | Reserve D16-D13 on subtargets that don't support them. | Jakob Stoklund Olesen | 2011-06-18 | 1 | -0/+6 |
| * | Explicitly invoke ArrayRef constructor to keep gcc happy. | Jakob Stoklund Olesen | 2011-06-17 | 1 | -12/+12 |
| * | Rename TRI::getAllocationOrder() to getRawAllocationOrder(). | Jakob Stoklund Olesen | 2011-06-16 | 1 | -38/+22 |
| * | Use the dwarf->llvm mapping to print register names in the cfi | Rafael Espindola | 2011-05-30 | 1 | -0/+4 |
