| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDR... | Silviu Baranga | 2012-03-22 | 1 | -2/+4 |
| * | Added soft fail cases for the disassembler when decoding MUL instructions on ... | Silviu Baranga | 2012-03-22 | 1 | -5/+6 |
| * | Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and ... | Evan Cheng | 2012-03-20 | 1 | -64/+33 |
| * | The ARM instructions that have an unpredictable behavior when the pc register... | Silviu Baranga | 2012-03-20 | 1 | -2/+2 |
| * | Test Commit - add a newline | Richard Barton | 2012-03-20 | 1 | -0/+1 |
| * | ARM optional operand on MRC/MCR assembly instructions. | Jim Grosbach | 2012-03-16 | 1 | -0/+12 |
| * | ARM pre-v6 assembly parsing for umull/smull. | Jim Grosbach | 2012-03-07 | 1 | -0/+10 |
| * | ARM pre-v6 alias for 'nop' to 'mov r0, r0' | Jim Grosbach | 2012-03-07 | 1 | -0/+4 |
| * | updated patch for the ARM fused multiply add/sub | Sebastian Pop | 2012-03-05 | 1 | -3/+3 |
| * | Re-commit r151623 with fix. Only issue special no-return calls if it's a dire... | Evan Cheng | 2012-02-28 | 1 | -0/+19 |
| * | Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack pre... | Daniel Dunbar | 2012-02-28 | 1 | -19/+0 |
| * | Some ARM implementaions, e.g. A-series, does return stack prediction. That is, | Evan Cheng | 2012-02-28 | 1 | -0/+19 |
| * | ARM BL/BLX instruction fixups should use relocations. | Jim Grosbach | 2012-02-27 | 1 | -3/+1 |
| * | Switch ARM target to register masks. | Jakob Stoklund Olesen | 2012-02-24 | 1 | -18/+6 |
| * | Optimize a couple of common patterns involving conditional moves where the false | Evan Cheng | 2012-02-23 | 1 | -0/+67 |
| * | ARM assemly parsing and validation of IT instruction. | Jim Grosbach | 2012-01-25 | 1 | -0/+4 |
| * | Use correct register class for am2offset register operands. | Anton Korobeynikov | 2012-01-24 | 1 | -2/+2 |
| * | Add missed mayStore flag to STREXD / t2STREXD | Anton Korobeynikov | 2012-01-23 | 1 | -3/+3 |
| * | Add fused multiple+add instructions from VFPv4. | Anton Korobeynikov | 2012-01-22 | 1 | -0/+6 |
| * | Use RegisterTuples to generate pseudo-registers. | Jakob Stoklund Olesen | 2012-01-13 | 1 | -7/+14 |
| * | Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138> | Bob Wilson | 2011-12-22 | 1 | -5/+10 |
| * | Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp. | Bob Wilson | 2011-12-22 | 1 | -1/+1 |
| * | Fix a couple of copy-n-paste bugs. Noticed by George Russell! | Chad Rosier | 2011-12-21 | 1 | -4/+4 |
| * | Fix a couple of copy-n-paste bugs. Noticed by George Russell. | Evan Cheng | 2011-12-21 | 1 | -2/+2 |
| * | ARM target code clean up. Check for iOS, not Darwin where it makes sense. | Evan Cheng | 2011-12-20 | 1 | -36/+36 |
| * | Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930. | Bob Wilson | 2011-12-20 | 1 | -2/+5 |
| * | Fix copy/pasto that skipped the 'modify' step. | Jim Grosbach | 2011-12-14 | 1 | -4/+4 |
| * | ARM/Thumb2 mov vs. mvn alias goes both ways. | Jim Grosbach | 2011-12-14 | 1 | -0/+2 |
| * | ARM/Thumb2 'cmp rn, #imm' alias to cmn. | Jim Grosbach | 2011-12-14 | 1 | -0/+5 |
| * | ARM LDM/STM system instruction variants. | Jim Grosbach | 2011-12-13 | 1 | -11/+31 |
| * | ARM pre-UAL NEG mnemonic for convenience when porting old code. | Jim Grosbach | 2011-12-13 | 1 | -0/+4 |
| * | ARM assembly aliases for BIC<-->AND (immediate). | Jim Grosbach | 2011-12-09 | 1 | -0/+14 |
| * | ARM NEON two-operand aliases for VSHL(immediate). | Jim Grosbach | 2011-12-08 | 1 | -0/+8 |
| * | ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm". | Jim Grosbach | 2011-12-08 | 1 | -5/+11 |
| * | ARM: NEON SHLL instruction immediate operand range checking. | Jim Grosbach | 2011-12-07 | 1 | -5/+36 |
| * | ARM mode 'mul' operand ordering tweak. | Jim Grosbach | 2011-12-06 | 1 | -1/+1 |
| * | ARM NEON VEXT aliases for data type suffices. | Jim Grosbach | 2011-12-02 | 1 | -0/+8 |
| * | ARM parsing aliases for VLD1 single register all lanes. | Jim Grosbach | 2011-11-30 | 1 | -0/+3 |
| * | ARM assembly parsing for shifted register operands for MOV instruction. | Jim Grosbach | 2011-11-16 | 1 | -0/+2 |
| * | ARM assmebly two operand forms for LSR, ASR, LSL, ROR register. | Jim Grosbach | 2011-11-16 | 1 | -0/+12 |
| * | ARM assembly parsing for RRX mnemonic. | Jim Grosbach | 2011-11-16 | 1 | -0/+2 |
| * | ARM mode aliases for bitwise instructions w/ register operands. | Jim Grosbach | 2011-11-16 | 1 | -0/+12 |
| * | Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup. | Bob Wilson | 2011-11-16 | 1 | -1/+1 |
| * | Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602> | Bob Wilson | 2011-11-16 | 1 | -9/+1 |
| * | ARM assembly parsing two operand forms for shift instructions. | Jim Grosbach | 2011-11-15 | 1 | -0/+10 |
| * | ARM assembly parsing for two-operand form of 'mul' instruction. | Jim Grosbach | 2011-11-15 | 1 | -0/+4 |
| * | Fix typo in comment. | Jay Foad | 2011-11-15 | 1 | -1/+1 |
| * | ARM refactor simple immediate asm operand render methods. | Jim Grosbach | 2011-11-12 | 1 | -16/+19 |
| * | ARM assembly parsing for LSR/LSL/ROR(immediate). | Jim Grosbach | 2011-11-10 | 1 | -1/+18 |
| * | ARM assembly parsing for ASR(immediate). | Jim Grosbach | 2011-11-10 | 1 | -0/+9 |
