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path: root/lib/Target/ARM/ARMInstrInfo.td
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* Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDR...Silviu Baranga2012-03-221-2/+4
* Added soft fail cases for the disassembler when decoding MUL instructions on ...Silviu Baranga2012-03-221-5/+6
* Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and ...Evan Cheng2012-03-201-64/+33
* The ARM instructions that have an unpredictable behavior when the pc register...Silviu Baranga2012-03-201-2/+2
* Test Commit - add a newlineRichard Barton2012-03-201-0/+1
* ARM optional operand on MRC/MCR assembly instructions.Jim Grosbach2012-03-161-0/+12
* ARM pre-v6 assembly parsing for umull/smull.Jim Grosbach2012-03-071-0/+10
* ARM pre-v6 alias for 'nop' to 'mov r0, r0'Jim Grosbach2012-03-071-0/+4
* updated patch for the ARM fused multiply add/subSebastian Pop2012-03-051-3/+3
* Re-commit r151623 with fix. Only issue special no-return calls if it's a dire...Evan Cheng2012-02-281-0/+19
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack pre...Daniel Dunbar2012-02-281-19/+0
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-281-0/+19
* ARM BL/BLX instruction fixups should use relocations.Jim Grosbach2012-02-271-3/+1
* Switch ARM target to register masks.Jakob Stoklund Olesen2012-02-241-18/+6
* Optimize a couple of common patterns involving conditional moves where the falseEvan Cheng2012-02-231-0/+67
* ARM assemly parsing and validation of IT instruction.Jim Grosbach2012-01-251-0/+4
* Use correct register class for am2offset register operands.Anton Korobeynikov2012-01-241-2/+2
* Add missed mayStore flag to STREXD / t2STREXDAnton Korobeynikov2012-01-231-3/+3
* Add fused multiple+add instructions from VFPv4.Anton Korobeynikov2012-01-221-0/+6
* Use RegisterTuples to generate pseudo-registers.Jakob Stoklund Olesen2012-01-131-7/+14
* Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>Bob Wilson2011-12-221-5/+10
* Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp.Bob Wilson2011-12-221-1/+1
* Fix a couple of copy-n-paste bugs. Noticed by George Russell!Chad Rosier2011-12-211-4/+4
* Fix a couple of copy-n-paste bugs. Noticed by George Russell.Evan Cheng2011-12-211-2/+2
* ARM target code clean up. Check for iOS, not Darwin where it makes sense.Evan Cheng2011-12-201-36/+36
* Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.Bob Wilson2011-12-201-2/+5
* Fix copy/pasto that skipped the 'modify' step.Jim Grosbach2011-12-141-4/+4
* ARM/Thumb2 mov vs. mvn alias goes both ways.Jim Grosbach2011-12-141-0/+2
* ARM/Thumb2 'cmp rn, #imm' alias to cmn.Jim Grosbach2011-12-141-0/+5
* ARM LDM/STM system instruction variants.Jim Grosbach2011-12-131-11/+31
* ARM pre-UAL NEG mnemonic for convenience when porting old code.Jim Grosbach2011-12-131-0/+4
* ARM assembly aliases for BIC<-->AND (immediate).Jim Grosbach2011-12-091-0/+14
* ARM NEON two-operand aliases for VSHL(immediate).Jim Grosbach2011-12-081-0/+8
* ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".Jim Grosbach2011-12-081-5/+11
* ARM: NEON SHLL instruction immediate operand range checking.Jim Grosbach2011-12-071-5/+36
* ARM mode 'mul' operand ordering tweak.Jim Grosbach2011-12-061-1/+1
* ARM NEON VEXT aliases for data type suffices.Jim Grosbach2011-12-021-0/+8
* ARM parsing aliases for VLD1 single register all lanes.Jim Grosbach2011-11-301-0/+3
* ARM assembly parsing for shifted register operands for MOV instruction.Jim Grosbach2011-11-161-0/+2
* ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.Jim Grosbach2011-11-161-0/+12
* ARM assembly parsing for RRX mnemonic.Jim Grosbach2011-11-161-0/+2
* ARM mode aliases for bitwise instructions w/ register operands.Jim Grosbach2011-11-161-0/+12
* Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.Bob Wilson2011-11-161-1/+1
* Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>Bob Wilson2011-11-161-9/+1
* ARM assembly parsing two operand forms for shift instructions.Jim Grosbach2011-11-151-0/+10
* ARM assembly parsing for two-operand form of 'mul' instruction.Jim Grosbach2011-11-151-0/+4
* Fix typo in comment.Jay Foad2011-11-151-1/+1
* ARM refactor simple immediate asm operand render methods.Jim Grosbach2011-11-121-16/+19
* ARM assembly parsing for LSR/LSL/ROR(immediate).Jim Grosbach2011-11-101-1/+18
* ARM assembly parsing for ASR(immediate).Jim Grosbach2011-11-101-0/+9