| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Add a way to define the bit range covered by a SubRegIndex. | Ahmed Bougacha | 2013-05-31 | 1 | -23/+23 |
| * | The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instruction... | Mihai Popa | 2013-05-13 | 1 | -6/+19 |
| * | Add GPRPair Register class to ARM. | Jakob Stoklund Olesen | 2012-10-26 | 1 | -0/+14 |
| * | Add LLVM support for Swift. | Bob Wilson | 2012-09-29 | 1 | -2/+7 |
| * | This field isn't used anymore, use it with HWEncoding instead. | Eric Christopher | 2012-08-09 | 1 | -4/+4 |
| * | Remove the SubRegClasses field from RegisterClass descriptions. | Jakob Stoklund Olesen | 2012-05-04 | 1 | -20/+4 |
| * | Prefer even-odd D-register pairs. | Jakob Stoklund Olesen | 2012-03-29 | 1 | -1/+2 |
| * | ARM vmrs system registers mvfr0 and mvfr1 handling. | Jim Grosbach | 2012-03-16 | 1 | -0/+2 |
| * | Allow the same types in DPair as in QPR. | Jakob Stoklund Olesen | 2012-03-06 | 1 | -1/+2 |
| * | Split fpscr into two registers: FPSCR and FPSCR_NZCV. | Lang Hames | 2012-03-06 | 1 | -5/+10 |
| * | ARM refactor away a bunch of VLD/VST pseudo instructions. | Jim Grosbach | 2012-03-05 | 1 | -1/+5 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -1/+1 |
| * | Add pseudo-registers for pairs, triples, and quads of D registers. | Jakob Stoklund Olesen | 2012-02-02 | 1 | -15/+70 |
| * | Move ARM subreg index compositions to the SubRegIndex itself. | Jakob Stoklund Olesen | 2012-02-01 | 1 | -28/+22 |
| * | Add a CoveredBySubRegs property to Register descriptions. | Jakob Stoklund Olesen | 2012-01-18 | 1 | -0/+2 |
| * | Use RegisterTuples to generate pseudo-registers. | Jakob Stoklund Olesen | 2012-01-13 | 1 | -32/+24 |
| * | Remove a register class that can just as well be synthesized. | Jakob Stoklund Olesen | 2011-12-19 | 1 | -8/+0 |
| * | Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical | Evan Cheng | 2011-08-30 | 1 | -0/+1 |
| * | Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode. | Jim Grosbach | 2011-08-24 | 1 | -0/+7 |
| * | Create a new register class for the set of all GPRs except the PC. Use it to... | Owen Anderson | 2011-08-09 | 1 | -0/+10 |
| * | ARM assembly parsing of MRS instruction. | Jim Grosbach | 2011-07-19 | 1 | -2/+4 |
| * | Add support for the 'h' constraint. | Eric Christopher | 2011-06-30 | 1 | -0/+3 |
| * | Switch ARM to using AltOrders instead of MethodBodies. | Jakob Stoklund Olesen | 2011-06-18 | 1 | -223/+26 |
| * | Use set operations instead of plain lists to enumerate register classes. | Jakob Stoklund Olesen | 2011-06-15 | 1 | -36/+17 |
| * | Flag unallocatable register classes instead of giving them empty | Jakob Stoklund Olesen | 2011-06-02 | 1 | -1/+3 |
| * | Eliminate the ARM sub-register indexes that are not needed by the sources. | Jakob Stoklund Olesen | 2011-05-07 | 1 | -33/+6 |
| * | As per ARM docs, register Dx is described as DW_OP_regx(256+x) in DWARF. | Devang Patel | 2011-04-21 | 1 | -24/+32 |
| * | Prefer cheap registers for busy live ranges. | Jakob Stoklund Olesen | 2011-04-20 | 1 | -0/+3 |
| * | Sorry, several patches in one. | Evan Cheng | 2011-01-20 | 1 | -1/+1 |
| * | Create two new generic classes to represent the following VMRS/VMSR variations: | Bruno Cardoso Lopes | 2011-01-18 | 1 | -0/+4 |
| * | PR8359: The ARM backend may end up allocating registers D16 to D31 when | Bob Wilson | 2010-10-12 | 1 | -3/+3 |
| * | Change register allocation order for ARM VFP and NEON registers to put the | Bob Wilson | 2010-10-08 | 1 | -6/+72 |
| * | Now that register allocation properly considers reserved regs, simplify the | Jim Grosbach | 2010-09-02 | 1 | -154/+18 |
| * | trivial cleanup | Jim Grosbach | 2010-09-02 | 1 | -4/+2 |
| * | Simplify the tGPR register class now that the register allocators know not | Jim Grosbach | 2010-09-01 | 1 | -26/+1 |
| * | fix emacs language spec's, patch by Edmund Grimley-Evans! | Chris Lattner | 2010-08-17 | 1 | -1/+1 |
| * | Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function... | Evan Cheng | 2010-08-10 | 1 | -11/+5 |
| * | Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP | Daniel Dunbar | 2010-08-10 | 1 | -5/+11 |
| * | Fix ARM hasFP() semantics. It should return true whenever FP register is | Evan Cheng | 2010-08-10 | 1 | -11/+5 |
| * | Many Thumb2 instructions can reference the full ARM register set (i.e., | Jim Grosbach | 2010-07-30 | 1 | -0/+109 |
| * | Clean up a comment. | Bob Wilson | 2010-07-08 | 1 | -5/+5 |
| * | Fix PR 7433. Silly typo in non-Darwin ARM tail call | Dale Johannesen | 2010-06-21 | 1 | -16/+6 |
| * | Allow ARM if-converter to be run after post allocation scheduling. | Evan Cheng | 2010-06-18 | 1 | -4/+3 |
| * | Next round of tail call changes. Register used in a tail | Dale Johannesen | 2010-06-15 | 1 | -0/+77 |
| * | Clean up 80 column violations. No functional change. | Jim Grosbach | 2010-06-02 | 1 | -1/+2 |
| * | Give SubRegIndex names to all ARM subregisters. This will be required by | Jakob Stoklund Olesen | 2010-05-26 | 1 | -14/+36 |
| * | Replace the SubRegSet tablegen class with a less error-prone mechanism. | Jakob Stoklund Olesen | 2010-05-26 | 1 | -99/+20 |
| * | Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." | Jakob Stoklund Olesen | 2010-05-26 | 1 | -20/+99 |
| * | Replace the SubRegSet tablegen class with a less error-prone mechanism. | Jakob Stoklund Olesen | 2010-05-26 | 1 | -99/+20 |
| * | Remove NumberHack entirely. | Jakob Stoklund Olesen | 2010-05-25 | 1 | -21/+21 |
