| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | ARM sched model: Add integer VFP/SIMD instructions on Swift | Arnold Schwaighofer | 2013-06-06 | 1 | -0/+3 |
| * | ARM sched model: Add divsion, loads, branches, vfp cvt | Arnold Schwaighofer | 2013-06-05 | 1 | -0/+15 |
| * | Revert series of sched model patches until I figure out what is going on. | Arnold Schwaighofer | 2013-06-04 | 1 | -15/+0 |
| * | ARM sched model: Add divsion, loads, branches, vfp cvt | Arnold Schwaighofer | 2013-06-04 | 1 | -0/+15 |
| * | ARM scheduler model: Add scheduler info to more instructions and resource | Arnold Schwaighofer | 2013-04-05 | 1 | -0/+5 |
| * | ARM scheduler model: Swift has varying latencies, uops for simple ALU ops | Arnold Schwaighofer | 2013-04-05 | 1 | -0/+2 |
| * | ARM Scheduler Model: Add resources instructions, map resources in subtargets | Arnold Schwaighofer | 2013-04-01 | 1 | -2/+9 |
| * | Revert ARM Scheduler Model: Add resources instructions, map resources | Arnold Schwaighofer | 2013-03-26 | 1 | -7/+0 |
| * | ARM Scheduler Model: Add resources instructions, map resources in subtargets | Arnold Schwaighofer | 2013-03-26 | 1 | -0/+7 |
| * | ARM Scheduler Model: Partial implementation of the new machine scheduler model | Arnold Schwaighofer | 2013-03-26 | 1 | -0/+57 |
| * | Add LLVM support for Swift. | Bob Wilson | 2012-09-29 | 1 | -0/+2 |
| * | Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." | Andrew Trick | 2012-07-02 | 1 | -11/+11 |
| * | Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary." | Andrew Trick | 2012-06-29 | 1 | -11/+11 |
| * | Make NumMicroOps a variable in the subtarget's instruction itinerary. | Andrew Trick | 2012-06-29 | 1 | -11/+11 |
| * | Use "NoItineraries" for processors with no itineraries. | Andrew Trick | 2012-06-22 | 1 | -2/+0 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -3/+3 |
| * | Add fused multiple+add instructions from VFPv4. | Anton Korobeynikov | 2012-01-22 | 1 | -0/+4 |
| * | Sorry, several patches in one. | Evan Cheng | 2011-01-20 | 1 | -0/+2 |
| * | Add support for NEON VLD3-dup instructions. | Bob Wilson | 2010-11-30 | 1 | -0/+2 |
| * | Add support for NEON VLD3-dup instructions. | Bob Wilson | 2010-11-29 | 1 | -0/+2 |
| * | Add support for NEON VLD2-dup instructions. | Bob Wilson | 2010-11-28 | 1 | -0/+2 |
| * | Add NEON VLD1-dup instructions (load 1 element to all lanes). | Bob Wilson | 2010-11-27 | 1 | -0/+2 |
| * | Conditional moves are slightly more expensive than moves. | Evan Cheng | 2010-11-13 | 1 | -0/+1 |
| * | Fix preload instruction isel. Only v7 supports pli, and only v7 with mp exten... | Evan Cheng | 2010-11-03 | 1 | -0/+1 |
| * | Add NEON VST1-lane instructions. Partial fix for Radar 8599955. | Bob Wilson | 2010-11-02 | 1 | -0/+2 |
| * | Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. | Bob Wilson | 2010-11-01 | 1 | -0/+2 |
| * | More ARM scheduling itinerary fixes. | Evan Cheng | 2010-10-11 | 1 | -0/+3 |
| * | Proper VST scheduling itineraries. | Evan Cheng | 2010-10-11 | 1 | -1/+22 |
| * | Add VLD4 scheduling itineraries. | Evan Cheng | 2010-10-09 | 1 | -0/+3 |
| * | Finish vld3 and vld4. | Evan Cheng | 2010-10-09 | 1 | -0/+3 |
| * | Correct some load / store instruction itinerary mistakes: | Evan Cheng | 2010-10-09 | 1 | -0/+12 |
| * | Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vld... | Evan Cheng | 2010-10-07 | 1 | -2/+4 |
| * | - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This | Evan Cheng | 2010-10-06 | 1 | -3/+7 |
| * | NEON scheduling info fix. vmov reg, reg are single cycle instructions. | Evan Cheng | 2010-10-01 | 1 | -0/+2 |
| * | ARM instruction itinerary fixes: | Evan Cheng | 2010-09-30 | 1 | -12/+30 |
| * | Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP | Evan Cheng | 2010-09-29 | 1 | -0/+1 |
| * | Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. | Evan Cheng | 2010-09-29 | 1 | -1/+9 |
| * | Assign bitwise binary instructions different itinerary classes from ALU instr... | Evan Cheng | 2010-09-29 | 1 | -0/+5 |
| * | Add support to model pipeline bypass / forwarding. | Evan Cheng | 2010-09-28 | 1 | -1/+1 |
| * | Remove a unused instruction itinerary class. | Evan Cheng | 2010-09-25 | 1 | -1/+0 |
| * | Fix zero and sign extension instructions scheduling itineraries. | Evan Cheng | 2010-09-25 | 1 | -0/+2 |
| * | More pseudo instruction scheduling itinerary fixes. | Evan Cheng | 2010-09-24 | 1 | -0/+1 |
| * | Fix scheduling itinerary for pseudo mov immediate instructions which expand i... | Evan Cheng | 2010-09-24 | 1 | -0/+1 |
| * | For each instruction itinerary class, specify the number of micro-ops each | Evan Cheng | 2010-09-09 | 1 | -5/+5 |
| * | Fix LDM_RET schedule itinery. | Evan Cheng | 2010-09-08 | 1 | -0/+1 |
| * | Make processor FUs unique for given itinerary. This extends the limit of 32 | Anton Korobeynikov | 2010-04-18 | 1 | -15/+1 |
| * | Split A8/A9 itins - they already were too big. | Anton Korobeynikov | 2010-04-07 | 1 | -1/+2 |
| * | Fix itins for VABA | Anton Korobeynikov | 2010-04-07 | 1 | -0/+2 |
| * | VHADD differs from VHSUB at least on A9 - the former reads both operands in t... | Anton Korobeynikov | 2010-04-07 | 1 | -0/+2 |
| * | Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON op... | Anton Korobeynikov | 2010-04-07 | 1 | -0/+4 |
