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* Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes ↵Silviu Baranga2013-09-041-78/+54
| | | | | | on Cortex-A9. This also makes the existing code more compact. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189958 91177308-0d34-0410-b5e6-96231b3b80d8
* Update machine models. Specify buffer sizes for OOO processors.Andrew Trick2013-06-151-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184033 91177308-0d34-0410-b5e6-96231b3b80d8
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-151-4/+1
| | | | | | | | | | | | | Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM sched model: Add integer VFP/SIMD instructions on SwiftArnold Schwaighofer2013-06-061-0/+1
| | | | | | Reapply 183269. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183441 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM sched model: Cortex A9 - More InstRW sched resourcesArnold Schwaighofer2013-06-061-4/+45
| | | | | | | | Add more InstRW mappings. Reapply 183266. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183435 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM sched model: Add divsion, loads, branches, vfp cvtArnold Schwaighofer2013-06-051-0/+7
| | | | | | | | Add some generic SchedWrites and assign resources for Swift and Cortex A9. Reapply of r183257. (Removed empty InstRW for division on swift) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183319 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer2013-06-041-52/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183273 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM sched model: Cortex A9 - More InstRW sched resourcesArnold Schwaighofer2013-06-041-4/+45
| | | | | | Add more InstRW mappings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183266 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM sched model: Add divsion, loads, branches, vfp cvtArnold Schwaighofer2013-06-041-0/+7
| | | | | | Add some generic SchedWrites and assign resources for Swift and Cortex A9. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183257 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM scheduler model: Add scheduler info to more instructions and resourceArnold Schwaighofer2013-04-051-7/+13
| | | | | | descriptions for compares git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178844 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM Scheduler Model: Add resources instructions, map resources in subtargetsArnold Schwaighofer2013-04-011-23/+24
| | | | | | | | | | | | | Reapply r177968: After commit 178074 we can now have undefined scheduler variants. Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. Incooperate Andrew's feedback. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178460 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert ARM Scheduler Model: Add resources instructions, map resourcesArnold Schwaighofer2013-03-261-11/+8
| | | | | | | | | | | | | This reverts commit r177968. It is causing failures in a local build bot. "fatal error: error in backend: Expected a variant SchedClass" Original commit message: Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178028 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM Scheduler Model: Add resources instructions, map resources in subtargetsArnold Schwaighofer2013-03-261-8/+11
| | | | | | | | Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define resource mappings under the CortexA9 SchedModel. Define resources and mappings for the SwiftModel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177968 91177308-0d34-0410-b5e6-96231b3b80d8
* MIsched: add an ILP window property to machine model.Andrew Trick2013-01-091-0/+3
| | | | | | | | | | This was an experimental option, but needs to be defined per-target. e.g. PPC A2 needs to aggressively hide latency. I converted some in-order scheduling tests to A2. Hal is working on more test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
* Cortex-A9 latency fixes (w/ -schedmodel only).Andrew Trick2012-09-211-5/+5
| | | | | | Quick review against the manual revealed a few obvious mistakes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164361 91177308-0d34-0410-b5e6-96231b3b80d8
* Cortex-A9 instruction-level scheduling machine model.Andrew Trick2012-09-141-3/+594
| | | | | | | | | | | | | | | | | | | | This models the A9 processor at the level of instruction operands, as opposed to the itinerary, which models each operation at the level of pipeline stages. The two primary motivations are: 1) Allow MachineScheduler to model A9 as an out-of-order processor. It can now distinguish between hazards that force interlocking vs. buffered resources. 2) Reduce long-term maintenance by allowing the itinerary and target hooks to eventually be removed. Note that almost all of the complexity in the new model exists to model instruction variants, which the itinerary cannot handle. Instead the scheduler previously relied on processor-specific target hooks which are incomplete and buggy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163921 91177308-0d34-0410-b5e6-96231b3b80d8
* Added MispredictPenalty to SchedMachineModel.Andrew Trick2012-08-081-0/+1
| | | | | | | This replaces an existing subtarget hook on ARM and allows standard CodeGen passes to potentially use the property. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-071-5/+23
| | | | | | | | | | | | | | | | | | | | | | | subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick2012-07-021-13/+22
| | | | | | Reapplies r159406 with minor cleanup. The regressions appear to have been spurious. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159541 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary."Andrew Trick2012-06-291-22/+13
| | | | | | This reverts commit r159406. I noticed a performance regression so I'll back out for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159411 91177308-0d34-0410-b5e6-96231b3b80d8
* Make NumMicroOps a variable in the subtarget's instruction itinerary.Andrew Trick2012-06-291-13/+22
| | | | | | | | | | | | | | The TargetInstrInfo::getNumMicroOps API does not change, but soon it will be used by MachineScheduler. Now each subtarget can specify the number of micro-ops per itinerary class. For ARM, this is currently always dynamic (-1), because it is used for load/store multiple which depends on the number of register operands. Zero is now a valid number of micro-ops. This can be used for nop pseudo-instructions or instructions that the hardware can squash during dispatch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159406 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM itinerary properties.Andrew Trick2012-06-051-1/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157980 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a number of problems with ARM fused multiply add/subtract instructions.Evan Cheng2012-04-111-0/+36
| | | | | | | | | | | 1. The new instruction itinerary entries are not properly described. 2. The asm parser can't handle vfms and vfnms. 3. There were no assembler, disassembler test cases. 4. HasNEON2 has the wrong assembler predicate. rdar://10139676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154456 91177308-0d34-0410-b5e6-96231b3b80d8
* Improvements for the Cortex-A9 scheduling itineraries.Bob Wilson2011-04-191-12/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129770 91177308-0d34-0410-b5e6-96231b3b80d8
* Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". ThatEvan Cheng2011-04-191-172/+171
| | | | | | | | | | is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129742 91177308-0d34-0410-b5e6-96231b3b80d8
* Sorry, several patches in one.Evan Cheng2011-01-201-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the ARM IIC_iCMPsi itinerary and add an important assert.Andrew Trick2011-01-041-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122794 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an obvious cut-n-paste error.Evan Cheng2010-12-081-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121307 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for NEON VLD3-dup instructions.Bob Wilson2010-11-301-0/+18
| | | | | | The encoding for alignment in VLD4-dup instructions is still a work in progress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120356 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for NEON VLD3-dup instructions.Bob Wilson2010-11-291-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120312 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix copy-and-paste errors in VLD2-dup scheduling itineraries.Bob Wilson2010-11-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120311 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for NEON VLD2-dup instructions.Bob Wilson2010-11-281-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120236 91177308-0d34-0410-b5e6-96231b3b80d8
* Add NEON VLD1-dup instructions (load 1 element to all lanes).Bob Wilson2010-11-271-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120194 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions.Bob Wilson2010-11-271-4/+4
| | | | | | | | I added these instructions recently but I have no idea where these "1" values in the NextCycles field came from. As far as I can tell now, these instruction stages are clearly intended to overlap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120193 91177308-0d34-0410-b5e6-96231b3b80d8
* Conditional moves are slightly more expensive than moves.Evan Cheng2010-11-131-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118985 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix preload instruction isel. Only v7 supports pli, and only v7 with mp ↵Evan Cheng2010-11-031-0/+4
| | | | | | extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify scheduling itineraries to correct instruction latencies (not operandEvan Cheng2010-11-031-77/+77
| | | | | | | latencies) of loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118134 91177308-0d34-0410-b5e6-96231b3b80d8
* Add NEON VST1-lane instructions. Partial fix for Radar 8599955.Bob Wilson2010-11-021-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118069 91177308-0d34-0410-b5e6-96231b3b80d8
* Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.Bob Wilson2010-11-011-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117964 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix fpscr <-> GPR latency info.Evan Cheng2010-10-291-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117737 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng2010-10-281-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ↵Evan Cheng2010-10-281-2/+2
| | | | | | to fail. Ugh. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117520 91177308-0d34-0410-b5e6-96231b3b80d8
* - Assign load / store with shifter op address modes the right itinerary classes.Evan Cheng2010-10-281-2/+2
| | | | | | | | | | | - For now, loads of [r, r] addressing mode is the same as the [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should identify the former case and reduce the output latency by 1. - Also identify [r, r << 2] case. This special form of shifter addressing mode is "free". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
* putback r116983 and fix simple-fp-encoding.ll testsAndrew Trick2010-10-211-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116992 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r116983, which is breaking all the buildbots.Owen Anderson2010-10-211-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116987 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing scheduling itineraries for transfers between core registers and ↵Evan Cheng2010-10-211-4/+4
| | | | | | VFP registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116983 91177308-0d34-0410-b5e6-96231b3b80d8
* Limit load / store issues (at least until we have a true multi-issue aware ↵Evan Cheng2010-10-131-107/+158
| | | | | | scheduler). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116389 91177308-0d34-0410-b5e6-96231b3b80d8
* More ARM scheduling itinerary fixes.Evan Cheng2010-10-111-372/+439
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116266 91177308-0d34-0410-b5e6-96231b3b80d8
* Proper VST scheduling itineraries.Evan Cheng2010-10-111-7/+131
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116251 91177308-0d34-0410-b5e6-96231b3b80d8
* Add VLD4 scheduling itineraries.Evan Cheng2010-10-091-5/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116143 91177308-0d34-0410-b5e6-96231b3b80d8
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