aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/ARM/Disassembler
Commit message (Expand)AuthorAgeFilesLines
* ARM: add fstmx and fldmx instructions for assemblyTim Northover2013-05-311-2/+15
* Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.Michael J. Spencer2013-05-241-1/+1
* Remove the Copied parameter from MemoryObject::readBytes.Benjamin Kramer2013-05-241-3/+3
* Add MCSymbolizer for symbolic/annotated disassembly.Ahmed Bougacha2013-05-241-107/+4
* VSTn instructions have a number of encoding constraints which are not impleme...Mihai Popa2013-05-201-0/+51
* Q registers are encoded in fields of the same length as D registers. As Q reg...Mihai Popa2013-05-201-1/+1
* Replace some bit operations with simpler ones. No functionality change.Benjamin Kramer2013-05-191-1/+1
* The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instruction...Mihai Popa2013-05-131-0/+18
* ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet2013-04-261-4/+6
* ARM: Permit "sp" in ARM variant of STREXD instructionsTim Northover2013-04-191-1/+1
* ARM: permit "sp" in ARM variants of MOVW/MOVT instructionsTim Northover2013-04-191-2/+3
* Fix treatment of ARM unallocated hint instructions.Quentin Colombet2013-04-171-0/+11
* Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when th...Gordon Keiser2013-03-281-2/+2
* Patch by Gordon Keiser!Joe Abbey2013-03-261-1/+1
* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-191-16/+0
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-6/+6
* Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInstKevin Enderby2012-11-291-1/+7
* Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch targetKevin Enderby2012-10-291-9/+21
* Fix a bug where a 32-bit address with the high bit does not get symbolicatedKevin Enderby2012-10-181-2/+3
* Fix the handling of edge cases in ARM shifted operands.Tim Northover2012-09-221-0/+5
* Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover2012-09-061-0/+4
* Check for invalid alignment values when decoding VLDn/VSTn (single ln) instru...Tim Northover2012-09-061-8/+38
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-241-1/+1
* Remove unnecessary include of ARMGenInstrInfo.inc.Craig Topper2012-08-171-1/+0
* Switch the fixed-length disassembler to be table-driven.Jim Grosbach2012-08-141-411/+425
* Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ...Jiangning Liu2012-08-021-3/+8
* Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.Jiangning Liu2012-08-021-12/+1
* Fix a typo (the the => the)Sylvestre Ledru2012-07-231-1/+1
* Fix instruction description of VMOV (between two ARM core registers and two s...Richard Barton2012-07-101-4/+4
* Revert r159938 (and r159945) to appease the buildbots.Chad Rosier2012-07-091-4/+4
* Oops - correct broken disassembly for VMOVRichard Barton2012-07-091-1/+1
* Fix instruction description of VMOV (between two ARM core registers and two s...Richard Barton2012-07-091-4/+4
* Correct decoder for T1 conditional B encodingRichard Barton2012-06-061-2/+2
* ARMDisassembler.cpp: Fix utf8 char in comments.NAKAMURA Takumi2012-05-221-3/+3
* Tweak to the fix in r156212, as with the change in removing the shift theKevin Enderby2012-05-041-1/+1
* Fix a bug in the ARM disassembler for wide branch conditional instructionsKevin Enderby2012-05-041-1/+1
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-031-4/+34
* Fixed disassembler for vstm/vldm ARM VFP instructions.Silviu Baranga2012-05-031-4/+6
* ARM: Tweak tADDrSP definition for consistent operand order.Jim Grosbach2012-04-271-1/+1
* Refactor IT handling not to store the bottom bit of the condition code in the...Richard Barton2012-04-271-8/+3
* Refactor Thumb ITState handling in ARM Disassembler to more efficiently use i...Richard Barton2012-04-241-31/+69
* Added support for disassembling unpredictable swp/swpb ARM instructions.Silviu Baranga2012-04-181-0/+4
* Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the ...Silviu Baranga2012-04-181-0/+30
* Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)Kevin Enderby2012-04-171-7/+1
* Fix a few more places in the ARM disassembler so that branches getKevin Enderby2012-04-121-4/+29
* Fixed a case of ARM disassembly getting an assert on a bad encodingKevin Enderby2012-04-111-0/+2
* Fix ARM disassembly of VLD instructions with writebacks.  And add test a caseKevin Enderby2012-04-111-0/+12
* ARMDisassembler: drop bogus dependency on ARMCodeGenDylan Noblesmith2012-04-032-3/+2
* Remove unnecessary llvm:: qualificationsCraig Topper2012-03-271-209/+209
* Added soft fail checks for the disassembler when decoding some corner cases o...Silviu Baranga2012-03-221-1/+81
generated by cgit v1.1 at 2025-02-11 05:05:19 +0000