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path: root/lib/Target/Alpha/AlphaRegisterInfo.cpp
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* - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but o...Evan Cheng2007-10-181-2/+2
* Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister p...Evan Cheng2007-10-181-4/+4
* - Added a few target hooks to generate load / store instructions from / to anyEvan Cheng2007-10-051-0/+50
* Allow copyRegToReg to emit cross register classes copies.Evan Cheng2007-09-261-4/+10
* Long live the exception handling!Anton Korobeynikov2007-07-141-2/+3
* eliminateFrameIndex() change.Evan Cheng2007-05-011-1/+3
* Removed tabs everywhere except autogenerated & external files. Add makeAnton Korobeynikov2007-04-161-10/+10
* Added MRegisterInfo hook to re-materialize an instruction.Evan Cheng2007-03-201-0/+9
* PEI now passes a RegScavenger ptr to eliminateFrameIndex.Evan Cheng2007-02-281-2/+2
* By default, spills kills the register being stored.Evan Cheng2007-02-231-3/+6
* Support to provide exception and selector registers.Jim Laskey2007-02-211-0/+10
* Re-apply my liveintervalanalysis changes. Now with PR1207 fixes.Evan Cheng2007-02-191-0/+9
* For PR1207:Reid Spencer2007-02-191-9/+0
* Added getReservedRegs().Evan Cheng2007-02-171-0/+9
* PEI is now responsible for adding MaxCallFrameSize to frame size and align th...Evan Cheng2007-01-231-10/+0
* hasFP() is now a virtual method of MRegisterInfo.Evan Cheng2007-01-231-1/+1
* Fix naming inconsistency.Evan Cheng2007-01-021-6/+6
* What should be the last unnecessary <iostream>s in the library.Bill Wendling2006-12-071-17/+16
* Change MachineInstr ctor's to take a TargetInstrDescriptor reference insteadEvan Cheng2006-11-271-27/+28
* Properly transfer kill / dead info.Evan Cheng2006-11-151-2/+5
* Matches MachineInstr changes.Evan Cheng2006-11-131-7/+8
* silence warnings.Chris Lattner2006-11-031-6/+0
* more shotenningAndrew Lenharth2006-10-311-6/+6
* Completely eliminate def&use operands. Now a register operand is EITHER aChris Lattner2006-09-051-16/+28
* Constify some methods. Patch provided by Anton Vayvod, thanks!Chris Lattner2006-08-171-1/+1
* Let the alpha breakage begin. First Formals and RET. next CallsAndrew Lenharth2006-06-121-1/+1
* getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.Evan Cheng2006-05-181-0/+27
* Fix call_adj.llAndrew Lenharth2006-05-171-1/+1
* Move some methods out of MachineInstr into MachineOperandChris Lattner2006-05-041-5/+4
* There shalt be only one "immediate" operand type!Chris Lattner2006-05-041-2/+2
* Remove a bunch more SparcV9 specific stuffChris Lattner2006-05-041-1/+2
* Foundation for call frame information.Jim Laskey2006-04-071-1/+6
* Expose base register for DwarfWriter. Refactor code accordingly.Jim Laskey2006-03-281-10/+2
* Translate llvm target registers to dwarf register numbers properly.Jim Laskey2006-03-271-1/+1
* Add support to locate local variables in frames (early version.)Jim Laskey2006-03-231-0/+13
* remove some now-dead codeChris Lattner2006-03-091-16/+0
* Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far ...Chris Lattner2006-02-021-19/+0
* Add immediate forms of cmov and remove some cruftAndrew Lenharth2006-02-011-1/+1
* allow R28 to be used for frame calculations without entirely removing it from...Andrew Lenharth2006-01-261-1/+1
* maintaining stackpointer alignment. Perhaps it doesn't matterAndrew Lenharth2006-01-251-0/+4
* clean this function up someAndrew Lenharth2006-01-011-37/+26
* whatever. Intermediate patch to see what breaks. Seems ok.Andrew Lenharth2005-11-091-13/+56
* ret 0; works, not much elseAndrew Lenharth2005-10-201-1/+1
* This seems useful from the original patch that added the function. If there ...Andrew Lenharth2005-10-091-0/+19
* Pass extra regclasses into spilling codeChris Lattner2005-09-301-2/+4
* This code has always been dead for alphaChris Lattner2005-08-191-20/+0
* Alpha JIT (beta)Andrew Lenharth2005-07-221-1/+9
* clean up prolouge and epilougeAndrew Lenharth2005-07-071-26/+25
* simplify call code, remove pseudo ops for div and rem, track more loads and s...Andrew Lenharth2005-07-011-0/+16
* remove a pseudo instruction, make ret always right, and fix vararg chainsAndrew Lenharth2005-06-231-1/+1
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