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R600
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R600Instructions.td
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Author
Age
Files
Lines
*
Update aosp/master LLVM for rebase to r235153
Pirama Arumuga Nainar
2015-05-18
1
-0
/
+5
*
Update aosp/master LLVM for rebase to r230699.
Stephen Hines
2015-03-23
1
-20
/
+16
*
Update aosp/master LLVM for rebase to r222494.
Stephen Hines
2014-12-02
1
-12
/
+27
*
Update LLVM for rebase to r212749.
Stephen Hines
2014-07-21
1
-35
/
+123
*
Update LLVM for 3.5 rebase (r209712).
Stephen Hines
2014-05-29
1
-0
/
+6
*
Update to LLVM 3.5a.
Stephen Hines
2014-04-24
1
-775
/
+13
*
Merging r195878:
Bill Wendling
2013-12-01
1
-4
/
+14
*
Merging r195514:
Bill Wendling
2013-11-25
1
-3
/
+3
*
R600/SI: Add support for private address space load/store
Tom Stellard
2013-11-13
1
-1
/
+0
*
R600: Use function inputs to represent data stored in gpr
Vincent Lejeune
2013-11-11
1
-1
/
+1
*
R600: Clear the VPM bit of export instructions.
Vincent Lejeune
2013-10-13
1
-4
/
+4
*
R600: Add a ldptr intrinsic to support MSAA.
Vincent Lejeune
2013-10-02
1
-0
/
+4
*
R600: add a pass that merges clauses.
Vincent Lejeune
2013-10-01
1
-0
/
+1
*
R600: Enable -verify-machineinstrs in some tests.
Vincent Lejeune
2013-10-01
1
-1
/
+1
*
R600: Fix handling of NAN in comparison instructions
Tom Stellard
2013-09-28
1
-43
/
+11
*
SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()
Tom Stellard
2013-09-28
1
-48
/
+0
*
R600: Add support for LDS atomic subtract
Aaron Watry
2013-09-06
1
-0
/
+4
*
R600: Add support for local memory atomic add
Tom Stellard
2013-09-05
1
-7
/
+35
*
R600: Use SchedModel enum for is{Trans,Vector}Only functions
Vincent Lejeune
2013-09-04
1
-20
/
+6
*
R600: Add support for i8 and i16 local memory loads
Tom Stellard
2013-08-26
1
-0
/
+12
*
R600: Add support for i8 and i16 local memory stores
Tom Stellard
2013-08-26
1
-3
/
+21
*
R600: Add support for i16 and i8 global stores
Tom Stellard
2013-08-16
1
-0
/
+13
*
R600: Add support for v4i32 stores on Cayman
Tom Stellard
2013-08-16
1
-0
/
+1
*
R600: Add IsExport bit to TableGen instruction definitions
Tom Stellard
2013-08-16
1
-0
/
+3
*
R600: Change the RAT instruction assembly names so they match the docs
Tom Stellard
2013-08-16
1
-30
/
+33
*
R600/SI: Handle MSAA texture targets
Tom Stellard
2013-08-14
1
-1
/
+15
*
R600: Add 64-bit float load/store support
Tom Stellard
2013-08-01
1
-5
/
+75
*
Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"
Tom Stellard
2013-07-31
1
-6
/
+20
*
R600: Use SchedModel enum for is{Trans,Vector}Only functions
Vincent Lejeune
2013-07-31
1
-20
/
+6
*
R600: Remove predicated_break inst
Vincent Lejeune
2013-07-31
1
-3
/
+0
*
R600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS loads when necessary
Tom Stellard
2013-07-23
1
-19
/
+0
*
R600: Add support for 24-bit MAD instructions
Tom Stellard
2013-07-23
1
-0
/
+6
*
R600: Add support for 24-bit MUL instructions
Tom Stellard
2013-07-23
1
-0
/
+7
*
R600: Improve support for < 32-bit loads
Tom Stellard
2013-07-23
1
-0
/
+8
*
R600: Use KCache for kernel arguments
Tom Stellard
2013-07-23
1
-1
/
+1
*
R600: Clean up extended load patterns
Tom Stellard
2013-07-23
1
-8
/
+8
*
R600: Don't emit empty then clause and use alu_pop_after
Vincent Lejeune
2013-07-19
1
-0
/
+1
*
R600: Do not predicated basic block with multiple alu clause
Vincent Lejeune
2013-07-09
1
-1
/
+1
*
R600: Use DAG lowering pass to handle fcos/fsin
Vincent Lejeune
2013-07-09
1
-22
/
+10
*
R600: Print Export Swizzle
Vincent Lejeune
2013-07-09
1
-2
/
+2
*
R600: Support schedule and packetization of trans-only inst
Vincent Lejeune
2013-06-29
1
-0
/
+2
*
R600: Add local memory support via LDS
Tom Stellard
2013-06-28
1
-0
/
+75
*
R600: Add support for GROUP_BARRIER instruction
Tom Stellard
2013-06-28
1
-0
/
+30
*
R600: Add ALUInst bit to tablegen definitions v2
Tom Stellard
2013-06-28
1
-0
/
+3
*
R600: Use new getNamedOperandIdx function generated by TableGen
Tom Stellard
2013-06-25
1
-4
/
+12
*
R600: Add support for i32 loads from the constant address space on Cayman
Tom Stellard
2013-06-25
1
-0
/
+9
*
R600: Fix spelling error in comment
Aaron Watry
2013-06-24
1
-1
/
+1
*
R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen.
Vincent Lejeune
2013-06-17
1
-14
/
+16
*
R600: Use correct encoding for Vertex Fetch instructions on Cayman
Tom Stellard
2013-06-14
1
-150
/
+268
*
R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on Cayman
Tom Stellard
2013-06-14
1
-37
/
+56
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