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path: root/lib/Target/R600/SIISelLowering.cpp
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* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-97/+210
* Update to LLVM 3.5a.Stephen Hines2014-04-241-61/+172
* Merging r195514:Bill Wendling2013-11-251-0/+15
* R600/SI: Implement add i64, but do not yet enable.Matt Arsenault2013-11-181-0/+28
* R600/SI: addc / adde i32 are legalMatt Arsenault2013-11-181-0/+2
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-10/+108
* R600/SI: Replace ffs(x) - 1 with countTrailingZeros(x)Tom Stellard2013-10-231-1/+1
* R600/SI: fix MIMG writemask adjustementTom Stellard2013-10-231-6/+21
* R600: Fix handling of vector kernel argumentsTom Stellard2013-10-231-17/+44
* R600/SI: Remove some leftover MI dump callVincent Lejeune2013-10-151-1/+0
* R600/SI: Support byval argumentsVincent Lejeune2013-10-131-1/+2
* Fix typoMatt Arsenault2013-10-101-2/+2
* R600/SI: Define a separate MIMG instruction for each possible output value typeTom Stellard2013-10-101-0/+2
* R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedbackTom Stellard2013-09-121-0/+39
* R600: Fix i64 to i32 trunc on SIMatt Arsenault2013-09-051-0/+1
* R600: Add support for vector local memory loadsTom Stellard2013-08-261-0/+17
* SelectionDAG: Use correct pointer size when lowering function arguments v2Tom Stellard2013-08-261-1/+1
* R600: Allocate memoperand in the MachienFunction so it doesn't leak.Benjamin Kramer2013-08-161-3/+4
* R600/SI: Improve legalization of vector operationsTom Stellard2013-08-141-3/+3
* R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsicsTom Stellard2013-08-141-2/+0
* R600/SI: Convert v16i8 resource descriptors to i128Tom Stellard2013-08-141-2/+53
* R600/SI: Assign a register class to the $vaddr operand for MIMG instructionsTom Stellard2013-08-141-2/+6
* R600/SI: FMA is faster than fmul and fadd for f64Niels Ole Salscheider2013-08-101-0/+18
* R600/SI: Implement fp32<->fp64 conversionsNiels Ole Salscheider2013-08-081-0/+3
* R600/SI: Use VSrc_* register classes as the default classes for typesTom Stellard2013-08-061-21/+7
* R600/SI: Add more special cases for opcodes to ensureSRegLimit()Tom Stellard2013-08-061-32/+56
* R600/SI: Custom lower i64 ZERO_EXTENDTom Stellard2013-08-011-0/+15
* R600: Improve support for < 32-bit loadsTom Stellard2013-07-231-2/+2
* R600/SI: Fix crash with VSELECTTom Stellard2013-07-181-1/+10
* R600/SI: Add support for 64-bit loadsTom Stellard2013-07-151-0/+2
* R600/SI: Add double precision fsub pattern for SITom Stellard2013-07-121-0/+15
* R600/SI: Add initial double precision support for SITom Stellard2013-07-121-0/+1
* R600/SI: Initial local memory supportMichel Danzer2013-07-101-0/+5
* R600: Consolidate expansion of v2i32/v4i32 ops for EG/SIAaron Watry2013-06-251-30/+0
* R600/SI: Expand xor v2i32/v4i32Aaron Watry2013-06-251-0/+3
* R600/SI: Expand urem of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
* R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EGAaron Watry2013-06-251-0/+3
* R600/SI: Expand ashr of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+2
* R600/SI: Expand srl of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+2
* R600/SI: Expand shl of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
* R600/SI: Expand or of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
* R600/SI: Expand mul of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
* R600/SI: Expand and of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
* R600/SI: Report unaligned memory accesses as legal for > 32-bit typesTom Stellard2013-06-251-0/+12
* R600/SI: Expand sub for v2i32 and v4i32 for SITom Stellard2013-06-201-0/+3
* R600/SI: Expand add for v2i32 and v4i32Tom Stellard2013-06-201-0/+2
* R600: Rework subtarget info and remove AMDILDevice classesTom Stellard2013-06-071-1/+0
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-3/+10
* R600: Replace predicate loop with predicate functionTom Stellard2013-06-051-11/+13
* R600/SI: Add support for work item and work group intrinsicsTom Stellard2013-06-031-13/+81
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