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Target
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X86
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X86InstrExtension.td
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Author
Age
Files
Lines
*
Update aosp/master LLVM for rebase to r230699.
Stephen Hines
2015-03-23
1
-8
/
+8
*
Update aosp/master LLVM for rebase to r222494.
Stephen Hines
2014-12-02
1
-2
/
+12
*
Update to LLVM 3.5a.
Stephen Hines
2014-04-24
1
-16
/
+16
*
Adds support for Atom Silvermont (SLM) - -march=slm
Preston Gurd
2013-09-13
1
-6
/
+6
*
X86: change zext moves to use sub-register infrastructure.
Tim Northover
2013-05-30
1
-35
/
+21
*
Annotate the remaining x86 instructions with SchedRW lists.
Jakob Stoklund Olesen
2013-03-26
1
-4
/
+4
*
Annotate X86InstrExtension.td with SchedRW lists.
Jakob Stoklund Olesen
2013-03-19
1
-26
/
+39
*
Mark MOVZX16/MOVSX16 as neverHasSideEffects/mayLoad
Craig Topper
2012-07-30
1
-0
/
+6
*
Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnl...
Craig Topper
2012-07-30
1
-0
/
+2
*
Intel Atom instruction itineraries for mov sign extension and mov zero extens...
Andrew Trick
2012-02-29
1
-32
/
+46
*
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...
Jia Liu
2012-02-18
1
-3
/
+3
*
Constrain both operands on MOVZX32_NOREXrr8.
Jakob Stoklund Olesen
2011-10-07
1
-2
/
+2
*
Re-commit 131641 with fixes; de-pseudoize MOVSX16rr8 and friends.
Stuart Hastings
2011-05-20
1
-30
/
+9
*
Reverting 131641 to investigate 'bot complaint.
Stuart Hastings
2011-05-19
1
-8
/
+11
*
Revise MOVSX16rr8/MOVZX16rr8 (and rm variants) to no longer be
Stuart Hastings
2011-05-19
1
-11
/
+8
*
make the asm matcher emitter reject instructions that have comments
Chris Lattner
2010-11-01
1
-2
/
+2
*
two changes: make the asmmatcher generator ignore ARM pseudos properly,
Chris Lattner
2010-10-31
1
-1
/
+11
*
add new file
Chris Lattner
2010-10-05
1
-0
/
+162