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* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-72/+93
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-26/+67
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update to LLVM 3.5a.Stephen Hines2014-04-241-220/+268
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. ↵Craig Topper2013-10-091-0/+4
| | | | | | This way the asm parser will pick the right one based on the mode. Instruction selection already did the right thing based on the pointer size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192266 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added TB prefix to all instructions without prefixes,Elena Demikhovsky2013-10-021-3/+3
| | | | | | | otherwise encoding fails after the last change in X86MCCodeEmitter.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191812 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding intrinsics to the llvm backend for TBM instruction set.Yunzhong Gao2013-09-271-0/+1
| | | | | | | | Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191539 91177308-0d34-0410-b5e6-96231b3b80d8
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-131-1/+1
| | | | | | | | | | | | | | Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190717 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added VMOVD, VMOVQ, VMOVSS, VMOVSD instructions.Elena Demikhovsky2013-08-181-11/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188637 91177308-0d34-0410-b5e6-96231b3b80d8
* Added encoding prefixes for KNL instructions (EVEX).Elena Demikhovsky2013-07-281-3/+112
| | | | | | | Added 512-bit operands printing. Added instruction formats for KNL instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187324 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the move to/from accumulator register instructions that use a full 64-bitKevin Enderby2013-07-221-0/+7
| | | | | | | | | absolute address encoded in the instruction. rdar://8612627 and rdar://14299221 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186878 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed PackedDouble domain from scalar instructions. Added more formats for ↵Elena Demikhovsky2013-06-091-4/+21
| | | | | | the scalar stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183626 91177308-0d34-0410-b5e6-96231b3b80d8
* removed commented linesElena Demikhovsky2013-05-211-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182377 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed SSEPacked domain from all forms (AVX, SSE, signed, unsigned) scalar ↵Elena Demikhovsky2013-05-211-1/+6
| | | | | | | | | compare instructions, like COMISS, COMISD. No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182371 91177308-0d34-0410-b5e6-96231b3b80d8
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-111-17/+19
| | | | | | | | | As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the X86 FMAs to the scheduling model.Nadav Rotem2013-03-281-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178303 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove IIC_DEFAULT from X86Schedule.tdJakob Stoklund Olesen2013-03-251-70/+70
| | | | | | | | All the instructions tagged with IIC_DEFAULT had nothing in common, and we already have a NoItineraries class to represent untagged instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177937 91177308-0d34-0410-b5e6-96231b3b80d8
* x86 -- add the XTEST instructionDave Zarzycki2013-03-251-8/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Make sure we account for the FMA4 register immediate value, otherwise ↵Benjamin Kramer2013-01-221-1/+1
| | | | | | | | rip-rel relocations will be off by one byte. PR15040. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173176 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix execution domain for packed FMA4 instructions.Craig Topper2012-11-211-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168417 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support of RTM from TSX extensionMichael Liao2012-11-081-8/+9
| | | | | | | | | | - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce 'UseSSEx' to force SSE legacy encodingMichael Liao2012-08-301-22/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is enabled. As the penalty of inter-mixing SSE and AVX instructions, we need prevent SSE legacy insn from being generated except explicitly specified through some intrinsics. For patterns supported by both SSE and AVX, so far, we force AVX insn will be tried first relying on AddedComplexity or position in td file. It's error-prone and introduces bugs accidentally. 'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited by AVX, we need this predicate to force VEX encoding or SSE legacy encoding only. For insns not inherited by AVX, we still use the previous predicates, i.e. 'HasSSEx'. So far, these insns fall into the following categories: * SSE insns with MMX operands * SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH, CRC, and etc.) * SSE4A insns. * MMX insns. * x87 insns added by SSE. 2 test cases are modified: - test/CodeGen/X86/fast-isel-x86-64.ll AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be selected by fast-isel due to complicated pattern and fast-isel fallback to materialize it from constant pool. - test/CodeGen/X86/widen_load-1.ll AVX code generation is different from SSE one after fixing SSE/AVX inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of 'vmovaps'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162919 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix patterns for CVTTPS2DQ to specify SSE2 instead of SSE1.Craig Topper2012-07-301-4/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160941 91177308-0d34-0410-b5e6-96231b3b80d8
* Make CVTDQ2PS instruction use SSE2 predicate instead of SSE1. No functional ↵Craig Topper2012-06-231-1/+1
| | | | | | change because there are no patterns in the instructions. Also fix a typo in a comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159087 91177308-0d34-0410-b5e6-96231b3b80d8
* Move CVTPD2DQ to use SSE2 predicate instead of SSE3. Move DQ2PD and PD2DQ to ↵Craig Topper2012-06-231-0/+1
| | | | | | the SSE2 section of the file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159086 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark several instructions SSE2 instead of SSE3 as they should be.Craig Topper2012-06-061-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158049 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang.Craig Topper2012-06-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157903 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Rename the CLMUL target feature to PCLMUL.Benjamin Kramer2012-05-311-5/+5
| | | | | | | It was renamed in gcc/gas a while ago and causes all kinds of confusion because it was named differently in llvm and clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157745 91177308-0d34-0410-b5e6-96231b3b80d8
* Added X86 Atom latencies to X86InstrMMX.td.Preston Gurd2012-05-111-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156615 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch continues the work of adding instruction latencies for X86 Atom,Preston Gurd2012-05-021-2/+3
| | | | | | | | by providing the latencies for the instructions in X86InstrFPStack.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155996 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove HasSSE2 from AES and CLMUL predicates. It's now implied by the HasAES ↵Craig Topper2012-05-011-3/+3
| | | | | | and HasCLMUL predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155890 91177308-0d34-0410-b5e6-96231b3b80d8
* Add vmfunc instruction to X86 assembler and disassembler.Craig Topper2012-02-191-8/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150899 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-3/+3
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 assembler and disassembler support for AMD SVM instructions. ↵Craig Topper2012-02-181-0/+8
| | | | | | Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-011-128/+144
| | | | | | | | | | | | | | Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction selection priority fixes to remove the XMM/XMMInt/orAVX ↵Craig Topper2012-01-101-24/+1
| | | | | | predicates. Another commit will remove orAVX functions from X86SubTarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147841 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't disable MMX support when AVX is enabled. Fix predicates for MMX ↵Craig Topper2012-01-091-3/+26
| | | | | | instructions that were added along with SSE instructions to check for AVX in addition to SSE level. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147762 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow CRC32 instructions to be selected when AVX is enabled.Craig Topper2012-01-011-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147411 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX ↵Craig Topper2012-01-011-4/+0
| | | | | | is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147409 91177308-0d34-0410-b5e6-96231b3b80d8
* Separate the concept of having memory access in operand 4 from the concept ↵Craig Topper2011-12-301-3/+3
| | | | | | of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147366 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 ↵Craig Topper2011-12-291-1/+1
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147353 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled ↵Craig Topper2011-12-291-1/+1
| | | | | | along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147345 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along ↵Craig Topper2011-12-291-2/+2
| | | | | | with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147344 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure we correctly note the existence of an i8 immediate for vblendvps ↵Eli Friedman2011-12-151-1/+1
| | | | | | and friends, so we compute fixups correctly. PR11586. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146709 91177308-0d34-0410-b5e6-96231b3b80d8
* XOP instructions and encoding tests.Jan Sjödin2011-12-121-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146407 91177308-0d34-0410-b5e6-96231b3b80d8
* XOP encoding bits and logic.Jan Sjödin2011-12-121-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146397 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove hasSSE1orAVX(). It's the same as hasXMM().Evan Cheng2011-12-091-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146246 91177308-0d34-0410-b5e6-96231b3b80d8
* Many of the SSE patterns should not be selected when AVX is available. This ↵Evan Cheng2011-12-081-0/+4
| | | | | | | | | | | | | | | | | | | led to the following code in X86Subtarget.cpp if (HasAVX) X86SSELevel = NoMMXSSE; This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected. However, this breaks instructions which do not have AVX variants. The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX(). Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change. However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case, the prefetch instructions. rdar://10538297 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146163 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch contains support for encoding FMA4 instructions andBruno Cardoso Lopes2011-11-251-1/+9
| | | | | | | | | tablegen patterns for scalar FMA4 operations and intrinsic. Also add tests for vfmaddsd. Patch by Jan Sjodin git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145133 91177308-0d34-0410-b5e6-96231b3b80d8
* More AVX2 instructions and their intrinsics.Craig Topper2011-11-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143895 91177308-0d34-0410-b5e6-96231b3b80d8
* Add more AVX2 instructions and intrinsics.Craig Topper2011-11-061-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143861 91177308-0d34-0410-b5e6-96231b3b80d8
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