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path: root/lib/Target/X86/X86Schedule.td
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* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-071-9/+7
* X86 itinerary properties.Andrew Trick2012-06-051-1/+23
* whitespaceAndrew Trick2012-06-051-4/+1
* Added X86 Atom latencies to X86InstrMMX.td.Preston Gurd2012-05-111-0/+36
* Added X86 Atom latencies for instructions in X86InstrInfo.td.Preston Gurd2012-05-101-0/+64
* Adds Intel Atom scheduling latencies to X86InstrSystem.td.Preston Gurd2012-05-041-0/+53
* This patch continues the work of adding instruction latencies for X86 Atom,Preston Gurd2012-05-021-0/+38
* This patch adds X86 instruction itineraries for non-pseudo opcodes inPreston Gurd2012-03-191-0/+11
* Intel Atom instruction itineraries for mov sign extension and mov zero extens...Andrew Trick2012-02-291-0/+11
* This patch adds instruction latencies for the SSE instructionsPreston Gurd2012-02-271-0/+136
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu2012-02-181-1/+1
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-011-0/+115