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* Fix comments.Matthijs Kooijman2008-11-241-2/+2
* Move target independent td files from lib/Target/ to include/llvm/Target so t...Evan Cheng2008-11-2414-1582/+10
* Added missing description for -disable-mmx option.Mon P Wang2008-11-241-1/+1
* Rename SetCCResultContents to BooleanContents. InDuncan Sands2008-11-236-6/+6
* Added -disable-mmx using a patch from Preston Gurd.Mon P Wang2008-11-231-1/+5
* CellSPU: Fix bug 3056. Varadic extract_element was not implemented (nor was itScott Michel2008-11-225-102/+294
* Make a convenient helper for printing offsets.Anton Korobeynikov2008-11-225-33/+11
* CellSPU:Scott Michel2008-11-214-51/+123
* CellSPU:Scott Michel2008-11-202-6/+5
* Allow XMM2 and XMM3 to be used for non ABI compliant code.Mon P Wang2008-11-201-3/+4
* CellSPU: Custom lower truncating stores of i8 to i1 (should not have beenScott Michel2008-11-202-3/+4
* CellSPU: Adjust spacing/tabulationScott Michel2008-11-201-8/+8
* Fix a thinko. MO is getOperand(i-1) so we don't have to adjust e.Evan Cheng2008-11-201-3/+1
* Eliminate a compile time warning.Evan Cheng2008-11-191-4/+6
* Eliminate a compile time warning.Evan Cheng2008-11-191-4/+6
* Experimental post-pass scheduling support. Post-pass schedulingDan Gohman2008-11-192-2/+2
* CMake: Removed source file from lib/Target/PIC16/CMakeLists.txt.Oscar Fuentes2008-11-191-1/+0
* CellSPU: Do not custom lower i1 stores, rely on type legalization to do theScott Michel2008-11-191-34/+11
* <rdar://problem/6351057>Stuart Hastings2008-11-191-10/+12
* Temporary check-in for Duncan to demonstrate CellSPU store problem.Scott Michel2008-11-191-8/+41
* Forgot to add this in the previous commit.Sanjiv Gupta2008-11-191-0/+62
* Fixed build warnings.Sanjiv Gupta2008-11-192-4/+6
* Added a more function PIC16 backend. However to get this working a patch inSanjiv Gupta2008-11-1923-2307/+1579
* Don't set neverHasSideEffects on x86's divide instructions, sinceDan Gohman2008-11-182-3/+1
* Add more const qualifiers. This fixes build breakage from r59540.Dan Gohman2008-11-1818-40/+63
* Move some former testcases (low-probability codegenDale Johannesen2008-11-171-0/+45
* Adds extern "C" ints to the .cpp files that use RegisterTarget, asOscar Fuentes2008-11-1513-0/+91
* Fix fuitos encoding.Evan Cheng2008-11-151-8/+4
* Fix MOVrx, MOVsrl_flag, and MOVsra_flag encodings.Evan Cheng2008-11-142-4/+52
* Remove unneeded stuff from GRAD register class.Dale Johannesen2008-11-141-19/+1
* [XCore] Remove whitespace in the description used whenRichard Osborne2008-11-141-1/+1
* [XCore] Fix expansion of 64 bit add/sub. Don't custom expandRichard Osborne2008-11-142-23/+13
* Add XCore intrinsics for getid (returns thread id) and bitrev (reversesRichard Osborne2008-11-142-5/+4
* Handle the rest of pseudo instructions.Evan Cheng2008-11-133-54/+71
* Lazy compilation callback save / restore VFP registers.Evan Cheng2008-11-131-0/+9
* Extend InlineAsm::C_Register to allow multiple specific registersDale Johannesen2008-11-132-5/+27
* Don't forget to emit stubs for function GV's emitted in CONSTPOOL_ENTRY's.Evan Cheng2008-11-131-3/+10
* fsub{d|s} encoding bugs.Evan Cheng2008-11-131-2/+6
* Missed a break statement.Evan Cheng2008-11-131-0/+1
* Fix pre- and post-indexed load / store encoding bugs.Evan Cheng2008-11-134-70/+98
* Move the code that inserts X87 FP_REG_KILL instructions from aDan Gohman2008-11-125-80/+148
* Remove the incorrect assertion. We don't have enough information before reloc...Evan Cheng2008-11-121-2/+1
* Address mode immediate offset has already been divided by 4.Evan Cheng2008-11-121-2/+1
* Fix a VFP binary arithmetic instruction encoding bug.Evan Cheng2008-11-121-1/+1
* Fix address mode 3 immediate offset mode encoding.Evan Cheng2008-11-122-5/+7
* Consolidate formats; fix FCMPED etc. encodings.Evan Cheng2008-11-125-168/+120
* Fix VFP conversion instruction encodings.Evan Cheng2008-11-124-86/+123
* Fix encoding of single-precision VFP registers.Evan Cheng2008-11-124-40/+174
* VFP fld / fst immediate field is multiplied by 4.Evan Cheng2008-11-123-19/+37
* This shouldn't be necessaryAndrew Lenharth2008-11-111-1/+2
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