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* [Mips] MipsTargetStreamer refactoring.Jack Carter2013-11-184-64/+92
* Revert "COFF: Emit all MCSymbols rather than filtering out some of them"Reid Kleckner2013-11-181-0/+1
* R600/SI: Fix moveToVALU when the first operand is VSrc.Matt Arsenault2013-11-182-2/+4
* R600/SI: Fix multiple SGPR reads when using VCC.Matt Arsenault2013-11-181-0/+18
* R600/SI: Implement add i64, but do not yet enable.Matt Arsenault2013-11-182-0/+29
* R600/SI: Specify SSrc operandsMatt Arsenault2013-11-181-2/+2
* R600/SI: addc / adde i32 are legalMatt Arsenault2013-11-181-0/+2
* R600/SI: Match addc to S_ADD_U32.Matt Arsenault2013-11-181-0/+7
* R600/SI: Match adde/sube to S_ADDC_U32/S_SUBB_U32Matt Arsenault2013-11-181-2/+4
* R600/SI: Specify S_ADD/S_SUB set SCC and add is commutableMatt Arsenault2013-11-181-1/+13
* R600/SI: Move patterns to match add / sub to scalar instructionsMatt Arsenault2013-11-182-10/+16
* R600/SI: Fix extra defs of VCC / SCC.Matt Arsenault2013-11-181-4/+15
* R600: Enable the IR structurizer by defaultTom Stellard2013-11-183-6/+5
* R600: Fix a crash in the AMDILCFGStrucurizerTom Stellard2013-11-181-6/+7
* R600: Add a SubtargetFeatture for disabling the ifcvt pass.Tom Stellard2013-11-184-1/+14
* R600: Use lower-case for EnableIRStructurizer featureTom Stellard2013-11-181-1/+1
* R600/SI: Fix illegal VGPR->SGPR copy inside of loopTom Stellard2013-11-181-2/+1
* R600/SI: Fix another case of illegal VGPR->SGPR copyTom Stellard2013-11-181-3/+2
* [mips] Fix 'ran out of registers' in MIPS32 with FP64 when generating code fo...Daniel Sanders2013-11-182-2/+12
* [mips][msa] Update encoding of bnz.v (typo).Matheus Almeida2013-11-181-1/+1
* [mips][msa] Fix immediate value of LSA instruction as it was being wrongly en...Matheus Almeida2013-11-185-6/+108
* Revert r194865 and r194874.Alexey Samsonov2013-11-1858-199/+44
* [AArch64 NEON]Add mov alias for simd copy instructions.Kevin Qin2013-11-181-35/+63
* Implement the newly added ACLE functions for ld1/st1 with 2/3/4 vectors.Hao Liu2013-11-184-45/+237
* Added a size field to the stack map record to handle subregister spills.Andrew Trick2013-11-173-12/+41
* The WebKit_JS CC preserves the same registers as the C CC.Juergen Ributzka2013-11-161-0/+1
* R600: Make dot_4 instructions predicableVincent Lejeune2013-11-161-0/+19
* X86: Encode the 'h' cpu subtype in the MachO header for x86.Jim Grosbach2013-11-161-6/+14
* Implemented aarch64 Neon scalar vmulx_lane intrinsicsAna Pazos2013-11-151-2/+169
* Remove unused arguments.Lang Hames2013-11-151-4/+2
* During folding for patchpoint/stackmap instructions, defer creation of new MIsLang Hames2013-11-151-4/+5
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-1558-44/+199
* Make method staticMatt Arsenault2013-11-152-2/+2
* [AArch64] Fix the scalar NEON ACLE functions so that they return float/doubleChad Rosier2013-11-151-4/+4
* Avoid illegal integer promotion in fastiselBob Wilson2013-11-153-21/+6
* R600/SI: Add VReg_96 register class to SIRegisterInfo::hasVGPRs()Tom Stellard2013-11-151-0/+1
* Add AVX512 unmasked FMA intrinsics and support.Cameron McInally2013-11-151-1/+25
* [mips][msa] lowerMSABitClear() should use SelectionDAG::getNOT() instead of u...Daniel Sanders2013-11-151-14/+2
* Hopefully fix uninitialized memory read in AArch64AsmParser found by MSan boo...Alexey Samsonov2013-11-151-5/+5
* Fix illegal DAG produced by SelectionDAG::getConstant() for v2i64 typeDaniel Sanders2013-11-151-59/+91
* [NVPTX] Fix handling of indirect callsJustin Holewinski2013-11-156-12/+46
* Use instr mapping for microMIPS in llvm-mc.Zoran Jovanovic2013-11-152-5/+9
* Add target hook to prevent folding some bitcasted loads.Matt Arsenault2013-11-152-0/+13
* [llvm-c] Make LLVMGetTargetFromName actually workPeter Zotov2013-11-151-1/+2
* [llvm-c] Add missing const qualifiers to LLVMCreateTargetMachinePeter Zotov2013-11-151-3/+4
* [llvm-c] Simplify signature of LLVMGetTargetFromNamePeter Zotov2013-11-151-7/+4
* Make all the conditional Mips 16 branches get initially set for theReed Kotler2013-11-153-28/+46
* Add addrspacecast instruction.Matt Arsenault2013-11-153-2/+11
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-159-51/+116
* R600/SI: Add processor type for HawaiiTom Stellard2013-11-141-0/+1
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