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* Merging r195716:Bill Wendling2013-11-263-328/+226
* Merging r195679:Bill Wendling2013-11-261-1/+5
* Merging r195591:Bill Wendling2013-11-251-9/+14
* Merging r195330:Bill Wendling2013-11-251-2/+23
* Merging r195327:Bill Wendling2013-11-251-39/+155
* Merging r195514:Bill Wendling2013-11-254-76/+98
* Merging r195491:Bill Wendling2013-11-251-0/+5
* Merging r195476:Bill Wendling2013-11-251-0/+9
* Merging r195432:Bill Wendling2013-11-254-44/+44
* Merging r195439:Bill Wendling2013-11-221-8/+14
* Merging r195473:Richard Sandiford2013-11-224-20/+34
* Merging r195423:Bill Wendling2013-11-224-44/+44
* Merging r195421:Bill Wendling2013-11-224-44/+44
* Merging r195399:Bill Wendling2013-11-222-0/+14
* Merging r195339:Bill Wendling2013-11-211-5/+0
* Merging r195317:Bill Wendling2013-11-211-0/+5
* Merging r195272:Bill Wendling2013-11-211-6/+6
* Merging r195318:Bill Wendling2013-11-211-14/+8
* Merging r195152:Bill Wendling2013-11-205-9/+70
* Merging r195129:Bill Wendling2013-11-201-2/+2
* Merging r195094:Bill Wendling2013-11-191-8/+6
* Merging r195093:Bill Wendling2013-11-191-63/+17
* Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.Hao Liu2013-11-199-191/+1840
* Remove unused special member functions and reformat.Eric Christopher2013-11-192-14/+3
* Fix previous commit and fully remove variable.Eric Christopher2013-11-193-5/+3
* Remove unused variable.Eric Christopher2013-11-191-1/+0
* Implement AArch64 SISD intrinsics for vget_high and vget_low.Jiangning Liu2013-11-191-4/+33
* implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit ...Kevin Qin2013-11-192-0/+12
* Add predicate for AArch64 crypto instructions.Jiangning Liu2013-11-191-1/+8
* [Mips] Support for MicroMips STO refactoring.Jack Carter2013-11-194-58/+9
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-1957-49/+193
* [Mips] MipsTargetStreamer refactoring.Jack Carter2013-11-184-64/+92
* Revert "COFF: Emit all MCSymbols rather than filtering out some of them"Reid Kleckner2013-11-181-0/+1
* R600/SI: Fix moveToVALU when the first operand is VSrc.Matt Arsenault2013-11-182-2/+4
* R600/SI: Fix multiple SGPR reads when using VCC.Matt Arsenault2013-11-181-0/+18
* R600/SI: Implement add i64, but do not yet enable.Matt Arsenault2013-11-182-0/+29
* R600/SI: Specify SSrc operandsMatt Arsenault2013-11-181-2/+2
* R600/SI: addc / adde i32 are legalMatt Arsenault2013-11-181-0/+2
* R600/SI: Match addc to S_ADD_U32.Matt Arsenault2013-11-181-0/+7
* R600/SI: Match adde/sube to S_ADDC_U32/S_SUBB_U32Matt Arsenault2013-11-181-2/+4
* R600/SI: Specify S_ADD/S_SUB set SCC and add is commutableMatt Arsenault2013-11-181-1/+13
* R600/SI: Move patterns to match add / sub to scalar instructionsMatt Arsenault2013-11-182-10/+16
* R600/SI: Fix extra defs of VCC / SCC.Matt Arsenault2013-11-181-4/+15
* R600: Enable the IR structurizer by defaultTom Stellard2013-11-183-6/+5
* R600: Fix a crash in the AMDILCFGStrucurizerTom Stellard2013-11-181-6/+7
* R600: Add a SubtargetFeatture for disabling the ifcvt pass.Tom Stellard2013-11-184-1/+14
* R600: Use lower-case for EnableIRStructurizer featureTom Stellard2013-11-181-1/+1
* R600/SI: Fix illegal VGPR->SGPR copy inside of loopTom Stellard2013-11-181-2/+1
* R600/SI: Fix another case of illegal VGPR->SGPR copyTom Stellard2013-11-181-3/+2
* [mips] Fix 'ran out of registers' in MIPS32 with FP64 when generating code fo...Daniel Sanders2013-11-182-2/+12