| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Fix handling of functions with internal linkage. | Akira Hatanaka | 2011-04-07 | 1 | -8/+27 |
| * | Add sanity checking for invalid register encodings for signed/unsigned extend... | Johnny Chen | 2011-04-07 | 1 | -0/+5 |
| * | Add sanity checking for invalid register encodings for saturating instructions. | Johnny Chen | 2011-04-07 | 1 | -0/+5 |
| * | Add some more comments about checkings of invalid register numbers. | Johnny Chen | 2011-04-07 | 1 | -0/+5 |
| * | Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector... | Tanya Lattner | 2011-04-07 | 1 | -0/+6 |
| * | Sanity check MSRi for invalid mask values and reject it as invalid. | Johnny Chen | 2011-04-07 | 1 | -0/+5 |
| * | The ARM disassembler was not recognizing USADA8 instruction. Need to add che... | Johnny Chen | 2011-04-07 | 1 | -3/+5 |
| * | Change -arm-divmod-libcall to a target neutral option. | Evan Cheng | 2011-04-07 | 2 | -6/+7 |
| * | Should also check SMLAD for invalid register values. | Johnny Chen | 2011-04-07 | 1 | -6/+12 |
| * | Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for ... | Owen Anderson | 2011-04-06 | 1 | -1/+8 |
| * | Cleanups from Jim: remove redundant constraints and a dead FIXME. | Owen Anderson | 2011-04-06 | 1 | -11/+5 |
| * | Tidy up. | Jim Grosbach | 2011-04-06 | 1 | -2/+1 |
| * | A8.6.393 | Johnny Chen | 2011-04-06 | 1 | -26/+47 |
| * | A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP" | Johnny Chen | 2011-04-06 | 1 | -1/+14 |
| * | Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong. | Johnny Chen | 2011-04-06 | 2 | -1/+3 |
| * | Add another case we are not optimizing. | Rafael Espindola | 2011-04-06 | 1 | -0/+30 |
| * | The original issue has been fixed by not doing unnecessary sign extensions. | Rafael Espindola | 2011-04-06 | 1 | -14/+17 |
| * | Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function. | Johnny Chen | 2011-04-06 | 1 | -7/+3 |
| * | Reapply r128946 (pseudoization of various instructions), and fix the extra im... | Owen Anderson | 2011-04-05 | 2 | -65/+42 |
| * | Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal... | Johnny Chen | 2011-04-05 | 1 | -1/+7 |
| * | Clean up some code for clarity. | Bob Wilson | 2011-04-05 | 1 | -5/+24 |
| * | Revert r128946 while I figure out why it broke the buildbots. | Owen Anderson | 2011-04-05 | 2 | -38/+64 |
| * | A7.3 register encoding | Johnny Chen | 2011-04-05 | 1 | -0/+10 |
| * | Give RSBS and RSCS the pseudo treatment. | Owen Anderson | 2011-04-05 | 2 | -64/+38 |
| * | ARM disassembler was erroneously accepting an invalid RSC instruction. | Johnny Chen | 2011-04-05 | 1 | -0/+6 |
| * | ARM disassembler was erroneously accepting an invalid LSL instruction. | Johnny Chen | 2011-04-05 | 1 | -0/+4 |
| * | Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doi... | Owen Anderson | 2011-04-05 | 3 | -80/+76 |
| * | The r128085 checkin modified the operand ordering for MRC/MRC2 instructions. | Johnny Chen | 2011-04-05 | 1 | -7/+19 |
| * | ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error. | Johnny Chen | 2011-04-05 | 1 | -2/+10 |
| * | Make second source operand of LDRD pre/post explicit. | Jim Grosbach | 2011-04-05 | 2 | -8/+28 |
| * | Constants with multiple encodings (ARM): | Johnny Chen | 2011-04-05 | 1 | -2/+3 |
| * | Check for invalid register encodings for UMAAL and friends where: | Johnny Chen | 2011-04-05 | 1 | -2/+49 |
| * | Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/... | Owen Anderson | 2011-04-05 | 2 | -41/+56 |
| * | Revamp the SjLj "dispatch setup" intrinsic. | Bill Wendling | 2011-04-05 | 2 | -4/+4 |
| * | Just use BL all the time. It's safer that way. | Eric Christopher | 2011-04-05 | 1 | -9/+1 |
| * | Fix SRS/SRSW encoding bits. | Johnny Chen | 2011-04-05 | 1 | -0/+4 |
| * | A8.6.105 MUL | Johnny Chen | 2011-04-04 | 1 | -1/+3 |
| * | RFE encoding should also specify the "should be" encoding bits. | Johnny Chen | 2011-04-04 | 3 | -28/+49 |
| * | Make OpcodeMask an unsigned long long literal to deal with overflow. | Joerg Sonnenberger | 2011-04-04 | 1 | -1/+1 |
| * | Fix incorrect alignment for NEON VST2b32_UPD. | Johnny Chen | 2011-04-04 | 1 | -7/+132 |
| * | Insert code in the right location when lowering PowerPC atomics. | Jakob Stoklund Olesen | 2011-04-04 | 1 | -2/+4 |
| * | - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT | Bruno Cardoso Lopes | 2011-04-04 | 7 | -32/+240 |
| * | Move transformation of JmpLink and related nodes done during instruction sele... | Akira Hatanaka | 2011-04-04 | 2 | -59/+27 |
| * | PowerPC atomic pseudos clobber CR0, they don't read it. | Jakob Stoklund Olesen | 2011-04-04 | 2 | -2/+2 |
| * | Use X0 instead of R0 for the zero register on ppc64. | Jakob Stoklund Olesen | 2011-04-04 | 1 | -10/+13 |
| * | Add support for the VIA PadLock instructions. | Joerg Sonnenberger | 2011-04-04 | 7 | -4/+81 |
| * | Expand Op0Mask by one bit in preparation for the PadLock prefixes. | Joerg Sonnenberger | 2011-04-04 | 3 | -50/+51 |
| * | Remove some support for ReturnInsts with multiple operands, and for | Jay Foad | 2011-04-04 | 1 | -18/+0 |
| * | ptx: support setp's 4-operand format | Che-Liang Chiou | 2011-04-02 | 2 | -35/+86 |
| * | Do some peephole optimizations to remove pointless VMOVs from Neon to integer | Cameron Zwarich | 2011-04-02 | 1 | -0/+31 |
