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* Add FMA4 instructions to disassembler.Craig Topper2011-12-301-38/+53
* Separate the concept of having memory access in operand 4 from the concept of...Craig Topper2011-12-305-34/+26
* Combine FMA4 SS/SD patterns with the instruction definitions.Craig Topper2011-12-301-97/+24
* Combine FMA4 PS/PD patterns with the instruction definitions.Craig Topper2011-12-301-219/+42
* Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to ...Craig Topper2011-12-301-58/+48
* Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 size,...Craig Topper2011-12-301-60/+43
* Cleanup stack/frame register define/kill states. This fixes two bugs:Hal Finkel2011-12-302-17/+17
* Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 ins...Craig Topper2011-12-292-19/+55
* Expose FMA3 instructions to the disassembler.Craig Topper2011-12-291-17/+15
* Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types a...Craig Topper2011-12-291-3/+4
* Change XOP detection to use the correct CPUID bit instead of using the FMA4 bit.Craig Topper2011-12-291-9/+13
* Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A ...Craig Topper2011-12-291-14/+17
* Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled alo...Craig Topper2011-12-291-1/+1
* Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along ...Craig Topper2011-12-291-2/+2
* Remove the separate explicit AES instruction patterns. They are equivalent to...Craig Topper2011-12-291-48/+5
* Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled o...Craig Topper2011-12-291-3/+2
* Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL f...Craig Topper2011-12-291-9/+8
* Remove some elses after returns.Craig Topper2011-12-291-7/+10
* Remove trailing spaces. Fix an assert to use && instead of || before string. ...Craig Topper2011-12-291-7/+5
* Fix type-checking for load transformation which is not legal on floating-poin...Eli Friedman2011-12-281-1/+2
* Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR.Elena Demikhovsky2011-12-281-4/+25
* Clean up some Release build warnings.Benjamin Kramer2011-12-274-24/+16
* Add handling of x86_avx2_pmovmskb to computeMaskedBitsForTargetNode for consi...Craig Topper2011-12-271-1/+6
* Sparc: Implement emitFrameIndexDebugValue and getDebugValue Location hooks.Venkatraman Govindaraju2011-12-253-1/+28
* Section relative fixups are a coff concept, not a x86 one. Replace theRafael Espindola2011-12-243-6/+6
* Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when theChandler Carruth2011-12-241-18/+14
* Add systematic testing for cttz as well, and fix the bug I spotted byChandler Carruth2011-12-241-1/+2
* Chandler fixed this.Benjamin Kramer2011-12-241-32/+0
* Expand more when we have a nice 'tzcnt' instruction, to avoid generatingChandler Carruth2011-12-241-0/+4
* Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to theChandler Carruth2011-12-243-11/+39
* Fix Comments.Jakob Stoklund Olesen2011-12-241-3/+3
* Add MachineMemOperands to instructions generated in storeRegToStackSlot orAkira Hatanaka2011-12-241-2/+16
* Detect unaligned loads/stores that have been added for Mips64 support.Akira Hatanaka2011-12-241-1/+8
* If target ABI is N64, LEA should be daddiu.Akira Hatanaka2011-12-241-1/+1
* Move x86 specific bits of the COFF writer to lib/Target/X86.Rafael Espindola2011-12-244-1/+74
* Experimental support for aligned NEON spills.Jakob Stoklund Olesen2011-12-233-13/+377
* Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>Bob Wilson2011-12-224-7/+23
* Fix 80-column violations.Chad Rosier2011-12-221-11/+14
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-224-16/+70
* Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp.Bob Wilson2011-12-221-1/+1
* Tidy up. Use predicate function a bit more liberally.Jim Grosbach2011-12-221-97/+52
* Fix incorrect relocation generation. Patch by Kristof Beyls.Rafael Espindola2011-12-221-8/+1
* ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns.Jim Grosbach2011-12-221-0/+3
* Remove some bogus comments.Jim Grosbach2011-12-221-36/+18
* ARM pre-UAL aliases. fcmp[sd].Jim Grosbach2011-12-222-1/+3
* Fix an incomplete refactoring of the ppc backend. Thanks to rdivacky for repo...Rafael Espindola2011-12-222-15/+3
* ARM assembler should accept shift-by-zero for any shifted-immediate operand.Jim Grosbach2011-12-221-0/+33
* ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.Jim Grosbach2011-12-221-0/+4
* Tidy up. Trailing whitespace.Jim Grosbach2011-12-221-2/+2
* Nuke invalid comment from copy/paste.Jim Grosbach2011-12-221-1/+0
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