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* Add FMA4 instructions to disassembler.Craig Topper2011-12-301-38/+53
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147367 91177308-0d34-0410-b5e6-96231b3b80d8
* Separate the concept of having memory access in operand 4 from the concept ↵Craig Topper2011-12-305-34/+26
| | | | | | of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147366 91177308-0d34-0410-b5e6-96231b3b80d8
* Combine FMA4 SS/SD patterns with the instruction definitions.Craig Topper2011-12-301-97/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147365 91177308-0d34-0410-b5e6-96231b3b80d8
* Combine FMA4 PS/PD patterns with the instruction definitions.Craig Topper2011-12-301-219/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147364 91177308-0d34-0410-b5e6-96231b3b80d8
* Change FMA4 memory forms to use memopv* instead of alignedloadv*. No need to ↵Craig Topper2011-12-301-58/+48
| | | | | | force alignment on these instructions. Add a couple testcases for memory forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147361 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix load size for FMA4 SS/SD instructions. They need to use f32 and f64 ↵Craig Topper2011-12-301-60/+43
| | | | | | size, but with the special handling to be compatible with the intrinsic expecting a vector. Similar handling is already used elsewhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147360 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup stack/frame register define/kill states. This fixes two bugs:Hal Finkel2011-12-302-17/+17
| | | | | | | | 1. The ST*UX instructions that store and update the stack pointer did not set define/kill on R1. This became a problem when I activated post-RA scheduling (and had incorrectly adjusted the Frames-large test). 2. eliminateFrameIndex did not kill its scavenged temporary register, and this could cause the scavenger to exhaust all available registers (and its emergency spill slot) when there were a lot of CR values to spill. The 2010-02-12-saveCR test has been adjusted to check for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147359 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 ↵Craig Topper2011-12-292-19/+55
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147353 91177308-0d34-0410-b5e6-96231b3b80d8
* Expose FMA3 instructions to the disassembler.Craig Topper2011-12-291-17/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147351 91177308-0d34-0410-b5e6-96231b3b80d8
* Make FMA3 imply AVX needs to be enabled. Particularly because 256-bit types ↵Craig Topper2011-12-291-3/+4
| | | | | | aren't valid unless AVX is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147349 91177308-0d34-0410-b5e6-96231b3b80d8
* Change XOP detection to use the correct CPUID bit instead of using the FMA4 bit.Craig Topper2011-12-291-9/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147348 91177308-0d34-0410-b5e6-96231b3b80d8
* Add FeaturePOPCNT to all CPU types that lost it was removed from SSE42/SSE4A ↵Craig Topper2011-12-291-14/+17
| | | | | | in r147339. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147347 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled ↵Craig Topper2011-12-291-1/+1
| | | | | | along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147345 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along ↵Craig Topper2011-12-291-2/+2
| | | | | | with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147344 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the separate explicit AES instruction patterns. They are equivalent ↵Craig Topper2011-12-291-48/+5
| | | | | | to the patterns specified by the instructions. Also remove unnecessary bitconverts from the AES patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147342 91177308-0d34-0410-b5e6-96231b3b80d8
* Make SSE42 and SSE4A not imply POPCNT. POPCNT should be able to be disabled ↵Craig Topper2011-12-291-3/+2
| | | | | | on its own without disabling SSE4.2 or SSE4A. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147339 91177308-0d34-0410-b5e6-96231b3b80d8
* Make LowerBUILD_VECTOR keep node vector types consistent when creating MOVL ↵Craig Topper2011-12-291-9/+8
| | | | | | for v16i16 and v32i8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147337 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some elses after returns.Craig Topper2011-12-291-7/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147336 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove trailing spaces. Fix an assert to use && instead of || before string. ↵Craig Topper2011-12-291-7/+5
| | | | | | Add same assert on similar code path. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147335 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix type-checking for load transformation which is not legal on ↵Eli Friedman2011-12-281-1/+2
| | | | | | floating-point types. PR11674. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147323 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR.Elena Demikhovsky2011-12-281-4/+25
| | | | | | | | | Matching MOVLP mask for AVX (265-bit vectors) was wrong. The failure was detected by conformance tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147308 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up some Release build warnings.Benjamin Kramer2011-12-274-24/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147289 91177308-0d34-0410-b5e6-96231b3b80d8
* Add handling of x86_avx2_pmovmskb to computeMaskedBitsForTargetNode for ↵Craig Topper2011-12-271-1/+6
| | | | | | consistency. Add comments and an assert for BMI instructions to PerformXorCombine since the enabling of the combine is conditional on it, but the function itself isn't. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147287 91177308-0d34-0410-b5e6-96231b3b80d8
* Sparc: Implement emitFrameIndexDebugValue and getDebugValue Location hooks.Venkatraman Govindaraju2011-12-253-1/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147269 91177308-0d34-0410-b5e6-96231b3b80d8
* Section relative fixups are a coff concept, not a x86 one. Replace theRafael Espindola2011-12-243-6/+6
| | | | | | x86 specific reloc_coff_secrel32 with a generic FK_SecRel_4. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147252 91177308-0d34-0410-b5e6-96231b3b80d8
* Use standard promotion for i8 CTTZ nodes and i8 CTLZ nodes when theChandler Carruth2011-12-241-18/+14
| | | | | | | | | | | | | | | | | | LZCNT instructions are available. Force promotion to i32 to get a smaller encoding since the fix-ups necessary are just as complex for either promoted type We can't do standard promotion for CTLZ when lowering through BSR because it results in poor code surrounding the 'xor' at the end of this instruction. Essentially, if we promote the entire CTLZ node to i32, we end up doing the xor on a 32-bit CTLZ implementation, and then subtracting appropriately to get back to an i8 value. Instead, our custom logic just uses the knowledge of the incoming size to compute a perfect xor. I'd love to know of a way to fix this, but so far I'm drawing a blank. I suspect the legalizer could be more clever and/or it could collude with the DAG combiner, but how... ;] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147251 91177308-0d34-0410-b5e6-96231b3b80d8
* Add systematic testing for cttz as well, and fix the bug I spotted byChandler Carruth2011-12-241-1/+2
| | | | | | inspection earlier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147250 91177308-0d34-0410-b5e6-96231b3b80d8
* Chandler fixed this.Benjamin Kramer2011-12-241-32/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147247 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand more when we have a nice 'tzcnt' instruction, to avoid generatingChandler Carruth2011-12-241-0/+4
| | | | | | | | | | | 'bsf' instructions here. This one is actually debatable to my eyes. It's not clear that any chip implementing 'tzcnt' would have a slow 'bsf' for any reason, and unless EFLAGS or a zero input matters, 'tzcnt' is just a longer encoding. Still, this restores the old behavior with 'tzcnt' enabled for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147246 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch the lowering of CTLZ_ZERO_UNDEF from a .td pattern back to theChandler Carruth2011-12-243-11/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | X86ISelLowering C++ code. Because this is lowered via an xor wrapped around a bsr, we want the dagcombine which runs after isel lowering to have a chance to clean things up. In particular, it is very common to see code which looks like: (sizeof(x)*8 - 1) ^ __builtin_clz(x) Which is trying to compute the most significant bit of 'x'. That's actually the value computed directly by the 'bsr' instruction, but if we match it too late, we'll get completely redundant xor instructions. The more naive code for the above (subtracting rather than using an xor) still isn't handled correctly due to the dagcombine getting confused. Also, while here fix an issue spotted by inspection: we should have been expanding the zero-undef variants to the normal variants when there is an 'lzcnt' instruction. Do so, and test for this. We don't want to generate unnecessary 'bsr' instructions. These two changes fix some regressions in encoding and decoding benchmarks. However, there is still a *lot* to be improve on in this type of code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147244 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Comments.Jakob Stoklund Olesen2011-12-241-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147238 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MachineMemOperands to instructions generated in storeRegToStackSlot orAkira Hatanaka2011-12-241-2/+16
| | | | | | | | loadRegFromStackSlot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147235 91177308-0d34-0410-b5e6-96231b3b80d8
* Detect unaligned loads/stores that have been added for Mips64 support.Akira Hatanaka2011-12-241-1/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147234 91177308-0d34-0410-b5e6-96231b3b80d8
* If target ABI is N64, LEA should be daddiu.Akira Hatanaka2011-12-241-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147232 91177308-0d34-0410-b5e6-96231b3b80d8
* Move x86 specific bits of the COFF writer to lib/Target/X86.Rafael Espindola2011-12-244-1/+74
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147231 91177308-0d34-0410-b5e6-96231b3b80d8
* Experimental support for aligned NEON spills.Jakob Stoklund Olesen2011-12-233-13/+377
| | | | | | | | | | | | | ARM targets with NEON units have access to aligned vector loads and stores that are potentially faster than unaligned operations. Add support for spilling the callee-saved NEON registers to an aligned stack area using 16-byte aligned NEON loads and store. This feature is off by default, controlled by an -align-neon-spills command line option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147211 91177308-0d34-0410-b5e6-96231b3b80d8
* Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>Bob Wilson2011-12-224-7/+23
| | | | | | | | | | | My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo instruction, but on Thumb1 some of those registers cannot be used. This caused massive failures on the testsuite when compiling for Thumb1. While fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp" variant, and I realized that dispatchsetup needs the same thing, so I have added that as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147204 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix 80-column violations.Chad Rosier2011-12-221-11/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147192 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-224-16/+70
| | | | | | rdar://10558523 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp.Bob Wilson2011-12-221-1/+1
| | | | | | Noticed by inspection; I don't have a testcase for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147188 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Use predicate function a bit more liberally.Jim Grosbach2011-12-221-97/+52
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147184 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix incorrect relocation generation. Patch by Kristof Beyls.Rafael Espindola2011-12-221-8/+1
| | | | | | Fixes PR11214. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147180 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns.Jim Grosbach2011-12-221-0/+3
| | | | | | | | | | The value from the operands isn't right yet, but we weren't encoding it at all previously. The parser needs to twiddle the values when building the instruction. Partial for: rdar://10558523 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147170 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some bogus comments.Jim Grosbach2011-12-221-36/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147169 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM pre-UAL aliases. fcmp[sd].Jim Grosbach2011-12-222-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147158 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an incomplete refactoring of the ppc backend. Thanks to rdivacky for ↵Rafael Espindola2011-12-222-15/+3
| | | | | | | | reporting it. It does need some some tests... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147154 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembler should accept shift-by-zero for any shifted-immediate operand.Jim Grosbach2011-12-221-0/+33
| | | | | | | | Just treat it as-if the shift wasn't there at all. 'as' compatibility. rdar://10604767 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147153 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.Jim Grosbach2011-12-221-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147152 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Trailing whitespace.Jim Grosbach2011-12-221-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147151 91177308-0d34-0410-b5e6-96231b3b80d8
* Nuke invalid comment from copy/paste.Jim Grosbach2011-12-221-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147150 91177308-0d34-0410-b5e6-96231b3b80d8
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