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* Revert r129401 for now. Clang is using the old way of doing things.Bill Wendling2011-04-122-0/+31
* Remove the unaligned load intrinsics in favor of using native unaligned loads.Bill Wendling2011-04-122-31/+0
* The Thumb2 RFE instructions need to have their second halfword fully specified.Johnny Chen2011-04-122-6/+11
* Add bad register checks for Thumb2 Ld/St instructions.Johnny Chen2011-04-121-0/+45
* The Thumb2 Ld, St, and Preload instructions with the i12 forms should have it...Johnny Chen2011-04-122-0/+5
* Print out a debug message when the reglist fails the sanity check for Thumb L...Johnny Chen2011-04-122-0/+29
* Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARMCameron Zwarich2011-04-121-2/+22
* A8.6.16 BJohnny Chen2011-04-121-0/+5
* Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen2011-04-112-2/+14
* Fix an error in the MBlaze delay slot filler.Wesley Peck2011-04-111-1/+1
* Add scheduling information for the MBlaze backend.Wesley Peck2011-04-1116-228/+710
* Don't crash on invalid instructions when disassembling MBlaze code.Wesley Peck2011-04-113-36/+115
* Fix the bug where the immediate shift amount for Thumb logical shift instruct...Johnny Chen2011-04-111-6/+17
* Fix another using-CPSR-twice bug in my ADCS/SBCS cleanups, and make proper us...Owen Anderson2011-04-111-2/+5
* Trivial comment fix.Johnny Chen2011-04-112-2/+2
* Check invalid register encodings for LdFrm/StFrm ARM instructions and flag th...Johnny Chen2011-04-111-0/+68
* Adding support for printing operands symbolically to llvm's public 'C'Kevin Enderby2011-04-114-6/+139
* Don't include Operator.h from InstrTypes.h.Jay Foad2011-04-112-0/+2
* Bugfix in the Cpp backend after API change on PHINode::Create.Nicolas Geoffray2011-04-101-1/+1
* fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately,Chris Lattner2011-04-092-0/+19
* Fix an apparent typo that made GCC complainMatt Beaumont-Gay2011-04-081-1/+1
* Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is...Evan Cheng2011-04-082-23/+12
* Check opcoe (dmb, dsb) instead of bitfields matching.Johnny Chen2011-04-081-12/+1
* Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.Johnny Chen2011-04-081-9/+10
* Sanity check the option operand for DMB/DSB.Johnny Chen2011-04-082-8/+29
* Mark hasExtraDefRegAllocReq=1 on LDRD.Jim Grosbach2011-04-081-1/+5
* Add sanity checking for bad register specifier(s) for the DPFrm instructions.Johnny Chen2011-04-081-0/+30
* Replace the old algorithm that emitted the "print the alias for an instruction"Bill Wendling2011-04-074-5/+22
* Add option to emit @llvm.trap as a function call instead of a trap instructio...Evan Cheng2011-04-071-1/+23
* Fix indentation.Akira Hatanaka2011-04-071-2/+2
* Update ATUsed every time after expandRegLargeImmPair is called.Akira Hatanaka2011-04-071-4/+8
* Fixed encoding for VEXTqfMon P Wang2011-04-071-2/+2
* Fix handling of functions with internal linkage.Akira Hatanaka2011-04-071-8/+27
* Add sanity checking for invalid register encodings for signed/unsigned extend...Johnny Chen2011-04-071-0/+5
* Add sanity checking for invalid register encodings for saturating instructions.Johnny Chen2011-04-071-0/+5
* Add some more comments about checkings of invalid register numbers.Johnny Chen2011-04-071-0/+5
* Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector...Tanya Lattner2011-04-071-0/+6
* Sanity check MSRi for invalid mask values and reject it as invalid.Johnny Chen2011-04-071-0/+5
* The ARM disassembler was not recognizing USADA8 instruction. Need to add che...Johnny Chen2011-04-071-3/+5
* Change -arm-divmod-libcall to a target neutral option.Evan Cheng2011-04-072-6/+7
* Should also check SMLAD for invalid register values.Johnny Chen2011-04-071-6/+12
* Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for ...Owen Anderson2011-04-061-1/+8
* Cleanups from Jim: remove redundant constraints and a dead FIXME.Owen Anderson2011-04-061-11/+5
* Tidy up.Jim Grosbach2011-04-061-2/+1
* A8.6.393Johnny Chen2011-04-061-26/+47
* A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"Johnny Chen2011-04-061-1/+14
* Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.Johnny Chen2011-04-062-1/+3
* Add another case we are not optimizing.Rafael Espindola2011-04-061-0/+30
* The original issue has been fixed by not doing unnecessary sign extensions.Rafael Espindola2011-04-061-14/+17
* Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.Johnny Chen2011-04-061-7/+3
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