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| * Remove unused special member functions and reformat.Eric Christopher2013-11-192-14/+3
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195077 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix previous commit and fully remove variable.Eric Christopher2013-11-193-5/+3
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195076 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove unused variable.Eric Christopher2013-11-191-1/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195075 91177308-0d34-0410-b5e6-96231b3b80d8
| * Implement AArch64 SISD intrinsics for vget_high and vget_low.Jiangning Liu2013-11-191-4/+33
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195074 91177308-0d34-0410-b5e6-96231b3b80d8
| * implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit ↵Kevin Qin2013-11-192-0/+12
| | | | | | | | | | | | integer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195072 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add predicate for AArch64 crypto instructions.Jiangning Liu2013-11-191-1/+8
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195071 91177308-0d34-0410-b5e6-96231b3b80d8
| * [Mips] Support for MicroMips STO refactoring.Jack Carter2013-11-194-58/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No true functional changes. Change the "hack" name of emitMipsHackSTOCG to emitSymSTO. Remove demonstration code in AsmParser for emitMipsHackSTOCG and emitMipsHackELFFlags. The STO field is in an ELF symbol and is not an explicit directive. That said, we are missing the compliment call in AsmParser and that will need to be addressed soon. XFAIL dummy tests for emitMipsHackELFFlags and emitMipsHackELFFlags. These will built out with following patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195067 91177308-0d34-0410-b5e6-96231b3b80d8
| * [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-1957-49/+193
| | | | | | | | | | | | | | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
| * [Mips] MipsTargetStreamer refactoring.Jack Carter2013-11-184-64/+92
| | | | | | | | | | | | | | No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195057 91177308-0d34-0410-b5e6-96231b3b80d8
| * Revert "COFF: Emit all MCSymbols rather than filtering out some of them"Reid Kleckner2013-11-181-0/+1
| | | | | | | | | | | | | | | | This reverts commit r190888, to fix PR17967. The original change wasn't the right way to get @feat.00 into the object file. The right fix is to make @feat.00 be a global symbol. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195053 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: Fix moveToVALU when the first operand is VSrc.Matt Arsenault2013-11-182-2/+4
| | | | | | | | | | | | | | Moving into a VSrc doesn't always work, since it could be replaced with an SGPR later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195042 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: Fix multiple SGPR reads when using VCC.Matt Arsenault2013-11-181-0/+18
| | | | | | | | | | | | | | No other SGPR operands are allowed, so if VCC is used, move the other to a VGPR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195041 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: Implement add i64, but do not yet enable.Matt Arsenault2013-11-182-0/+29
| | | | | | | | | | | | | | | | Test doesn't actually check the output. I need to fix add i64 being matched for the addressing calculations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195040 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: Specify SSrc operandsMatt Arsenault2013-11-181-2/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195039 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: addc / adde i32 are legalMatt Arsenault2013-11-181-0/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195038 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: Match addc to S_ADD_U32.Matt Arsenault2013-11-181-0/+7
| | | | | | | | | | | | The carry always goes to SCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195037 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: Match adde/sube to S_ADDC_U32/S_SUBB_U32Matt Arsenault2013-11-181-2/+4
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195036 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: Specify S_ADD/S_SUB set SCC and add is commutableMatt Arsenault2013-11-181-1/+13
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195035 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: Move patterns to match add / sub to scalar instructionsMatt Arsenault2013-11-182-10/+16
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195034 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: Fix extra defs of VCC / SCC.Matt Arsenault2013-11-181-4/+15
| | | | | | | | | | | | | | When replacing scalar operations with vector, the wrong implicit output register was used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195033 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600: Enable the IR structurizer by defaultTom Stellard2013-11-183-6/+5
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195031 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600: Fix a crash in the AMDILCFGStrucurizerTom Stellard2013-11-181-6/+7
| | | | | | | | | | | | | | The ifPatternMatch() function was not correctly reporting the number of matches in some cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195030 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600: Add a SubtargetFeatture for disabling the ifcvt pass.Tom Stellard2013-11-184-1/+14
| | | | | | | | | | | | This is useful when writing test cases for the AMDIL structurizer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195029 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600: Use lower-case for EnableIRStructurizer featureTom Stellard2013-11-181-1/+1
| | | | | | | | | | | | | | llc converts all values passed to -mattr= to lowercase, so this enables us to toggle this feature when using llc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195028 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: Fix illegal VGPR->SGPR copy inside of loopTom Stellard2013-11-181-2/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195026 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: Fix another case of illegal VGPR->SGPR copyTom Stellard2013-11-181-3/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195025 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips] Fix 'ran out of registers' in MIPS32 with FP64 when generating code ↵Daniel Sanders2013-11-182-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | for (ConstantFP 0.0) Fixed an inappropriate use of BuildPairF64 when compiling for MIPS32 with FP64 which resulted in an impossible constraint on the register allocation. It now uses BuildPairF64_64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195007 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips][msa] Update encoding of bnz.v (typo).Matheus Almeida2013-11-181-1/+1
| | | | | | | | | | | | | | | | Note that there's no hardware yet that relies on that encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195006 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips][msa] Fix immediate value of LSA instruction as it was being wrongly ↵Matheus Almeida2013-11-185-6/+108
| | | | | | | | | | | | | | | | | | | | | | encoded. The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195004 91177308-0d34-0410-b5e6-96231b3b80d8
| * Revert r194865 and r194874.Alexey Samsonov2013-11-1858-199/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
| * [AArch64 NEON]Add mov alias for simd copy instructions.Kevin Qin2013-11-181-35/+63
| | | | | | | | | | | | Set some unspecified bits of INS/DUP to zero as ARMARM requested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194996 91177308-0d34-0410-b5e6-96231b3b80d8
| * Implement the newly added ACLE functions for ld1/st1 with 2/3/4 vectors.Hao Liu2013-11-184-45/+237
| | | | | | | | | | | | | | The functions are like: vst1_s8_x2 ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194990 91177308-0d34-0410-b5e6-96231b3b80d8
| * Added a size field to the stack map record to handle subregister spills.Andrew Trick2013-11-173-12/+41
| | | | | | | | | | | | | | | | Implementing this on bigendian platforms could get strange. I added a target hook, getStackSlotRange, per Jakob's recommendation to make this as explicit as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194942 91177308-0d34-0410-b5e6-96231b3b80d8
| * The WebKit_JS CC preserves the same registers as the C CC.Juergen Ributzka2013-11-161-0/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194936 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600: Make dot_4 instructions predicableVincent Lejeune2013-11-161-0/+19
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194927 91177308-0d34-0410-b5e6-96231b3b80d8
| * X86: Encode the 'h' cpu subtype in the MachO header for x86.Jim Grosbach2013-11-161-6/+14
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194906 91177308-0d34-0410-b5e6-96231b3b80d8
| * Implemented aarch64 Neon scalar vmulx_lane intrinsicsAna Pazos2013-11-151-2/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implemented aarch64 Neon scalar vfma_lane intrinsics Implemented aarch64 Neon scalar vfms_lane intrinsics Implemented legacy vmul_n_f64, vmul_lane_f64, vmul_laneq_f64 intrinsics (v1f64 parameter type) using Neon scalar instructions. Implemented legacy vfma_lane_f64, vfms_lane_f64, vfma_laneq_f64, vfms_laneq_f64 intrinsics (v1f64 parameter type) using Neon scalar instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194888 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove unused arguments.Lang Hames2013-11-151-4/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194882 91177308-0d34-0410-b5e6-96231b3b80d8
| * During folding for patchpoint/stackmap instructions, defer creation of new MIsLang Hames2013-11-151-4/+5
| | | | | | | | | | | | | | | | | | | | until we know that folding will be successful. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194880 91177308-0d34-0410-b5e6-96231b3b80d8
| * [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-1558-44/+199
| | | | | | | | | | | | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
| * Make method staticMatt Arsenault2013-11-152-2/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194858 91177308-0d34-0410-b5e6-96231b3b80d8
| * [AArch64] Fix the scalar NEON ACLE functions so that they return float/doubleChad Rosier2013-11-151-4/+4
| | | | | | | | | | | | rather than the vector equivalent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194853 91177308-0d34-0410-b5e6-96231b3b80d8
| * Avoid illegal integer promotion in fastiselBob Wilson2013-11-153-21/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stop folding constant adds into GEP when the type size doesn't match. Otherwise, the adds' operands are effectively being promoted, changing the conditions of an overflow. Results are different when: sext(a) + sext(b) != sext(a + b) Problem originally found on x86-64, but also fixed issues with ARM and PPC, which used similar code. <rdar://problem/15292280> Patch by Duncan Exon Smith! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194840 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: Add VReg_96 register class to SIRegisterInfo::hasVGPRs()Tom Stellard2013-11-151-0/+1
| | | | | | | | | | | | This fixes a crash with GNOME settings manager. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194836 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add AVX512 unmasked FMA intrinsics and support.Cameron McInally2013-11-151-1/+25
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194824 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips][msa] lowerMSABitClear() should use SelectionDAG::getNOT() instead of ↵Daniel Sanders2013-11-151-14/+2
| | | | | | | | | | | | | | | | | | | | | | using a long-winded equivalent. Now that getConstant(-1, MVT::v2i64) works correctly on MIPS32 we can use SelectionDAG::getNOT() to produce the bitmask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194819 91177308-0d34-0410-b5e6-96231b3b80d8
| * Hopefully fix uninitialized memory read in AArch64AsmParser found by MSan ↵Alexey Samsonov2013-11-151-5/+5
| | | | | | | | | | | | bootstrap bot git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194818 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix illegal DAG produced by SelectionDAG::getConstant() for v2i64 typeDaniel Sanders2013-11-151-59/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When getConstant() is called for an expanded vector type, it is split into multiple scalar constants which are then combined using appropriate build_vector and bitcast operations. In addition to the usual big/little endian differences, the case where the element-order of the vector does not have the same endianness as the elements themselves is also accounted for. For example, for v4i32 on big-endian MIPS, the byte-order of the vector is <3210,7654,BA98,FEDC>. For little-endian, it is <0123,4567,89AB,CDEF>. Handling this case turns out to be a nop since getConstant() returns a splatted vector (so reversing the element order doesn't change the value) This fixes a number of cases in MIPS MSA where calling getConstant() during operation legalization introduces illegal types (e.g. to legalize v2i64 UNDEF into a v2i64 BUILD_VECTOR of illegal i64 zeros). It should also handle bigger differences between illegal and legal types such as legalizing v2i64 into v8i16. lowerMSASplatImm() in the MIPS backend no longer needs to avoid calling getConstant() so this function has been updated in the same patch. For the sake of transparency, the steps I've taken since the review are: * Added 'virtual' to isVectorEltOrderLittleEndian() as requested. This revealed that the MIPS tests were falsely passing because a polymorphic function was not actually polymorphic in the reviewed patch. * Fixed the tests that were now failing. This involved deleting the code to handle the MIPS MSA element-order (which was previously doing an byte-order swap instead of an element-order swap). This left isVectorEltOrderLittleEndian() unused and it was deleted. * Fixed build failures caused by rebasing beyond r194467-r194472. These build failures involved the bset, bneg, and bclr instructions added in these commits using lowerMSASplatImm() in a way that was no longer valid after this patch. Some of these were fixed by calling SelectionDAG::getConstant() instead, others were fixed by a new function getBuildVectorSplat() that provided the removed functionality of lowerMSASplatImm() in a more sensible way. Reviewers: bkramer Reviewed By: bkramer CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1973 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194811 91177308-0d34-0410-b5e6-96231b3b80d8
| * [NVPTX] Fix handling of indirect callsJustin Holewinski2013-11-156-12/+46
| | | | | | | | | | | | Using a special machine node is cleaner than an InlineAsm node, and fixes an assertion failure in InstrEmitter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194810 91177308-0d34-0410-b5e6-96231b3b80d8
| * Use instr mapping for microMIPS in llvm-mc.Zoran Jovanovic2013-11-152-5/+9
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194792 91177308-0d34-0410-b5e6-96231b3b80d8
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