| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction. | Jim Grosbach | 2011-10-24 | 3 | -4/+0 |
| * | ARM assembly parsing and encoding for VLD1 w/ writeback. | Jim Grosbach | 2011-10-24 | 4 | -21/+33 |
| * | More fixes and improvements to MachO relocation pretty-printing, particular f... | Owen Anderson | 2011-10-24 | 1 | -31/+127 |
| * | Don't crash on variable insertelement on ARM. PR10258. | Eli Friedman | 2011-10-24 | 1 | -0/+11 |
| * | Check the visibility of the global variable before placing it into the stubs | Bill Wendling | 2011-10-24 | 1 | -2/+6 |
| * | ARMConstantPoolMBB::print should print BB number. | Evan Cheng | 2011-10-24 | 1 | -0/+1 |
| * | ARM assembly parsing and encoding for VLD1 w/ writeback. | Jim Grosbach | 2011-10-24 | 2 | -0/+38 |
| * | ARM refactor am6offset usage for VLD1. | Jim Grosbach | 2011-10-24 | 5 | -71/+181 |
| * | Get relocation parsing/dumping to a mostly-working state for MachO files. | Owen Anderson | 2011-10-24 | 1 | -6/+127 |
| * | Now that we look at all the header PHIs, we need to consider all the header PHIs | Nick Lewycky | 2011-10-24 | 1 | -6/+14 |
| * | Add support to the old JIT for acquire/release loads and stores on x86. PR11... | Eli Friedman | 2011-10-24 | 1 | -9/+24 |
| * | Stub out some of the MachO relocation decoding hooks. | Owen Anderson | 2011-10-24 | 1 | -0/+4 |
| * | Really unbreak CMake build | Douglas Gregor | 2011-10-24 | 1 | -3/+1 |
| * | Unbreak CMake build | Douglas Gregor | 2011-10-24 | 1 | -0/+1 |
| * | Fix a NEON disassembly case that was broken in the recent refactorings. As m... | Owen Anderson | 2011-10-24 | 1 | -6/+0 |
| * | Delete the top-down "Latency" scheduler. Top-down scheduling doesn't handle | Dan Gohman | 2011-10-24 | 1 | -265/+0 |
| * | Delete the Latency scheduling preference. | Dan Gohman | 2011-10-24 | 1 | -2/+0 |
| * | Change this overloaded use of Sched::Latency to be an overloaded | Dan Gohman | 2011-10-24 | 2 | -6/+6 |
| * | Remove the explicit request for "Latency" scheduling from MSP430, | Dan Gohman | 2011-10-24 | 1 | -1/+0 |
| * | Change the default scheduler from Latency to ILP, since Latency | Dan Gohman | 2011-10-24 | 1 | -1/+1 |
| * | Thumb2 LDM instructions can target PC. Make sure to encode it. | Jim Grosbach | 2011-10-24 | 1 | -8/+4 |
| * | Cleanup. Get rid of the old SjLj EH lowering code. No functionality change. | Bill Wendling | 2011-10-24 | 1 | -584/+10 |
| * | Sink an otherwise unused variable's initializer into the asserts that | Chandler Carruth | 2011-10-24 | 1 | -3/+2 |
| * | Remove return heuristics from the static branch probabilities, and | Chandler Carruth | 2011-10-24 | 1 | -73/+76 |
| * | Reapply r142781 with fix. Original message: | Nick Lewycky | 2011-10-24 | 1 | -20/+32 |
| * | PHI nodes not in the loop header aren't part of the loop iteration initial | Nick Lewycky | 2011-10-24 | 1 | -1/+1 |
| * | A dead malloc, a free(NULL) and a free(undef) are all trivially dead | Nick Lewycky | 2011-10-24 | 1 | -0/+8 |
| * | Speculatively revert r142781. Bots are showing | Nick Lewycky | 2011-10-24 | 1 | -32/+20 |
| * | Windows/Path.inc: [PR8460] Get rid of ScopedNullTerminator. Thanks to Zvi Rac... | NAKAMURA Takumi | 2011-10-24 | 1 | -18/+9 |
| * | Simplify the design of BranchProbabilityInfo by collapsing it into | Chandler Carruth | 2011-10-24 | 1 | -135/+90 |
| * | Enhance SCEV's brute force loop analysis to handle multiple PHI nodes in the | Nick Lewycky | 2011-10-23 | 1 | -20/+32 |
| * | Tidy up a loop to be more idiomatic for LLVM's codebase, and remove some | Chandler Carruth | 2011-10-23 | 1 | -18/+9 |
| * | Add X86 SARX, SHRX, and SHLX instructions. | Craig Topper | 2011-10-23 | 1 | -18/+32 |
| * | Teach the BranchProbabilityInfo pass to print its results, and use that | Chandler Carruth | 2011-10-23 | 1 | -2/+20 |
| * | Now that we have comparison on probabilities, add some static functions | Chandler Carruth | 2011-10-23 | 1 | -8/+5 |
| * | Remove a commented out line of code that snuck by my auditing. | Chandler Carruth | 2011-10-23 | 1 | -1/+0 |
| * | Print branch probabilities as percentages. | Benjamin Kramer | 2011-10-23 | 1 | -3/+3 |
| * | Add compare operators to BranchProbability and use it to determine if an edge... | Benjamin Kramer | 2011-10-23 | 2 | -15/+4 |
| * | Completely re-write the algorithm behind MachineBlockPlacement based on | Chandler Carruth | 2011-10-23 | 1 | -399/+227 |
| * | Add X86 RORX instruction | Craig Topper | 2011-10-23 | 5 | -0/+36 |
| * | The element insertion code in scalar replacement doesn't handle incorrect | Cameron Zwarich | 2011-10-23 | 1 | -2/+4 |
| * | Add X86 MULX instruction for disassembler. | Craig Topper | 2011-10-23 | 1 | -0/+24 |
| * | Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 ... | Craig Topper | 2011-10-22 | 1 | -5/+5 |
| * | A non-escaping malloc in the entry block is not unlike an alloca. Do dead-store | Nick Lewycky | 2011-10-22 | 1 | -2/+25 |
| * | Make SCEV's brute force analysis stronger in two ways. Firstly, we should be | Nick Lewycky | 2011-10-22 | 1 | -26/+145 |
| * | Move various generated tables into read-only memory, fixing up const correctn... | Benjamin Kramer | 2011-10-22 | 3 | -11/+12 |
| * | Fix pr11193. | Nadav Rotem | 2011-10-22 | 1 | -3/+0 |
| * | The different flavors of ARM have different valid subsets of registers. Check | Bill Wendling | 2011-10-22 | 1 | -3/+13 |
| * | Assembly parsing for 4-register sequential variant of VLD2. | Jim Grosbach | 2011-10-21 | 3 | -36/+18 |
| * | Assembly parsing for 2-register sequential variant of VLD2. | Jim Grosbach | 2011-10-21 | 4 | -30/+46 |
