| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Remove the local register allocator. | Jakob Stoklund Olesen | 2010-06-15 | 4 | -4/+0 |
| * | Set the mtriple in some tests so that they use AAPCS. | Rafael Espindola | 2010-06-15 | 4 | -4/+4 |
| * | Remove the arm_aapcscc marker from the tests. It is the default | Rafael Espindola | 2010-06-15 | 8 | -16/+16 |
| * | Generalize the pre-coalescing of extract_subregs feeding reg_sequences, | Bob Wilson | 2010-06-15 | 1 | -2/+2 |
| * | Add a missing bitcast. This code used to only handle conversions between | Bob Wilson | 2010-06-11 | 1 | -0/+19 |
| * | Re-apply 105308 with fix. | Evan Cheng | 2010-06-04 | 1 | -0/+18 |
| * | More tail call removal. | Dale Johannesen | 2010-06-04 | 1 | -1/+1 |
| * | Remove more tail calls. | Dale Johannesen | 2010-06-04 | 2 | -2/+2 |
| * | Remove a tail call, and move some CHECKs to the | Dale Johannesen | 2010-06-04 | 1 | -3/+3 |
| * | Revert 105308. | Bob Wilson | 2010-06-03 | 1 | -18/+0 |
| * | Enable machine cse of instructions which define physical registers. | Evan Cheng | 2010-06-02 | 1 | -0/+18 |
| * | Fix some latency computation bugs: if the use is not a machine opcode do not ... | Evan Cheng | 2010-05-28 | 2 | -13/+14 |
| * | Add a -regalloc=default option that chooses a register allocator based on the -O | Jakob Stoklund Olesen | 2010-05-27 | 1 | -1/+1 |
| * | llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error. | Evan Cheng | 2010-05-27 | 1 | -8/+0 |
| * | LR is in GPR, not tGPR even in Thumb1 mode. | Evan Cheng | 2010-05-24 | 1 | -0/+2 |
| * | Implement @llvm.returnaddress. rdar://8015977. | Evan Cheng | 2010-05-22 | 2 | -2/+29 |
| * | Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by | Bob Wilson | 2010-05-22 | 2 | -1/+45 |
| * | Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements | Bob Wilson | 2010-05-21 | 1 | -7/+7 |
| * | Teach VirtRegRewriter to handle spilling in instructions that have multiple | Jakob Stoklund Olesen | 2010-05-21 | 1 | -0/+45 |
| * | Change ARM scheduling default to list-hybrid if the target supports floating ... | Evan Cheng | 2010-05-21 | 8 | -14/+14 |
| * | When canonicalizing icmp operand order to put the loop invariant | Dan Gohman | 2010-05-20 | 1 | -0/+256 |
| * | Handle Neon v2f64 and v2i64 vector shuffles as register copies. | Bob Wilson | 2010-05-20 | 1 | -0/+7 |
| * | Teach LSR how to cope better with unrolled loops on targets where | Dan Gohman | 2010-05-19 | 1 | -0/+386 |
| * | TwoAddressInstructionPass doesn't really know how to merge live intervals when | Jakob Stoklund Olesen | 2010-05-19 | 1 | -0/+17 |
| * | Testcase to go with 104141. | Bob Wilson | 2010-05-19 | 1 | -0/+14 |
| * | Intrinsics which do a vector compare (results are all zero or all ones) are m... | Evan Cheng | 2010-05-19 | 1 | -0/+13 |
| * | Remember to update VirtRegLastUse when spilling without killing before a call. | Jakob Stoklund Olesen | 2010-05-18 | 1 | -0/+37 |
| * | Sink dag combine's post index load / store code that swap base ptr and index ... | Evan Cheng | 2010-05-18 | 1 | -0/+25 |
| * | Fix PR7162: Use source register classes and sub-indices to determine the corr... | Evan Cheng | 2010-05-18 | 1 | -0/+38 |
| * | FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (... | Evan Cheng | 2010-05-18 | 1 | -0/+17 |
| * | Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG... | Evan Cheng | 2010-05-17 | 1 | -0/+35 |
| * | Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace ... | Evan Cheng | 2010-05-17 | 1 | -0/+46 |
| * | Careful with reg_sequence coalescing to not to overwrite sub-register indices. | Evan Cheng | 2010-05-17 | 1 | -0/+42 |
| * | Turn on -neon-reg-sequence by default. | Evan Cheng | 2010-05-17 | 1 | -0/+170 |
| * | Avoid allocating the same physreg to multiple virtregs in one instruction. | Jakob Stoklund Olesen | 2010-05-17 | 1 | -0/+105 |
| * | Some cheap DAG combine goodness for multiplication with a particular constant. | Anton Korobeynikov | 2010-05-15 | 1 | -4/+30 |
| * | Allow TargetLowering::getRegClassFor() to be called on illegal types. Also | Evan Cheng | 2010-05-15 | 1 | -0/+10 |
| * | Keep track of the last place a live virtreg was used. | Jakob Stoklund Olesen | 2010-05-11 | 3 | -0/+3 |
| * | Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. | Evan Cheng | 2010-05-11 | 1 | -0/+12 |
| * | Correct some bogus target triples. | Duncan Sands | 2010-05-07 | 1 | -1/+1 |
| * | fix copy/paste oops. | Jim Grosbach | 2010-05-05 | 1 | -3/+3 |
| * | Add tests for ARMV7M divide instruction use | Jim Grosbach | 2010-05-05 | 1 | -9/+19 |
| * | remove unneeded underscores. | Jim Grosbach | 2010-05-05 | 1 | -4/+4 |
| * | Convert to filecheck | Jim Grosbach | 2010-05-05 | 1 | -5/+9 |
| * | Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul, | Dan Gohman | 2010-05-03 | 13 | -38/+38 |
| * | Fix a bug which prevented tail merging of return instructions in | Dan Gohman | 2010-05-03 | 2 | -7/+8 |
| * | Remove the -enable-sjlj-eh option, which doesn't do anything. | Duncan Sands | 2010-05-02 | 3 | -8/+0 |
| * | Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield | Jim Grosbach | 2010-04-22 | 1 | -0/+28 |
| * | Fix tests for Neon load/store intrinsics to match the i8* types expected by | Bob Wilson | 2010-04-20 | 10 | -94/+188 |
| * | Fix declarations in a few more tests. | Nick Lewycky | 2010-04-17 | 2 | -2/+2 |
