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* Remove the local register allocator.Jakob Stoklund Olesen2010-06-154-4/+0
| | | | | | Please use the fast allocator instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106051 91177308-0d34-0410-b5e6-96231b3b80d8
* Set the mtriple in some tests so that they use AAPCS.Rafael Espindola2010-06-154-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106041 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the arm_aapcscc marker from the tests. It is the defaultRafael Espindola2010-06-158-16/+16
| | | | | | for the linux targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106029 91177308-0d34-0410-b5e6-96231b3b80d8
* Generalize the pre-coalescing of extract_subregs feeding reg_sequences,Bob Wilson2010-06-151-2/+2
| | | | | | | | | | replacing the overly conservative checks that I had introduced recently to deal with correctness issues. This makes a pretty noticable difference in our testcases where reg_sequences are used. I've updated one test to check that we no longer emit the unnecessary subreg moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105991 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a missing bitcast. This code used to only handle conversions betweenBob Wilson2010-06-111-0/+19
| | | | | | | | i64 and f64 types, but now it also handle Neon vector types, so the f64 result of VMOVDRR may need to be converted to a Neon type. Radar 8084742. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105845 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply 105308 with fix.Evan Cheng2010-06-041-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105502 91177308-0d34-0410-b5e6-96231b3b80d8
* More tail call removal.Dale Johannesen2010-06-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105485 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove more tail calls.Dale Johannesen2010-06-042-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105450 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a tail call, and move some CHECKs to theDale Johannesen2010-06-041-3/+3
| | | | | | | | functions where they belong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105449 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 105308.Bob Wilson2010-06-031-18/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105399 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable machine cse of instructions which define physical registers.Evan Cheng2010-06-021-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105308 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some latency computation bugs: if the use is not a machine opcode do not ↵Evan Cheng2010-05-282-13/+14
| | | | | | just return zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105061 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a -regalloc=default option that chooses a register allocator based on the -OJakob Stoklund Olesen2010-05-271-1/+1
| | | | | | | | | optimization level. This only really affects llc for now because both the llvm-gcc and clang front ends override the default register allocator. I intend to remove that code later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104904 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.Evan Cheng2010-05-271-8/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104891 91177308-0d34-0410-b5e6-96231b3b80d8
* LR is in GPR, not tGPR even in Thumb1 mode.Evan Cheng2010-05-241-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement @llvm.returnaddress. rdar://8015977.Evan Cheng2010-05-222-2/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104421 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented byBob Wilson2010-05-222-1/+45
| | | | | | | | | copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll tests, so I tweaked those tests to keep that code from being optimized away. Radar 7872877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415 91177308-0d34-0410-b5e6-96231b3b80d8
* Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elementsBob Wilson2010-05-211-7/+7
| | | | | | | | | so that it will continue to test what it was meant to test when I commit a separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon. Fix a DAG combiner crash exposed by this test change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104380 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach VirtRegRewriter to handle spilling in instructions that have multipleJakob Stoklund Olesen2010-05-211-0/+45
| | | | | | | | | | | | | definitions of the virtual register. This happens when spilling the registers produced by REG_SEQUENCE: %reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0 The rewriter would spill the register multiple times, dead store elimination tried to keep up, but ended up cutting the branch it was sitting on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104321 91177308-0d34-0410-b5e6-96231b3b80d8
* Change ARM scheduling default to list-hybrid if the target supports floating ↵Evan Cheng2010-05-218-14/+14
| | | | | | point instructions (and is not using soft float). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
* When canonicalizing icmp operand order to put the loop invariantDan Gohman2010-05-201-0/+256
| | | | | | | | | | | | | operand on the left, the interesting operand is on the right. This fixes a bug where LSR was failing to recognize ICmpZero uses, which led it to be unable to reverse the induction variable in the attached testcase. Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test is extremely fragile and hard to meaningfully update. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104262 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle Neon v2f64 and v2i64 vector shuffles as register copies.Bob Wilson2010-05-201-0/+7
| | | | | | | This fixes the remaining issue with pr7167. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104257 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach LSR how to cope better with unrolled loops on targets whereDan Gohman2010-05-191-0/+386
| | | | | | | | | the addressing modes don't make this trivially easy. This allows it to avoid falling into the less precise heuristics in more cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104186 91177308-0d34-0410-b5e6-96231b3b80d8
* TwoAddressInstructionPass doesn't really know how to merge live intervals whenJakob Stoklund Olesen2010-05-191-0/+17
| | | | | | | | lowering REG_SEQUENCE instructions. Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104146 91177308-0d34-0410-b5e6-96231b3b80d8
* Testcase to go with 104141.Bob Wilson2010-05-191-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104142 91177308-0d34-0410-b5e6-96231b3b80d8
* Intrinsics which do a vector compare (results are all zero or all ones) are ↵Evan Cheng2010-05-191-0/+13
| | | | | | | | | | | modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction. The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that. Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104094 91177308-0d34-0410-b5e6-96231b3b80d8
* Remember to update VirtRegLastUse when spilling without killing before a call.Jakob Stoklund Olesen2010-05-181-0/+37
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104074 91177308-0d34-0410-b5e6-96231b3b80d8
* Sink dag combine's post index load / store code that swap base ptr and index ↵Evan Cheng2010-05-181-0/+25
| | | | | | into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR7162: Use source register classes and sub-indices to determine the ↵Evan Cheng2010-05-181-0/+38
| | | | | | correct register class of the definitions of REG_SEQUENCE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104050 91177308-0d34-0410-b5e6-96231b3b80d8
* FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op ↵Evan Cheng2010-05-181-0/+17
| | | | | | (build_vector), (build_vector)). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104004 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other ↵Evan Cheng2010-05-171-0/+35
| | | | | | REG_SEQUENCE instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103994 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace ↵Evan Cheng2010-05-171-0/+46
| | | | | | it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103984 91177308-0d34-0410-b5e6-96231b3b80d8
* Careful with reg_sequence coalescing to not to overwrite sub-register indices.Evan Cheng2010-05-171-0/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103971 91177308-0d34-0410-b5e6-96231b3b80d8
* Turn on -neon-reg-sequence by default.Evan Cheng2010-05-171-0/+170
| | | | | | | Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103960 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid allocating the same physreg to multiple virtregs in one instruction.Jakob Stoklund Olesen2010-05-171-0/+105
| | | | | | | | | While that approach works wonders for register pressure, it tends to break everything. This should unbreak the arm-linux builder and fix a number of miscompilations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103946 91177308-0d34-0410-b5e6-96231b3b80d8
* Some cheap DAG combine goodness for multiplication with a particular constant.Anton Korobeynikov2010-05-151-4/+30
| | | | | | This can be extended later on to handle more "complex" constants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103881 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow TargetLowering::getRegClassFor() to be called on illegal types. AlsoEvan Cheng2010-05-151-0/+10
| | | | | | | | allow target to override it in order to map register classes to illegal but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103854 91177308-0d34-0410-b5e6-96231b3b80d8
* Keep track of the last place a live virtreg was used.Jakob Stoklund Olesen2010-05-113-0/+3
| | | | | | | This allows us to add accurate kill markers, something the scavenger likes. Add some more tests from ARM that needed this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103521 91177308-0d34-0410-b5e6-96231b3b80d8
* Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.Evan Cheng2010-05-111-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103459 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct some bogus target triples.Duncan Sands2010-05-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103265 91177308-0d34-0410-b5e6-96231b3b80d8
* fix copy/paste oops.Jim Grosbach2010-05-051-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103122 91177308-0d34-0410-b5e6-96231b3b80d8
* Add tests for ARMV7M divide instruction useJim Grosbach2010-05-051-9/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103120 91177308-0d34-0410-b5e6-96231b3b80d8
* remove unneeded underscores.Jim Grosbach2010-05-051-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103114 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert to filecheckJim Grosbach2010-05-051-5/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103113 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul,Dan Gohman2010-05-0313-38/+38
| | | | | | | when the type is floating-point. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102969 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug which prevented tail merging of return instructions inDan Gohman2010-05-032-7/+8
| | | | | | | | | | | | | | | | | | | | | beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102907 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the -enable-sjlj-eh option, which doesn't do anything.Duncan Sands2010-05-023-8/+0
| | | | | | | | Remove the -enable-eh option which is only used by the JIT, and replace it with -jit-enable-eh. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102865 91177308-0d34-0410-b5e6-96231b3b80d8
* Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfieldJim Grosbach2010-04-221-0/+28
| | | | | | | | extraction. This fixes PR5998. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102144 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix tests for Neon load/store intrinsics to match the i8* types expected byBob Wilson2010-04-2010-94/+188
| | | | | | | | | | | the intrinsics. The reason for those i8* types is that the intrinsics are overloaded on the vector type and we don't have a way to declare an intrinsic where one argument is an overloaded vector type and another argument is a pointer to the vector element type. The bitcasts added here will match what the frontend will typically generate when these intrinsics are used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101840 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix declarations in a few more tests.Nick Lewycky2010-04-172-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101676 91177308-0d34-0410-b5e6-96231b3b80d8
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