| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging.... | Stephen Lin | 2013-07-13 | 7 | -7/+7 |
| * | Hexagon: Pass to replace tranfer/copy instructions into combine instruction | Jyotsna Verma | 2013-05-14 | 2 | -6/+38 |
| * | Hexagon: Add patterns to generate 'combine' instructions. | Jyotsna Verma | 2013-05-14 | 1 | -0/+80 |
| * | Hexagon: ArePredicatesComplement should not restrict itself to TFRs. | Jyotsna Verma | 2013-05-14 | 1 | -0/+32 |
| * | Hexagon: Test case to check if branch probabilities are properly reflected in | Jyotsna Verma | 2013-05-14 | 1 | -0/+79 |
| * | Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. | Jyotsna Verma | 2013-05-10 | 1 | -0/+28 |
| * | Hexagon: Use relation map for getMatchingCondBranchOpcode() and | Jyotsna Verma | 2013-05-09 | 1 | -0/+30 |
| * | Hexagon: Fix Small Data support to handle -G 0 correctly. | Jyotsna Verma | 2013-05-07 | 1 | -0/+26 |
| * | Reverting r181331. | Jyotsna Verma | 2013-05-07 | 1 | -26/+0 |
| * | Hexagon: Fix Small Data support to handle -G 0 correctly. | Jyotsna Verma | 2013-05-07 | 1 | -0/+26 |
| * | Hexagon - Add peephole optimizations for zero extends. | Pranav Bhandarkar | 2013-05-02 | 2 | -6/+24 |
| * | TBAA: remove !tbaa from testing cases if not used. | Manman Ren | 2013-04-30 | 6 | -40/+19 |
| * | Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions. | Jyotsna Verma | 2013-04-23 | 1 | -0/+45 |
| * | Hexagon: Remove assembler mapped instruction definitions. | Jyotsna Verma | 2013-04-23 | 1 | -0/+87 |
| * | Hexagon: Remove duplicate instructions to handle global/immediate values | Jyotsna Verma | 2013-04-23 | 1 | -0/+18 |
| * | Hexagon: Enable SupportDebugInfomation and DwarfInSection flags. | Jyotsna Verma | 2013-03-28 | 1 | -1/+0 |
| * | Hexagon: Use multiclass for gp-relative instructions. | Jyotsna Verma | 2013-03-28 | 1 | -0/+33 |
| * | Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. | Jyotsna Verma | 2013-03-26 | 1 | -0/+21 |
| * | Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and w... | Jyotsna Verma | 2013-03-22 | 4 | -0/+1465 |
| * | Hexagon: Removed asserts regarding alignment and offset. | Jyotsna Verma | 2013-03-14 | 1 | -0/+16 |
| * | Hexagon: Add patterns for zero extended loads from i1->i64. | Jyotsna Verma | 2013-03-08 | 1 | -0/+25 |
| * | Hexagon: Handle i8, i16 and i1 Var Args. | Jyotsna Verma | 2013-03-07 | 3 | -0/+124 |
| * | Hexagon: Add support to lower block address. | Jyotsna Verma | 2013-03-07 | 2 | -0/+78 |
| * | reverting patch 176508. | Jyotsna Verma | 2013-03-05 | 2 | -78/+0 |
| * | Hexagon: Add support for lowering block address. | Jyotsna Verma | 2013-03-05 | 2 | -0/+78 |
| * | Hexagon: Expand addc, adde, subc and sube. | Jyotsna Verma | 2013-03-05 | 2 | -0/+63 |
| * | Hexagon: Add encoding bits to the TFR64 instructions. | Jyotsna Verma | 2013-03-05 | 2 | -5/+5 |
| * | Hexagon: Add constant extender support framework. | Jyotsna Verma | 2013-03-01 | 2 | -0/+61 |
| * | Hexagon: Expand cttz, ctlz, and ctpop for now. | Anshuman Dasgupta | 2013-02-21 | 1 | -0/+34 |
| * | Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h. | Jyotsna Verma | 2013-02-20 | 2 | -2/+59 |
| * | Hexagon: add support for predicate-GPR copies. | Anshuman Dasgupta | 2013-02-13 | 1 | -0/+8 |
| * | Hexagon: Use absolute addressing mode loads/stores for global+offset | Jyotsna Verma | 2013-02-13 | 2 | -0/+86 |
| * | Hexagon: Add support to generate predicated absolute addressing mode | Jyotsna Verma | 2013-02-12 | 1 | -0/+19 |
| * | Extend Hexagon hardware loop generation to handle various additional cases: | Krzysztof Parzyszek | 2013-02-11 | 7 | -0/+1528 |
| * | Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle | Jyotsna Verma | 2013-02-05 | 3 | -0/+322 |
| * | Hexagon: Add testcase for post-increment store instructions. | Jyotsna Verma | 2013-02-05 | 1 | -0/+29 |
| * | Hexagon: Use multiclass for absolute addressing mode stores. | Jyotsna Verma | 2013-02-05 | 1 | -0/+46 |
| * | Hexagon: Add V4 compare instructions. Enable relationship mapping | Jyotsna Verma | 2013-02-05 | 2 | -0/+77 |
| * | Hexagon: Add V4 combine instructions and some more Def Pats for V2. | Jyotsna Verma | 2013-02-04 | 2 | -1/+56 |
| * | Hexagon: Test case to confirm generation of indexed loads with zero offset. | Jyotsna Verma | 2013-02-01 | 1 | -0/+70 |
| * | Add indexed load/store instructions for offset validation check. | Jyotsna Verma | 2013-01-17 | 1 | -0/+36 |
| * | In hexagon convertToHardwareLoop, don't deref end() iterator | Matthew Curtis | 2012-12-07 | 1 | -1/+1 |
| * | Use multiclass to define store instructions with base+immediate offset | Jyotsna Verma | 2012-12-05 | 2 | -4/+3 |
| * | test/CodeGen/Hexagon/postinc-load.ll: Suppress it for now. It triggered the f... | NAKAMURA Takumi | 2012-11-14 | 1 | -1/+1 |
| * | Added multiclass for post-increment load instructions. | Jyotsna Verma | 2012-11-14 | 1 | -0/+29 |
| * | LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access the | Pranav Bhandarkar | 2012-09-05 | 1 | -0/+80 |
| * | Porting Hexagon MI Scheduler to the new API. | Sergei Larin | 2012-09-04 | 3 | -4/+4 |
| * | Remove extra MayLoad/MayStore flags from atomic_load/store. | Jakob Stoklund Olesen | 2012-08-28 | 2 | -6/+0 |
| * | Infer instruction properties from single-instruction patterns. | Jakob Stoklund Olesen | 2012-08-24 | 2 | -0/+6 |
| * | [Hexagon] Don't mark callee saved registers as clobbered by a tail call | Arnold Schwaighofer | 2012-08-13 | 1 | -0/+14 |
