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* Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar2015-04-09255-3268/+4271
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-23321-3360/+10798
* MISched: Fix moving stores across barriersTom Stellard2015-01-211-0/+42
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-02328-4591/+15523
* Update LLVM for rebase to r212749.Stephen Hines2014-07-2199-442/+5427
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-2977-360/+2488
* Update to LLVM 3.5a.Stephen Hines2014-04-2490-311/+4679
* Merging r195881:Bill Wendling2013-12-011-2/+34
* Merging r195879:Bill Wendling2013-12-011-0/+692
* Merging r195878:Bill Wendling2013-12-011-0/+41
* Merging r195514:Bill Wendling2013-11-252-9/+577
* Merging r195398:Bill Wendling2013-11-221-0/+15
* R600/SI: Fix moveToVALU when the first operand is VSrc.Matt Arsenault2013-11-181-11/+10
* R600/SI: Fix multiple SGPR reads when using VCC.Matt Arsenault2013-11-181-3/+18
* R600/SI: Implement add i64, but do not yet enable.Matt Arsenault2013-11-181-0/+45
* R600/SI: Move patterns to match add / sub to scalar instructionsMatt Arsenault2013-11-184-20/+24
* R600: Enable the IR structurizer by defaultTom Stellard2013-11-183-3/+3
* R600: Fix a crash in the AMDILCFGStrucurizerTom Stellard2013-11-181-0/+62
* R600/SI: Fix illegal VGPR->SGPR copy inside of loopTom Stellard2013-11-181-0/+31
* R600/SI: Fix another case of illegal VGPR->SGPR copyTom Stellard2013-11-181-0/+26
* Use right address space pointer sizeMatt Arsenault2013-11-171-0/+11
* Fix assert on unaligned access to global with different address space size.Matt Arsenault2013-11-161-1/+23
* Fix codegen for null different sized pointer.Matt Arsenault2013-11-161-0/+11
* R600: Make dot_4 instructions predicableVincent Lejeune2013-11-161-0/+27
* R600/SI: Add VReg_96 register class to SIRegisterInfo::hasVGPRs()Tom Stellard2013-11-151-0/+46
* Add target hook to prevent folding some bitcasted loads.Matt Arsenault2013-11-151-0/+42
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-152-3/+104
* R600/SI: Add testcase for problem I ran intoMatt Arsenault2013-11-141-0/+18
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-134-20/+27
* R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard2013-11-138-109/+128
* R600: Fix selection failure on EXTLOADMatt Arsenault2013-11-131-0/+51
* R600/SI: Change formatting of printed registers.Matt Arsenault2013-11-1253-280/+279
* R600/SI: Add test that fails due to requiring i64 mul for pointersMatt Arsenault2013-11-111-0/+18
* R600: Use function inputs to represent data stored in gprVincent Lejeune2013-11-1125-280/+246
* R600: Fix LowerUDIVREMVincent Lejeune2013-11-061-4/+17
* Fix CodeGen for unaligned loads with address spacesMatt Arsenault2013-10-301-0/+19
* R600: Custom lower f32 = uint_to_fp i64Tom Stellard2013-10-301-4/+19
* R600/SI: Add compute support for CI v2Tom Stellard2013-10-291-7/+11
* R600: Expand vector FSQRT opsTom Stellard2013-10-291-0/+54
* R600/SI: fix MIMG writemask adjustementTom Stellard2013-10-231-0/+93
* R600: Fix handling of vector kernel argumentsTom Stellard2013-10-235-115/+502
* R600/SI: Add support for i64 bitwise orTom Stellard2013-10-231-4/+17
* R600/SI: Use S_LOAD_DWORD instructions for v8i32 and v16i32Tom Stellard2013-10-231-5/+10
* R600: Simplify handling of private address spaceTom Stellard2013-10-221-0/+39
* Fix CodeGen for vectors of pointers with address spaces.Matt Arsenault2013-10-211-0/+30
* Fix CodeGen for different size address space GEPsMatt Arsenault2013-10-211-0/+10
* R600: Fix a crash in the AMDILCFGStructurizerTom Stellard2013-10-161-0/+83
* R600: improve dump of S_WAITCNTVincent Lejeune2013-10-131-0/+37
* R600: Use masked read sel for texture instructionsVincent Lejeune2013-10-131-8/+7
* R600: fix swizzle exportVincent Lejeune2013-10-132-1/+147
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