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* Add missing zextloadi1 to i64 patterns. PR16721.Jakob Stoklund Olesen2013-06-071-0/+8
* Disallow i64 div/rem in PPC32 counter loopsHal Finkel2013-06-071-0/+93
* Revert commits related to stack warning.Quentin Colombet2013-06-072-48/+0
* Explicit triple in warn stack size test cases to not depend on OS.Quentin Colombet2013-06-072-4/+4
* R600: Fix calculation of stack offset in AMDGPUFrameLoweringTom Stellard2013-06-071-0/+33
* R600: Fix the fetch limits for R600 generation GPUsTom Stellard2013-06-072-0/+129
* Add a backend option to warn on a given stack size limit.Quentin Colombet2013-06-072-0/+48
* ARM FastISel integer sext/zext improvementsJF Bastien2013-06-079-29/+188
* Teach AsmPrinter how to print odd constants.Quentin Colombet2013-06-073-0/+52
* Fix a typo in asm string of BP* family of instructions. With this fixRoman Divacky2013-06-071-2/+2
* Support OpenBSD's native frame protection conventions.Rafael Espindola2013-06-071-0/+5
* [Sparc]: Use cmp instruction instead of subcc to compare integers.Venkatraman Govindaraju2013-06-074-17/+17
* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-051-0/+30
* R600: Schedule copy from phys register at beginning of blockVincent Lejeune2013-06-0510-10/+10
* [mips] brcond + setgt/setugt instruction selection patterns.Akira Hatanaka2013-06-051-0/+134
* [PATCH] Fix VGATHER* operand constraintsMichael Liao2013-06-051-0/+18
* R600: Make sure to schedule AR register uses and defs in the same clauseTom Stellard2013-06-051-0/+32
* Revert "R600: Add a pass that merge Vector Register"Rafael Espindola2013-06-051-30/+0
* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-041-0/+30
* R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune2013-06-041-0/+27
* Cortex-R5 can issue Thumb2 integer division instructions.Evan Cheng2013-06-042-20/+23
* ARM: Fix crash in ARM backend inside of ARMConstantIslandPassDavid Majnemer2013-06-041-0/+14
* R600: Swizzle texture/export instructionsVincent Lejeune2013-06-041-5/+5
* R600: Add a test for r183108Vincent Lejeune2013-06-041-0/+2
* R600/SI: Add support for work item and work group intrinsicsTom Stellard2013-06-031-0/+211
* R600/SI: Add a calling convention for compute shadersTom Stellard2013-06-037-10/+10
* R600/SI: Custom lower i64 sign_extendTom Stellard2013-06-031-0/+12
* R600/SI: Add support for global loadsTom Stellard2013-06-031-3/+49
* R600: use capital letter for PV channelVincent Lejeune2013-06-0314-17/+17
* Sparc: Add support for indirect branch and blockaddress in Sparc backend.Venkatraman Govindaraju2013-06-031-0/+77
* Sparc: When storing 0, use %g0 directly in the store instruction instead ofVenkatraman Govindaraju2013-06-032-0/+27
* Sparc: Combine add/or/sethi instruction with restore if possible.Venkatraman Govindaraju2013-06-024-8/+125
* Sparc: Perform leaf procedure optimization by defaultVenkatraman Govindaraju2013-06-029-34/+36
* Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics ...Venkatraman Govindaraju2013-06-012-0/+24
* Revert r183069: "TMP: LEA64_32r fixing"Tim Northover2013-06-011-4/+3
* TMP: LEA64_32r fixingTim Northover2013-06-011-3/+4
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-06-011-10/+10
* [Sparc] Generate correct code for leaf functions with stack objects Venkatraman Govindaraju2013-06-011-0/+23
* Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as itEric Christopher2013-05-311-10/+10
* Modify how the formulae are rated in Loop Strength Reduce.Quentin Colombet2013-05-311-3/+2
* [SystemZ] Don't use LOAD and STORE REVERSED for volatile accessesRichard Sandiford2013-05-314-24/+72
* [NVPTX] Re-enable support for virtual registers in the final outputJustin Holewinski2013-05-312-35/+35
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-05-311-10/+10
* [mips] Big-endian code generation for atomic instructions.Akira Hatanaka2013-05-311-160/+335
* Revert r182937 and r182877.Rafael Espindola2013-05-3024-82/+12
* Force a triple so we don't get bitten by windows' different regalloc.Benjamin Kramer2013-05-301-1/+1
* Force fragile test to the atom scheduler model.Benjamin Kramer2013-05-301-2/+4
* X86: allow registers 8-15 in testTim Northover2013-05-301-3/+3
* X86: use sub-register sequences for MOV*r0 operationsTim Northover2013-05-3013-24/+51
* [NVPTX] Fix case where a sext load of an i1 type may produce anJustin Holewinski2013-05-301-0/+14
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