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* X86: Stop LEA64_32r doing unspeakable things to its arguments.Tim Northover2013-06-103-6/+8
| | | | | | | | | | | | Previously LEA64_32r went through virtually the entire backend thinking it was using 32-bit registers until its blissful illusions were cruelly snatched away by MCInstLower and 64-bit equivalents were substituted at the last minute. This patch makes it behave normally, and take 64-bit registers as sources all the way through. Previous uses (for 32-bit arithmetic) are accommodated via SUBREG_TO_REG instructions which make the types and classes agree properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183693 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Remove old CONST_NOT_GEN address space that is not being used ↵Justin Holewinski2013-06-101-0/+10
| | | | | | anymore and causes constants to be emitted in the global address space git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183652 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test for ARM FastISel load/store register classesJF Bastien2013-06-101-0/+70
| | | | | | r183624 fixed an issue that was tested indirectly. Test it directly with this new test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183634 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a regression I introduced when I expanded the complex pseudos inReed Kotler2013-06-091-0/+6406
| | | | | | | | | | | the Mips16 port. A few of the psuedos could either take signed or unsigned arguments and I did not distinguish the case and improperly rejected some valid cases that the assembler had previously accepted when they were pure pseudos that expanded as assembly instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183633 91177308-0d34-0410-b5e6-96231b3b80d8
* Refine the ARM EHABI test cases.Logan Chien2013-06-099-413/+323
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we have ARM unwind directive parser and assembler, we can check the correctness in two stages: 1. From LLVM assembly (.ll) to ARM assembly (.s) 2. From ARM assembly (.s) to ELF object file (.o) We already have several "*.s to *.o" test cases. This CL adds some "*.ll to *.s" test cases and removes the redundant "*.ll to *.o" test cases. New test cases to check "*.ll to *.s" code generator: - ehabi.ll: Check the correctness of the generated unwind directives. - section-name.ll: Check the section name of functions. Removed test cases: - ehabi-mc-cantunwind.ll (Covered by ehabi-cantunwind.ll, and eh-directive-cantunwind.s) - ehabi-mc-compact-pr0.ll (Covered by ehabi.ll, eh-compact-pr0.s, eh-directive-save.s, and eh-directive-setfp.s) - ehabi-mc-compact-pr1.ll (Covered by ehabi.ll, eh-compact-pr1.s, eh-directive-save.s, and eh-directive-setfp.s) - ehabi-mc.ll (Covered by ehabi.ll, and eh-directive-integrated-test.s) - ehabi-mc-section-group.ll (Covered by section-name.ll, and eh-directive-section-comdat.s) - ehabi-mc-section.ll (Covered by section-name.ll, and eh-directive-section.s) - ehabi-mc-sh_link.ll (Covered by eh-directive-text-section.s, and eh-directive-section.s) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183628 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM unwind opcode assembler in several cases.Logan Chien2013-06-092-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes to ARM unwind opcode assembler: * Fix multiple .save or .vsave directives. Besides, the order is preserved now. * For the directives which will generate multiple opcodes, such as ".save {r0-r11}", the order of the unwind opcode is fixed now, i.e. the registers with less encoding value are popped first. * Fix the $sp offset calculation. Now, we can use the .setfp, .pad, .save, and .vsave directives at any order. Changes to test cases: * Add test cases to check the order of multiple opcodes for the .save directive. * Fix the incorrect $sp offset in the test case. The stack pointer offset specified in the test case was incorrect. (Changed test cases: ehabi-mc-section.ll and ehabi-mc.ll) * The opcode to restore $sp are slightly reordered. The behavior are not changed, and the new output is same as the output of GNU as. (Changed test cases: eh-directive-pad.s and eh-directive-setfp.s) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183627 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed PackedDouble domain from scalar instructions. Added more formats for ↵Elena Demikhovsky2013-06-092-3/+3
| | | | | | the scalar stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183626 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc ↵Venkatraman Govindaraju2013-06-081-0/+47
| | | | | | backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183613 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r183552. This time, use a standard type for the option to avoid templateQuentin Colombet2013-06-082-0/+48
| | | | | | | | | | | | | | | | instantiation issue with non-standard type. Add a backend option to warn on a given stack size limit. Option: -mllvm -warn-stack-size=<limit> Output (if limit is exceeded): warning: Stack size limit exceeded (<actual size>) in <functionName>. The longer term plan is to hook that to a clang warning. PR:4072 <rdar://problem/13987214>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183595 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Anti dep better handled in tex clauseVincent Lejeune2013-06-071-0/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183592 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing zextloadi1 to i64 patterns. PR16721.Jakob Stoklund Olesen2013-06-071-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183587 91177308-0d34-0410-b5e6-96231b3b80d8
* Disallow i64 div/rem in PPC32 counter loopsHal Finkel2013-06-071-0/+93
| | | | | | | | On PPC32, [su]div,rem on i64 types are transformed into runtime library function calls. As a result, they are not allowed in counter-based loops (the counter-loops verification pass caught this error; this change fixes PR16169). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183581 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert commits related to stack warning.Quentin Colombet2013-06-072-48/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183579 91177308-0d34-0410-b5e6-96231b3b80d8
* Explicit triple in warn stack size test cases to not depend on OS.Quentin Colombet2013-06-072-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183574 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix calculation of stack offset in AMDGPUFrameLoweringTom Stellard2013-06-071-0/+33
| | | | | | | | | | We weren't computing structure size correctly and we were relying on the original alloca instruction to compute the offset, which isn't always reliable. Reviewed-by: Vincent Lejeune <vljn@ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183568 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix the fetch limits for R600 generation GPUsTom Stellard2013-06-072-0/+129
| | | | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64257 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183560 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a backend option to warn on a given stack size limit.Quentin Colombet2013-06-072-0/+48
| | | | | | | | | | | | | Option: -mllvm -warn-stack-size=<limit> Output (if limit is exceeded): warning: Stack size limit exceeded (<actual size>) in <functionName>. The longer term plan is to hook that to a clang warning. PR:4072 <rdar://problem/13987214> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183552 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM FastISel integer sext/zext improvementsJF Bastien2013-06-079-29/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | My recent ARM FastISel patch exposed this bug: http://llvm.org/bugs/show_bug.cgi?id=16178 The root cause is that it can't select integer sext/zext pre-ARMv6 and asserts out. The current integer sext/zext code doesn't handle other cases gracefully either, so this patch makes it handle all sext and zext from i1/i8/i16 to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This should fix the bug as well as make FastISel faster because it bails to SelectionDAG less often. See fastisel-ext.patch for this. fastisel-ext-tests.patch changes current tests to always use reg-imm AND for 8-bit zext instead of UXTB. This simplifies code since it is supported on ARMv4t and later, and at least on A15 both should perform exactly the same (both have exec 1 uop 1, type I). 2013-05-31-char-shift-crash.ll is a bitcode version of the above bug 16178 repro. fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel should now handle. Note that my ARM FastISel enabling patch was reverted due to a separate failure when dealing with MCJIT, I'll fix this second failure and then turn FastISel on again for non-iOS ARM targets. I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15 hardware. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183551 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach AsmPrinter how to print odd constants.Quentin Colombet2013-06-073-0/+52
| | | | | | | | | | | | Fix an assertion when the compiler encounters big constants whose bit width is not a multiple of 64-bits. Although clang would never generate something like this, the backend should be able to handle any legal IR. <rdar://problem/13363576> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183544 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo in asm string of BP* family of instructions. With this fixRoman Divacky2013-06-071-2/+2
| | | | | | | I am able to compile/assemble/link/run /bin/echo from FreeBSD. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183537 91177308-0d34-0410-b5e6-96231b3b80d8
* Support OpenBSD's native frame protection conventions.Rafael Espindola2013-06-071-0/+5
| | | | | | | | | | | | | | | OpenBSD's stack smashing protection differs slightly from other platforms: 1. The smash handler function is "__stack_smash_handler(const char *funcname)" instead of "__stack_chk_fail(void)". 2. There's a hidden "long __guard_local" object that gets linked into each executable and DSO. Patch by Matthew Dempsky. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183533 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc]: Use cmp instruction instead of subcc to compare integers.Venkatraman Govindaraju2013-06-074-17/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183463 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-051-0/+30
| | | | | | | Previously commited @183279 but tests were failing, reverted @183286 It was broken because @183336 was missing, now it's there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183343 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Schedule copy from phys register at beginning of blockVincent Lejeune2013-06-0510-10/+10
| | | | | | It allows regalloc pass to remove them by trivially assigning associated reg git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183336 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] brcond + setgt/setugt instruction selection patterns.Akira Hatanaka2013-06-051-0/+134
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183334 91177308-0d34-0410-b5e6-96231b3b80d8
* [PATCH] Fix VGATHER* operand constraintsMichael Liao2013-06-051-0/+18
| | | | | | | | | | | | | | Add earlyclobber constaints to prevent input register being allocated as the output register because, according to Intel spec [1], "If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault." --- [1] http://software.intel.com/sites/default/files/319433-014.pdf git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183327 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Make sure to schedule AR register uses and defs in the same clauseTom Stellard2013-06-051-0/+32
| | | | | | Reviewed-by: vljn at ovi.com git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183294 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "R600: Add a pass that merge Vector Register"Rafael Espindola2013-06-051-30/+0
| | | | | | This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183286 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-041-0/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183279 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune2013-06-041-0/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183278 91177308-0d34-0410-b5e6-96231b3b80d8
* Cortex-R5 can issue Thumb2 integer division instructions.Evan Cheng2013-06-042-20/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183275 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix crash in ARM backend inside of ARMConstantIslandPassDavid Majnemer2013-06-041-0/+14
| | | | | | | | | | | The ARM backend did not expect LDRBi12 to hold a constant pool operand. Allow for LLVM to deal with the instruction similar to how it deals with LDRi12. This fixes PR16215. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183238 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Swizzle texture/export instructionsVincent Lejeune2013-06-041-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183229 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add a test for r183108Vincent Lejeune2013-06-041-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183228 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add support for work item and work group intrinsicsTom Stellard2013-06-031-0/+211
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183138 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add a calling convention for compute shadersTom Stellard2013-06-037-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183137 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Custom lower i64 sign_extendTom Stellard2013-06-031-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183136 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add support for global loadsTom Stellard2013-06-031-3/+49
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183131 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: use capital letter for PV channelVincent Lejeune2013-06-0314-17/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183107 91177308-0d34-0410-b5e6-96231b3b80d8
* Sparc: Add support for indirect branch and blockaddress in Sparc backend.Venkatraman Govindaraju2013-06-031-0/+77
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183094 91177308-0d34-0410-b5e6-96231b3b80d8
* Sparc: When storing 0, use %g0 directly in the store instruction instead ofVenkatraman Govindaraju2013-06-032-0/+27
| | | | | | | using two instructions (sethi and store). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183090 91177308-0d34-0410-b5e6-96231b3b80d8
* Sparc: Combine add/or/sethi instruction with restore if possible.Venkatraman Govindaraju2013-06-024-8/+125
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183088 91177308-0d34-0410-b5e6-96231b3b80d8
* Sparc: Perform leaf procedure optimization by defaultVenkatraman Govindaraju2013-06-029-34/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183083 91177308-0d34-0410-b5e6-96231b3b80d8
* Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics ↵Venkatraman Govindaraju2013-06-012-0/+24
| | | | | | as non-leaf functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183079 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r183069: "TMP: LEA64_32r fixing"Tim Northover2013-06-011-4/+3
| | | | | | Very sorry, it was committed from the wrong branch by mistake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183070 91177308-0d34-0410-b5e6-96231b3b80d8
* TMP: LEA64_32r fixingTim Northover2013-06-011-3/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183069 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-06-011-10/+10
| | | | | | | | | | | | | | The MOV64ri64i32 instruction required hacky MCInst lowering because it was allocated as setting a GR64, but the eventual instruction ("movl") only set a GR32. This converts it into a so-called "MOV32ri64" which still accepts a (appropriate) 64-bit immediate but defines a GR32. This is then converted to the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy. This fixes a typo in the opcode field of the original patch, which should make the legact JIT work again (& adds test for that problem). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183068 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Generate correct code for leaf functions with stack objects Venkatraman Govindaraju2013-06-011-0/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183067 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as itEric Christopher2013-05-311-10/+10
| | | | | | seems to have caused PR16192 and other JIT related failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183059 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify how the formulae are rated in Loop Strength Reduce.Quentin Colombet2013-05-311-3/+2
| | | | | | | | | | | | | | | Namely, check if the target allows to fold more that one register in the addressing mode and if yes, adjust the cost accordingly. Prior to this commit, reg1 + scale * reg2 accesses were artificially preferred to reg1 + reg2 accesses. Indeed, the cost model wrongly assumed that reg1 + reg2 needs a temporary register for the computation, whereas it was correctly estimated for reg1 + scale * reg2. <rdar://problem/13973908> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183021 91177308-0d34-0410-b5e6-96231b3b80d8
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