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* radeonsi: clean up compute flushBas Nieuwenhuizen2016-04-191-15/+8
| | | | | | Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: split setting graphics and compute descriptorsBas Nieuwenhuizen2016-04-191-1/+1
| | | | | | Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: split texture decompression for compute shadersBas Nieuwenhuizen2016-04-191-1/+1
| | | | | | Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: Add CE synchronization.Bas Nieuwenhuizen2016-04-191-0/+26
| | | | | Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeonsi: always use PFP_SYNC_ME when doing flushes and waitsMarek Olšák2016-04-181-1/+9
| | | | | | This is typically used by the closed driver before SURFACE_SYNC. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: don't do VS/PS partial flushes if SURFACE_SYNC waits tooMarek Olšák2016-04-181-11/+14
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: add safety assertions for meta cache flushesMarek Olšák2016-04-181-0/+4
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: don't use ACQUIRE_MEM on the graphics ringMarek Olšák2016-04-181-18/+8
| | | | | | | | | It's only required on the compute ring. This matches the closed driver. The compute flag is removed to prevent confusion and Bas's compute shader patches remove it in the whole function. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: remove TODO and correct a comment in si_emit_cache_flushMarek Olšák2016-04-181-2/+1
| | | | | | Yes, that flag is really needed. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: move pipeline stat context flags to common codeMarek Olšák2016-04-121-2/+2
| | | | | Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: unify checking streamout enable stateMarek Olšák2016-04-121-2/+1
| | | | | Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: implement and rely on set_active_query_stateMarek Olšák2016-04-121-0/+10
| | | | | Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: move si_decompress_textures to si_blit.cNicolai Hähnle2016-03-101-15/+0
| | | | | | | | | Since it is all about calling into blitter functions, it makes more sense here. This change also reduces the size of the interfaces between .c files. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* gallium/radeon: disable CMASK on handle export if sharing doesn't allow it (v2)Marek Olšák2016-03-091-1/+11
| | | | | | | v2: remove the list of all contexts Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: add struct si_shader_configMarek Olšák2016-01-071-2/+2
| | | | | | | There will be 1 config per variant, which will be a union of configs from {prolog, main, epilog}. For now, just add the structure. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* u_upload_mgr: pass alignment to u_upload_data manuallyMarek Olšák2016-01-021-1/+1
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* u_upload_mgr: pass alignment to u_upload_alloc manuallyMarek Olšák2016-01-021-1/+1
| | | | | | | | | | The fixed alignment of u_upload_mgr will go away. This is the first step. The motivation is that one u_upload_mgr can have multiple users, each allocating from the same buffer, but requiring a different alignment. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: apply the streamout workaround to Fiji as wellMarek Olšák2015-12-111-1/+3
| | | | | Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* radeonsi: don't call of u_prims_for_vertices for patches and rectanglesMarek Olšák2015-12-111-1/+13
| | | | | | | | | Both caused a crash due to a division by zero in that function. This is an alternative fix. Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* radeonsi: Rename si_shader::ls_rsrc{1,2} to si_shader::rsrc{1,2}Tom Stellard2015-11-251-2/+2
| | | | | | In the future, these will be used by other shaders types. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* gallium/radeon: shorten render_cond variable namesMarek Olšák2015-11-131-1/+1
| | | | | | and ..._cond -> ..._invert Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: remove predicate_drawing flagMarek Olšák2015-11-131-1/+1
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: simplify disabling render condition for u_blitterMarek Olšák2015-11-131-4/+5
| | | | | | just disable it by not setting the predication bit Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* gallium/radeon: inline the r600_rings structureMarek Olšák2015-11-131-12/+12
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: rename cache flushing flags once moreMarek Olšák2015-11-131-6/+4
| | | | | | | | | | | | | | | KCACHE, TC L1 and TC L2 are renamed to: - SMEM L1 - VMEM L1 - GLOBAL L2 You can easily tell what they are used for now. Shaders must deal with coherency issues between both L1s manually, e.g. by setting GLC=1 or by using s_dcache_*. BOTH_ICACHE_KCACHE was an unused definition. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: Add FLUSH_AND_INV_CB_DATA_TS for DCC.Bas Nieuwenhuizen2015-10-241-0/+11
| | | | | Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
* radeonsi: add another requirement for PARTIAL_ES_WAVEMarek Olšák2015-10-241-0/+4
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: merge two ifs setting WD_SWITCH_ON_EOPMarek Olšák2015-10-241-5/+2
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: make PARTIAL_ES_WAVE globally dependent on SWITCH_ON_EOIMarek Olšák2015-10-241-5/+6
| | | | | | This catches the other cases that enable SWITCH_ON_EOI. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: add one more SWITCH_ON_EOI requirement for Hawaii and VIMarek Olšák2015-10-241-1/+10
| | | | | | The VI condition depends on geometry shaders and MAX_PRIMGRP_IN_WAVE. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: only apply the instancing bug workaround to BonaireMarek Olšák2015-10-241-5/+5
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: add SWITCH_ON_EOI requirement for 4 SE partsMarek Olšák2015-10-241-0/+4
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: remove unnecessary PARTIAL_VS_WAVE setting for streamoutMarek Olšák2015-10-241-4/+0
| | | | | | hardware does this automatically Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: add draw_vbo check for a NULL pixel shaderMarek Olšák2015-10-241-1/+6
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: support thread-safe shaders shared by multiple contextsMarek Olšák2015-10-201-22/+22
| | | | | | | | | | | | The "current" shader pointer is moved from the CSO to the context, so that the CSO is mostly immutable. The only drawback is that the "current" pointer isn't saved when unbinding a shader and it must be looked up when the shader is bound again. This is also a prerequisite for multithreaded shader compilation. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: remove TC L2 cache flush for index buffers on VIMarek Olšák2015-10-071-3/+3
| | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* gallium/radeon: add separate stencil level dirty flagsMarek Olšák2015-10-031-0/+3
| | | | | | | We will only do depth-only or stencil-only decompress blits, whichever is needed by textures, instead of always doing both. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: tell the winsys the exact resource binding typesMarek Olšák2015-10-031-5/+5
| | | | | | | Use the priority flags and expand them. This information will be used for debugging. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: skip drawing if the tess factor ring allocation failsMarek Olšák2015-09-241-2/+2
| | | | | | Cc: 11.0 <mesa-stable@lists.freedesktop.org> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: handle index buffer alloc failuresMarek Olšák2015-09-241-0/+6
| | | | | | Cc: 11.0 <mesa-stable@lists.freedesktop.org> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: don't send IB dword usage to si_need_cs_spaceMarek Olšák2015-09-011-1/+1
| | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
* gallium/radeon: rename r600_context_bo_reloc -> radeon_add_to_buffer_listMarek Olšák2015-09-011-5/+5
| | | | | | | this name should be easy to understand without other knowledge Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
* gallium/radeon: rename write_*_reg functionsMarek Olšák2015-09-011-15/+15
| | | | | | | | e.g. radeon_set_context_reg is nicer and looks consistent next to radeon_emit(). Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
* radeonsi: use a bitmask for tracking dirty atomsMarek Olšák2015-09-011-6/+7
| | | | | | | | This mainly removes the cache misses when checking the dirty flags. Not much else though. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
* radeonsi: call si_init_atom for remaining radeonsi atomsMarek Olšák2015-09-011-3/+2
| | | | | | | | | | I need to initialize more atom IDs. This adds 4 more si_init_atom calls, which simplifies the code. (si_init_atom needs a different context type of the emit functions though) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
* radeonsi: define the state atom array separatelyMarek Olšák2015-09-011-1/+1
| | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com>
* radeonsi: add IB parser support for CP DMA packetsMarek Olšák2015-08-261-3/+3
| | | | | | | | | If the packet encoding is defined in the same format as register definitions, the python script can process them automatically and the parser support becomes trivial. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
* radeonsi: add IB tracing support for debug contextsMarek Olšák2015-08-261-10/+9
| | | | | | | | | This adds trace points to all IBs and the parser prints them and also prints which trace points were reached (executed) by the CP. This can help pinpoint a problematic packet, draw call, etc. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
* radeonsi: remove old CS tracing codeMarek Olšák2015-08-261-6/+1
| | | | | | | Some of it is left there and it will be re-used in the next commit. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
* radeonsi: add VI hardware supportMarek Olšák2015-08-141-10/+31
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