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author | Stephen Hines <srhines@google.com> | 2014-12-01 14:51:49 -0800 |
---|---|---|
committer | Stephen Hines <srhines@google.com> | 2014-12-02 16:08:10 -0800 |
commit | 37ed9c199ca639565f6ce88105f9e39e898d82d0 (patch) | |
tree | 8fb36d3910e3ee4c4e1b7422f4f017108efc52f5 /test/MC/Mips/mips32r6 | |
parent | d2327b22152ced7bc46dc629fc908959e8a52d03 (diff) | |
download | external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.zip external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.gz external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.bz2 |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
Diffstat (limited to 'test/MC/Mips/mips32r6')
-rw-r--r-- | test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s | 12 | ||||
-rw-r--r-- | test/MC/Mips/mips32r6/invalid-mips1.s | 4 | ||||
-rw-r--r-- | test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s | 14 | ||||
-rw-r--r-- | test/MC/Mips/mips32r6/invalid-mips2.s | 12 | ||||
-rw-r--r-- | test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s | 20 | ||||
-rw-r--r-- | test/MC/Mips/mips32r6/invalid-mips32.s | 2 | ||||
-rw-r--r-- | test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s | 16 | ||||
-rw-r--r-- | test/MC/Mips/mips32r6/invalid-mips4.s | 2 | ||||
-rw-r--r-- | test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s | 8 | ||||
-rw-r--r-- | test/MC/Mips/mips32r6/valid.s | 23 |
10 files changed, 66 insertions, 47 deletions
diff --git a/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s index 52fa5f5..cc7d403 100644 --- a/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s +++ b/test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s @@ -5,13 +5,13 @@ # RUN: FileCheck %s < %t1 .set noat - bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction lwl $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips32r6/invalid-mips1.s b/test/MC/Mips/mips32r6/invalid-mips1.s index 44d4fbb..94810f4 100644 --- a/test/MC/Mips/mips32r6/invalid-mips1.s +++ b/test/MC/Mips/mips32r6/invalid-mips1.s @@ -5,6 +5,8 @@ # RUN: FileCheck %s < %t1 .set noat + add $9,$14,15176 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + add $24,-7193 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -22,3 +24,5 @@ multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled # div has been re-encoded. See valid.s # divu has been re-encoded. See valid.s + sub $22,$17,-3126 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sub $13,6512 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s index b799c8e..1cec777 100644 --- a/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s +++ b/test/MC/Mips/mips32r6/invalid-mips2-wrong-error.s @@ -6,15 +6,5 @@ # RUN: FileCheck %s < %t1 .set noat - beql $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bgezall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bgezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bgtzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - blezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bltzall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bltzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bnel $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips32r6/invalid-mips2.s b/test/MC/Mips/mips32r6/invalid-mips2.s index bfa2c4c..642d6bd 100644 --- a/test/MC/Mips/mips32r6/invalid-mips2.s +++ b/test/MC/Mips/mips32r6/invalid-mips2.s @@ -6,6 +6,18 @@ .set noat addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1fl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1fl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1tl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1tl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + beql $14,$s3,12544 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bnel $gp,$s4,5107 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezl $4,-6858 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgtzl $10,-3738 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + blezl $6,2974 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltzl $s1,-9964 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bltzall $6,488 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s index e63bdd4..3131c5a 100644 --- a/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s +++ b/test/MC/Mips/mips32r6/invalid-mips32-wrong-error.s @@ -6,15 +6,11 @@ # RUN: FileCheck %s < %t1 .set noat - bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2f 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2f $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2t 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2t $fcc0,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2tl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2fl $fcc1,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips32r6/invalid-mips32.s b/test/MC/Mips/mips32r6/invalid-mips32.s index e0889ea..b2330c2 100644 --- a/test/MC/Mips/mips32r6/invalid-mips32.s +++ b/test/MC/Mips/mips32r6/invalid-mips32.s @@ -5,6 +5,8 @@ # RUN: FileCheck %s < %t1 .set noat + bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s index f3131a9..06bf58c 100644 --- a/test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s +++ b/test/MC/Mips/mips32r6/invalid-mips4-wrong-error.s @@ -6,16 +6,6 @@ # RUN: FileCheck %s < %t1 .set noat - beql $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bgezall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bgezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bgtzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - blezl $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bltzall $3,8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bltzl $4,16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bnel $1,$2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips32r6/invalid-mips4.s b/test/MC/Mips/mips32r6/invalid-mips4.s index 8ba2ed8..9d8f02f 100644 --- a/test/MC/Mips/mips32r6/invalid-mips4.s +++ b/test/MC/Mips/mips32r6/invalid-mips4.s @@ -5,6 +5,8 @@ # RUN: FileCheck %s < %t1 .set noat + bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s b/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s index 99d10c3..b5d7380 100644 --- a/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s +++ b/test/MC/Mips/mips32r6/invalid-mips5-wrong-error.s @@ -5,7 +5,7 @@ # RUN: FileCheck %s < %t1 .set noat - bc1any2f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1any2t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1any4f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction - bc1any4t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: Unknown instruction + bc1any2f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc1any2t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc1any4f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + bc1any4t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s index f23dbd7..362785b 100644 --- a/test/MC/Mips/mips32r6/valid.s +++ b/test/MC/Mips/mips32r6/valid.s @@ -17,6 +17,7 @@ # FIXME: Add the instructions carried forward from older ISA's and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] addiupc $4, 100 # CHECK: addiupc $4, 100 # encoding: [0xec,0x80,0x00,0x19] + addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x7c,0x43,0x22,0xa0] aluipc $3, 56 # CHECK: aluipc $3, 56 # encoding: [0xec,0x7f,0x00,0x38] aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x3c,0x62,0xff,0xe9] @@ -96,8 +97,12 @@ cmp.sle.d $f2,$f3,$f4 # CHECK: cmp.sle.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8e] cmp.sule.s $f2,$f3,$f4 # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x46,0x84,0x18,0x8f] cmp.sule.d $f2,$f3,$f4 # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x46,0xa4,0x18,0x8f] + di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00] + di # CHECK: di # encoding: [0x41,0x60,0x60,0x00] div $2,$3,$4 # CHECK: div $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9a] divu $2,$3,$4 # CHECK: divu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x9b] + ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] + ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] jialc $5, 256 # CHECK: jialc $5, 256 # encoding: [0xf8,0x05,0x01,0x00] jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xd8,0x05,0x01,0x00] lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0xc5] @@ -114,6 +119,12 @@ msubf.s $f2,$f3,$f4 # CHECK: msubf.s $f2, $f3, $f4 # encoding: [0x46,0x04,0x18,0x99] msubf.d $f2,$f3,$f4 # CHECK: msubf.d $f2, $f3, $f4 # encoding: [0x46,0x24,0x18,0x99] pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0x7c,0xa1,0x04,0x35] + # FIXME: Use the code generator in order to print the .set directives + # instead of the instruction printer. + rdhwr $sp,$11 # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $sp, $11 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] sel.d $f0,$f1,$f2 # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10] sel.s $f0,$f1,$f2 # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10] seleqz $2,$3,$4 # CHECK: seleqz $2, $3, $4 # encoding: [0x00,0x64,0x10,0x35] @@ -152,3 +163,15 @@ sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x00,0x08,0x8e] sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] + teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] + tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] + tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] + tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] + tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] + tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32] + tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] + tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] + tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] + tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] + tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] |