| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Update to LLVM 3.5a. | Stephen Hines | 2014-04-24 | 1 | -3/+14 |
| * | Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes ... | Silviu Baranga | 2013-09-04 | 1 | -78/+54 |
| * | Update machine models. Specify buffer sizes for OOO processors. | Andrew Trick | 2013-06-15 | 1 | -2/+2 |
| * | Machine Model: Add MicroOpBufferSize and resource BufferSize. | Andrew Trick | 2013-06-15 | 1 | -4/+1 |
| * | ARM sched model: Add integer VFP/SIMD instructions on Swift | Arnold Schwaighofer | 2013-06-06 | 1 | -0/+1 |
| * | ARM sched model: Cortex A9 - More InstRW sched resources | Arnold Schwaighofer | 2013-06-06 | 1 | -4/+45 |
| * | ARM sched model: Add divsion, loads, branches, vfp cvt | Arnold Schwaighofer | 2013-06-05 | 1 | -0/+7 |
| * | Revert series of sched model patches until I figure out what is going on. | Arnold Schwaighofer | 2013-06-04 | 1 | -52/+4 |
| * | ARM sched model: Cortex A9 - More InstRW sched resources | Arnold Schwaighofer | 2013-06-04 | 1 | -4/+45 |
| * | ARM sched model: Add divsion, loads, branches, vfp cvt | Arnold Schwaighofer | 2013-06-04 | 1 | -0/+7 |
| * | ARM scheduler model: Add scheduler info to more instructions and resource | Arnold Schwaighofer | 2013-04-05 | 1 | -7/+13 |
| * | ARM Scheduler Model: Add resources instructions, map resources in subtargets | Arnold Schwaighofer | 2013-04-01 | 1 | -23/+24 |
| * | Revert ARM Scheduler Model: Add resources instructions, map resources | Arnold Schwaighofer | 2013-03-26 | 1 | -11/+8 |
| * | ARM Scheduler Model: Add resources instructions, map resources in subtargets | Arnold Schwaighofer | 2013-03-26 | 1 | -8/+11 |
| * | MIsched: add an ILP window property to machine model. | Andrew Trick | 2013-01-09 | 1 | -0/+3 |
| * | Cortex-A9 latency fixes (w/ -schedmodel only). | Andrew Trick | 2012-09-21 | 1 | -5/+5 |
| * | Cortex-A9 instruction-level scheduling machine model. | Andrew Trick | 2012-09-14 | 1 | -3/+594 |
| * | Added MispredictPenalty to SchedMachineModel. | Andrew Trick | 2012-08-08 | 1 | -0/+1 |
| * | I'm introducing a new machine model to simultaneously allow simple | Andrew Trick | 2012-07-07 | 1 | -5/+23 |
| * | Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." | Andrew Trick | 2012-07-02 | 1 | -13/+22 |
| * | Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary." | Andrew Trick | 2012-06-29 | 1 | -22/+13 |
| * | Make NumMicroOps a variable in the subtarget's instruction itinerary. | Andrew Trick | 2012-06-29 | 1 | -13/+22 |
| * | ARM itinerary properties. | Andrew Trick | 2012-06-05 | 1 | -1/+5 |
| * | Fix a number of problems with ARM fused multiply add/subtract instructions. | Evan Cheng | 2012-04-11 | 1 | -0/+36 |
| * | Improvements for the Cortex-A9 scheduling itineraries. | Bob Wilson | 2011-04-19 | 1 | -12/+16 |
| * | Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That | Evan Cheng | 2011-04-19 | 1 | -172/+171 |
| * | Sorry, several patches in one. | Evan Cheng | 2011-01-20 | 1 | -0/+10 |
| * | Fix the ARM IIC_iCMPsi itinerary and add an important assert. | Andrew Trick | 2011-01-04 | 1 | -1/+2 |
| * | Fix an obvious cut-n-paste error. | Evan Cheng | 2010-12-08 | 1 | -2/+2 |
| * | Add support for NEON VLD3-dup instructions. | Bob Wilson | 2010-11-30 | 1 | -0/+18 |
| * | Add support for NEON VLD3-dup instructions. | Bob Wilson | 2010-11-29 | 1 | -0/+18 |
| * | Fix copy-and-paste errors in VLD2-dup scheduling itineraries. | Bob Wilson | 2010-11-29 | 1 | -2/+2 |
| * | Add support for NEON VLD2-dup instructions. | Bob Wilson | 2010-11-28 | 1 | -0/+18 |
| * | Add NEON VLD1-dup instructions (load 1 element to all lanes). | Bob Wilson | 2010-11-27 | 1 | -0/+18 |
| * | Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions. | Bob Wilson | 2010-11-27 | 1 | -4/+4 |
| * | Conditional moves are slightly more expensive than moves. | Evan Cheng | 2010-11-13 | 1 | -0/+4 |
| * | Fix preload instruction isel. Only v7 supports pli, and only v7 with mp exten... | Evan Cheng | 2010-11-03 | 1 | -0/+4 |
| * | Modify scheduling itineraries to correct instruction latencies (not operand | Evan Cheng | 2010-11-03 | 1 | -77/+77 |
| * | Add NEON VST1-lane instructions. Partial fix for Radar 8599955. | Bob Wilson | 2010-11-02 | 1 | -0/+18 |
| * | Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. | Bob Wilson | 2010-11-01 | 1 | -0/+18 |
| * | Fix fpscr <-> GPR latency info. | Evan Cheng | 2010-10-29 | 1 | -1/+2 |
| * | Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. | Evan Cheng | 2010-10-28 | 1 | -2/+2 |
| * | Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ... | Evan Cheng | 2010-10-28 | 1 | -2/+2 |
| * | - Assign load / store with shifter op address modes the right itinerary classes. | Evan Cheng | 2010-10-28 | 1 | -2/+2 |
| * | putback r116983 and fix simple-fp-encoding.ll tests | Andrew Trick | 2010-10-21 | 1 | -4/+4 |
| * | Revert r116983, which is breaking all the buildbots. | Owen Anderson | 2010-10-21 | 1 | -4/+4 |
| * | Add missing scheduling itineraries for transfers between core registers and V... | Evan Cheng | 2010-10-21 | 1 | -4/+4 |
| * | Limit load / store issues (at least until we have a true multi-issue aware sc... | Evan Cheng | 2010-10-13 | 1 | -107/+158 |
| * | More ARM scheduling itinerary fixes. | Evan Cheng | 2010-10-11 | 1 | -372/+439 |
| * | Proper VST scheduling itineraries. | Evan Cheng | 2010-10-11 | 1 | -7/+131 |
