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* Restore an accidentally removed comment.Cameron Zwarich2011-05-251-0/+1
* Change the order of tBX's operands so that the predicate operands come after theCameron Zwarich2011-05-251-1/+10
* Rename tBX_Rm to tBX.Cameron Zwarich2011-05-251-2/+2
* Fix Bug 9386 - ARM disassembler failed to disassemble conditional bxJohnny Chen2011-05-221-3/+4
* Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immedi...Johnny Chen2011-05-181-1/+1
* Fix a bug in the case that there is no add or subtract symbol and the offsetKevin Enderby2011-04-271-2/+6
* Fix typo in the comment.Johnny Chen2011-04-191-1/+1
* Thumb2 BFC was insufficiently encoded.Johnny Chen2011-04-151-1/+1
* A8.6.315 VLD3 (single 3-element structure to all lanes)Johnny Chen2011-04-151-0/+6
* The ARM disassembler did not handle the alignment correctly for VLD*DUP* inst...Johnny Chen2011-04-151-0/+27
* Add sanity checkings for Thumb2 Load/Store Register Exclusive family of opera...Johnny Chen2011-04-141-4/+41
* Thumb disassembler did not handle tBRIND (indirect branch) properly.Johnny Chen2011-04-131-6/+10
* Check for unallocated instruction encodings when disassembling Thumb Branch i...Johnny Chen2011-04-131-5/+11
* The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.Johnny Chen2011-04-131-6/+14
* Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as...Johnny Chen2011-04-131-1/+33
* Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was no...Johnny Chen2011-04-131-3/+11
* Add sanity check for Ld/St Dual forms of Thumb2 instructions.Johnny Chen2011-04-121-0/+29
* The Thumb2 RFE instructions need to have their second halfword fully specified.Johnny Chen2011-04-121-2/+6
* Add bad register checks for Thumb2 Ld/St instructions.Johnny Chen2011-04-121-0/+45
* The Thumb2 Ld, St, and Preload instructions with the i12 forms should have it...Johnny Chen2011-04-121-0/+2
* Print out a debug message when the reglist fails the sanity check for Thumb L...Johnny Chen2011-04-122-0/+29
* A8.6.16 BJohnny Chen2011-04-121-0/+5
* Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen2011-04-111-2/+5
* Fix the bug where the immediate shift amount for Thumb logical shift instruct...Johnny Chen2011-04-111-6/+17
* Trivial comment fix.Johnny Chen2011-04-112-2/+2
* Check invalid register encodings for LdFrm/StFrm ARM instructions and flag th...Johnny Chen2011-04-111-0/+68
* Adding support for printing operands symbolically to llvm's public 'C'Kevin Enderby2011-04-114-6/+139
* Fix an apparent typo that made GCC complainMatt Beaumont-Gay2011-04-081-1/+1
* Check opcoe (dmb, dsb) instead of bitfields matching.Johnny Chen2011-04-081-12/+1
* Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.Johnny Chen2011-04-081-9/+10
* Sanity check the option operand for DMB/DSB.Johnny Chen2011-04-082-8/+29
* Add sanity checking for bad register specifier(s) for the DPFrm instructions.Johnny Chen2011-04-081-0/+30
* Add sanity checking for invalid register encodings for signed/unsigned extend...Johnny Chen2011-04-071-0/+5
* Add sanity checking for invalid register encodings for saturating instructions.Johnny Chen2011-04-071-0/+5
* Add some more comments about checkings of invalid register numbers.Johnny Chen2011-04-071-0/+5
* Sanity check MSRi for invalid mask values and reject it as invalid.Johnny Chen2011-04-071-0/+5
* The ARM disassembler was not recognizing USADA8 instruction. Need to add che...Johnny Chen2011-04-071-3/+5
* Should also check SMLAD for invalid register values.Johnny Chen2011-04-071-6/+12
* A8.6.393Johnny Chen2011-04-061-26/+47
* A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"Johnny Chen2011-04-061-1/+14
* Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.Johnny Chen2011-04-061-1/+1
* Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.Johnny Chen2011-04-061-7/+3
* Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal...Johnny Chen2011-04-051-1/+7
* A7.3 register encodingJohnny Chen2011-04-051-0/+10
* ARM disassembler was erroneously accepting an invalid RSC instruction.Johnny Chen2011-04-051-0/+6
* ARM disassembler was erroneously accepting an invalid LSL instruction.Johnny Chen2011-04-051-0/+4
* The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.Johnny Chen2011-04-051-7/+19
* ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.Johnny Chen2011-04-051-2/+10
* Make second source operand of LDRD pre/post explicit.Jim Grosbach2011-04-051-5/+2
* Check for invalid register encodings for UMAAL and friends where:Johnny Chen2011-04-051-2/+49
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