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* Update aosp/master LLVM with patches for fp16Pirama Arumuga Nainar2015-05-261-2/+22
| | | | | | | | | | Cherry-pick LLVM revisions r235191, r235215, r235220, r235341, r235363, r235530, r235609, r235610, r237004 r235191 has a required bug-fix and the rest are all related to fp16. Change-Id: I7fe8da5ffd8f2c06150885a54769abd18c3a04c6 (cherry picked from commit a18e6af1712fd41c4a705a19ad71f6e9ac7a4e68)
* Update aosp/master LLVM for rebase to r235153Pirama Arumuga Nainar2015-05-181-0/+1
| | | | | Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7 (cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
* Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar2015-04-091-1/+45
| | | | Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-167/+280
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-535/+544
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update LLVM for rebase to r212749.Stephen Hines2014-07-211-78/+169
| | | | | | | Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-171/+125
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Update to LLVM 3.5a.Stephen Hines2014-04-241-69/+123
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* [mips] Fix a bug in function CC_MipsO32_FP64. The second double precisionAkira Hatanaka2013-11-121-1/+1
| | | | | | | | argument was not being passed in $f14. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194522 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Revert part of r194510 that was accidentally committed.Akira Hatanaka2013-11-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194511 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix and re-enable a test case that has been disabled for a long time.Akira Hatanaka2013-11-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194510 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Enable inlinse assembly for MSA.Daniel Sanders2013-11-121-9/+46
| | | | | | | | | | | | | | | | Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194476 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Make sure there is a chain edge dependency between loads that readAkira Hatanaka2013-11-091-3/+5
| | | | | | | | | | formal arguments on the stack and stores created afterwards. We need this to ensure tail call optimized function calls do not write over the argument area of the stack before it is read out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194309 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Simplify LowerFormalArguments using getRegClassFor.Akira Hatanaka2013-10-281-15/+2
| | | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193540 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename isel nodes.Akira Hatanaka2013-10-151-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192663 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Transfer kill flag to the newly created operand.Akira Hatanaka2013-10-151-1/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192662 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Do not generate INS/EXT nodes if target does not have support forAkira Hatanaka2013-10-091-14/+18
| | | | | | | | ins/ext. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192330 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Coding style clean up.Akira Hatanaka2013-10-071-48/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192125 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix definition of mfhi and mflo instructions to read from the wholeAkira Hatanaka2013-10-071-1/+2
| | | | | | | | | | | | | | | | | accumulator instead of its sub-registers, $hi and $lo. We need this change to prevent a mflo following a mtlo from reading an unpredictable/undefined value, as shown in the following example: mult $6, $7 // result of $6 * $7 is written to $lo and $hi. mflo $2 // read lower 32-bit result from $lo. mtlo $4 // write to $lo. the content of $hi becomes unpredictable. mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value. I don't have a test case for this change that reliably reproduces the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192119 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted outAkira Hatanaka2013-09-281-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | of loops. Previously, two consecutive calls to function "func" would result in the following sequence of instructions: 1. load $16, %got(func)($gp) // load address of lazy-binding stub. 2. move $25, $16 3. jalr $25 // jump to lazy-binding stub. 4. nop 5. move $25, $16 6. jalr $25 // jump to lazy-binding stub again. With this patch, the second call directly jumps to func's address, bypassing the lazy-binding resolution routine: 1. load $25, %got(func)($gp) // load address of lazy-binding stub. 2. jalr $25 // jump to lazy-binding stub. 3. nop 4. load $25, %got(func)($gp) // load resolved address of func. 5. jalr $25 // directly jump to func. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191591 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rewrite MipsTargetLowering::getAddr functions as template functions.Akira Hatanaka2013-09-271-74/+48
| | | | | | | | | No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191546 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r191350.Akira Hatanaka2013-09-251-83/+51
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191353 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Define getTargetNode as a template function.Akira Hatanaka2013-09-251-51/+83
| | | | | | | | | No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191350 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. ↵Daniel Sanders2013-09-241-0/+2
| | | | | | not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191306 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal ↵Daniel Sanders2013-09-241-0/+4
| | | | | | IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191304 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-241-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191302 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-241-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191301 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching ↵Daniel Sanders2013-09-241-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191299 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching max, maxi, min, mini from normal IR ↵Daniel Sanders2013-09-241-0/+4
| | | | | | (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191291 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching comparisons from normal IR (i.e. not ↵Daniel Sanders2013-09-241-0/+5
| | | | | | | | | | intrinsics) MIPS SelectionDAG changes: * Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191286 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching insert and copy from normal IR (i.e. ↵Daniel Sanders2013-09-231-0/+2
| | | | | | | | | | | | not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191199 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics)Daniel Sanders2013-09-231-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191195 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Implemented build_vector using ldi, fill, and custom ↵Daniel Sanders2013-09-231-0/+2
| | | | | | | | | | | | | | | | | | | SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191191 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix unused variables.Eli Friedman2013-09-101-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190448 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a problem with dual mips16/mips32 mode. When the underlying processorReed Kotler2013-08-301-4/+4
| | | | | | | | | | | | | | | has hard float, when you compile the mips32 code you have to make sure that it knows to compile any mips32 routines as hard float. I need to clean up the way mips16 hard float is specified but I need to first think through all the details. Mips16 always has a form of soft float, the difference being whether the underlying hardware has floating point. So it's not really necessary to pass the -soft-float to llvm since soft-float is always true for mips16 by virtue of the fact that it will not register floating point registers. By using this fact, I can simplify the way this is all handled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189690 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added bnz.df, bnz.v, bz.df, and bz.vDaniel Sanders2013-08-281-0/+4
| | | | | | | | | | | | | | | These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189478 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add support for calling convention CC_MipsO32_FP64, which is used ↵Akira Hatanaka2013-08-201-13/+29
| | | | | | | | | | | when the size of floating point registers is 64-bit. Test case will be added when support for mfhc1 and mthc1 is added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188847 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Resolve register classes dynamically using ptr_rc to reduce the number ofAkira Hatanaka2013-08-201-48/+12
| | | | | | | | | | load/store instructions defined. Previously, we were defining load/store instructions for each pointer size (32 and 64-bit), but now we need just one definition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188830 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename HIRegs and LORegs.Akira Hatanaka2013-08-141-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Properly parse registers that appear in inline-asm constraints.Akira Hatanaka2013-08-141-0/+81
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188336 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-061-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Implement llvm.trap intrinsic.Akira Hatanaka2013-07-261-0/+2
| | | | | | | | Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187244 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix FP conditional move instructions to have explicit FP condition codeAkira Hatanaka2013-07-261-1/+2
| | | | | | | | register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix FP branch instructions to have explicit FP condition code registerAkira Hatanaka2013-07-261-1/+2
| | | | | | | | operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-141-4/+4
| | | | | | size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-041-5/+0
| | | | | | These exception-related opcodes are not used any longer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185625 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r185595-185596 which broke buildbots.Jakob Stoklund Olesen2013-07-041-0/+5
| | | | | | | Revert "Simplify landing pad lowering." Revert "Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185600 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the EXCEPTIONADDR, EHSELECTION, and LSDAADDR ISD opcodes.Jakob Stoklund Olesen2013-07-031-5/+0
| | | | | | These exception-related opcodes are not used any longer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185596 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Reverse the order of source operands of shift and rotate instructions ↵Akira Hatanaka2013-07-011-7/+7
| | | | | | | | | | | that have three register operands. No intended functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185376 91177308-0d34-0410-b5e6-96231b3b80d8
* The getRegForInlineAsmConstraint function should only accept MVT value types.Chad Rosier2013-06-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184642 91177308-0d34-0410-b5e6-96231b3b80d8
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